diff --git a/.properties b/.properties index 9d29de5604..3eed56a6f7 100644 --- a/.properties +++ b/.properties @@ -1,6 +1,6 @@ id=com.silabs.sdk.stack.super -version=4.1.0 +version=4.1.1 label=Gecko SDK Suite description=Gecko SDK Suite @@ -15,7 +15,7 @@ buildNumber=0 # Look in these locations for extra properties # note that the single .properties input is a hack so that this will work while the stacks are updated -extendedProperties=app/bluetooth/find_my.properties app/amazon/app_amazon.properties app/mcu_example/app_mcu.properties .studio/efm32.properties app/bluetooth/esf.properties app/bluetooth/btmesh.properties app/flex/esf.properties extension/homekit/app/esf.properties app/common/app_common.properties platform/bootloader/esf.properties platform/halconfig/halconfig.properties platform/base/base.properties platform/micrium_os/micrium-krnx.properties protocol/openthread/esf.properties protocol/zigbee/esf.properties protocol/z-wave/esf.properties protocol/usb/usb.properties hardware/kit/kit.properties hardware/reference_design/ref_design.properties util/plugin/plugin.properties app/wisun/esf.properties util/third_party/tensorflow_extra/apack.properties extension/wiseconnect/esf.properties +extendedProperties=app/bluetooth/bluetooth_esl.properties app/bluetooth/find_my.properties app/amazon/app_amazon.properties app/mcu_example/app_mcu.properties .studio/efm32.properties app/bluetooth/esf.properties app/bluetooth/btmesh.properties app/flex/esf.properties extension/homekit/app/esf.properties app/common/app_common.properties platform/bootloader/esf.properties platform/halconfig/halconfig.properties platform/base/base.properties platform/micrium_os/micrium-krnx.properties protocol/openthread/esf.properties protocol/zigbee/esf.properties protocol/z-wave/esf.properties protocol/usb/usb.properties hardware/kit/kit.properties hardware/reference_design/ref_design.properties util/plugin/plugin.properties app/wisun/esf.properties util/third_party/tensorflow_extra/apack.properties extension/wiseconnect/esf.properties # ISD options baseDirectory=platform/base diff --git a/app/amazon/amazon_bluetooth_alpha_templates.xml b/app/amazon/amazon_bluetooth_alpha_templates.xml index 951c7ee6b9..4aebedc10f 100644 --- a/app/amazon/amazon_bluetooth_alpha_templates.xml +++ b/app/amazon/amazon_bluetooth_alpha_templates.xml @@ -6,8 +6,8 @@ - - + + @@ -21,8 +21,8 @@ - - + + @@ -36,9 +36,9 @@ - - - + + + diff --git a/app/amazon/amazon_platform_alpha_templates.xml b/app/amazon/amazon_platform_alpha_templates.xml index 7960371b5e..bcefc38dab 100644 --- a/app/amazon/amazon_platform_alpha_templates.xml +++ b/app/amazon/amazon_platform_alpha_templates.xml @@ -6,9 +6,9 @@ - - - + + + diff --git a/app/amazon/example/amazon_aws_demos/amazon_aws_soc_gatt_server.slcp b/app/amazon/example/amazon_aws_demos/amazon_aws_soc_gatt_server.slcp index 9429eab0dc..dbb0d7806d 100644 --- a/app/amazon/example/amazon_aws_demos/amazon_aws_soc_gatt_server.slcp +++ b/app/amazon/example/amazon_aws_demos/amazon_aws_soc_gatt_server.slcp @@ -75,7 +75,7 @@ configuration: tag: - hardware:device:ram:64 - hardware:rf:band:2400 - - hardware:device:sdid:200|205 + - hardware:device:sdid:200|205|215 ui_hints: highlight: config/aws_clientcredential.h diff --git a/app/amazon/example/amazon_aws_demos/amazon_aws_soc_mqtt_over_ble.slcp b/app/amazon/example/amazon_aws_demos/amazon_aws_soc_mqtt_over_ble.slcp index cf8c687e5a..bffb1388d7 100644 --- a/app/amazon/example/amazon_aws_demos/amazon_aws_soc_mqtt_over_ble.slcp +++ b/app/amazon/example/amazon_aws_demos/amazon_aws_soc_mqtt_over_ble.slcp @@ -75,7 +75,7 @@ configuration: tag: - hardware:device:ram:64 - hardware:rf:band:2400 - - hardware:device:sdid:200|205 + - hardware:device:sdid:200|205|215 ui_hints: highlight: config/aws_clientcredential.h diff --git a/app/amazon/example/amazon_aws_tests/amazon_aws_soc_bt_tests.slcp b/app/amazon/example/amazon_aws_tests/amazon_aws_soc_bt_tests.slcp index a72e522d61..3806cdac95 100644 --- a/app/amazon/example/amazon_aws_tests/amazon_aws_soc_bt_tests.slcp +++ b/app/amazon/example/amazon_aws_tests/amazon_aws_soc_bt_tests.slcp @@ -80,7 +80,7 @@ configuration: tag: - hardware:device:ram:64 - hardware:rf:band:2400 - - hardware:device:sdid:200|205 + - hardware:device:sdid:200|205|215 filter: - name: "Wireless Technology" diff --git a/app/bluetooth/bluetooth_production_demos.xml b/app/bluetooth/bluetooth_production_demos.xml index 025c6b1391..42dd8bc29d 100644 --- a/app/bluetooth/bluetooth_production_demos.xml +++ b/app/bluetooth/bluetooth_production_demos.xml @@ -1,1599 +1,1659 @@ + + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. + + + + + + + + + + + + Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. + + + + + + + + + + - - - - - - - - Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. + + + + + + + + - - - - - - - - Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. + + + + + + + + - - - - - - - - Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. + + + + + + + + - - - - - - - - Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. + + + + + + + + - - - - - - - - Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. + + + + + + + + - - - - - - - - Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. + + + + + + + + - - - - - - - - Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. + + + + + + + + - - - - - - - - Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. + + + + + + + + - - - - - - - - Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. + + + + + + + + - - - - - - - - Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. + + + + + + + + - - - - - - - - Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. + + + + + + + + - - - - - - - - Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. + + + + + + + + - - - - - - - - Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. + + + + + + + + - - - - - - - - Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. + + + + + + + + - - - - - - - - Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. + + + + + + + + - - - - - - - - Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. + + + + + + + + - - - - - - - - Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. + + + + + + + + - - - - - - - - Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. + + + + + + + + - - - - - - - - Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. + + + + + + + + - - - - - - - - Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. + + + + + + + + - - - - - - - - Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. + + + + + + + + - - - - - - - - Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. + + + + + + + + - - - - - - - - Network Co-Processor (NCP) target application. Runs the Bluetooth stack dynamically and provides access to it via Bluetooth API (BGAPI) using UART connection. NCP mode makes it possible to run your application on a host controller or PC. + + + + + + + + - - - - - - - - The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. + + + + + + + + + + + The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. + + + + + + + + + - - - - - - - - The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - The classic blinky example using Bluetooth communication. Demonstrates a simple two-way data exchange over GATT. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Demonstrates the features of the EFR32xG24 Dev Kit Board. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. + + + + + + + + - - - - - - - - Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. + + + + + + + + - - - - - - - - Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. + + + + + + + + - - - - - - - - Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. + + + + + + + + - - - - - - - - Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. + + + + + + + + - - - - - - - - Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. + + + + + + + + - - - - - - - - Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. + + + + + + + + - - - - - - - - Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. + + + + + + + + - - - - - - - - Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. + + + + + + + + - - - - - - - - Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. + + + + + + + + - - - - - - - - Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the mock relative humidity and temperature sensor. + + + + + + + + - - - - - - - - Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. + + + + + + + + - - - - - - - - Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. + + + + + + + + - - - - - - - - Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. + + + + + + + + - - - - - - - - Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. + + + + + + + + - - - - - - - - Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. + + + + + + + + - - - - - - - - Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. + + + + + + + + - - - - - - - - Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. + + + + + + + + - - - - - - - - Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. + + + + + + + + - - - - - - - - Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. + + + + + + + + - - - - - - - - Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. + + + + + + + + - - - - - - - - Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. + + + + + + + + - - - - - - - - Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. + + + + + + + + - - - - - - - - Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. + + + + + + + + - - - - - - - - Implements a GATT Server with the Health Thermometer Profile, which enables a Client device to connect and get temperature data. Temperature is read from the Si7021 digital relative humidity and temperature sensor of the WSTK or of the Thunderboard. + + + + + + + + - - - - - - - - This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. + + + + + + + + - - - - - - - - This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. + + + + + + + + - - - - - - - - This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. + + + + + + + + - - - - - - - - This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. + + + + + + + + - - - - - - - - This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. + + + + + + + + - - - - - - - - This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. + + + + + + + + - - - - - - - - This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. + + + + + + + + - - - - - - - - This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. + + + + + + + + - - - - - - - - This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. + + + + + + + + - - - - - - - - This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. + + + + + + + + - - - - - - - - This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. + + + + + + + + - - - - - - - - This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. + + + + + + + + - - - - - - - - This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. + + + + + + + + - - - - - - - - This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. + + + + + + + + - - - - - - - - This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. + + + + + + + + + + + This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. + + + + + + + + + - - - - - - - - This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. + + + + + + + + - - - - - - - - This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. + + + + + + + + - - - - - - - - This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. + + + + + + + + - - - - - - - - This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. + + + + + + + + - - - - - - - - This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. + + + + + + + + - - - - - - - - This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. + + + + + + + + - - - - - - - - This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. + + + + + + + + - - - - - - - - This example tests the throughput capabilities of the device and can be used to measure throughput between 2 *EFR32* devices, as well as between a device and a smartphone using EFR Connect mobile app, through the Throughput demo tile. + + + + + + + + - - - - - - - - Demonstrates the features of the Thunderboard EFR32BG22 Kit. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Demonstrates the features of the Thunderboard EFR32BG22 Kit. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Demonstrates the features of the Thunderboard Sense 2 Kit. This can be tested with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Voice over Bluetooth Low Energy sample application. It is supported by Thunderboard Sense 2 and Thunderboard EFR32BG22 boards and demonstrates how to send voice data over GATT, which is acquired from the on-board microphones. + + + + + + + + - - - - - - - - Voice over Bluetooth Low Energy sample application. It is supported by Thunderboard Sense 2 and Thunderboard EFR32BG22 boards and demonstrates how to send voice data over GATT, which is acquired from the on-board microphones. + + + + + + + + - - - - - - - - Voice over Bluetooth Low Energy sample application. It is supported by Thunderboard Sense 2 and Thunderboard EFR32BG22 boards and demonstrates how to send voice data over GATT, which is acquired from the on-board microphones. + + + + + + + + - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacons to smartphones. This example can be tested together with the EFR Connect mobile app. + + + + + + + + - - - - - - - - Network Co-Processor (NCP) target application extended with CTE Receiver support. It enables Angle of Arrival (AoA) calculation. Use this application with Direction Finding host examples. + + + + + + + + - - - - - - - - Network Co-Processor (NCP) target application extended with CTE Receiver support. It enables Angle of Arrival (AoA) calculation. Use this application with Direction Finding host examples. + + + + + + + + + + + This sample app demonstrates a CTE (Constant Tone Extension) transmitter that can be used as an asset tag in a Direction Finding setup estimating Angle of Arrival (AoA). + + + + + + + + + - - - - - - - - This sample app demonstrates a CTE (Constant Tone Extension) transmitter that can be used as an asset tag in a Direction Finding setup estimating Angle of Arrival (AoA). + + + + + + + + - - - - - - - - This sample app demonstrates a CTE (Constant Tone Extension) transmitter that can be used as an asset tag in a Direction Finding setup estimating Angle of Arrival (AoA). + + + + + + + + - - - - - - - - This is a Dynamic Multiprotocol reference application demonstrating a light bulb that can be switched both via Bluetooth and via a Proprietary protocol. Can be tested with the EFR Connect mobile app and Flex (RAIL) Switch sample app. + + + + + + + + diff --git a/app/bluetooth/bluetooth_production_templates.xml b/app/bluetooth/bluetooth_production_templates.xml index 1dcf3b31c1..2411aca05c 100644 --- a/app/bluetooth/bluetooth_production_templates.xml +++ b/app/bluetooth/bluetooth_production_templates.xml @@ -7,8 +7,8 @@ - - + + @@ -21,9 +21,9 @@ - - - + + + @@ -36,9 +36,9 @@ - + - + @@ -53,7 +53,7 @@ - + @@ -66,9 +66,9 @@ - + - + @@ -81,9 +81,9 @@ - + - + @@ -96,9 +96,9 @@ - + - + @@ -111,9 +111,9 @@ - + - + @@ -126,9 +126,9 @@ - + - + @@ -143,7 +143,7 @@ - + @@ -158,7 +158,7 @@ - + @@ -173,7 +173,7 @@ - + @@ -188,7 +188,7 @@ - + @@ -201,9 +201,9 @@ - + - + @@ -216,9 +216,9 @@ - + - + @@ -233,7 +233,7 @@ - + @@ -248,7 +248,7 @@ - + @@ -263,7 +263,7 @@ - + @@ -276,9 +276,9 @@ - + - + @@ -293,7 +293,7 @@ - + @@ -306,9 +306,9 @@ - - - + + + @@ -321,9 +321,9 @@ - - - + + + @@ -336,9 +336,9 @@ - + - + @@ -351,9 +351,9 @@ - + - + @@ -366,9 +366,9 @@ - + - + @@ -383,7 +383,7 @@ - + @@ -396,9 +396,9 @@ - + - + @@ -413,7 +413,7 @@ - + @@ -428,7 +428,7 @@ - + @@ -441,9 +441,9 @@ - + - + @@ -458,7 +458,7 @@ - + @@ -471,9 +471,9 @@ - + - + @@ -486,9 +486,9 @@ - + - + @@ -501,9 +501,9 @@ - + - + @@ -516,9 +516,9 @@ - + - + @@ -531,9 +531,9 @@ - + - + @@ -548,7 +548,7 @@ - + @@ -563,7 +563,7 @@ - + @@ -578,7 +578,7 @@ - + @@ -593,7 +593,7 @@ - + @@ -608,7 +608,7 @@ - + @@ -623,7 +623,7 @@ - + diff --git a/app/bluetooth/btmesh.properties b/app/bluetooth/btmesh.properties index f851d36fd6..512cb7500c 100644 --- a/app/bluetooth/btmesh.properties +++ b/app/bluetooth/btmesh.properties @@ -2,8 +2,8 @@ id=com.silabs.stack.btMesh label=Bluetooth Mesh SDK description=Bluetooth Mesh Software Development Kit -version=3.0.0.0 -prop.subLabel=Bluetooth\\ Mesh\\ 3.0.0 +version=3.0.1.0 +prop.subLabel=Bluetooth\\ Mesh\\ 3.0.1 # Default compatibility of the BT Mesh SDK (This is needed for the documentation only) prop.boardCompatibility=.* diff --git a/app/bluetooth/btmesh_internal_demos.xml b/app/bluetooth/btmesh_internal_demos.xml index b4e147e970..43cda56d0a 100644 --- a/app/bluetooth/btmesh_internal_demos.xml +++ b/app/bluetooth/btmesh_internal_demos.xml @@ -1,159 +1,159 @@ - - - - - - - - Friend example for IOP test. This node acts as a friend for the low power node and caches messages sent to it when the low power node is sleeping. + + + + + + + + - - - - - - - - Friend example for IOP test. This node acts as a friend for the low power node and caches messages sent to it when the low power node is sleeping. + + + + + + + + - - - - - - - - Friend example for IOP test. This node acts as a friend for the low power node and caches messages sent to it when the low power node is sleeping. + + + + + + + + - - - - - - - - Low power node example for IOP test. This node acts as a typical low power device and sleeps most of the time. It needs a friend node to cache messages and forward them when polled. + + + + + + + + - - - - - - - - Low power node example for IOP test. This node acts as a typical low power device and sleeps most of the time. It needs a friend node to cache messages and forward them when polled. + + + + + + + + - - - - - - - - Low power node example for IOP test. This node acts as a typical low power device and sleeps most of the time. It needs a friend node to cache messages and forward them when polled. + + + + + + + + - - - - - - - - Low power node example for IOP test. This node acts as a typical low power device and sleeps most of the time. It needs a friend node to cache messages and forward them when polled. + + + + + + + + - - - - - - - - Proxy example for IOP test. This node forwards/relays messages between GATT and advertising bearers in the network. + + + + + + + + - - - - - - - - Proxy example for IOP test. This node forwards/relays messages between GATT and advertising bearers in the network. + + + + + + + + - - - - - - - - Proxy example for IOP test. This node forwards/relays messages between GATT and advertising bearers in the network. + + + + + + + + - - - - - - - - Relay example for IOP test. This node acts as a relay, i.e. if a node is out of range for another node, it relays messages between the two, provided the relay node is in range for both. + + + + + + + + - - - - - - - - Relay example for IOP test. This node acts as a relay, i.e. if a node is out of range for another node, it relays messages between the two, provided the relay node is in range for both. + + + + + + + + - - - - - - - - Relay example for IOP test. This node acts as a relay, i.e. if a node is out of range for another node, it relays messages between the two, provided the relay node is in range for both. + + + + + + + + diff --git a/app/bluetooth/btmesh_production_demos.xml b/app/bluetooth/btmesh_production_demos.xml index 65b240a015..b0033b0baa 100644 --- a/app/bluetooth/btmesh_production_demos.xml +++ b/app/bluetooth/btmesh_production_demos.xml @@ -1,1803 +1,1803 @@ - - - - - - - - An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. + + + + + + + + - - - - - - - - An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. + + + + + + + + - - - - - - - - Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. + + + + + + + + - - - - - - - - An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. + + + + + + + + - - - - - - - - An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. + + + + + + + + - - - - - - - - An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. + + + + + + + + - - - - - - - - An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. + + + + + + + + - - - - - - - - Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. + + + + + + + + - - - - - - - - Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. + + + + + + + + - - - - - - - - Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. + + + + + + + + - - - - - - - - Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. + + + + + + + + - - - - - - - - Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. + + + + + + + + - - - - - - - - An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. + + + + + + + + - - - - - - - - An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. + + + + + + + + - - - - - - - - An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. + + + + + + + + - - - - - - - - An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. + + + + + + + + - - - - - - - - An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. + + + + + + + + - - - - - - - - An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. + + + + + + + + - - - - - - - - An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. + + + + + + + + - - - - - - - - An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. + + + + + + + + - - - - - - - - An NCP Target C application that makes it possible for the NCP Host Controller to access the Bluetooth Mesh stack via UART. It provides access to the host layer via BGAPI and not to the link layer via HCI. + + + + + + + + - - - - - - - - Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. + + + + + + + + - - - - - - - - Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. + + + + + + + + - - - - - - - - Demonstrates the bare minimum needed for an NCP Target C application. This example is recommended for EFR32xG22, which has limited RAM and flash, and therefore some of the stack classes are disabled by default. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the Thunderboard Sense 2 can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, hue, and saturation can be set. The example also tries to establish friendship as a Friend node. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the mainboard can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the Thunderboard Sense 2 board can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. + + + + + + + + - - - - - - - - An out-of-the-box software demo where the LEDs of the WSTK can be switched on and off, and their lighting intensity, color temperature, and delta UV can be set. + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Client Model. It collects and displays sensor measurement data from remote device(s) (e.g., btmesh_soc_sensor_server). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature, people count, and illuminance, and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and people count, and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and people count, and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature, people count, and illuminance, and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and people count, and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and people count, and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and people count, and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and people count, and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and people count, and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and people count, and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature, people count, and illuminance, and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature, people count, and illuminance, and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and people count, and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and people count, and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and people count, and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and people count, and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and people count, and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and people count, and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and people count, and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and people count, and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and people count, and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and people count, and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and people count, and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). + + + + + + + + - - - - - - - - This example demonstrates the Bluetooth Mesh Sensor Server Model and Sensor Setup Server Model. It measures temperature and people count, and sends the measurement data to a remote device (e.g., btmesh_soc_sensor_client). + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. It is optimized for low current consumption with disabled CLI, logging, and LCD.Push Button presses can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. It is optimized for low current consumption with disabled CLI, logging, and LCD.Push Button presses can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - A Software Demo where the device acts as a switch. It is optimized for low current consumption with disabled CLI, logging, and LCD. Button presses (only PB0 is functional) can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. It is optimized for low current consumption with disabled CLI, logging, and LCD.Push Button presses can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. It is optimized for low current consumption with disabled CLI, logging, and LCD.Push Button presses can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. It is optimized for low current consumption with disabled CLI, logging, and LCD.Push Button presses can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. It is optimized for low current consumption with disabled CLI, logging, and LCD.Push Button presses can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. It is optimized for low current consumption with disabled CLI, logging, and LCD.Push Button presses can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - A Software Demo where the device acts as a switch. It is optimized for low current consumption with disabled CLI, logging, and LCD. Button presses (only PB0 is functional) can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - A Software Demo where the device acts as a switch. It is optimized for low current consumption with disabled CLI, logging, and LCD. Button presses (only PB0 is functional) can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - A Software Demo where the device acts as a switch. It is optimized for low current consumption with disabled CLI, logging, and LCD. Button presses (only PB0 is functional) can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - A Software Demo where the device acts as a switch. It is optimized for low current consumption with disabled CLI, logging, and LCD. Button presses (only PB0 is functional) can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. It is optimized for low current consumption with disabled CLI, logging, and LCD.Push Button presses can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. It is optimized for low current consumption with disabled CLI, logging, and LCD.Push Button presses can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. It is optimized for low current consumption with disabled CLI, logging, and LCD.Push Button presses can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. It is optimized for low current consumption with disabled CLI, logging, and LCD.Push Button presses can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. It is optimized for low current consumption with disabled CLI, logging, and LCD.Push Button presses can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. It is optimized for low current consumption with disabled CLI, logging, and LCD.Push Button presses can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. It is optimized for low current consumption with disabled CLI, logging, and LCD.Push Button presses can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. It is optimized for low current consumption with disabled CLI, logging, and LCD.Push Button presses can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. It is optimized for low current consumption with disabled CLI, logging, and LCD.Push Button presses can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. It is optimized for low current consumption with disabled CLI, logging, and LCD.Push Button presses can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. It is optimized for low current consumption with disabled CLI, logging, and LCD.Push Button presses can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - A Software Demo where the device acts as a switch. It is optimized for low current consumption with disabled CLI, logging, and LCD. Button presses (only PB0 is functional) can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. Push Button presses or CLI commands can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. Push Button presses or CLI commands can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. Push Button presses (only PB0 is functional) or CLI commands can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. Push Button presses or CLI commands can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. Push Button presses or CLI commands can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. Push Button presses or CLI commands can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. Push Button presses or CLI commands can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. Push Button presses or CLI commands can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. Push Button presses (only PB0 is functional) or CLI commands can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. Push Button presses (only PB0 is functional) or CLI commands can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. Push Button presses (only PB0 is functional) or CLI commands can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. Push Button presses (only PB0 is functional) or CLI commands can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. Push Button presses or CLI commands can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. Push Button presses or CLI commands can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. Push Button presses or CLI commands can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. Push Button presses or CLI commands can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. Push Button presses or CLI commands can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. Push Button presses or CLI commands can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. Push Button presses or CLI commands can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. Push Button presses or CLI commands can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. Push Button presses or CLI commands can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. Push Button presses or CLI commands can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. Push Button presses or CLI commands can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + - - - - - - - - An out-of-the-box Software Demo where the device acts as a switch. Push Button presses (only PB0 is functional) or CLI commands can control the state, lightness, and color temperature of the LEDs and scenes on a remote device. + + + + + + + + diff --git a/app/bluetooth/common/btmesh_dcd_configuration/dcd_config.btmeshconf b/app/bluetooth/common/btmesh_dcd_configuration/dcd_config.btmeshconf index 843b1d37aa..02db9b46e5 100644 --- a/app/bluetooth/common/btmesh_dcd_configuration/dcd_config.btmeshconf +++ b/app/bluetooth/common/btmesh_dcd_configuration/dcd_config.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0xffff", - "vid": "0x0300", + "vid": "0x0301", "elements": [ { "name": "Main", diff --git a/app/bluetooth/common/cbap/config/sl_bt_cbap_root_cert.h b/app/bluetooth/common/cbap/config/sl_bt_cbap_root_cert.h index 453038a6c3..67b6761cbc 100644 --- a/app/bluetooth/common/cbap/config/sl_bt_cbap_root_cert.h +++ b/app/bluetooth/common/cbap/config/sl_bt_cbap_root_cert.h @@ -1,7 +1,6 @@ /***************************************************************************//** * @file * @brief Root certificate definition in PEM format. - * Autogenerated file, do not edit. ******************************************************************************* * # License * Copyright 2022 Silicon Laboratories Inc. www.silabs.com diff --git a/app/bluetooth/common/cbap/sl_bt_cbap.c b/app/bluetooth/common/cbap/sl_bt_cbap.c index a3dda776d8..c478ffa3e1 100644 --- a/app/bluetooth/common/cbap/sl_bt_cbap.c +++ b/app/bluetooth/common/cbap/sl_bt_cbap.c @@ -52,15 +52,20 @@ // Defines #if defined(SL_CATALOG_APP_LOG_PRESENT) && SL_BT_CBAP_LOG -#define app_log_cbap_info(...) app_log_info(__VA_ARGS__) -#define app_log_cbap_debug(...) app_log_debug(__VA_ARGS__) -#define app_log_cbap_hexdump(p_data, len) app_log_hexdump_debug(p_data, len) +#define sl_bt_cbap_log_debug(...) app_log_debug(__VA_ARGS__) +#define sl_bt_cbap_log_info(...) app_log_info(__VA_ARGS__) +#define sl_bt_cbap_log_error(...) app_log_error(__VA_ARGS__) +#define sl_bt_cbap_log_hexdump(p_data, len) app_log_hexdump_debug(p_data, len) #else -#define app_log_cbap_info(...) -#define app_log_cbap_debug(...) -#define app_log_cbap_hexdump(p_data, len) +#define sl_bt_cbap_log_debug(...) +#define sl_bt_cbap_log_info(...) +#define sl_bt_cbap_log_error(...) +#define sl_bt_cbap_log_hexdump(p_data, len) #endif +#define IS_PERIPHERAL_IN_PROGRESS (cbap_peripheral_state > 0 && cbap_peripheral_state < SL_BT_CBAP_PERIPHERAL_STATE_NUM - 1) +#define IS_CENTRAL_IN_PROGRESS (cbap_central_state > 0 && cbap_central_state < SL_BT_CBAP_CENTRAL_STATE_NUM - 1) + #define UUID_16_LEN 2 #define UUID_128_LEN 16 #define HANDLE_NOT_INITIALIZED 0 @@ -107,8 +112,8 @@ typedef enum { // Device role static sl_bt_cbap_role_t role; -// Connection handle -static uint8_t connection; +// Handle of the active connection. +static uint8_t connection = SL_BT_INVALID_CONNECTION_HANDLE; // Root certificate in PEM format. const char *root_certificate_pem = SL_BT_CBAP_ROOT_CERT; @@ -184,6 +189,9 @@ static void on_event_peripheral(sl_bt_msg_t *evt); // Peripheral device bluetooth event handler. static void on_event_central(sl_bt_msg_t *evt); +// Reset CBAP process states, flags and timers. +static void cbap_reset(void); + // Search for a Service UUID in scan report. static bool find_service_in_advertisement(const uint8_t *scan_data, uint8_t scan_data_len, @@ -206,32 +214,23 @@ void sl_bt_cbap_init(void) device_certificate_der, &device_certificate_der_len); app_assert_status(sc); - app_log_cbap_info("Device certificate verified." APP_LOG_NL); + sl_bt_cbap_log_info("Device certificate verified." APP_LOG_NL); + + cbap_reset(); } // Start CBAP procedure. -sl_status_t sl_bt_cbap_start(sl_bt_cbap_role_t cbap_role, uint8_t connection_handle) +sl_status_t sl_bt_cbap_start(sl_bt_cbap_role_t cbap_role, + uint8_t connection_handle) { sl_status_t sc; - if (((cbap_central_state != 0) - && (cbap_central_state != SL_BT_CBAP_CENTRAL_STATE_NUM - 1)) - || ((cbap_peripheral_state != 0) - && (cbap_peripheral_state != SL_BT_CBAP_PERIPHERAL_STATE_NUM - 1))) { + if (IS_PERIPHERAL_IN_PROGRESS || IS_CENTRAL_IN_PROGRESS) { return SL_STATUS_IN_PROGRESS; } role = cbap_role; connection = connection_handle; - // Reset variables - remote_cert_arrived = false; - device_cert_sent = false; - remote_certificate_der_len = 0; - dev_cert_sending_progression = 0; - cbap_central_state = SL_BT_CBAP_CENTRAL_SCANNING; - char_state = (characteristics_t)0; - cbap_peripheral_state = SL_BT_CBAP_PERIPHERAL_IDLE; - if (role == SL_BT_CBAP_ROLE_CENTRAL) { // Discover CBAP service on the peripheral device sc = sl_bt_gatt_discover_primary_services_by_uuid(connection, @@ -296,21 +295,21 @@ static void on_event_peripheral(sl_bt_msg_t *evt) break; } - app_log_cbap_debug("Security mode: %i" APP_LOG_NL, - evt->data.evt_connection_parameters.security_mode); + sl_bt_cbap_log_debug("Security mode: %i" APP_LOG_NL, + evt->data.evt_connection_parameters.security_mode); if (evt->data.evt_connection_parameters.security_mode > sl_bt_connection_mode1_level1 && cbap_peripheral_state != SL_BT_CBAP_PERIPHERAL_CENTRAL_OOB_OK) { - app_log_cbap_info("The central device increased the security level with " \ - "no CBAP. Disconnecting." APP_LOG_NL); - sc = sl_bt_connection_close(connection); - app_assert_status(sc); + sl_bt_cbap_log_error("The central device increased the security level with " \ + "no CBAP. Disconnecting." APP_LOG_NL); + sl_bt_on_cbap_error(); + cbap_reset(); break; } if (evt->data.evt_connection_parameters.security_mode == sl_bt_connection_mode1_level4) { cbap_peripheral_state = SL_BT_CBAP_PERIPHERAL_DONE; sl_bt_cbap_peripheral_on_event(cbap_peripheral_state); - set_timeout(false); // Last state. Stop timer. + cbap_reset(); } break; @@ -332,7 +331,7 @@ static void on_event_peripheral(sl_bt_msg_t *evt) sc = SL_STATUS_OK; if (evt->data.evt_gatt_server_user_write_request.value.data[0] == 0) { // Last packet of the remote cert arrived - app_log_cbap_info("Getting certificate from central." APP_LOG_NL); + sl_bt_cbap_log_info("Getting certificate from central." APP_LOG_NL); remote_cert_arrived = true; sc = sl_bt_cbap_lib_process_remote_cert(remote_certificate_der, remote_certificate_der_len); @@ -343,10 +342,10 @@ static void on_event_peripheral(sl_bt_msg_t *evt) sl_bt_cbap_peripheral_on_event(cbap_peripheral_state); set_timeout(true); } else { - app_log_cbap_info("Remote certificate verification failed. " \ - "Disconnecting." APP_LOG_NL); - sc = sl_bt_connection_close(connection); - app_assert_status(sc); + sl_bt_cbap_log_error("Remote certificate verification failed. " \ + "Disconnecting." APP_LOG_NL); + sl_bt_on_cbap_error(); + cbap_reset(); break; } } @@ -363,7 +362,7 @@ static void on_event_peripheral(sl_bt_msg_t *evt) } // Receiving OOB data from central device else if (evt->data.evt_gatt_server_user_write_request.characteristic == gattdb_central_oob ) { - app_log_cbap_info("Getting OOB data from central." APP_LOG_NL); + sl_bt_cbap_log_info("Getting OOB data from central." APP_LOG_NL); aes_key_128 remote_random; aes_key_128 remote_confirm; uint8_t remote_oob_signature[OOB_SIGNATURE_LEN]; @@ -382,21 +381,24 @@ static void on_event_peripheral(sl_bt_msg_t *evt) SL_STATUS_OK); app_assert_status(sc); - app_log_cbap_debug("Remote OOB data:" APP_LOG_NL); - app_log_cbap_hexdump(&remote_random, sizeof(aes_key_128)); - app_log_cbap_debug(APP_LOG_NL); - app_log_cbap_hexdump(&remote_confirm, sizeof(aes_key_128)); - app_log_cbap_debug(APP_LOG_NL); - app_log_cbap_debug("Remote OOB signature:" APP_LOG_NL); - app_log_cbap_hexdump(&remote_oob_signature, OOB_SIGNATURE_LEN); - app_log_cbap_debug(APP_LOG_NL); + sl_bt_cbap_log_debug("Remote OOB data:" APP_LOG_NL); + sl_bt_cbap_log_hexdump(&remote_random, sizeof(aes_key_128)); + sl_bt_cbap_log_debug(APP_LOG_NL); + sl_bt_cbap_log_hexdump(&remote_confirm, sizeof(aes_key_128)); + sl_bt_cbap_log_debug(APP_LOG_NL); + sl_bt_cbap_log_debug("Remote OOB signature:" APP_LOG_NL); + sl_bt_cbap_log_hexdump(&remote_oob_signature, OOB_SIGNATURE_LEN); + sl_bt_cbap_log_debug(APP_LOG_NL); sc = sl_bt_cbap_lib_verify_remote_oob_data(remote_random.data, remote_confirm.data, remote_oob_signature); app_assert_status(sc); + sl_bt_cbap_log_info("Remote OOB data verified." APP_LOG_NL); sc = sl_bt_sm_set_remote_oob(1, remote_random, remote_confirm); app_assert_status(sc); + sc = sl_bt_cbap_destroy_key(); + app_assert_status(sc); app_assert(cbap_peripheral_state == SL_BT_CBAP_PERIPHERAL_CENTRAL_CERT_OK, "Unexpected peripheral state."); @@ -413,18 +415,17 @@ static void on_event_peripheral(sl_bt_msg_t *evt) if (gattdb_peripheral_cert == evt->data.evt_gatt_server_characteristic_status.characteristic) { if (sl_bt_gatt_server_client_config == (sl_bt_gatt_server_characteristic_status_flag_t)evt->data.evt_gatt_server_characteristic_status.status_flags) { - if (sl_bt_gatt_indication == (sl_bt_gatt_client_config_flag_t)evt->data.evt_gatt_server_characteristic_status.client_config_flags) { - if (device_cert_sent == false) { - uint8_t buff[CERT_IND_CHUNK_LEN + 1]; - buff[0] = 1; - memcpy(&buff[1], device_certificate_der, CERT_IND_CHUNK_LEN); - sc = sl_bt_gatt_server_send_indication(connection, - gattdb_peripheral_cert, - CERT_IND_CHUNK_LEN + 1, - buff); - app_assert_status(sc); - dev_cert_sending_progression += CERT_IND_CHUNK_LEN; - } + if (sl_bt_gatt_indication == (sl_bt_gatt_client_config_flag_t)evt->data.evt_gatt_server_characteristic_status.client_config_flags + && device_cert_sent == false) { + uint8_t buff[CERT_IND_CHUNK_LEN + 1]; + buff[0] = 1; + memcpy(&buff[1], device_certificate_der, CERT_IND_CHUNK_LEN); + sc = sl_bt_gatt_server_send_indication(connection, + gattdb_peripheral_cert, + CERT_IND_CHUNK_LEN + 1, + buff); + app_assert_status(sc); + dev_cert_sending_progression += CERT_IND_CHUNK_LEN; } } // Sending Peripheral certificate to Central device @@ -454,38 +455,37 @@ static void on_event_peripheral(sl_bt_msg_t *evt) } // Sending Peripheral OOB data to Central device else if (gattdb_peripheral_oob == evt->data.evt_gatt_server_characteristic_status.characteristic ) { - if (sl_bt_gatt_server_client_config == (sl_bt_gatt_server_characteristic_status_flag_t)evt->data.evt_gatt_server_characteristic_status.status_flags) { - if (sl_bt_gatt_indication == (sl_bt_gatt_client_config_flag_t)evt->data.evt_gatt_server_characteristic_status.client_config_flags) { - aes_key_128 device_random; - aes_key_128 device_confirm; - // Generate device oob data and send over GATT - sc = sl_bt_sm_set_oob(1, &device_random, &device_confirm); - app_assert_status(sc); + if (sl_bt_gatt_server_client_config == (sl_bt_gatt_server_characteristic_status_flag_t)evt->data.evt_gatt_server_characteristic_status.status_flags + && sl_bt_gatt_indication == (sl_bt_gatt_client_config_flag_t)evt->data.evt_gatt_server_characteristic_status.client_config_flags) { + aes_key_128 device_random; + aes_key_128 device_confirm; + // Generate device oob data and send over GATT + sc = sl_bt_sm_set_oob(1, &device_random, &device_confirm); + app_assert_status(sc); - app_log_cbap_debug("Device OOB Data:" APP_LOG_NL); - app_log_cbap_hexdump(&device_random, OOB_RANDOM_LEN); - app_log_cbap_debug(APP_LOG_NL); - app_log_cbap_hexdump(&device_confirm, OOB_RANDOM_LEN); - app_log_cbap_debug(APP_LOG_NL); + sl_bt_cbap_log_debug("Device OOB Data:" APP_LOG_NL); + sl_bt_cbap_log_hexdump(&device_random, OOB_RANDOM_LEN); + sl_bt_cbap_log_debug(APP_LOG_NL); + sl_bt_cbap_log_hexdump(&device_confirm, OOB_RANDOM_LEN); + sl_bt_cbap_log_debug(APP_LOG_NL); - sc = sl_bt_cbap_lib_sign_device_oob_data(device_random.data, - device_confirm.data, - signed_device_oob_data, - &signed_device_oob_len); - app_assert_status(sc); + sc = sl_bt_cbap_lib_sign_device_oob_data(device_random.data, + device_confirm.data, + signed_device_oob_data, + &signed_device_oob_len); + app_assert_status(sc); - app_log_cbap_debug("Device OOB Signature:" APP_LOG_NL); - app_log_cbap_hexdump(&signed_device_oob_data[OOB_DATA_LEN], + sl_bt_cbap_log_debug("Device OOB Signature:" APP_LOG_NL); + sl_bt_cbap_log_hexdump(&signed_device_oob_data[OOB_DATA_LEN], OOB_SIGNATURE_LEN); - app_log_cbap_debug(APP_LOG_NL); + sl_bt_cbap_log_debug(APP_LOG_NL); - sc = sl_bt_gatt_server_send_indication(connection, - gattdb_peripheral_oob, - signed_device_oob_len, - signed_device_oob_data); - app_assert_status(sc); - } + sc = sl_bt_gatt_server_send_indication(connection, + gattdb_peripheral_oob, + signed_device_oob_len, + signed_device_oob_data); + app_assert_status(sc); } } break; @@ -507,20 +507,20 @@ static void on_event_central(sl_bt_msg_t *evt) break; } - app_log_cbap_debug("Security mode: %i" APP_LOG_NL, evt->data.evt_connection_parameters.security_mode); + sl_bt_cbap_log_debug("Security mode: %i" APP_LOG_NL, evt->data.evt_connection_parameters.security_mode); if (evt->data.evt_connection_parameters.security_mode > sl_bt_connection_mode1_level1 && cbap_central_state != SL_BT_CBAP_CENTRAL_INCREASE_SECURITY) { - app_log_cbap_info("Security level has been increased with no CBAP. " \ - "Disconnecting." APP_LOG_NL); - sc = sl_bt_connection_close(connection); - app_assert_status(sc); + sl_bt_cbap_log_error("Security level has been increased with no CBAP. " \ + "Disconnecting." APP_LOG_NL); + sl_bt_on_cbap_error(); + cbap_reset(); break; } if (evt->data.evt_connection_parameters.security_mode == sl_bt_connection_mode1_level4) { cbap_central_state = SL_BT_CBAP_CENTRAL_DONE; sl_bt_cbap_central_on_event(cbap_central_state); - set_timeout(false); // Last state. Stop timer. + cbap_reset(); } break; @@ -534,7 +534,7 @@ static void on_event_central(sl_bt_msg_t *evt) if (cbap_service_handle == HANDLE_NOT_INITIALIZED) { // Save service handle for future reference cbap_service_handle = evt->data.evt_gatt_service.service; - app_log_cbap_debug("Service handle found: %i" APP_LOG_NL, cbap_service_handle); + sl_bt_cbap_log_debug("Service handle found: %i" APP_LOG_NL, cbap_service_handle); } break; @@ -548,8 +548,8 @@ static void on_event_central(sl_bt_msg_t *evt) if (cbap_characteristics[char_state].handle == HANDLE_NOT_INITIALIZED) { // Save characteristic handle for future reference cbap_characteristics[char_state].handle = evt->data.evt_gatt_characteristic.characteristic; - app_log_cbap_debug("Characteristic handle found: %i" APP_LOG_NL, - cbap_characteristics[char_state].handle); + sl_bt_cbap_log_debug("Characteristic handle found: %i" APP_LOG_NL, + cbap_characteristics[char_state].handle); } break; @@ -563,10 +563,10 @@ static void on_event_central(sl_bt_msg_t *evt) // Check result if (evt->data.evt_gatt_procedure_completed.result != 0) { - app_log_cbap_info("GATT procedure failed [E:%i]. Disconnecting." APP_LOG_NL, - evt->data.evt_gatt_procedure_completed.result); - sc = sl_bt_connection_close(connection); - app_assert_status(sc); + sl_bt_cbap_log_error("GATT procedure failed [E:%i]. Disconnecting." APP_LOG_NL, + evt->data.evt_gatt_procedure_completed.result); + sl_bt_on_cbap_error(); + cbap_reset(); break; } @@ -646,11 +646,11 @@ static void on_event_central(sl_bt_msg_t *evt) sc = sl_bt_sm_set_oob(1, &device_random, &device_confirm); app_assert_status(sc); - app_log_cbap_debug("Device OOB Data:" APP_LOG_NL); - app_log_cbap_hexdump(&device_random, OOB_RANDOM_LEN); - app_log_cbap_debug(APP_LOG_NL); - app_log_cbap_hexdump(&device_confirm, OOB_RANDOM_LEN); - app_log_cbap_debug(APP_LOG_NL); + sl_bt_cbap_log_debug("Device OOB Data:" APP_LOG_NL); + sl_bt_cbap_log_hexdump(&device_random, OOB_RANDOM_LEN); + sl_bt_cbap_log_debug(APP_LOG_NL); + sl_bt_cbap_log_hexdump(&device_confirm, OOB_RANDOM_LEN); + sl_bt_cbap_log_debug(APP_LOG_NL); sc = sl_bt_cbap_lib_sign_device_oob_data(device_random.data, device_confirm.data, @@ -658,10 +658,10 @@ static void on_event_central(sl_bt_msg_t *evt) &signed_device_oob_len); app_assert_status(sc); - app_log_cbap_debug("Device OOB Signature:" APP_LOG_NL); - app_log_cbap_hexdump(&signed_device_oob_data[OOB_DATA_LEN], - OOB_SIGNATURE_LEN); - app_log_cbap_debug(APP_LOG_NL); + sl_bt_cbap_log_debug("Device OOB Signature:" APP_LOG_NL); + sl_bt_cbap_log_hexdump(&signed_device_oob_data[OOB_DATA_LEN], + OOB_SIGNATURE_LEN); + sl_bt_cbap_log_debug(APP_LOG_NL); cbap_central_state = SL_BT_CBAP_CENTRAL_GET_PERIPHERAL_OOB; sl_bt_cbap_central_on_event(cbap_central_state); @@ -725,12 +725,12 @@ static void on_event_central(sl_bt_msg_t *evt) sc = sl_bt_cbap_lib_process_remote_cert(remote_certificate_der, remote_certificate_der_len); if (sc == SL_STATUS_OK) { - app_log_cbap_info("Remote certificate verified." APP_LOG_NL); + sl_bt_cbap_log_info("Remote certificate verified." APP_LOG_NL); } else { - app_log_cbap_info("Remote certificate verification failed. " \ - "Disconnecting." APP_LOG_NL); - sc = sl_bt_connection_close(connection); - app_assert_status(sc); + sl_bt_cbap_log_error("Remote certificate verification failed. " \ + "Disconnecting." APP_LOG_NL); + sl_bt_on_cbap_error(); + cbap_reset(); break; } } @@ -757,31 +757,53 @@ static void on_event_central(sl_bt_msg_t *evt) sl_bt_gatt_disable); app_assert_status(sc); - app_log_cbap_debug("Remote OOB data:" APP_LOG_NL); - app_log_cbap_hexdump(&remote_random, sizeof(aes_key_128)); - app_log_cbap_debug(APP_LOG_NL); - app_log_cbap_hexdump(&remote_confirm, sizeof(aes_key_128)); - app_log_cbap_debug(APP_LOG_NL); - app_log_cbap_debug("Remote OOB signature:" APP_LOG_NL); - app_log_cbap_hexdump(&remote_oob_signature, OOB_SIGNATURE_LEN); - app_log_cbap_debug(APP_LOG_NL); + sl_bt_cbap_log_debug("Remote OOB data:" APP_LOG_NL); + sl_bt_cbap_log_hexdump(&remote_random, sizeof(aes_key_128)); + sl_bt_cbap_log_debug(APP_LOG_NL); + sl_bt_cbap_log_hexdump(&remote_confirm, sizeof(aes_key_128)); + sl_bt_cbap_log_debug(APP_LOG_NL); + sl_bt_cbap_log_debug("Remote OOB signature:" APP_LOG_NL); + sl_bt_cbap_log_hexdump(&remote_oob_signature, OOB_SIGNATURE_LEN); + sl_bt_cbap_log_debug(APP_LOG_NL); sc = sl_bt_cbap_lib_verify_remote_oob_data(remote_random.data, remote_confirm.data, remote_oob_signature); app_assert_status(sc); - app_log_cbap_info("Remote OOB data verified." APP_LOG_NL); + sl_bt_cbap_log_info("Remote OOB data verified." APP_LOG_NL); sc = sl_bt_sm_set_remote_oob(1, remote_random, remote_confirm); app_assert_status(sc); + sc = sl_bt_cbap_destroy_key(); + app_assert_status(sc); } break; } } +/***************************************************************************//** + * Reset CBAP process states, flags and timers. + ******************************************************************************/ +static void cbap_reset(void) +{ + set_timeout(false); // Make sure timer is stopped + connection = SL_BT_INVALID_CONNECTION_HANDLE; // Clear connection handle + // Reset states + cbap_peripheral_state = (sl_bt_cbap_peripheral_state_t)0; + sl_bt_cbap_peripheral_on_event(cbap_peripheral_state); + cbap_central_state = (sl_bt_cbap_central_state_t)0; + sl_bt_cbap_central_on_event(cbap_central_state); + char_state = (characteristics_t)0; + // Reset flags + remote_cert_arrived = false; + device_cert_sent = false; + remote_certificate_der_len = 0; + dev_cert_sending_progression = 0; +} + /******************************************************************************* * Search for a Service UUID in scan report. * - * @param[in] scan_data Data received in evt_scanner_scan_report + * @param[in] scan_data Data received in scanner advertisement report event * @param[in] scan_data_len Length of the scan data * @param[in] uuid Service UUID to search for * @param[in] uuid_len Service UUID length @@ -853,11 +875,10 @@ static void state_timer_cb(sl_simple_timer_t *handle, void *data) { (void)handle; (void)data; - sl_status_t sc; - app_log_cbap_info("Timeout error. Disconnecting." APP_LOG_NL); - sc = sl_bt_connection_close(connection); - app_assert_status(sc); + sl_bt_cbap_log_error("Timeout error. Disconnecting." APP_LOG_NL); + sl_bt_on_cbap_error(); + cbap_reset(); } // CBAP Peripheral event handler WEAK implementation. @@ -871,3 +892,11 @@ SL_WEAK void sl_bt_cbap_central_on_event(sl_bt_cbap_central_state_t status) { (void)status; } + +// Callback to handle CBAP process errors. +SL_WEAK void sl_bt_on_cbap_error(void) +{ + sl_status_t sc; + sc = sl_bt_connection_close(connection); + app_assert_status(sc); +} diff --git a/app/bluetooth/common/cbap/sl_bt_cbap.h b/app/bluetooth/common/cbap/sl_bt_cbap.h index 5cbcd54c15..024a27c1b5 100644 --- a/app/bluetooth/common/cbap/sl_bt_cbap.h +++ b/app/bluetooth/common/cbap/sl_bt_cbap.h @@ -71,7 +71,7 @@ void sl_bt_cbap_init(void); * Start CBAP procedure. * @param[in] cbap_role Device role. Should be either SL_BT_CBAP_ROLE_PERIPHERAL or * SL_BT_CBAP_ROLE_CENTRAL. - * @param[in] connection Connection handle. + * @param[in] connection Handle of the active connection. * * @param SL_STATUS_OK if successful otherwise error code. *****************************************************************************/ @@ -98,10 +98,16 @@ void sl_bt_cbap_peripheral_on_event(sl_bt_cbap_peripheral_state_t status); *****************************************************************************/ void sl_bt_cbap_central_on_event(sl_bt_cbap_central_state_t status); +/**************************************************************************//** + * Callback to handle CBAP process errors. + * @note To be implemented in user code. + *****************************************************************************/ +void sl_bt_on_cbap_error(void); + /**************************************************************************//** * Search for a the CBAP Service UUID in scan report. * - * @param[in] scan_data Data received in evt_scanner_scan_report + * @param[in] scan_data Data received in scanner advertisement report event * @param[in] scan_data_len Length of the scan data * @return true if the CBAP service is found *****************************************************************************/ diff --git a/app/bluetooth/common/cbap_lib/lib/cbap_CM33_gcc.a b/app/bluetooth/common/cbap_lib/lib/cbap_CM33_gcc.a index c06fad2775..38879a2fb0 100644 --- a/app/bluetooth/common/cbap_lib/lib/cbap_CM33_gcc.a +++ b/app/bluetooth/common/cbap_lib/lib/cbap_CM33_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6dc4caaa6de828d6a4340e8418254ed1bd01fd3b38f06df0e7e423a3284be7c5 -size 4780 +oid sha256:90f4f2f4bcd59f33b6e80ece80ba6966d51df97213d96667e20b6f0883d14519 +size 5318 diff --git a/app/bluetooth/common/cbap_lib/lib/cbap_CM33_iar.a b/app/bluetooth/common/cbap_lib/lib/cbap_CM33_iar.a index 578e8976fa..da5f072582 100644 --- a/app/bluetooth/common/cbap_lib/lib/cbap_CM33_iar.a +++ b/app/bluetooth/common/cbap_lib/lib/cbap_CM33_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2e6dbfff481a375584dbc800abc890f35235d1c624891558716aae95065be59d -size 10088 +oid sha256:a44c17e6fda0c47b809a50b7bde40f1939faeae076f81e05cef85a133d72fbaa +size 10508 diff --git a/app/bluetooth/common/cbap_lib/sl_bt_cbap_lib.h b/app/bluetooth/common/cbap_lib/sl_bt_cbap_lib.h index 8ceb0fd0c7..1c4b69d7ab 100644 --- a/app/bluetooth/common/cbap_lib/sl_bt_cbap_lib.h +++ b/app/bluetooth/common/cbap_lib/sl_bt_cbap_lib.h @@ -86,4 +86,11 @@ sl_status_t sl_bt_cbap_lib_verify_remote_oob_data(uint8_t *remote_random, uint8_t *remote_confirm, uint8_t *remote_oob_signature); +/***************************************************************************//** + * Destroys the keys which were used during the CBAP process. + * + * @return SL_STATUS_OK if OK, error code otherwise. + ******************************************************************************/ +sl_status_t sl_bt_cbap_destroy_key(void); + #endif // SL_BT_CBAP_LIB_H diff --git a/app/bluetooth/common/gatt_service_cte_adv/sl_gatt_service_cte_connectionless.c b/app/bluetooth/common/gatt_service_cte_adv/sl_gatt_service_cte_connectionless.c index 74b52b9661..8604e17044 100644 --- a/app/bluetooth/common/gatt_service_cte_adv/sl_gatt_service_cte_connectionless.c +++ b/app/bluetooth/common/gatt_service_cte_adv/sl_gatt_service_cte_connectionless.c @@ -101,7 +101,7 @@ sl_status_t adv_cte_start(void) // Set PHY. if (sc == SL_STATUS_OK) { sc = sl_bt_extended_advertiser_set_phy(advertising_set_handle, - sl_bt_gap_1m_phy, + sl_bt_gap_phy_1m, ADV_CTE_PHY_CONVERT(adv_cte_phy)); } diff --git a/app/bluetooth/common/gatt_service_cte_adv/sl_gatt_service_cte_silabs.c b/app/bluetooth/common/gatt_service_cte_adv/sl_gatt_service_cte_silabs.c index cd3d5253cd..ebdcc42dd8 100644 --- a/app/bluetooth/common/gatt_service_cte_adv/sl_gatt_service_cte_silabs.c +++ b/app/bluetooth/common/gatt_service_cte_adv/sl_gatt_service_cte_silabs.c @@ -101,7 +101,7 @@ sl_status_t adv_cte_start(void) // Set PHY. if (sc == SL_STATUS_OK) { sc = sl_bt_extended_advertiser_set_phy(advertising_set_handle, - sl_bt_gap_1m_phy, + sl_bt_gap_phy_1m, ADV_CTE_PHY_CONVERT(adv_cte_phy)); } diff --git a/app/bluetooth/common/gatt_service_cte_adv/sli_gatt_service_cte_adv.h b/app/bluetooth/common/gatt_service_cte_adv/sli_gatt_service_cte_adv.h index 58616183ba..ed058418f9 100644 --- a/app/bluetooth/common/gatt_service_cte_adv/sli_gatt_service_cte_adv.h +++ b/app/bluetooth/common/gatt_service_cte_adv/sli_gatt_service_cte_adv.h @@ -62,7 +62,7 @@ typedef uint8_t adv_cte_phy_t; extern adv_cte_phy_t adv_cte_phy; #define ADV_CTE_PHY_1M 0 #define ADV_CTE_PHY_2M 1 -#define ADV_CTE_PHY_CONVERT(p) (((p) == ADV_CTE_PHY_2M) ? sl_bt_gap_2m_phy : sl_bt_gap_1m_phy) +#define ADV_CTE_PHY_CONVERT(p) (((p) == ADV_CTE_PHY_2M) ? sl_bt_gap_phy_2m : sl_bt_gap_phy_1m) /**************************************************************************//** * Initialize advertisement package according to CTE specifications. diff --git a/app/bluetooth/common/l2cap_transfer/src/sl_bt_l2cap_transfer.c b/app/bluetooth/common/l2cap_transfer/src/sl_bt_l2cap_transfer.c index 32aae3afdf..c48464a74d 100644 --- a/app/bluetooth/common/l2cap_transfer/src/sl_bt_l2cap_transfer.c +++ b/app/bluetooth/common/l2cap_transfer/src/sl_bt_l2cap_transfer.c @@ -449,11 +449,11 @@ static void register_open_response_from_server(sl_bt_evt_l2cap_le_channel_open_r transfer = select_transfer_by_connection(response_event->connection, request_pending_transfer_list); - transfer->max_pdu = response_event->max_pdu; - transfer->max_sdu = response_event->max_sdu; - transfer->credit = response_event->credit; - if (transfer != NULL) { + transfer->max_pdu = response_event->max_pdu; + transfer->max_sdu = response_event->max_sdu; + transfer->credit = response_event->credit; + CORE_ENTER_CRITICAL(); sl_slist_remove(&request_pending_transfer_list, &transfer->node); @@ -466,11 +466,11 @@ static void register_open_response_from_server(sl_bt_evt_l2cap_le_channel_open_r } CORE_EXIT_CRITICAL(); - } - if (sl_bt_l2cap_connection_result_successful != error_code) { - transfer->channel_error = error_code; - close_transfer(transfer->connection, transfer->cid, error_code); + if (sl_bt_l2cap_connection_result_successful != error_code) { + transfer->channel_error = error_code; + close_transfer(transfer->connection, transfer->cid, error_code); + } } } diff --git a/app/bluetooth/common/ots/inc/sl_bt_ots_client.h b/app/bluetooth/common/ots/inc/sl_bt_ots_client.h index ff198f2805..c598f90239 100644 --- a/app/bluetooth/common/ots/inc/sl_bt_ots_client.h +++ b/app/bluetooth/common/ots/inc/sl_bt_ots_client.h @@ -641,6 +641,16 @@ sl_status_t sl_bt_ots_client_oacp_abort(sl_bt_ots_client_handle_t client); sl_status_t sl_bt_ots_client_increase_credit(sl_bt_ots_client_handle_t client, uint16_t credit); +/***************************************************************************//** + * Abort current write or read operation. Close the L2CAP channel in case of + * Write operation is in progress or execute OACP Abort in case of Read + * operation is in progress. + * + * @param[in] client Client handle. + * @return Status code + ******************************************************************************/ +sl_status_t sl_bt_ots_client_abort(sl_bt_ots_client_handle_t client); + /***************************************************************************//** * Internal Bluetooth event handler. * @param[in] evt Bluetooth event. diff --git a/app/bluetooth/common/ots/src/sl_bt_ots_client.c b/app/bluetooth/common/ots/src/sl_bt_ots_client.c index 5459ec7422..a852b5e1b0 100644 --- a/app/bluetooth/common/ots/src/sl_bt_ots_client.c +++ b/app/bluetooth/common/ots/src/sl_bt_ots_client.c @@ -235,6 +235,14 @@ sl_status_t sl_bt_ots_client_init(sl_bt_ots_client_handle_t client, client->status = CLIENT_STATUS_BEGIN; + // Active parameter clear + client->active_handle_index = SL_BT_OTS_CHARACTERISTIC_UUID_INDEX_INVALID; + client->active_opcode = 0; + client->active_transfer_size = 0; + client->active_transfer_offset = 0; + client->active_transfer_sdu = 0; + client->active_transfer_pdu = 0; + // Add client to the list sl_slist_push_back(&client_list, &client->node); @@ -783,8 +791,12 @@ sl_status_t sl_bt_ots_client_oacp_execute(sl_bt_ots_client_handle_t client, return SL_STATUS_NULL_POINTER; } - uint8_t total_size = sizeof(sl_bt_ots_oacp_opcode_t) + optional_data_size; - uint8_t content[total_size]; + uint16_t total_size = sizeof(sl_bt_ots_oacp_opcode_t) + optional_data_size; + if (total_size > SL_BT_OTS_CLIENT_CONFIG_WRITE_REQUEST_DATA_SIZE) { + return SL_STATUS_INVALID_PARAMETER; + } + + uint8_t content[SL_BT_OTS_CLIENT_CONFIG_WRITE_REQUEST_DATA_SIZE]; sl_bt_ots_oacp_message_t *message = (sl_bt_ots_oacp_message_t *)&content; message->opcode = SL_BT_OTS_OACP_OPCODE_EXECUTE; @@ -820,7 +832,7 @@ sl_status_t sl_bt_ots_client_oacp_read(sl_bt_ots_client_handle_t client, } uint8_t total_size = sizeof(sl_bt_ots_oacp_opcode_t) + sizeof(sl_bt_ots_oacp_read_parameters_t); - uint8_t content[total_size]; + uint8_t content[sizeof(sl_bt_ots_oacp_opcode_t) + sizeof(sl_bt_ots_oacp_read_parameters_t)]; sl_bt_ots_oacp_message_t *message = (sl_bt_ots_oacp_message_t *)&content; sl_bt_ots_oacp_read_parameters_t *parameters = (sl_bt_ots_oacp_read_parameters_t *)message->data; @@ -862,7 +874,7 @@ sl_status_t sl_bt_ots_client_oacp_write(sl_bt_ots_client_handle_t client, } uint8_t total_size = sizeof(sl_bt_ots_oacp_opcode_t) + sizeof(sl_bt_ots_oacp_write_parameters_t); - uint8_t content[total_size]; + uint8_t content[sizeof(sl_bt_ots_oacp_opcode_t) + sizeof(sl_bt_ots_oacp_write_parameters_t)]; sl_bt_ots_oacp_message_t *message = (sl_bt_ots_oacp_message_t *)&content; sl_bt_ots_oacp_write_parameters_t *parameters = (sl_bt_ots_oacp_write_parameters_t *)message->data; @@ -894,7 +906,7 @@ sl_status_t sl_bt_ots_client_oacp_abort(sl_bt_ots_client_handle_t client) // Check status for read in progress if ((client->status) != CLIENT_STATUS_WAIT_OACP_TRANSFER - && client->active_opcode == SL_BT_OTS_OACP_OPCODE_READ) { + || client->active_opcode != SL_BT_OTS_OACP_OPCODE_READ) { return SL_STATUS_INVALID_STATE; } @@ -926,6 +938,30 @@ sl_status_t sl_bt_ots_client_increase_credit(sl_bt_ots_client_handle_t client, return sc; } +sl_status_t sl_bt_ots_client_abort(sl_bt_ots_client_handle_t client) +{ + sl_status_t sc = SL_STATUS_INVALID_STATE; + + // Check arguments + CHECK_NULL(client); + + // Check state + if (client->status == CLIENT_STATUS_WAIT_OACP_TRANSFER) { + if (client->active_opcode == SL_BT_OTS_OACP_OPCODE_READ) { + // Abort read in a gentle way. + sc = sl_bt_ots_client_oacp_abort(client); + } else if (client->active_opcode == SL_BT_OTS_OACP_OPCODE_WRITE) { + // Check progress of the operation + sc = sl_bt_l2cap_transfer_check_progress(&client->l2cap_transfer); + if (sc == SL_STATUS_IN_PROGRESS) { + // Abort the L2CAP transfer + sc = sl_bt_l2cap_transfer_abort_transfer(&client->l2cap_transfer); + } + } + } + return sc; +} + void sli_bt_ots_client_init(void) { for (uint8_t connection_index = 0; connection_index < SL_BT_CONFIG_MAX_CONNECTIONS; connection_index++) { @@ -1035,6 +1071,10 @@ void sli_bt_ots_client_on_bt_event(sl_bt_msg_t *evt) } // Set status handle->status = CLIENT_STATUS_DISCONNECTED; + + // Remove client from the list + sl_slist_remove(&client_list, &handle->node); + // Do callback CALL_SAFE(handle, on_disconnect, handle); } @@ -1164,7 +1204,7 @@ void sli_bt_ots_client_on_bt_event(sl_bt_msg_t *evt) memcpy(buffer->data, evt->data.evt_gatt_characteristic_value.value.data, buffer->len); } // Handle indication - if (evt->data.evt_gatt_characteristic_value.att_opcode == gatt_handle_value_indication + if (evt->data.evt_gatt_characteristic_value.att_opcode == sl_bt_gatt_handle_value_indication && handle != NULL) { uint8_t att_error = ATT_ERR_SUCCESS; // OLCP indication @@ -1270,9 +1310,10 @@ void sli_bt_ots_client_on_bt_event(sl_bt_msg_t *evt) && (response->opcode == SL_BT_OTS_OACP_OPCODE_READ || response->opcode == SL_BT_OTS_OACP_OPCODE_WRITE)) { // Set transfer parameters - handle->l2cap_transfer.callbacks = &l2cap_transfer_callbacks; - handle->l2cap_transfer.connection = handle->connection; + handle->l2cap_transfer.callbacks = &l2cap_transfer_callbacks; + handle->l2cap_transfer.connection = handle->connection; handle->l2cap_transfer.data_length = handle->active_transfer_size; + handle->l2cap_transfer.data_offset = handle->active_transfer_offset; handle->l2cap_transfer.mode = (response->opcode == SL_BT_OTS_OACP_OPCODE_WRITE) ? SL_BT_L2CAP_TRANSFER_MODE_TRANSMIT : SL_BT_L2CAP_TRANSFER_MODE_RECEIVE; @@ -1457,6 +1498,12 @@ static void l2cap_transfer_transfer_finished(sl_bt_l2cap_transfer_transfer_handl if (error_code != SL_STATUS_OK) { result = SL_BT_OTS_TRANSFER_FINISHED_RESPONSE_CODE_CHANNEL_ERROR; } + // Active transfer clear + handle->active_transfer_size = 0; + handle->active_transfer_offset = 0; + handle->active_transfer_sdu = 0; + handle->active_transfer_pdu = 0; + CALL_SAFE(handle, on_data_transfer_finished, handle, @@ -1667,6 +1714,11 @@ static sl_bt_ots_client_status_t finish_init(sl_bt_ots_client_t *client, // Clear active client for connection active_client[HANDLE_TO_INDEX(client->connection)] = NULL; + if (client->status == CLIENT_STATUS_ERROR) { + // Remove client from the list + sl_slist_remove(&client_list, &client->node); + } + return client->status; } diff --git a/app/bluetooth/common/ots/src/sl_bt_ots_server.c b/app/bluetooth/common/ots/src/sl_bt_ots_server.c index 1857aa75ce..eb769b1a4d 100644 --- a/app/bluetooth/common/ots/src/sl_bt_ots_server.c +++ b/app/bluetooth/common/ots/src/sl_bt_ots_server.c @@ -576,9 +576,9 @@ static void set_object_invalid(sl_bt_ots_object_id_t *object) static sl_bt_ots_characteristic_uuid_index find_characteristic_index(uint16_t handle, sl_bt_ots_server_t **server) { + *server = NULL; // Find handle on a server if (INVALID_CHARACTERISTIC_HANDLE == handle) { - server = NULL; return SL_BT_OTS_CHARACTERISTIC_UUID_INDEX_INVALID; } // Find handle on a server @@ -1818,14 +1818,15 @@ static void handle_gatt_write(sl_bt_evt_gatt_server_user_write_request_t *write_ { sl_bt_ots_server_t *server = NULL; sl_bt_ots_server_client_db_entry_t *client = NULL; - sl_bt_ots_characteristic_uuid_index characteristic_index = SL_BT_OTS_CHARACTERISTIC_UUID_INDEX_INVALID; + sl_bt_ots_characteristic_uuid_index characteristic_index = SL_BT_OTS_CHARACTERISTIC_UUID_INDEX_INVALID; uint8_t att_error = ATT_ERR_SUCCESS; // Find characteristic handle characteristic_index = find_characteristic_index(write_request->characteristic, &server); // Check server hand characteristic index - if (server != NULL && characteristic_index != SL_BT_OTS_CHARACTERISTIC_UUID_INDEX_INVALID) { + if (server != NULL + && characteristic_index != SL_BT_OTS_CHARACTERISTIC_UUID_INDEX_INVALID) { // Identify client client = find_client(server, write_request->connection); @@ -1908,15 +1909,16 @@ static void handle_gatt_write(sl_bt_evt_gatt_server_user_write_request_t *write_ static void handle_cccd(sl_bt_evt_gatt_server_characteristic_status_t *characteristic_status) { - sl_bt_ots_server_t *server; + sl_bt_ots_server_t *server = NULL; if (sl_bt_gatt_server_client_config == characteristic_status->status_flags ) { sl_bt_ots_characteristic_uuid_index characteristic_index = find_characteristic_index(characteristic_status->characteristic, &server); bool value = (sl_bt_gatt_indication & characteristic_status->client_config_flags) > 0; - if (server != NULL) { - sl_bt_ots_server_client_db_entry_t * client = find_client(server, - characteristic_status->connection); + if (server != NULL + && characteristic_index != SL_BT_OTS_CHARACTERISTIC_UUID_INDEX_INVALID) { + sl_bt_ots_server_client_db_entry_t *client = find_client(server, + characteristic_status->connection); bool changed = false; if (client != NULL) { switch (characteristic_index) { diff --git a/app/bluetooth/common/power_supply/sl_power_supply.c b/app/bluetooth/common/power_supply/sl_power_supply.c index b850037893..7a3fde22c7 100644 --- a/app/bluetooth/common/power_supply/sl_power_supply.c +++ b/app/bluetooth/common/power_supply/sl_power_supply.c @@ -72,9 +72,9 @@ typedef struct { // ----------------------------------------------------------------------------- // Private variables -static float supply_voltage; ///< Supply voltage -static float supply_ir; ///< Internal resistance of the supply -static uint8_t supply_type; ///< Type of the connected supply +static float supply_voltage = 0.0f; ///< Supply voltage +static float supply_ir = 0.0f; ///< Internal resistance of the supply +static uint8_t supply_type = SL_POWER_SUPPLY_TYPE_UNKNOWN; ///< Type of the connected supply static batt_model_entry_t batt_model_cr2032[] = { { 3.0, 100 }, { 2.9, 80 }, { 2.8, 60 }, { 2.7, 40 }, { 2.6, 30 }, @@ -306,23 +306,27 @@ void sl_power_supply_probe(void) "[E: %#04x] Si7021 sensor not available\n", sc); sc = sl_si70xx_init(rht_sensor, SI7021_ADDR); - app_assert_status(sc); - - // Try to measure using 9.18 mA first. - v = sl_power_supply_measure_voltage(16); - r = measure_supply_ir(0x00); - if ( r > 5.0 ) { - type = SL_POWER_SUPPLY_TYPE_CR2032; - } else if (r > 0.5) { - type = SL_POWER_SUPPLY_TYPE_AAA; + + if (sc == SL_STATUS_OK) { + // Try to measure using 9.18 mA first. + v = sl_power_supply_measure_voltage(16); + r = measure_supply_ir(0x00); + if ( r > 5.0 ) { + type = SL_POWER_SUPPLY_TYPE_CR2032; + } else if (r > 0.5) { + type = SL_POWER_SUPPLY_TYPE_AAA; + } else { + type = SL_POWER_SUPPLY_TYPE_USB; + } + + // Store measurement results in global variables. + supply_voltage = v; + supply_ir = r; + supply_type = type; } else { - type = SL_POWER_SUPPLY_TYPE_USB; + app_log_warning("Si7021 sensor initialization failed. " + "Unable to detect power supply type." APP_LOG_NL); } - - // Store measurement results in global variables. - supply_voltage = v; - supply_ir = r; - supply_type = type; } /***************************************************************************//** @@ -348,15 +352,7 @@ uint8_t sl_power_supply_get_type(void) ******************************************************************************/ bool sl_power_supply_is_low_power(void) { - bool lp; - - if ( (supply_type != SL_POWER_SUPPLY_TYPE_CR2032) && (supply_type != SL_POWER_SUPPLY_TYPE_UNKNOWN) ) { - lp = false; - } else { - lp = true; - } - - return lp; + return supply_type == SL_POWER_SUPPLY_TYPE_CR2032; } /***************************************************************************//** diff --git a/app/bluetooth/common/simple_com/sl_simple_com_cpc.c b/app/bluetooth/common/simple_com/sl_simple_com_cpc.c index 4b05b1cc39..edef30f51d 100644 --- a/app/bluetooth/common/simple_com/sl_simple_com_cpc.c +++ b/app/bluetooth/common/simple_com/sl_simple_com_cpc.c @@ -39,8 +39,15 @@ static uint8_t tx_buf[SL_SIMPLE_COM_TX_BUF_SIZE] = { 0 }; static sl_cpc_endpoint_handle_t endpoint_handle; +// Write completed signal +typedef struct { + uint8_t write_completed; + sl_status_t wr_comp_status; +} sig_wr_comp; + // Signals to handle communication between callback functions static uint8_t signal_write = 0; +static sig_wr_comp signal_wr_comp = { 0 }; static uint8_t signal_read = 0; static uint8_t signal_init = 1; @@ -109,10 +116,20 @@ void sl_simple_com_step(void) // Everything OK, send msg to upper layers memcpy(rx_buf, rx_buf_p, len); sl_simple_com_receive_cb(status, len, rx_buf); + sl_cpc_free_rx_buffer((void *) &rx_buf); signal_read--; memset(rx_buf, 0, sizeof(rx_buf)); } } + + if (signal_wr_comp.write_completed > 0) { + if (!signal_init) { + memset(tx_buf, 0, sizeof(tx_buf)); + sl_simple_com_transmit_cb(signal_wr_comp.wr_comp_status); + signal_wr_comp.wr_comp_status = SL_STATUS_FAIL; + signal_wr_comp.write_completed--; + } + } } /**************************************************************************//** @@ -189,6 +206,7 @@ void cpc_rx_cb(uint8_t endpoint_id, void *arg) { (void)endpoint_id; (void)arg; + signal_read++; } @@ -204,8 +222,8 @@ void cpc_tx_cb(sl_cpc_user_endpoint_id_t endpoint_id, (void)(buffer); (void)(arg); - if (!signal_init) { - memset(tx_buf, 0, sizeof(tx_buf)); - sl_simple_com_transmit_cb(status); - } + CORE_ATOMIC_SECTION( + signal_wr_comp.wr_comp_status = status; + signal_wr_comp.write_completed++; + ) } diff --git a/app/bluetooth/common/throughput/throughput_types.h b/app/bluetooth/common/throughput/throughput_types.h index 20d05ec651..814e2dda75 100644 --- a/app/bluetooth/common/throughput/throughput_types.h +++ b/app/bluetooth/common/throughput/throughput_types.h @@ -79,7 +79,7 @@ typedef uint16_t throughput_mtu_size_t; /// Data size type typedef uint16_t throughput_data_size_t; /// PHY type -typedef sl_bt_gap_phy_and_coding_type_t throughput_phy_t; +typedef sl_bt_gap_phy_coding_t throughput_phy_t; /// Notification/indication type typedef sl_bt_gatt_client_config_flag_t throughput_notification_t; /// Throughput type diff --git a/app/bluetooth/common/throughput_central/config/throughput_central_config.h b/app/bluetooth/common/throughput_central/config/throughput_central_config.h index d9710fb38e..6d349f11ea 100644 --- a/app/bluetooth/common/throughput_central/config/throughput_central_config.h +++ b/app/bluetooth/common/throughput_central/config/throughput_central_config.h @@ -37,18 +37,18 @@ #define THROUGHPUT_CENTRAL_MTU_SIZE 247 // Default PHY for scanning -// 1M PHY -// Coded PHY -// Default: sl_bt_gap_1m_phy_uncoded -#define THROUGHPUT_DEFAULT_SCAN_PHY sl_bt_gap_1m_phy_uncoded +// 1M PHY +// Coded PHY +// Default: sl_bt_gap_phy_coding_1m_uncoded +#define THROUGHPUT_DEFAULT_SCAN_PHY sl_bt_gap_phy_coding_1m_uncoded // Default PHY -// 1M PHY -// 2M PHY -// 125k Coded PHY (S=8) -// 500k Coded PHY (S=2) -// Default: sl_bt_gap_1m_phy_uncoded -#define THROUGHPUT_DEFAULT_PHY sl_bt_gap_1m_phy_uncoded +// 1M PHY +// 2M PHY +// 125k Coded PHY (S=8) +// 500k Coded PHY (S=2) +// Default: sl_bt_gap_phy_coding_1m_uncoded +#define THROUGHPUT_DEFAULT_PHY sl_bt_gap_phy_coding_1m_uncoded // diff --git a/app/bluetooth/common/throughput_central/throughput_central.c b/app/bluetooth/common/throughput_central/throughput_central.c index 112873cdb4..2cb40dd871 100644 --- a/app/bluetooth/common/throughput_central/throughput_central.c +++ b/app/bluetooth/common/throughput_central/throughput_central.c @@ -60,8 +60,6 @@ // Hardware clock ticks that equal one second #define HW_TICKS_PER_SECOND 32768 -#define SCAN_PASSIVE 0 -#define TRANSMISSION_ON 1 #define TRANSMISSION_OFF 0 #define UUID_LEN 16 @@ -90,8 +88,8 @@ static throughput_count_t bytes_received = 0; static throughput_count_t operation_count = 0; /// Power control status -static connection_power_reporting_mode_t power_control_enabled - = connection_power_reporting_disable; +static sl_bt_connection_power_reporting_mode_t power_control_enabled + = sl_bt_connection_power_reporting_disable; /// Deep sleep enabled static bool deep_sleep_enabled = THROUGHPUT_CENTRAL_SLEEP_ENABLE; @@ -143,7 +141,11 @@ const uint8_t result_characteristic_uuid[] = { 0x1b, 0x29, 0xcc, 0xa6, 0x03, 0xb 0x0c, 0x40, 0x0f, 0xb0, 0x27, 0x22, 0xf3, 0xad }; // Function declarations -static bool process_scan_response(sl_bt_evt_scanner_scan_report_t *response); +static void handle_scan_event(bd_addr *address, + uint8_t address_type, + uint8_t * data, + uint16_t len); +static bool process_scan_response(uint8_t *data, uint16_t data_len); static void process_procedure_complete_event(sl_bt_msg_t *evt); static void check_characteristic_uuid(sl_bt_msg_t *evt); static void reset_variables(void); @@ -186,45 +188,30 @@ void bt_on_event_central(sl_bt_msg_t *evt) } switch (SL_BT_MSG_ID(evt->header)) { - case sl_bt_evt_scanner_scan_report_id: - if ((central_state.discovery_state == THROUGHPUT_DISCOVERY_STATE_SCAN) - & process_scan_response(&(evt->data.evt_scanner_scan_report))) { - // Apply allowlist filtering - if (false == throughput_central_allowlist_apply(evt->data.evt_scanner_scan_report.address.addr)) { - break; - } - - // Stop scanning - sc = sl_bt_scanner_stop(); - app_assert_status(sc); - - // Open the connection - central_state.discovery_state = THROUGHPUT_DISCOVERY_STATE_CONN; - throughput_central_on_discovery_state_change(central_state.discovery_state); - - sc = sl_bt_connection_open(evt->data.evt_scanner_scan_report.address, - evt->data.evt_scanner_scan_report.address_type, - central_state.phy, - &connection_handle); - - // Handle if the default PHY is not supported - if (sc == SL_STATUS_INVALID_PARAMETER) { - app_log_status_warning_f(sc, "Connection PHY is not supported and set to 1M PHY" APP_LOG_NEW_LINE); - - central_state.phy = sl_bt_gap_1m_phy_uncoded; - sc = sl_bt_connection_open(evt->data.evt_scanner_scan_report.address, - evt->data.evt_scanner_scan_report.address_type, - central_state.phy, - &connection_handle); - } - // Assertion to first or second attempt to connect - app_assert_status(sc); - } else { - waiting_indication(); + case sl_bt_evt_scanner_legacy_advertisement_report_id: + // If the device is connectable and scannable + if (evt->data.evt_scanner_legacy_advertisement_report.event_flags + & (SL_BT_SCANNER_EVENT_FLAG_CONNECTABLE | SL_BT_SCANNER_EVENT_FLAG_SCANNABLE)) { + handle_scan_event(&evt->data.evt_scanner_legacy_advertisement_report.address, + evt->data.evt_scanner_legacy_advertisement_report.address_type, + evt->data.evt_scanner_legacy_advertisement_report.data.data, + evt->data.evt_scanner_legacy_advertisement_report.data.len); + } + break; + case sl_bt_evt_scanner_extended_advertisement_report_id: + // If the device is connectable, scannable and the data is complete + if ((evt->data.evt_scanner_extended_advertisement_report.event_flags + & (SL_BT_SCANNER_EVENT_FLAG_CONNECTABLE | SL_BT_SCANNER_EVENT_FLAG_SCANNABLE)) + && (evt->data.evt_scanner_extended_advertisement_report.data_completeness + == sl_bt_scanner_data_status_complete)) { + handle_scan_event(&evt->data.evt_scanner_extended_advertisement_report.address, + evt->data.evt_scanner_extended_advertisement_report.address_type, + evt->data.evt_scanner_extended_advertisement_report.data.data, + evt->data.evt_scanner_extended_advertisement_report.data.len); } break; - case sl_bt_evt_connection_opened_id: + connection_handle = evt->data.evt_connection_opened.connection; // Set remote connection power reporting - needed for Power Control sc = sl_bt_connection_set_remote_power_reporting(connection_handle, power_control_enabled); @@ -281,7 +268,7 @@ void bt_on_event_central(sl_bt_msg_t *evt) finish_test = true; } } else if (evt->data.evt_gatt_characteristic_value.characteristic == result_handle) { - if (evt->data.evt_gatt_characteristic_value.att_opcode == gatt_handle_value_indication) { + if (evt->data.evt_gatt_characteristic_value.att_opcode == sl_bt_gatt_handle_value_indication) { sl_bt_gatt_send_characteristic_confirmation(evt->data.evt_gatt_characteristic_value.connection); // Responder sends indication about result after each test. Data is uint8array LSB first. memcpy(&results.throughput_peripheral_side, evt->data.evt_gatt_characteristic_value.value.data, 4); @@ -294,7 +281,7 @@ void bt_on_event_central(sl_bt_msg_t *evt) || evt->data.evt_gatt_characteristic_value.characteristic == notifications_handle) { // Send confirmation if needed if (evt->data.evt_gatt_characteristic_value.characteristic == indications_handle) { - if (evt->data.evt_gatt_characteristic_value.att_opcode == gatt_handle_value_indication) { + if (evt->data.evt_gatt_characteristic_value.att_opcode == sl_bt_gatt_handle_value_indication) { sl_bt_gatt_send_characteristic_confirmation(evt->data.evt_gatt_characteristic_value.connection); } } @@ -395,22 +382,67 @@ static void check_received_data(uint8_t * data, uint8_t len) } } +static void handle_scan_event(bd_addr *address, + uint8_t address_type, + uint8_t * data, + uint16_t len) +{ + sl_status_t sc; + + if ((central_state.discovery_state == THROUGHPUT_DISCOVERY_STATE_SCAN) + & process_scan_response(data, len)) { + // Apply allowlist filtering + if (false == throughput_central_allowlist_apply(address->addr)) { + return; + } + + // Stop scanning + app_log_info("Scanning stop." APP_LOG_NL); + sc = sl_bt_scanner_stop(); + app_assert_status(sc); + + // Open the connection + central_state.discovery_state = THROUGHPUT_DISCOVERY_STATE_CONN; + throughput_central_on_discovery_state_change(central_state.discovery_state); + + sc = sl_bt_connection_open(*address, + address_type, + central_state.phy, + &connection_handle); + + // Handle if the default PHY is not supported + if (sc == SL_STATUS_INVALID_PARAMETER) { + app_log_status_warning_f(sc, "Connection PHY is not supported and set to 1M PHY" APP_LOG_NEW_LINE); + + central_state.phy = sl_bt_gap_phy_coding_1m_uncoded; + sc = sl_bt_connection_open(*address, + address_type, + central_state.phy, + &connection_handle); + } + // Assertion to first or second attempt to connect + app_assert_status(sc); + } else { + waiting_indication(); + } +} + // Cycle through advertisement contents and look for matching device name. -static bool process_scan_response(sl_bt_evt_scanner_scan_report_t *response) +static bool process_scan_response(uint8_t *data, uint16_t data_len) { int i = 0; bool device_name_match = false; uint8_t advertisement_length; uint8_t advertisement_type; - while (i < (response->data.len - 1)) { - advertisement_length = response->data.data[i]; - advertisement_type = response->data.data[i + 1]; + while (i < (data_len - 1)) { + advertisement_length = data[i]; + advertisement_type = data[i + 1]; /* Type 0x09 = Complete Local Name, 0x08 Shortened Name */ if (advertisement_type == 0x09) { /* Check if device name is Throughput Tester */ - if (memcmp(response->data.data + i + 2, device_name, strlen(device_name)) == 0) { + if (memcmp(data + i + 2, device_name, strlen(device_name)) == 0) { device_name_match = true; break; } @@ -678,6 +710,7 @@ void throughput_central_scanning_stop(void) { sl_status_t sc; if (central_state.discovery_state == THROUGHPUT_DISCOVERY_STATE_SCAN) { + app_log_info("Scanning stop." APP_LOG_NL); sc = sl_bt_scanner_stop(); app_assert_status(sc); central_state.discovery_state = THROUGHPUT_DISCOVERY_STATE_IDLE; @@ -688,16 +721,10 @@ void throughput_central_scanning_stop(void) // Apply phy for scanning sl_status_t throughput_central_scanning_apply_phy(throughput_phy_t phy) { - sl_status_t sc; - throughput_central_scanning_stop(); - // Set passive scanning on selected PHY - sc = sl_bt_scanner_set_mode(phy, SCAN_PASSIVE); - if (sc == SL_STATUS_OK) { - central_state.scan_phy = phy; - } + central_state.scan_phy = phy; throughput_central_scanning_start(); - return sc; + return SL_STATUS_OK; } // Start scanning @@ -735,14 +762,6 @@ void throughput_central_scanning_start(void) sc = sl_bt_gatt_server_set_max_mtu(central_state.mtu_size, &(central_state.mtu_size)); app_assert_status(sc); - // Set passive scanning on selected PHY - // Check if scanning phy is supported by setting mode - sc = sl_bt_scanner_set_mode(central_state.scan_phy, SCAN_PASSIVE); - if (sc != SL_STATUS_OK) { - central_state.scan_phy = sl_bt_gap_1m_phy_uncoded; - app_log_warning("Scanning PHY is not supported and set to 1M PHY" APP_LOG_NEW_LINE); - } - // Set the default connection parameters for subsequent connections sc = sl_bt_connection_set_default_parameters(central_state.connection_interval_min, central_state.connection_interval_max, @@ -753,7 +772,13 @@ void throughput_central_scanning_start(void) app_assert_status(sc); // Start scanning - looking for peripheral devices - sc = sl_bt_scanner_start(central_state.scan_phy, scanner_discover_generic); + sc = sl_bt_scanner_start(central_state.scan_phy, sl_bt_scanner_discover_generic); + if (sc != SL_STATUS_OK) { + central_state.scan_phy = sl_bt_gap_phy_coding_1m_uncoded; + app_log_warning("Requested scanning PHY is not supported and set to 1M PHY" APP_LOG_NEW_LINE); + // Start scanning with the modified PHY + sc = sl_bt_scanner_start(central_state.scan_phy, sl_bt_scanner_discover_generic); + } app_assert_status(sc); } @@ -992,7 +1017,7 @@ sl_status_t throughput_central_set_tx_power(throughput_tx_power_t tx_power, sl_status_t res = SL_STATUS_OK; if (enabled && central_state.state != THROUGHPUT_STATE_TEST) { central_state.tx_power_requested = tx_power; - power_control_enabled = (connection_power_reporting_mode_t)power_control; + power_control_enabled = (sl_bt_connection_power_reporting_mode_t)power_control; deep_sleep_enabled = deep_sleep; throughput_central_scanning_restart(); } else { @@ -1102,8 +1127,8 @@ sl_status_t throughput_central_set_connection_phy(throughput_phy_t phy) if (enabled && (central_state.state == THROUGHPUT_STATE_CONNECTED || central_state.state == THROUGHPUT_STATE_SUBSCRIBED) ) { - if (phy == sl_bt_gap_coded_phy_500k) { - accepted_phy = sl_bt_gap_coded_phy; + if (phy == sl_bt_gap_phy_coding_500k_coded) { + accepted_phy = sl_bt_gap_phy_coded; } res = sl_bt_connection_set_preferred_phy(connection_handle, phy, @@ -1125,41 +1150,41 @@ sl_status_t throughput_central_change_phy(void) // If connected current_phy = central_state.phy; switch (current_phy) { - case sl_bt_gap_1m_phy_uncoded: - res = throughput_central_set_connection_phy(sl_bt_gap_2m_phy_uncoded); + case sl_bt_gap_phy_coding_1m_uncoded: + res = throughput_central_set_connection_phy(sl_bt_gap_phy_coding_2m_uncoded); // if cannot switch to 2M, switch to 1M if (res != SL_STATUS_OK) { - res = throughput_central_set_connection_phy(sl_bt_gap_1m_phy_uncoded); + res = throughput_central_set_connection_phy(sl_bt_gap_phy_coding_1m_uncoded); } break; - case sl_bt_gap_2m_phy_uncoded: - res = throughput_central_set_connection_phy(sl_bt_gap_coded_phy_125k); + case sl_bt_gap_phy_coding_2m_uncoded: + res = throughput_central_set_connection_phy(sl_bt_gap_phy_coding_125k_coded); // if cannot switch to coded, switch to 1M if (res != SL_STATUS_OK) { - res = throughput_central_set_connection_phy(sl_bt_gap_1m_phy_uncoded); + res = throughput_central_set_connection_phy(sl_bt_gap_phy_coding_1m_uncoded); } break; - case sl_bt_gap_coded_phy_125k: - res = throughput_central_set_connection_phy(sl_bt_gap_coded_phy_500k); + case sl_bt_gap_phy_coding_125k_coded: + res = throughput_central_set_connection_phy(sl_bt_gap_phy_coding_500k_coded); // if cannot switch to coded, switch to 1M if (res != SL_STATUS_OK) { - res = throughput_central_set_connection_phy(sl_bt_gap_1m_phy_uncoded); + res = throughput_central_set_connection_phy(sl_bt_gap_phy_coding_1m_uncoded); } break; - case sl_bt_gap_coded_phy_500k: - res = throughput_central_set_connection_phy(sl_bt_gap_1m_phy_uncoded); + case sl_bt_gap_phy_coding_500k_coded: + res = throughput_central_set_connection_phy(sl_bt_gap_phy_coding_1m_uncoded); break; default: - res = throughput_central_set_connection_phy(sl_bt_gap_1m_phy_uncoded); + res = throughput_central_set_connection_phy(sl_bt_gap_phy_coding_1m_uncoded); break; } } else if (central_state.state == THROUGHPUT_STATE_DISCONNECTED) { // if disconnected current_phy = central_state.scan_phy; - if (current_phy == sl_bt_gap_1m_phy_uncoded) { - res = throughput_central_set_scan_phy(sl_bt_gap_coded_phy_125k); + if (current_phy == sl_bt_gap_phy_coding_1m_uncoded) { + res = throughput_central_set_scan_phy(sl_bt_gap_phy_coding_125k_coded); } else { - res = throughput_central_set_scan_phy(sl_bt_gap_1m_phy_uncoded); + res = throughput_central_set_scan_phy(sl_bt_gap_phy_coding_1m_uncoded); } } } @@ -1208,9 +1233,9 @@ void throughput_central_enable(void) central_state.packet_lost = 0; if (THROUGHPUT_CENTRAL_POWER_CONTROL_ENABLE) { - power_control_enabled = connection_power_reporting_enable; + power_control_enabled = sl_bt_connection_power_reporting_enable; } else { - power_control_enabled = connection_power_reporting_disable; + power_control_enabled = sl_bt_connection_power_reporting_disable; } // if the power is greater than 10 dBm AFH must be used afh_bit = (central_state.tx_power_requested > 10); @@ -1263,13 +1288,6 @@ void throughput_central_enable(void) throughput_ui_set_all(central_state); #endif // SL_CATALOG_THROUGHPUT_UI_PRESENT - // Check if scanning phy is supported by setting mode - sc = sl_bt_scanner_set_mode(central_state.scan_phy, SCAN_PASSIVE); - if (sc != SL_STATUS_OK) { - central_state.scan_phy = sl_bt_gap_1m_phy_uncoded; - app_log_warning("Default scanning PHY is not supported and set to 1M PHY" APP_LOG_NEW_LINE); - } - // Start scanning throughput_central_scanning_start(); @@ -1436,16 +1454,16 @@ SL_WEAK void throughput_central_on_phy_change(throughput_phy_t phy) throughput_ui_update(); #else switch (phy) { - case sl_bt_gap_1m_phy_uncoded: + case sl_bt_gap_phy_coding_1m_uncoded: app_log_info(THROUGHPUT_UI_PHY_1M_TEXT); break; - case sl_bt_gap_2m_phy_uncoded: + case sl_bt_gap_phy_coding_2m_uncoded: app_log_info(THROUGHPUT_UI_PHY_2M_TEXT); break; - case sl_bt_gap_coded_phy_125k: + case sl_bt_gap_phy_coding_125k_coded: app_log_info(THROUGHPUT_UI_PHY_CODED_125K_TEXT); break; - case sl_bt_gap_coded_phy_500k: + case sl_bt_gap_phy_coding_500k_coded: app_log_info(THROUGHPUT_UI_PHY_CODED_500K_TEXT); break; default: @@ -1846,22 +1864,11 @@ void cli_throughput_central_phy_scan_set(sl_cli_command_arg_t *arguments) return; } uint8_t phy_scan; - sl_status_t sc; if (central_state.state != THROUGHPUT_STATE_TEST) { phy_scan = sl_cli_get_argument_uint8(arguments, 0); + central_state.scan_phy = (throughput_phy_t)phy_scan; throughput_central_scanning_restart(); - - // Set passive scanning on selected PHY - sc = sl_bt_scanner_set_mode(phy_scan, SCAN_PASSIVE); - if (sc == SL_STATUS_OK) { - central_state.scan_phy = (throughput_phy_t)phy_scan; - } - - if (sc == SL_STATUS_OK) { - CLI_RESPONSE(CLI_OK); - } else { - CLI_RESPONSE(CLI_ERROR); - } + CLI_RESPONSE(CLI_OK); } else { CLI_RESPONSE(CLI_ERROR); } diff --git a/app/bluetooth/common/throughput_peripheral/throughput_peripheral.c b/app/bluetooth/common/throughput_peripheral/throughput_peripheral.c index 3c5c77e644..cc0729dcd5 100644 --- a/app/bluetooth/common/throughput_peripheral/throughput_peripheral.c +++ b/app/bluetooth/common/throughput_peripheral/throughput_peripheral.c @@ -182,8 +182,8 @@ static bool notification_sent = false; static bool indication_confirmed = false; /// Power control status -static connection_power_reporting_mode_t power_control_enabled - = connection_power_reporting_disable; +static sl_bt_connection_power_reporting_mode_t power_control_enabled + = sl_bt_connection_power_reporting_disable; /// Requested notification data size static uint8_t requested_notification_size = @@ -314,7 +314,7 @@ static void throughput_peripheral_advertising_start(void) app_assert_status(sc); sc = sl_bt_legacy_advertiser_start(advertising_set_handle, - advertiser_connectable_scannable); + sl_bt_advertiser_connectable_scannable); app_assert_status(sc); #ifdef SL_CATALOG_BLUETOOTH_FEATURE_EXTENDED_ADVERTISER_PRESENT @@ -345,8 +345,8 @@ static void throughput_peripheral_advertising_start(void) // Set PHY for extended advertiser sc = sl_bt_extended_advertiser_set_phy(coded_advertising_set_handle, - sl_bt_gap_coded_phy, - sl_bt_gap_coded_phy); + sl_bt_gap_phy_coded, + sl_bt_gap_phy_coded); app_assert( (sc == SL_STATUS_OK) || (sc == SL_STATUS_INVALID_PARAMETER), "[E: 0x%04x] Failed to set CODED PHY for the advertistment\n", @@ -354,7 +354,7 @@ static void throughput_peripheral_advertising_start(void) if (sc == SL_STATUS_OK) { sc = sl_bt_extended_advertiser_start(coded_advertising_set_handle, - advertiser_connectable_non_scannable, + sl_bt_advertiser_connectable_non_scannable, SL_BT_EXTENDED_ADVERTISER_INCLUDE_TX_POWER); app_assert_status(sc); } @@ -829,7 +829,7 @@ void throughput_peripheral_enable(void) peripheral_state.mode = THROUGHPUT_PERIPHERAL_MODE_DEFAULT; peripheral_state.tx_power = THROUGHPUT_PERIPHERAL_TX_POWER; peripheral_state.rssi = 0; - peripheral_state.phy = sl_bt_gap_1m_phy_uncoded; + peripheral_state.phy = sl_bt_gap_phy_coding_1m_uncoded; peripheral_state.interval = 0; peripheral_state.pdu_size = 0; peripheral_state.mtu_size = THROUGHPUT_PERIPHERAL_MTU_SIZE; @@ -842,9 +842,9 @@ void throughput_peripheral_enable(void) peripheral_state.packet_lost = 0; if (THROUGHPUT_PERIPHERAL_TX_POWER_CONTROL_ENABLE) { - power_control_enabled = connection_power_reporting_enable; + power_control_enabled = sl_bt_connection_power_reporting_enable; } else { - power_control_enabled = connection_power_reporting_disable; + power_control_enabled = sl_bt_connection_power_reporting_disable; } // Convert power to mdBm @@ -1171,7 +1171,7 @@ void throughput_peripheral_on_bt_event(sl_bt_msg_t *evt) // Handle received data // Send confirmation if needed if (evt->data.evt_gatt_characteristic_value.characteristic == indications_handle) { - if (evt->data.evt_gatt_characteristic_value.att_opcode == gatt_handle_value_indication) { + if (evt->data.evt_gatt_characteristic_value.att_opcode == sl_bt_gatt_handle_value_indication) { sl_bt_gatt_send_characteristic_confirmation(evt->data.evt_gatt_characteristic_value.connection); } } @@ -1276,9 +1276,9 @@ sl_status_t throughput_peripheral_set_tx_power(throughput_tx_power_t tx_power, deep_sleep_enabled = deep_sleep; if (power_control) { - power_control_enabled = connection_power_reporting_enable; + power_control_enabled = sl_bt_connection_power_reporting_enable; } else { - power_control_enabled = connection_power_reporting_disable; + power_control_enabled = sl_bt_connection_power_reporting_disable; } // Reconnect if required diff --git a/app/bluetooth/common/throughput_ui/throughput_ui.c b/app/bluetooth/common/throughput_ui/throughput_ui.c index 98df118400..2617a635d1 100644 --- a/app/bluetooth/common/throughput_ui/throughput_ui.c +++ b/app/bluetooth/common/throughput_ui/throughput_ui.c @@ -258,19 +258,19 @@ void throughput_ui_set_phy(throughput_phy_t phy) { clear_row(ROW_PHY); switch (phy) { - case sl_bt_gap_1m_phy_uncoded: + case sl_bt_gap_phy_coding_1m_uncoded: write_row(THROUGHPUT_UI_PHY_1M_TEXT, ROW_PHY); LOG(THROUGHPUT_UI_PHY_1M_TEXT); break; - case sl_bt_gap_2m_phy_uncoded: + case sl_bt_gap_phy_coding_2m_uncoded: write_row(THROUGHPUT_UI_PHY_2M_TEXT, ROW_PHY); LOG(THROUGHPUT_UI_PHY_2M_TEXT); break; - case sl_bt_gap_coded_phy_125k: + case sl_bt_gap_phy_coding_125k_coded: write_row(THROUGHPUT_UI_PHY_CODED_125K_TEXT, ROW_PHY); LOG(THROUGHPUT_UI_PHY_CODED_125K_TEXT); break; - case sl_bt_gap_coded_phy_500k: + case sl_bt_gap_phy_coding_500k_coded: write_row(THROUGHPUT_UI_PHY_CODED_500K_TEXT, ROW_PHY); LOG(THROUGHPUT_UI_PHY_CODED_500K_TEXT); break; diff --git a/app/bluetooth/common/throughput_ui/throughput_ui.h b/app/bluetooth/common/throughput_ui/throughput_ui.h index 077ce55cff..249fba4137 100644 --- a/app/bluetooth/common/throughput_ui/throughput_ui.h +++ b/app/bluetooth/common/throughput_ui/throughput_ui.h @@ -120,9 +120,9 @@ void throughput_ui_set_data_size(throughput_data_size_t size); * Sets the PHY on UI. * * @param[in] phy can be either of - * - sl_bt_gap_1m_phy: 1M phy - * - sl_bt_gap_2m_phy: 2M phy - * - sl_bt_gap_coded_phy: Coded phy + * - sl_bt_gap_phy_coding_1m_uncoded: 1M phy + * - sl_bt_gap_phy_coding_2m_uncoded: 2M phy + * - sl_bt_gap_phy_coding_500k_coded: Coded phy *****************************************************************************/ void throughput_ui_set_phy(throughput_phy_t phy); diff --git a/app/bluetooth/common/throughput_ui/throughput_ui_log.c b/app/bluetooth/common/throughput_ui/throughput_ui_log.c index 065f207744..6ec8abcaab 100644 --- a/app/bluetooth/common/throughput_ui/throughput_ui_log.c +++ b/app/bluetooth/common/throughput_ui/throughput_ui_log.c @@ -149,19 +149,19 @@ static void refresh_ui(uint8_t refresh_row) break; case ROW_PHY: switch (ui_state.phy) { - case sl_bt_gap_1m_phy_uncoded: + case sl_bt_gap_phy_coding_1m_uncoded: UI_PRINTF(THROUGHPUT_UI_PHY_1M_TEXT); UI_PRINTBOX(" "); break; - case sl_bt_gap_2m_phy_uncoded: + case sl_bt_gap_phy_coding_2m_uncoded: UI_PRINTF(THROUGHPUT_UI_PHY_2M_TEXT); UI_PRINTBOX(" "); break; - case sl_bt_gap_coded_phy_125k: + case sl_bt_gap_phy_coding_125k_coded: UI_PRINTF(THROUGHPUT_UI_PHY_CODED_125K_TEXT); UI_PRINTBOX(" "); break; - case sl_bt_gap_coded_phy_500k: + case sl_bt_gap_phy_coding_500k_coded: UI_PRINTF(THROUGHPUT_UI_PHY_CODED_500K_TEXT); UI_PRINTBOX(" "); break; diff --git a/app/bluetooth/common_host/aoa_cte/cte_conn.c b/app/bluetooth/common_host/aoa_cte/cte_conn.c index 6200c60bb8..2729f4fe6c 100644 --- a/app/bluetooth/common_host/aoa_cte/cte_conn.c +++ b/app/bluetooth/common_host/aoa_cte/cte_conn.c @@ -69,19 +69,21 @@ sl_status_t cte_bt_on_event_conn(sl_bt_msg_t *evt) // Do not call any stack command before receiving this boot event! case sl_bt_evt_system_boot_id: // Set passive scanning on 1M PHY - sc = sl_bt_scanner_set_mode(sl_bt_gap_1m_phy, AOA_CTE_SCAN_MODE); + sc = sl_bt_scanner_set_mode(sl_bt_gap_phy_1m, AOA_CTE_SCAN_MODE); if (SL_STATUS_OK != sc) { break; } // Set scan interval and scan window - sc = sl_bt_scanner_set_timing(sl_bt_gap_1m_phy, AOA_CTE_SCAN_INTERVAL, AOA_CTE_SCAN_WINDOW); + sc = sl_bt_scanner_set_timing(sl_bt_gap_phy_1m, + AOA_CTE_SCAN_INTERVAL, + AOA_CTE_SCAN_WINDOW); if (SL_STATUS_OK != sc) { break; } // Start scanning - looking for tags - sc = sl_bt_scanner_start(sl_bt_gap_1m_phy, sl_bt_scanner_discover_generic); + sc = sl_bt_scanner_start(sl_bt_gap_phy_1m, sl_bt_scanner_discover_generic); if (SL_STATUS_OK != sc) { break; } @@ -131,7 +133,7 @@ sl_status_t cte_bt_on_event_conn(sl_bt_msg_t *evt) uint8_t conn_handle; sc = sl_bt_connection_open(evt->data.evt_scanner_scan_report.address, evt->data.evt_scanner_scan_report.address_type, - sl_bt_gap_1m_phy, + sl_bt_gap_phy_1m, &conn_handle); if (SL_STATUS_BT_CTRL_CONNECTION_LIMIT_EXCEEDED == sc) { app_log_warning("SL_BT_CONFIG_MAX_CONNECTIONS reached, stop scanning." APP_LOG_NL); @@ -252,7 +254,7 @@ sl_status_t cte_bt_on_event_conn(sl_bt_msg_t *evt) } // Restart the scanner to discover new tags. - sc = sl_bt_scanner_start(sl_bt_gap_1m_phy, sl_bt_scanner_discover_generic); + sc = sl_bt_scanner_start(sl_bt_gap_phy_1m, sl_bt_scanner_discover_generic); if (SL_STATUS_INVALID_STATE == sc) { // Scanning is already running, continue execution. sc = SL_STATUS_OK; @@ -274,7 +276,7 @@ sl_status_t cte_bt_on_event_conn(sl_bt_msg_t *evt) aoa_db_remove_tag((uint16_t)evt->data.evt_connection_closed.connection); // Restart the scanner to discover new tags - sc = sl_bt_scanner_start(sl_bt_gap_1m_phy, sl_bt_scanner_discover_generic); + sc = sl_bt_scanner_start(sl_bt_gap_phy_1m, sl_bt_scanner_discover_generic); if (SL_STATUS_INVALID_STATE == sc) { // Scanning is already running, continue execution. diff --git a/app/bluetooth/common_host/aoa_cte/cte_conn_less.c b/app/bluetooth/common_host/aoa_cte/cte_conn_less.c index 300577b0ab..53ba5847f5 100644 --- a/app/bluetooth/common_host/aoa_cte/cte_conn_less.c +++ b/app/bluetooth/common_host/aoa_cte/cte_conn_less.c @@ -55,19 +55,21 @@ sl_status_t cte_bt_on_event_conn_less(sl_bt_msg_t *evt) // Do not call any stack command before receiving this boot event! case sl_bt_evt_system_boot_id: // Set passive scanning on 1M PHY - sc = sl_bt_scanner_set_mode(sl_bt_gap_1m_phy, AOA_CTE_SCAN_MODE); + sc = sl_bt_scanner_set_mode(sl_bt_gap_phy_1m, AOA_CTE_SCAN_MODE); if (SL_STATUS_OK != sc) { break; } // Set scan interval and scan window - sc = sl_bt_scanner_set_timing(sl_bt_gap_1m_phy, AOA_CTE_SCAN_INTERVAL, AOA_CTE_SCAN_WINDOW); + sc = sl_bt_scanner_set_timing(sl_bt_gap_phy_1m, + AOA_CTE_SCAN_INTERVAL, + AOA_CTE_SCAN_WINDOW); if (SL_STATUS_OK != sc) { break; } // Start scanning - looking for tags - sc = sl_bt_scanner_start(sl_bt_gap_1m_phy, sl_bt_scanner_discover_generic); + sc = sl_bt_scanner_start(sl_bt_gap_phy_1m, sl_bt_scanner_discover_generic); break; // ------------------------------- @@ -151,7 +153,7 @@ sl_status_t cte_bt_on_event_conn_less(sl_bt_msg_t *evt) aoa_db_remove_tag(evt->data.evt_cte_receiver_connectionless_iq_report.sync); // Restart the scanner to discover new tags - sc = sl_bt_scanner_start(sl_bt_gap_1m_phy, sl_bt_scanner_discover_generic); + sc = sl_bt_scanner_start(sl_bt_gap_phy_1m, sl_bt_scanner_discover_generic); if (SL_STATUS_INVALID_STATE == sc) { // Scanning is already running, continue execution. diff --git a/app/bluetooth/common_host/aoa_cte/cte_silabs.c b/app/bluetooth/common_host/aoa_cte/cte_silabs.c index 354f009e66..6e9b5968ea 100644 --- a/app/bluetooth/common_host/aoa_cte/cte_silabs.c +++ b/app/bluetooth/common_host/aoa_cte/cte_silabs.c @@ -65,19 +65,21 @@ sl_status_t cte_bt_on_event_silabs(sl_bt_msg_t *evt) } // Set passive scanning on 1M PHY - sc = sl_bt_scanner_set_mode(sl_bt_gap_1m_phy, AOA_CTE_SCAN_MODE); + sc = sl_bt_scanner_set_mode(sl_bt_gap_phy_1m, AOA_CTE_SCAN_MODE); if (SL_STATUS_OK != sc) { break; } // Set scan interval and scan window - sc = sl_bt_scanner_set_timing(sl_bt_gap_1m_phy, AOA_CTE_SCAN_INTERVAL, AOA_CTE_SCAN_WINDOW); + sc = sl_bt_scanner_set_timing(sl_bt_gap_phy_1m, + AOA_CTE_SCAN_INTERVAL, + AOA_CTE_SCAN_WINDOW); if (SL_STATUS_OK != sc) { break; } // Start scanning - looking for tags - sc = sl_bt_scanner_start(sl_bt_gap_1m_phy, sl_bt_scanner_discover_generic); + sc = sl_bt_scanner_start(sl_bt_gap_phy_1m, sl_bt_scanner_discover_generic); if (SL_STATUS_OK != sc) { break; } diff --git a/app/bluetooth/common_host/aoa_loc/aoa_loc.c b/app/bluetooth/common_host/aoa_loc/aoa_loc.c index e4605ea042..daf2cbc930 100644 --- a/app/bluetooth/common_host/aoa_loc/aoa_loc.c +++ b/app/bluetooth/common_host/aoa_loc/aoa_loc.c @@ -76,7 +76,6 @@ static sl_status_t aoa_loc_run_estimation(aoa_asset_tag_t *tag, uint32_t angle_count, aoa_angle_t *angle_list, aoa_id_t *locator_list); -static void aoa_loc_destroy_locators(void); // ----------------------------------------------------------------------------- // Module variables @@ -419,24 +418,22 @@ sl_status_t aoa_loc_calc_position(aoa_id_t tag_id, } /**************************************************************************//** - * Destroy the module database + * Reinitialize the estimator. *****************************************************************************/ -void aoa_loc_destroy(void) +sl_status_t aoa_loc_reinit(void) { - aoa_loc_destroy_tags(); - aoa_loc_destroy_locators(); - sl_rtl_loc_deinit(&loc_libitem); + (void)aoa_loc_deinit(); + return aoa_loc_init(); } /**************************************************************************//** - * Reinitialize the estimator. + * Deinitialize the estimator. *****************************************************************************/ -sl_status_t aoa_loc_reinit(void) +sl_status_t aoa_loc_deinit(void) { - sl_rtl_loc_deinit(&loc_libitem); enum sl_rtl_error_code ec; - ec = sl_rtl_loc_init(&loc_libitem); + ec = sl_rtl_loc_deinit(&loc_libitem); CHECK_ERROR(ec); return SL_STATUS_OK; @@ -459,6 +456,22 @@ void aoa_loc_destroy_tags(void) head_tag = NULL; } +/**************************************************************************//** + * Destroy the locator database + *****************************************************************************/ +void aoa_loc_destroy_locators(void) +{ + aoa_locator_node_t *current; + aoa_locator_node_t *next; + + for (current = head_locator; current != NULL; current = next) { + next = current->next; + free(current); + } + + head_locator = NULL; +} + /**************************************************************************//** * Position ready callback. Weak, implement it in the application. *****************************************************************************/ @@ -692,19 +705,3 @@ static sl_status_t aoa_loc_run_estimation(aoa_asset_tag_t *tag, return SL_STATUS_OK; } - -/**************************************************************************//** - * Destroy the locator database - *****************************************************************************/ -static void aoa_loc_destroy_locators(void) -{ - aoa_locator_node_t *current; - aoa_locator_node_t *next; - - for (current = head_locator; current != NULL; current = next) { - next = current->next; - free(current); - } - - head_locator = NULL; -} diff --git a/app/bluetooth/common_host/aoa_loc/aoa_loc.h b/app/bluetooth/common_host/aoa_loc/aoa_loc.h index ca018a1f12..237c5a77cf 100644 --- a/app/bluetooth/common_host/aoa_loc/aoa_loc.h +++ b/app/bluetooth/common_host/aoa_loc/aoa_loc.h @@ -201,7 +201,7 @@ sl_status_t aoa_loc_get_tag_by_index(uint32_t index, * @param[in] locator_list Locator list. * * @retval SL_STATUS_FAIL - Position calculation failed in the RTL lib. - * @retval SL_STATUS_OK - Calculation was succesful. + * @retval SL_STATUS_OK - Calculation was successful. *****************************************************************************/ sl_status_t aoa_loc_calc_position(aoa_id_t tag_id, uint32_t angle_count, @@ -209,9 +209,9 @@ sl_status_t aoa_loc_calc_position(aoa_id_t tag_id, aoa_id_t *locator_list); /**************************************************************************//** - * Destroy the module database. + * Destroy the locator database. *****************************************************************************/ -void aoa_loc_destroy(void); +void aoa_loc_destroy_locators(void); /**************************************************************************//** * Destroy the tags database @@ -230,11 +230,21 @@ sl_status_t aoa_loc_remove_locator(aoa_id_t locator_id); /**************************************************************************//** * Reinitialize the estimator. * + * @deprecated Use the combination of aoa_loc_deinit and aoa_loc_init instead. + * * @retval SL_STATUS_FAIL - Reinitialization failed. - * @retval SL_STATUS_OK - Reinitialization was succesful. + * @retval SL_STATUS_OK - Reinitialization was successful. *****************************************************************************/ sl_status_t aoa_loc_reinit(void); +/**************************************************************************//** + * Deinitialize the estimator. + * + * @retval SL_STATUS_FAIL - Deinitialization failed. + * @retval SL_STATUS_OK - Deinitialization was successful. + *****************************************************************************/ +sl_status_t aoa_loc_deinit(void); + /**************************************************************************//** * Position ready callback. * diff --git a/app/bluetooth/common_host/aoa_parse/aoa_parse.c b/app/bluetooth/common_host/aoa_parse/aoa_parse.c index c8742848c3..2665efd2c5 100644 --- a/app/bluetooth/common_host/aoa_parse/aoa_parse.c +++ b/app/bluetooth/common_host/aoa_parse/aoa_parse.c @@ -121,7 +121,7 @@ sl_status_t aoa_parse_init(const char *config) sl_status_t aoa_parse_check_config_exist(char *config_name, aoa_id_t locator_id) { - cJSON *array; + cJSON *item; cJSON *locator; sl_status_t sc; @@ -133,8 +133,8 @@ sl_status_t aoa_parse_check_config_exist(char *config_name, } // Try parse locator specific config - array = cJSON_GetObjectItem(locator, config_name); - if (NULL == array) { + item = cJSON_GetObjectItem(locator, config_name); + if (item == NULL) { return SL_STATUS_NOT_FOUND; } @@ -354,6 +354,10 @@ sl_status_t aoa_parse_locator(aoa_id_t id, // Increment locator index. ++locator_index; + // Reset array indices. + allowlist_index = 0; + azimuth_mask_index = 0; + elevation_mask_index = 0; return SL_STATUS_OK; } @@ -595,6 +599,10 @@ static sl_status_t aoa_parse_find_locator_config(cJSON **locator, cJSON *item; uint32_t i = 0; + if (locator_id == NULL) { + return SL_STATUS_NULL_POINTER; + } + array = cJSON_GetObjectItem(root, "locators"); CHECK_TYPE(array, cJSON_Array); //Check if array of locator configs present diff --git a/app/bluetooth/common_host/aoa_util/aoa_topics.h b/app/bluetooth/common_host/aoa_util/aoa_topics.h index e1be7c59e0..e13de786b0 100644 --- a/app/bluetooth/common_host/aoa_util/aoa_topics.h +++ b/app/bluetooth/common_host/aoa_util/aoa_topics.h @@ -40,5 +40,7 @@ #define AOA_TOPIC_CORRECTION_PRINT "silabs/aoa/correction/%s/%s" #define AOA_TOPIC_CORRECTION_SCAN "silabs/aoa/correction/%64[^/]/%64[^/]" #define AOA_TOPIC_CONFIG_PRINT "silabs/aoa/config/%s" +#define AOA_TOPIC_CONFIG_SCAN "silabs/aoa/config/%64[^/]" +#define AOA_TOPIC_CONFIG_BROADCAST "silabs/aoa/config" #endif // AOA_TOPICS_H diff --git a/app/bluetooth/common_host/cpc/cpc.c b/app/bluetooth/common_host/cpc/cpc.c new file mode 100644 index 0000000000..f56a03728c --- /dev/null +++ b/app/bluetooth/common_host/cpc/cpc.c @@ -0,0 +1,255 @@ +/***************************************************************************//** + * @file + * @brief CPC communication through UART on POSIX platform + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_cpc.h" +#include "app_log.h" +#include +#include +#include +#include +#include +#include +#include +#include + +#define RETRY_COUNT 10 +#define CPC_RETRY_SLEEP_NS 100000000L +#define CPC_RESET_SLEEP_NS 10000L +#define CPC_TRANSMIT_WINDOW 1 +#define FROM_CPC_BUF_SIZE SL_CPC_READ_MINIMUM_SIZE + +// cpc related structures +static cpc_handle_t lib_handle; +static cpc_endpoint_t endpoint; + +// temporary rx buffer +typedef struct { + int32_t len; + uint8_t buf[FROM_CPC_BUF_SIZE]; +} buf_t; + +static buf_t buf_rx = { 0 }; + +static uint8_t handshake_msg[4] = { 0x20, 0x00, 0x01, 0x00 }; + +// end the receiving loop if signal is received. +static volatile bool run = true; +// signal if the controller was reset +static volatile bool has_reset = false; + +// two worker threads +static pthread_t sv; + +// Static receive function +static void *supervisor(void *ptr); + +// ----------------------------------------------------------------------------- +// Private Function Declaration + +static void reset_callback(void); + +// ----------------------------------------------------------------------------- +// Public Function Definitions + +int32_t cpc_open(void *handle, char *cpc_instance) +{ + int ret; + uint8_t retry = 0; + + // Initialize CPC communication + do { + ret = cpc_init(&lib_handle, cpc_instance, false, reset_callback); + if (ret == 0) { + // speed up boot process if everything seems ok + break; + } + nanosleep((const struct timespec[]){{ 0, CPC_RETRY_SLEEP_NS } }, NULL); + retry++; + } while ((ret != 0) && (retry < RETRY_COUNT)); + + if (ret < 0) { + perror("cpc_init: "); + return ret; + } + + // Start Bluetooth endpoint + ret = cpc_open_endpoint(lib_handle, + &endpoint, + SL_CPC_ENDPOINT_BLUETOOTH, + CPC_TRANSMIT_WINDOW); + if (ret < 0) { + perror("cpc_open_endpoint "); + return ret; + } + + // Create supervisory thread + ret = pthread_create(&sv, NULL, supervisor, NULL); + if (ret) { + perror("Couldn't create thread "); + return ret; + } + + handle = endpoint.ptr; + + // Send handshake msg + (void)cpc_write_endpoint(endpoint, &handshake_msg[0], 4, 0); + + // Discard response + (void)cpc_read_endpoint(endpoint, &buf_rx.buf, FROM_CPC_BUF_SIZE, 0); + buf_rx.len = 0; + memset(buf_rx.buf, 0, FROM_CPC_BUF_SIZE); + + return ret; +} + +int32_t cpc_tx(void *handle, uint32_t data_length, uint8_t *data) +{ + (void)handle; + ssize_t size = 0; + + if (!has_reset) { + size = cpc_write_endpoint(endpoint, &data[0], data_length, 0); + } else { + // In case of reset we don't care if send was succesfull or not + size = data_length; + } + + return (int32_t)size; +} + +int32_t cpc_rx(void *handle, uint32_t data_length, uint8_t *data) +{ + (void)handle; + + if (buf_rx.len > 0) { + memcpy(data, buf_rx.buf, buf_rx.len); + } + + return buf_rx.len; +} + +int32_t cpc_rx_peek(void *handle) +{ + (void)handle; + + if (!has_reset) { + // Make read blocking - possible because threaded structure in host_comm + buf_rx.len = (int32_t)cpc_read_endpoint(endpoint, &buf_rx.buf, + FROM_CPC_BUF_SIZE, 0); + } else { + // If in reset, don't try to read + buf_rx.len = 0; + } + if (buf_rx.len < 0) { + buf_rx.len = 0; + } + return buf_rx.len; +} + +int32_t cpc_close(void *handle) +{ + return cpc_close_endpoint(&endpoint); +} + +// ----------------------------------------------------------------------------- +// Public Function Definitions + +/**************************************************************************//** + * Callback to register reset from other end. + *****************************************************************************/ +static void reset_callback(void) +{ + has_reset = true; +} + +/**************************************************************************//** + * Reset CPC communication after other end restarted. + *****************************************************************************/ +int reset_cpc(void) +{ + int ret; + uint8_t retry = 0; + + app_log_debug("RESET" APP_LOG_NL); + + // Restart cpp communication + do { + ret = cpc_restart(&lib_handle); + if (ret == 0) { + // speed up boot process if everything seems ok + break; + } + nanosleep((const struct timespec[]){{ 0, CPC_RETRY_SLEEP_NS } }, NULL); + retry++; + } while ((ret != 0) && (retry < RETRY_COUNT)); + + if (ret < 0) { + perror("cpc restart "); + return ret; + } + + // Open Bluetooth endpoint + ret = cpc_open_endpoint(lib_handle, + &endpoint, + SL_CPC_ENDPOINT_BLUETOOTH, + CPC_TRANSMIT_WINDOW); + if (ret < 0) { + perror(" open endpoint "); + return ret; + } + + // Send handshake msg, but don't discard the answer, as upper layers need it. + cpc_write_endpoint(endpoint, &handshake_msg[0], 4, 0); + has_reset = false; + return ret; +} + +/**************************************************************************//** + * Supervisor thread + *****************************************************************************/ +void *supervisor(void *ptr) +{ + // unused variable + (void)ptr; + int ret; + + while (run) { + if (has_reset) { + ret = reset_cpc(); + if (ret < 0) { + perror("reset "); + // better to die here than continue to work falsely + exit(EXIT_FAILURE); + } + } + nanosleep((const struct timespec[]){{ 0, CPC_RESET_SLEEP_NS } }, NULL); + } + return NULL; +} diff --git a/app/bluetooth/common_host/cpc/cpc.h b/app/bluetooth/common_host/cpc/cpc.h new file mode 100644 index 0000000000..35b667e599 --- /dev/null +++ b/app/bluetooth/common_host/cpc/cpc.h @@ -0,0 +1,79 @@ +/***************************************************************************//** + * @file + * @brief CPC communication header file + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef CPC_H +#define CPC_H + +#include + +/**************************************************************************//** + * Open a CPC communication through CPCd. + * @param[out] handle eventually it's a socket handle + * @param[in] cpc_instance Instance name of CPCd + * @return 0 on success, -1 on failure. + *****************************************************************************/ +int32_t cpc_open(void *handle, char *cpc_instance); + +/**************************************************************************//** + * Send data to device through CPCd. The function will block until + * the desired amount has been written or an error occurs. + * @param[in] handle Socket handle + * @param[in] data_length The amount of bytes to write. + * @param[in] data Buffer used for storing the data. + * @return The amount of bytes written or -1 on failure. + *****************************************************************************/ +int32_t cpc_tx(void *handle, uint32_t data_length, uint8_t *data); + +/**************************************************************************//** + * Read data from device through CPCd. The function can be called only after + * cpc_rx_peak returned that there's data in the queue. + * @param[in] handle Socket handle + * @param[in] data_length The amount of bytes to read. + * @param[out] data Buffer used for storing the data. + * @return The amount of bytes read or -1 on failure. + *****************************************************************************/ +int32_t cpc_rx(void *handle, uint32_t data_length, uint8_t *data); + +/**************************************************************************//** + * Return the number of bytes in the input buffer. This call will block until + * there's data in the buffer. + * @param[in] handle Socket handle + * @return The number of bytes in the input buffer or -1 on failure. + *****************************************************************************/ +int32_t cpc_rx_peek(void *handle); + +/**************************************************************************//** + * Close the CPC connection. + * @param[in] handle Socket handle + * @return 0 on success, -1 on failure. + *****************************************************************************/ +int32_t cpc_close(void *handle); + +#endif // CPC_H diff --git a/app/bluetooth/common_host/host_comm/host_comm.c b/app/bluetooth/common_host/host_comm/host_comm.c index a3c5870a27..4460868712 100644 --- a/app/bluetooth/common_host/host_comm/host_comm.c +++ b/app/bluetooth/common_host/host_comm/host_comm.c @@ -43,6 +43,9 @@ #if defined(POSIX) && POSIX == 1 #include "named_socket.h" +#if defined (CPC) && CPC == 1 +#include "cpc.h" +#endif // defined (CPC) && CPC == 1 #else #include #endif // defined(POSIX) && POSIX == 1 @@ -52,9 +55,10 @@ #define DEFAULT_UART_BAUD_RATE 115200 #define DEFAULT_UART_FLOW_CONTROL 1 #define DEFAULT_UART_TIMEOUT 100 -#define DEFAUKT_TCP_ADDRESS "" +#define DEFAULT_TCP_ADDRESS "" #define DEFAULT_TCP_PORT "4901" #define MAX_OPT_LEN 255 +#define DEFAULT_CPC_INST_NAME "cpcd_0" #define IS_EMPTY_STRING(s) ((s)[0] == '\0') #define HANDLE_VALUE_MIN 0 @@ -79,11 +83,19 @@ static uint32_t uart_baud_rate = DEFAULT_UART_BAUD_RATE; static uint32_t uart_flow_control = DEFAULT_UART_FLOW_CONTROL; // TCP/IP address. -static char tcp_address[MAX_OPT_LEN] = DEFAUKT_TCP_ADDRESS; +static char tcp_address[MAX_OPT_LEN] = DEFAULT_TCP_ADDRESS; #if defined(POSIX) && POSIX == 1 // AF socket descriptor path static char named_socket_target_address[MAX_OPT_LEN]; +#if defined (CPC) && CPC == 1 +// CPCd instance name. +static char cpc_instance_name[MAX_OPT_LEN] = DEFAULT_CPC_INST_NAME; + +// CPC connection +static bool cpc_conn = false; +#endif // defined (CPC) && CPC == 1 + #endif // defined(POSIX) && POSIX == 1 #if defined(POSIX) && POSIX == 1 @@ -145,6 +157,15 @@ sl_status_t host_comm_init(void) app_log_critical("Connection to domain socket unsuccessful. Exiting.." APP_LOG_NL); exit(EXIT_FAILURE); } +#if defined (CPC) && CPC == 1 + } else if (cpc_conn) { + handle_ptr = &handle; + HOST_COMM_API_INITIALIZE_NONBLOCK(cpc_tx, cpc_rx, cpc_rx_peek); + if (cpc_open(handle_ptr, cpc_instance_name)) { + app_log_critical("Connection to CPCd unsuccessful. Exiting.." APP_LOG_NL); + exit(EXIT_FAILURE); + } +#endif // defined (CPC) && CPC == 1 #endif // defined(POSIX) && POSIX == 1 } else { app_log_error("Either UART serial port or TCP/IP address is mandatory." @@ -190,6 +211,13 @@ sl_status_t host_comm_set_option(char option, char *value) case 'n': strncpy(named_socket_target_address, value, MAX_OPT_LEN); break; +#if defined (CPC) && CPC == 1 + // CPC connection + case 'C': + strncpy(cpc_instance_name, value, MAX_OPT_LEN); + cpc_conn = true; + break; +#endif // defined (CPC) && CPC == 1 #endif // defined(POSIX) && POSIX == 1 // Unknown option. default: diff --git a/app/bluetooth/common_host/host_comm/host_comm.h b/app/bluetooth/common_host/host_comm/host_comm.h index 105d42aa7d..140a13ae81 100644 --- a/app/bluetooth/common_host/host_comm/host_comm.h +++ b/app/bluetooth/common_host/host_comm/host_comm.h @@ -33,6 +33,23 @@ #include "sl_status.h" +// Macros used by CPC +#if defined(POSIX) && POSIX == 1 && defined (CPC) && CPC == 1 +#define HOST_COMM_CPC_OPTSTRING "C:" + +// Usage info. +#define HOST_COMM_CPC_USAGE " | -C " + +// Options info. +#define HOST_COMM_CPC_OPTIONS \ + " -C CPC connection\n" \ + " Name of the CPCd instance to connect to.\n" +#else // defined(POSIX) && POSIX == 1 && defined (CPC) && CPC == 1 +#define HOST_COMM_CPC_OPTSTRING +#define HOST_COMM_CPC_USAGE +#define HOST_COMM_CPC_OPTIONS +#endif // defined(POSIX) && POSIX == 1 && defined (CPC) && CPC == 1 + // Macros used by Named Socket #if defined(POSIX) && POSIX == 1 #define CLIENT_PATH "client_unencrypted" @@ -54,10 +71,10 @@ #endif // defined(POSIX) && POSIX == 1 // Optstring argument for getopt. -#define HOST_COMM_OPTSTRING HOST_COMM_NS_OPTSTRING "t:u:b:f" +#define HOST_COMM_OPTSTRING HOST_COMM_NS_OPTSTRING HOST_COMM_CPC_OPTSTRING "t:u:b:f" // Usage info. -#define HOST_COMM_USAGE "-t | -u " HOST_COMM_NS_USAGE " [-b ] [-f]" +#define HOST_COMM_USAGE "-t | -u " HOST_COMM_NS_USAGE HOST_COMM_CPC_USAGE " [-b ] [-f]" // Options info. #define HOST_COMM_OPTIONS \ @@ -65,7 +82,7 @@ " TCP/IP address of the dev board.\n" \ " -u UART serial connection option.\n" \ " Serial port assigned to the dev board by the host system. (COM# on Windows, /dev/tty# on POSIX)\n" \ - HOST_COMM_NS_OPTIONS \ + HOST_COMM_NS_OPTIONS HOST_COMM_CPC_OPTIONS \ " -b Baud rate of the serial connection.\n" \ " Baud rate, default: 115200\n" \ " -f Disable flow control (RTS/CTS), default: enabled\n" \ diff --git a/app/bluetooth/common_host/mqtt/mqtt.c b/app/bluetooth/common_host/mqtt/mqtt.c index 6d3fa931e1..0eb1565a1f 100644 --- a/app/bluetooth/common_host/mqtt/mqtt.c +++ b/app/bluetooth/common_host/mqtt/mqtt.c @@ -45,7 +45,9 @@ #define QOS 1 #define KEEPALIVE_INTERVAL_SEC 30 #define LOOP_TIMEOUT_MS 1 -#define LOG_MASK MOSQ_LOG_NONE +#ifndef MQTT_LOG_MASK +#define MQTT_LOG_MASK MOSQ_LOG_NONE +#endif static void mqtt_on_connect(struct mosquitto *mosq, void *obj, int rc); static void mqtt_on_disconnect(struct mosquitto *mosq, void *obj, int rc); @@ -100,6 +102,9 @@ sl_status_t mqtt_init(mqtt_handle_t *handle) } else { handle->client = mosq; } + if (sc == SL_STATUS_OK) { + app_log_info("MQTT init client: %s" APP_LOG_NL, handle->client_id); + } return sc; } @@ -182,6 +187,9 @@ sl_status_t mqtt_subscribe(mqtt_handle_t *handle, const char *topic) } else { sc = SL_STATUS_NOT_INITIALIZED; } + if (sc == SL_STATUS_OK) { + app_log_info("MQTT subscribe: %s" APP_LOG_NL, topic); + } return sc; } @@ -199,7 +207,7 @@ sl_status_t mqtt_unsubscribe(mqtt_handle_t *handle, const char *topic) rc = mosquitto_unsubscribe(handle->client, NULL, topic); if ((rc != MOSQ_ERR_SUCCESS) && (rc != MOSQ_ERR_NO_CONN)) { - app_log_info("MQTT unsubscribe attempt failed from topic '%s': '%s'\n", + app_log_info("MQTT unsubscribe attempt failed from topic '%s': '%s'" APP_LOG_NL, topic, mqtt_err2str(rc)); sc = SL_STATUS_FAIL; @@ -208,12 +216,15 @@ sl_status_t mqtt_unsubscribe(mqtt_handle_t *handle, const char *topic) // Remove topic from topic list. sc = mqtt_remove_topic(handle, topic); if (SL_STATUS_OK != sc) { - app_log_info("MQTT failed to remove topic from topic list.\n"); + app_log_info("MQTT failed to remove topic from topic list." APP_LOG_NL); sc = SL_STATUS_FAIL; } } else { sc = SL_STATUS_NOT_INITIALIZED; } + if (sc == SL_STATUS_OK) { + app_log_info("MQTT unsubscribe: %s" APP_LOG_NL, topic); + } return sc; } @@ -335,7 +346,7 @@ static void mqtt_on_message(struct mosquitto *mosq, void *obj, const struct mosq static void mqtt_on_log(struct mosquitto *mosq, void *obj, int level, const char *str) { - if (level & LOG_MASK) { + if (level & MQTT_LOG_MASK) { app_log("MQTT log (%d): %s" APP_LOG_NL, level, str); } } diff --git a/app/bluetooth/component/bt_fp_ncp_default.slcc b/app/bluetooth/component/bt_fp_ncp_default.slcc index f7b4b49c5a..7e2eaea62a 100644 --- a/app/bluetooth/component/bt_fp_ncp_default.slcc +++ b/app/bluetooth/component/bt_fp_ncp_default.slcc @@ -17,7 +17,8 @@ requires: - name: bluetooth_feature_gatt - name: bluetooth_feature_gatt_server - name: bluetooth_feature_nvm - - name: bluetooth_feature_scanner + - name: bluetooth_feature_legacy_scanner + - name: bluetooth_feature_extended_scanner - name: bluetooth_feature_sm - name: bluetooth_feature_sync - name: bluetooth_feature_system diff --git a/app/bluetooth/component/bt_fp_soc_client.slcc b/app/bluetooth/component/bt_fp_soc_client.slcc index 0c660ac5bf..5095a82b44 100644 --- a/app/bluetooth/component/bt_fp_soc_client.slcc +++ b/app/bluetooth/component/bt_fp_soc_client.slcc @@ -11,7 +11,8 @@ requires: - name: gatt_configuration - name: bluetooth_feature_connection - name: bluetooth_feature_gatt - - name: bluetooth_feature_scanner + - name: bluetooth_feature_legacy_scanner + - name: bluetooth_feature_extended_scanner - name: bluetooth_feature_sm - name: bluetooth_feature_system ui_hints: diff --git a/app/bluetooth/component/bt_fp_soc_default.slcc b/app/bluetooth/component/bt_fp_soc_default.slcc index 678ca759ec..7efa73e0b5 100644 --- a/app/bluetooth/component/bt_fp_soc_default.slcc +++ b/app/bluetooth/component/bt_fp_soc_default.slcc @@ -14,7 +14,8 @@ requires: - name: bluetooth_feature_connection - name: bluetooth_feature_gatt - name: bluetooth_feature_gatt_server - - name: bluetooth_feature_scanner + - name: bluetooth_feature_legacy_scanner + - name: bluetooth_feature_extended_scanner - name: bluetooth_feature_sm - name: bluetooth_feature_system ui_hints: diff --git a/app/bluetooth/component/throughput_central.slcc b/app/bluetooth/component/throughput_central.slcc index cc3ee901b7..8772d6d081 100644 --- a/app/bluetooth/component/throughput_central.slcc +++ b/app/bluetooth/component/throughput_central.slcc @@ -27,10 +27,12 @@ requires: - name: "app_log" - name: "app_assert" - name: "bluetooth_stack" + - name: "bluetooth_feature_system" - name: "bluetooth_feature_afh" - name: "bluetooth_feature_power_control" - name: "bluetooth_feature_connection" - - name: "bluetooth_feature_scanner" + - name: "bluetooth_feature_legacy_scanner" + - name: "bluetooth_feature_extended_scanner" - name: "bluetooth_feature_gatt" - name: "power_manager" - name: "throughput" diff --git a/app/bluetooth/component/throughput_peripheral.slcc b/app/bluetooth/component/throughput_peripheral.slcc index a0458f51d7..f815dc17ce 100644 --- a/app/bluetooth/component/throughput_peripheral.slcc +++ b/app/bluetooth/component/throughput_peripheral.slcc @@ -26,6 +26,7 @@ requires: - name: app_assert - name: gatt_configuration - name: bluetooth_stack + - name: bluetooth_feature_system - name: bluetooth_feature_afh - name: bluetooth_feature_power_control - name: bluetooth_feature_connection diff --git a/app/bluetooth/component_host/ncp_host_bt.mk b/app/bluetooth/component_host/ncp_host_bt.mk index a1d199bdc2..2f8c2eae51 100644 --- a/app/bluetooth/component_host/ncp_host_bt.mk +++ b/app/bluetooth/component_host/ncp_host_bt.mk @@ -16,6 +16,21 @@ endif SECURITY ?= $(SECURITY_DEFAULT) +# CPC communication is disabled per default. +# It can be enabled by assigning a non-zero value to the CPC variable +# e.g. via command line like 'make CPC=1'. +# Be aware that CPC can only be enabled on Linux OS + +ifneq (, $(filter $(MAKECMDGOALS), export)) +# Collect CPC resources when exporting. +CPC_DEFAULT = 1 +else +CPC_DEFAULT = 0 +endif + +CPC ?= $(CPC_DEFAULT) +CPC_DIR ?= + override INCLUDEPATHS += \ $(SDK_DIR)/app/bluetooth/common_host/app_sleep \ $(SDK_DIR)/app/bluetooth/common_host/host_comm \ @@ -68,6 +83,33 @@ ifneq ($(SECURITY), 0) endif endif +# CPC related settings +ifneq ($(CPC), 0) + ifeq (, $(filter $(MAKECMDGOALS), export)) + ifeq ($(OS), win) + $(error CPC is not supported on Windows OS!) + endif + ifeq ($(UNAME), darwin) + $(error CPC is not supported on MacOS!) + endif + ifeq ($(CPC_DIR), ) + $(error Please set CPC library dir: CPC_DIR! e.g. /home/user/cpc) + endif + endif + override INCLUDEPATHS += $(SDK_DIR)/app/bluetooth/common_host/cpc + # CPCd is outside of GSDK. Therefore, add it directly as a compiler flag + # instead of adding it to INCLUDEPATHS. + override CFLAGS += -I"$(CPC_DIR)/daemon/lib" + + override C_SRC += $(SDK_DIR)/app/bluetooth/common_host/cpc/cpc.c + + LIBS += $(CPC_DIR)/daemon/build/libcpc.so + + override CFLAGS += -DCPC + + override LDFLAGS += -lpthread -lutil +endif + ifeq ($(OS), win) # Ws2_32: WinSock library override LDFLAGS += -lWs2_32 diff --git a/app/bluetooth/documentation/btmesh-release-highlights.txt b/app/bluetooth/documentation/btmesh-release-highlights.txt index 8195179f7d..014621f1dd 100644 --- a/app/bluetooth/documentation/btmesh-release-highlights.txt +++ b/app/bluetooth/documentation/btmesh-release-highlights.txt @@ -1,5 +1,2 @@ -Bluetooth Mesh SDK 3.0.0.0 -- Reduced project flash consumption by optimizing Mesh stack code size -- Support added for xGM240P PCB Modules and BG22/BGM220 Explorer Kits -- Support added for GCC version 10.3-2021.10 and IAR version 9.20.4 - +Bluetooth Mesh SDK 3.0.1.0 +- Targeted quality improvements and bug fixes \ No newline at end of file diff --git a/app/bluetooth/documentation/example/btmesh_ncp_empty/readme.md b/app/bluetooth/documentation/example/btmesh_ncp_empty/readme.md index 5e0f2b5f8e..ddfc6a7ed7 100644 --- a/app/bluetooth/documentation/example/btmesh_ncp_empty/readme.md +++ b/app/bluetooth/documentation/example/btmesh_ncp_empty/readme.md @@ -40,7 +40,7 @@ NCP Commander can be used to control the target and test NCP firmware without de ![step 3](readme_img6.png) -5. Once you have factory-reset the node, you can initialize the stack as a node by calling the initializing routine `sl_btmesh_node_init()`. In the API help menu, select the corresponding routine, copy it in the command field and send it. You can now see the device scanning. If you want to prevent the device scanning (as the display may be flooded with the scan response messages), you can also call `sl_bt_user_manage_event_filter(00 A0 00 05 01)` to block all the Bluetooth LE scan reports. This can be called even before the node initialization. +5. Once you have factory-reset the node, you can initialize the stack as a node by calling the initializing routine `sl_btmesh_node_init()`. In the API help menu, select the corresponding routine, copy it in the command field and send it. You can now see the device scanning. If you want to prevent the device scanning (as the display may be flooded with the scan response messages), you can also call `sl_bt_user_manage_event_filter(00 A0 00 05 00)`, `sl_bt_user_manage_event_filter(00 A0 00 05 01)` and `sl_bt_user_manage_event_filter(00 A0 00 05 02)` to block all the Bluetooth LE scan reports. This can be called even before the node initialization. ![step 3](readme_img7.png) diff --git a/app/bluetooth/documentation/example/ncp/readme.md b/app/bluetooth/documentation/example/ncp/readme.md index 01444d87aa..97614bd48d 100644 --- a/app/bluetooth/documentation/example/ncp/readme.md +++ b/app/bluetooth/documentation/example/ncp/readme.md @@ -4,6 +4,8 @@ This is a Network Co-Processor (NCP) target application. It runs the Bluetooth This example does not have a GATT database, but makes it possible to build one from the application using Dynamic GATT API. Use this example together with NCP host example applications. +> Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. + ## Getting Started To get started with Silicon Labs Bluetooth software and Simplicity Studio, see [QSG169: Bluetooth SDK v3.x Quick Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg169-bluetooth-sdk-v3x-quick-start-guide.pdf). @@ -45,23 +47,41 @@ This example project does not have a GATT database. It only contains the Generic ## Troubleshooting -Note that Software Example-based projects do not include a bootloader. However, they are configured to expect a bootloader to be present on the device. To get your application to work, either -- flash a bootloader to the device or -- uninstall the **Bootloader Application Interface** software component. +### Bootloader Issues + +Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either +- flash the proper bootloader or +- remove the DFU functionality from the project. + +**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. + +**If you want to add a bootloader**, then either +- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: + - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader + - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader + - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader + +- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. + - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. + - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. -To flash a bootloader, either create a bootloader project or run a precompiled **Demo** on your device from the Launcher view. Precompiled demos flash both bootloader and application images to the device. Then flash your own application image to overwrite the demo application but leave the bootloader in place. +**Important Notes:** +- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. -- To flash an OTA DFU-capable bootloader to the device, flash the **Bluetooth - SoC Thermometer** demo. -- To flash a UART DFU-capable bootloader to the device, flash the **Bluetooth - NCP** demo. -- For other bootloader types, create your own bootloader project and flash it to the device before flashing your application. -- When you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. - On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. -- For more information, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). -Before programming the radio board mounted on the mainboard, make sure the power supply switch the AEM position (right side) as shown below. +- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. + +For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). + + +### Programming the Radio Board + +Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. ![Radio board power supply switch](readme_img0.png) + ## Resources [Bluetooth Documentation](https://docs.silabs.com/bluetooth/latest/) diff --git a/app/bluetooth/documentation/example/ncp_aoa_locator/readme.md b/app/bluetooth/documentation/example/ncp_aoa_locator/readme.md index f69e6bbff4..1c07c67661 100644 --- a/app/bluetooth/documentation/example/ncp_aoa_locator/readme.md +++ b/app/bluetooth/documentation/example/ncp_aoa_locator/readme.md @@ -4,6 +4,8 @@ This is an NCP (Network Co-Processor) target example to be used together with th Use this example together with **SoC - AoA Asset Tag**, which can transmit CTE signals. +> Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. + ## Getting Started To get started with Silicon Labs Bluetooth software and Simplicity Studio, see [QSG169: Bluetooth SDK v3.x Quick-Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg169-bluetooth-sdk-v3x-quick-start-guide.pdf). @@ -46,23 +48,42 @@ After programming your antenna array board with the **NCP - AoA Locator** target Note that, when using **NCP - AoA Locator**, you may need to change the mainboard flow control settings. Follow the instructions of [AN1296: Application Development with Silicon Labs’ RTL Library](https://www.silabs.com/documents/public/application-notes/an1296-application-development-with-rtl-library.pdf). -Note that Software Example-based projects do not include a bootloader. However, they are configured to expect a bootloader to be present on the device. To get your application to work, either -- flash a bootloader to the device or -- uninstall the **Bootloader Application Interface** software component. +### Bootloader Issues + +Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either +- flash the proper bootloader or +- remove the DFU functionality from the project. + +**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. -To flash a bootloader, either create a bootloader project or run a precompiled **Demo** on your device from the Launcher view. Precompiled demos flash both bootloader and application images to the device. Then flash your own application image to overwrite the demo application but leave the bootloader in place. +**If you want to add a bootloader**, then either +- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: + - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader + - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader + - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader + +- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. + - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. + - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. + +**Important Notes:** +- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. -- To flash an OTA DFU-capable bootloader to the device, flash the **Bluetooth - SoC Thermometer** demo. -- To flash a UART DFU-capable bootloader to the device, flash the **Bluetooth - NCP** demo. -- For other bootloader types, create your own bootloader project and flash it to the device before flashing your application. -- When you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. - On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. -- For more information, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). -Before programming the radio board mounted on the mainboard, make sure the power supply switch the AEM position (right side), as shown below. +- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. + +For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). + + +### Programming the Radio Board + +Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. ![Radio board power supply switch](readme_img0.png) + + ## Resources [Bluetooth Documentation](https://docs.silabs.com/bluetooth/latest/) diff --git a/app/bluetooth/documentation/example/ncp_host/readme.md b/app/bluetooth/documentation/example/ncp_host/readme.md index c1d18a88e3..2566543095 100644 --- a/app/bluetooth/documentation/example/ncp_host/readme.md +++ b/app/bluetooth/documentation/example/ncp_host/readme.md @@ -4,6 +4,8 @@ This is a reference implementation of an NCP (Network Co-Processor) host, which This example uses the Dynamic GATT feature, and it must be used together with the **Bluetooth - NCP** target app. +> Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. + ## Getting Started To get started with Silicon Labs Bluetooth software and Simplicity Studio, see [QSG169: Bluetooth SDK v3.x Quick-Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg169-bluetooth-sdk-v3x-quick-start-guide.pdf). @@ -70,20 +72,40 @@ See the Bluetooth API reference manual section "GATT Database" for more details. ## Troubleshooting -Note that Software Example-based projects do not include a bootloader. However, they are configured to expect a bootloader to be present on the device. +### Bootloader Issues + +Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either +- flash the proper bootloader or +- remove the DFU functionality from the project. + +**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. + +**If you want to add a bootloader**, then either +- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: + - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader + - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader + - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader + +- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. + - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. + - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. -To flash a bootloader, either create a bootloader project or run a precompiled **Demo** on your device from the Launcher view. Precompiled demos flash both bootloader and application images to the device. Then flash your own application image to overwrite the demo application but leave the bootloader in place. +**Important Notes:** +- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. -- To flash an OTA DFU-capable bootloader to the device, flash the **Bluetooth - SoC Thermometer** demo. -- To flash a UART DFU-capable bootloader to the device, flash the **Bluetooth - NCP** demo. -- For other bootloader types, create your own bootloader project and flash it to the device before flashing your application. -- When you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. - On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. -- For more information, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). -Before programming the radio board mounted on the mainboard, make sure the power supply switch of the NCP host is in the AEM position (right side) as shown below, while the power supply switch of the NCP target board is in the BAT position. +- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. + +For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). + + +### Programming the Radio Board + +Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. + +![Radio board power supply switch](readme_img0.png) -![Radio Board Power Supply Switch](readme_img0.png) ## Resources diff --git a/app/bluetooth/documentation/example/rcp/readme.md b/app/bluetooth/documentation/example/rcp/readme.md index 8885e0c372..c509839cca 100644 --- a/app/bluetooth/documentation/example/rcp/readme.md +++ b/app/bluetooth/documentation/example/rcp/readme.md @@ -2,6 +2,8 @@ The RCP (Radio Co-Processor)) example application runs the Bluetooth Controller (radio + Link Layer) and implements the controller part of the HCI, as defined in the *Bluetooth Core Specification, Vol 4: Host Controller Interface*. The HCI is a standardized way for Bluetooth host and controller to communicate with each other. Because the interface is standard, the host and controller can be from different vendors. Currently, Silicon Labs Bluetooth Controller supports UART (Universal Asynchronous Receiver-Transmitter) as the HCI transport layer. +> Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. + ## Getting Started To get started with Silicon Labs Bluetooth and Simplicity Studio, see [QSG169: Bluetooth SDK v3.x Quick Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg169-bluetooth-sdk-v3x-quick-start-guide.pdf). @@ -51,23 +53,41 @@ Now, it can be controlled with any tool that uses HCI commands, e.g., *bluetooth ## Troubleshooting -Note that Software Example-based projects do not include a bootloader. However, they are configured to expect a bootloader to be present on the device. To get your application to work, either -- flash a bootloader to the device or -- uninstall the **Bootloader Application Interface** software component. +### Bootloader Issues + +Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either +- flash the proper bootloader or +- remove the DFU functionality from the project. + +**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. + +**If you want to add a bootloader**, then either +- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: + - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader + - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader + - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader + +- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. + - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. + - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. -To flash a bootloader, either create a bootloader project or run a precompiled **Demo** on your device from the Launcher view. Precompiled demos flash both bootloader and application images to the device. Then flash your own application image to overwrite the demo application but leave the bootloader in place. +**Important Notes:** +- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. -- To flash an OTA DFU-capable bootloader to the device, flash the **Bluetooth - SoC Thermometer** demo. -- To flash a UART DFU-capable bootloader to the device, flash the **Bluetooth - NCP** demo. -- For other bootloader types, create your own bootloader project and flash it to the device before flashing your application. -- When you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. - On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. -- For more information, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). -Before programming the radio board mounted on the mainboard, make sure the power supply switch the AEM position (right side) as shown below. +- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. + +For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). + + +### Programming the Radio Board + +Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. ![Radio board power supply switch](readme_img0.png) + ## Resources [Bluetooth Documentation](https://docs.silabs.com/bluetooth/latest/) diff --git a/app/bluetooth/documentation/example/rcp_cpc/readme.md b/app/bluetooth/documentation/example/rcp_cpc/readme.md index 8be6d43270..38a5d28322 100644 --- a/app/bluetooth/documentation/example/rcp_cpc/readme.md +++ b/app/bluetooth/documentation/example/rcp_cpc/readme.md @@ -2,6 +2,8 @@ The RCP (Radio Co-Processor) example application runs the Bluetooth Controller (radio + Link Layer) and implements the controller part of the HCI, as defined in the *Bluetooth Core Specification, Vol 4: Host Controller Interface*. The HCI is a standardized way for Bluetooth host and controller to communicate with each other. Because the interface is standard, the host and controller can be from different vendors. Currently, Silicon Labs Bluetooth Controller supports UART (Universal Asynchronous Receiver-Transmitter) as the HCI transport layer. In this project Silicon Labs’ proprietary CPC (Co-Processor Communication) protocol is used as the transport protocol over UART. +> Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. + ## Getting Started To get started with Silicon Labs Bluetooth and Simplicity Studio, see [QSG169: Bluetooth SDK v3.x Quick Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg169-bluetooth-sdk-v3x-quick-start-guide.pdf). @@ -36,20 +38,37 @@ For more information on CPC, refer to [AN1351: Using the Co-Processor Communicat ## Troubleshooting -Note that Software Example-based projects do not include a bootloader. However, they are configured to expect a bootloader to be present on the device. To get your application to work, either -- flash a bootloader to the device or -- uninstall the **Bootloader Application Interface** software component. +### Bootloader Issues + +Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either +- flash the proper bootloader or +- remove the DFU functionality from the project. + +**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. + +**If you want to add a bootloader**, then either +- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: + - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader + - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader + - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader + +- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. + - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. + - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. -To flash a bootloader, either create a bootloader project or run a precompiled **Demo** on your device from the Launcher view. Precompiled demos flash both bootloader and application images to the device. Then flash your own application image to overwrite the demo application but leave the bootloader in place. +**Important Notes:** +- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. -- To flash an OTA DFU-capable bootloader to the device, flash the **Bluetooth - SoC Thermometer** demo. -- To flash a UART DFU-capable bootloader to the device, flash the **Bluetooth - NCP** demo. -- For other bootloader types, create your own bootloader project and flash it to the device before flashing your application. -- When you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. - On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. -- For more information, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). -Before programming the radio board mounted on the mainboard, make sure the power supply switch the AEM position (right side) as shown below. +- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. + +For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). + + +### Programming the Radio Board + +Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. ![Radio board power supply switch](readme_img0.png) diff --git a/app/bluetooth/documentation/example/soc_aoa_asset_tag/readme.md b/app/bluetooth/documentation/example/soc_aoa_asset_tag/readme.md index c8ae449f47..0140bfe8c4 100644 --- a/app/bluetooth/documentation/example/soc_aoa_asset_tag/readme.md +++ b/app/bluetooth/documentation/example/soc_aoa_asset_tag/readme.md @@ -2,6 +2,8 @@ This example application demonstrates a CTE (Constant Tone Extension) transmitter that can be used as an asset tag in a direction finding setup estimating Angle of Arrival (AoA). Test this example with **NCP - AoA Locator**, which (when used together with the **aoa_locator host** applications) can estimate the direction of the asset tag. +> Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. + ## Getting Started To learn the basics of Bluetooth direction finding technology , see [UG103.18: Bluetooth Direction Finding Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-18-bluetooth-direction-finding-fundamentals.pdf). @@ -41,23 +43,41 @@ AoA Asset Tag can be tested together with an AoA Locator. After programming the ## Troubleshooting -Note that Software Example-based projects do not include a bootloader. However, they are configured to expect a bootloader to be present on the device. To get your application to work, either -- flash a bootloader to the device or -- uninstall the **OTA DFU** and **Bootloader Application Interface** software components. +### Bootloader Issues + +Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either +- flash the proper bootloader or +- remove the DFU functionality from the project. + +**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. + +**If you want to add a bootloader**, then either +- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: + - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader + - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader + - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader + +- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. + - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. + - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. -To flash a bootloader, either create a bootloader project or run a precompiled **Demo** on your device from the Launcher view. Precompiled demos flash both bootloader and application images to the device. Then flash your own application image to overwrite the demo application but leave the bootloader in place. +**Important Notes:** +- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. -- To flash an OTA DFU-capable bootloader to the device, flash the **Bluetooth - SoC Thermometer** demo. -- To flash a UART DFU-capable bootloader to the device, flash the **Bluetooth - NCP** demo. -- For other bootloader types, create your own bootloader project and flash it to the device before flashing your application. -- When you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. - On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. -- For more information, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). -Before programming the radio board mounted on the mainboard, make sure the power supply switch the AEM position (right side) as shown below. +- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. + +For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). + + +### Programming the Radio Board + +Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. ![Radio board power supply switch](readme_img0.png) + ## Resources [Bluetooth Documentation](https://docs.silabs.com/bluetooth/latest/) diff --git a/app/bluetooth/documentation/example/soc_app_ota_dfu/readme.md b/app/bluetooth/documentation/example/soc_app_ota_dfu/readme.md index e698a57687..8e41ba0972 100644 --- a/app/bluetooth/documentation/example/soc_app_ota_dfu/readme.md +++ b/app/bluetooth/documentation/example/soc_app_ota_dfu/readme.md @@ -2,6 +2,7 @@ This example project demonstrates the Application Over-the-Air Device Firmware Upgrade (OTA DFU) service, which unlocks firmware update during application runtime without resetting the device into 'OTA DFU mode' and without installing any application loader utility to the device. The downloaded firmware is stored in dedicated flash storage (slot 0). Once the download has finished, the bootloader is configured to update the firmware on the device. During the reboot session the new firmware is copied to the application space in the flash and the new application is loaded. + > Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. ## Getting Started @@ -66,20 +67,37 @@ This is a minimal example with the application OTA service that allows it to do ## Troubleshooting -Note that __NO__ Bootloader is included in any Software Example projects, but they are configured to expect a bootloader to be present on the device. To get your application to work, you should either -- flash a bootloader to the device or -- uninstall the **OTA DFU** and **Bootloader Application Interface** software components. +### Bootloader Issues -To flash a bootloader, you should either create a bootloader project or run a precompiled **Demo** on your device from the Launcher view. Precompiled Demos flash both bootloader and application images to your device. +Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either +- flash the proper bootloader or +- remove the DFU functionality from the project. -- To flash an OTA DFU-capable bootloader to your device, *SoC-Thermometer* demo can be flashed before your application to load the bootloader. -- To flash a UART DFU-capable bootloader to your device, *NCP* demo can be flashed before your application to load the bootloader. -- For your custom application, create your own bootloader project and flash it to your device before flashing your application. -- When you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. -- On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done in one step by flashing the **-combined.s37** file found in your bootloader project after building the project. -- For more information, see *[UG103: Bootloading fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf)*, *[UG266: Silicon Labs Gecko Bootloader User's Guide](https://www.silabs.com/documents/public/user-guides/ug266-gecko-bootloader-user-guide.pdf)* and *[UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://www.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf)*. +**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. -Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side), as shown below. +**If you want to add a bootloader**, then either +- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: + - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader + - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader + - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader + +- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. + - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. + - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. + +**Important Notes:** +- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. + +- On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. + +- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. + +For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). + + +### Programming the Radio Board + +Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. ![Radio board power supply switch](readme_img0.png) diff --git a/app/bluetooth/documentation/example/soc_blinky/readme.md b/app/bluetooth/documentation/example/soc_blinky/readme.md index 2c8322cbc9..ed22768224 100644 --- a/app/bluetooth/documentation/example/soc_blinky/readme.md +++ b/app/bluetooth/documentation/example/soc_blinky/readme.md @@ -2,6 +2,8 @@ This example application is the "Hello World" of Bluetooth Low Energy (BLE). It allows a BLE central device to control the LED on the mainboard and receive button press notifications. +> Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. + ## Getting started To get started with Silicon Labs Bluetooth and Simplicity Studio, see [QSG169: Bluetooth SDK v3.x Quick Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg169-bluetooth-sdk-v3x-quick-start-guide.pdf). @@ -24,23 +26,42 @@ The animation below showcases the demo running on a BGM220 Explorer Kit (BGM220- ## Troubleshooting -Note that Software Example-based projects do not include a bootloader. However, they are configured to expect a bootloader to be present on the device. To get your application to work, either -- flash a bootloader to the device or -- uninstall the **OTA DFU** and **Bootloader Application Interface** software components. +### Bootloader Issues + +Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either +- flash the proper bootloader or +- remove the DFU functionality from the project. + +**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. -To flash a bootloader, either create a bootloader project or run a precompiled **Demo** on your device from the Launcher view. Precompiled demos flash both bootloader and application images to the device. Then flash your own application image to overwrite the demo application but leave the bootloader in place. +**If you want to add a bootloader**, then either +- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: + - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader + - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader + - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader + +- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. + - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. + - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. + +**Important Notes:** +- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. -- To flash an OTA DFU-capable bootloader to the device, flash the **Bluetooth - SoC Thermometer** demo. -- To flash a UART DFU-capable bootloader to the device, flash the **Bluetooth - NCP** demo. -- For other bootloader types, create your own bootloader project and flash it to the device before flashing your application. -- When you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. - On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. -- For more information, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). -Before programming the radio board mounted on the mainboard, make sure the power supply switch the AEM position (right side) as shown below. +- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. + +For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). + + +### Programming the Radio Board + +Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. ![Radio board power supply switch](readme_img0.png) + + ## Resources [Bluetooth Documentation](https://docs.silabs.com/bluetooth/latest/) diff --git a/app/bluetooth/documentation/example/soc_cbap/readme.md b/app/bluetooth/documentation/example/soc_cbap/readme.md index 4575f04a6e..01ecd7abe1 100644 --- a/app/bluetooth/documentation/example/soc_cbap/readme.md +++ b/app/bluetooth/documentation/example/soc_cbap/readme.md @@ -2,6 +2,8 @@ This example application demonstrates how to create secure connections with trusted devices, where the trust between the devices is based on device certificates instead of some classical authentication method like numeric comparison or passkey entry. This method ensures authenticated connections without any user interaction. A signed device certificate must be present on the devices. +> Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. + ## Getting started To get started with Silicon Labs Bluetooth and Simplicity Studio, see [QSG169: Bluetooth® Quick-Start Guide for SDK v3.x and Higher](https://www.silabs.com/documents/public/quick-start-guides/qsg169-bluetooth-sdk-v3x-quick-start-guide.pdf). @@ -38,23 +40,41 @@ To test the example: ## Troubleshooting -Note that Software Example-based projects do not include a bootloader. However, they are configured to expect a bootloader to be present on the device. To get your application to work, either -- flash a bootloader to the device or -- uninstall the **OTA DFU** and **Bootloader Application Interface** software components. +### Bootloader Issues + +Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either +- flash the proper bootloader or +- remove the DFU functionality from the project. + +**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. + +**If you want to add a bootloader**, then either +- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: + - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader + - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader + - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader + +- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. + - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. + - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. -To flash a bootloader, either create a bootloader project or run a precompiled **Demo** on your device from the Launcher view. Precompiled demos flash both bootloader and application images to the device. Then flash your own application image to overwrite the demo application but leave the bootloader in place. +**Important Notes:** +- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. -- To flash an OTA DFU-capable bootloader to the device, flash the **Bluetooth - SoC Thermometer** demo. -- To flash a UART DFU-capable bootloader to the device, flash the **Bluetooth - NCP** demo. -- For other bootloader types, create your own bootloader project and flash it to the device before flashing your application. -- When you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. - On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. -- For more information, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). + +- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. + +For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). + + +### Programming the Radio Board Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. ![Radio board power supply switch](readme_img0.png) + ## Resources [Bluetooth Documentation](https://docs.silabs.com/bluetooth/latest/) diff --git a/app/bluetooth/documentation/example/soc_dtm/readme.md b/app/bluetooth/documentation/example/soc_dtm/readme.md index e311975419..1fd6b51629 100644 --- a/app/bluetooth/documentation/example/soc_dtm/readme.md +++ b/app/bluetooth/documentation/example/soc_dtm/readme.md @@ -2,6 +2,8 @@ This example application provides the Direct Test Mode (DTM) through a 2-wire UART interface for the RF PHY testing of a Bluetooth Low Energy device. +> Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. + ## Direct Test Mode (DTM) Overview DTM is typically used with a separate Bluetooth Tester device. @@ -46,23 +48,41 @@ Detailed specifications are in the Bluetooth Specifications. ## Troubleshooting -Note that Software Example-based projects do not include a bootloader. However, they are configured to expect a bootloader to be present on the device. To get your application to work, either -- flash a bootloader to the device or -- uninstall the **OTA DFU** and **Bootloader Application Interface** software components. +### Bootloader Issues + +Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either +- flash the proper bootloader or +- remove the DFU functionality from the project. + +**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. + +**If you want to add a bootloader**, then either +- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: + - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader + - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader + - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader + +- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. + - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. + - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. -To flash a bootloader, either create a bootloader project or run a precompiled **Demo** on your device from the Launcher view. Precompiled demos flash both bootloader and application images to the device. Then flash your own application image to overwrite the demo application but leave the bootloader in place. +**Important Notes:** +- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. -- To flash an OTA DFU-capable bootloader to the device, flash the **Bluetooth - SoC Thermometer** demo. -- To flash a UART DFU-capable bootloader to the device, flash the **Bluetooth - NCP** demo. -- For other bootloader types, create your own bootloader project and flash it to the device before flashing your application. -- When you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. - On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. -- For more information, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). -Before programming the radio board mounted on the mainboard, make sure the power supply switch the AEM position (right side) as shown below. +- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. + +For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). + + +### Programming the Radio Board + +Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. ![Radio board power supply switch](readme_img0.png) + **Note!** With the mainboard and the Radio Board, the DTM example uses EXP-header UART pins by default and not the USB UART as most of the other examples. Also, the default is no flow control. diff --git a/app/bluetooth/documentation/example/soc_empty/readme.md b/app/bluetooth/documentation/example/soc_empty/readme.md index d5e09bdd31..f32a03ba2a 100644 --- a/app/bluetooth/documentation/example/soc_empty/readme.md +++ b/app/bluetooth/documentation/example/soc_empty/readme.md @@ -2,6 +2,8 @@ The Bluetooth SoC-Empty example is a project that you can use as a template for any standalone Bluetooth application. +> Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. + ## Getting Started To learn the Bluetooth technology basics, see [UG103.14: Bluetooth LE Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-14-fundamentals-ble.pdf). @@ -60,23 +62,41 @@ As described above, an empty example does nothing except advertising and letting ## Troubleshooting -Note that Software Example-based projects do not include a bootloader. However, they are configured to expect a bootloader to be present on the device. To get your application to work, either -- flash a bootloader to the device or -- uninstall the **OTA DFU** and **Bootloader Application Interface** software components. +### Bootloader Issues + +Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either +- flash the proper bootloader or +- remove the DFU functionality from the project. + +**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. + +**If you want to add a bootloader**, then either +- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: + - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader + - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader + - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader + +- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. + - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. + - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. -To flash a bootloader, either create a bootloader project or run a precompiled **Demo** on your device from the Launcher view. Precompiled demos flash both bootloader and application images to the device. Then flash your own application image to overwrite the demo application but leave the bootloader in place. +**Important Notes:** +- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. -- To flash an OTA DFU-capable bootloader to the device, flash the **Bluetooth - SoC Thermometer** demo. -- To flash a UART DFU-capable bootloader to the device, flash the **Bluetooth - NCP** demo. -- For other bootloader types, create your own bootloader project and flash it to the device before flashing your application. -- When you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. - On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. -- For more information, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). -Before programming the radio board mounted on the mainboard, make sure the power supply switch the AEM position (right side) as shown below. +- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. + +For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). + + +### Programming the Radio Board + +Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. ![Radio board power supply switch](readme_img0.png) + ## Resources [Bluetooth Documentation](https://docs.silabs.com/bluetooth/latest/) diff --git a/app/bluetooth/documentation/example/soc_empty_rail_dmp/readme.md b/app/bluetooth/documentation/example/soc_empty_rail_dmp/readme.md index cf0161a742..b7003bda2a 100644 --- a/app/bluetooth/documentation/example/soc_empty_rail_dmp/readme.md +++ b/app/bluetooth/documentation/example/soc_empty_rail_dmp/readme.md @@ -2,6 +2,8 @@ This is a basic implementation of a Bluetooth and proprietary dynamic multiprotocol (DMP) application. It serves as a starting point for any DMP application development. +> Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. + ## Getting Started To get started with Silicon Labs Bluetooth and Simplicity Studio, see [QSG169: Bluetooth SDK v3.x Quick Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg169-bluetooth-sdk-v3x-quick-start-guide.pdf). @@ -58,23 +60,41 @@ You can implement additional application-specific tasks in *app.c*. You can crea ## Troubleshooting -Note that Software Example-based projects do not include a bootloader. However, they are configured to expect a bootloader to be present on the device. To get your application to work, either -- flash a bootloader to the device or -- uninstall the **OTA DFU** and **Bootloader Application Interface** software components. +### Bootloader Issues + +Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either +- flash the proper bootloader or +- remove the DFU functionality from the project. + +**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. + +**If you want to add a bootloader**, then either +- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: + - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader + - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader + - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader + +- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. + - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. + - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. -To flash a bootloader, either create a bootloader project or run a precompiled **Demo** on your device from the Launcher view. Precompiled demos flash both bootloader and application images to the device. Then flash your own application image to overwrite the demo application but leave the bootloader in place. +**Important Notes:** +- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. -- To flash an OTA DFU-capable bootloader to the device, flash the **Bluetooth - SoC Thermometer** demo. -- To flash a UART DFU-capable bootloader to the device, flash the **Bluetooth - NCP** demo. -- For other bootloader types, create your own bootloader project and flash it to the device before flashing your application. -- When you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. - On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. -- For more information, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). -Before programming the radio board mounted on the mainboard, make sure the power supply switch the AEM position (right side) as shown below. +- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. + +For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). + + +### Programming the Radio Board + +Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. ![Radio board power supply switch](readme_img0.png) + ## Resources [Bluetooth Documentation](https://docs.silabs.com/bluetooth/latest/) diff --git a/app/bluetooth/documentation/example/soc_empty_std_dmp/readme.md b/app/bluetooth/documentation/example/soc_empty_std_dmp/readme.md index 500302b4e4..eb31c2c9ae 100644 --- a/app/bluetooth/documentation/example/soc_empty_std_dmp/readme.md +++ b/app/bluetooth/documentation/example/soc_empty_std_dmp/readme.md @@ -4,6 +4,8 @@ This example application contains a basic implementation of a Bluetooth and prop Note: This DMP application uses a standard physical layer for the proprietary protocol, defined by the IEEE 802.15.4 standard, which cannot be changed. +> Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. + ## Getting Started To get started with Silicon Labs Bluetooth and Simplicity Studio, see [QSG169: Bluetooth SDK v3.x Quick Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg169-bluetooth-sdk-v3x-quick-start-guide.pdf). @@ -56,23 +58,41 @@ You can implement additional application-specific tasks in *app.c*. You can crea ## Troubleshooting -Note that Software Example-based projects do not include a bootloader. However, they are configured to expect a bootloader to be present on the device. To get your application to work, either -- flash a bootloader to the device or -- uninstall the **OTA DFU** and **Bootloader Application Interface** software components. +### Bootloader Issues + +Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either +- flash the proper bootloader or +- remove the DFU functionality from the project. + +**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. + +**If you want to add a bootloader**, then either +- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: + - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader + - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader + - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader + +- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. + - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. + - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. -To flash a bootloader, either create a bootloader project or run a precompiled **Demo** on your device from the Launcher view. Precompiled demos flash both bootloader and application images to the device. Then flash your own application image to overwrite the demo application but leave the bootloader in place. +**Important Notes:** +- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. -- To flash an OTA DFU-capable bootloader to the device, flash the **Bluetooth - SoC Thermometer** demo. -- To flash a UART DFU-capable bootloader to the device, flash the **Bluetooth - NCP** demo. -- For other bootloader types, create your own bootloader project and flash it to the device before flashing your application. -- When you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. - On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. -- For more information, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). -Before programming the radio board mounted on the mainboard, make sure the power supply switch the AEM position (right side) as shown below. +- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. + +For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). + + +### Programming the Radio Board + +Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. ![Radio board power supply switch](readme_img0.png) + ## Resources [Bluetooth Documentation](https://docs.silabs.com/bluetooth/latest/) diff --git a/app/bluetooth/documentation/example/soc_ibeacon/readme.md b/app/bluetooth/documentation/example/soc_ibeacon/readme.md index e69b33a7b7..fe1e7c6387 100644 --- a/app/bluetooth/documentation/example/soc_ibeacon/readme.md +++ b/app/bluetooth/documentation/example/soc_ibeacon/readme.md @@ -2,6 +2,8 @@ An iBeacon device is an implementation that sends non-connectable advertisements in iBeacon format. The iBeacon Service gives Bluetooth accessories a simple and convenient way to send iBeacon to smartphones. This example can be tested together with the EFR Connect mobile app. +> Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. + ## Getting Started Introduced in iOS 7, iBeacon enables new location awareness possibilities for apps. Leveraging Bluetooth Low Energy (BLE), a device with iBeacon technology can be used to establish a region around an object. This allows an iOS device to determine when it has entered or left the region, along with an estimation of proximity to a beacon. @@ -35,23 +37,41 @@ Follow these steps to set up the project: ## Troubleshooting -Note that Software Example-based projects do not include a bootloader. However, they are configured to expect a bootloader to be present on the device. To get your application to work, either -- flash a bootloader to the device or -- uninstall the **OTA DFU** and **Bootloader Application Interface** software components. +### Bootloader Issues + +Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either +- flash the proper bootloader or +- remove the DFU functionality from the project. + +**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. + +**If you want to add a bootloader**, then either +- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: + - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader + - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader + - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader + +- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. + - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. + - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. -To flash a bootloader, either create a bootloader project or run a precompiled **Demo** on your device from the Launcher view. Precompiled demos flash both bootloader and application images to the device. Then flash your own application image to overwrite the demo application but leave the bootloader in place. +**Important Notes:** +- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. -- To flash an OTA DFU-capable bootloader to the device, flash the **Bluetooth - SoC Thermometer** demo. -- To flash a UART DFU-capable bootloader to the device, flash the **Bluetooth - NCP** demo. -- For other bootloader types, create your own bootloader project and flash it to the device before flashing your application. -- When you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. - On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. -- For more information, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). -Before programming the radio board mounted on the mainboard, make sure the power supply switch the AEM position (right side) as shown below. +- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. + +For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). + + +### Programming the Radio Board + +Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. ![Radio board power supply switch](readme_img0.png) + ## Resources [Bluetooth Documentation](https://docs.silabs.com/bluetooth/latest/) diff --git a/app/bluetooth/documentation/example/soc_iop_test/readme.md b/app/bluetooth/documentation/example/soc_iop_test/readme.md index 657c989725..4742eb1ba1 100644 --- a/app/bluetooth/documentation/example/soc_iop_test/readme.md +++ b/app/bluetooth/documentation/example/soc_iop_test/readme.md @@ -4,6 +4,8 @@ Interoperability (IOP) is one of the key value propositions of Bluetooth Low Ene This readme describes the Silicon Labs IOP test framework, composed of hardware kits, embedded software, and a mobile app. It also explains the requirements for building the IOP test setup, running the test, and collecting data for further analysis. +> Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. + **Because some optional steps need to be taken before the IOP test starts, read this document before running the IOP test.** ## Introduction @@ -113,23 +115,41 @@ While UART logs have multiple COMPort emulators such as tera term, you can also ## Troubleshooting -Note that Software Example-based projects do not include a bootloader. However, they are configured to expect a bootloader to be present on the device. To get your application to work, either -- flash a bootloader to the device or -- uninstall the **OTA DFU** and **Bootloader Application Interface** software components. +### Bootloader Issues + +Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either +- flash the proper bootloader or +- remove the DFU functionality from the project. + +**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. + +**If you want to add a bootloader**, then either +- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: + - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader + - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader + - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader + +- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. + - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. + - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. -To flash a bootloader, either create a bootloader project or run a precompiled **Demo** on your device from the Launcher view. Precompiled demos flash both bootloader and application images to the device. Then flash your own application image to overwrite the demo application but leave the bootloader in place. +**Important Notes:** +- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. -- To flash an OTA DFU-capable bootloader to the device, flash the **Bluetooth - SoC Thermometer** demo. -- To flash a UART DFU-capable bootloader to the device, flash the **Bluetooth - NCP** demo. -- For other bootloader types, create your own bootloader project and flash it to the device before flashing your application. -- When you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. - On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. -- For more information, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). -Before programming the radio board mounted on the mainboard, make sure the power supply switch the AEM position (right side) as shown below. +- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. + +For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). + + +### Programming the Radio Board + +Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. ![Radio board power supply switch](readme_img0.png) + ## Resources [Bluetooth Documentation](https://docs.silabs.com/bluetooth/latest/) diff --git a/app/bluetooth/documentation/example/soc_light_rail_dmp/readme.md b/app/bluetooth/documentation/example/soc_light_rail_dmp/readme.md index 611966d0f2..b8d047e5e7 100644 --- a/app/bluetooth/documentation/example/soc_light_rail_dmp/readme.md +++ b/app/bluetooth/documentation/example/soc_light_rail_dmp/readme.md @@ -2,6 +2,8 @@ This is a Dynamic Multiprotocol reference application demonstrating a light bulb that can be switched both via Bluetooth and via a Proprietary protocol. To switch it via Bluetooth, use the EFR Connect smartphone app. To switch it via a Proprietary protocol, use the **Flex (RAIL) - Switch** example. +> Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. + ## Getting Started To get started with Silicon Labs Bluetooth and Simplicity Studio, see [QSG169: Bluetooth SDK v3.x Quick Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg169-bluetooth-sdk-v3x-quick-start-guide.pdf). @@ -99,23 +101,41 @@ The main logic of the demo application is implemented in `demo_app_task()` that ## Troubleshooting -Note that Software Example-based projects do not include a bootloader. However, they are configured to expect a bootloader to be present on the device. To get your application to work, either -- flash a bootloader to the device or -- uninstall the **OTA DFU** and **Bootloader Application Interface** software components. +### Bootloader Issues + +Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either +- flash the proper bootloader or +- remove the DFU functionality from the project. + +**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. + +**If you want to add a bootloader**, then either +- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: + - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader + - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader + - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader + +- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. + - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. + - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. -To flash a bootloader, either create a bootloader project or run a precompiled **Demo** on your device from the Launcher view. Precompiled demos flash both bootloader and application images to the device. Then flash your own application image to overwrite the demo application but leave the bootloader in place. +**Important Notes:** +- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. -- To flash an OTA DFU-capable bootloader to the device, flash the **Bluetooth - SoC Thermometer** demo. -- To flash a UART DFU-capable bootloader to the device, flash the **Bluetooth - NCP** demo. -- For other bootloader types, create your own bootloader project and flash it to the device before flashing your application. -- When you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. - On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. -- For more information, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). -Before programming the radio board mounted on the mainboard, make sure the power supply switch the AEM position (right side) as shown below. +- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. + +For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). + + +### Programming the Radio Board + +Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. ![Radio board power supply switch](readme_img0.png) + ## Resources [Bluetooth Documentation](https://docs.silabs.com/bluetooth/latest/) diff --git a/app/bluetooth/documentation/example/soc_light_std_dmp/readme.md b/app/bluetooth/documentation/example/soc_light_std_dmp/readme.md index a83a5be44c..439f8d305f 100644 --- a/app/bluetooth/documentation/example/soc_light_std_dmp/readme.md +++ b/app/bluetooth/documentation/example/soc_light_std_dmp/readme.md @@ -4,6 +4,8 @@ This is a Dynamic Multiprotocol reference application demonstrating a light bulb Note: This DMP application uses a standard physical layer for the proprietary protocol, defined by the IEEE 802.15.4 standard, which cannot be changed. +> Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. + ## Getting Started To get started with Silicon Labs Bluetooth and Simplicity Studio, see [QSG169: Bluetooth SDK v3.x Quick Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg169-bluetooth-sdk-v3x-quick-start-guide.pdf). @@ -97,23 +99,41 @@ The main logic of the demo application is implemented in `demo_app_task()` that ## Troubleshooting -Note that Software Example-based projects do not include a bootloader. However, they are configured to expect a bootloader to be present on the device. To get your application to work, either -- flash a bootloader to the device or -- uninstall the **OTA DFU** and **Bootloader Application Interface** software components. +### Bootloader Issues + +Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either +- flash the proper bootloader or +- remove the DFU functionality from the project. + +**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. + +**If you want to add a bootloader**, then either +- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: + - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader + - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader + - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader + +- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. + - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. + - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. -To flash a bootloader, either create a bootloader project or run a precompiled **Demo** on your device from the Launcher view. Precompiled demos flash both bootloader and application images to the device. Then flash your own application image to overwrite the demo application but leave the bootloader in place. +**Important Notes:** +- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. -- To flash an OTA DFU-capable bootloader to the device, flash the **Bluetooth - SoC Thermometer** demo. -- To flash a UART DFU-capable bootloader to the device, flash the **Bluetooth - NCP** demo. -- For other bootloader types, create your own bootloader project and flash it to the device before flashing your application. -- When you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. - On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. -- For more information, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). -Before programming the radio board mounted on the mainboard, make sure the power supply switch the AEM position (right side) as shown below. +- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. + +For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). + + +### Programming the Radio Board + +Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. ![Radio board power supply switch](readme_img0.png) + ## Resources [Bluetooth Documentation](https://docs.silabs.com/bluetooth/latest/) diff --git a/app/bluetooth/documentation/example/soc_thermometer/readme.md b/app/bluetooth/documentation/example/soc_thermometer/readme.md index 3d8bb61718..df4bcaccdf 100644 --- a/app/bluetooth/documentation/example/soc_thermometer/readme.md +++ b/app/bluetooth/documentation/example/soc_thermometer/readme.md @@ -2,6 +2,8 @@ This example implements the Health Thermometer service. It enables a peer device to connect and receive temperature values via Bluetooth. The reported values are measured by a temperature sensor located on the mainboard. +> Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. + ## Getting Started To get started with Silicon Labs Bluetooth and Simplicity Studio, see [QSG169: Bluetooth SDK v3.x Quick Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg169-bluetooth-sdk-v3x-quick-start-guide.pdf). @@ -43,23 +45,41 @@ Alternatively, you can follow the steps below instead of steps 3-5 to use the He ## Troubleshooting -Note that Software Example-based projects do not include a bootloader. However, they are configured to expect a bootloader to be present on the device. To get your application to work, either -- flash a bootloader to the device or -- uninstall the **OTA DFU** and **Bootloader Application Interface** software components. +### Bootloader Issues + +Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either +- flash the proper bootloader or +- remove the DFU functionality from the project. + +**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. + +**If you want to add a bootloader**, then either +- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: + - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader + - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader + - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader + +- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. + - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. + - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. -To flash a bootloader, either create a bootloader project or run a precompiled **Demo** on your device from the Launcher view. Precompiled demos flash both bootloader and application images to the device. Then flash your own application image to overwrite the demo application but leave the bootloader in place. +**Important Notes:** +- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. -- To flash an OTA DFU-capable bootloader to the device, flash the **Bluetooth - SoC Thermometer** demo. -- To flash a UART DFU-capable bootloader to the device, flash the **Bluetooth - NCP** demo. -- For other bootloader types, create your own bootloader project and flash it to the device before flashing your application. -- When you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. - On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. -- For more information, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). -Before programming the radio board mounted on the mainboard, make sure the power supply switch the AEM position (right side) as shown below. +- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. + +For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). + + +### Programming the Radio Board + +Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. ![Radio board power supply switch](readme_img0.png) + ## Resources [Bluetooth Documentation](https://docs.silabs.com/bluetooth/latest/) diff --git a/app/bluetooth/documentation/example/soc_thermometer_client/readme.md b/app/bluetooth/documentation/example/soc_thermometer_client/readme.md index e2a10f35c5..ce1bdd9c82 100644 --- a/app/bluetooth/documentation/example/soc_thermometer_client/readme.md +++ b/app/bluetooth/documentation/example/soc_thermometer_client/readme.md @@ -2,6 +2,8 @@ This example demonstrates the operation of a client device in a multi-peripheral Bluetooth LE (BLE) topology. The Silicon Labs Bluetooth stack supports simultaneous connections for up to eight peripheral devices at one time. This example application illustrates how to handle simultaneous connection to four thermometer peripheral devices. +> Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. + ## Getting Started To get started with Silicon Labs Bluetooth and Simplicity Studio, see [QSG169: Bluetooth SDK v3.x Quick Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg169-bluetooth-sdk-v3x-quick-start-guide.pdf). @@ -32,23 +34,41 @@ After programming the devices, open your terminal emulator and connect to your c ## Troubleshooting -Note that Software Example-based projects do not include a bootloader. However, they are configured to expect a bootloader to be present on the device. To get your application to work, either -- flash a bootloader to the device or -- uninstall the **OTA DFU** and **Bootloader Application Interface** software components. +### Bootloader Issues + +Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either +- flash the proper bootloader or +- remove the DFU functionality from the project. + +**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. + +**If you want to add a bootloader**, then either +- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: + - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader + - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader + - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader + +- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. + - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. + - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. -To flash a bootloader, either create a bootloader project or run a precompiled **Demo** on your device from the Launcher view. Precompiled demos flash both bootloader and application images to the device. Then flash your own application image to overwrite the demo application but leave the bootloader in place. +**Important Notes:** +- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. -- To flash an OTA DFU-capable bootloader to the device, flash the **Bluetooth - SoC Thermometer** demo. -- To flash a UART DFU-capable bootloader to the device, flash the **Bluetooth - NCP** demo. -- For other bootloader types, create your own bootloader project and flash it to the device before flashing your application. -- When you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. - On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. -- For more information, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). -Before programming the radio board mounted on the mainboard, make sure the power supply switch the AEM position (right side) as shown below. +- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. + +For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). + + +### Programming the Radio Board + +Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. ![Radio board power supply switch](readme_img0.png) + ## Resources [Bluetooth Documentation](https://docs.silabs.com/bluetooth/latest/) diff --git a/app/bluetooth/documentation/example/soc_thermometer_rtos/readme.md b/app/bluetooth/documentation/example/soc_thermometer_rtos/readme.md index 5c995b7992..a7af1f33aa 100644 --- a/app/bluetooth/documentation/example/soc_thermometer_rtos/readme.md +++ b/app/bluetooth/documentation/example/soc_thermometer_rtos/readme.md @@ -2,6 +2,8 @@ This example application demonstrates the integration of a Real Time Operating System (RTOS) into Bluetooth applications. RTOS is added to the **Bluetooth - SoC Thermometer** example. +> Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. + ## Getting Started To get started with Silicon Labs Bluetooth and Simplicity Studio, see [QSG169: Bluetooth SDK v3.x Quick Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg169-bluetooth-sdk-v3x-quick-start-guide.pdf). @@ -20,23 +22,41 @@ To learn more about RTOS integration into Bluetooth projects, see [AN1260: Integ ## Troubleshooting -Note that Software Example-based projects do not include a bootloader. However, they are configured to expect a bootloader to be present on the device. To get your application to work, either -- flash a bootloader to the device or -- uninstall the **OTA DFU** and **Bootloader Application Interface** software components. +### Bootloader Issues + +Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either +- flash the proper bootloader or +- remove the DFU functionality from the project. + +**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. + +**If you want to add a bootloader**, then either +- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: + - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader + - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader + - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader + +- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. + - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. + - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. -To flash a bootloader, either create a bootloader project or run a precompiled **Demo** on your device from the Launcher view. Precompiled demos flash both bootloader and application images to the device. Then flash your own application image to overwrite the demo application but leave the bootloader in place. +**Important Notes:** +- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. -- To flash an OTA DFU-capable bootloader to the device, flash the **Bluetooth - SoC Thermometer** demo. -- To flash a UART DFU-capable bootloader to the device, flash the **Bluetooth - NCP** demo. -- For other bootloader types, create your own bootloader project and flash it to the device before flashing your application. -- When you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. - On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. -- For more information, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). -Before programming the radio board mounted on the mainboard, make sure the power supply switch the AEM position (right side) as shown below. +- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. + +For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). + + +### Programming the Radio Board + +Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. ![Radio board power supply switch](readme_img0.png) + ## Resources [Bluetooth Documentation](https://docs.silabs.com/bluetooth/latest/) diff --git a/app/bluetooth/documentation/example/soc_throughput/readme.md b/app/bluetooth/documentation/example/soc_throughput/readme.md index 96fb0ac4fc..b9d0066e6e 100644 --- a/app/bluetooth/documentation/example/soc_throughput/readme.md +++ b/app/bluetooth/documentation/example/soc_throughput/readme.md @@ -2,6 +2,8 @@ This example allows measuring data throughput between EFR32 devices as well as between an EFR32 and a smartphone running the EFR Connect mobile app. +> Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. + ## Getting started To get started with Silicon Labs Bluetooth and Simplicity Studio, see [QSG169: Bluetooth SDK v3.x Quick Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg169-bluetooth-sdk-v3x-quick-start-guide.pdf). @@ -86,23 +88,41 @@ On devices without display, the CLI is used for printing a virtual display which ## Troubleshooting -Note that Software Example-based projects do not include a bootloader. However, they are configured to expect a bootloader to be present on the device. To get your application to work, either -- flash a bootloader to the device or -- uninstall the **OTA DFU** and **Bootloader Application Interface** software components. +### Bootloader Issues + +Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either +- flash the proper bootloader or +- remove the DFU functionality from the project. + +**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. + +**If you want to add a bootloader**, then either +- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: + - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader + - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader + - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader + +- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. + - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. + - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. -To flash a bootloader, either create a bootloader project or run a precompiled **Demo** on your device from the Launcher view. Precompiled demos flash both bootloader and application images to the device. Then flash your own application image to overwrite the demo application but leave the bootloader in place. +**Important Notes:** +- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. -- To flash an OTA DFU-capable bootloader to the device, flash the **Bluetooth - SoC Thermometer** demo. -- To flash a UART DFU-capable bootloader to the device, flash the **Bluetooth - NCP** demo. -- For other bootloader types, create your own bootloader project and flash it to the device before flashing your application. -- When you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. - On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. -- For more information, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). -Before programming the radio board mounted on the mainboard, make sure the power supply switch the AEM position (right side) as shown below. +- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. + +For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). + + +### Programming the Radio Board + +Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. ![Radio board power supply switch](readme_img0.png) + ## Resources [Bluetooth Documentation](https://docs.silabs.com/bluetooth/latest/) diff --git a/app/bluetooth/documentation/example/soc_thunderboard/readme.md b/app/bluetooth/documentation/example/soc_thunderboard/readme.md index 9c8da4106e..169bd87866 100644 --- a/app/bluetooth/documentation/example/soc_thunderboard/readme.md +++ b/app/bluetooth/documentation/example/soc_thunderboard/readme.md @@ -2,6 +2,8 @@ This example collects and processes sensor data from the Thunderboard Sense 2 or the Thunderboard EFR32BG22 board, and gives immediate graphical feedback through the Thunderboard iOS/Android application. +> Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. + ## Getting Started To get started with Silicon Labs Bluetooth and Simplicity Studio, see [QSG169: Bluetooth SDK v3.x Quick Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg169-bluetooth-sdk-v3x-quick-start-guide.pdf). @@ -49,23 +51,41 @@ Additional functionality can be added to the empty app_process_action function. ## Troubleshooting -Note that Software Example-based projects do not include a bootloader. However, they are configured to expect a bootloader to be present on the device. To get your application to work, either -- flash a bootloader to the device or -- uninstall the **OTA DFU** and **Bootloader Application Interface** software components. +### Bootloader Issues + +Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either +- flash the proper bootloader or +- remove the DFU functionality from the project. + +**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. + +**If you want to add a bootloader**, then either +- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: + - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader + - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader + - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader + +- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. + - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. + - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. -To flash a bootloader, either create a bootloader project or run a precompiled **Demo** on your device from the Launcher view. Precompiled demos flash both bootloader and application images to the device. Then flash your own application image to overwrite the demo application but leave the bootloader in place. +**Important Notes:** +- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. -- To flash an OTA DFU-capable bootloader to the device, flash the **Bluetooth - SoC Thermometer** demo. -- To flash a UART DFU-capable bootloader to the device, flash the **Bluetooth - NCP** demo. -- For other bootloader types, create your own bootloader project and flash it to the device before flashing your application. -- When you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. - On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. -- For more information, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). -Before programming the radio board mounted on the mainboard, make sure the power supply switch the AEM position (right side) as shown below. +- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. + +For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). + + +### Programming the Radio Board + +Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. ![Radio board power supply switch](readme_img0.png) + ## Resources [Bluetooth Documentation](https://docs.silabs.com/bluetooth/latest/) diff --git a/app/bluetooth/documentation/example/soc_voice/readme.md b/app/bluetooth/documentation/example/soc_voice/readme.md index 3f96e6d99c..a51c17eab5 100644 --- a/app/bluetooth/documentation/example/soc_voice/readme.md +++ b/app/bluetooth/documentation/example/soc_voice/readme.md @@ -2,6 +2,8 @@ This is a Voice over Bluetooth Low Energy example. It is supported by a Thunderboard Sense 2 board and demonstrates how to send voice data over GATT, which is acquired from the on-board microphone. +> Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. + ## Getting started To get started with Silicon Labs Bluetooth and Simplicity Studio, see [QSG169: Bluetooth SDK v3.x Quick Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg169-bluetooth-sdk-v3x-quick-start-guide.pdf). @@ -81,23 +83,41 @@ The handling of the microphone, the encoding, buffering and filtering can be fou ## Troubleshooting -Note that Software Example-based projects do not include a bootloader. However, they are configured to expect a bootloader to be present on the device. To get your application to work, either -- flash a bootloader to the device or -- uninstall the **OTA DFU** and **Bootloader Application Interface** software components. +### Bootloader Issues + +Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either +- flash the proper bootloader or +- remove the DFU functionality from the project. + +**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. + +**If you want to add a bootloader**, then either +- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: + - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader + - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader + - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader + +- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. + - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. + - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. -To flash a bootloader, either create a bootloader project or run a precompiled **Demo** on your device from the Launcher view. Precompiled demos flash both bootloader and application images to the device. Then flash your own application image to overwrite the demo application but leave the bootloader in place. +**Important Notes:** +- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. -- To flash an OTA DFU-capable bootloader to the device, flash the **Bluetooth - SoC Thermometer** demo. -- To flash a UART DFU-capable bootloader to the device, flash the **Bluetooth - NCP** demo. -- For other bootloader types, create your own bootloader project and flash it to the device before flashing your application. -- When you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. - On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. -- For more information, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). -Before programming the radio board mounted on the mainboard, make sure the power supply switch the AEM position (right side) as shown below. +- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. + +For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). + + +### Programming the Radio Board + +Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. ![Radio board power supply switch](readme_img0.png) + ## Resources [Bluetooth Documentation](https://docs.silabs.com/bluetooth/latest/) diff --git a/app/bluetooth/documentation/slBluetooth_docContent.xml b/app/bluetooth/documentation/slBluetooth_docContent.xml index 442a330286..41dcc3aba6 100644 --- a/app/bluetooth/documentation/slBluetooth_docContent.xml +++ b/app/bluetooth/documentation/slBluetooth_docContent.xml @@ -1,373 +1,373 @@ - - + + + Includes detailed information on using the Gecko Bootloader with Silicon Labs Bluetooth applications. It supplements the general Gecko Bootloader implementation information provided in UG489: Silicon Labs Gecko Bootloader User's Guide. - Includes detailed information on using the Gecko Bootloader with Silicon Labs Bluetooth applications. It supplements the general Gecko Bootloader implementation information provided in UG489: Silicon Labs Gecko Bootloader User's Guide. - + + Describes the Wi-Fi impact on Bluetooth and methods to improve Bluetooth coexistence with Wi-Fi. Explains design considerations to improve coexistence without direct interaction between Bluetooth and Wi-Fi radios. These techniques are applicable to the EFR32MGx and EFR32BGx series. Discusses the Silicon Labs Packet Traffic Arbitration (PTA) support to coordinate 2.4GHz RF traffic for co-located Bluetooth and Wi-Fi radios. - Describes the Wi-Fi impact on Bluetooth and methods to improve Bluetooth coexistence with Wi-Fi. Explains design considerations to improve coexistence without direct interaction between Bluetooth and Wi-Fi radios. These techniques are applicable to the EFR32MGx and EFR32BGx series. Discusses the Silicon Labs Packet Traffic Arbitration (PTA) support to coordinate 2.4GHz RF traffic for co-located Bluetooth and Wi-Fi radios. - + + Explains how NVM3 can be used as non-volatile data storage in various protocol implementations. - Explains how NVM3 can be used as non-volatile data storage in various protocol implementations. - + + Describes how to lock and unlock the debug access of EFR32 Gecko Series 2 devices. Many aspects of the debug access, including the secure debug unlock are described. The Debug Challenge Interface (DCI) and Secure Engine (SE) Mailbox Interface for locking and unlocking debug access are also included. - Describes how to lock and unlock the debug access of EFR32 Gecko Series 2 devices. Many aspects of the debug access, including the secure debug unlock are described. The Debug Challenge Interface (DCI) and Secure Engine (SE) Mailbox Interface for locking and unlocking debug access are also included. - + + Contains detailed information on configuring and using the Secure Boot with hardware Root of Trust and Secure Loader on Series 2 devices, including how to provision the signing key. This is a companion document to UG489: Silicon Labs Gecko Bootloader User's Guide. - Contains detailed information on configuring and using the Secure Boot with hardware Root of Trust and Secure Loader on Series 2 devices, including how to provision the signing key. This is a companion document to UG489: Silicon Labs Gecko Bootloader User's Guide. - + + Details on programming, provisioning, and configuring Series 2 devices in production environments. Covers Secure Engine Subsystem of Series 2 devices, which runs easily upgradeable Secure Engine (SE) or Virtual Secure Engine (VSE) firmware. - Details on programming, provisioning, and configuring Series 2 devices in production environments. Covers Secure Engine Subsystem of Series 2 devices, which runs easily upgradeable Secure Engine (SE) or Virtual Secure Engine (VSE) firmware. - + + Describes how to measure the power consumption of EFR32BG devices running the Bluetooth i-Beacon example. For general instructions, see AN969: Measuring Power Consumption in Wireless Gecko Devices, available on silabs.com. - Describes how to measure the power consumption of EFR32BG devices running the Bluetooth i-Beacon example. For general instructions, see AN969: Measuring Power Consumption in Wireless Gecko Devices, available on silabs.com. - + + How to program, provision, and configure the anti-tamper module on EFR32 Series 2 devices with Secure Vault. - How to program, provision, and configure the anti-tamper module on EFR32 Series 2 devices with Secure Vault. - + + Describes how to configure the NCP target and how to program the NCP host when using the Bluetooth Stack in Network Co-Processor mode - Describes how to configure the NCP target and how to program the NCP host when using the Bluetooth Stack in Network Co-Processor mode - + + Describes how to integrate a v3.x Silicon Labs Bluetooth application with an RTOS, and demonstrate how a time- and event-driven application can be run in parallel with the Bluetooth stack. - Describes how to integrate a v3.x Silicon Labs Bluetooth application with an RTOS, and demonstrate how a time- and event-driven application can be run in parallel with the Bluetooth stack. - + + Reviews performing radio frequency physical layer evaluation with EFR32BG SoCs and BGM modules using the Direct Test Mode protocol in Bluetooth SDK v3.x. - Reviews performing radio frequency physical layer evaluation with EFR32BG SoCs and BGM modules using the Direct Test Mode protocol in Bluetooth SDK v3.x. - + + How to authenticate an EFR32 Series 2 device with Secure Vault, using secure device certificates and signatures. - How to authenticate an EFR32 Series 2 device with Secure Vault, using secure device certificates and signatures. - + + Provides details on how to develop a dynamic multiprotocol application running Bluetooth and a proprietary protocol on RAIL in GSDK v3.x. - Provides details on how to develop a dynamic multiprotocol application running Bluetooth and a proprietary protocol on RAIL in GSDK v3.x. - + + How to securely "wrap" keys in EFR32 Series 2 devices with Secure Vault, so they can be stored in non-volatile storage. - How to securely "wrap" keys in EFR32 Series 2 devices with Secure Vault, so they can be stored in non-volatile storage. - + + Describes the sample applications provided to demonstrate the directing finding capabilities of Bluetooth 5.1. Angle of Arrival (AoA) estimation is demonstrated with the use of Silicon Labs' Real Time Locating (RTL) library. These techniques are applicable to the EFR32MGx and EFR32BGx series. - Describes the sample applications provided to demonstrate the directing finding capabilities of Bluetooth 5.1. Angle of Arrival (AoA) estimation is demonstrated with the use of Silicon Labs' Real Time Locating (RTL) library. These techniques are applicable to the EFR32MGx and EFR32BGx series. - + + Bluetooth 5.1 makes it possible to send Constant Tone Extensions (CTEs) in Bluetooth packets on which phase measurements can be done. This guide is for those implementing custom applications that take advantage of phase measurement and antenna switching capabilites. - Bluetooth 5.1 makes it possible to send Constant Tone Extensions (CTEs) in Bluetooth packets on which phase measurements can be done. This guide is for those implementing custom applications that take advantage of phase measurement and antenna switching capabilites. - + + Provides details on designing Bluetooth Low Energy applications with security and privacy in mind. - Provides details on designing Bluetooth Low Energy applications with security and privacy in mind. - + + Describes how to provision and configure Series 2 devices through the DCI and SWD. - Describes how to provision and configure Series 2 devices through the DCI and SWD. - + + Includes the results of the interoperability testing of Silicon Labs' ICs and Bluetooth Low Energy stack with Android and iOS smart phones. - Includes the results of the interoperability testing of Silicon Labs' ICs and Bluetooth Low Energy stack with Android and iOS smart phones. - + + Describes how to integrate crypto functionality into applications using PSA Crypto compared to Mbed TLS. - Describes how to integrate crypto functionality into applications using PSA Crypto compared to Mbed TLS. - + + Describes using Simplicity Studio 5's Network Analyzer to debug Bluetooth Mesh and Low Energy applications. It can be read jointly with AN958: Debugging and Programming Interfaces for Customer Designs for more information on using Packet Trace Interface with custom hardware. - Describes using Simplicity Studio 5's Network Analyzer to debug Bluetooth Mesh and Low Energy applications. It can be read jointly with AN958: Debugging and Programming Interfaces for Customer Designs for more information on using Packet Trace Interface with custom hardware. - + + Gecko Bootloader v2.x, introduced in GSDK 4.0, contains a number of changes compared to Gecko Bootloader v1.x. This document describes the differences between the versions, including how to configure the new Gecko Bootloader in Simplicity Studio 5. - Gecko Bootloader v2.x, introduced in GSDK 4.0, contains a number of changes compared to Gecko Bootloader v1.x. This document describes the differences between the versions, including how to configure the new Gecko Bootloader in Simplicity Studio 5. - + + Gives a short overview of the standard Host Controller Interface (HCI) and how to use it with a Silicon Labs Bluetooth LE controller. - Gives a short overview of the standard Host Controller Interface (HCI) and how to use it with a Silicon Labs Bluetooth LE controller. - + + Describes how to run any combination of Zigbee EmberZNet, OpenThread, and Bluetooth networking stacks on a Linux host processor, interfacing with a single EFR32 Radio Co-processor (RCP) with multiprotocol and multi-PAN support, as well as how to run the Zigbee stack on the EFR32 as a network co-processor (NCP) alongside the OpenThread RCP. - Describes how to run any combination of Zigbee EmberZNet, OpenThread, and Bluetooth networking stacks on a Linux host processor, interfacing with a single EFR32 Radio Co-processor (RCP) with multiprotocol and multi-PAN support. - + + Summarizes Amazon FreeRTOS components and sample applications, and explains how to use the examples to communicate with the Amazon Web Services (AWS) cloud with a smart phone app. - Summarizes Amazon FreeRTOS components and sample applications, and explains how to use the examples to communicate with the Amazon Web Services (AWS) cloud with a smart phone app. - + + Describes how to exploit the different features of Bluetooth technology to achieve the minimum possible energy consumption for a given use case. - Describes how to exploit the different features of Bluetooth technology to achieve the minimum possible energy consumption for a given use case. - + + Provides an overview and hyperlinks to all packaged documentation. - Provides an overview and hyperlinks to all packaged documentation. - + + Describes the differences between using Bluetooth SDK v2.x in Simplicity Studio 4 and using Bluetooth SDK v3.x in Simplicity Studio 5. Outlines the steps needed to migrate a v2.x project to v3.x. - Describes the differences between using Bluetooth SDK v2.x in Simplicity Studio 4 and using Bluetooth SDK v3.x in Simplicity Studio 5. Outlines the steps needed to migrate a v2.x project to v3.x. - + + Describes using the Simplicity Studio 5 IDE and tools for application development with Bluetooth SDK v3.x. - Describes using the Simplicity Studio 5 IDE and tools for application development with Bluetooth SDK v3.x. - + + Describes the software components provided by Silicon Labs to support Direction Finding (DF) and provides instructions on how to start developing your own application. - Describes the software components provided by Silicon Labs to support Direction Finding (DF) and provides instructions on how to start developing your own application. - + + Contains a comprehensive list of APIs used to interface to the Silicon Labs Bluetooth Real-Time Locating Library. - Contains a comprehensive list of APIs used to interface to the Silicon Labs Bluetooth Real-Time Locating Library. - + + Contains a comprehensive list of APIs used to interface to the Silicon Labs Bluetooth stack. - Contains a comprehensive list of APIs used to interface to the Silicon Labs Bluetooth stack. - + + Lists compatibility requirements and sources for all software components in the development environment. Discusses the latest changes to the Silicon Labs Bluetooth SDK and associated utilities, including added/deleted/deprecated features/API, and lists fixed and known issues. - Lists compatibility requirements and sources for all software components in the development environment. Discusses the latest changes to the Silicon Labs Bluetooth SDK and associated utilities, including added/deleted/deprecated features/API, and lists fixed and known issues. - + + Discusses the latest changes to the The Real-Time Locating (RTL) library, including added/deleted/deprecated APIs, and lists fixed and known issues. - Discusses the latest changes to the The Real-Time Locating (RTL) library, including added/deleted/deprecated APIs, and lists fixed and known issues. - + + A detailed overview of the changes, additions, and fixes in the Gecko Platform components. The Gecko Platform includes EMLIB, EMDRV, RAIL Library, NVM3, and the component-based infrastructure. - A detailed overview of the changes, additions, and fixes in the Gecko Platform components. The Gecko Platform includes EMLIB, EMDRV, RAIL Library, NVM3, and the component-based infrastructure. - + + Introduces the security concepts that must be considered when implementing an Internet of Things (IoT) system. Using the ioXt Alliance's eight security principles as a structure, it clearly delineates the solutions Silicon Labs provides to support endpoint security and what you must do outside of the Silicon Labs framework. - Introduces the security concepts that must be considered when implementing an Internet of Things (IoT) system. Using the ioXt Alliance's eight security principles as a structure, it clearly delineates the solutions Silicon Labs provides to support endpoint security and what you must do outside of the Silicon Labs framework. - + + Introduces bootloading for Silicon Labs networking devices. Discusses the Gecko Bootloader as well as legacy Ember and Bluetooth bootloaders, and describes the file formats used by each. - Introduces bootloading for Silicon Labs networking devices. Discusses the Gecko Bootloader as well as legacy Ember and Bluetooth bootloaders, and describes the file formats used by each. - + + Introduces non-volatile data storage using flash and the three different storage implementations offered for Silicon Labs microcontrollers and SoCs: Simulated EEPROM, PS Store, and NVM3. - Introduces non-volatile data storage using flash and the three different storage implementations offered for Silicon Labs microcontrollers and SoCs: Simulated EEPROM, PS Store, and NVM3. - + + Offers an overview for those new to the Bluetooth low energy technology. - Offers an overview for those new to the Bluetooth low energy technology. - + + Describes the four multiprotocol modes, discusses considerations when selecting protocols for multiprotocol implementations, and reviews the Radio Scheduler, a required component of a dynamic multiprotocol solution. - Describes the four multiprotocol modes, discusses considerations when selecting protocols for multiprotocol implementations, and reviews the Radio Scheduler, a required component of a dynamic multiprotocol solution. - + + Describes methods to improve the coexistence of 2.4 GHz IEEE 802.11b/g/n Wi-Fi and other 2.4 GHz radios such as Bluetooth, Bluetooth Mesh, Bluetooth Low Energy, and IEEE 802.15.4-based radios such as Zigbee and OpenThread. - Describes methods to improve the coexistence of 2.4 GHz IEEE 802.11b/g/n Wi-Fi and other 2.4 GHz radios such as Bluetooth, Bluetooth Mesh, Bluetooth Low Energy, and IEEE 802.15.4-based radios such as Zigbee and OpenThread. - + + Explains the basics of Bluetooth Angle of Arrival (AoA) and Angle of Departure (AoD) direction finding technologies and provides the theory behind estimating angle of arrival. - Explains the basics of Bluetooth Angle of Arrival (AoA) and Angle of Departure (AoD) direction finding technologies and provides the theory behind estimating angle of arrival. - + + Reviews using this XML-based mark-up language to describe the Bluetooth GATT database, configure access and security properties, and include the GATT database as part of the firmware. - Reviews using this XML-based mark-up language to describe the Bluetooth GATT database, configure access and security properties, and include the GATT database as part of the firmware. - + + Describes how and when to use Simplicity Commander's Command-Line Interface. - Describes how and when to use Simplicity Commander's Command-Line Interface. - + + Describes how to implement a dynamic multiprotocol solution. - Describes how to implement a dynamic multiprotocol solution. - + + Covers the Bluetooth stack v3.x architecture, application development flow, using the MCU core and peripherals, stack configuration options, and stack resource usage. - Covers the Bluetooth stack v3.x architecture, application development flow, using the MCU core and peripherals, stack configuration options, and stack resource usage. - + + Describes how to use the Simplicity Studio 5 GATT Configurator, an intuitive interface providing access to all the Profiles, Services, Characteristics, and Descriptors as defined in the Bluetooth specification. - Describes how to use the Simplicity Studio 5 GATT Configurator, an intuitive interface providing access to all the Profiles, Services, Characteristics, and Descriptors as defined in the Bluetooth specification. - + + Describes the high-level implementation of the Silicon Labs Gecko Bootloader for EFR32 SoCs and NCPs, and provides information on how to get started using the Gecko Bootloader with Silicon Labs wireless protocol stacks in GSDK 4.0 and higher. - Describes the high-level implementation of the Silicon Labs Gecko Bootloader for EFR32 SoCs and NCPs, and provides information on how to get started using the Gecko Bootloader with Silicon Labs wireless protocol stacks in GSDK 4.0 and higher. - + + The Bluetooth Direction Finding Tool Suite is meant to ease development with the Silicon Labs' RTL library. It provides multiple tools to configure the system, and also helps the development with analyzer tools that calculate many output parameters from the observed IQ samples. - The Bluetooth Direction Finding Tool Suite is meant to ease development with the Silicon Labs' RTL library. It provides multiple tools to configure the system, and also helps the development with analyzer tools that calculate many output parameters from the observed IQ samples. diff --git a/app/bluetooth/documentation/slBtMesh_docContent.xml b/app/bluetooth/documentation/slBtMesh_docContent.xml index 50031c172c..e45753be64 100644 --- a/app/bluetooth/documentation/slBtMesh_docContent.xml +++ b/app/bluetooth/documentation/slBtMesh_docContent.xml @@ -1,308 +1,308 @@ - - + + + Includes detailed information on using the Gecko Bootloader with Silicon Labs Bluetooth applications. It supplements the general Gecko Bootloader implementation information provided in UG489: Silicon Labs Gecko Bootloader User's Guide. - Includes detailed information on using the Gecko Bootloader with Silicon Labs Bluetooth applications. It supplements the general Gecko Bootloader implementation information provided in UG489: Silicon Labs Gecko Bootloader User's Guide. - + + Describes the Wi-Fi impact on Bluetooth and methods to improve Bluetooth coexistence with Wi-Fi. Explains design considerations to improve coexistence without direct interaction between Bluetooth and Wi-Fi radios. These techniques are applicable to the EFR32MGx and EFR32BGx series. Discusses the Silicon Labs Packet Traffic Arbitration (PTA) support to coordinate 2.4GHz RF traffic for co-located Bluetooth and Wi-Fi radios. - Describes the Wi-Fi impact on Bluetooth and methods to improve Bluetooth coexistence with Wi-Fi. Explains design considerations to improve coexistence without direct interaction between Bluetooth and Wi-Fi radios. These techniques are applicable to the EFR32MGx and EFR32BGx series. Discusses the Silicon Labs Packet Traffic Arbitration (PTA) support to coordinate 2.4GHz RF traffic for co-located Bluetooth and Wi-Fi radios. - + + Explains how NVM3 can be used as non-volatile data storage in various protocol implementations. - Explains how NVM3 can be used as non-volatile data storage in various protocol implementations. - + + Details methods for testing Bluetooth mesh network performance; results are intended to provide guidance on design practices and principles as well as expected field performance results. - Details methods for testing Bluetooth mesh network performance; results are intended to provide guidance on design practices and principles as well as expected field performance results. - + + Reviews the Zigbee, Thread, and Bluetooth mesh networks to evaluate their differences in performance and behavior. - Reviews the Zigbee, Thread, and Bluetooth mesh networks to evaluate their differences in performance and behavior. - + + Describes how to lock and unlock the debug access of EFR32 Gecko Series 2 devices. Many aspects of the debug access, including the secure debug unlock are described. The Debug Challenge Interface (DCI) and Secure Engine (SE) Mailbox Interface for locking and unlocking debug access are also included. - Describes how to lock and unlock the debug access of EFR32 Gecko Series 2 devices. Many aspects of the debug access, including the secure debug unlock are described. The Debug Challenge Interface (DCI) and Secure Engine (SE) Mailbox Interface for locking and unlocking debug access are also included. - + + Contains detailed information on configuring and using the Secure Boot with hardware Root of Trust and Secure Loader on Series 2 devices, including how to provision the signing key. This is a companion document to UG489: Silicon Labs Gecko Bootloader User's Guide. - Contains detailed information on configuring and using the Secure Boot with hardware Root of Trust and Secure Loader on Series 2 devices, including how to provision the signing key. This is a companion document to UG489: Silicon Labs Gecko Bootloader User's Guide. - + + Details on programming, provisioning, and configuring Series 2 devices in production environments. Covers Secure Engine Subsystem of Series 2 devices, which runs easily upgradeable Secure Engine (SE) or Virtual Secure Engine (VSE) firmware. - Details on programming, provisioning, and configuring Series 2 devices in production environments. Covers Secure Engine Subsystem of Series 2 devices, which runs easily upgradeable Secure Engine (SE) or Virtual Secure Engine (VSE) firmware. - + + How to program, provision, and configure the anti-tamper module on EFR32 Series 2 devices with Secure Vault. - How to program, provision, and configure the anti-tamper module on EFR32 Series 2 devices with Secure Vault. - + + Describes how to configure the NCP target and how to program the NCP host when using the Bluetooth Stack in Network Co-Processor mode - Describes how to configure the NCP target and how to program the NCP host when using the Bluetooth Stack in Network Co-Processor mode - + + Reviews performing radio frequency physical layer evaluation with EFR32BG SoCs and BGM modules using the Direct Test Mode protocol in Bluetooth SDK v3.x. - Reviews performing radio frequency physical layer evaluation with EFR32BG SoCs and BGM modules using the Direct Test Mode protocol in Bluetooth SDK v3.x. - + + How to authenticate an EFR32 Series 2 device with Secure Vault, using secure device certificates and signatures. - How to authenticate an EFR32 Series 2 device with Secure Vault, using secure device certificates and signatures. - + + How to securely "wrap" keys in EFR32 Series 2 devices with Secure Vault, so they can be stored in non-volatile storage. - How to securely "wrap" keys in EFR32 Series 2 devices with Secure Vault, so they can be stored in non-volatile storage. - + + Describes the differences between using Bluetooth mesh SDK v1.x in Simplicity Studio 4 and using Bluetooth mesh SDK v2.x in Simplicity Studio 5. Outlines the steps needed to migrate a v1.x project to v2.x. - Describes the differences between using Bluetooth mesh SDK v1.x in Simplicity Studio 4 and using Bluetooth mesh SDK v2.x in Simplicity Studio 5. Outlines the steps needed to migrate a v1.x project to v2.x. - + + Discusses the basics of Bluetooth mesh required to understand the Bluetooth mesh lighting example, and walks through key aspects of the application source code. - Discusses the basics of Bluetooth mesh required to understand the Bluetooth mesh lighting example, and walks through key aspects of the application source code. - + + Discusses the basics of sensor models and describe the related sample applications in the SDK that create a wireless network of sensors and sensor clients using Bluetooth mesh technology. - Discusses the basics of sensor models and describe the related sample applications in the SDK that create a wireless network of sensors and sensor clients using Bluetooth mesh technology. - + + Describes how to provision and configure Series 2 devices through the DCI and SWD. - Describes how to provision and configure Series 2 devices through the DCI and SWD. - + + Includes the results of the interoperability testing of Silicon Labs' ICs and Bluetooth Mesh stack with Android and iOS smart phones. - Includes the results of the interoperability testing of Silicon Labs' ICs and Bluetooth Mesh stack with Android and iOS smart phones. - + + Describes how to integrate crypto functionality into applications using PSA Crypto compared to Mbed TLS. - Describes how to integrate crypto functionality into applications using PSA Crypto compared to Mbed TLS. - + + Describes Low Power Node (LPN) and Friend operation and the parameters related to power consumption. It also describes how to measure the power consumption of EFR32BG devices acting as Bluetooth mesh LPNs using the setup and procedures recommended in AN969: Measuring Power Consumption in Wireless Gecko Devices. - Describes Low Power Node (LPN) and Friend operation and the parameters related to power consumption. It also describes how to measure the power consumption of EFR32BG devices acting as Bluetooth mesh LPNs using the setup and procedures recommended in AN969: Measuring Power Consumption in Wireless Gecko Devices. - + + Describes in detail how the Bluetooth mesh toplogy can influence network operation. Provides tips on how to tune your network and its nodes to achieve best performance. - Describes in detail how the Bluetooth mesh toplogy can influence network operation. Provides tips on how to tune your network and its nodes to achieve best performance. - + + Describes using Simplicity Studio 5's Network Analyzer to debug Bluetooth Mesh and Low Energy applications. It can be read jointly with AN958: Debugging and Programming Interfaces for Customer Designs for more information on using Packet Trace Interface with custom hardware. - Describes using Simplicity Studio 5's Network Analyzer to debug Bluetooth Mesh and Low Energy applications. It can be read jointly with AN958: Debugging and Programming Interfaces for Customer Designs for more information on using Packet Trace Interface with custom hardware. - + + Provides background information on the sequence number and IV index in a Bluetooth mesh network and the IV Update and IV Index Recovery procedures. It also discusses how to implement IV Update functionality in a Bluetooth mesh application. - Provides background information on the sequence number and IV index in a Bluetooth mesh network and the IV Update and IV Index Recovery procedures. It also discusses how to implement IV Update functionality in a Bluetooth mesh application. - + + Gecko Bootloader v2.x, introduced in GSDK 4.0, contains a number of changes compared to Gecko Bootloader v1.x. This document describes the differences between the versions, including how to configure the new Gecko Bootloader in Simplicity Studio 5. - Gecko Bootloader v2.x, introduced in GSDK 4.0, contains a number of changes compared to Gecko Bootloader v1.x. This document describes the differences between the versions, including how to configure the new Gecko Bootloader in Simplicity Studio 5. - + + The NCP Host Provisioner example demonstrates how to run a provisioner on a computer with a NCP node connected. The user can provision, configure, and reset other nodes through the NCP node. - The NCP Host Provisioner example demonstrates how to run a provisioner on a computer with a NCP node connected. The user can provision, configure, and reset other nodes through the NCP node. - + + Provides an overview and hyperlinks to all packaged documentation. - Provides an overview and hyperlinks to all packaged documentation. - + + Describes using the Simplicity Studio 5 IDE and tools for application development with Bluetooth Mesh SDK v2.x. - Describes using the Simplicity Studio 5 IDE and tools for application development with Bluetooth Mesh SDK v2.x. - + + Contains a comprehensive list of APIs used to interface to the Silicon Labs Bluetooth Mesh stack. - Contains a comprehensive list of APIs used to interface to the Silicon Labs Bluetooth Mesh stack. - + + A reference for those developing C-based applications for the Silicon Labs EFR32 products using the Silicon Labs Bluetooth mesh stack. A companion to UG434: Silicon Labs Bluetooth C Application Developers Guide for SDK v3.x containing content specific to Bluetooth mesh application development. Covers Bluetooth mesh stack architecture, application development flow, use and limitations of the MCU core and peripherals, stack configuration options, and stack resource usage. - A reference for those developing C-based applications for the Silicon Labs EFR32 products using the Silicon Labs Bluetooth mesh stack. A companion to UG434: Silicon Labs Bluetooth C Application Developers Guide for SDK v3.x containing content specific to Bluetooth mesh application development. Covers Bluetooth mesh stack architecture, application development flow, use and limitations of the MCU core and peripherals, stack configuration options, and stack resource usage. - + + Lists compatibility requirements and sources for all software components in the development environment. Discusses the latest changes to the Silicon Labs Bluetooth mesh SDK and associated utilities, including added/deleted/deprecated features/API, and lists fixed and known issues. - Lists compatibility requirements and sources for all software components in the development environment. Discusses the latest changes to the Silicon Labs Bluetooth mesh SDK and associated utilities, including added/deleted/deprecated features/API, and lists fixed and known issues. - + + A detailed overview of the changes, additions, and fixes in the Gecko Platform components. The Gecko Platform includes EMLIB, EMDRV, RAIL Library, NVM3, and the component-based infrastructure. - A detailed overview of the changes, additions, and fixes in the Gecko Platform components. The Gecko Platform includes EMLIB, EMDRV, RAIL Library, NVM3, and the component-based infrastructure. - + + Introduces the security concepts that must be considered when implementing an Internet of Things (IoT) system. Using the ioXt Alliance's eight security principles as a structure, it clearly delineates the solutions Silicon Labs provides to support endpoint security and what you must do outside of the Silicon Labs framework. - Introduces the security concepts that must be considered when implementing an Internet of Things (IoT) system. Using the ioXt Alliance's eight security principles as a structure, it clearly delineates the solutions Silicon Labs provides to support endpoint security and what you must do outside of the Silicon Labs framework. - + + Introduces bootloading for Silicon Labs networking devices. Discusses the Gecko Bootloader as well as legacy Ember and Bluetooth bootloaders, and describes the file formats used by each. - Introduces bootloading for Silicon Labs networking devices. Discusses the Gecko Bootloader as well as legacy Ember and Bluetooth bootloaders, and describes the file formats used by each. - + + Introduces non-volatile data storage using flash and the three different storage implementations offered for Silicon Labs microcontrollers and SoCs: Simulated EEPROM, PS Store, and NVM3. - Introduces non-volatile data storage using flash and the three different storage implementations offered for Silicon Labs microcontrollers and SoCs: Simulated EEPROM, PS Store, and NVM3. - + + Describes methods to improve the coexistence of 2.4 GHz IEEE 802.11b/g/n Wi-Fi and other 2.4 GHz radios such as Bluetooth, Bluetooth Mesh, Bluetooth Low Energy, and IEEE 802.15.4-based radios such as Zigbee and OpenThread. - Describes methods to improve the coexistence of 2.4 GHz IEEE 802.11b/g/n Wi-Fi and other 2.4 GHz radios such as Bluetooth, Bluetooth Mesh, Bluetooth Low Energy, and IEEE 802.15.4-based radios such as Zigbee and OpenThread. - + + Reviews using this XML-based mark-up language to describe the Bluetooth GATT database, configure access and security properties, and include the GATT database as part of the firmware. - Reviews using this XML-based mark-up language to describe the Bluetooth GATT database, configure access and security properties, and include the GATT database as part of the firmware. - + + Describes how and when to use Simplicity Commander's Command-Line Interface. - Describes how and when to use Simplicity Commander's Command-Line Interface. - + + Describes how to use the Simplicity Studio 5 GATT Configurator, an intuitive interface providing access to all the Profiles, Services, Characteristics, and Descriptors as defined in the Bluetooth specification. - Describes how to use the Simplicity Studio 5 GATT Configurator, an intuitive interface providing access to all the Profiles, Services, Characteristics, and Descriptors as defined in the Bluetooth specification. - + + Describes the components, stack, and DCD (Device Composition Data) configuration options for the Bluetooth Mesh v2.x SDK. - Describes the components, stack, and DCD (Device Composition Data) configuration options for the Bluetooth Mesh v2.x SDK. - + + Describes the high-level implementation of the Silicon Labs Gecko Bootloader for EFR32 SoCs and NCPs, and provides information on how to get started using the Gecko Bootloader with Silicon Labs wireless protocol stacks in GSDK 4.0 and higher. - Describes the high-level implementation of the Silicon Labs Gecko Bootloader for EFR32 SoCs and NCPs, and provides information on how to get started using the Gecko Bootloader with Silicon Labs wireless protocol stacks in GSDK 4.0 and higher. diff --git a/app/bluetooth/esf.properties b/app/bluetooth/esf.properties index 6e064ecf2c..0e26dddfd6 100644 --- a/app/bluetooth/esf.properties +++ b/app/bluetooth/esf.properties @@ -3,8 +3,8 @@ id=com.silabs.stack.ble label=Bluetooth SDK description=Bluetooth Software Development Kit -version=4.0.0.0 -prop.subLabel=Bluetooth\\ 4.0.0 +version=4.1.0.0 +prop.subLabel=Bluetooth\\ 4.1.0 # Default compatibility of the BLE SDK prop.boardCompatibility=.* diff --git a/app/bluetooth/example/bt_aoa_soc_asset_tag/app.c b/app/bluetooth/example/bt_aoa_soc_asset_tag/app.c index c18c8f5dd6..0cc34b3086 100644 --- a/app/bluetooth/example/bt_aoa_soc_asset_tag/app.c +++ b/app/bluetooth/example/bt_aoa_soc_asset_tag/app.c @@ -3,7 +3,7 @@ * @brief Core application logic. ******************************************************************************* * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -28,7 +28,6 @@ * ******************************************************************************/ #include "em_common.h" -#include "app_log.h" #include "app_assert.h" #include "sl_bluetooth.h" #include "gatt_db.h" @@ -81,13 +80,6 @@ void sl_bt_on_event(sl_bt_msg_t *evt) // This event indicates the device has started and the radio is ready. // Do not call any stack command before receiving this boot event! case sl_bt_evt_system_boot_id: - // Print boot message. - app_log_info("Bluetooth stack booted: v%d.%d.%d-b%d\n", - evt->data.evt_system_boot.major, - evt->data.evt_system_boot.minor, - evt->data.evt_system_boot.patch, - evt->data.evt_system_boot.build); - // Extract unique ID from BT Address. sc = sl_bt_system_get_identity_address(&address, &address_type); app_assert_status(sc); @@ -108,20 +100,11 @@ void sl_bt_on_event(sl_bt_msg_t *evt) system_id); app_assert_status(sc); - app_log_info("Bluetooth %s address: %02X:%02X:%02X:%02X:%02X:%02X\n", - address_type ? "static random" : "public device", - address.addr[5], - address.addr[4], - address.addr[3], - address.addr[2], - address.addr[1], - address.addr[0]); - // Create an advertising set. sc = sl_bt_advertiser_create_set(&advertising_set_handle); app_assert_status(sc); - // Generate data for advertising + // Generate data for advertising. sc = sl_bt_legacy_advertiser_generate_data(advertising_set_handle, sl_bt_advertiser_general_discoverable); app_assert_status(sc); @@ -134,56 +117,33 @@ void sl_bt_on_event(sl_bt_msg_t *evt) 0, // adv. duration 0); // max. num. adv. events app_assert_status(sc); - // Start general advertising and enable connections. + + // Enable connections. sc = sl_bt_legacy_advertiser_start(advertising_set_handle, sl_bt_advertiser_connectable_scannable); app_assert_status(sc); - app_log_info("Started advertising\n"); break; // ------------------------------- // This event indicates that a new connection was opened. case sl_bt_evt_connection_opened_id: - app_log_info("Connection opened: %d\n", evt->data.evt_connection_opened.connection); - app_log_info("Client address: %02X:%02X:%02X:%02X:%02X:%02X\n", - evt->data.evt_connection_opened.address.addr[5], - evt->data.evt_connection_opened.address.addr[4], - evt->data.evt_connection_opened.address.addr[3], - evt->data.evt_connection_opened.address.addr[2], - evt->data.evt_connection_opened.address.addr[1], - evt->data.evt_connection_opened.address.addr[0]); connection_count++; // Continue advertising if the stack allows further connections. if (connection_count < SL_BT_CONFIG_MAX_CONNECTIONS) { - // Generate data for advertising - sc = sl_bt_legacy_advertiser_generate_data(advertising_set_handle, - sl_bt_advertiser_general_discoverable); - app_assert_status(sc); - sc = sl_bt_legacy_advertiser_start(advertising_set_handle, sl_bt_advertiser_connectable_scannable); app_assert_status(sc); - app_log_info("Continue advertising\n"); } break; // ------------------------------- // This event indicates that a connection was closed. case sl_bt_evt_connection_closed_id: - app_log_info("Connection closed: %d\n", - evt->data.evt_connection_closed.connection); - - // Generate data for advertising - sc = sl_bt_legacy_advertiser_generate_data(advertising_set_handle, - sl_bt_advertiser_general_discoverable); - app_assert_status(sc); - if (connection_count >= SL_BT_CONFIG_MAX_CONNECTIONS) { // Restart advertising after client has disconnected. sc = sl_bt_legacy_advertiser_start(advertising_set_handle, sl_bt_advertiser_connectable_scannable); app_assert_status(sc); - app_log_info("Restart advertising\n"); } connection_count--; break; diff --git a/app/bluetooth/example/bt_aoa_soc_asset_tag/bt_aoa_soc_asset_tag.slcp b/app/bluetooth/example/bt_aoa_soc_asset_tag/bt_aoa_soc_asset_tag.slcp index 2ed78bcca9..0aae81fed9 100644 --- a/app/bluetooth/example/bt_aoa_soc_asset_tag/bt_aoa_soc_asset_tag.slcp +++ b/app/bluetooth/example/bt_aoa_soc_asset_tag/bt_aoa_soc_asset_tag.slcp @@ -23,7 +23,6 @@ component: - id: bluetooth_feature_connection - id: bluetooth_feature_gatt - id: bluetooth_feature_gatt_server - - id: bluetooth_feature_scanner - id: bluetooth_feature_sm - id: bluetooth_feature_system - id: in_place_ota_dfu @@ -34,11 +33,6 @@ component: - id: mpu - id: gatt_service_cte - id: gatt_service_cte_silabs - - id: app_log - - id: iostream_usart - instance: - - vcom - - id: iostream_retarget_stdio source: - path: main.c @@ -74,10 +68,6 @@ configuration: value: "2752" - name: SL_HEAP_SIZE value: "9200" - - name: SL_BOARD_ENABLE_VCOM - value: "1" - condition: - - iostream_usart - name: SL_PSA_KEY_USER_SLOT_COUNT value: "0" condition: diff --git a/app/bluetooth/example/bt_ncp/bt_ncp.slcp b/app/bluetooth/example/bt_ncp/bt_ncp.slcp index a560bf2841..821690820f 100644 --- a/app/bluetooth/example/bt_ncp/bt_ncp.slcp +++ b/app/bluetooth/example/bt_ncp/bt_ncp.slcp @@ -28,7 +28,8 @@ component: - id: bluetooth_feature_gatt - id: bluetooth_feature_gatt_server - id: bluetooth_feature_nvm - - id: bluetooth_feature_scanner + - id: bluetooth_feature_legacy_scanner + - id: bluetooth_feature_extended_scanner - id: bluetooth_feature_sm - id: bluetooth_feature_sync - id: bluetooth_feature_system diff --git a/app/bluetooth/example/bt_ncp/bt_ncp_xg1.slcp b/app/bluetooth/example/bt_ncp/bt_ncp_xg1.slcp index d443d05ff0..135f0e7bd3 100644 --- a/app/bluetooth/example/bt_ncp/bt_ncp_xg1.slcp +++ b/app/bluetooth/example/bt_ncp/bt_ncp_xg1.slcp @@ -26,7 +26,7 @@ component: - id: bluetooth_feature_gatt - id: bluetooth_feature_gatt_server - id: bluetooth_feature_nvm - - id: bluetooth_feature_scanner + - id: bluetooth_feature_legacy_scanner - id: bluetooth_feature_sm - id: bluetooth_feature_sync - id: bluetooth_feature_system diff --git a/app/bluetooth/example/bt_rail_dmp_soc_empty/bt_rail_dmp_soc_empty_freertos.slcp b/app/bluetooth/example/bt_rail_dmp_soc_empty/bt_rail_dmp_soc_empty_freertos.slcp index cfd368ce42..047a567061 100644 --- a/app/bluetooth/example/bt_rail_dmp_soc_empty/bt_rail_dmp_soc_empty_freertos.slcp +++ b/app/bluetooth/example/bt_rail_dmp_soc_empty/bt_rail_dmp_soc_empty_freertos.slcp @@ -24,9 +24,7 @@ component: - id: gatt_configuration - id: bluetooth_feature_legacy_advertiser - id: bluetooth_feature_connection - - id: bluetooth_feature_gatt - id: bluetooth_feature_gatt_server - - id: bluetooth_feature_scanner - id: bluetooth_feature_sm - id: bluetooth_feature_system - id: bootloader_interface diff --git a/app/bluetooth/example/bt_rail_dmp_soc_empty/bt_rail_dmp_soc_empty_micriumos.slcp b/app/bluetooth/example/bt_rail_dmp_soc_empty/bt_rail_dmp_soc_empty_micriumos.slcp index c9159e35b3..6aaeebbb6c 100644 --- a/app/bluetooth/example/bt_rail_dmp_soc_empty/bt_rail_dmp_soc_empty_micriumos.slcp +++ b/app/bluetooth/example/bt_rail_dmp_soc_empty/bt_rail_dmp_soc_empty_micriumos.slcp @@ -24,9 +24,7 @@ component: - id: gatt_configuration - id: bluetooth_feature_legacy_advertiser - id: bluetooth_feature_connection - - id: bluetooth_feature_gatt - id: bluetooth_feature_gatt_server - - id: bluetooth_feature_scanner - id: bluetooth_feature_sm - id: bluetooth_feature_system - id: bootloader_interface diff --git a/app/bluetooth/example/bt_rail_dmp_soc_empty_std/bt_rail_dmp_soc_empty_std_freertos.slcp b/app/bluetooth/example/bt_rail_dmp_soc_empty_std/bt_rail_dmp_soc_empty_std_freertos.slcp index f12ca4a3e3..1e152f1520 100644 --- a/app/bluetooth/example/bt_rail_dmp_soc_empty_std/bt_rail_dmp_soc_empty_std_freertos.slcp +++ b/app/bluetooth/example/bt_rail_dmp_soc_empty_std/bt_rail_dmp_soc_empty_std_freertos.slcp @@ -24,9 +24,7 @@ component: - id: gatt_configuration - id: bluetooth_feature_legacy_advertiser - id: bluetooth_feature_connection - - id: bluetooth_feature_gatt - id: bluetooth_feature_gatt_server - - id: bluetooth_feature_scanner - id: bluetooth_feature_sm - id: bluetooth_feature_system - id: bootloader_interface diff --git a/app/bluetooth/example/bt_rail_dmp_soc_empty_std/bt_rail_dmp_soc_empty_std_micriumos.slcp b/app/bluetooth/example/bt_rail_dmp_soc_empty_std/bt_rail_dmp_soc_empty_std_micriumos.slcp index a57a1b98ec..027f6231b6 100644 --- a/app/bluetooth/example/bt_rail_dmp_soc_empty_std/bt_rail_dmp_soc_empty_std_micriumos.slcp +++ b/app/bluetooth/example/bt_rail_dmp_soc_empty_std/bt_rail_dmp_soc_empty_std_micriumos.slcp @@ -24,11 +24,9 @@ component: - id: gatt_configuration - id: bluetooth_feature_legacy_advertiser - id: bluetooth_feature_connection - - id: bluetooth_feature_gatt - id: bluetooth_feature_gatt_server - - id: bluetooth_feature_scanner - - id: bluetooth_feature_sm - id: bluetooth_feature_system + - id: bluetooth_feature_sm - id: bootloader_interface - id: mpu - id: in_place_ota_dfu diff --git a/app/bluetooth/example/bt_rail_dmp_soc_light/bt_rail_dmp_soc_light_freertos.slcp b/app/bluetooth/example/bt_rail_dmp_soc_light/bt_rail_dmp_soc_light_freertos.slcp index 456d1928c2..cdde7f28d0 100644 --- a/app/bluetooth/example/bt_rail_dmp_soc_light/bt_rail_dmp_soc_light_freertos.slcp +++ b/app/bluetooth/example/bt_rail_dmp_soc_light/bt_rail_dmp_soc_light_freertos.slcp @@ -25,9 +25,7 @@ component: - id: gatt_configuration - id: bluetooth_feature_legacy_advertiser - id: bluetooth_feature_connection - - id: bluetooth_feature_gatt - id: bluetooth_feature_gatt_server - - id: bluetooth_feature_scanner - id: bluetooth_feature_sm - id: bluetooth_feature_system - id: in_place_ota_dfu diff --git a/app/bluetooth/example/bt_rail_dmp_soc_light/bt_rail_dmp_soc_light_micriumos.slcp b/app/bluetooth/example/bt_rail_dmp_soc_light/bt_rail_dmp_soc_light_micriumos.slcp index 54f8181a58..8e430ad695 100644 --- a/app/bluetooth/example/bt_rail_dmp_soc_light/bt_rail_dmp_soc_light_micriumos.slcp +++ b/app/bluetooth/example/bt_rail_dmp_soc_light/bt_rail_dmp_soc_light_micriumos.slcp @@ -25,9 +25,7 @@ component: - id: gatt_configuration - id: bluetooth_feature_legacy_advertiser - id: bluetooth_feature_connection - - id: bluetooth_feature_gatt - id: bluetooth_feature_gatt_server - - id: bluetooth_feature_scanner - id: bluetooth_feature_sm - id: bluetooth_feature_system - id: in_place_ota_dfu diff --git a/app/bluetooth/example/bt_rail_dmp_soc_light_std/bt_rail_dmp_soc_light_std_freertos.slcp b/app/bluetooth/example/bt_rail_dmp_soc_light_std/bt_rail_dmp_soc_light_std_freertos.slcp index ebfb183de1..e21b126380 100644 --- a/app/bluetooth/example/bt_rail_dmp_soc_light_std/bt_rail_dmp_soc_light_std_freertos.slcp +++ b/app/bluetooth/example/bt_rail_dmp_soc_light_std/bt_rail_dmp_soc_light_std_freertos.slcp @@ -25,9 +25,7 @@ component: - id: gatt_configuration - id: bluetooth_feature_legacy_advertiser - id: bluetooth_feature_connection - - id: bluetooth_feature_gatt - id: bluetooth_feature_gatt_server - - id: bluetooth_feature_scanner - id: bluetooth_feature_sm - id: bluetooth_feature_system - id: in_place_ota_dfu diff --git a/app/bluetooth/example/bt_rail_dmp_soc_light_std/bt_rail_dmp_soc_light_std_micriumos.slcp b/app/bluetooth/example/bt_rail_dmp_soc_light_std/bt_rail_dmp_soc_light_std_micriumos.slcp index e9029311f5..8229a7ec94 100644 --- a/app/bluetooth/example/bt_rail_dmp_soc_light_std/bt_rail_dmp_soc_light_std_micriumos.slcp +++ b/app/bluetooth/example/bt_rail_dmp_soc_light_std/bt_rail_dmp_soc_light_std_micriumos.slcp @@ -25,9 +25,7 @@ component: - id: gatt_configuration - id: bluetooth_feature_legacy_advertiser - id: bluetooth_feature_connection - - id: bluetooth_feature_gatt - id: bluetooth_feature_gatt_server - - id: bluetooth_feature_scanner - id: bluetooth_feature_sm - id: bluetooth_feature_system - id: in_place_ota_dfu diff --git a/app/bluetooth/example/bt_rcp/bt_rcp.slcp b/app/bluetooth/example/bt_rcp/bt_rcp.slcp index b731d573bf..3350aa7095 100644 --- a/app/bluetooth/example/bt_rcp/bt_rcp.slcp +++ b/app/bluetooth/example/bt_rcp/bt_rcp.slcp @@ -29,7 +29,8 @@ component: - id: bluetooth_feature_extended_advertiser - id: bluetooth_feature_periodic_advertiser - id: bluetooth_feature_connection_phy_update - - id: bluetooth_feature_scanner + - id: bluetooth_feature_legacy_scanner + - id: bluetooth_feature_extended_scanner - id: device_init - id: bootloader_interface diff --git a/app/bluetooth/example/bt_rcp/bt_rcp_cpc.slcp b/app/bluetooth/example/bt_rcp/bt_rcp_cpc.slcp index d83a96c369..e10e7519fa 100644 --- a/app/bluetooth/example/bt_rcp/bt_rcp_cpc.slcp +++ b/app/bluetooth/example/bt_rcp/bt_rcp_cpc.slcp @@ -32,7 +32,8 @@ component: - id: bluetooth_feature_extended_advertiser - id: bluetooth_feature_periodic_advertiser - id: bluetooth_feature_connection_phy_update - - id: bluetooth_feature_scanner + - id: bluetooth_feature_legacy_scanner + - id: bluetooth_feature_extended_scanner - id: device_init - id: bootloader_interface diff --git a/app/bluetooth/example/bt_soc_app_ota_dfu/bt_soc_app_ota_dfu.slcp b/app/bluetooth/example/bt_soc_app_ota_dfu/bt_soc_app_ota_dfu.slcp index 7bfa8c9238..0b3715b9bd 100644 --- a/app/bluetooth/example/bt_soc_app_ota_dfu/bt_soc_app_ota_dfu.slcp +++ b/app/bluetooth/example/bt_soc_app_ota_dfu/bt_soc_app_ota_dfu.slcp @@ -21,11 +21,9 @@ component: - id: gatt_configuration - id: bluetooth_feature_legacy_advertiser - id: bluetooth_feature_connection - - id: bluetooth_feature_gatt - id: bluetooth_feature_gatt_server - - id: bluetooth_feature_scanner - id: bluetooth_feature_sm - - id: bluetooth_feature_system + - id: bluetooth_feature_system - id: bootloader_interface - id: rail_util_pti - id: simple_button diff --git a/app/bluetooth/example/bt_soc_app_ota_dfu/bt_soc_app_ota_dfu_freertos.slcp b/app/bluetooth/example/bt_soc_app_ota_dfu/bt_soc_app_ota_dfu_freertos.slcp index fbaf9723a7..024ce68439 100644 --- a/app/bluetooth/example/bt_soc_app_ota_dfu/bt_soc_app_ota_dfu_freertos.slcp +++ b/app/bluetooth/example/bt_soc_app_ota_dfu/bt_soc_app_ota_dfu_freertos.slcp @@ -23,9 +23,7 @@ component: - id: gatt_configuration - id: bluetooth_feature_legacy_advertiser - id: bluetooth_feature_connection - - id: bluetooth_feature_gatt - id: bluetooth_feature_gatt_server - - id: bluetooth_feature_scanner - id: bluetooth_feature_sm - id: bluetooth_feature_system - id: bootloader_interface diff --git a/app/bluetooth/example/bt_soc_app_ota_dfu/bt_soc_app_ota_dfu_micriumos.slcp b/app/bluetooth/example/bt_soc_app_ota_dfu/bt_soc_app_ota_dfu_micriumos.slcp index cfbca920f7..020f4b12ba 100644 --- a/app/bluetooth/example/bt_soc_app_ota_dfu/bt_soc_app_ota_dfu_micriumos.slcp +++ b/app/bluetooth/example/bt_soc_app_ota_dfu/bt_soc_app_ota_dfu_micriumos.slcp @@ -23,9 +23,7 @@ component: - id: gatt_configuration - id: bluetooth_feature_legacy_advertiser - id: bluetooth_feature_connection - - id: bluetooth_feature_gatt - id: bluetooth_feature_gatt_server - - id: bluetooth_feature_scanner - id: bluetooth_feature_sm - id: bluetooth_feature_system - id: bootloader_interface diff --git a/app/bluetooth/example/bt_soc_cbap/app.c b/app/bluetooth/example/bt_soc_cbap/app.c index 16c0dab1a6..62d0c93a5d 100644 --- a/app/bluetooth/example/bt_soc_cbap/app.c +++ b/app/bluetooth/example/bt_soc_cbap/app.c @@ -28,44 +28,84 @@ * ******************************************************************************/ #include +#include #include "em_common.h" #include "sl_bluetooth.h" #include "gatt_db.h" #include "app_assert.h" #include "app_log.h" #include "sl_simple_led_instances.h" +#include "sl_simple_timer.h" #include "sl_bt_cbap.h" #include "cbap_config.h" #include "app.h" -#define SCAN_INTERVAL 16 // 10ms -#define SCAN_WINDOW 16 // 10ms +#define LED_TIMEOUT 500 // ms +#define NO_CALLBACK_DATA (void *)NULL // Callback has no parameters -#define BT_ADDR_LEN 6 // Bluetooth address length +#if SL_BT_CONFIG_MAX_CONNECTIONS < 1 + #error At least 1 connection has to be enabled! +#endif + +// Connection properties +typedef struct { + uint8_t connection_handle; + bd_addr address; +} conn_properties_t; // The advertising set handle allocated from Bluetooth stack. -static uint8_t advertising_set_handle = 0xff; -// Connection handle -static uint8_t connection = 0xff; +static uint8_t advertising_set_handle = SL_BT_INVALID_ADVERTISING_SET_HANDLE; + +// The connectiopn handle and the Bluetooth address of the remote device we +// have CBAP in progress with +static conn_properties_t candidate_device; + +// Array for holding properties of the trusted connections +static conn_properties_t trusted_devices[SL_BT_CONFIG_MAX_CONNECTIONS]; // Device role static sl_bt_cbap_role_t role = ROLE; // Should we search for a specified peripheral device or not static bool peripheral_target_defined = ADDR_ENABLE; // Target device Bluetooth address -static uint8_t peripheral_target_addr[BT_ADDR_LEN]; +static bd_addr peripheral_target_addr; + +// Timer handle +static sl_simple_timer_t led_timer; + +// Clears candidate device. +static void clear_connection_info(void); +// Adds the candidate device to the trusted devices array. +static void save_connection_info(void); +// Logs the connection handle and the Bluetooth address of the trusted devices. +static void print_trusted_devices(void); // Convert address string to address data bytes. -static bool decode_address(char *addess_str, uint8_t *address); +static bool decode_address(char *addess_str, bd_addr *address); // Examine a scan report and decide if a connection should be established. -bool check_scan_report(sl_bt_evt_scanner_scan_report_t *scan_report); +bool check_scan_report(sl_bt_evt_scanner_legacy_advertisement_report_t *scan_report); + +// Timer Callback. +static void led_timer_cb(sl_simple_timer_t *handle, void *data); /**************************************************************************//** * Application Init. *****************************************************************************/ SL_WEAK void app_init(void) { + // Initialize candidate device data + clear_connection_info(); + + // Initialize connection array + uint8_t i, j; + for (i = 0; i < SL_BT_CONFIG_MAX_CONNECTIONS; i++) { + trusted_devices[i].connection_handle = SL_BT_INVALID_CONNECTION_HANDLE; + for (j = 0; j < sizeof(bd_addr); j++) { + trusted_devices[i].address.addr[j] = 0xff; + } + } + ///////////////////////////////////////////////////////////////////////////// // Put your additional application init code here! // // This is called once during start-up. // @@ -156,14 +196,14 @@ void sl_bt_on_event(sl_bt_msg_t *evt) // If defined, get target address if (peripheral_target_defined) { - if (decode_address(ADDR, peripheral_target_addr)) { - app_log_info("Searching for %02X:%02X:%02X:%02X:%02X:%02X. ", - peripheral_target_addr[5], - peripheral_target_addr[4], - peripheral_target_addr[3], - peripheral_target_addr[2], - peripheral_target_addr[1], - peripheral_target_addr[0]); + if (decode_address(ADDR, &peripheral_target_addr)) { + app_log_info("Searching for %02X:%02X:%02X:%02X:%02X:%02X. " APP_LOG_NL, + peripheral_target_addr.addr[5], + peripheral_target_addr.addr[4], + peripheral_target_addr.addr[3], + peripheral_target_addr.addr[2], + peripheral_target_addr.addr[1], + peripheral_target_addr.addr[0]); } else { peripheral_target_defined = false; app_log_error("Reading target address failed. Searching for any " \ @@ -174,12 +214,6 @@ void sl_bt_on_event(sl_bt_msg_t *evt) "Service." APP_LOG_NL); } - // Set default scanning parameters. - sc = sl_bt_scanner_set_parameters(sl_bt_scanner_scan_mode_passive, - SCAN_INTERVAL, - SCAN_WINDOW); - app_assert_status(sc); - // Start scanning sc = sl_bt_scanner_start(sl_bt_scanner_scan_phy_1m, sl_bt_scanner_discover_generic); @@ -196,19 +230,20 @@ void sl_bt_on_event(sl_bt_msg_t *evt) // ------------------------------- // This event is generated when an advertisement packet or a scan response // is received from a responder - case sl_bt_evt_scanner_scan_report_id: + case sl_bt_evt_scanner_legacy_advertisement_report_id: if (role == SL_BT_CBAP_ROLE_CENTRAL) { // Filter for connectable scannable undirected advertisements - if (evt->data.evt_scanner_scan_report.packet_type == 0 - && check_scan_report(&evt->data.evt_scanner_scan_report)) { + if ((evt->data.evt_scanner_legacy_advertisement_report.event_flags + == (SL_BT_SCANNER_EVENT_FLAG_CONNECTABLE | SL_BT_SCANNER_EVENT_FLAG_SCANNABLE)) + && check_scan_report(&evt->data.evt_scanner_legacy_advertisement_report)) { // Target device found. Stop scanning. sc = sl_bt_scanner_stop(); app_assert_status(sc); // Connect to device - sc = sl_bt_connection_open(evt->data.evt_scanner_scan_report.address, - evt->data.evt_scanner_scan_report.address_type, - sl_bt_gap_1m_phy, + sc = sl_bt_connection_open(evt->data.evt_scanner_legacy_advertisement_report.address, + evt->data.evt_scanner_legacy_advertisement_report.address_type, + sl_bt_gap_phy_1m, NULL); app_assert_status(sc); } @@ -219,47 +254,35 @@ void sl_bt_on_event(sl_bt_msg_t *evt) // This event indicates that a new connection was opened. case sl_bt_evt_connection_opened_id: app_log_info("Connection opened." APP_LOG_NL); - connection = evt->data.evt_connection_opened.connection; + // Store data of the candidate device + candidate_device.connection_handle = evt->data.evt_connection_opened.connection; + candidate_device.address = evt->data.evt_connection_opened.address; if (evt->data.evt_connection_opened.bonding != SL_BT_INVALID_BONDING_HANDLE) { app_log_warning("Devices are already bonded." APP_LOG_NL); } - sl_bt_cbap_start(role, connection); + sc = sl_bt_cbap_start(role, candidate_device.connection_handle); + app_log_status_error(sc); + if (sc == SL_STATUS_OK) { + app_log_info("CBAP procedure start." APP_LOG_NL); + } break; // ------------------------------- // This event indicates that a connection was closed. case sl_bt_evt_connection_closed_id: - switch (role) { - case SL_BT_CBAP_ROLE_PERIPHERAL: - // Turn off LED - sl_led_turn_off(SL_SIMPLE_LED_INSTANCE(0)); - app_log_info("LED off." APP_LOG_NL); - - // Generate data for advertising - sc = sl_bt_legacy_advertiser_generate_data(advertising_set_handle, - sl_bt_advertiser_general_discoverable); - app_assert_status(sc); - - // Restart advertising after client has disconnected - sc = sl_bt_legacy_advertiser_start(advertising_set_handle, - sl_bt_advertiser_connectable_scannable); - app_assert_status(sc); - app_log_info("Connection closed. Advertising started." APP_LOG_NL); - break; - - case SL_BT_CBAP_ROLE_CENTRAL: - // Start scanning - sc = sl_bt_scanner_start(sl_bt_scanner_scan_phy_1m, - sl_bt_scanner_discover_generic); - app_log_info("Connection closed. Scanning started." APP_LOG_NL); - break; - - default: - app_assert_status_f(SL_STATUS_INVALID_STATE, "Invalid role!"); - break; + // Remove connection from the connection array if present + for (int i = 0; i < SL_BT_CONFIG_MAX_CONNECTIONS; i++) { + if (trusted_devices[i].connection_handle == evt->data.evt_connection_closed.connection) { + trusted_devices[i].connection_handle = SL_BT_INVALID_CONNECTION_HANDLE; + for (uint8_t j = 0; j < sizeof(bd_addr); j++) { + trusted_devices[i].address.addr[j] = 0xff; + } + app_log_info("Trusted device [%d] removed." APP_LOG_NL, + evt->data.evt_connection_closed.connection); + } } break; @@ -286,13 +309,20 @@ void sl_bt_on_event(sl_bt_msg_t *evt) break; } - // Set LED state. if (data_recv == 0x00) { + // Turn off LED. sl_led_turn_off(SL_SIMPLE_LED_INSTANCE(0)); app_log_info("LED off." APP_LOG_NL); } else { + // Blink LED. sl_led_turn_on(SL_SIMPLE_LED_INSTANCE(0)); app_log_info("LED on." APP_LOG_NL); + sc = sl_simple_timer_start(&led_timer, + LED_TIMEOUT, + led_timer_cb, + NO_CALLBACK_DATA, + false); + app_assert_status(sc); } } break; @@ -311,6 +341,8 @@ void sl_bt_on_event(sl_bt_msg_t *evt) // CBAP Peripheral event handler. void sl_bt_cbap_peripheral_on_event(sl_bt_cbap_peripheral_state_t status) { + sl_status_t sc; + switch (status) { case SL_BT_CBAP_PERIPHERAL_IDLE: break; @@ -325,6 +357,15 @@ void sl_bt_cbap_peripheral_on_event(sl_bt_cbap_peripheral_state_t status) case SL_BT_CBAP_PERIPHERAL_DONE: app_log_info("CBAP procedure complete." APP_LOG_NL); + save_connection_info(); + clear_connection_info(); + print_trusted_devices(); + + // Restart advertising and enable connections + sc = sl_bt_legacy_advertiser_start(advertising_set_handle, + sl_bt_advertiser_connectable_scannable); + app_assert_status(sc); + app_log_info("Advertising started." APP_LOG_NL); break; default: @@ -372,13 +413,22 @@ void sl_bt_cbap_central_on_event(sl_bt_cbap_central_state_t status) case SL_BT_CBAP_CENTRAL_DONE: { app_log_info("CBAP procedure complete." APP_LOG_NL); - // Turn on LED on peripheral - uint8_t led_on = 0x01; - sc = sl_bt_gatt_write_characteristic_value(connection, + // Blink LED on peripheral + uint8_t led = 0x01; + sc = sl_bt_gatt_write_characteristic_value(candidate_device.connection_handle, gattdb_aio_digital_out, - sizeof(led_on), - &led_on); + sizeof(led), + &led); app_assert_status(sc); + + save_connection_info(); + clear_connection_info(); + print_trusted_devices(); + + // Start scanning + sc = sl_bt_scanner_start(sl_bt_scanner_scan_phy_1m, + sl_bt_scanner_discover_generic); + app_log_info("Scanning started." APP_LOG_NL); break; } @@ -387,16 +437,114 @@ void sl_bt_cbap_central_on_event(sl_bt_cbap_central_state_t status) } } +// Callback to handle CBAP process errors. +void sl_bt_on_cbap_error(void) +{ + sl_status_t sc; + app_log_info("CBAP procedure was aborted for connection %d." APP_LOG_NL, + candidate_device.connection_handle); + + sc = sl_bt_connection_close(candidate_device.connection_handle); + app_log_status_error(sc); + clear_connection_info(); + + switch (role) { + case SL_BT_CBAP_ROLE_PERIPHERAL: + // Restart advertising and enable connections + sc = sl_bt_legacy_advertiser_start(advertising_set_handle, + sl_bt_advertiser_connectable_scannable); + app_assert_status(sc); + app_log_info("Advertising started." APP_LOG_NL); + break; + + case SL_BT_CBAP_ROLE_CENTRAL: + // Start scanning + sc = sl_bt_scanner_start(sl_bt_scanner_scan_phy_1m, + sl_bt_scanner_discover_generic); + app_assert_status(sc); + app_log_info("Scanning started." APP_LOG_NL); + break; + + default: + app_assert_status_f(SL_STATUS_INVALID_STATE, "Invalid role!"); + break; + } +} + +/**************************************************************************//** + * Clears candidate device. + *****************************************************************************/ +static void clear_connection_info(void) +{ + candidate_device.connection_handle = SL_BT_INVALID_CONNECTION_HANDLE; + for (uint8_t i = 0; i < sizeof(bd_addr); i++) { + candidate_device.address.addr[i] = 0xff; + } +} + +/**************************************************************************//** + * Adds the candidate device to the trusted devices array. + *****************************************************************************/ +static void save_connection_info(void) +{ + // Find next available slot + int index = -1; + for (int i = 0; i < SL_BT_CONFIG_MAX_CONNECTIONS; i++) { + if (trusted_devices[i].connection_handle == SL_BT_INVALID_CONNECTION_HANDLE) { + index = i; + break; + } + } + if (index == -1) { + app_log_error("Connection array is full." APP_LOG_NL); + return; + } + + // Save connection parameters + trusted_devices[index].connection_handle = candidate_device.connection_handle; + trusted_devices[index].address = candidate_device.address; + + app_log_info("Trusted device [%d] added." APP_LOG_NL, + trusted_devices[index].connection_handle); +} + +/**************************************************************************//** + * Logs the connection handle and the Bluetooth address of the trusted devices. + *****************************************************************************/ +static void print_trusted_devices(void) +{ + bool found = false; + app_log_info("List of trusted connections:" APP_LOG_NL); + + for (int i = 0; i < SL_BT_CONFIG_MAX_CONNECTIONS; i++) { + if (trusted_devices[i].connection_handle != SL_BT_INVALID_CONNECTION_HANDLE) { + found = true; + app_log_info(" Connection handle: %d Address: %02X:%02X:%02X:%02X:%02X:%02X" APP_LOG_NL, + trusted_devices[i].connection_handle, + trusted_devices[i].address.addr[5], + trusted_devices[i].address.addr[4], + trusted_devices[i].address.addr[3], + trusted_devices[i].address.addr[2], + trusted_devices[i].address.addr[1], + trusted_devices[i].address.addr[0]); + } + } + + if (!found) { + app_log_info(" None." APP_LOG_NL); + } +} + /**************************************************************************//** * Convert address string to address data bytes. * @param[in] addess_str Address string - * @param[out] address address byte array + * @param[out] address Bluetooth address byte array * @return true if operation was successful *****************************************************************************/ -static bool decode_address(char *addess_str, uint8_t *address) +static bool decode_address(char *addess_str, bd_addr *address) { uint8_t retval; - unsigned int address_cache[BT_ADDR_LEN]; + unsigned int address_cache[sizeof(bd_addr)]; retval = sscanf(addess_str, "%02X:%02X:%02X:%02X:%02X:%02X", &address_cache[5], @@ -406,13 +554,13 @@ static bool decode_address(char *addess_str, uint8_t *address) &address_cache[1], &address_cache[0]); - if (retval != BT_ADDR_LEN) { + if (retval != sizeof(bd_addr)) { app_log_error("Invalid Bluetooth address." APP_LOG_NL); return false; } - for (int i = 0; i < BT_ADDR_LEN; i++) { - address[i] = (uint8_t)(address_cache[i]); + for (uint8_t i = 0; i < sizeof(bd_addr); i++) { + address->addr[i] = (uint8_t)(address_cache[i]); } return true; } @@ -422,11 +570,18 @@ static bool decode_address(char *addess_str, uint8_t *address) * @param[in] scan_report Scan report coming from the Bluetooth stack event. * return true if a connection should be established with the device. *****************************************************************************/ -bool check_scan_report(sl_bt_evt_scanner_scan_report_t *scan_report) +bool check_scan_report(sl_bt_evt_scanner_legacy_advertisement_report_t *scan_report) { + // Check if there is a connection with this device already + for (int i = 0; i < SL_BT_CONFIG_MAX_CONNECTIONS; i++) { + if (memcmp(scan_report->address.addr, trusted_devices[i].address.addr, sizeof(bd_addr)) == 0) { + return false; + } + } + // If target defined, check the address if (peripheral_target_defined - && memcmp(scan_report->address.addr, peripheral_target_addr, BT_ADDR_LEN) != 0) { + && memcmp(scan_report->address.addr, peripheral_target_addr.addr, sizeof(bd_addr)) != 0) { return false; // Target device is defined but with different address. } @@ -434,3 +589,17 @@ bool check_scan_report(sl_bt_evt_scanner_scan_report_t *scan_report) return sl_bt_cbap_find_service_in_advertisement(scan_report->data.data, scan_report->data.len); } + +/***************************************************************************//** + * Timer Callback. + * @param[in] handle pointer to handle instance + * @param[in] data pointer to input data + ******************************************************************************/ +static void led_timer_cb(sl_simple_timer_t *handle, void *data) +{ + (void)handle; + (void)data; + + sl_led_turn_off(SL_SIMPLE_LED_INSTANCE(0)); + app_log_info("LED off." APP_LOG_NL); +} diff --git a/app/bluetooth/example/bt_soc_cbap/bt_soc_cbap.slcp b/app/bluetooth/example/bt_soc_cbap/bt_soc_cbap.slcp index fb40e7b842..1c3bd11c9d 100644 --- a/app/bluetooth/example/bt_soc_cbap/bt_soc_cbap.slcp +++ b/app/bluetooth/example/bt_soc_cbap/bt_soc_cbap.slcp @@ -21,7 +21,7 @@ component: - id: bluetooth_feature_connection - id: bluetooth_feature_gatt - id: bluetooth_feature_gatt_server - - id: bluetooth_feature_scanner + - id: bluetooth_feature_legacy_scanner - id: bluetooth_feature_sm - id: bluetooth_feature_system - id: in_place_ota_dfu @@ -34,6 +34,7 @@ component: - id: simple_led instance: - led0 + - id: simple_timer - id: cbap source: @@ -72,7 +73,7 @@ configuration: - name: SL_HEAP_SIZE value: "15000" - name: SL_PSA_KEY_USER_SLOT_COUNT - value: "0" + value: "1" condition: - psa_crypto - name: SL_BOARD_ENABLE_VCOM @@ -82,6 +83,9 @@ configuration: - name: APP_LOG_LEVEL_FILTER_THRESHOLD value: APP_LOG_LEVEL_INFO +requires: + - name: device_security_vault + tag: - hardware:rf:band:2400 - hardware:device:flash:512 diff --git a/app/bluetooth/example/bt_soc_csr_generator/bt_soc_csr_generator.slcp b/app/bluetooth/example/bt_soc_csr_generator/bt_soc_csr_generator.slcp index e53e864821..aae22294c1 100644 --- a/app/bluetooth/example/bt_soc_csr_generator/bt_soc_csr_generator.slcp +++ b/app/bluetooth/example/bt_soc_csr_generator/bt_soc_csr_generator.slcp @@ -102,6 +102,10 @@ configuration: condition: - psa_crypto +requires: + - name: device_supports_bluetooth + - name: device_security_vault + tag: - hardware:device:flash:512 - hardware:device:ram:32 diff --git a/app/bluetooth/example/bt_soc_dtm/bt_soc_dtm.slcp b/app/bluetooth/example/bt_soc_dtm/bt_soc_dtm.slcp index 81be841852..a00e4d700e 100644 --- a/app/bluetooth/example/bt_soc_dtm/bt_soc_dtm.slcp +++ b/app/bluetooth/example/bt_soc_dtm/bt_soc_dtm.slcp @@ -22,7 +22,6 @@ component: - id: bluetooth_feature_connection - id: bluetooth_feature_gatt - id: bluetooth_feature_gatt_server - - id: bluetooth_feature_scanner - id: bluetooth_feature_sm - id: bluetooth_feature_system - id: bluetooth_feature_test diff --git a/app/bluetooth/example/bt_soc_empty/bt_soc_empty.slcp b/app/bluetooth/example/bt_soc_empty/bt_soc_empty.slcp index a169e957b5..8a927165ef 100644 --- a/app/bluetooth/example/bt_soc_empty/bt_soc_empty.slcp +++ b/app/bluetooth/example/bt_soc_empty/bt_soc_empty.slcp @@ -23,7 +23,7 @@ component: - id: bluetooth_feature_connection - id: bluetooth_feature_gatt - id: bluetooth_feature_gatt_server - - id: bluetooth_feature_scanner + - id: bluetooth_feature_legacy_scanner - id: bluetooth_feature_sm - id: bluetooth_feature_system - id: in_place_ota_dfu diff --git a/app/bluetooth/example/bt_soc_ibeacon/bt_soc_ibeacon.slcp b/app/bluetooth/example/bt_soc_ibeacon/bt_soc_ibeacon.slcp index 84663aa669..de24f06ce7 100644 --- a/app/bluetooth/example/bt_soc_ibeacon/bt_soc_ibeacon.slcp +++ b/app/bluetooth/example/bt_soc_ibeacon/bt_soc_ibeacon.slcp @@ -22,9 +22,7 @@ component: - id: gatt_configuration - id: bluetooth_feature_legacy_advertiser - id: bluetooth_feature_connection - - id: bluetooth_feature_gatt - id: bluetooth_feature_gatt_server - - id: bluetooth_feature_scanner - id: bluetooth_feature_sm - id: bluetooth_feature_system - id: app_assert diff --git a/app/bluetooth/example/bt_soc_iop_test/app.c b/app/bluetooth/example/bt_soc_iop_test/app.c index 06ea2c1c42..ecfa5ba4a3 100644 --- a/app/bluetooth/example/bt_soc_iop_test/app.c +++ b/app/bluetooth/example/bt_soc_iop_test/app.c @@ -135,7 +135,7 @@ void sl_bt_on_event(sl_bt_msg_t* evt) // Generate data for advertising sc = sl_bt_legacy_advertiser_generate_data(advertising_set_handle, - advertiser_general_discoverable); + sl_bt_advertiser_general_discoverable); app_log_status_error(sc); // Default advertisement parameters: 32 (20 ms) interval. Other optional @@ -149,7 +149,7 @@ void sl_bt_on_event(sl_bt_msg_t* evt) // Start advertising and enable connections. sc = sl_bt_legacy_advertiser_start(advertising_set_handle, - advertiser_connectable_scannable); + sl_bt_advertiser_connectable_scannable); app_assert_status(sc); if (sc == SL_STATUS_OK) { @@ -251,22 +251,22 @@ void sl_bt_on_event(sl_bt_msg_t* evt) (int)supv_timeout); switch (evt->data.evt_connection_parameters.security_mode) { - case connection_mode1_level1: { + case sl_bt_connection_mode1_level1: { app_log_info("Connection security: No Security." APP_LOG_NL); break; } - case connection_mode1_level2: { + case sl_bt_connection_mode1_level2: { app_log_info("Connection security: Unauthenticated pairing." APP_LOG_NL); break; } - case connection_mode1_level3: { + case sl_bt_connection_mode1_level3: { app_log_info("Connection security: Authenticated pairing." APP_LOG_NL); break; } - case connection_mode1_level4: { + case sl_bt_connection_mode1_level4: { app_log_info("Connection security: Bonded." APP_LOG_NL); break; } @@ -372,12 +372,12 @@ void sl_bt_on_event(sl_bt_msg_t* evt) // Generate data for advertising sc = sl_bt_legacy_advertiser_generate_data(advertising_set_handle, - advertiser_general_discoverable); + sl_bt_advertiser_general_discoverable); app_log_status_error(sc); // Restart advertising. sc = sl_bt_legacy_advertiser_start(advertising_set_handle, - advertiser_connectable_scannable); + sl_bt_advertiser_connectable_scannable); app_log_status_error(sc); if (sc == SL_STATUS_OK) { diff --git a/app/bluetooth/example/bt_soc_thermometer_client/app.c b/app/bluetooth/example/bt_soc_thermometer_client/app.c index 15516e0702..882bb54c5f 100644 --- a/app/bluetooth/example/bt_soc_thermometer_client/app.c +++ b/app/bluetooth/example/bt_soc_thermometer_client/app.c @@ -50,10 +50,6 @@ #define CONN_MIN_CE_LENGTH 0 #define CONN_MAX_CE_LENGTH 0xffff -#define SCAN_INTERVAL 16 //10ms -#define SCAN_WINDOW 16 //10ms -#define SCAN_PASSIVE 0 - #define TEMP_INVALID NAN #define UNIT_INVALID ('?') #define UNIT_CELSIUS ('C') @@ -183,12 +179,7 @@ void sl_bt_on_event(sl_bt_msg_t* evt) evt->data.evt_system_boot.build); // Print bluetooth address. print_bluetooth_address(); - // Set passive scanning on 1Mb PHY - sc = sl_bt_scanner_set_mode(sl_bt_gap_1m_phy, SCAN_PASSIVE); - app_assert_status(sc); - // Set scan interval and scan window - sc = sl_bt_scanner_set_timing(sl_bt_gap_1m_phy, SCAN_INTERVAL, SCAN_WINDOW); - app_assert_status(sc); + // Set the default connection parameters for subsequent connections sc = sl_bt_connection_set_default_parameters(CONN_INTERVAL_MIN, CONN_INTERVAL_MAX, @@ -198,7 +189,7 @@ void sl_bt_on_event(sl_bt_msg_t* evt) CONN_MAX_CE_LENGTH); app_assert_status(sc); // Start scanning - looking for thermometer devices - sc = sl_bt_scanner_start(sl_bt_gap_1m_phy, sl_bt_scanner_discover_generic); + sc = sl_bt_scanner_start(sl_bt_gap_phy_1m, sl_bt_scanner_discover_generic); app_assert_status_f(sc, "Failed to start discovery #1\n"); conn_state = scanning; @@ -207,20 +198,21 @@ void sl_bt_on_event(sl_bt_msg_t* evt) // ------------------------------- // This event is generated when an advertisement packet or a scan response // is received from a responder - case sl_bt_evt_scanner_scan_report_id: + case sl_bt_evt_scanner_legacy_advertisement_report_id: // Parse advertisement packets - if (evt->data.evt_scanner_scan_report.packet_type == 0) { + if (evt->data.evt_scanner_legacy_advertisement_report.event_flags + == (SL_BT_SCANNER_EVENT_FLAG_CONNECTABLE | SL_BT_SCANNER_EVENT_FLAG_SCANNABLE)) { // If a thermometer advertisement is found... - if (find_service_in_advertisement(&(evt->data.evt_scanner_scan_report.data.data[0]), - evt->data.evt_scanner_scan_report.data.len) != 0) { + if (find_service_in_advertisement(&(evt->data.evt_scanner_legacy_advertisement_report.data.data[0]), + evt->data.evt_scanner_legacy_advertisement_report.data.len) != 0) { // then stop scanning for a while sc = sl_bt_scanner_stop(); app_assert_status(sc); // and connect to that device if (active_connections_num < SL_BT_CONFIG_MAX_CONNECTIONS) { - sc = sl_bt_connection_open(evt->data.evt_scanner_scan_report.address, - evt->data.evt_scanner_scan_report.address_type, - sl_bt_gap_1m_phy, + sc = sl_bt_connection_open(evt->data.evt_scanner_legacy_advertisement_report.address, + evt->data.evt_scanner_legacy_advertisement_report.address_type, + sl_bt_gap_phy_1m, NULL); app_assert_status(sc); conn_state = opening; @@ -307,7 +299,7 @@ void sl_bt_on_event(sl_bt_msg_t* evt) // and we can connect to more devices if (active_connections_num < SL_BT_CONFIG_MAX_CONNECTIONS) { // start scanning again to find new devices - sc = sl_bt_scanner_start(sl_bt_gap_1m_phy, sl_bt_scanner_discover_generic); + sc = sl_bt_scanner_start(sl_bt_gap_phy_1m, sl_bt_scanner_discover_generic); app_assert_status_f(sc, "Failed to start discovery #2\n"); conn_state = scanning; @@ -325,7 +317,7 @@ void sl_bt_on_event(sl_bt_msg_t* evt) remove_connection(evt->data.evt_connection_closed.connection); if (conn_state != scanning) { // start scanning again to find new devices - sc = sl_bt_scanner_start(sl_bt_gap_1m_phy, sl_bt_scanner_discover_generic); + sc = sl_bt_scanner_start(sl_bt_gap_phy_1m, sl_bt_scanner_discover_generic); app_assert_status_f(sc, "Failed to start discovery #3\n"); conn_state = scanning; diff --git a/app/bluetooth/example/bt_soc_thermometer_client/bt_soc_thermometer_client.slcp b/app/bluetooth/example/bt_soc_thermometer_client/bt_soc_thermometer_client.slcp index da579acf0f..f9ff781dcb 100644 --- a/app/bluetooth/example/bt_soc_thermometer_client/bt_soc_thermometer_client.slcp +++ b/app/bluetooth/example/bt_soc_thermometer_client/bt_soc_thermometer_client.slcp @@ -22,7 +22,7 @@ component: - id: bluetooth_feature_connection - id: bluetooth_feature_gatt - id: bluetooth_feature_gatt_server - - id: bluetooth_feature_scanner + - id: bluetooth_feature_legacy_scanner - id: bluetooth_feature_system - id: bluetooth_feature_power_control - id: in_place_ota_dfu diff --git a/app/bluetooth/example/bt_soc_thunderboard/app.c b/app/bluetooth/example/bt_soc_thunderboard/app.c index aba300a8ee..c549876624 100644 --- a/app/bluetooth/example/bt_soc_thunderboard/app.c +++ b/app/bluetooth/example/bt_soc_thunderboard/app.c @@ -130,8 +130,7 @@ static void sensor_deinit(void); void app_init(void) { - app_log_info("Thuderboard demo initialised"); - app_log_nl(); + app_log_info("Thuderboard demo initialised" APP_LOG_NL); sl_power_supply_probe(); shutdown_start_timer(); #if defined(BOARD_RGBLED_COUNT) && (BOARD_RGBLED_COUNT > 0) @@ -176,23 +175,21 @@ void sl_bt_on_event(sl_bt_msg_t *evt) (uint8_t *)fw_rev); app_log_status_error(sc); // Print boot message. - app_log_info("Bluetooth stack booted: v%d.%d.%d-b%d", + app_log_info("Bluetooth stack booted: v%d.%d.%d-b%d" APP_LOG_NL, evt->data.evt_system_boot.major, evt->data.evt_system_boot.minor, evt->data.evt_system_boot.patch, evt->data.evt_system_boot.build); - app_log_nl(); sc = sl_bt_system_get_identity_address(&address, &address_type); app_assert_status(sc); app_log_info("Bluetooth %s address: %02X:%02X:%02X:%02X:%02X:%02X", - address_type ? "static random" : "public device", + address_type ? "static random" : "public device" APP_LOG_NL, address.addr[5], address.addr[4], address.addr[3], address.addr[2], address.addr[1], address.addr[0]); - app_log_nl(); unique_id = 0xFFFFFF & *((uint32_t*) address.addr); // Pad and reverse unique ID to get System ID @@ -216,8 +213,7 @@ void sl_bt_on_event(sl_bt_msg_t *evt) // ------------------------------- case sl_bt_evt_connection_opened_id: - app_log_info("Connection opened"); - app_log_nl(); + app_log_info("Connection opened" APP_LOG_NL); advertise_stop(); shutdown_stop_timer(); sensor_init(); @@ -225,8 +221,7 @@ void sl_bt_on_event(sl_bt_msg_t *evt) // ------------------------------- case sl_bt_evt_connection_closed_id: - app_log_info("Connection closed"); - app_log_nl(); + app_log_info("Connection closed" APP_LOG_NL); shutdown_start_timer(); sensor_deinit(); advertise_start(); @@ -295,29 +290,25 @@ static void sensor_init(void) #ifdef SL_CATALOG_SENSOR_HALL_PRESENT sc = sl_sensor_hall_init(); if (sc != SL_STATUS_OK) { - app_log_warning("Hall sensor initialization failed."); - app_log_nl(); + app_log_warning("Hall sensor initialization failed." APP_LOG_NL); } #endif // SL_CATALOG_SENSOR_HALL_PRESENT #ifdef SL_CATALOG_SENSOR_LIGHT_PRESENT sc = sl_sensor_light_init(); if (sc != SL_STATUS_OK) { - app_log_warning("Ambient light and UV index sensor initialization failed."); - app_log_nl(); + app_log_warning("Ambient light and UV index sensor initialization failed." APP_LOG_NL); } #endif // SL_CATALOG_SENSOR_LIGHT_PRESENT #ifdef SL_CATALOG_SENSOR_LUX_PRESENT sc = sl_sensor_lux_init(); if (sc != SL_STATUS_OK) { - app_log_warning("Ambient light sensor initialization failed."); - app_log_nl(); + app_log_warning("Ambient light sensor initialization failed." APP_LOG_NL); } #endif // SL_CATALOG_SENSOR_LUX_PRESENT #ifdef SL_CATALOG_SENSOR_RHT_PRESENT sc = sl_sensor_rht_init(); if (sc != SL_STATUS_OK) { - app_log_warning("Relative Humidity and Temperature sensor initialization failed."); - app_log_nl(); + app_log_warning("Relative Humidity and Temperature sensor initialization failed." APP_LOG_NL); } #endif // SL_CATALOG_SENSOR_RHT_PRESENT #ifdef SL_CATALOG_SENSOR_IMU_PRESENT @@ -326,24 +317,21 @@ static void sensor_init(void) #ifdef SL_CATALOG_SENSOR_PRESSURE_PRESENT sc = sl_sensor_pressure_init(); if (sc != SL_STATUS_OK) { - app_log_warning("Air Pressure sensor initialization failed."); - app_log_nl(); + app_log_warning("Air Pressure sensor initialization failed." APP_LOG_NL); } #endif // SL_CATALOG_SENSOR_PRESSURE_PRESENT #ifdef SL_CATALOG_SENSOR_GAS_PRESENT if (!sl_power_supply_is_low_power()) { sc = sl_sensor_gas_init(); if (sc != SL_STATUS_OK) { - app_log_warning("Air quality sensor initialization failed."); - app_log_nl(); + app_log_warning("Air quality sensor initialization failed." APP_LOG_NL); } } #endif // SL_CATALOG_SENSOR_GAS_PRESENT #ifdef SL_CATALOG_SENSOR_SOUND_PRESENT sc = sl_sensor_sound_init(); if (sc != SL_STATUS_OK) { - app_log_warning("Sound level sensor initialization failed."); - app_log_nl(); + app_log_warning("Sound level sensor initialization failed." APP_LOG_NL); } #endif // SL_CATALOG_SENSOR_SOUND_PRESENT } @@ -389,8 +377,7 @@ uint8_t sl_gatt_service_battery_get_level(void) { uint8_t bat_level; bat_level = sl_power_supply_get_battery_level(); - app_log_info("Battery level = %d %%", bat_level); - app_log_nl(); + app_log_info("Battery level = %d %%" APP_LOG_NL, bat_level); return bat_level; } @@ -406,14 +393,11 @@ sl_status_t sl_gatt_service_hall_get(float *field_strength, bool *alert, bool *t sl_status_t sc; sc = sl_sensor_hall_get(field_strength, alert, tamper); if (SL_STATUS_OK == sc) { - app_log_info("Magnetic Flux = %4.3f mT", *field_strength); - app_log_nl(); + app_log_info("Magnetic Flux = %4.3f mT" APP_LOG_NL, *field_strength); } else if (SL_STATUS_NOT_INITIALIZED == sc) { - app_log_info("Hall sensor is not initialized."); - app_log_nl(); + app_log_info("Hall sensor is not initialized." APP_LOG_NL); } else { - app_log_status_error_f(sc, "Hall sensor measurement failed"); - app_log_nl(); + app_log_status_error_f(sc, "Hall sensor measurement failed" APP_LOG_NL); } return sc; } @@ -425,16 +409,12 @@ sl_status_t sl_gatt_service_light_get(float *lux, float *uvi) sl_status_t sc; sc = sl_sensor_light_get(lux, uvi); if (SL_STATUS_OK == sc) { - app_log_info("Amb light = %f Lux", *lux); - app_log_nl(); - app_log_info("UV Index = %d", *uvi); - app_log_nl(); + app_log_info("Amb light = %f Lux" APP_LOG_NL, *lux); + app_log_info("UV Index = %d" APP_LOG_NL, *uvi); } else if (SL_STATUS_NOT_INITIALIZED == sc) { - app_log_info("Ambient light and UV index sensor is not initialized."); - app_log_nl(); + app_log_info("Ambient light and UV index sensor is not initialized." APP_LOG_NL); } else { - app_log_status_error_f(sc, "Light sensor measurement failed"); - app_log_nl(); + app_log_status_error_f(sc, "Light sensor measurement failed" APP_LOG_NL); } return sc; } @@ -448,8 +428,7 @@ sl_status_t sl_gatt_service_lux_get(float *lux) if (SL_STATUS_OK == sc) { app_log_info("Amb light = %f Lux\r\n", *lux); } else if (SL_STATUS_NOT_INITIALIZED == sc) { - app_log_info("Ambient light sensor is not initialized."); - app_log_nl(); + app_log_info("Ambient light sensor is not initialized." APP_LOG_NL); } else { app_log_status_error_f(sc, "Light sensor measurement failed\n"); } @@ -463,16 +442,12 @@ sl_status_t sl_gatt_service_rht_get(uint32_t *rh, int32_t *t) sl_status_t sc; sc = sl_sensor_rht_get(rh, t); if (SL_STATUS_OK == sc) { - app_log_info("Humidity = %3.2f %%RH", (float)*rh / 1000.0f); - app_log_nl(); - app_log_info("Temp = %3.2f C", (float)*t / 1000.0f); - app_log_nl(); + app_log_info("Humidity = %3.2f %%RH" APP_LOG_NL, (float)*rh / 1000.0f); + app_log_info("Temp = %3.2f C" APP_LOG_NL, (float)*t / 1000.0f); } else if (SL_STATUS_NOT_INITIALIZED == sc) { - app_log_info("Relative Humidity and Temperature sensor is not initialized."); - app_log_nl(); + app_log_info("Relative Humidity and Temperature sensor is not initialized." APP_LOG_NL); } else { - app_log_status_error_f(sc, "RHT sensor measurement failed"); - app_log_nl(); + app_log_status_error_f(sc, "RHT sensor measurement failed" APP_LOG_NL); } return sc; } @@ -484,13 +459,10 @@ sl_status_t sl_gatt_service_imu_get(int16_t ovec[3], int16_t avec[3]) sl_status_t sc; sc = sl_sensor_imu_get(ovec, avec); if (SL_STATUS_OK == sc) { - app_log_info("IMU: ORI : %04d,%04d,%04d", ovec[0], ovec[1], ovec[2]); - app_log_nl(); - app_log_info("IMU: ACC : %04d,%04d,%04d", avec[0], avec[1], avec[2]); - app_log_nl(); + app_log_info("IMU: ORI : %04d,%04d,%04d" APP_LOG_NL, ovec[0], ovec[1], ovec[2]); + app_log_info("IMU: ACC : %04d,%04d,%04d" APP_LOG_NL, avec[0], avec[1], avec[2]); } else if (SL_STATUS_NOT_INITIALIZED == sc) { - app_log_info("Inertial Measurement Unit sensor is not initialized."); - app_log_nl(); + app_log_info("Inertial Measurement Unit sensor is not initialized." APP_LOG_NL); } return sc; } @@ -500,11 +472,9 @@ sl_status_t sl_gatt_service_imu_calibrate(void) sl_status_t sc; sc = sl_sensor_imu_calibrate(); if (SL_STATUS_NOT_INITIALIZED == sc) { - app_log_info("Inertial Measurement Unit sensor is not initialized."); - app_log_nl(); + app_log_info("Inertial Measurement Unit sensor is not initialized." APP_LOG_NL); } else { - app_log_info("IMU calibration status: %d", sc); - app_log_nl(); + app_log_info("IMU calibration status: %d" APP_LOG_NL, sc); } return sc; } @@ -512,12 +482,10 @@ sl_status_t sl_gatt_service_imu_calibrate(void) void sl_gatt_service_imu_enable(bool enable) { sl_status_t sc; - app_log_info("IMU %sable", enable ? "en" : "dis"); - app_log_nl(); + app_log_info("IMU %sable" APP_LOG_NL, enable ? "en" : "dis"); sc = sl_sensor_imu_enable(enable); if (enable && SL_STATUS_OK != sc) { - app_log_warning("Inertial Measurement Unit sensor sensor initialization failed."); - app_log_nl(); + app_log_warning("Inertial Measurement Unit sensor sensor initialization failed." APP_LOG_NL); } } #endif @@ -527,8 +495,7 @@ void sl_gatt_service_rgb_set_led(uint8_t m, uint8_t r, uint8_t g, uint8_t b) { if (!sl_power_supply_is_low_power()) { rgb_led_set(m, r, g, b); - app_log_info("RGBLED write: m:%02x r:%02x g:%02x b:%02x", m, r, g, b); - app_log_nl(); + app_log_info("RGBLED write: m:%02x r:%02x g:%02x b:%02x" APP_LOG_NL, m, r, g, b); } } @@ -544,14 +511,11 @@ sl_status_t sl_gatt_service_pressure_get(float *pressure) sl_status_t sc; sc = sl_sensor_pressure_get(pressure); if (SL_STATUS_OK == sc) { - app_log_info("Pressure = %0.3f mbar", *pressure); - app_log_nl(); + app_log_info("Pressure = %0.3f mbar" APP_LOG_NL, *pressure); } else if (SL_STATUS_NOT_INITIALIZED == sc) { - app_log_info("Air Pressure sensor is not initialized."); - app_log_nl(); + app_log_info("Air Pressure sensor is not initialized." APP_LOG_NL); } else { - app_log_status_error_f(sc, "Pressure sensor measurement failed"); - app_log_nl(); + app_log_status_error_f(sc, "Pressure sensor measurement failed" APP_LOG_NL); } return sc; } @@ -564,16 +528,12 @@ sl_status_t sl_gatt_service_gas_get(uint16_t *eco2, uint16_t *tvoc) if (!sl_power_supply_is_low_power()) { sc = sl_sensor_gas_get(eco2, tvoc); if (SL_STATUS_OK == sc) { - app_log_info("eCO2 = %u ppm", (uint16_t)*eco2); - app_log_nl(); - app_log_info("TVOC = %u ppd", (uint16_t)*tvoc); - app_log_nl(); + app_log_info("eCO2 = %u ppm" APP_LOG_NL, (uint16_t)*eco2); + app_log_info("TVOC = %u ppd" APP_LOG_NL, (uint16_t)*tvoc); } else if (SL_STATUS_NOT_INITIALIZED == sc) { - app_log_info("Air quality sensor is not initialized."); - app_log_nl(); + app_log_info("Air quality sensor is not initialized." APP_LOG_NL); } else if (SL_STATUS_NOT_READY != sc) { - app_log_status_error_f(sc, "Air quality sensor measurement failed"); - app_log_nl(); + app_log_status_error_f(sc, "Air quality sensor measurement failed" APP_LOG_NL); } } return sc; @@ -586,14 +546,11 @@ sl_status_t sl_gatt_service_sound_get(float *sound_level) sl_status_t sc; sc = sl_sensor_sound_get(sound_level); if (SL_STATUS_OK == sc) { - app_log_info("Sound Level = %3.2f dBA", *sound_level); - app_log_nl(); + app_log_info("Sound Level = %3.2f dBA" APP_LOG_NL, *sound_level); } else if (SL_STATUS_NOT_INITIALIZED == sc) { - app_log_info("Sound level sensor is not initialized."); - app_log_nl(); + app_log_info("Sound level sensor is not initialized." APP_LOG_NL); } else { - app_log_status_error_f(sc, "Sound level measurement failed"); - app_log_nl(); + app_log_status_error_f(sc, "Sound level measurement failed" APP_LOG_NL); } return sc; } diff --git a/app/bluetooth/example/bt_soc_thunderboard/brd2601b/rgbled.c b/app/bluetooth/example/bt_soc_thunderboard/brd2601b/rgbled.c index dcb52b9ed6..4da6c81d44 100644 --- a/app/bluetooth/example/bt_soc_thunderboard/brd2601b/rgbled.c +++ b/app/bluetooth/example/bt_soc_thunderboard/brd2601b/rgbled.c @@ -70,7 +70,7 @@ void rgb_led_init(void) void rgb_led_deinit(void) { - sl_simple_rgb_pwm_led_turn_off(sl_led_rgb.led_common.context); + sl_simple_rgb_pwm_led_turn_off(sl_simple_rgb_pwm_led_rgb_led0.led_common.context); } void rgb_led_set(uint8_t m, uint8_t r, uint8_t g, uint8_t b) @@ -82,18 +82,18 @@ void rgb_led_set(uint8_t m, uint8_t r, uint8_t g, uint8_t b) } if (m != 0) { - sl_simple_rgb_pwm_led_set_color(sl_led_rgb.led_common.context, + sl_simple_rgb_pwm_led_set_color(sl_simple_rgb_pwm_led_rgb_led0.led_common.context, light_levels[r], light_levels[g], light_levels[b]); } else { - sl_simple_rgb_pwm_led_turn_off(sl_led_rgb.led_common.context); + sl_simple_rgb_pwm_led_turn_off(sl_simple_rgb_pwm_led_rgb_led0.led_common.context); } } void adv_led_turn_on(void) { - sl_simple_rgb_pwm_led_set_color(sl_led_rgb.led_common.context, + sl_simple_rgb_pwm_led_set_color(sl_simple_rgb_pwm_led_rgb_led0.led_common.context, light_levels[ADV_LED_RED_INTENSITY], light_levels[ADV_LED_GREEN_INTENSITY], light_levels[ADV_LED_BLUE_INTENSITY]); @@ -101,10 +101,10 @@ void adv_led_turn_on(void) void adv_led_turn_off(void) { - sl_simple_rgb_pwm_led_turn_off(sl_led_rgb.led_common.context); + sl_simple_rgb_pwm_led_turn_off(sl_simple_rgb_pwm_led_rgb_led0.led_common.context); } void adv_led_toggle(void) { - sl_simple_rgb_pwm_led_toggle(sl_led_rgb.led_common.context); + sl_simple_rgb_pwm_led_toggle(sl_simple_rgb_pwm_led_rgb_led0.led_common.context); } diff --git a/app/bluetooth/example/bt_soc_thunderboard/brd2601b/sl_simple_rgb_pwm_led_led_rgb_config.h b/app/bluetooth/example/bt_soc_thunderboard/brd2601b/sl_simple_rgb_pwm_led_led_rgb_config.h deleted file mode 100644 index 47ac21f73c..0000000000 --- a/app/bluetooth/example/bt_soc_thunderboard/brd2601b/sl_simple_rgb_pwm_led_led_rgb_config.h +++ /dev/null @@ -1,95 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_LED_RGB_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_LED_RGB -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_LED_RGB] -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_PERIPHERAL TIMER1 -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_PERIPHERAL_NO 1 - -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_RED_CHANNEL 0 -// TIMER1 CC0 on PD02 -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_RED_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_RED_PIN 2 - -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_GREEN_CHANNEL 1 -// TIMER1 CC1 on PA04 -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_GREEN_PORT gpioPortA -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_GREEN_PIN 4 - -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_BLUE_CHANNEL 2 -// TIMER1 CC2 on PB00 -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_BLUE_PORT gpioPortB -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_BLUE_PIN 0 -// [TIMER_SL_SIMPLE_RGB_PWM_LED_LED_RGB]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_LED_RGB_CONFIG_H diff --git a/app/bluetooth/example/bt_soc_thunderboard/brd4166a/rgbled.c b/app/bluetooth/example/bt_soc_thunderboard/brd4166a/rgbled.c index f15961def3..7c0e790f9b 100644 --- a/app/bluetooth/example/bt_soc_thunderboard/brd4166a/rgbled.c +++ b/app/bluetooth/example/bt_soc_thunderboard/brd4166a/rgbled.c @@ -130,7 +130,7 @@ void rgb_led_set(uint8_t m, uint8_t r, uint8_t g, uint8_t b) { rgb_led_enable(false, (~m & BOARD_RGBLED_MASK)); rgb_led_enable(true, m); - sl_led_set_rgb_color(&sl_led_rgb, + sl_led_set_rgb_color(&sl_simple_rgb_pwm_led_rgb_led0, light_levels[r], light_levels[g], light_levels[b]); diff --git a/app/bluetooth/example/bt_soc_thunderboard/brd4166a/sl_simple_rgb_pwm_led_led_rgb_config.h b/app/bluetooth/example/bt_soc_thunderboard/brd4166a/sl_simple_rgb_pwm_led_led_rgb_config.h deleted file mode 100644 index ef7bc74060..0000000000 --- a/app/bluetooth/example/bt_soc_thunderboard/brd4166a/sl_simple_rgb_pwm_led_led_rgb_config.h +++ /dev/null @@ -1,99 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_LED_RGB_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_HIGH -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_HIGH - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_HIGH -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_HIGH - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_HIGH -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_HIGH -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_LED_RGB -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_LED_RGB] -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_PERIPHERAL TIMER1 -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_PERIPHERAL_NO 1 - -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_RED_CHANNEL 0 -// TIMER0 CC0 on PD11 -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_RED_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_RED_PIN 11 -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_RED_LOC 19 - -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_GREEN_CHANNEL 1 -// TIMER0 CC1 on PD12 -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_GREEN_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_GREEN_PIN 12 -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_GREEN_LOC 19 - -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_BLUE_CHANNEL 2 -// TIMER0 CC2 on PD13 -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_BLUE_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_BLUE_PIN 13 -#define SL_SIMPLE_RGB_PWM_LED_LED_RGB_BLUE_LOC 19 -// [TIMER_SL_SIMPLE_RGB_PWM_LED_LED_RGB]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_LED_RGB_CONFIG_H diff --git a/app/bluetooth/example/bt_soc_thunderboard/bt_soc_thunderboard_brd4166a.slcp b/app/bluetooth/example/bt_soc_thunderboard/bt_soc_thunderboard_brd4166a.slcp index 248731dec7..7cfb9491e0 100644 --- a/app/bluetooth/example/bt_soc_thunderboard/bt_soc_thunderboard_brd4166a.slcp +++ b/app/bluetooth/example/bt_soc_thunderboard/bt_soc_thunderboard_brd4166a.slcp @@ -21,9 +21,7 @@ component: - id: gatt_configuration - id: bluetooth_feature_legacy_advertiser - id: bluetooth_feature_connection - - id: bluetooth_feature_gatt - id: bluetooth_feature_gatt_server - - id: bluetooth_feature_scanner - id: bluetooth_feature_sm - id: bluetooth_feature_system - id: in_place_ota_dfu @@ -72,7 +70,7 @@ component: - btn1 - id: simple_rgb_pwm_led instance: - - led_rgb + - rgb_led0 source: - path: advertise.c @@ -98,11 +96,6 @@ config_file: file_id: gatt_configuration_file_id path: gatt_configuration_brd4166a.btconf directory: btconf - - override: - component: simple_rgb_pwm_led - file_id: simple_rgb_pwm_led_config - instance: led_rgb - path: brd4166a/sl_simple_rgb_pwm_led_led_rgb_config.h other_file: - path: ../../script/create_bl_files.bat diff --git a/app/bluetooth/example/bt_soc_thunderboard/bt_soc_thunderboard_brd4184a.slcp b/app/bluetooth/example/bt_soc_thunderboard/bt_soc_thunderboard_brd4184a.slcp index f68e6a0ddb..af1ba830aa 100644 --- a/app/bluetooth/example/bt_soc_thunderboard/bt_soc_thunderboard_brd4184a.slcp +++ b/app/bluetooth/example/bt_soc_thunderboard/bt_soc_thunderboard_brd4184a.slcp @@ -21,9 +21,7 @@ component: - id: gatt_configuration - id: bluetooth_feature_legacy_advertiser - id: bluetooth_feature_connection - - id: bluetooth_feature_gatt - id: bluetooth_feature_gatt_server - - id: bluetooth_feature_scanner - id: bluetooth_feature_sm - id: bluetooth_feature_system - id: in_place_ota_dfu diff --git a/app/bluetooth/example/bt_soc_thunderboard/bt_soc_thunderboard_brd4184b.slcp b/app/bluetooth/example/bt_soc_thunderboard/bt_soc_thunderboard_brd4184b.slcp index d6ee2f7bc7..a8d6ddd929 100644 --- a/app/bluetooth/example/bt_soc_thunderboard/bt_soc_thunderboard_brd4184b.slcp +++ b/app/bluetooth/example/bt_soc_thunderboard/bt_soc_thunderboard_brd4184b.slcp @@ -21,9 +21,7 @@ component: - id: gatt_configuration - id: bluetooth_feature_legacy_advertiser - id: bluetooth_feature_connection - - id: bluetooth_feature_gatt - id: bluetooth_feature_gatt_server - - id: bluetooth_feature_scanner - id: bluetooth_feature_sm - id: bluetooth_feature_system - id: in_place_ota_dfu diff --git a/app/bluetooth/example/bt_soc_thunderboard/bt_soc_xg24_dev_kit_brd2601b.slcp b/app/bluetooth/example/bt_soc_thunderboard/bt_soc_xg24_dev_kit_brd2601b.slcp index d2614ac3cc..f35be7183b 100644 --- a/app/bluetooth/example/bt_soc_thunderboard/bt_soc_xg24_dev_kit_brd2601b.slcp +++ b/app/bluetooth/example/bt_soc_thunderboard/bt_soc_xg24_dev_kit_brd2601b.slcp @@ -21,9 +21,7 @@ component: - id: gatt_configuration - id: bluetooth_feature_legacy_advertiser - id: bluetooth_feature_connection - - id: bluetooth_feature_gatt - id: bluetooth_feature_gatt_server - - id: bluetooth_feature_scanner - id: bluetooth_feature_sm - id: bluetooth_feature_system - id: in_place_ota_dfu @@ -64,7 +62,7 @@ component: - btn1 - id: simple_rgb_pwm_led instance: - - led_rgb + - rgb_led0 source: - path: advertise.c @@ -90,11 +88,6 @@ config_file: file_id: gatt_configuration_file_id path: gatt_configuration_brd2601b.btconf directory: btconf - - override: - component: simple_rgb_pwm_led - file_id: simple_rgb_pwm_led_config - instance: led_rgb - path: brd2601b/sl_simple_rgb_pwm_led_led_rgb_config.h other_file: - path: ../../script/create_bl_files.bat diff --git a/app/bluetooth/example/bt_soc_voice/app.c b/app/bluetooth/example/bt_soc_voice/app.c index 848a552786..cdc98927a2 100644 --- a/app/bluetooth/example/bt_soc_voice/app.c +++ b/app/bluetooth/example/bt_soc_voice/app.c @@ -126,8 +126,8 @@ void sl_bt_on_event(sl_bt_msg_t *evt) evt->data.evt_system_boot.patch, evt->data.evt_system_boot.build); - // Set maximal MTU. - sc = sl_bt_gatt_set_max_mtu(250, &max_mtu_out); + // Set maximal MTU for GATT Server. + sc = sl_bt_gatt_server_set_max_mtu(250, &max_mtu_out); app_assert_status(sc); // Extract unique ID from BT Address. diff --git a/app/bluetooth/example/bt_soc_voice/bt_soc_voice.slcp b/app/bluetooth/example/bt_soc_voice/bt_soc_voice.slcp index cbb5dffd73..853644f247 100644 --- a/app/bluetooth/example/bt_soc_voice/bt_soc_voice.slcp +++ b/app/bluetooth/example/bt_soc_voice/bt_soc_voice.slcp @@ -21,9 +21,7 @@ component: - id: gatt_configuration - id: bluetooth_feature_legacy_advertiser - id: bluetooth_feature_connection - - id: bluetooth_feature_gatt - id: bluetooth_feature_gatt_server - - id: bluetooth_feature_scanner - id: bluetooth_feature_sm - id: bluetooth_feature_system - id: in_place_ota_dfu diff --git a/app/bluetooth/example/btmesh_ncp_empty/btmesh_ncp_empty.slcp b/app/bluetooth/example/btmesh_ncp_empty/btmesh_ncp_empty.slcp index 5df2e0e384..d50e36cb50 100644 --- a/app/bluetooth/example/btmesh_ncp_empty/btmesh_ncp_empty.slcp +++ b/app/bluetooth/example/btmesh_ncp_empty/btmesh_ncp_empty.slcp @@ -129,7 +129,7 @@ configuration: condition: - psa_crypto - name: SL_STACK_SIZE - value: "0x1200" + value: "0x1400" - name: SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE value: uartdrvFlowControlNone condition: diff --git a/app/bluetooth/example/btmesh_ncp_empty/btmesh_ncp_empty_xg22.slcp b/app/bluetooth/example/btmesh_ncp_empty/btmesh_ncp_empty_xg22.slcp index cd23e8b7a6..bed249fa9e 100644 --- a/app/bluetooth/example/btmesh_ncp_empty/btmesh_ncp_empty_xg22.slcp +++ b/app/bluetooth/example/btmesh_ncp_empty/btmesh_ncp_empty_xg22.slcp @@ -134,7 +134,7 @@ configuration: - name: SL_SIMPLE_COM_TX_BUF_SIZE value: "768" - name: SL_STACK_SIZE - value: "0xD00" + value: "0xE00" - name: SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE value: uartdrvFlowControlNone condition: diff --git a/app/bluetooth/example/btmesh_ncp_empty/dcd_config.btmeshconf b/app/bluetooth/example/btmesh_ncp_empty/dcd_config.btmeshconf index 69b4f33f23..3021489714 100644 --- a/app/bluetooth/example/btmesh_ncp_empty/dcd_config.btmeshconf +++ b/app/bluetooth/example/btmesh_ncp_empty/dcd_config.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x0000", - "vid": "0x0300", + "vid": "0x0301", "elements": [ { "name": "Primary Element", diff --git a/app/bluetooth/example/btmesh_ncp_empty/dcd_config_xg22.btmeshconf b/app/bluetooth/example/btmesh_ncp_empty/dcd_config_xg22.btmeshconf index ba5a194090..2d6ff4f487 100644 --- a/app/bluetooth/example/btmesh_ncp_empty/dcd_config_xg22.btmeshconf +++ b/app/bluetooth/example/btmesh_ncp_empty/dcd_config_xg22.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x0000", - "vid": "0x0300", + "vid": "0x0301", "elements": [ { "name": "Main", diff --git a/app/bluetooth/example/btmesh_soc_empty/btmesh_soc_empty.slcp b/app/bluetooth/example/btmesh_soc_empty/btmesh_soc_empty.slcp index c67d8eb596..837ba76887 100644 --- a/app/bluetooth/example/btmesh_soc_empty/btmesh_soc_empty.slcp +++ b/app/bluetooth/example/btmesh_soc_empty/btmesh_soc_empty.slcp @@ -72,7 +72,7 @@ configuration: condition: - psa_crypto - name: SL_STACK_SIZE - value: "0x1000" + value: "0x1200" tag: - hardware:device:flash:512 diff --git a/app/bluetooth/example/btmesh_soc_empty/dcd_config.btmeshconf b/app/bluetooth/example/btmesh_soc_empty/dcd_config.btmeshconf index 08f7e16039..8c41a98e6f 100644 --- a/app/bluetooth/example/btmesh_soc_empty/dcd_config.btmeshconf +++ b/app/bluetooth/example/btmesh_soc_empty/dcd_config.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x0001", - "vid": "0x0300", + "vid": "0x0301", "elements": [ { "name": "Main", diff --git a/app/bluetooth/example/btmesh_soc_hsl/btmesh_soc_hsl_brd2601b.slcp b/app/bluetooth/example/btmesh_soc_hsl/btmesh_soc_hsl_brd2601b.slcp index 7d4933d7b0..5de29abefe 100644 --- a/app/bluetooth/example/btmesh_soc_hsl/btmesh_soc_hsl_brd2601b.slcp +++ b/app/bluetooth/example/btmesh_soc_hsl/btmesh_soc_hsl_brd2601b.slcp @@ -53,7 +53,7 @@ component: - btn1 - id: simple_rgb_pwm_led instance: - - led_rgb + - rgb_led0 - id: simple_timer source: @@ -77,11 +77,6 @@ config_file: file_id: gatt_configuration_file_id path: gatt_configuration.btconf directory: btconf - - override: - component: simple_rgb_pwm_led - file_id: simple_rgb_pwm_led_config - instance: led_rgb - path: sl_simple_rgb_pwm_led_led_rgb_brd2601_config.h - override: component: btmesh_dcd_configuration file_id: dcd_configuration_file_id @@ -147,7 +142,7 @@ configuration: condition: - psa_crypto - name: SL_STACK_SIZE - value: "0x1300" + value: "0x1500" define: - name: SL_BTMESH_HSL_RGB_BRD2601 diff --git a/app/bluetooth/example/btmesh_soc_hsl/btmesh_soc_hsl_brd4166a.slcp b/app/bluetooth/example/btmesh_soc_hsl/btmesh_soc_hsl_brd4166a.slcp index f68010bf0b..062a624778 100644 --- a/app/bluetooth/example/btmesh_soc_hsl/btmesh_soc_hsl_brd4166a.slcp +++ b/app/bluetooth/example/btmesh_soc_hsl/btmesh_soc_hsl_brd4166a.slcp @@ -53,7 +53,7 @@ component: - btn1 - id: simple_rgb_pwm_led instance: - - led_rgb + - rgb_led0 - id: simple_timer source: @@ -77,11 +77,6 @@ config_file: file_id: gatt_configuration_file_id path: gatt_configuration.btconf directory: btconf - - override: - component: simple_rgb_pwm_led - file_id: simple_rgb_pwm_led_config - instance: led_rgb - path: sl_simple_rgb_pwm_led_led_rgb_brd4166_config.h - override: component: btmesh_dcd_configuration file_id: dcd_configuration_file_id @@ -147,7 +142,7 @@ configuration: condition: - psa_crypto - name: SL_STACK_SIZE - value: "0x1300" + value: "0x1500" define: - name: SL_BTMESH_HSL_RGB_BRD4166 diff --git a/app/bluetooth/example/btmesh_soc_hsl/btmesh_soc_hsl_display.slcp b/app/bluetooth/example/btmesh_soc_hsl/btmesh_soc_hsl_display.slcp index c8ae259499..ea837452b7 100644 --- a/app/bluetooth/example/btmesh_soc_hsl/btmesh_soc_hsl_display.slcp +++ b/app/bluetooth/example/btmesh_soc_hsl/btmesh_soc_hsl_display.slcp @@ -141,7 +141,7 @@ configuration: condition: - psa_crypto - name: SL_STACK_SIZE - value: "0x1300" + value: "0x1500" template_contribution: - name: cli_command diff --git a/app/bluetooth/example/btmesh_soc_hsl/btmesh_soc_hsl_log.slcp b/app/bluetooth/example/btmesh_soc_hsl/btmesh_soc_hsl_log.slcp index e9b26dff1b..3caceebebe 100644 --- a/app/bluetooth/example/btmesh_soc_hsl/btmesh_soc_hsl_log.slcp +++ b/app/bluetooth/example/btmesh_soc_hsl/btmesh_soc_hsl_log.slcp @@ -140,7 +140,7 @@ configuration: condition: - psa_crypto - name: SL_STACK_SIZE - value: "0x1300" + value: "0x1500" template_contribution: - name: cli_command diff --git a/app/bluetooth/example/btmesh_soc_hsl/dcd_config.btmeshconf b/app/bluetooth/example/btmesh_soc_hsl/dcd_config.btmeshconf index 20aba3b3f4..d987799001 100644 --- a/app/bluetooth/example/btmesh_soc_hsl/dcd_config.btmeshconf +++ b/app/bluetooth/example/btmesh_soc_hsl/dcd_config.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x0002", - "vid": "0x0300", + "vid": "0x0301", "elements": [ { "name": "Main", diff --git a/app/bluetooth/example/btmesh_soc_hsl/rgbled_brd2601.c b/app/bluetooth/example/btmesh_soc_hsl/rgbled_brd2601.c index 650db1101e..5eb78e3e26 100644 --- a/app/bluetooth/example/btmesh_soc_hsl/rgbled_brd2601.c +++ b/app/bluetooth/example/btmesh_soc_hsl/rgbled_brd2601.c @@ -60,7 +60,7 @@ void rgb_led_deinit(void) void rgb_led_set_rgb(uint8_t m, uint8_t r, uint8_t g, uint8_t b) { (void) m; - sl_led_set_rgb_color(&sl_led_rgb, + sl_led_set_rgb_color(&sl_simple_rgb_pwm_led_rgb_led0, (uint16_t)r, (uint16_t)g, (uint16_t)b); diff --git a/app/bluetooth/example/btmesh_soc_hsl/rgbled_brd4166.c b/app/bluetooth/example/btmesh_soc_hsl/rgbled_brd4166.c index 3d23d3ad2f..966e192142 100644 --- a/app/bluetooth/example/btmesh_soc_hsl/rgbled_brd4166.c +++ b/app/bluetooth/example/btmesh_soc_hsl/rgbled_brd4166.c @@ -124,7 +124,7 @@ void rgb_led_set_rgb(uint8_t m, uint8_t r, uint8_t g, uint8_t b) { rgb_led_enable(false, ~m); rgb_led_enable(true, m); - sl_led_set_rgb_color(&sl_led_rgb, + sl_led_set_rgb_color(&sl_simple_rgb_pwm_led_rgb_led0, (uint16_t)r, (uint16_t)g, (uint16_t)b); diff --git a/app/bluetooth/example/btmesh_soc_hsl/sl_simple_rgb_pwm_led_led_rgb_brd2601_config.h b/app/bluetooth/example/btmesh_soc_hsl/sl_simple_rgb_pwm_led_led_rgb_brd2601_config.h deleted file mode 100644 index f9e4730922..0000000000 --- a/app/bluetooth/example/btmesh_soc_hsl/sl_simple_rgb_pwm_led_led_rgb_brd2601_config.h +++ /dev/null @@ -1,93 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_INSTANCE_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_INSTANCE -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_INSTANCE] -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_PERIPHERAL TIMER1 -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_PERIPHERAL_NO 1 - -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_RED_CHANNEL 0 -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_RED_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_RED_PIN 2 - -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_GREEN_CHANNEL 1 -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_GREEN_PORT gpioPortA -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_GREEN_PIN 4 - -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_BLUE_CHANNEL 2 -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_BLUE_PORT gpioPortB -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_BLUE_PIN 0 -// [TIMER_SL_SIMPLE_RGB_PWM_LED_INSTANCE]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_INSTANCE_CONFIG_H diff --git a/app/bluetooth/example/btmesh_soc_hsl/sl_simple_rgb_pwm_led_led_rgb_brd4166_config.h b/app/bluetooth/example/btmesh_soc_hsl/sl_simple_rgb_pwm_led_led_rgb_brd4166_config.h deleted file mode 100644 index dccf063aba..0000000000 --- a/app/bluetooth/example/btmesh_soc_hsl/sl_simple_rgb_pwm_led_led_rgb_brd4166_config.h +++ /dev/null @@ -1,96 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_INSTANCE_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_HIGH - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_HIGH - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_HIGH -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_INSTANCE -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_INSTANCE] -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_PERIPHERAL TIMER1 -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_PERIPHERAL_NO 1 - -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_RED_CHANNEL 0 -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_RED_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_RED_PIN 11 - #define SL_SIMPLE_RGB_PWM_LED_INSTANCE_RED_LOC 19 - -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_GREEN_CHANNEL 1 -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_GREEN_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_GREEN_PIN 12 - #define SL_SIMPLE_RGB_PWM_LED_INSTANCE_GREEN_LOC 19 - -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_BLUE_CHANNEL 2 -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_BLUE_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_BLUE_PIN 13 - #define SL_SIMPLE_RGB_PWM_LED_INSTANCE_BLUE_LOC 19 -// [TIMER_SL_SIMPLE_RGB_PWM_LED_INSTANCE]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_INSTANCE_CONFIG_H diff --git a/app/bluetooth/example/btmesh_soc_light/btmesh_soc_light_brd2601b.slcp b/app/bluetooth/example/btmesh_soc_light/btmesh_soc_light_brd2601b.slcp index 2b415497b1..bd325548bf 100644 --- a/app/bluetooth/example/btmesh_soc_light/btmesh_soc_light_brd2601b.slcp +++ b/app/bluetooth/example/btmesh_soc_light/btmesh_soc_light_brd2601b.slcp @@ -53,7 +53,7 @@ component: - btn1 - id: simple_rgb_pwm_led instance: - - led_rgb + - rgb_led0 - id: simple_timer source: @@ -77,11 +77,6 @@ config_file: file_id: gatt_configuration_file_id path: gatt_configuration.btconf directory: btconf - - override: - component: simple_rgb_pwm_led - file_id: simple_rgb_pwm_led_config - instance: led_rgb - path: sl_simple_rgb_pwm_led_led_rgb_brd2601_config.h - override: component: btmesh_dcd_configuration file_id: dcd_configuration_file_id @@ -147,7 +142,7 @@ configuration: condition: - psa_crypto - name: SL_STACK_SIZE - value: "0x1300" + value: "0x1500" define: - name: SL_BTMESH_LIGHT_RGB_BRD2601 diff --git a/app/bluetooth/example/btmesh_soc_light/btmesh_soc_light_brd4166a.slcp b/app/bluetooth/example/btmesh_soc_light/btmesh_soc_light_brd4166a.slcp index 1835fd39e9..b873c186f0 100644 --- a/app/bluetooth/example/btmesh_soc_light/btmesh_soc_light_brd4166a.slcp +++ b/app/bluetooth/example/btmesh_soc_light/btmesh_soc_light_brd4166a.slcp @@ -53,7 +53,7 @@ component: - btn1 - id: simple_rgb_pwm_led instance: - - led_rgb + - rgb_led0 - id: simple_timer source: @@ -77,11 +77,6 @@ config_file: file_id: gatt_configuration_file_id path: gatt_configuration.btconf directory: btconf - - override: - component: simple_rgb_pwm_led - file_id: simple_rgb_pwm_led_config - instance: led_rgb - path: sl_simple_rgb_pwm_led_led_rgb_brd4166_config.h - override: component: btmesh_dcd_configuration file_id: dcd_configuration_file_id @@ -147,7 +142,7 @@ configuration: condition: - psa_crypto - name: SL_STACK_SIZE - value: "0x1300" + value: "0x1500" define: - name: SL_BTMESH_LIGHT_RGB_BRD4166 diff --git a/app/bluetooth/example/btmesh_soc_light/btmesh_soc_light_display.slcp b/app/bluetooth/example/btmesh_soc_light/btmesh_soc_light_display.slcp index 514e97f322..9c5ee77cc1 100644 --- a/app/bluetooth/example/btmesh_soc_light/btmesh_soc_light_display.slcp +++ b/app/bluetooth/example/btmesh_soc_light/btmesh_soc_light_display.slcp @@ -141,7 +141,7 @@ configuration: condition: - psa_crypto - name: SL_STACK_SIZE - value: "0x1300" + value: "0x1500" template_contribution: - name: cli_command diff --git a/app/bluetooth/example/btmesh_soc_light/btmesh_soc_light_log.slcp b/app/bluetooth/example/btmesh_soc_light/btmesh_soc_light_log.slcp index dedf38353c..4b3dee7beb 100644 --- a/app/bluetooth/example/btmesh_soc_light/btmesh_soc_light_log.slcp +++ b/app/bluetooth/example/btmesh_soc_light/btmesh_soc_light_log.slcp @@ -140,7 +140,7 @@ configuration: condition: - psa_crypto - name: SL_STACK_SIZE - value: "0x1300" + value: "0x1500" template_contribution: - name: cli_command diff --git a/app/bluetooth/example/btmesh_soc_light/dcd_config.btmeshconf b/app/bluetooth/example/btmesh_soc_light/dcd_config.btmeshconf index 491c563e72..35d55e388b 100644 --- a/app/bluetooth/example/btmesh_soc_light/dcd_config.btmeshconf +++ b/app/bluetooth/example/btmesh_soc_light/dcd_config.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x0003", - "vid": "0x0300", + "vid": "0x0301", "elements": [ { "name": "Main", diff --git a/app/bluetooth/example/btmesh_soc_light/rgbled_brd2601.c b/app/bluetooth/example/btmesh_soc_light/rgbled_brd2601.c index c23da4353a..792287a4b0 100644 --- a/app/bluetooth/example/btmesh_soc_light/rgbled_brd2601.c +++ b/app/bluetooth/example/btmesh_soc_light/rgbled_brd2601.c @@ -60,7 +60,7 @@ void rgb_led_deinit(void) void rgb_led_set_rgb(uint8_t m, uint8_t r, uint8_t g, uint8_t b) { (void) m; - sl_led_set_rgb_color(&sl_led_rgb, + sl_led_set_rgb_color(&sl_simple_rgb_pwm_led_rgb_led0, (uint16_t)r, (uint16_t)g, (uint16_t)b); diff --git a/app/bluetooth/example/btmesh_soc_light/rgbled_brd4166.c b/app/bluetooth/example/btmesh_soc_light/rgbled_brd4166.c index ced58c810e..3ac2688ec6 100644 --- a/app/bluetooth/example/btmesh_soc_light/rgbled_brd4166.c +++ b/app/bluetooth/example/btmesh_soc_light/rgbled_brd4166.c @@ -124,7 +124,7 @@ void rgb_led_set_rgb(uint8_t m, uint8_t r, uint8_t g, uint8_t b) { rgb_led_enable(false, ~m); rgb_led_enable(true, m); - sl_led_set_rgb_color(&sl_led_rgb, + sl_led_set_rgb_color(&sl_simple_rgb_pwm_led_rgb_led0, (uint16_t)r, (uint16_t)g, (uint16_t)b); diff --git a/app/bluetooth/example/btmesh_soc_light/sl_simple_rgb_pwm_led_led_rgb_brd2601_config.h b/app/bluetooth/example/btmesh_soc_light/sl_simple_rgb_pwm_led_led_rgb_brd2601_config.h deleted file mode 100644 index f9e4730922..0000000000 --- a/app/bluetooth/example/btmesh_soc_light/sl_simple_rgb_pwm_led_led_rgb_brd2601_config.h +++ /dev/null @@ -1,93 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_INSTANCE_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_INSTANCE -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_INSTANCE] -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_PERIPHERAL TIMER1 -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_PERIPHERAL_NO 1 - -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_RED_CHANNEL 0 -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_RED_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_RED_PIN 2 - -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_GREEN_CHANNEL 1 -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_GREEN_PORT gpioPortA -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_GREEN_PIN 4 - -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_BLUE_CHANNEL 2 -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_BLUE_PORT gpioPortB -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_BLUE_PIN 0 -// [TIMER_SL_SIMPLE_RGB_PWM_LED_INSTANCE]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_INSTANCE_CONFIG_H diff --git a/app/bluetooth/example/btmesh_soc_light/sl_simple_rgb_pwm_led_led_rgb_brd4166_config.h b/app/bluetooth/example/btmesh_soc_light/sl_simple_rgb_pwm_led_led_rgb_brd4166_config.h deleted file mode 100644 index dccf063aba..0000000000 --- a/app/bluetooth/example/btmesh_soc_light/sl_simple_rgb_pwm_led_led_rgb_brd4166_config.h +++ /dev/null @@ -1,96 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_INSTANCE_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_HIGH - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_HIGH - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_HIGH -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_INSTANCE -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_INSTANCE] -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_PERIPHERAL TIMER1 -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_PERIPHERAL_NO 1 - -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_RED_CHANNEL 0 -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_RED_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_RED_PIN 11 - #define SL_SIMPLE_RGB_PWM_LED_INSTANCE_RED_LOC 19 - -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_GREEN_CHANNEL 1 -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_GREEN_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_GREEN_PIN 12 - #define SL_SIMPLE_RGB_PWM_LED_INSTANCE_GREEN_LOC 19 - -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_BLUE_CHANNEL 2 -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_BLUE_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INSTANCE_BLUE_PIN 13 - #define SL_SIMPLE_RGB_PWM_LED_INSTANCE_BLUE_LOC 19 -// [TIMER_SL_SIMPLE_RGB_PWM_LED_INSTANCE]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_INSTANCE_CONFIG_H diff --git a/app/bluetooth/example/btmesh_soc_sensor_client/btmesh_soc_sensor_client_display.slcp b/app/bluetooth/example/btmesh_soc_sensor_client/btmesh_soc_sensor_client_display.slcp index afa46c5397..e7a1f99cd6 100644 --- a/app/bluetooth/example/btmesh_soc_sensor_client/btmesh_soc_sensor_client_display.slcp +++ b/app/bluetooth/example/btmesh_soc_sensor_client/btmesh_soc_sensor_client_display.slcp @@ -129,13 +129,7 @@ configuration: - name: SL_SIMPLE_BUTTON_ALLOW_LED_CONFLICT value: "1" - name: SL_STACK_SIZE - value: "0x1000" - unless: - - "device_sdid_205" - - name: SL_STACK_SIZE - value: "0xF00" - condition: - - "device_sdid_205" + value: "0x1300" template_contribution: - name: cli_command diff --git a/app/bluetooth/example/btmesh_soc_sensor_client/btmesh_soc_sensor_client_log.slcp b/app/bluetooth/example/btmesh_soc_sensor_client/btmesh_soc_sensor_client_log.slcp index 25853d7088..b999a7f96a 100644 --- a/app/bluetooth/example/btmesh_soc_sensor_client/btmesh_soc_sensor_client_log.slcp +++ b/app/bluetooth/example/btmesh_soc_sensor_client/btmesh_soc_sensor_client_log.slcp @@ -120,7 +120,7 @@ configuration: - name: SL_SIMPLE_BUTTON_ALLOW_LED_CONFLICT value: "1" - name: SL_STACK_SIZE - value: "0x1000" + value: "0x1200" template_contribution: - name: cli_command diff --git a/app/bluetooth/example/btmesh_soc_sensor_client/btmesh_soc_sensor_client_log_single.slcp b/app/bluetooth/example/btmesh_soc_sensor_client/btmesh_soc_sensor_client_log_single.slcp index fbd3030c42..e339de33fa 100644 --- a/app/bluetooth/example/btmesh_soc_sensor_client/btmesh_soc_sensor_client_log_single.slcp +++ b/app/bluetooth/example/btmesh_soc_sensor_client/btmesh_soc_sensor_client_log_single.slcp @@ -116,7 +116,7 @@ configuration: condition: - psa_crypto - name: SL_STACK_SIZE - value: "0x1000" + value: "0x1200" define: - name: "SINGLE_BUTTON" diff --git a/app/bluetooth/example/btmesh_soc_sensor_client/dcd_config.btmeshconf b/app/bluetooth/example/btmesh_soc_sensor_client/dcd_config.btmeshconf index 295722c69e..1651efe558 100644 --- a/app/bluetooth/example/btmesh_soc_sensor_client/dcd_config.btmeshconf +++ b/app/bluetooth/example/btmesh_soc_sensor_client/dcd_config.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x0004", - "vid": "0x0300", + "vid": "0x0301", "elements": [ { "name": "Main", diff --git a/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_brd2601b.slcp b/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_brd2601b.slcp index 5e3459d9b2..d85c9bf7ea 100644 --- a/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_brd2601b.slcp +++ b/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_brd2601b.slcp @@ -130,7 +130,7 @@ configuration: condition: - psa_crypto - name: SL_STACK_SIZE - value: "0x1000" + value: "0x1200" template_contribution: - name: cli_command diff --git a/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_display.slcp b/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_display.slcp index 4c0edebb95..9ed0966e80 100644 --- a/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_display.slcp +++ b/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_display.slcp @@ -139,13 +139,7 @@ configuration: - name: SL_SIMPLE_BUTTON_ALLOW_LED_CONFLICT value: "1" - name: SL_STACK_SIZE - value: "0x1000" - unless: - - "device_sdid_205" - - name: SL_STACK_SIZE - value: "0xF00" - condition: - - "device_sdid_205" + value: "0x1300" template_contribution: - name: cli_command diff --git a/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_mock_display.slcp b/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_mock_display.slcp index 1f828d9fc2..30d11296e5 100644 --- a/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_mock_display.slcp +++ b/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_mock_display.slcp @@ -125,7 +125,7 @@ configuration: - name: SL_SIMPLE_BUTTON_ALLOW_LED_CONFLICT value: "1" - name: SL_STACK_SIZE - value: "0x1000" + value: "0x1400" template_contribution: - name: cli_command diff --git a/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_mock_log.slcp b/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_mock_log.slcp index fe2cc4647b..07bbeeca50 100644 --- a/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_mock_log.slcp +++ b/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_mock_log.slcp @@ -122,7 +122,7 @@ configuration: - name: SL_SIMPLE_BUTTON_ALLOW_LED_CONFLICT value: "1" - name: SL_STACK_SIZE - value: "0x1000" + value: "0x1200" template_contribution: - name: cli_command diff --git a/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_mock_log_single.slcp b/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_mock_log_single.slcp index 8a60535f1c..10f229bd1d 100644 --- a/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_mock_log_single.slcp +++ b/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_mock_log_single.slcp @@ -118,7 +118,7 @@ configuration: condition: - psa_crypto - name: SL_STACK_SIZE - value: "0x1000" + value: "0x1200" define: - name: "SINGLE_BUTTON" diff --git a/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_tbbg22a.slcp b/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_tbbg22a.slcp index 1313207a9b..d872ff2315 100644 --- a/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_tbbg22a.slcp +++ b/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_tbbg22a.slcp @@ -130,7 +130,7 @@ configuration: condition: - psa_crypto - name: SL_STACK_SIZE - value: "0x1000" + value: "0x1200" define: - name: "SINGLE_LED" diff --git a/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_tbbg22b.slcp b/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_tbbg22b.slcp index 2050ebdacd..062b39a2ae 100644 --- a/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_tbbg22b.slcp +++ b/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_tbbg22b.slcp @@ -128,7 +128,7 @@ configuration: condition: - psa_crypto - name: SL_STACK_SIZE - value: "0x1000" + value: "0x1200" define: - name: "SINGLE_LED" diff --git a/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_tbsense.slcp b/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_tbsense.slcp index 6d256e726f..ce74b7e98f 100644 --- a/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_tbsense.slcp +++ b/app/bluetooth/example/btmesh_soc_sensor_server/btmesh_soc_sensor_server_tbsense.slcp @@ -130,7 +130,7 @@ configuration: condition: - psa_crypto - name: SL_STACK_SIZE - value: "0x1000" + value: "0x1200" template_contribution: - name: cli_command diff --git a/app/bluetooth/example/btmesh_soc_sensor_server/dcd_config.btmeshconf b/app/bluetooth/example/btmesh_soc_sensor_server/dcd_config.btmeshconf index cf048c7992..cdfff067bd 100644 --- a/app/bluetooth/example/btmesh_soc_sensor_server/dcd_config.btmeshconf +++ b/app/bluetooth/example/btmesh_soc_sensor_server/dcd_config.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x0005", - "vid": "0x0300", + "vid": "0x0301", "elements": [ { "name": "Main", diff --git a/app/bluetooth/example/btmesh_soc_switch/btmesh_soc_switch_display.slcp b/app/bluetooth/example/btmesh_soc_switch/btmesh_soc_switch_display.slcp index 116bfb1b98..21d411c8ae 100644 --- a/app/bluetooth/example/btmesh_soc_switch/btmesh_soc_switch_display.slcp +++ b/app/bluetooth/example/btmesh_soc_switch/btmesh_soc_switch_display.slcp @@ -122,7 +122,7 @@ configuration: condition: - "device_sdid_205" - name: SL_HEAP_SIZE - value: "0x4000" + value: "0x4100" unless: - "device_sdid_205" - name: SL_PSA_KEY_USER_SLOT_COUNT @@ -132,13 +132,7 @@ configuration: - name: SL_SIMPLE_BUTTON_ALLOW_LED_CONFLICT value: "1" - name: SL_STACK_SIZE - value: "0xE00" - condition: - - "device_sdid_205" - - name: SL_STACK_SIZE - value: "0x1000" - unless: - - "device_sdid_205" + value: "0x1300" template_contribution: - name: cli_command diff --git a/app/bluetooth/example/btmesh_soc_switch/btmesh_soc_switch_log.slcp b/app/bluetooth/example/btmesh_soc_switch/btmesh_soc_switch_log.slcp index f1bc393022..5a9f8f9998 100644 --- a/app/bluetooth/example/btmesh_soc_switch/btmesh_soc_switch_log.slcp +++ b/app/bluetooth/example/btmesh_soc_switch/btmesh_soc_switch_log.slcp @@ -115,7 +115,7 @@ configuration: condition: - "device_sdid_205" - name: SL_HEAP_SIZE - value: "0x4000" + value: "0x4100" - name: SL_PSA_KEY_USER_SLOT_COUNT value: "0" condition: @@ -123,7 +123,7 @@ configuration: - name: SL_SIMPLE_BUTTON_ALLOW_LED_CONFLICT value: "1" - name: SL_STACK_SIZE - value: "0x1000" + value: "0x1200" template_contribution: - name: cli_command diff --git a/app/bluetooth/example/btmesh_soc_switch/btmesh_soc_switch_log_single.slcp b/app/bluetooth/example/btmesh_soc_switch/btmesh_soc_switch_log_single.slcp index c827412112..8d25821031 100644 --- a/app/bluetooth/example/btmesh_soc_switch/btmesh_soc_switch_log_single.slcp +++ b/app/bluetooth/example/btmesh_soc_switch/btmesh_soc_switch_log_single.slcp @@ -123,7 +123,7 @@ configuration: condition: - psa_crypto - name: SL_STACK_SIZE - value: "0x1000" + value: "0x1200" define: - name: "SINGLE_BUTTON" diff --git a/app/bluetooth/example/btmesh_soc_switch/btmesh_soc_switch_low_power.slcp b/app/bluetooth/example/btmesh_soc_switch/btmesh_soc_switch_low_power.slcp index 8257a85b24..1d4f05f451 100644 --- a/app/bluetooth/example/btmesh_soc_switch/btmesh_soc_switch_low_power.slcp +++ b/app/bluetooth/example/btmesh_soc_switch/btmesh_soc_switch_low_power.slcp @@ -96,7 +96,7 @@ configuration: - name: NVM3_DEFAULT_CACHE_SIZE value: 100 - name: SL_HEAP_SIZE - value: "0x4000" + value: "0x4100" - name: SL_PSA_KEY_USER_SLOT_COUNT value: "0" condition: @@ -104,7 +104,7 @@ configuration: - name: SL_SIMPLE_BUTTON_ALLOW_LED_CONFLICT value: "1" - name: SL_STACK_SIZE - value: "0x1000" + value: "0x1200" tag: - hardware:board_only diff --git a/app/bluetooth/example/btmesh_soc_switch/btmesh_soc_switch_low_power_single.slcp b/app/bluetooth/example/btmesh_soc_switch/btmesh_soc_switch_low_power_single.slcp index 380e33d8fc..019ccbe599 100644 --- a/app/bluetooth/example/btmesh_soc_switch/btmesh_soc_switch_low_power_single.slcp +++ b/app/bluetooth/example/btmesh_soc_switch/btmesh_soc_switch_low_power_single.slcp @@ -104,7 +104,7 @@ configuration: condition: - psa_crypto - name: SL_STACK_SIZE - value: "0x1000" + value: "0x1200" define: - name: "SINGLE_BUTTON" diff --git a/app/bluetooth/example/btmesh_soc_switch/dcd_config.btmeshconf b/app/bluetooth/example/btmesh_soc_switch/dcd_config.btmeshconf index 78def78d10..c50d998a9d 100644 --- a/app/bluetooth/example/btmesh_soc_switch/dcd_config.btmeshconf +++ b/app/bluetooth/example/btmesh_soc_switch/dcd_config.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x0006", - "vid": "0x0300", + "vid": "0x0301", "elements": [ { "name": "Main", diff --git a/app/bluetooth/example/btmesh_soc_switch/dcd_config_low_power.btmeshconf b/app/bluetooth/example/btmesh_soc_switch/dcd_config_low_power.btmeshconf index fc858d5d06..db43106c87 100644 --- a/app/bluetooth/example/btmesh_soc_switch/dcd_config_low_power.btmeshconf +++ b/app/bluetooth/example/btmesh_soc_switch/dcd_config_low_power.btmeshconf @@ -2,7 +2,7 @@ "composition_data": { "cid": "0x02ff", "pid": "0x0007", - "vid": "0x0300", + "vid": "0x0301", "elements": [ { "name": "Main", diff --git a/app/bluetooth/example_host/bt_aoa_host_locator/app.c b/app/bluetooth/example_host/bt_aoa_host_locator/app.c index 880c0540cc..c23a70f84d 100644 --- a/app/bluetooth/example_host/bt_aoa_host_locator/app.c +++ b/app/bluetooth/example_host/bt_aoa_host_locator/app.c @@ -81,13 +81,14 @@ static void parse_config(const char *config); static void on_message(mqtt_handle_t *handle, const char *topic, const char *payload); +static void on_correction(aoa_id_t loc_id, + aoa_id_t tag_id, + char *correction); static void subscribe_correction(void); static void subscribe_config(void); -static sl_status_t check_config_topic(const char* topic_literal, - const char* topic, - size_t topic_size); +static sl_status_t check_config_topic(const char* topic); // report mode config static aoa_report_mode_t report_mode; @@ -102,13 +103,6 @@ static char *mqtt_host = NULL; // Config file path static char *config_file = NULL; -// CTE Mode strings -static const char *cte_mode_string[] = { - "Silabs", - "connection", - "connectionless" -}; - /**************************************************************************//** * Application Init. *****************************************************************************/ @@ -117,6 +111,7 @@ void app_init(int argc, char *argv[]) sl_status_t sc; int opt; char *port_str; + char *cte_mode_string; report_mode = DEFAULT_REPORT_MODE; @@ -176,8 +171,10 @@ void app_init(int argc, char *argv[]) app_assert_status(sc); app_log_info("NCP host initialised." APP_LOG_NL); - app_log_info("Selected CTE mode: %s" APP_LOG_NL, - cte_mode_string[aoa_cte_get_mode()]); + sc = aoa_parse_cte_mode_to_string(aoa_cte_get_mode(), &cte_mode_string); + if (sc == SL_STATUS_OK) { + app_log_info("Selected CTE mode: %s" APP_LOG_NL, cte_mode_string); + } app_log_info("Press Crtl+C to quit" APP_LOG_NL APP_LOG_NL); ncp_reset(); } @@ -298,6 +295,9 @@ static void subscribe_config(void) sc = mqtt_subscribe(&mqtt_handle, topic); app_assert_status(sc); + + sc = mqtt_subscribe(&mqtt_handle, AOA_TOPIC_CONFIG_BROADCAST); + app_assert_status(sc); } /**************************************************************************//** @@ -320,19 +320,21 @@ static void subscribe_correction(void) /**************************************************************************//** * Check the received topic *****************************************************************************/ -static sl_status_t check_config_topic(const char* topic_literal, - const char* topic, - size_t topic_size) +static sl_status_t check_config_topic(const char* topic) { - char topic_buffer[sizeof(topic_literal) + sizeof(aoa_id_t)]; - - snprintf(topic_buffer, sizeof(topic_buffer), topic_literal, locator_id); + aoa_id_t loc_id; - if (strncmp(topic_buffer, topic, topic_size) == 0) { + if (strcmp(topic, AOA_TOPIC_CONFIG_BROADCAST) == 0) { + // Broadcast config return SL_STATUS_OK; - } else { - return SL_STATUS_NOT_FOUND; } + if (sscanf(topic, AOA_TOPIC_CONFIG_SCAN, loc_id) == 1) { + if (aoa_id_compare(loc_id, locator_id) == 0) { + // Unicast config + return SL_STATUS_OK; + } + } + return SL_STATUS_NOT_FOUND; } /**************************************************************************//** @@ -342,8 +344,30 @@ static void on_message(mqtt_handle_t *handle, const char *topic, const char *payload) { - int result; + (void)handle; aoa_id_t loc_id, tag_id; + + if (check_config_topic(topic) == SL_STATUS_OK) { + parse_config(payload); + ncp_reset(); + return; + } + + if (sscanf(topic, AOA_TOPIC_CORRECTION_SCAN, loc_id, tag_id) == 2) { + on_correction(loc_id, tag_id, (char *)payload); + return; + } + + app_log_error("Failed to parse topic: %s." APP_LOG_NL, topic); +} + +/**************************************************************************//** + * Correction message arrived callback. + *****************************************************************************/ +static void on_correction(aoa_id_t loc_id, + aoa_id_t tag_id, + char *correction_str) +{ aoa_angle_t correction; bd_addr tag_addr; uint8_t tag_addr_type; @@ -355,51 +379,39 @@ static void on_message(mqtt_handle_t *handle, sc = aoa_angle_get_config(locator_id, &angle_config); app_assert_status(sc); - (void)handle; - - if (check_config_topic(AOA_TOPIC_CONFIG_PRINT, - topic, - sizeof(AOA_TOPIC_CONFIG_PRINT)) == SL_STATUS_OK) { - parse_config(payload); - - ncp_reset(); - } else if (report_mode == ANGLE_REPORT) { - // Parse topic - result = sscanf(topic, AOA_TOPIC_CORRECTION_SCAN, loc_id, tag_id); - app_assert(result == 2, - "Failed to parse correction topic: %d." APP_LOG_NL, - result); - - if (aoa_id_compare(loc_id, locator_id) != 0) { - // Accidentally got a wrong message - return; - } - // Find asset tag in the database - sc = aoa_id_to_address(tag_id, tag_addr.addr, &tag_addr_type); - if (SL_STATUS_OK == sc) { - sc = aoa_db_get_tag_by_address(&tag_addr, &tag); - } - if (SL_STATUS_OK == sc) { - // Parse payload - sc = aoa_deserialize_angle((char *)payload, &correction); - app_assert_status(sc); + if (report_mode != ANGLE_REPORT) { + // Ignore correction messages if not in angle report mode. + return; + } + if (aoa_id_compare(loc_id, locator_id) != 0) { + // Accidentally got a wrong message. + return; + } + // Find asset tag in the database + sc = aoa_id_to_address(tag_id, tag_addr.addr, &tag_addr_type); + if (SL_STATUS_OK == sc) { + sc = aoa_db_get_tag_by_address(&tag_addr, &tag); + } + if (SL_STATUS_OK == sc) { + // Parse payload + sc = aoa_deserialize_angle(correction_str, &correction); + app_assert_status(sc); - if (aoa_sequence_compare(tag->sequence, correction.sequence) - <= angle_config->angle_correction_delay) { - app_log("Apply correction #%d for asset tag '%s'" APP_LOG_NL, - correction.sequence, - tag_id); - ec = aoa_set_correction((aoa_state_t *)tag->user_data, - &correction, - locator_id); - app_assert(ec == SL_RTL_ERROR_SUCCESS, - "[E: %d] Failed to set correction values" APP_LOG_NL, - ec); - } else { - app_log("Omit correction #%d for asset tag '%s'" APP_LOG_NL, - correction.sequence, - tag_id); - } + if (aoa_sequence_compare(tag->sequence, correction.sequence) + <= angle_config->angle_correction_delay) { + app_log("Apply correction #%d for asset tag '%s'" APP_LOG_NL, + correction.sequence, + tag_id); + ec = aoa_set_correction((aoa_state_t *)tag->user_data, + &correction, + locator_id); + app_assert(ec == SL_RTL_ERROR_SUCCESS, + "[E: %d] Failed to set correction values" APP_LOG_NL, + ec); + } else { + app_log("Omit correction #%d for asset tag '%s'" APP_LOG_NL, + correction.sequence, + tag_id); } } } diff --git a/app/bluetooth/example_host/bt_host_cpc_hci_bridge/bridge.c b/app/bluetooth/example_host/bt_host_cpc_hci_bridge/bridge.c index c654884d04..abcc6a496f 100644 --- a/app/bluetooth/example_host/bt_host_cpc_hci_bridge/bridge.c +++ b/app/bluetooth/example_host/bt_host_cpc_hci_bridge/bridge.c @@ -33,19 +33,25 @@ * ******************************************************************************/ #include "sl_cpc.h" +#include #include #include #include #include -#include #include #include #include #include +#include // set this to 1 for more runtime log messages #define DEBUG 0 +#define SUCCESS 0 +#define FAILURE (-1) +#define TIMEOUT_IN_SEC 0 +#define TIMEOUT_IN_USEC 5000 + #define TO_CPC_BUF_SIZE 256 #define FROM_CPC_BUF_SIZE SL_CPC_READ_MINIMUM_SIZE #define INST_NAME_LEN 100 @@ -56,6 +62,8 @@ #define CPC_TRANSMIT_WINDOW 1 #define SYMLINK_PATH "pts_hci" +#define MAX(x, y) ((x) > (y) ? (x) : (y)) + // cpc related structures static cpc_handle_t lib_handle; static cpc_endpoint_t endpoint; @@ -67,6 +75,7 @@ static char cpc_instance[INST_NAME_LEN]; static int pty_m; static int pty_s; +static int ep_sock_fd; // end the receiving loop if signal is received. static volatile bool run = true; @@ -74,14 +83,7 @@ static volatile bool run = true; static volatile bool has_reset = false; static void reset_callback(void); - -// two worker threads -static pthread_t thread_rx; -static pthread_t thread_tx; - -// Static receive function -static void *cpc_to_pty_func(void *ptr); -static void *pty_to_cpc_func(void *ptr); +static int cpc_poll_fds(void); // Custom signal handler. static void signal_handler(int sig) @@ -123,10 +125,14 @@ uint32_t startup(void) perror("cpc_open_endpoint "); return ret; } + ep_sock_fd = ret; // Open virtual UART device ret = openpty(&pty_m, &pty_s, NULL, NULL, NULL); if (ret >= 0) { + int flags = fcntl(pty_m, F_GETFL, 0); + flags = flags | O_NONBLOCK; + fcntl(pty_m, F_SETFL, flags); char *pName = ttyname(pty_s); printf("Name of secondary pty side is <%s>\n", pName); remove(SYMLINK_PATH); @@ -182,10 +188,12 @@ int reset_cpc(void) &endpoint, SL_CPC_ENDPOINT_BLUETOOTH_RCP, CPC_TRANSMIT_WINDOW); + if (ret < 0) { perror(" open endpoint "); } + ep_sock_fd = ret; return ret; } @@ -211,21 +219,6 @@ int main(int argc, char *argv[]) if (startup() < 0) { exit(EXIT_FAILURE); } - // Creating receiving working threads - ret = pthread_create(&thread_rx, NULL, cpc_to_pty_func, NULL); - if (ret) { - printf("Error - pthread_create(thread_rx) return code: %d\n", ret); - exit(EXIT_FAILURE); - } - ret = pthread_create(&thread_tx, NULL, pty_to_cpc_func, NULL); - if (ret) { - printf("Error - pthread_create(thread_tx) return code: %d\n", ret); - exit(EXIT_FAILURE); - } - - if (DEBUG) { - printf("\nCPC - VHCI bridge working, main thread is going to sleep\n\n"); - } // Reset cpc communication if daemon signals while (run) { @@ -235,23 +228,58 @@ int main(int argc, char *argv[]) perror("reset "); exit(EXIT_FAILURE); } + } else { + ret = cpc_poll_fds(); + if (ret < 0) { + perror("select error"); + } } - nanosleep((const struct timespec[]){{ 0, CPC_RESET_SLEEP_NS } }, NULL); } } -/**************************************************************************//** - * Working thread from CPCd - *****************************************************************************/ -void *cpc_to_pty_func(void *ptr) +int cpc_poll_fds(void) { + int ret; + int max_fd; ssize_t size = 0; + struct timeval tv; + tv.tv_sec = TIMEOUT_IN_SEC; + tv.tv_usec = TIMEOUT_IN_USEC; - // unused variable - (void)ptr; + fd_set readfds; - while (run) { - // Read data from cpc + FD_ZERO(&readfds); + FD_SET(pty_m, &readfds); + FD_SET(ep_sock_fd, &readfds); + + max_fd = MAX(pty_m, ep_sock_fd); + + ret = select(max_fd + 1, &readfds, NULL, NULL, &tv); + if ((ret < 0) && (errno != EINTR)) { + return ret; + } + + if (FD_ISSET(pty_m, &readfds)) { + size = read(pty_m, data_to_cpc, TO_CPC_BUF_SIZE); + if (size > 0) { + if (DEBUG) { + printf("Len to cpc %zd\n", size); + printf("Data to cpc: "); + for (int i = 0; i < size; i++) { + printf("%x ", data_to_cpc[i]); + } + printf("\n"); + } + // Write data to cpc + cpc_write_endpoint(endpoint, &data_to_cpc[0], size, 0); + memset(&data_to_cpc[0], 0, TO_CPC_BUF_SIZE); + } else if (errno != EAGAIN && errno != ECONNRESET) { + perror("pty_to_cpc_func error"); + return FAILURE; + } + } + + if (FD_ISSET(ep_sock_fd, &readfds)) { size = cpc_read_endpoint(endpoint, &data_from_cpc[0], FROM_CPC_BUF_SIZE, @@ -268,49 +296,11 @@ void *cpc_to_pty_func(void *ptr) // Write data to pty write(pty_m, &data_from_cpc[0], size); memset(&data_from_cpc[0], 0, FROM_CPC_BUF_SIZE); - } else if (has_reset) { - // intentionally left blank } else if (errno != EAGAIN && errno != ECONNRESET) { perror("cpc_to_pty_func error "); - exit(-1); + return FAILURE; } - nanosleep((const struct timespec[]){{ 0, THREAD_SLEEP_NS } }, NULL); } - return NULL; -} -/**************************************************************************//** - * Working thread to CPCd - *****************************************************************************/ -void *pty_to_cpc_func(void *ptr) -{ - ssize_t size = 0; - - // unused variable - (void)ptr; - - while (run) { - // Read data from pty - size = read(pty_m, data_to_cpc, TO_CPC_BUF_SIZE); - if (size > 0) { - if (DEBUG) { - printf("Len to cpc %zd\n", size); - printf("Data to cpc: "); - for (int i = 0; i < size; i++) { - printf("%x ", data_to_cpc[i]); - } - printf("\n"); - } - // Write data to cpc - cpc_write_endpoint(endpoint, &data_to_cpc[0], size, 0); - memset(&data_to_cpc[0], 0, TO_CPC_BUF_SIZE); - } else if (has_reset) { - // intentionally left blank - } else if (errno != EAGAIN && errno != ECONNRESET) { - perror("pty_to_cpc_func error"); - exit(-1); - } - nanosleep((const struct timespec[]){{ 0, THREAD_SLEEP_NS } }, NULL); - } - return NULL; + return SUCCESS; } diff --git a/app/bluetooth/example_host/bt_host_cpc_hci_bridge/makefile b/app/bluetooth/example_host/bt_host_cpc_hci_bridge/makefile index d971cd13ce..90ffb9f811 100644 --- a/app/bluetooth/example_host/bt_host_cpc_hci_bridge/makefile +++ b/app/bluetooth/example_host/bt_host_cpc_hci_bridge/makefile @@ -95,7 +95,7 @@ bridge.c LIBS = $(CPC_DIR)/daemon/build/libcpc.so -override LDFLAGS += -lpthread -lutil +override LDFLAGS += -lutil ################################################################################ # Rules # diff --git a/app/bluetooth/example_host/bt_host_ota_dfu/main.c b/app/bluetooth/example_host/bt_host_ota_dfu/main.c index 77f60aac7e..7e35449f59 100644 --- a/app/bluetooth/example_host/bt_host_ota_dfu/main.c +++ b/app/bluetooth/example_host/bt_host_ota_dfu/main.c @@ -359,7 +359,7 @@ void ota_change_state(enum ota_states new_state) case OTA_SCAN: { addr_found = 0; - sl_bt_scanner_start(sl_bt_gap_1m_phy, sl_bt_scanner_discover_generic); + sl_bt_scanner_start(sl_bt_gap_phy_1m, sl_bt_scanner_discover_generic); app_log("Scanning..."); } break; @@ -380,7 +380,7 @@ void ota_change_state(enum ota_states new_state) } //move to connect state, connect to device address - sc = sl_bt_connection_open(remote_address, remote_address_type, sl_bt_gap_1m_phy, &connection); + sc = sl_bt_connection_open(remote_address, remote_address_type, sl_bt_gap_phy_1m, &connection); if (sc) { ERROR_EXIT("Error, open failed,0x%x", sc); } @@ -502,15 +502,15 @@ void print_address(bd_addr address) } } -static int parse_scan_data(uint8array *data, bd_addr *addr) +static int parse_scan_data(uint8_t *data, uint8_t len, bd_addr *addr) { uint8_t i = 0; - while (i < data->len) { - if (data->data[i + 1] == GAP_ADDR_TYPE) { - memcpy(addr, &data->data[i + 3], sizeof(bd_addr)); + while (i < len) { + if (data[i + 1] == GAP_ADDR_TYPE) { + memcpy(addr, &data[i + 3], sizeof(bd_addr)); return 0; } else { - i += data->data[i] + 1; + i += data[i] + 1; } } @@ -589,6 +589,33 @@ int hw_init(int argc, char* argv[]) return ret; } +static void handle_scan_event(uint8_t *address, + uint8_t address_type, + uint8_t *data, + uint8_t data_len) +{ + if (!addr_found) { + bd_addr addr; + if (!memcmp(address, &remote_public_address, sizeof(bd_addr))) { + memcpy(&remote_address, address, sizeof(bd_addr)); + remote_address_type = address_type; + addr_found = 1; + } else if (parse_scan_data(data, data_len, &addr) == 0) { + if (!memcmp(&addr, &remote_public_address, sizeof(bd_addr))) { + memcpy(&remote_address, address, sizeof(bd_addr)); + remote_address_type = address_type; + addr_found = 1; + } + } + if (addr_found) { + sl_bt_scanner_stop(); + app_log("OK\n"); + app_log("Device address found, connecting.\n"); + ota_change_state(OTA_CONNECT); + } + } +} + /** * The main program. */ @@ -834,26 +861,24 @@ int main(int argc, char* argv[]) case OTA_SCAN: switch (SL_BT_MSG_ID(p->header)) { - case sl_bt_evt_scanner_scan_report_id: - if (!addr_found) { - bd_addr addr; - if (!memcmp(&p->data.evt_scanner_scan_report.address, &remote_public_address, sizeof(bd_addr))) { - memcpy(&remote_address, &p->data.evt_scanner_scan_report.address, sizeof(bd_addr)); - remote_address_type = p->data.evt_scanner_scan_report.address_type; - addr_found = 1; - } else if (parse_scan_data(&p->data.evt_scanner_scan_report.data, &addr) == 0) { - if (!memcmp(&addr, &remote_public_address, sizeof(bd_addr))) { - memcpy(&remote_address, &p->data.evt_scanner_scan_report.address, sizeof(bd_addr)); - remote_address_type = p->data.evt_scanner_scan_report.address_type; - addr_found = 1; - } - } - if (addr_found) { - sl_bt_scanner_stop(); - app_log("OK\n"); - app_log("Device address found, connecting.\n"); - ota_change_state(OTA_CONNECT); - } + case sl_bt_evt_scanner_legacy_advertisement_report_id: + if (p->data.evt_scanner_legacy_advertisement_report.event_flags + & SL_BT_SCANNER_EVENT_FLAG_CONNECTABLE) { + handle_scan_event(p->data.evt_scanner_legacy_advertisement_report.address.addr, + p->data.evt_scanner_legacy_advertisement_report.address_type, + p->data.evt_scanner_legacy_advertisement_report.data.data, + p->data.evt_scanner_legacy_advertisement_report.data.len); + } + break; + case sl_bt_evt_scanner_extended_advertisement_report_id: + if ((p->data.evt_scanner_extended_advertisement_report.event_flags + & SL_BT_SCANNER_EVENT_FLAG_CONNECTABLE) + && (p->data.evt_scanner_extended_advertisement_report.data_completeness + == sl_bt_scanner_data_status_complete)) { + handle_scan_event(p->data.evt_scanner_extended_advertisement_report.address.addr, + p->data.evt_scanner_extended_advertisement_report.address_type, + p->data.evt_scanner_extended_advertisement_report.data.data, + p->data.evt_scanner_extended_advertisement_report.data.len); } break; default: diff --git a/app/bluetooth/example_host/bt_host_positioning/app.c b/app/bluetooth/example_host/bt_host_positioning/app.c index d39b79b3c6..37ba1e2235 100644 --- a/app/bluetooth/example_host/bt_host_positioning/app.c +++ b/app/bluetooth/example_host/bt_host_positioning/app.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include "app.h" @@ -74,21 +75,26 @@ // ----------------------------------------------------------------------------- // Private variables static mqtt_handle_t mqtt_handle = MQTT_DEFAULT_HANDLE; +static aoa_id_t mqtt_client_id; static aoa_id_t positioning_id = ""; static aoa_report_mode_t *loc_report_mode = NULL; +static angle_queue_config_t angle_queue_config = ANGLE_QUEUE_DEFAULT_CONFIG; // ----------------------------------------------------------------------------- // Private function declarations +static char *get_app_name(char *arg_0); static void parse_config_file(const char *filename); static void parse_config(const char *payload); +static void parse_locator_config(void); static void on_message(mqtt_handle_t *handle, const char *topic, const char *payload); -static void subscribe_topic(char *topic_template, - size_t topic_size, - aoa_locator_t *loc); -static void subscribe_config(void); -static sl_status_t check_config_topic(const char* topic); +static void on_locator_report(aoa_id_t loc_id, + aoa_id_t tag_id, + aoa_report_mode_t report_mode, + const char *payload); +static void locator_subscription(aoa_id_t loc_id, bool subscribe); +static void on_new_positioning_id(char *new_id); static void angle_queue_on_angles_ready(aoa_id_t tag_id, uint32_t angle_count, aoa_angle_t *angle_list, @@ -103,6 +109,7 @@ void app_init(int argc, char *argv[]) int opt; char *port_str = NULL; char *config_file = NULL; + char *app_name = get_app_name(argv[0]); // Process command line options. while ((opt = getopt(argc, argv, OPTSTRING)) != -1) { @@ -128,7 +135,7 @@ void app_init(int argc, char *argv[]) // Print help. case 'h': - app_log(USAGE, argv[0]); + app_log(USAGE, app_name); app_log(OPTIONS); exit(EXIT_SUCCESS); @@ -136,18 +143,28 @@ void app_init(int argc, char *argv[]) default: sc = app_log_set_option((char)opt, optarg); if (sc != SL_STATUS_OK) { - app_log(USAGE, argv[0]); + app_log(USAGE, app_name); exit(EXIT_FAILURE); } } } - // Configuration file is mandatory. - if (config_file == NULL) { - app_log(USAGE, argv[0]); - exit(EXIT_FAILURE); + // MQTT client init. + snprintf(mqtt_client_id, sizeof(mqtt_client_id), "%s_%i", app_name, getpid()); + mqtt_handle.client_id = mqtt_client_id; + mqtt_handle.on_message = on_message; + + sc = mqtt_init(&mqtt_handle); + app_assert_status(sc); + + sc = mqtt_subscribe(&mqtt_handle, AOA_TOPIC_CONFIG_BROADCAST); + app_assert_status(sc); + + angle_queue_config.on_angles_ready = &angle_queue_on_angles_ready; + + if (config_file != NULL) { + parse_config_file(config_file); } - parse_config_file(config_file); app_log("Press Crtl+C to quit" APP_LOG_NL APP_LOG_NL); } @@ -171,12 +188,28 @@ void app_deinit(void) sc = mqtt_deinit(&mqtt_handle); app_assert_status(sc); - aoa_loc_destroy(); + aoa_loc_destroy_tags(); + aoa_loc_destroy_locators(); + (void)aoa_loc_deinit(); angle_queue_deinit(); } /**************************************************************************//** - * Configuration file parser + * Application name helper. + *****************************************************************************/ +static char *get_app_name(char *arg_0) +{ + char *app_name = basename(arg_0); + // Remove the trailing .exe on Windows. + char *extension = strstr(app_name, ".exe"); + if (extension != NULL) { + *extension = '\0'; + } + return app_name; +} + +/**************************************************************************//** + * Configuration file parser. *****************************************************************************/ static void parse_config_file(const char *filename) { @@ -194,46 +227,26 @@ static void parse_config(const char *payload) { sl_status_t sc; aoa_locator_t *loc; - aoa_id_t locator_id; - struct sl_rtl_loc_locator_item item; - aoa_angle_config_t *angle_config; - angle_queue_config_t angle_queue_config = ANGLE_QUEUE_DEFAULT_CONFIG; - float mask_min = 0; - float mask_max = 0; - uint8_t *antenna_switch_pattern = NULL; - uint8_t antenna_switch_pattern_size = 0; - enum sl_rtl_aox_array_type antenna_array_type; char *str_config; sc = aoa_parse_init(payload); app_assert_status(sc); - sc = aoa_parse_string_config(&str_config, "id", NULL); - if (sc == SL_STATUS_OK) { - aoa_id_copy(positioning_id, str_config); - } - - if (positioning_id != mqtt_handle.client_id) { - mqtt_handle.on_message = on_message; - mqtt_handle.client_id = positioning_id; - - sc = mqtt_init(&mqtt_handle); - app_assert_status(sc); - app_log_nl(); - } - subscribe_config(); - - aoa_loc_destroy(); - aoa_angle_reset_configs(); angle_queue_deinit(); + aoa_loc_destroy_tags(); + (void)aoa_loc_deinit(); sc = aoa_loc_init(); app_assert_status(sc); - angle_queue_config.on_angles_ready = &angle_queue_on_angles_ready; + app_log_info("----------CONFIG START----------" APP_LOG_NL); + + sc = aoa_parse_string_config(&str_config, "id", NULL); + if (sc == SL_STATUS_OK) { + app_log_info("Positioning ID set to: %s" APP_LOG_NL, str_config); + on_new_positioning_id(str_config); + } - app_log_info("Parsing positioning configuration:" APP_LOG_NL); - app_log_nl(); sc = aoa_parse_string_config(&str_config, "estimationModeLocation", NULL); if (sc == SL_STATUS_OK) { sc = aoa_parse_estimation_mode_from_string(str_config, &aoa_loc_config.estimation_mode); @@ -296,15 +309,83 @@ static void parse_config(const char *payload) aoa_loc_config.max_sequence_diff = angle_queue_config.max_sequence_diff; - app_log_nl(); - app_log_info("Parsing locator configurations:" APP_LOG_NL); + sc = aoa_parse_check_config_exist("locators", NULL); + if (sc == SL_STATUS_OK) { + // Configuration contains locators. + if (aoa_loc_config.locator_count > 0) { + // Clear current locators. + for (uint32_t i = 0; i < aoa_loc_config.locator_count; i++) { + aoa_loc_get_locator_by_index(i, &loc); + locator_subscription(loc->id, false); + } + aoa_loc_destroy_locators(); + aoa_angle_reset_configs(); + } + parse_locator_config(); + + aoa_loc_config.locator_count = aoa_loc_get_number_of_locators(); + if (aoa_loc_config.locator_count > 0) { + angle_queue_config.locator_count = aoa_loc_config.locator_count; + // Parse report modes of the locators. + loc_report_mode = (aoa_report_mode_t *)realloc(loc_report_mode, + aoa_loc_config.locator_count + * sizeof(aoa_report_mode_t)); + for (uint32_t i = 0; i < aoa_loc_config.locator_count; i++) { + aoa_loc_get_locator_by_index(i, &loc); + sc = aoa_parse_string_config(&str_config, "reportMode", loc->id); + if (sc == SL_STATUS_OK) { + sc = aoa_parse_report_mode_from_string(str_config, &loc_report_mode[i]); + if (sc == SL_STATUS_OK) { + app_log_info("Report mode set to: %s" APP_LOG_NL, str_config); + } else { + app_log_error("Failed to set report mode to %s" APP_LOG_NL, str_config); + } + } + locator_subscription(loc->id, true); + } + app_log_info("Locator count: %d" APP_LOG_NL, aoa_loc_config.locator_count); + } + } + app_log_info("-----------CONFIG END-----------" APP_LOG_NL); + + // If no locator configured, just wait for MQTT config + if (aoa_loc_config.locator_count > 0) { + sc = aoa_loc_finalize_config(); + app_assert_status(sc); + + sc = angle_queue_init(&angle_queue_config); + app_assert_status(sc); + } + + sc = aoa_parse_deinit(); + app_assert_status(sc); +} + +/**************************************************************************//** + * Parse locator specific configuration. + * @pre aoa_parse_init + * @post aoa_parse_deinit + *****************************************************************************/ +static void parse_locator_config(void) +{ + sl_status_t sc; + aoa_locator_t *loc; + aoa_id_t locator_id; + struct sl_rtl_loc_locator_item item; + aoa_angle_config_t *angle_config; + float mask_min = 0; + float mask_max = 0; + uint8_t *antenna_switch_pattern = NULL; + uint8_t antenna_switch_pattern_size = 0; + enum sl_rtl_aox_array_type antenna_array_type; + char *str_config; + while (aoa_parse_locator(locator_id, &item) == SL_STATUS_OK) { - app_log_nl(); sc = aoa_loc_add_locator(locator_id, item, &loc); app_assert_status_f(sc, "Failed to allocate memory for locator"); sc = aoa_angle_add_config(locator_id, &angle_config); app_assert_status_f(sc, "Failed to allocate memory for locator"); - app_log_info("Locator added:" APP_LOG_NL); + app_log_info("----LOCATOR----" APP_LOG_NL); app_log_info("id: %s," APP_LOG_NL, loc->id); app_log_info("coordinate: %f %f %f" APP_LOG_NL, loc->item.coordinate_x, @@ -316,7 +397,6 @@ static void parse_config(const char *payload) loc->item.orientation_z_axis_degrees); loc->functional = true; - app_log_nl(); sc = aoa_parse_string_config(&str_config, "aoxMode", locator_id); if (sc == SL_STATUS_OK) { sc = aoa_parse_aox_mode_from_string(str_config, &angle_config->aox_mode); @@ -448,104 +528,68 @@ static void parse_config(const char *payload) sc = aoa_angle_finalize_config(locator_id); app_assert_status(sc); } - app_log_nl(); - aoa_loc_config.locator_count = aoa_loc_get_number_of_locators(); - - // If no locator configured, just wait for MQTT config - if (0 != aoa_loc_config.locator_count) { - angle_queue_config.locator_count = aoa_loc_config.locator_count; - loc_report_mode = (aoa_report_mode_t *)realloc(loc_report_mode, - aoa_loc_config.locator_count - * sizeof(aoa_report_mode_t)); - sc = aoa_loc_finalize_config(); - app_assert_status(sc); - - for (uint32_t i = 0; i < aoa_loc_config.locator_count; i++) { - aoa_loc_get_locator_by_index(i, &loc); - sc = aoa_parse_string_config(&str_config, "reportMode", loc->id); - if (sc == SL_STATUS_OK) { - sc = aoa_parse_report_mode_from_string(str_config, &loc_report_mode[i]); - if (sc == SL_STATUS_OK) { - app_log_info("Report mode set to: %s" APP_LOG_NL, str_config); - } else { - app_log_error("Failed to set report mode to %s" APP_LOG_NL, str_config); - } - } - - subscribe_topic(AOA_TOPIC_ANGLE_PRINT, - sizeof(AOA_TOPIC_ANGLE_PRINT), - loc); - - subscribe_topic(AOA_TOPIC_IQ_REPORT_PRINT, - sizeof(AOA_TOPIC_IQ_REPORT_PRINT), - loc); - } - sc = angle_queue_init(&angle_queue_config); - app_assert_status(sc); - } - - app_log_nl(); - app_log_info("Locator count: %d" APP_LOG_NL, aoa_loc_config.locator_count); - - sc = aoa_parse_deinit(); - app_assert_status(sc); } /**************************************************************************//** - * Subscribe for a topic. + * Manage locator subscriptions. *****************************************************************************/ -static void subscribe_topic(char *topic_template, - size_t topic_size, - aoa_locator_t *loc) +static void locator_subscription(aoa_id_t loc_id, bool subscribe) { sl_status_t sc; - size_t size = (topic_size + sizeof(aoa_id_t) + 1); - char *topic = malloc(size); - app_assert(NULL != topic, "Failed to allocate memory for MQTT topic."); + const char angle_topic_template[] = AOA_TOPIC_ANGLE_PRINT; + char angle_topic[sizeof(angle_topic_template) + sizeof(aoa_id_t) + 1]; + snprintf(angle_topic, sizeof(angle_topic), angle_topic_template, loc_id, "+"); - snprintf(topic, size, topic_template, loc->id, "+"); + if (subscribe) { + sc = mqtt_subscribe(&mqtt_handle, angle_topic); + } else { + sc = mqtt_unsubscribe(&mqtt_handle, angle_topic); + } + app_assert_status(sc); - app_log_info("Subscribing to topic '%s'." APP_LOG_NL, topic); + const char iq_report_topic_template[] = AOA_TOPIC_IQ_REPORT_PRINT; + char iq_report_topic[sizeof(iq_report_topic_template) + sizeof(aoa_id_t) + 1]; + snprintf(iq_report_topic, sizeof(iq_report_topic), iq_report_topic_template, loc_id, "+"); - sc = mqtt_subscribe(&mqtt_handle, topic); + if (subscribe) { + sc = mqtt_subscribe(&mqtt_handle, iq_report_topic); + } else { + sc = mqtt_unsubscribe(&mqtt_handle, iq_report_topic); + } app_assert_status(sc); - free(topic); } /**************************************************************************//** - * Subscribe for config topic. + * Handle new positioning ID. *****************************************************************************/ -static void subscribe_config(void) +static void on_new_positioning_id(char *new_id) { const char topic_template[] = AOA_TOPIC_CONFIG_PRINT; char topic[sizeof(topic_template) + sizeof(aoa_id_t) + 1]; sl_status_t sc; - snprintf(topic, sizeof(topic), topic_template, positioning_id); - - app_log_info("Subscribing to topic '%s'." APP_LOG_NL, topic); + if (strlen(new_id) == 0) { + // Positioning ID is invalid, nothing to do. + return; + } - sc = mqtt_subscribe(&mqtt_handle, topic); - app_assert_status(sc); -} + if (aoa_id_compare(positioning_id, new_id) == 0) { + // Positioning ID is unchanged, nothing to do. + return; + } -/**************************************************************************//** - * Check the received topic - *****************************************************************************/ -static sl_status_t check_config_topic(const char* topic) -{ - char topic_buffer[sizeof(AOA_TOPIC_CONFIG_PRINT) + sizeof(aoa_id_t)]; + if (strlen(positioning_id) > 0) { + snprintf(topic, sizeof(topic), topic_template, positioning_id); + sc = mqtt_unsubscribe(&mqtt_handle, topic); + app_assert_status(sc); + } - snprintf(topic_buffer, - sizeof(topic_buffer), - AOA_TOPIC_CONFIG_PRINT, - positioning_id); + // Store new ID. + aoa_id_copy(positioning_id, new_id); - if (strncmp(topic_buffer, topic, sizeof(AOA_TOPIC_CONFIG_PRINT)) == 0) { - return SL_STATUS_OK; - } else { - return SL_STATUS_NOT_FOUND; - } + snprintf(topic, sizeof(topic), topic_template, positioning_id); + sc = mqtt_subscribe(&mqtt_handle, topic); + app_assert_status(sc); } /**************************************************************************//** @@ -555,35 +599,55 @@ static void on_message(mqtt_handle_t *handle, const char *topic, const char *payload) { - int result; + aoa_id_t pos_id; aoa_id_t loc_id; aoa_id_t tag_id; - uint32_t locator_idx; - aoa_asset_tag_t *tag; - aoa_locator_t *locator; - aoa_angle_t angle; - sl_status_t sc; - aoa_iq_report_t iq_report; - int8_t samples[256]; - aoa_report_mode_t report_mode = ANGLE_REPORT; (void)handle; - if (check_config_topic(topic) == SL_STATUS_OK) { - // Unsubscribe from all topics - sc = mqtt_unsubscribe_all(&mqtt_handle); - app_assert_status(sc); + if (strcmp(topic, AOA_TOPIC_CONFIG_BROADCAST) == 0) { + // Broadcast config parse_config(payload); return; } - // Parse topic. - if (2 != sscanf(topic, AOA_TOPIC_ANGLE_SCAN, loc_id, tag_id)) { - result = sscanf(topic, AOA_TOPIC_IQ_REPORT_SCAN, loc_id, tag_id); - app_assert(result == 2, "Failed to parse topic: %d." APP_LOG_NL, result); - report_mode = IQ_REPORT; + if (sscanf(topic, AOA_TOPIC_CONFIG_SCAN, pos_id) == 1) { + if (aoa_id_compare(pos_id, positioning_id) == 0) { + // Unicast config + parse_config(payload); + } + return; + } + + if (sscanf(topic, AOA_TOPIC_ANGLE_SCAN, loc_id, tag_id) == 2) { + on_locator_report(loc_id, tag_id, ANGLE_REPORT, payload); + return; + } + + if (sscanf(topic, AOA_TOPIC_IQ_REPORT_SCAN, loc_id, tag_id) == 2) { + on_locator_report(loc_id, tag_id, IQ_REPORT, payload); + return; } + app_log_error("Failed to parse topic: %s." APP_LOG_NL, topic); +} + +/**************************************************************************//** + * IQ and angle report handler callback. + *****************************************************************************/ +static void on_locator_report(aoa_id_t loc_id, + aoa_id_t tag_id, + aoa_report_mode_t report_mode, + const char *payload) +{ + sl_status_t sc; + uint32_t locator_idx; + aoa_asset_tag_t *tag; + aoa_locator_t *locator; + aoa_angle_t angle; + aoa_iq_report_t iq_report; + int8_t samples[256]; + // Find locator. sc = aoa_loc_get_locator_by_id(loc_id, &locator_idx, &locator); if (sc != SL_STATUS_OK) { diff --git a/app/bluetooth/example_host/bt_host_throughput/app.c b/app/bluetooth/example_host/bt_host_throughput/app.c index 035751d5a9..4a387ed35a 100644 --- a/app/bluetooth/example_host/bt_host_throughput/app.c +++ b/app/bluetooth/example_host/bt_host_throughput/app.c @@ -94,7 +94,7 @@ typedef struct { uint16_t connection_interval; - sl_bt_gap_phy_and_coding_type_t phy; + sl_bt_gap_phy_coding_t phy; uint16_t mtu_size; sl_bt_gatt_client_config_flag_t test_type; throughput_mode_t mode; @@ -163,14 +163,14 @@ void app_init(int argc, char *argv[]) // PHY to use case 'p': - test_parameters.phy = (sl_bt_gap_phy_and_coding_type_t)strtoul(optarg, - NULL, - 0); + test_parameters.phy = (sl_bt_gap_phy_coding_t)strtoul(optarg, + NULL, + 0); // Validate input value - if (test_parameters.phy != sl_bt_gap_1m_phy_uncoded - && test_parameters.phy != sl_bt_gap_2m_phy_uncoded - && test_parameters.phy != sl_bt_gap_coded_phy_125k - && test_parameters.phy != sl_bt_gap_coded_phy_500k) { + if (test_parameters.phy != sl_bt_gap_phy_coding_1m_uncoded + && test_parameters.phy != sl_bt_gap_phy_coding_2m_uncoded + && test_parameters.phy != sl_bt_gap_phy_coding_125k_coded + && test_parameters.phy != sl_bt_gap_phy_coding_500k_coded) { app_log_critical("PHY must be one of these: 1 => 1M, 2 => 2M, " "4 => 125k, 8 => 500k" APP_LOG_NL); exit(EXIT_FAILURE); @@ -285,7 +285,7 @@ void app_init(int argc, char *argv[]) app_log_info("Resetting NCP..." APP_LOG_NL); // Reset NCP to ensure it gets into a defined state. // Once the chip successfully boots, boot event should be received. - sl_bt_system_reset(0); + sl_bt_system_reset(sl_bt_system_boot_mode_normal); } /**************************************************************************//** diff --git a/app/bluetooth/example_host/bt_host_voice/app.c b/app/bluetooth/example_host/bt_host_voice/app.c index 3236fa2bd3..ed4e25f99f 100644 --- a/app/bluetooth/example_host/bt_host_voice/app.c +++ b/app/bluetooth/example_host/bt_host_voice/app.c @@ -327,7 +327,7 @@ void sl_bt_on_event(sl_bt_msg_t* evt) connect_remote(CONF_get()->remote_address); } else { DEBUG_INFO("Scanning for VoBLE devices..."); - sc = sl_bt_scanner_start(sl_bt_gap_1m_phy, sl_bt_scanner_discover_generic); + sc = sl_bt_scanner_start(sl_bt_gap_phy_1m, sl_bt_scanner_discover_generic); app_assert(sc == SL_STATUS_OK, "[E: 0x%04x] Failed to start discovery #1\n", (int)sc); @@ -527,7 +527,7 @@ void sl_bt_on_event(sl_bt_msg_t* evt) // ------------------------------- // This event is triggered when a scan report received - case sl_bt_evt_scanner_scan_report_id: + case sl_bt_evt_scanner_legacy_advertisement_report_id: SCAN_Process_scan_response(evt); if (SCAN_Is_Device_Found()) { @@ -631,7 +631,7 @@ static void connect_remote(bd_addr remote_address) } //move to connect state, connect to device address - sc = sl_bt_connection_open(remote_address, /* le_gap_address_type_public = */ 0, sl_bt_gap_1m_phy, &ble_connection); + sc = sl_bt_connection_open(remote_address, /* le_gap_address_type_public = */ 0, sl_bt_gap_phy_1m, &ble_connection); if (sc != SL_STATUS_OK) { ERROR_EXIT("Error, open failed,%x", sc); } diff --git a/app/bluetooth/example_host/bt_host_voice/scan.c b/app/bluetooth/example_host/bt_host_voice/scan.c index 5ff861aff4..22fb3e749a 100644 --- a/app/bluetooth/example_host/bt_host_voice/scan.c +++ b/app/bluetooth/example_host/bt_host_voice/scan.c @@ -95,8 +95,9 @@ static void print_address(bd_addr address) **************************************************************************************************/ void SCAN_Process_scan_response(sl_bt_msg_t *evt) { - if ( is_voble_service(evt->data.evt_scanner_scan_report.data.data, evt->data.evt_scanner_scan_report.data.len) ) { - memcpy(&CONF_get()->remote_address, &evt->data.evt_scanner_scan_report.address, sizeof(bd_addr)); + if ( is_voble_service(evt->data.evt_scanner_legacy_advertisement_report.data.data, + evt->data.evt_scanner_legacy_advertisement_report.data.len) ) { + memcpy(&CONF_get()->remote_address, &evt->data.evt_scanner_legacy_advertisement_report.address, sizeof(bd_addr)); app_log("\r"); DEBUG_INFO("VoBLE device found: "); print_address(CONF_get()->remote_address); app_log("\n"); sl_status_t sc = sl_bt_scanner_stop(); app_assert(sc == SL_STATUS_OK, diff --git a/app/bluetooth/example_host/btmesh_host_provisioner/app.c b/app/bluetooth/example_host/btmesh_host_provisioner/app.c index 572e82c480..a67c43c69f 100644 --- a/app/bluetooth/example_host/btmesh_host_provisioner/app.c +++ b/app/bluetooth/example_host/btmesh_host_provisioner/app.c @@ -169,6 +169,14 @@ static void app_on_scan_timer(sl_simple_timer_t *timer, void *data); *******************************************************************************/ static void app_on_reset_timer(sl_simple_timer_t *timer, void *data); +/***************************************************************************//** +* Add user event filter via sl_bt_user_manage_event_filter +* +* @param[in] event_id ID of the event to be filtered +* @return Status of the sl_bt_user_manage_event_filter command +*******************************************************************************/ +static sl_status_t app_add_user_event_filter(const uint32_t event_id); + // ----------------------------------------------------------------------------- // Static Variables @@ -381,21 +389,16 @@ void sl_bt_on_event(sl_bt_msg_t *evt) // Do not call any stack command before receiving this boot event! case sl_bt_evt_system_boot_id: { - // Filter scanner report events as it would send a message every 5 ms - // and clog UART while scanning for unprovisioned nodes - uint8_t user_data[SL_NCP_EVT_FILTER_CMD_ADD_LEN]; - uint32_t command_id = sl_bt_evt_scanner_scan_report_id; - - user_data[0] = SL_NCP_EVT_FILTER_CMD_ADD_ID; - user_data[1] = (command_id >> 0); - user_data[2] = (command_id >> 8); - user_data[3] = (command_id >> 16); - user_data[4] = (command_id >> 24); - sc = sl_bt_user_manage_event_filter(SL_NCP_EVT_FILTER_CMD_ADD_LEN, - user_data); - app_assert(sc == SL_STATUS_OK, - "[E: 0x%04x] Failed to enable filtering on the target\n", - (int)sc); + // Filter legacy and new scanner report events as it would send a message + // every 5 ms and clog UART while scanning for unprovisioned nodes + sc = app_add_user_event_filter(sl_bt_evt_scanner_scan_report_id); + app_assert_status_f(sc, "Failed to enable filtering on the target" APP_LOG_NEW_LINE); + + sc = app_add_user_event_filter(sl_bt_evt_scanner_legacy_advertisement_report_id); + app_assert_status_f(sc, "Failed to enable filtering on the target" APP_LOG_NEW_LINE); + + sc = app_add_user_event_filter(sl_bt_evt_scanner_extended_advertisement_report_id); + app_assert_status_f(sc, "Failed to enable filtering on the target" APP_LOG_NEW_LINE); // Print boot message. app_log_info("Bluetooth stack booted: v%d.%d.%d-b%d" APP_LOG_NEW_LINE, @@ -741,6 +744,21 @@ void app_parse_address(char *input, size_t length, uint16_t *address) } } +sl_status_t app_add_user_event_filter(const uint32_t event_id) +{ + sl_status_t sc = SL_STATUS_OK; + uint8_t user_data[SL_NCP_EVT_FILTER_CMD_ADD_LEN]; + + user_data[0] = SL_NCP_EVT_FILTER_CMD_ADD_ID; + user_data[1] = event_id >> 0; + user_data[2] = event_id >> 8; + user_data[3] = event_id >> 16; + user_data[4] = event_id >> 24; + + sc = sl_bt_user_manage_event_filter(SL_NCP_EVT_FILTER_CMD_ADD_LEN, user_data); + return sc; +} + // ----------------------------------------------------------------------------- // Callbacks diff --git a/app/common/app_common.properties b/app/common/app_common.properties index b67e68ddc3..080045fba7 100644 --- a/app/common/app_common.properties +++ b/app/common/app_common.properties @@ -7,5 +7,5 @@ dependantSdkVersion=4.1.0 prop.subLabel=Platform\\ 4.1.0.0 # General properties are prepended with "prop." -prop.file.templatesFile=platform_development_templates.xml platform_test_templates.xml platform_alpha_templates.xml builtin_templates.xml platform_production_templates.xml platform_internal_templates.xml +prop.file.templatesFile=platform_beta_templates.xml platform_development_templates.xml platform_test_templates.xml platform_alpha_templates.xml builtin_templates.xml platform_production_templates.xml platform_internal_templates.xml prop.file.demosFile= platform_production_demos.xml platform_beta_demos.xml platform_alpha_demos.xml platform_deprecated_demos.xml diff --git a/app/common/example/audio_classifier/audio_classifier.slcp b/app/common/example/audio_classifier/audio_classifier.slcp index 11deb34b93..be07bd2bc9 100644 --- a/app/common/example/audio_classifier/audio_classifier.slcp +++ b/app/common/example/audio_classifier/audio_classifier.slcp @@ -32,7 +32,7 @@ component: - id: device_init - id: tensorflow_lite_micro - id: ml_audio_feature_generation - - id: printf + - id: printf - id: iostream_recommended_stream - id: iostream_retarget_stdio - id: simple_led @@ -41,11 +41,16 @@ component: - id: micriumos_kernel - id: power_manager - id: sleeptimer -config_file: +config_file: - path: config/audio_classifier_config.h - - path: "config/tflite/audio_classifier.tflite" + - path: "tflite_models/tflite/keyword_spotting_on_off.tflite" file_id: flatbuffer_file_id directory: "tflite" + unless: [tensorflow_lite_micro_accelerated_kernels] + - path: "tflite_models/tflite/keyword_spotting_on_off_v2.tflite" + file_id: flatbuffer_file_id + directory: "tflite" + condition: [tensorflow_lite_micro_accelerated_kernels] define: - name: DEBUG_EFM - name: TF_LITE_STATIC_MEMORY @@ -64,8 +69,8 @@ configuration: value: "4096" - name: SL_ML_AUDIO_FEATURE_GENERATION_AUDIO_GAIN value: "2" - - name: SL_TFLITE_MICRO_ARENA_SIZE - value: "7000" + - name: SL_TFLITE_MICRO_ARENA_SIZE + value: "50000" - name: SL_HEAP_SIZE value: "0x2000" - name: SL_SIMPLE_LED_LED1_PIN @@ -74,6 +79,8 @@ configuration: toolchain_settings: - option: gcc_compiler_option value: "-Wno-unused-parameter" + - option: gcc_compiler_option + value: "-Wno-missing-field-initializers" readme: - path: readme.md ui_hints: diff --git a/app/common/example/audio_classifier/readme.md b/app/common/example/audio_classifier/readme.md index 8d4f832584..bc072b0b06 100644 --- a/app/common/example/audio_classifier/readme.md +++ b/app/common/example/audio_classifier/readme.md @@ -30,21 +30,28 @@ being filtered out in the audio classifier application based on the label text. By default any labels that start with an underscore are ignored when processing results. This behavior can be disabled in the application configuration file. -## Model -The default model used in this application is called "audio_classifier.tflite" -and is able to classify audio into 4 different classes labeled "on", "off", -"_unknown_", "_silence_". The source for the model can be found here: https://github.com/siliconlabs/mltk/blob/master/mltk/models/siliconlabs/keyword_spotting_on_off.py +## Model +The application uses one of two different available models +(```keyword_spotting_on_off.tflite``` or ```keyword_spotting_on_off_v2.tflite```) +as the default model, depending on whether the application is generated for a +development board featuring an MVP hardware accelerator or not. When an MVP +hardware accelerator is featured on the board, inference will run at a faster +speed such that a larger model can be chosen, yielding more accurate keyword +detections. + +Details about the model architectures and scripts for generating the models can +be found in the [Silicon Labs machine learning applications](https://github.com/SiliconLabs/machine_learning_applications/tree/main/) repository, under +```voice/keyword_spotting/model```. The application is designed to work with an audio classification model created using the Silicon Labs Machine Learning Toolkit ([MLTK](https://siliconlabs.github.io/mltk)). Use the MLTK to train a new audio classifier model and replace the model inside this example with the new audio classification model. To replace the audio classification model with a new model -created using the MLTK you can rename the new .tflite file to -"audio_classifier.tflite" and copy it into the config/tflite folder of this -project. After a new .tflite file is added to the project Simplicity Studio will -automatically use the [flatbuffer converter tool](https://docs.silabs.com/gecko-platform/latest/machine-learning/tensorflow/flatbuffer-conversion) -to convert a .tflite file into a c file which is added to the project. +created using the MLTK simply replace the .tflite file in the config/tflite folder +of this project with your new. tflite file. After a new .tflite file is added +to the project Simplicity Studio will automatically use the [flatbuffer converter tool](https://docs.silabs.com/gecko-platform/latest/machine-learning/tensorflow/flatbuffer-conversion) +to convert the .tflite file into a c file which is added to the project. In order for the audio classification to work correctly we need to use the same audio feature generator configuration parameters for inference as is used when diff --git a/app/common/example/audio_classifier/recognize_commands.cc b/app/common/example/audio_classifier/recognize_commands.cc index 90bee9e517..4f21d4058b 100644 --- a/app/common/example/audio_classifier/recognize_commands.cc +++ b/app/common/example/audio_classifier/recognize_commands.cc @@ -19,6 +19,7 @@ #include #include + RecognizeCommands::RecognizeCommands(tflite::ErrorReporter* error_reporter, int32_t average_window_duration_ms, uint8_t detection_threshold, @@ -41,6 +42,10 @@ TfLiteStatus RecognizeCommands::ProcessLatestResults( const TfLiteTensor* latest_results, const int32_t current_time_ms, uint8_t* found_command_index, uint8_t* score, bool* is_new_command) { + int8_t current_top_index = 0; + uint32_t current_top_score = 0; + uint8_t converted_scores[category_count]; + if ((latest_results->dims->size != 2) || (latest_results->dims->data[0] != 1) || (latest_results->dims->data[1] != category_count)) { @@ -53,14 +58,6 @@ TfLiteStatus RecognizeCommands::ProcessLatestResults( return kTfLiteError; } - if (latest_results->type != kTfLiteInt8) { - TF_LITE_REPORT_ERROR( - error_reporter_, - "The results for recognition should be int8_t elements, but are %d", - latest_results->type); - return kTfLiteError; - } - if ((!previous_results_.empty()) && (current_time_ms < previous_results_.front().time_)) { TF_LITE_REPORT_ERROR( @@ -71,55 +68,86 @@ TfLiteStatus RecognizeCommands::ProcessLatestResults( return kTfLiteError; } - // Add the latest results to the head of the queue. - previous_results_.push_back({current_time_ms, latest_results->data.int8}); - - // Prune any earlier results that are too old for the averaging window. - const int64_t time_limit = current_time_ms - average_window_duration_ms_; - while ((!previous_results_.empty()) - && previous_results_.front().time_ < time_limit) { - previous_results_.pop_front(); + // Convert the model output to uint8 + if (latest_results->type == kTfLiteFloat32) { + for (int i = 0; i < category_count; ++i) { + converted_scores[i] = (uint8_t)(latest_results->data.f[i] * 255); + } + } else if (latest_results->type == kTfLiteInt8) { + for (int i = 0; i < category_count; ++i) { + converted_scores[i] = (uint8_t)(latest_results->data.int8[i] + 128); + } + } else { + TF_LITE_REPORT_ERROR(error_reporter_, "Unsupported output tensor data type, must be int8 or float32"); + return kTfLiteError; } - // If there are too few results, assume the result will be unreliable and - // bail. - const int32_t how_many_results = previous_results_.size(); - if ((how_many_results < minimum_count_)) { - *found_command_index = previous_top_label_index_; - *score = 0; - *is_new_command = false; - return kTfLiteOk; - } + // If the minimum count is 0, then disable averaging and only consider the latest result + if (minimum_count_ == 0) { + // Find the current highest scoring category + for (int i = 0; i < category_count; i++) { + if (converted_scores[i] > current_top_score) { + current_top_score = converted_scores[i]; + current_top_index = i; + } + } + } else { + // Add the latest results to the head of the queue. + previous_results_.push_back({current_time_ms, converted_scores}); + + // Prune any earlier results that are too old for the averaging window. + const int64_t time_limit = current_time_ms - average_window_duration_ms_; + while ((!previous_results_.empty()) + && previous_results_.front().time_ < time_limit) { + previous_results_.pop_front(); + } - // Calculate the average score across all the results in the window. - int32_t average_scores[category_count]; - for (int offset = 0; offset < previous_results_.size(); ++offset) { - // Iterates the amount of times to achieve average_window_duration - PreviousResultsQueue::Result previous_result = - previous_results_.from_front(offset); - const int8_t* scores = previous_result.scores; - for (int i = 0; i < category_count; ++i) { - if (offset == 0) { - average_scores[i] = scores[i] + 128; - } else { - average_scores[i] += scores[i] + 128; + // If there are too few results, assume the result will be unreliable and + // bail. + static int consecutive_min_count = 0; + const int32_t how_many_results = previous_results_.size(); + if ((how_many_results < minimum_count_)) { + ++consecutive_min_count; + if (consecutive_min_count % 10 == 0) { + printf("Too few samples for averaging. This likely means the inference loop is taking too long.\n"); + printf("Either decrease the 'minimum_count' and/or increase 'average_window_duration_ms'\n"); + } + *found_command_index = previous_top_label_index_; + *score = 0; + *is_new_command = false; + return kTfLiteOk; + } + consecutive_min_count = 0; + + // Calculate the average score across all the results in the window. + uint32_t average_scores[category_count]; + for (int offset = 0; offset < previous_results_.size(); ++offset) { + // Iterates the amount of times to achieve average_window_duration + PreviousResultsQueue::Result previous_result = + previous_results_.from_front(offset); + const uint8_t* scores = previous_result.scores; + for (int i = 0; i < category_count; ++i) { + if (offset == 0) { + average_scores[i] = scores[i]; + } else { + average_scores[i] += scores[i]; + } } } - } - for (int i = 0; i < category_count; ++i) { - average_scores[i] /= how_many_results; - } + for (int i = 0; i < category_count; ++i) { + average_scores[i] /= how_many_results; + } - // Find the current highest scoring category. - int8_t current_top_index = 0; - int32_t current_top_score = 0; - for (int i = 0; i < category_count; ++i) { - if (average_scores[i] > current_top_score) { - current_top_score = average_scores[i]; - current_top_index = i; + // Find the current highest scoring category. + for (int i = 0; i < category_count; ++i) { + if (average_scores[i] > current_top_score) { + current_top_score = average_scores[i]; + current_top_index = i; + } } } + const char *current_top_label = get_category_label(current_top_index); // If we've recently had another label trigger, assume one that occurs too @@ -147,7 +175,7 @@ TfLiteStatus RecognizeCommands::ProcessLatestResults( prev_time_ms = current_time_ms; ptr += sprintf(ptr, "[%6ld] (%3d) ", current_time_ms, diff); for (int i = 0; i < category_count; ++i) { - ptr += sprintf(ptr, "%3ld ", average_scores[i]); + ptr += sprintf(ptr, "%3d ", converted_scores[i]); } *ptr++ = 0; puts(buffer); diff --git a/app/common/example/audio_classifier/recognize_commands.h b/app/common/example/audio_classifier/recognize_commands.h index 3c96dd02e5..a21eb31428 100644 --- a/app/common/example/audio_classifier/recognize_commands.h +++ b/app/common/example/audio_classifier/recognize_commands.h @@ -42,13 +42,13 @@ class PreviousResultsQueue { struct Result { Result() : time_(0), scores() { } - Result(int32_t time, int8_t * input_scores) : time_(time) { + Result(int32_t time, uint8_t * input_scores) : time_(time) { for (int i = 0; i < category_count; ++i) { scores[i] = input_scores[i]; } } int32_t time_; - int8_t scores[MAX_CATEGORY_COUNT]; + uint8_t scores[MAX_CATEGORY_COUNT]; }; int size() diff --git a/app/common/example/voice_control_light/config/tflite/keyword_spotting_on_off.tflite b/app/common/example/audio_classifier/tflite_models/tflite/keyword_spotting_on_off.tflite similarity index 100% rename from app/common/example/voice_control_light/config/tflite/keyword_spotting_on_off.tflite rename to app/common/example/audio_classifier/tflite_models/tflite/keyword_spotting_on_off.tflite diff --git a/app/common/example/audio_classifier/tflite_models/tflite/keyword_spotting_on_off_v2.tflite b/app/common/example/audio_classifier/tflite_models/tflite/keyword_spotting_on_off_v2.tflite new file mode 100644 index 0000000000..8f926c576b Binary files /dev/null and b/app/common/example/audio_classifier/tflite_models/tflite/keyword_spotting_on_off_v2.tflite differ diff --git a/app/common/example/cpc_secondary_vcom_security_micriumos/cpc_secondary_vcom_security_micriumos.slcp b/app/common/example/cpc_secondary_vcom_security_micriumos/cpc_secondary_vcom_security_micriumos.slcp index 5b48c6815a..83b7cbe319 100644 --- a/app/common/example/cpc_secondary_vcom_security_micriumos/cpc_secondary_vcom_security_micriumos.slcp +++ b/app/common/example/cpc_secondary_vcom_security_micriumos/cpc_secondary_vcom_security_micriumos.slcp @@ -1,4 +1,4 @@ -project_name: cpc_secondary_vcom_micriumos_security +project_name: cpc_secondary_vcom_security_micriumos package: platform quality: production label: Platform - CPC Secondary with Micrium OS and Security Enabled diff --git a/app/common/example/dci_swd_programming/readme.md b/app/common/example/dci_swd_programming/readme.md index 549c38215b..5e6aabff32 100644 --- a/app/common/example/dci_swd_programming/readme.md +++ b/app/common/example/dci_swd_programming/readme.md @@ -54,7 +54,7 @@ The following SWD operations are supported in this example: 1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 2. Open any terminal program and connect to the kit’s VCOM port. -3. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). +3. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). 4. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). 5. Run the example and follow the instructions shown on the console. diff --git a/app/common/example/psa_crypto_aead/readme.md b/app/common/example/psa_crypto_aead/readme.md index af33b22096..f7b34de0af 100644 --- a/app/common/example/psa_crypto_aead/readme.md +++ b/app/common/example/psa_crypto_aead/readme.md @@ -94,7 +94,7 @@ The following PSA Crypto APIs are used in this example: 1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 2. Upgrade the device’s SE firmware to the latest version when Series 2 device is used (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 3. Open any terminal program and connect to the kit’s VCOM port (if using `Device Console` in Simplicity Studio 5, `Line terminator:` must be set to `None`). -4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). 5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). 6. Run the example and follow the instructions shown on the console. diff --git a/app/common/example/psa_crypto_asymmetric_key/readme.md b/app/common/example/psa_crypto_asymmetric_key/readme.md index e19030c8d3..c4e637b889 100644 --- a/app/common/example/psa_crypto_asymmetric_key/readme.md +++ b/app/common/example/psa_crypto_asymmetric_key/readme.md @@ -105,7 +105,7 @@ The following PSA Crypto APIs are used in this example: 1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 2. Upgrade the device’s SE firmware to the latest version when Series 2 device is used (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 3. Open any terminal program and connect to the kit’s VCOM port (if using `Device Console` in Simplicity Studio 5, `Line terminator:` must be set to `None`). -4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). 5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). 6. Run the example and follow the instructions shown on the console. diff --git a/app/common/example/psa_crypto_cipher/app_process.c b/app/common/example/psa_crypto_cipher/app_process.c index 50fb80d462..c097d520e8 100644 --- a/app/common/example/psa_crypto_cipher/app_process.c +++ b/app/common/example/psa_crypto_cipher/app_process.c @@ -630,7 +630,7 @@ void app_process_action(void) printf(" + Destroying a %d-bit %s key... ", sizeof(cfb_key) * 8, symmetric_key_storage_string[symmetric_key_storage_select]); if (destroy_key() != PSA_SUCCESS) { - return; + break; } // Start encryption encrypt_decrypt = false; @@ -771,7 +771,7 @@ void app_process_action(void) printf(" + Destroying a %d-bit %s key... ", sizeof(ctr_key) * 8, symmetric_key_storage_string[symmetric_key_storage_select]); if (destroy_key() != PSA_SUCCESS) { - return; + break; } // Start encryption encrypt_decrypt = false; @@ -913,7 +913,7 @@ void app_process_action(void) printf(" + Destroying a %d-bit %s key... ", sizeof(chacha20_key) * 8, symmetric_key_storage_string[symmetric_key_storage_select]); if (destroy_key() != PSA_SUCCESS) { - return; + break; } encrypt_decrypt = false; print_key_storage(); diff --git a/app/common/example/psa_crypto_cipher/readme.md b/app/common/example/psa_crypto_cipher/readme.md index bd94afc7d1..74d547fd79 100644 --- a/app/common/example/psa_crypto_cipher/readme.md +++ b/app/common/example/psa_crypto_cipher/readme.md @@ -129,7 +129,7 @@ The following PSA Crypto APIs are used in this example: 1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 2. Upgrade the device’s SE firmware to the latest version when Series 2 device is used (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 3. Open any terminal program and connect to the kit’s VCOM port (if using `Device Console` in Simplicity Studio 5, `Line terminator:` must be set to `None`). -4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). 5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). 6. Run the example and follow the instructions shown on the console. diff --git a/app/common/example/psa_crypto_dsa/readme.md b/app/common/example/psa_crypto_dsa/readme.md index 1b74fa3f2f..6addc193d1 100644 --- a/app/common/example/psa_crypto_dsa/readme.md +++ b/app/common/example/psa_crypto_dsa/readme.md @@ -159,7 +159,7 @@ The following PSA Crypto APIs are used in this example: 1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 2. Upgrade the device’s SE firmware to the latest version when Series 2 device is used (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 3. Open any terminal program and connect to the kit’s VCOM port (if using `Device Console` in Simplicity Studio 5, `Line terminator:` must be set to `None`). -4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). 5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). 6. Run the example and follow the instructions shown on the console. diff --git a/app/common/example/psa_crypto_ecdh/readme.md b/app/common/example/psa_crypto_ecdh/readme.md index 59187cde80..049d2e07ad 100644 --- a/app/common/example/psa_crypto_ecdh/readme.md +++ b/app/common/example/psa_crypto_ecdh/readme.md @@ -89,7 +89,7 @@ The following PSA Crypto APIs are used in this example: 1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 2. Upgrade the device’s SE firmware to the latest version when Series 2 device is used (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 3. Open any terminal program and connect to the kit’s VCOM port (if using `Device Console` in Simplicity Studio 5, `Line terminator:` must be set to `None`). -4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). 5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). 6. Run the example and follow the instructions shown on the console. diff --git a/app/common/example/psa_crypto_hash/readme.md b/app/common/example/psa_crypto_hash/readme.md index 9447aa3529..bacc875200 100644 --- a/app/common/example/psa_crypto_hash/readme.md +++ b/app/common/example/psa_crypto_hash/readme.md @@ -62,7 +62,7 @@ The following PSA Crypto APIs are used in this example: 1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 2. Upgrade the device’s SE firmware to the latest version when Series 2 device is used (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 3. Open any terminal program and connect to the kit’s VCOM port (if using `Device Console` in Simplicity Studio 5, `Line terminator:` must be set to `None`). -4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). 5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). 6. Run the example and follow the instructions shown on the console. diff --git a/app/common/example/psa_crypto_kdf/readme.md b/app/common/example/psa_crypto_kdf/readme.md index 38c85bcfc2..f78e30b171 100644 --- a/app/common/example/psa_crypto_kdf/readme.md +++ b/app/common/example/psa_crypto_kdf/readme.md @@ -125,7 +125,7 @@ The following PSA Crypto APIs are used in this example: 1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 2. Upgrade the device’s SE firmware to the latest version when Series 2 device is used (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 3. Open any terminal program and connect to the kit’s VCOM port (if using `Device Console` in Simplicity Studio 5, `Line terminator:` must be set to `None`). -4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). 5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). 6. Run the example and follow the instructions shown on the console. diff --git a/app/common/example/psa_crypto_mac/readme.md b/app/common/example/psa_crypto_mac/readme.md index 37c2e4ec31..9083841eb4 100644 --- a/app/common/example/psa_crypto_mac/readme.md +++ b/app/common/example/psa_crypto_mac/readme.md @@ -107,7 +107,7 @@ The following PSA Crypto APIs are used in this example: 1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 2. Upgrade the device’s SE firmware to the latest version when Series 2 device is used (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 3. Open any terminal program and connect to the kit’s VCOM port (if using `Device Console` in Simplicity Studio 5, `Line terminator:` must be set to `None`). -4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). 5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). 6. Run the example and follow the instructions shown on the console. diff --git a/app/common/example/psa_crypto_symmetric_key/readme.md b/app/common/example/psa_crypto_symmetric_key/readme.md index 91355a4541..e4ad232640 100644 --- a/app/common/example/psa_crypto_symmetric_key/readme.md +++ b/app/common/example/psa_crypto_symmetric_key/readme.md @@ -97,7 +97,7 @@ The following PSA Crypto APIs are used in this example: 1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 2. Upgrade the device’s SE firmware to the latest version when Series 2 device is used (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 3. Open any terminal program and connect to the kit’s VCOM port (if using `Device Console` in Simplicity Studio 5, `Line terminator:` must be set to `None`). -4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). 5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). 6. Run the example and follow the instructions shown on the console. diff --git a/app/common/example/psa_crypto_x509/readme.md b/app/common/example/psa_crypto_x509/readme.md index ed32a6db30..6eab62c672 100644 --- a/app/common/example/psa_crypto_x509/readme.md +++ b/app/common/example/psa_crypto_x509/readme.md @@ -157,7 +157,7 @@ The following Mbed TLS APIs are used in this example: 1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 2. Upgrade the device’s SE firmware to the latest version when Series 2 device is used (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 3. Open any terminal program and connect to the kit’s VCOM port (if using `Device Console` in Simplicity Studio 5, `Line terminator:` must be set to `None`). -4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). 5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). 6. Run the example and follow the instructions shown on the console. diff --git a/app/common/example/se_manager_asymmetric_key_handling/readme.md b/app/common/example/se_manager_asymmetric_key_handling/readme.md index a5cd8f8e44..002f6e48a4 100644 --- a/app/common/example/se_manager_asymmetric_key_handling/readme.md +++ b/app/common/example/se_manager_asymmetric_key_handling/readme.md @@ -77,7 +77,7 @@ The following SE Manager APIs are used in this example: 1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 2. Upgrade the device’s SE firmware to the latest version (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 3. Open any terminal program and connect to the kit’s VCOM port (if using `Device Console` in Simplicity Studio 5, `Line terminator:` must be set to `None`). -4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). 5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). 6. Run the example and follow the instructions shown on the console. diff --git a/app/common/example/se_manager_attestation/readme.md b/app/common/example/se_manager_attestation/readme.md index 25b3b32bea..d392c41296 100644 --- a/app/common/example/se_manager_attestation/readme.md +++ b/app/common/example/se_manager_attestation/readme.md @@ -1,5 +1,8 @@ -#SE Manager Attestation +# SE Manager Attestation + + This example uses the SE Manager API to fetch attestation tokens on the supported Series 2 device. + The example also contains code that demonstrates how the tokens can be parsed and printed in a human-readable format. Parsing and printing of tokens on the actual device might not be a strictly typical use case, but it is nevertheless included in order to showcase the structure and capabilities of the supported attestation tokens. @@ -9,27 +12,35 @@ An attestation token provided by the SE Manager API is a COSE_Sign1 structure th The example redirects standard I/O to the virtual serial port (VCOM) of the kit. By default, the serial port setting is 115200 bps and 8-N-1 configuration. -The example has been instrumented with code to count the number of clock cycles spent in different operations. The results are printed on the VCOM serial port console. This feature can be disabled by defining SE_MANAGER_PRINT=0 (default is 1) in the IDE setting (Preprocessor->Defined symbols). +The example has been instrumented with code to count the number of clock cycles spent in different operations. The results are printed on the VCOM serial port console. This feature can be disabled by defining `SE_MANAGER_PRINT=0` (default is 1) in the IDE setting (`Preprocessor->Defined symbols`). + +## SE Manager API + -##SE Manager API The following SE Manager APIs are used in this example: -sl_se_init -sl_se_deinit -sl_se_init_command_context -sl_se_deinit_command_context -sl_se_get_random -sl_se_attestation_get_psa_iat_token -sl_se_attestation_get_config_token - -##Getting Started -Upgrade the kit’s firmware to the latest version (see Adapter Firmware under General Device Information in the Simplicity Studio 5 User's Guide). -Upgrade the device’s SE firmware to the latest version (see Secure Firmware under General Device Information in the Simplicity Studio 5 User's Guide). -Open any terminal program and connect to the kit’s VCOM port. -Create this platform example project in the Simplicity IDE (see Examples in the Simplicity Studio 5 User's Guide, check Platform() checkbox to browse the platform examples). -Build the example and download it to the kit (see Simple Build and Flash Programmer in the Simplicity Studio 5 User's Guide). -Run the example and the console should display the process steps of this example. - -##Additional Information -###Resources -[SE Manager API](https://docs.silabs.com/gecko-platform/latest/service/api/group-sl-se-manager) + +* `sl_se_init` +* `sl_se_deinit` +* `sl_se_init_command_context` +* `sl_se_deinit_command_context` +* `sl_se_get_random` +* `sl_se_attestation_get_psa_iat_token` +* `sl_se_attestation_get_config_token` + + +## Getting Started + + +1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). +2. Upgrade the device’s SE firmware to the latest version (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). +3. Open any terminal program and connect to the kit’s VCOM port (if using `Device Console` in Simplicity Studio 5, `Line terminator:` must be set to `None`). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). +5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). +6. Run the example and follow the instructions shown on the console. + + +## Resources + + +[SE Manager API](https://docs.silabs.com/gecko-platform/latest/service/api/group-sl-se-manager) \ No newline at end of file diff --git a/app/common/example/se_manager_block_cipher/readme.md b/app/common/example/se_manager_block_cipher/readme.md index eb6a01e66c..2cf37c79c0 100644 --- a/app/common/example/se_manager_block_cipher/readme.md +++ b/app/common/example/se_manager_block_cipher/readme.md @@ -117,7 +117,7 @@ The following SE Manager APIs are used in this example: 1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 2. Upgrade the device’s SE firmware to the latest version (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 3. Open any terminal program and connect to the kit’s VCOM port (if using `Device Console` in Simplicity Studio 5, `Line terminator:` must be set to `None`). -4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). 5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). 6. Run the example and follow the instructions shown on the console. diff --git a/app/common/example/se_manager_ecdh/readme.md b/app/common/example/se_manager_ecdh/readme.md index 1a44f7f977..a68877ba40 100644 --- a/app/common/example/se_manager_ecdh/readme.md +++ b/app/common/example/se_manager_ecdh/readme.md @@ -73,7 +73,7 @@ The following SE Manager APIs are used in this example: 1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 2. Upgrade the device’s SE firmware to the latest version (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 3. Open any terminal program and connect to the kit’s VCOM port (if using `Device Console` in Simplicity Studio 5, `Line terminator:` must be set to `None`). -4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). 5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). 6. Run the example and follow the instructions shown on the console. diff --git a/app/common/example/se_manager_ecjpake/readme.md b/app/common/example/se_manager_ecjpake/readme.md index 5ce1bac026..0b465981ef 100644 --- a/app/common/example/se_manager_ecjpake/readme.md +++ b/app/common/example/se_manager_ecjpake/readme.md @@ -43,7 +43,7 @@ The following SE Manager APIs are used in this example: 1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 2. Upgrade the device’s SE firmware to the latest version (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 3. Open any terminal program and connect to the kit’s VCOM port. -4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). 5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). 6. Run the example and the console should display the process steps of this example. diff --git a/app/common/example/se_manager_hash/readme.md b/app/common/example/se_manager_hash/readme.md index 78c6007507..208ff61d56 100644 --- a/app/common/example/se_manager_hash/readme.md +++ b/app/common/example/se_manager_hash/readme.md @@ -68,7 +68,7 @@ The following SE Manager APIs are used in this example: 1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 2. Upgrade the device’s SE firmware to the latest version (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 3. Open any terminal program and connect to the kit’s VCOM port (if using `Device Console` in Simplicity Studio 5, `Line terminator:` must be set to `None`). -4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). 5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). 6. Run the example and follow the instructions shown on the console. diff --git a/app/common/example/se_manager_host_firmware_upgrade/readme.md b/app/common/example/se_manager_host_firmware_upgrade/readme.md index 72d97cdc28..251de07cf5 100644 --- a/app/common/example/se_manager_host_firmware_upgrade/readme.md +++ b/app/common/example/se_manager_host_firmware_upgrade/readme.md @@ -39,7 +39,7 @@ The following SE Manager APIs are used in this example: 1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 2. Upgrade the device’s SE firmware to the latest version (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 3. Open any terminal program and connect to the kit’s VCOM port (if using `Device Console` in Simplicity Studio 5, `Line terminator:` must be set to `None`). -4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). 5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). 6. Run the example and follow the instructions shown on the console. diff --git a/app/common/example/se_manager_kdf/readme.md b/app/common/example/se_manager_kdf/readme.md index 68c9bee934..5dc9702d3d 100644 --- a/app/common/example/se_manager_kdf/readme.md +++ b/app/common/example/se_manager_kdf/readme.md @@ -42,7 +42,7 @@ The following SE Manager APIs are used in this example: 1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 2. Upgrade the device’s SE firmware to the latest version (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 3. Open any terminal program and connect to the kit’s VCOM port. -4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). 5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). 6. Run the example and the console should display the process steps of this example. diff --git a/app/common/example/se_manager_key_provisioning/readme.md b/app/common/example/se_manager_key_provisioning/readme.md index abf8212e98..58d438fd24 100644 --- a/app/common/example/se_manager_key_provisioning/readme.md +++ b/app/common/example/se_manager_key_provisioning/readme.md @@ -75,7 +75,7 @@ The following SE Manager APIs are used in this example: 1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 2. Upgrade the device’s SE firmware to the latest version (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 3. Open any terminal program and connect to the kit’s VCOM port (if using `Device Console` in Simplicity Studio 5, `Line terminator:` must be set to `None`). -4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). 5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). 6. Run the example and follow the instructions shown on the console. diff --git a/app/common/example/se_manager_se_firmware_upgrade/app_se_firmware_image.c b/app/common/example/se_manager_se_firmware_upgrade/app_se_firmware_image.c index 744cf5647b..b320d6e0ca 100644 --- a/app/common/example/se_manager_se_firmware_upgrade/app_se_firmware_image.c +++ b/app/common/example/se_manager_se_firmware_upgrade/app_se_firmware_image.c @@ -8106,6 +8106,905 @@ SL_ALIGN(4) static const uint8_t se_firmware_image[] SL_ATTRIBUTE_ALIGN(4) = 0x7A, 0xE3, 0xBB, 0x17, 0xC8, 0x3C, 0x83, 0xCA, 0xAC, 0xCA, 0x7B, 0x24, 0xAF, 0x5D, 0x5D, 0x9E, 0xCD, 0x56, 0x6B, 0x38, 0xE9, 0x12, 0x5A, 0xF1, 0x4F, 0xF0, 0x3B, 0xA7, 0x12, 0xA0, 0xE8, 0x5E, 0x51, 0xCD, 0xAF, 0xEB, 0xA2, 0x8D, 0x7B, 0x82, 0xA3, 0x43, 0x2D, 0x7A, 0x04, 0xB8, 0x61, 0x05, 0x25, 0x4E, 0xD3, 0x20, 0xB3, 0x6C, 0x24, 0x2F, 0x7C, 0x14, 0xD8, 0x19, 0x6B, 0x3A, 0x45, 0xEE, 0xFA, 0x26, 0xA0, 0xC4, 0x3F, 0xE6, 0x89, 0xCA, 0xC4, 0x69, 0xE6, 0xAB, 0x41, 0x46, 0x57, 0xBE, 0xAB, 0x1A, 0x0F, 0x84, 0x40, 0x9E, 0xFA, 0x9D, 0x44, 0x31, 0x21, 0xBB, 0x7D, 0x1C, 0x63, 0x7B, 0x62, 0xCC, 0x6A, 0xD1, 0x64, 0x3C, 0x15, 0xA1, 0xCB +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) // EFR32xG27 v2.2.0 + 0xEB, 0x17, 0xA6, 0x5E, 0x45, 0x8C, 0x00, 0x00, 0xA8, 0x8B, 0x00, 0x00, 0x00, 0x02, 0x02, 0x06, 0x01, 0x01, 0x00, 0x00, 0x73, 0x86, 0xD4, 0x38, 0x58, 0xEA, 0xB9, 0x8F, 0xCF, 0xF5, 0xDA, 0xF9, 0x22, 0xFA, 0x4B, 0x0F, 0x49, 0xED, 0x2F, 0x6D, + 0xC9, 0xDD, 0x73, 0xA5, 0xAA, 0x85, 0x5B, 0xCF, 0xC3, 0xD2, 0x9C, 0x4C, 0x00, 0xA9, 0xFB, 0x36, 0x32, 0x96, 0x9E, 0x90, 0xE0, 0xBE, 0xDD, 0x14, 0xEC, 0x23, 0xFA, 0x78, 0xF8, 0x77, 0xE7, 0x12, 0x7F, 0xF7, 0xD0, 0x85, 0x98, 0xF9, 0x71, 0x51, + 0xD2, 0xDA, 0x3D, 0x92, 0xC7, 0xC7, 0x0F, 0x13, 0xA4, 0xB3, 0x18, 0xDD, 0xD0, 0x65, 0x59, 0x6F, 0x06, 0xBE, 0x24, 0x3E, 0x00, 0x0C, 0xD0, 0xCD, 0x4A, 0xCE, 0x67, 0xFE, 0x9F, 0x82, 0x40, 0x82, 0xFB, 0xB7, 0x2E, 0xD1, 0xD9, 0xFC, 0x2E, 0xE9, + 0xC4, 0x8F, 0xF3, 0xD3, 0xA3, 0x3B, 0xB1, 0x09, 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0xDE, 0xE9, + 0x97, 0x30, 0xCA, 0xCE, 0xB8, 0x1A, 0x47, 0xBA, 0xC3, 0x25, 0x67, 0x16, 0xF9, 0x13, 0xAA, 0x20, 0xBF, 0x5D, 0x07, 0x81, 0x94, 0xDA, 0x55, 0xB4, 0xE6, 0xB6, 0x7F, 0x77, 0xE7, 0xF6, 0x76, 0x58, 0xA0, 0xFE, 0x59, 0xC3, 0xB8, 0xC5, 0x1B, 0x3D, + 0x15, 0x13, 0x15, 0x50, 0xD5, 0x9D, 0x00, 0x81, 0x98, 0xFE, 0x9C, 0x58, 0x1B, 0x85, 0x45, 0xF8, 0xF0, 0x18, 0x22, 0xC6, 0x80, 0x35, 0xEE, 0x45, 0xE1, 0xC1, 0x09, 0xA6, 0x02, 0xF2, 0x82, 0xB0, 0x6B, 0x3C, 0x1D, 0x73, 0x82, 0xAC, 0xB8, 0x65, + 0x67, 0x21, 0x00, 0xDC, 0xAB, 0xD8, 0xA7, 0x71, 0x5F, 0xBE, 0xB9, 0xEB, 0xC8, 0x68, 0x03, 0x1B, 0x62, 0x9C, 0x02, 0x56, 0x36, 0xE2, 0x83, 0x73, 0x88, 0x48, 0x19, 0x18, 0xC7, 0x5F, 0x44, 0x98, 0xB9, 0xEB, 0x30, 0xEE, 0x82, 0x48, 0x40, 0x53, + 0xD2, 0x38, 0x75, 0xC2, 0xED, 0xE3, 0x58, 0x08, 0xFD, 0xCB, 0x67, 0x38, 0x0C, 0x5E, 0x1E, 0xF8, 0xF0, 0xBC, 0xCB, 0x68, 0xBB, 0xEA, 0xB4, 0x28, 0xDF, 0xDC, 0x63, 0xC8, 0x43, 0xA9, 0x29, 0x05, 0x94, 0xFE, 0xE3, 0x3D, 0xE4, 0x88, 0x8E, 0x42, + 0x77, 0x72, 0xAE, 0x0E, 0xA9, 0xB4, 0x2C, 0x97, 0xCE, 0xFF, 0xF9, 0x01, 0x16, 0x13, 0x40, 0x7D, 0xC9, 0xD2, 0x6F, 0xE8, 0x72, 0xF7, 0x6F, 0x51, 0x07, 0xAC, 0x7A, 0x35, 0xC3, 0x4F, 0x17, 0x36, 0x28, 0x7E, 0xBB, 0xA9, 0x3F, 0x42, 0x7F, 0x17, + 0x6C, 0xA3, 0x69, 0x0E, 0x46, 0x41, 0xB0, 0xD7, 0x0E, 0x24, 0x35, 0xAF, 0xE5, 0x12, 0x0F, 0x3D, 0x89, 0xD6, 0x66, 0x6F, 0xA9, 0x56, 0x79, 0x05, 0x3A, 0x9F, 0xA9, 0x0E, 0x54, 0xC6, 0x48, 0xA1, 0x8E, 0x17, 0xE8, 0xEF, 0x89, 0x5A, 0x84, 0xF2, + 0xC9, 0x49, 0xF0, 0x20, 0xFE, 0x19, 0x49, 0xBC, 0x19, 0xBB, 0x0D, 0x87, 0x31, 0xAA, 0xFD, 0x3A, 0x6C, 0xD4, 0x65, 0x33, 0x22, 0xB6, 0xA8, 0x57, 0x48, 0xD3, 0xE2, 0x9E, 0xE8, 0x16, 0xE9, 0x46, 0xF0, 0xC7, 0x14, 0x88, 0x61, 0x86, 0x6C, 0x92, + 0xA0, 0x95, 0x4A, 0x8E, 0x93, 0xDD, 0x44, 0x83, 0xC2, 0x7C, 0x20, 0x82, 0xA3, 0x62, 0xD1, 0x95, 0xF4, 0xB4, 0xA5, 0x8B, 0xCC, 0x14, 0x25, 0xA7, 0x76, 0x94, 0x5D, 0xBD, 0x07, 0xF6, 0x30, 0x2E, 0x21, 0xDF, 0xC4, 0x3A, 0x30, 0xD0, 0x6D, 0x45, + 0xA2, 0x03, 0x08, 0xC0, 0x97, 0xB0, 0xAE, 0x4D, 0xA1, 0xD8, 0x2E, 0x7B, 0x06, 0x43, 0x3D, 0x5E, 0x4C, 0x9E, 0x6C, 0xBD, 0xA3, 0x12, 0x3A, 0x33, 0x33, 0x2E, 0x99, 0x59, 0x02, 0xA4, 0xB9, 0x2F, 0x64, 0x67, 0xF8, 0x10, 0xE0, 0x9F, 0x00, 0x00, + 0x2A, 0xAD, 0x34, 0x57, 0x60, 0x4C, 0xF1, 0x68, 0xF0, 0x3B, 0xE9, 0xA0, 0x8C, 0x9A, 0x34, 0xF9, 0x56, 0x09, 0x8B, 0xC8, 0xD5, 0x85, 0xC2, 0xB7, 0xEF, 0x33, 0x2B, 0x41, 0xB7, 0x14, 0x14, 0xC4, 0x46, 0x32, 0x0B, 0xBF, 0x6C, 0x30, 0x28, 0xBF, + 0xB4, 0x1E, 0x37, 0xE5, 0x9C, 0xCF, 0xFD, 0xC0, 0x09, 0xDB, 0x96, 0xB0, 0xB0, 0xF1, 0x60, 0x40, 0xD2, 0xB1, 0x59, 0xF0, 0x25, 0x2D, 0xF0, 0x93, 0x1E, 0x33, 0x9B, 0x73, 0x7D, 0x87, 0x8D, 0x67, 0x72, 0x78, 0xF1, 0x57, 0xDC, 0xB4, 0xBD, 0x17, + 0xF5, 0xE7, 0x06, 0x16, 0xA6, 0x78, 0xD2, 0x27, 0x62, 0x3C, 0x38, 0x8C, 0xED, 0x69, 0xA5, 0x1D, 0x4E, 0x81, 0x03, 0x34, 0x2A, 0xC8, 0x76, 0x95, 0x0C, 0xAB, 0x7B, 0x94, 0x27, 0x18, 0x97, 0x47, 0x4B, 0x33, 0x80, 0x1C, 0x3A #else #error "Undefined device" #endif diff --git a/app/common/example/se_manager_se_firmware_upgrade/readme.md b/app/common/example/se_manager_se_firmware_upgrade/readme.md index f1aef6a61e..a4c15cacdd 100644 --- a/app/common/example/se_manager_se_firmware_upgrade/readme.md +++ b/app/common/example/se_manager_se_firmware_upgrade/readme.md @@ -1,33 +1,29 @@ # SE Manager SE Firmware Upgrade - This example uses the SE Manager API to upgrade the SE firmware on the supported Series 2 device. +The SE upgrade firmware image must be stored to the device's internal flash in `.seu` format. The latest SE firmware image (`.seu` and `.hex`) and release notes can be found in the Windows folder below. -The SE upgrade firmware image must be stored to the device’s internal flash in `.seu` format. The latest SE firmware image (`.sec` and `.hex`) can be found in the Windows folders below (`v3.1` or above). - +For GSDK v3.2 and lower:
-*C:\SiliconLabs\SimplicityStudio\v5\developer\sdks\gecko\_sdk\_suite\v3.1\util\se\_release\public* +_C:\SiliconLabs\SimplicityStudio\v5\developer\sdks\GSDK VERSION\util\se_release\public_ +For GSDK v4.0 and higher:
-The SE firmware image (`.sec`) can be converted to a C source file with the SEGGER free utility [Bin2C.exe](https://www.segger.com/free-utilities/bin2c/). Copy the SE firmware image data array (discard the last `NULL-0x00` character) in the converted C file to `se_firmware_image[]` array in `app_se_firmware_image.c`. +_C:\Users\PC USER NAME\SimplicityStudio\SDKs\gecko_sdk\util\se_release\public_ +The SE firmware image (`.seu`) can be converted to a C source file by SEGGER free utility [Bin2C.exe](https://www.segger.com/free-utilities/bin2c/). Copy the SE firmware image data array (discard the last `NULL-0x00` character) in converted C file to `se_firmware_image[]` array in `app_se_firmware_image.c`. The SE firmware image validation will fail if the image version is equal to or less than the current SE firmware version. - The example redirects standard I/O to the virtual serial port (VCOM) of the kit. By default, the serial port setting is 115200 bps and 8-N-1 configuration. - The example has been instrumented with code to count the number of clock cycles spent in different operations. The results are printed on the VCOM serial port console. This feature can be disabled by defining `SE_MANAGER_PRINT=0` (default is 1) in the IDE setting (`Preprocessor->Defined symbols`). - ## SE Manager API - The following SE Manager APIs are used in this example: - * `sl_se_init` * `sl_se_deinit` * `sl_se_init_command_context` @@ -39,34 +35,25 @@ The following SE Manager APIs are used in this example: * `sl_se_read_executed_command` (VSE only) * `sl_se_ack_command` (VSE only) - ## Getting Started - -1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). -2. Upgrade the device’s SE firmware to the latest version (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). -3. Open any terminal program and connect to the kit’s VCOM port (if using `Device Console` in Simplicity Studio 5, `Line terminator:` must be set to `None`). -4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). -5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). +1. Upgrade the kit's firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in Simplicity Studio 5 Users Guide). +2. Upgrade the device's SE firmware to the latest version (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in Simplicity Studio 5 Users Guide). +3. Open any terminal program and connect to the kit's VCOM port (if using `Device Console` in Simplicity Studio 5, `Line terminator:` must be set to `None`). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in Simplicity Studio 5 Users Guide). +5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in Simplicity Studio 5 Users Guide). 6. Run the example and follow the instructions shown on the console. - ## Additional Information - 1. The current version for HSE or VSE firmware upgrade can be found in the `app_se_firmware_image.c`. 2. For a device with VSE, a reset will be issued when running specified SE Manager APIs. -3. EFR32xG23 and EFR32xG24 devices require SE firmware `v2.0.1` or above to run this example. +3. EFR32xG23 and EFR32xG24 devices require SE firmware v2.0.1 or above to run this example. 4. The device should disconnect from the debugger when upgrading the HSE or VSE firmware. 5. The default optimization level is `Optimize for debugging (-Og)` on Simplicity IDE and `None` on IAR Embedded Workbench. - ## Resources - [SE Manager API](https://docs.silabs.com/gecko-platform/latest/service/api/group-sl-se-manager) - [AN1222: Production Programming of Series 2 Devices](https://www.silabs.com/documents/public/application-notes/an1222-efr32xg2x-production-programming.pdf) - - diff --git a/app/common/example/se_manager_secure_debug/readme.md b/app/common/example/se_manager_secure_debug/readme.md index 3551f2834d..2c151633b4 100644 --- a/app/common/example/se_manager_secure_debug/readme.md +++ b/app/common/example/se_manager_secure_debug/readme.md @@ -71,7 +71,7 @@ The following SE Manager APIs are used in this example: 1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 2. Upgrade the device’s SE firmware to the latest version (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 3. Open any terminal program and connect to the kit’s VCOM port (if using `Device Console` in Simplicity Studio 5, `Line terminator:` must be set to `None`). -4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). 5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). 6. Run the example and follow the instructions shown on the console. diff --git a/app/common/example/se_manager_secure_identity/app_se_manager_secure_identity.c b/app/common/example/se_manager_secure_identity/app_se_manager_secure_identity.c index d0c1204416..18f7105682 100644 --- a/app/common/example/se_manager_secure_identity/app_se_manager_secure_identity.c +++ b/app/common/example/se_manager_secure_identity/app_se_manager_secure_identity.c @@ -53,9 +53,6 @@ static uint8_t pub_device_key_buf[SL_SE_CERT_KEY_SIZE]; /// Signature buffer static uint8_t signature_buf[SL_SE_CERT_SIGN_SIZE]; -/// Number of bytes actually used in the token. -static size_t token_len; - // ----------------------------------------------------------------------------- // Public Function Definitions // ----------------------------------------------------------------------------- @@ -99,14 +96,6 @@ uint8_t * get_pub_device_key_buf_ptr(void) return(pub_device_key_buf); } -/***************************************************************************//** - * Get token length. - ******************************************************************************/ -size_t get_token_len(void) -{ - return(token_len); -} - /***************************************************************************//** * Initialize the SE Manager. ******************************************************************************/ diff --git a/app/common/example/se_manager_secure_identity/app_se_manager_secure_identity.h b/app/common/example/se_manager_secure_identity/app_se_manager_secure_identity.h index 5abaf9c384..7f2ebbe115 100644 --- a/app/common/example/se_manager_secure_identity/app_se_manager_secure_identity.h +++ b/app/common/example/se_manager_secure_identity/app_se_manager_secure_identity.h @@ -72,13 +72,6 @@ uint8_t * get_cert_buf_ptr(void); ******************************************************************************/ uint8_t * get_pub_device_key_buf_ptr(void); -/***************************************************************************//** - * Get token length. - * - * @returns Returns length of the token. - ******************************************************************************/ -size_t get_token_len(void); - /***************************************************************************//** * Initialize the SE Manager. * diff --git a/app/common/example/se_manager_secure_identity/readme.md b/app/common/example/se_manager_secure_identity/readme.md index 6304e05ba7..f147a4a590 100644 --- a/app/common/example/se_manager_secure_identity/readme.md +++ b/app/common/example/se_manager_secure_identity/readme.md @@ -43,7 +43,7 @@ The following SE Manager APIs are used in this example: 1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 2. Upgrade the device’s SE firmware to the latest version (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 3. Open any terminal program and connect to the kit’s VCOM port. -4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). 5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). 6. Run the example and the console should display the process steps of this example. diff --git a/app/common/example/se_manager_signature/readme.md b/app/common/example/se_manager_signature/readme.md index 0fd8ec4232..aac58b5fef 100644 --- a/app/common/example/se_manager_signature/readme.md +++ b/app/common/example/se_manager_signature/readme.md @@ -97,7 +97,7 @@ The following SE Manager APIs are used in this example: 1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 2. Upgrade the device’s SE firmware to the latest version (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 3. Open any terminal program and connect to the kit’s VCOM port (if using `Device Console` in Simplicity Studio 5, `Line terminator:` must be set to `None`). -4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). 5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). 6. Run the example and follow the instructions shown on the console. diff --git a/app/common/example/se_manager_stream_cipher/readme.md b/app/common/example/se_manager_stream_cipher/readme.md index 7fd8d0a5d5..a30fb407d1 100644 --- a/app/common/example/se_manager_stream_cipher/readme.md +++ b/app/common/example/se_manager_stream_cipher/readme.md @@ -52,7 +52,7 @@ The following SE Manager APIs are used in this example: 1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 2. Upgrade the device’s SE firmware to the latest version (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 3. Open any terminal program and connect to the kit’s VCOM port. -4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). 5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). 6. Run the example and the console should display the process steps of this example. diff --git a/app/common/example/se_manager_symmetric_key_handling/readme.md b/app/common/example/se_manager_symmetric_key_handling/readme.md index 3b9f513a7b..accfdccd9e 100644 --- a/app/common/example/se_manager_symmetric_key_handling/readme.md +++ b/app/common/example/se_manager_symmetric_key_handling/readme.md @@ -61,7 +61,7 @@ The following SE Manager APIs are used in this example: 1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 2. Upgrade the device’s SE firmware to the latest version (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 3. Open any terminal program and connect to the kit’s VCOM port (if using `Device Console` in Simplicity Studio 5, `Line terminator:` must be set to `None`). -4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). 5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). 6. Run the example and follow the instructions shown on the console. diff --git a/app/common/example/se_manager_tamper/readme.md b/app/common/example/se_manager_tamper/readme.md index af56826e1c..759d3b140a 100644 --- a/app/common/example/se_manager_tamper/readme.md +++ b/app/common/example/se_manager_tamper/readme.md @@ -1,44 +1,29 @@ # SE Manager Tamper - This example uses the SE Manager API to demonstrate the tamper feature on the supported Series 2 Secure Vault High device. - -For demonstration purposes, a private command key is stored in the device’s memory to sign the access certificate for tamper disable. The device’s public command key in the SE OTP must match with the public key of this private command key to disable tamper signals. - +For demonstration purposes, a private command key is stored in the device's memory to sign the access certificate for tamper disable. The device's public command key in the SE OTP must match with the public key of this private command key to disable tamper responses. The default private command key (`cmd-unsafe-privkey.pem`) in PEM format can be found in the Windows folder below. - -*C:\SiliconLabs\SimplicityStudio\v5\developer\adapter\_packs\secmgr\scripts\offline* - +_C:\SiliconLabs\SimplicityStudio\v5\developer\adapter_packs\secmgr\scripts\offline_ The public key of `cmd-unsafe-privkey.pem` in text format is: - `X - B1BC6F6FA56640ED522B2EE0F5B3CF7E5D48F60BE8148F0DC08440F0A4E1DCA4` - `Y - 7C04119ED6A1BE31B7707E5F9D001A659A051003E95E1B936F05C37EA793AD63` +If the device does not have public command key in the SE OTP, the program will prompt the user to program the public key above to the device. -If the device does not have a public command key in the SE OTP, the program will prompt the user to program the public key above to the device. - - -The user can change the private command key (`private_command_key[]`) in `app_se_manager_tamper_disable.c` to match with the device’s public command key in the SE OTP for tamper disable. - +The user can change the private command key (`private_command_key[]`) in `app_se_manager_tamper_disable.c` to match with the device's public command key in the SE OTP for tamper disable. The example redirects standard I/O to the virtual serial port (VCOM) of the kit. By default, the serial port setting is 115200 bps and 8-N-1 configuration. - The example has been instrumented with code to count the number of clock cycles spent in different operations. The results are printed on the VCOM serial port console. This feature can be disabled by defining `SE_MANAGER_PRINT=0` (default is 1) in the IDE setting (`Preprocessor->Defined symbols`). - ## Tamper Responses - - - | Level | Responses | Description | | --- | --- | --- | | 0 | Ignore | No action is taken | @@ -47,11 +32,7 @@ The example has been instrumented with code to count the number of clock cycles | 4 | Reset | The device is reset | | 7 | Erase OTP | Erases the OTP configuration of the device (make the device and all wrapped secrets unrecoverable) | - -## Tamper Signals - - - +## Tamper Sources (EFR32xG21B Device) | Number | Name | Default level | User level in this example | | --- | --- | --- | --- | @@ -63,7 +44,7 @@ The example has been instrumented with code to count the number of clock cycles | 5 | SE Hardfault | 4 | 4 | | 6 | Reserved | — | — | | 7 | Software Assertion | 4 | 4 | -| 8 | Reserved | — | — | +| 8 | SE CodeAuth | 4 | 4 | | 9 | UserCodeAuth | 0 | 0 | | 10 | MailboxAuth | 0 | 1 | | 11 | DCIAuth | 0 | 0 | @@ -71,14 +52,14 @@ The example has been instrumented with code to count the number of clock cycles | 13 | Reserved | — | — | | 14 | Self-test | 4 | 4 | | 15 | TRNG Monitor | 0 | 1 | -| 16 | PRS0 | 0 | 1 (Push button PB0) | -| 17 | PRS1 | 0 | 1 (None) | -| 18 | PRS2 | 0 | 2 (Push button PB0) | -| 19 | PRS3 | 0 | 2 (None) | -| 20 | PRS4 | 0 | 4 (Push button PB1) | -| 21 | PRS5 | 0 | 4 (Software) | -| 22 | PRS6 | 0 | 7 (None) | -| 23 | PRS7 | 0 | 7 (None) | +| 16 | PRS0 | 0 | 1 (PRS source: Push button PB0) | +| 17 | PRS1 | 0 | 1 (PRS source: None) | +| 18 | PRS2 | 0 | 2 (PRS source: Push button PB0) | +| 19 | PRS3 | 0 | 2 (PRS source: None) | +| 20 | PRS4 | 0 | 4 (PRS source: Push button PB1) | +| 21 | PRS5 | 0 | 4 (PRS source: Software) | +| 22 | PRS6 | 0 | 7 (PRS source: None) | +| 23 | PRS7 | 0 | 7 (PRS source: None) | | 24 | DECOUPLE BOD | 4 | 4 | | 25 | TempSensor | 0 | 2 | | 26 | VGlitch Falling | 0 | 2 | @@ -88,32 +69,63 @@ The example has been instrumented with code to count the number of clock cycles | 30 | Digital glitch | 0 | 2 | | 31 | SE ICACHE | 4 | 4 | +## Tamper Sources (Other Series 2 Secure Vault High Devices) -The disable tamper command simply reverts all masked tamper sources (`TAMPER_DISABLE_MASK` in `app_se_manager_tamper_disable.h`) to the hardcoded configuration (default levels in table above). - - -The default value of `TAMPER_DISABLE_MASK` is `0x00fa0000` so PRS7, PRS6, PRS5, PRS4, PRS3, and PRS1 are restored to the default level 0 (Ignore) after running the disable tamper command. - +| Number | Name | Default level | User level in this example | +| --- | --- | --- | --- | +| 0 | Reserved | — | — | +| 1 | Filter Counter | 0 | 1 | +| 2 | SE Watchdog | 4 | 4 | +| 3 | Reserved | — | — | +| 4 | SE RAM ECC 2 | 4 | 4 | +| 5 | SE Hardfault | 4 | 4 | +| 6 | Reserved | — | — | +| 7 | Software Assertion | 4 | 4 | +| 8 | SE CodeAuth | 4 | 4 | +| 9 | UserCodeAuth | 0 | 0 | +| 10 | MailboxAuth | 0 | 1 | +| 11 | DCIAuth | 0 | 0 | +| 12 | OTP Read | 4 | 4 | +| 13 | Reserved | — | — | +| 14 | Self-test | 4 | 4 | +| 15 | TRNG Monitor | 0 | 1 | +| 16 | SecureLock | 4 | 4 | +| 17 | DGlitch | 0 | 2 | +| 18 | VGlitch | 0 | 2 | +| 19 | SE ICACHE | 4 | 4 | +| 20 | SE RAM ECC 1 | 0 | 1 | +| 21 | BOD | 4 | 4 | +| 22 | TempSensor | 0 | 2 | +| 23 | DPLL Fall | 0 | 2 | +| 24 | DPLL Rise | 0 | 2 | +| 25 | PRS0 | 0 | 1 (PRS source: None) | +| 26 | PRS1 | 0 | 1 (PRS source: Push button PB0) | +| 27 | PRS2 | 0 | 2 (PRS source: Push button PB0) | +| 28 | PRS3 | 0 | 2 (PRS source: None) | +| 29 | PRS4 | 0 | 4 (PRS source: Push button PB1) | +| 30 | PRS5 | 0 | 4 (PRS source: Software) | +| 31 | PRS6 | 0 | 7 (PRS source: None) | + +The disable tamper command reverts all masked tamper sources (`TAMPER_DISABLE_MASK` in `app_se_manager_tamper_disable.h`) to the hardcoded configuration (default levels in tables above). + +For EFR32xG21B devices, the default value of `TAMPER_DISABLE_MASK` is `0x00fa0000`. It restores PRS7, PRS6, PRS5, PRS4, PRS3, and PRS1 to the default level 0 (Ignore) after running the disable tamper command. + +For other Series 2 Secure Vault High devices, the default value of `TAMPER_DISABLE_MASK` is `0xf2000000`. It restores PRS6, PRS5, PRS4, PRS3, and PRS0 to the default level 0 (Ignore) after running the disable tamper command. ## Tamper Settings - - - | Setting | User value in this example | | --- | --- | | Filter - trigger threshold | 4 | | Filter - reset period | ~33 seconds | -| Flags | Digital Glitch Detector Always On: Disabled | +| Flag | Digital Glitch Detector Always On: Disabled | +| Flag (not available on EFR32xG21B devices) | Keep Tamper Alive During Sleep: Disabled | | Reset threshold | 5 | - ## SE Manager API - The following SE Manager APIs are used in this example: - * `sl_se_init` * `sl_se_deinit` * `sl_se_init_command_context` @@ -134,32 +146,25 @@ The following SE Manager APIs are used in this example: * `sl_se_disable_tamper` * `sl_se_roll_challenge` - ## Getting Started - -1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). -2. Upgrade the device’s SE firmware to the latest version (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). -3. Open any terminal program and connect to the kit’s VCOM port (if using `Device Console` in Simplicity Studio 5, `Line terminator:` must be set to `None`). -4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). -5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). +1. Upgrade the kit's firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in Simplicity Studio 5 Users Guide). +2. Upgrade the device's SE firmware to the latest version (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in Simplicity Studio 5 Users Guide). +3. Open any terminal program and connect to the kit's VCOM port (if using `Device Console` in Simplicity Studio 5, `Line terminator:` must be set to `None`). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). +5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in Simplicity Studio 5 Users Guide). 6. Run the example and follow the instructions shown on the console. - ## Additional Information - 1. The hard-coded private command key is an insecure method so the user should find a way to import the signed access certificate for tamper disable. -2. The device should disconnect from the debugger when running this example. -3. **Warning:** Loading the tamper configuration and a public command key into the SE are a **ONE-TIME-ONLY** process. Both of these assignment operations are irrevocable and persist for the life of the device. -4. The default optimization level is `Optimize for debugging (-Og)` on Simplicity IDE and `None` on IAR Embedded Workbench. - +2. This example does not enable the secure boot when provisioning the tamper configuration in `app_se_manager_tamper.c`. +3. The device should disconnect from the debugger when running this example. +4. **Warning:** Loading the tamper configuration and a public command key into the SE are a **ONE-TIME-ONLY** process. Both of these assignment operations are irrevocable and persist for the life of the device. +5. The default optimization level is `Optimize for debugging (-Og)` on Simplicity IDE and `None` on IAR Embedded Workbench. ## Resources - -[SE Manager API](https://docs.silabs.com/gecko-platform/latest/service/api/group-sl-se-manager) +[SE Manager API](https://docs.silabs.com/gecko-platform/latest/service/api/group-sl-se-manager)
[AN1247: Anti-Tamper Protection Configuration and Use](https://www.silabs.com/documents/public/application-notes/an1247-efr32-secure-vault-tamper.pdf) - - diff --git a/app/common/example/se_manager_user_data/readme.md b/app/common/example/se_manager_user_data/readme.md index ce7c5c51bf..138a180af6 100644 --- a/app/common/example/se_manager_user_data/readme.md +++ b/app/common/example/se_manager_user_data/readme.md @@ -30,7 +30,7 @@ The following SE Manager APIs are used in this example: 1. Upgrade the kit’s firmware to the latest version (see `Adapter Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 2. Upgrade the device’s SE firmware to the latest version (see `Secure Firmware` under [General Device Information](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-about-the-launcher/welcome-and-device-tabs#general-device-information) in the Simplicity Studio 5 User's Guide). 3. Open any terminal program and connect to the kit’s VCOM port. -4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide, check `Platform()` checkbox to browse the platform examples). +4. Create this platform example project in the Simplicity IDE (see [Examples](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-getting-started/start-a-project#examples) in the Simplicity Studio 5 User's Guide). 5. Build the example and download it to the kit (see [Simple Build](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/building#simple-build) and [Flash Programmer](https://docs.silabs.com/simplicity-studio-5-users-guide/latest/ss-5-users-guide-building-and-flashing/flashing#flash-programmer) in the Simplicity Studio 5 User's Guide). 6. Run the example and the console should display the process steps of this example. diff --git a/app/common/example/se_manager_user_data/se_manager_user_data.slcp b/app/common/example/se_manager_user_data/se_manager_user_data.slcp index 0542a8a4cb..1e1485ac5a 100644 --- a/app/common/example/se_manager_user_data/se_manager_user_data.slcp +++ b/app/common/example/se_manager_user_data/se_manager_user_data.slcp @@ -40,6 +40,8 @@ component: - id: printf - id: iostream_retarget_stdio - id: iostream_recommended_stream +requires: + - name: device_sdid_200 configuration: - name: SL_STATUS_STRING_ENABLE_BLUETOOTH value: 0 diff --git a/app/common/example/tensorflow_model_profiler/tensorflow_model_profiler.slcp b/app/common/example/tensorflow_model_profiler/tensorflow_model_profiler.slcp index 550f591dd3..3769b5e773 100644 --- a/app/common/example/tensorflow_model_profiler/tensorflow_model_profiler.slcp +++ b/app/common/example/tensorflow_model_profiler/tensorflow_model_profiler.slcp @@ -14,6 +14,8 @@ filter: value: ["32-bit MCU"] - name: "Project Difficulty" value: ["Advanced"] + - name: "Capability" + value: ["Machine Learning"] include: - path: . file_list: diff --git a/app/common/example/voice_control_light/config/recognize_commands_config.h b/app/common/example/voice_control_light/config/recognize_commands_config.h index bdd1a2700a..ac9fc00516 100644 --- a/app/common/example/voice_control_light/config/recognize_commands_config.h +++ b/app/common/example/voice_control_light/config/recognize_commands_config.h @@ -48,7 +48,7 @@ // Sets a time window to wait after a detected keyword before triggering // a new detection. // Default: 1000 -#define SUPPRESION_TIME_MS 750 +#define SUPPRESION_TIME_MS 1000 // <<< end of configuration section >>> diff --git a/app/common/example/voice_control_light/keyword_detection_model.png b/app/common/example/voice_control_light/keyword_detection_model.png deleted file mode 100644 index c056f61809..0000000000 --- a/app/common/example/voice_control_light/keyword_detection_model.png +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:c5ce813c86697af4108a31d2f83b8d7156cf79e45b2b898929636be638c64430 -size 71475 diff --git a/app/common/example/voice_control_light/readme.md b/app/common/example/voice_control_light/readme.md index 1f37b21a72..695d007ae5 100644 --- a/app/common/example/voice_control_light/readme.md +++ b/app/common/example/voice_control_light/readme.md @@ -1,5 +1,7 @@ # Voice Control Light -This application uses TensorFlow Lite for Microcontrollers to detect the spoken words "on" and "off" from audio data recorded on the microphone. The detected keywords are used to control an LED on the board. +This application uses TensorFlow Lite for Microcontrollers to detect the spoken +words "on" and "off" from audio data recorded on the microphone. The detected +keywords are used to control an LED on the board. Audio is sampled continuously from the microphone at a rate of 8kHz. The frequency components are then extracted by calculating the FFT on short segments @@ -11,16 +13,22 @@ toggle accordingly and the keyword detection result is printed on VCOM. The application is based on TensorFlow's example application, **[micro speech](https://github.com/tensorflow/tensorflow/tree/v2.3.1/tensorflow/lite/micro/examples/micro_speech)**. -## Model +## Model +The application uses one of two different available models +(```keyword_spotting_on_off.tflite``` or ```keyword_spotting_on_off_v2.tflite```) +as the default model, depending on whether the application is generated for a +development board featuring an MVP hardware accelerator or not. When an MVP +hardware accelerator is featured on the board, inference will run at a faster +speed such that a larger model can be chosen, yielding more accurate keyword +detections. + The neural network model has been trained to identify the two keywords "on" and "off" from preprocessed audio data. When neither words are recognized, the model -will classify the input as either "unknown" or "background". - -The model takes an array of filterbanks as input and outputs a vector with each -value corresponding to the probability that the input belongs to each of the -categories ("on", "off", "unknown", "background"). The architecture of the model -is visualized below using [Netron](https://github.com/lutzroeder/netron). - -![Voice Control Light Model Architecture](keyword_detection_model.png "Voice Control Light Model Architecture") +will classify the input as either "unknown" or "background". The model takes an +array of filterbanks as input and outputs a vector with each value corresponding +to the probability that the input belongs to each of the +categories. -The source for the model can be found here: https://siliconlabs.github.io/mltk/docs/python_api/models.html#keyword-spotting-on-off +Details about the model architectures and scripts for generating the models can +be found in the [Silicon Labs machine learning applications](https://github.com/SiliconLabs/machine_learning_applications/tree/main/) repository, under +```voice/keyword_spotting/model```. \ No newline at end of file diff --git a/app/common/example/voice_control_light/recognize_commands.cc b/app/common/example/voice_control_light/recognize_commands.cc index 8458ad94b1..0b15370a61 100644 --- a/app/common/example/voice_control_light/recognize_commands.cc +++ b/app/common/example/voice_control_light/recognize_commands.cc @@ -24,7 +24,7 @@ // 1 - off // 2 - unknown // 3 - background -const char* kCategoryLabels[kCategoryCount] = { +const char* kCategoryLabels[kMaxCategoryCount] = { "on", "off", "unknown", @@ -51,89 +51,25 @@ TfLiteStatus RecognizeCommands::ProcessLatestResults( const TfLiteTensor* latest_results, const int32_t current_time_ms, uint8_t* found_command_index, uint8_t* score, bool* is_new_command) { - if ((latest_results->dims->size != 2) - || (latest_results->dims->data[0] != 1) - || (latest_results->dims->data[1] != kCategoryCount)) { - TF_LITE_REPORT_ERROR( - error_reporter_, - "The results for recognition should contain %d elements, but there are " - "%d in an %d-dimensional shape", - kCategoryCount, latest_results->dims->data[1], - latest_results->dims->size); - return kTfLiteError; - } - - if (latest_results->type != kTfLiteInt8) { - TF_LITE_REPORT_ERROR( - error_reporter_, - "The results for recognition should be int8_t elements, but are %d", - latest_results->type); - return kTfLiteError; - } - if ((!previous_results_.empty()) - && (current_time_ms < previous_results_.front().time_)) { - TF_LITE_REPORT_ERROR( - error_reporter_, - "Results must be fed in increasing time order, but received a " - "timestamp of %d that was earlier than the previous one of %d", - current_time_ms, previous_results_.front().time_); - return kTfLiteError; - } - - // Add the latest results to the head of the queue. - previous_results_.push_back({current_time_ms, latest_results->data.int8}); - - // Prune any earlier results that are too old for the averaging window. - const int64_t time_limit = current_time_ms - average_window_duration_ms_; - while ((!previous_results_.empty()) - && previous_results_.front().time_ < time_limit) { - previous_results_.pop_front(); - } +uint8_t category_count = latest_results->dims->data[1]; +int8_t current_top_index = 0; +int32_t current_top_score = 0; +uint8_t converted_scores[kMaxCategoryCount]; - // If there are too few results, assume the result will be unreliable and - // bail. - const int32_t how_many_results = previous_results_.size(); - if ((how_many_results < minimum_count_)) { - *found_command_index = previous_top_label_index_; - *score = 0; - *is_new_command = false; - /* Don't report non-error - TF_LITE_REPORT_ERROR( - error_reporter_, - "The smoothing window contains less than %d inference result(s), a " - "reliable keyword detection can not be made.", - minimum_count_); - */ - return kTfLiteOk; - } - - // Calculate the average score across all the results in the window. - int32_t average_scores[kCategoryCount]; - for (int offset = 0; offset < previous_results_.size(); ++offset) { - // Iterates the amount of times to achieve average_window_duration - PreviousResultsQueue::Result previous_result = - previous_results_.from_front(offset); - const int8_t* scores = previous_result.scores; - for (int i = 0; i < kCategoryCount; ++i) { - if (offset == 0) { - average_scores[i] = scores[i] + 128; - } else { - average_scores[i] += scores[i] + 128; - } +// Convert the model output to uint8 +if (latest_results->type == kTfLiteInt8) { + for(int i = 0; i < category_count; ++i) { + converted_scores[i] = (uint8_t)(latest_results->data.int8[i] + 128); } + } else { + TF_LITE_REPORT_ERROR(error_reporter_, "Unsupported output tensor data type, must be int8 or float32"); + return kTfLiteError; } - for (int i = 0; i < kCategoryCount; ++i) { - average_scores[i] /= how_many_results; - } - - // Find the current highest scoring category. - int8_t current_top_index = 0; - int32_t current_top_score = 0; - for (int i = 0; i < kCategoryCount; ++i) { - if (average_scores[i] > current_top_score) { - current_top_score = average_scores[i]; + for (int i = 0; i < category_count; i++) { + if (converted_scores[i] > current_top_score) { + current_top_score = converted_scores[i]; current_top_index = i; } } diff --git a/app/common/example/voice_control_light/recognize_commands.h b/app/common/example/voice_control_light/recognize_commands.h index c80f1e1c15..60cfe4e4a9 100644 --- a/app/common/example/voice_control_light/recognize_commands.h +++ b/app/common/example/voice_control_light/recognize_commands.h @@ -23,8 +23,8 @@ #include "tensorflow/lite/c/common.h" #include "tensorflow/lite/micro/micro_error_reporter.h" -constexpr int kCategoryCount = 4; -extern const char* kCategoryLabels[kCategoryCount]; +constexpr int kMaxCategoryCount = 4; +extern const char* kCategoryLabels[kMaxCategoryCount]; // Partial implementation of std::dequeue, just providing the functionality // that's needed to keep a record of previous neural network results over a @@ -44,12 +44,12 @@ class PreviousResultsQueue { Result() : time_(0), scores() { } Result(int32_t time, int8_t * input_scores) : time_(time) { - for (int i = 0; i < kCategoryCount; ++i) { + for (int i = 0; i < kMaxCategoryCount; ++i) { scores[i] = input_scores[i]; } } int32_t time_; - int8_t scores[kCategoryCount]; + int8_t scores[kMaxCategoryCount]; }; int size() diff --git a/app/common/example/audio_classifier/config/tflite/audio_classifier.tflite b/app/common/example/voice_control_light/tflite_models/tflite/keyword_spotting_on_off.tflite similarity index 100% rename from app/common/example/audio_classifier/config/tflite/audio_classifier.tflite rename to app/common/example/voice_control_light/tflite_models/tflite/keyword_spotting_on_off.tflite diff --git a/app/common/example/voice_control_light/tflite_models/tflite/keyword_spotting_on_off_v2.tflite b/app/common/example/voice_control_light/tflite_models/tflite/keyword_spotting_on_off_v2.tflite new file mode 100644 index 0000000000..8f926c576b Binary files /dev/null and b/app/common/example/voice_control_light/tflite_models/tflite/keyword_spotting_on_off_v2.tflite differ diff --git a/app/common/example/voice_control_light/voice_control_light.cc b/app/common/example/voice_control_light/voice_control_light.cc index 356360c986..fabbde4fd3 100644 --- a/app/common/example/voice_control_light/voice_control_light.cc +++ b/app/common/example/voice_control_light/voice_control_light.cc @@ -104,7 +104,7 @@ static sl_status_t process_output(){ if (process_status != kTfLiteOk) { return SL_STATUS_FAIL; - } + } if (is_new_command) { // Print heard command diff --git a/app/common/example/voice_control_light/voice_control_light.slcp b/app/common/example/voice_control_light/voice_control_light.slcp index bf7afee65b..39d45a95f1 100644 --- a/app/common/example/voice_control_light/voice_control_light.slcp +++ b/app/common/example/voice_control_light/voice_control_light.slcp @@ -32,7 +32,7 @@ component: - id: device_init - id: tensorflow_lite_micro - id: ml_audio_feature_generation - - id: printf + - id: printf - id: iostream_recommended_stream - id: iostream_retarget_stdio - id: simple_led @@ -41,11 +41,16 @@ component: - id: micriumos_kernel - id: power_manager - id: sleeptimer -config_file: +config_file: - path: config/recognize_commands_config.h - - path: "config/tflite/keyword_spotting_on_off.tflite" + - path: "tflite_models/tflite/keyword_spotting_on_off.tflite" file_id: flatbuffer_file_id directory: "tflite" + unless: [tensorflow_lite_micro_accelerated_kernels] + - path: "tflite_models/tflite/keyword_spotting_on_off_v2.tflite" + file_id: flatbuffer_file_id + directory: "tflite" + condition: [tensorflow_lite_micro_accelerated_kernels] define: - name: DEBUG_EFM - name: TF_LITE_STATIC_MEMORY @@ -62,10 +67,8 @@ configuration: condition: [iostream_uart] - name: SL_ML_AUDIO_FEATURE_GENERATION_AUDIO_BUFFER_SIZE value: "4096" - - name: SL_ML_AUDIO_FEATURE_GENERATION_AUDIO_GAIN - value: "2" - - name: SL_TFLITE_MICRO_ARENA_SIZE - value: "7000" + - name: SL_TFLITE_MICRO_ARENA_SIZE + value: "50000" - name: SL_HEAP_SIZE value: "0x2000" toolchain_settings: @@ -73,8 +76,6 @@ toolchain_settings: value: "-Wno-unused-parameter" - option: gcc_compiler_option value: "-Wno-missing-field-initializers" -other_file: - - path: keyword_detection_model.png readme: - path: readme.md ui_hints: diff --git a/app/common/platform_production_demos.xml b/app/common/platform_production_demos.xml index 768c59a316..e10919535e 100644 --- a/app/common/platform_production_demos.xml +++ b/app/common/platform_production_demos.xml @@ -1,1455 +1,1466 @@ - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + + + + This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + + + + This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). - - - - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + - - - - - - - This example project demonstrates use of the Memory Liquid Crystal Display (LCD) module in a baremetal application, using Silicon Labs Graphics Library (glib). + + + + + + + diff --git a/app/common/platform_production_templates.xml b/app/common/platform_production_templates.xml index 824ddbd701..171df6f5a5 100644 --- a/app/common/platform_production_templates.xml +++ b/app/common/platform_production_templates.xml @@ -3,11 +3,12 @@ + - + @@ -17,11 +18,12 @@ + - - - + + + @@ -31,11 +33,12 @@ + - - - + + + @@ -45,11 +48,12 @@ + - - - + + + @@ -59,11 +63,12 @@ + - - - + + + @@ -73,11 +78,12 @@ + - + - + @@ -87,11 +93,12 @@ + - + - + @@ -101,11 +108,12 @@ + - + - + @@ -115,11 +123,12 @@ + - + @@ -129,11 +138,12 @@ + - - - + + + @@ -143,51 +153,57 @@ + - - - + + + + + - - - + + + - + + - - - + + + + + - + @@ -197,11 +213,12 @@ + - - - + + + @@ -211,11 +228,12 @@ + - + - + @@ -225,11 +243,12 @@ + - + - + @@ -239,11 +258,12 @@ + - + - + @@ -253,11 +273,12 @@ + - + - + @@ -267,11 +288,12 @@ + - - - + + + @@ -281,11 +303,12 @@ + - - - + + + @@ -295,11 +318,12 @@ + - - - + + + @@ -309,11 +333,12 @@ + - - - + + + @@ -323,11 +348,12 @@ + - - - + + + @@ -337,11 +363,12 @@ + - - - + + + @@ -351,11 +378,12 @@ + - - - + + + @@ -365,11 +393,12 @@ + - - - + + + @@ -379,11 +408,12 @@ + - - - + + + @@ -393,11 +423,12 @@ + - - - + + + @@ -407,11 +438,12 @@ + - + - + @@ -421,11 +453,12 @@ + - - - + + + @@ -435,11 +468,12 @@ + - - - + + + @@ -449,11 +483,12 @@ + - - - + + + @@ -463,11 +498,12 @@ + - - - + + + @@ -477,11 +513,12 @@ + - - - + + + @@ -491,11 +528,12 @@ + - - - + + + @@ -505,11 +543,12 @@ + - - - + + + @@ -519,11 +558,12 @@ + - - - + + + @@ -533,11 +573,12 @@ + - - - + + + @@ -547,11 +588,12 @@ + - - - + + + @@ -561,11 +603,12 @@ + - - - + + + @@ -575,11 +618,12 @@ + - - - + + + @@ -589,11 +633,12 @@ + - - - + + + @@ -603,11 +648,12 @@ + - - - + + + @@ -617,11 +663,12 @@ + - - - + + + @@ -631,11 +678,12 @@ + - + - + @@ -645,11 +693,12 @@ + - + - + @@ -659,11 +708,12 @@ + - + - + @@ -673,11 +723,12 @@ + - + - + @@ -687,11 +738,12 @@ + - + - + @@ -701,11 +753,12 @@ + - + - + @@ -715,11 +768,12 @@ + - + @@ -729,11 +783,12 @@ + - + - + @@ -743,11 +798,12 @@ + - + - + @@ -757,11 +813,12 @@ + - + - + @@ -771,11 +828,12 @@ + - + - + @@ -785,11 +843,12 @@ + - + - + @@ -799,11 +858,12 @@ + - + - + @@ -813,11 +873,12 @@ + - + - + @@ -827,11 +888,12 @@ + - + - + @@ -841,11 +903,12 @@ + - + - + @@ -855,11 +918,12 @@ + - - - + + + @@ -869,11 +933,12 @@ + - - - + + + @@ -883,11 +948,12 @@ + - - - + + + @@ -897,11 +963,12 @@ + - - - + + + @@ -911,11 +978,12 @@ + - - - + + + @@ -925,11 +993,12 @@ + - + - + @@ -939,11 +1008,12 @@ + - + - + @@ -953,11 +1023,12 @@ + - + - + @@ -967,11 +1038,12 @@ + - + - + @@ -981,11 +1053,12 @@ + - - - + + + @@ -995,11 +1068,12 @@ + - - - + + + @@ -1009,11 +1083,12 @@ + - - - + + + @@ -1023,11 +1098,12 @@ + - - - + + + @@ -1037,11 +1113,12 @@ + - - - + + + @@ -1051,25 +1128,27 @@ + - + - + - + + - + - + @@ -1079,11 +1158,12 @@ + - + @@ -1093,11 +1173,12 @@ + - + @@ -1107,11 +1188,12 @@ + - + @@ -1121,11 +1203,12 @@ + - + @@ -1135,11 +1218,12 @@ + - + @@ -1149,11 +1233,12 @@ + - + @@ -1163,11 +1248,12 @@ + - + @@ -1177,11 +1263,12 @@ + - + @@ -1191,11 +1278,12 @@ + - + @@ -1205,11 +1293,12 @@ + - + @@ -1219,11 +1308,12 @@ + - + @@ -1233,11 +1323,12 @@ + - + diff --git a/app/flex/component/connect/sl_connect_sdk_ota_broadcast_bootloader_test/sl_connect_sdk_ota_broadcast_bootloader_test.c b/app/flex/component/connect/sl_connect_sdk_ota_broadcast_bootloader_test/sl_connect_sdk_ota_broadcast_bootloader_test.c index a99dc2be3c..ed029fc613 100644 --- a/app/flex/component/connect/sl_connect_sdk_ota_broadcast_bootloader_test/sl_connect_sdk_ota_broadcast_bootloader_test.c +++ b/app/flex/component/connect/sl_connect_sdk_ota_broadcast_bootloader_test/sl_connect_sdk_ota_broadcast_bootloader_test.c @@ -179,6 +179,8 @@ bool emberAfPluginOtaBootloaderClientNewIncomingImageCallback(EmberNodeId server EmberNodeId *alternateServerId, uint8_t imageTag) { + (void)alternateServerId; + (void)serverId; // The client shall accept images with matching tag bool accept = (imageTag == ota_bootloader_test_image_tag); @@ -200,6 +202,7 @@ void emberAfPluginOtaBootloaderClientIncomingImageSegmentCallback(EmberNodeId se uint8_t imageTag, uint8_t *imageSegment) { + (void)serverId; app_log_info("(client): incoming segment, start: %d, end: %d, tag: 0x%x\n", startIndex, endIndex, imageTag); @@ -253,6 +256,7 @@ bool emberAfPluginOtaBootloaderClientIncomingRequestBootloadCallback(EmberNodeId uint32_t bootloadDelayMs, uint8_t *applicationStatus) { + (void)serverId; // The client shall bootload an image with matching tag. if (applicationStatus == NULL) { diff --git a/app/flex/component/connect/sl_connect_sdk_ota_unicast_bootloader_test/sl_connect_sdk_ota_unicast_bootloader_test.c b/app/flex/component/connect/sl_connect_sdk_ota_unicast_bootloader_test/sl_connect_sdk_ota_unicast_bootloader_test.c index 255ddb66ed..cfccea4a0b 100644 --- a/app/flex/component/connect/sl_connect_sdk_ota_unicast_bootloader_test/sl_connect_sdk_ota_unicast_bootloader_test.c +++ b/app/flex/component/connect/sl_connect_sdk_ota_unicast_bootloader_test/sl_connect_sdk_ota_unicast_bootloader_test.c @@ -57,10 +57,12 @@ EmberEventControl emAfPluginOtaUnicastBootloaderTestEventControl; // ----------------------------------------------------------------------------- /// Node ID of the target static EmberNodeId target; +#if defined(SL_CATALOG_CONNECT_OTA_UNICAST_BOOTLOADER_CLIENT_PRESENT) /// Enable resuming an image after the timeout period. static bool ota_resume_enable = true; /// the image index to start/resume the download static uint32_t unicast_download_start_index = 0; +#endif // ----------------------------------------------------------------------------- // Public Function Definitions diff --git a/app/flex/documentation/release-highlights.txt b/app/flex/documentation/release-highlights.txt index eae31ee6e7..c0ecdf9d72 100644 --- a/app/flex/documentation/release-highlights.txt +++ b/app/flex/documentation/release-highlights.txt @@ -1,7 +1,3 @@ -Flex SDK 3.4.0.0 -- EFR32xG24 GA with Antenna Diversity support -- FGM230S proprietary module GA -- Secure Vault integration to Connect stack -- BGM220 Range Test + DMP pre-compiled demo with EFR Connect Mobile Application - +Flex SDK 3.4.1.0 +- RAIL Library: Targeted quality improvements and bug fixes diff --git a/app/flex/documentation/slFlex_docContent.xml b/app/flex/documentation/slFlex_docContent.xml index 541b3ca46a..e5f02373d1 100644 --- a/app/flex/documentation/slFlex_docContent.xml +++ b/app/flex/documentation/slFlex_docContent.xml @@ -1,339 +1,339 @@ - - + + + Includes detailed information on using the Silicon Labs Gecko Bootloader with Connect. It supplements the general Gecko Bootloader implementation information provided in UG489: Silicon Labs Gecko Bootloader User's Guide. - Includes detailed information on using the Silicon Labs Gecko Bootloader with Connect. It supplements the general Gecko Bootloader implementation information provided in UG489: Silicon Labs Gecko Bootloader User's Guide. - + + Describes using the Flex SDK for Wireless M-Bus development on EFR32 Wireless Geckos. Includes features and limitations as well as examples. - Describes using the Flex SDK for Wireless M-Bus development on EFR32 Wireless Geckos. Includes features and limitations as well as examples. - + + Outlines how to account for the variation in output characteristics across custom boards and applications for the Silicon Labs EFR32 family of chips. - Outlines how to account for the variation in output characteristics across custom boards and applications for the Silicon Labs EFR32 family of chips. - + + Explains how NVM3 can be used as non-volatile data storage in various protocol implementations. - Explains how NVM3 can be used as non-volatile data storage in various protocol implementations. - + + Describes tokens and shows how to use them for non-volatile data storage in EmberZNet PRO and Silicon Labs Flex applications. - Describes tokens and shows how to use them for non-volatile data storage in EmberZNet PRO and Silicon Labs Flex applications. - + + Describes how to lock and unlock the debug access of EFR32 Gecko Series 2 devices. Many aspects of the debug access, including the secure debug unlock are described. The Debug Challenge Interface (DCI) and Secure Engine (SE) Mailbox Interface for locking and unlocking debug access are also included. - Describes how to lock and unlock the debug access of EFR32 Gecko Series 2 devices. Many aspects of the debug access, including the secure debug unlock are described. The Debug Challenge Interface (DCI) and Secure Engine (SE) Mailbox Interface for locking and unlocking debug access are also included. - + + Contains detailed information on configuring and using the Secure Boot with hardware Root of Trust and Secure Loader on Series 2 devices, including how to provision the signing key. This is a companion document to UG489: Silicon Labs Gecko Bootloader User's Guide. - Contains detailed information on configuring and using the Secure Boot with hardware Root of Trust and Secure Loader on Series 2 devices, including how to provision the signing key. This is a companion document to UG489: Silicon Labs Gecko Bootloader User's Guide. - + + Details on programming, provisioning, and configuring Series 2 devices in production environments. Covers Secure Engine Subsystem of Series 2 devices, which runs easily upgradeable Secure Engine (SE) or Virtual Secure Engine (VSE) firmware. - Details on programming, provisioning, and configuring Series 2 devices in production environments. Covers Secure Engine Subsystem of Series 2 devices, which runs easily upgradeable Secure Engine (SE) or Virtual Secure Engine (VSE) firmware. - + + Describes the distinguishing features of different EFR32 families that are most relevant to porting proprietary wireless applications between them. Provides insight that is also helpful when selecting an initial target platform for proprietary wireless solutions. - Describes the distinguishing features of different EFR32 families that are most relevant to porting proprietary wireless applications between them. Provides insight that is also helpful when selecting an initial target platform for proprietary wireless solutions. - + + How to program, provision, and configure the anti-tamper module on EFR32 Series 2 devices with Secure Vault. - How to program, provision, and configure the anti-tamper module on EFR32 Series 2 devices with Secure Vault. - + + Illustrates reducing power consumption in a Connect v3.x application using the sensor example. - Illustrates reducing power consumption in a Connect v3.x application using the sensor example. - + + Describes the radio configurator GUI for RAIL framework applications in Simplicity Studio 5. With it, you can create standard or custom radio configurations on which to run your RAIL-based applications. The role of each GUI item is explained. - Describes the radio configurator GUI for RAIL framework applications in Simplicity Studio 5. With it, you can create standard or custom radio configurations on which to run your RAIL-based applications. The role of each GUI item is explained. - + + How to authenticate an EFR32 Series 2 device with Secure Vault, using secure device certificates and signatures. - How to authenticate an EFR32 Series 2 device with Secure Vault, using secure device certificates and signatures. - + + How to securely "wrap" keys in EFR32 Series 2 devices with Secure Vault, so they can be stored in non-volatile storage. - How to securely "wrap" keys in EFR32 Series 2 devices with Secure Vault, so they can be stored in non-volatile storage. - + + Describes how to provision and configure Series 2 devices through the DCI and SWD. - Describes how to provision and configure Series 2 devices through the DCI and SWD. - + + Describes how to integrate crypto functionality into applications using PSA Crypto compared to Mbed TLS. - Describes how to integrate crypto functionality into applications using PSA Crypto compared to Mbed TLS. - + + Gecko Bootloader v2.x, introduced in GSDK 4.0, contains a number of changes compared to Gecko Bootloader v1.x. This document describes the differences between the versions, including how to configure the new Gecko Bootloader in Simplicity Studio 5. - Gecko Bootloader v2.x, introduced in GSDK 4.0, contains a number of changes compared to Gecko Bootloader v1.x. This document describes the differences between the versions, including how to configure the new Gecko Bootloader in Simplicity Studio 5. - + + Describes how to initialize a piece of custom hardware (a 'device') based on the EFR32MG and EFR32FG families so that it interfaces correctly with a network stack. The same procedures can be used to restore devices whose settings have been corrupted or erased. - Describes how to initialize a piece of custom hardware (a 'device') based on the EFR32MG and EFR32FG families so that it interfaces correctly with a network stack. The same procedures can be used to restore devices whose settings have been corrupted or erased. - + + Describes using RAILTest to evaluate radio functionality, as well as peripherals, deep sleep states, etc. With it you can fully evaluate the receiving and transmitting performance and test RF functionality of development kit hardware or custom hardware. - Describes using RAILTest to evaluate radio functionality, as well as peripherals, deep sleep states, etc. With it you can fully evaluate the receiving and transmitting performance and test RF functionality of development kit hardware or custom hardware. - + + Provides an overview and hyperlinks to all packaged documentation. - Provides an overview and hyperlinks to all packaged documentation. - + + Provides basic information on configuring, building, and installing applications using Silicon Labs Connect and RAIL, the two development paths in the Silicon Labs Proprietary Flex SDK v3.x. - Provides basic information on configuring, building, and installing applications using Silicon Labs Connect and RAIL, the two development paths in the Silicon Labs Proprietary Flex SDK v3.x. - + + Contains a comprehensive list of APIs used to interface to the Silicon Labs Connect stack. - Contains a comprehensive list of APIs used to interface to the Silicon Labs Connect stack. - + + Contains a comprehensive list of APIs used to interface to the Silicon Labs RAIL library. - Contains a comprehensive list of APIs used to interface to the Silicon Labs RAIL library. - + + Lists compatibility requirements and sources for all software components in the development environment. Discusses the latest changes to the SiliconLabs Flex SDK, including added/deleted/deprecated features/API. Reviews fixed and known issues. - Lists compatibility requirements and sources for all software components in the development environment. Discusses the latest changes to the SiliconLabs Flex SDK, including added/deleted/deprecated features/API. Reviews fixed and known issues. - + + A detailed overview of the changes, additions, and fixes in the Gecko Platform components. The Gecko Platform includes EMLIB, EMDRV, RAIL Library, NVM3, and the component-based infrastructure. - A detailed overview of the changes, additions, and fixes in the Gecko Platform components. The Gecko Platform includes EMLIB, EMDRV, RAIL Library, NVM3, and the component-based infrastructure. - + + Introduces some fundamental concepts of wireless networking. These concepts are referred to in other Fundamentals documents. If you are new to wireless networking, you should read this document first. - Introduces some fundamental concepts of wireless networking. These concepts are referred to in other Fundamentals documents. If you are new to wireless networking, you should read this document first. - + + Introduces the security concepts that must be considered when implementing an Internet of Things (IoT) system. Using the ioXt Alliance's eight security principles as a structure, it clearly delineates the solutions Silicon Labs provides to support endpoint security and what you must do outside of the Silicon Labs framework. - Introduces the security concepts that must be considered when implementing an Internet of Things (IoT) system. Using the ioXt Alliance's eight security principles as a structure, it clearly delineates the solutions Silicon Labs provides to support endpoint security and what you must do outside of the Silicon Labs framework. - + + Introduces bootloading for Silicon Labs networking devices. Discusses the Gecko Bootloader as well as legacy Ember and Bluetooth bootloaders, and describes the file formats used by each. - Introduces bootloading for Silicon Labs networking devices. Discusses the Gecko Bootloader as well as legacy Ember and Bluetooth bootloaders, and describes the file formats used by each. - + + Introduces non-volatile data storage using flash and the three different storage implementations offered for Silicon Labs microcontrollers and SoCs: Simulated EEPROM, PS Store, and NVM3. - Introduces non-volatile data storage using flash and the three different storage implementations offered for Silicon Labs microcontrollers and SoCs: Simulated EEPROM, PS Store, and NVM3. - + + Describes the features and functions of the Silicon Labs Connect stack, including its device types, network topologies, and its 'building block' development methodology using plugins. - Describes the features and functions of the Silicon Labs Connect stack, including its device types, network topologies, and its 'building block' development methodology using plugins. - + + Describes the features and functions of Silicon Labs RAIL (Radio Abstraction Interface Layer). RAIL provides an intuitive, easily-customizable radio interface layer that is designed to support proprietary or standards-based wireless protocols. - Describes the features and functions of Silicon Labs RAIL (Radio Abstraction Interface Layer). RAIL provides an intuitive, easily-customizable radio interface layer that is designed to support proprietary or standards-based wireless protocols. - + + Describes the four multiprotocol modes, discusses considerations when selecting protocols for multiprotocol implementations, and reviews the Radio Scheduler, a required component of a dynamic multiprotocol solution. - Describes the four multiprotocol modes, discusses considerations when selecting protocols for multiprotocol implementations, and reviews the Radio Scheduler, a required component of a dynamic multiprotocol solution. - + + Describes how and when to use Simplicity Commander's Command-Line Interface. - Describes how and when to use Simplicity Commander's Command-Line Interface. - + + Describes how to implement a dynamic multiprotocol solution. - Describes how to implement a dynamic multiprotocol solution. - + + Describes the functionality available in the RAILtest application. - Describes the functionality available in the RAILtest application. - + + Introduces the Connect User's Guide for the Flex SDK v3.x. - Introduces the Connect User's Guide for the Flex SDK v3.x. - + + Introduces the IEEE 802.15.4 standard on which Connect v3.x is based. - Introduces the IEEE 802.15.4 standard on which Connect v3.x is based. - + + Describes the architecture of the Silicon Labs Connect stack v3.x an how it implements IEEE 802.15.4. - Describes the architecture of the Silicon Labs Connect stack v3.x an how it implements IEEE 802.15.4. - + + Describes how to use components, callbacks, and events on top of the Gecko Platform application framework to configure features and application behavior. - Describes how to use components, callbacks, and events on top of the Gecko Platform application framework to configure features and application behavior. - + + Describes the process to implement a Connect-based application on top of one of the supported Real Time Operating Systems (RTOS). - Describes the process to implement a Connect-based application on top of one of the supported Real Time Operating Systems (RTOS). - + + Explains standalone (serial) and application (OTA) bootloader options available for use within Connect v3.x -based applications - Explains standalone (serial) and application (OTA) bootloader options available for use within Connect v3.x -based applications - + + Describes the features available in Connect v3.x to reduce power consumption. Using those features is described in AN1252: Building Low Power Networks with the Silicon Labs Connect Stack v3.x. - Describes the features available in Connect v3.x to reduce power consumption. Using those features is described in AN1252: Building Low Power Networks with the Silicon Labs Connect Stack v3.x. - + + Introduces the long-range radio profile, escribes its development, and examines underlying details that enable it to realize extended range. Instructions for using example applications are included. - Introduces the long-range radio profile, escribes its development, and examines underlying details that enable it to realize extended range. Instructions for using example applications are included. - + + Provides an easy way to evaluate the link budget of the Wireless Gecko EFR32 devices using Silicon Labs RAIL (RAIL) by performing a range test between two nodes using Range Test, a standalone test application. The range test demo implements Packet Error Rate (PER) measurement. - Provides an easy way to evaluate the link budget of the Wireless Gecko EFR32 devices using Silicon Labs RAIL (RAIL) by performing a range test between two nodes using Range Test, a standalone test application. The range test demo implements Packet Error Rate (PER) measurement. - + + Describes the high-level implementation of the Silicon Labs Gecko Bootloader for EFR32 SoCs and NCPs, and provides information on how to get started using the Gecko Bootloader with Silicon Labs wireless protocol stacks in GSDK 4.0 and higher. - Describes the high-level implementation of the Silicon Labs Gecko Bootloader for EFR32 SoCs and NCPs, and provides information on how to get started using the Gecko Bootloader with Silicon Labs wireless protocol stacks in GSDK 4.0 and higher. diff --git a/app/flex/esf.properties b/app/flex/esf.properties index 3e1136bd7d..635483dc02 100644 --- a/app/flex/esf.properties +++ b/app/flex/esf.properties @@ -3,8 +3,8 @@ id=com.silabs.stack.flex label=Flex SDK description=Flex Software Development Kit -version=3.4.0.0 -prop.subLabel=Flex\\ 3.4.0.0 +version=3.4.1.0 +prop.subLabel=Flex\\ 3.4.1.0 # General properties are prepended with "prop." prop.file.templatesFile=flex_production_templates.xml flex_demos_only_templates.xml flex_internal_templates.xml diff --git a/app/flex/example/connect/connect_soc_direct_mode_device/hw_filter_tags.yaml b/app/flex/example/connect/connect_soc_direct_mode_device/hw_filter_tags.yaml index 086219161d..8334bd52cf 100644 --- a/app/flex/example/connect/connect_soc_direct_mode_device/hw_filter_tags.yaml +++ b/app/flex/example/connect/connect_soc_direct_mode_device/hw_filter_tags.yaml @@ -4,7 +4,7 @@ tag: - hardware: device: memory: - flash: 208 + flash: 207 ram: 25 board: rf_bands: diff --git a/app/flex/example/connect/connect_soc_ecdh_key_exchange/hw_filter_tags.yaml b/app/flex/example/connect/connect_soc_ecdh_key_exchange/hw_filter_tags.yaml index 738983fa71..15c32af76c 100644 --- a/app/flex/example/connect/connect_soc_ecdh_key_exchange/hw_filter_tags.yaml +++ b/app/flex/example/connect/connect_soc_ecdh_key_exchange/hw_filter_tags.yaml @@ -4,8 +4,8 @@ tag: - hardware: device: memory: - flash: 226 - ram: 24 + flash: 225 + ram: 29 board: rf_bands: - any diff --git a/app/flex/example/connect/connect_soc_mac_mode_device/hw_filter_tags.yaml b/app/flex/example/connect/connect_soc_mac_mode_device/hw_filter_tags.yaml index f8bfe9d4d5..bf189ffac2 100644 --- a/app/flex/example/connect/connect_soc_mac_mode_device/hw_filter_tags.yaml +++ b/app/flex/example/connect/connect_soc_mac_mode_device/hw_filter_tags.yaml @@ -4,7 +4,7 @@ tag: - hardware: device: memory: - flash: 213 + flash: 212 ram: 25 board: rf_bands: diff --git a/app/flex/example/connect/light_switch/connect_soc_switch/app_process.c b/app/flex/example/connect/light_switch/connect_soc_switch/app_process.c index 624ef767b1..28acc829c7 100644 --- a/app/flex/example/connect/light_switch/connect_soc_switch/app_process.c +++ b/app/flex/example/connect/light_switch/connect_soc_switch/app_process.c @@ -106,7 +106,7 @@ psa_key_id_t security_key_id = 0; // Static Variables // ----------------------------------------------------------------------------- /// Destination of the currently processed sink node -static EmberNodeId light_node_id = EMBER_NULL_NODE_ID; +static EmberNodeId light_node_id = EMBER_COORDINATOR_ADDRESS; /// Store the Connect's status static EmberStatus stack_status; @@ -381,6 +381,6 @@ static void toggle_light() tx_options); if (status == EMBER_SUCCESS) { - app_log_info("TX: Data to 0x%04X: \n", light_node_id); + app_log_info("TX: Data to 0x%04X:\n", light_node_id); } } diff --git a/app/flex/example/connect/light_switch/connect_soc_switch/hw_filter_tags.yaml b/app/flex/example/connect/light_switch/connect_soc_switch/hw_filter_tags.yaml index 663bf0cac9..e849a43b80 100644 --- a/app/flex/example/connect/light_switch/connect_soc_switch/hw_filter_tags.yaml +++ b/app/flex/example/connect/light_switch/connect_soc_switch/hw_filter_tags.yaml @@ -4,7 +4,7 @@ tag: - hardware: device: memory: - flash: 211 + flash: 210 ram: 26 board: rf_bands: diff --git a/app/flex/example/connect/sensor_sink/connect_soc_sensor/hw_filter_tags.yaml b/app/flex/example/connect/sensor_sink/connect_soc_sensor/hw_filter_tags.yaml index ccaa7d31d4..2d43448587 100644 --- a/app/flex/example/connect/sensor_sink/connect_soc_sensor/hw_filter_tags.yaml +++ b/app/flex/example/connect/sensor_sink/connect_soc_sensor/hw_filter_tags.yaml @@ -4,7 +4,7 @@ tag: - hardware: device: memory: - flash: 219 + flash: 218 ram: 26 board: rf_bands: diff --git a/app/flex/example/connect/sensor_sink/connect_soc_sink/hw_filter_tags.yaml b/app/flex/example/connect/sensor_sink/connect_soc_sink/hw_filter_tags.yaml index 286f4ba708..44a3db9a61 100644 --- a/app/flex/example/connect/sensor_sink/connect_soc_sink/hw_filter_tags.yaml +++ b/app/flex/example/connect/sensor_sink/connect_soc_sink/hw_filter_tags.yaml @@ -4,7 +4,7 @@ tag: - hardware: device: memory: - flash: 213 + flash: 212 ram: 25 board: rf_bands: diff --git a/app/flex/example/rail/rail_soc_railtest/rail_soc_railtest.slcp b/app/flex/example/rail/rail_soc_railtest/rail_soc_railtest.slcp index b7da797f2e..6d484f1ed5 100644 --- a/app/flex/example/rail/rail_soc_railtest/rail_soc_railtest.slcp +++ b/app/flex/example/rail/rail_soc_railtest/rail_soc_railtest.slcp @@ -311,8 +311,6 @@ configuration: toolchain_settings: - option: optimize value: debug - - option: gcc_compiler_option - value: --no-builtin ui_hints: highlight: diff --git a/app/flex/example/rail/rail_soc_simple_trx_auto_ack/hw_filter_tags.yaml b/app/flex/example/rail/rail_soc_simple_trx_auto_ack/hw_filter_tags.yaml index 7357ae6109..d1bc72b198 100644 --- a/app/flex/example/rail/rail_soc_simple_trx_auto_ack/hw_filter_tags.yaml +++ b/app/flex/example/rail/rail_soc_simple_trx_auto_ack/hw_filter_tags.yaml @@ -4,7 +4,7 @@ tag: - hardware: device: memory: - flash: 102 + flash: 101 ram: 9 board: rf_bands: diff --git a/app/flex/flex_demos_only_demos.xml b/app/flex/flex_demos_only_demos.xml index c62b274e84..6d503f36e5 100644 --- a/app/flex/flex_demos_only_demos.xml +++ b/app/flex/flex_demos_only_demos.xml @@ -1,23 +1,23 @@ - - - - - - - Range Test BLE and IEEE802.15.4 with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This application demonstrates over the air range of the Silicon Labs boards. 5 predefined PHYs can be used for this: BLE: 125kbps, BLE: 500kbps, BLE: 1Mbps, BLE: 2Mbps, IEEE80215.4: 250kbps. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length defined by the PHY and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given predefined PHY and inspects the packets received. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. Radio related events can be logged on UART on demand. CLI can be used to set and get configuration of the app, and to start and stop it. To get started with CLI please send 'help' with a terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test BLE and IEEE802.15.4 with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This application demonstrates over the air range of the Silicon Labs boards. 5 predefined PHYs can be used for this: BLE: 125kbps, BLE: 500kbps, BLE: 1Mbps, BLE: 2Mbps, IEEE80215.4: 250kbps. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length defined by the PHY and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given predefined PHY and inspects the packets received. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. Radio related events can be logged on UART on demand. CLI can be used to set and get configuration of the app, and to start and stop it. To get started with CLI please send 'help' with a terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + diff --git a/app/flex/flex_production_demos.xml b/app/flex/flex_production_demos.xml index 104fc618da..5ba24e9528 100644 --- a/app/flex/flex_production_demos.xml +++ b/app/flex/flex_production_demos.xml @@ -1,484 +1,484 @@ - - - - - - - This is a customizable Range Test Sample Application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - This is a customizable Range Test Sample Application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - This is a customizable Range Test Sample Application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - This is a customizable Range Test Sample Application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - This is a customizable Range Test Sample Application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - This is a customizable Range Test Sample Application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - This is a customizable Range Test Sample Application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - This is a customizable Range Test Sample Application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - This is a customizable Range Test Sample Application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - This is a customizable Range Test Sample Application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - This is a customizable Range Test Sample Application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - - The purpose of the application is to demonstrate a simple wireless communication between two or more boards. In combination with the Light sample application it creates a basic switch functionality, where the light can be toggled in the Light node. After power up, the node is in SCAN state. It means the broadcast messages of the light modules can be captured. After pushing PB1 button, the closest Light module will be connected. This is called the LINK state. If the Light module has done the same procedure, light can be toggled from all the boards with pushing BP0 button + + + + + + + + - - - - - - - Range Test BLE and IEEE802.15.4 with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This application demonstrates over the air range of the Silicon Labs boards. 5 predefined PHYs can be used for this: BLE: 125kbps, BLE: 500kbps, BLE: 1Mbps, BLE: 2Mbps, IEEE80215.4: 250kbps. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length defined by the PHY and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given predefined PHY and inspects the packets received. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. Radio related events can be logged on UART on demand. CLI can be used to set and get configuration of the app, and to start and stop it. To get started with CLI please send 'help' with a terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test BLE and IEEE802.15.4 with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This application demonstrates over the air range of the Silicon Labs boards. 5 predefined PHYs can be used for this: BLE: 125kbps, BLE: 500kbps, BLE: 1Mbps, BLE: 2Mbps, IEEE80215.4: 250kbps. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length defined by the PHY and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given predefined PHY and inspects the packets received. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. Radio related events can be logged on UART on demand. CLI can be used to set and get configuration of the app, and to start and stop it. To get started with CLI please send 'help' with a terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test BLE and IEEE802.15.4 with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This application demonstrates over the air range of the Silicon Labs boards. 5 predefined PHYs can be used for this: BLE: 125kbps, BLE: 500kbps, BLE: 1Mbps, BLE: 2Mbps, IEEE80215.4: 250kbps. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length defined by the PHY and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given predefined PHY and inspects the packets received. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. Radio related events can be logged on UART on demand. CLI can be used to set and get configuration of the app, and to start and stop it. To get started with CLI please send 'help' with a terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test BLE and IEEE802.15.4 with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This application demonstrates over the air range of the Silicon Labs boards. 5 predefined PHYs can be used for this: BLE: 125kbps, BLE: 500kbps, BLE: 1Mbps, BLE: 2Mbps, IEEE80215.4: 250kbps. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length defined by the PHY and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given predefined PHY and inspects the packets received. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. Radio related events can be logged on UART on demand. CLI can be used to set and get configuration of the app, and to start and stop it. To get started with CLI please send 'help' with a terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test BLE and IEEE802.15.4 with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This application demonstrates over the air range of the Silicon Labs boards. 5 predefined PHYs can be used for this: BLE: 125kbps, BLE: 500kbps, BLE: 1Mbps, BLE: 2Mbps, IEEE80215.4: 250kbps. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length defined by the PHY and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given predefined PHY and inspects the packets received. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. Radio related events can be logged on UART on demand. CLI can be used to set and get configuration of the app, and to start and stop it. To get started with CLI please send 'help' with a terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test BLE and IEEE802.15.4 with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This application demonstrates over the air range of the Silicon Labs boards. 5 predefined PHYs can be used for this: BLE: 125kbps, BLE: 500kbps, BLE: 1Mbps, BLE: 2Mbps, IEEE80215.4: 250kbps. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length defined by the PHY and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given predefined PHY and inspects the packets received. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. Radio related events can be logged on UART on demand. CLI can be used to set and get configuration of the app, and to start and stop it. To get started with CLI please send 'help' with a terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test BLE and IEEE802.15.4 with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This application demonstrates over the air range of the Silicon Labs boards. 5 predefined PHYs can be used for this: BLE: 125kbps, BLE: 500kbps, BLE: 1Mbps, BLE: 2Mbps, IEEE80215.4: 250kbps. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length defined by the PHY and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given predefined PHY and inspects the packets received. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. Radio related events can be logged on UART on demand. CLI can be used to set and get configuration of the app, and to start and stop it. To get started with CLI please send 'help' with a terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test BLE and IEEE802.15.4 with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This application demonstrates over the air range of the Silicon Labs boards. 5 predefined PHYs can be used for this: BLE: 125kbps, BLE: 500kbps, BLE: 1Mbps, BLE: 2Mbps, IEEE80215.4: 250kbps. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length defined by the PHY and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given predefined PHY and inspects the packets received. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. Radio related events can be logged on UART on demand. CLI can be used to set and get configuration of the app, and to start and stop it. To get started with CLI please send 'help' with a terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test BLE and IEEE802.15.4 with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This application demonstrates over the air range of the Silicon Labs boards. 5 predefined PHYs can be used for this: BLE: 125kbps, BLE: 500kbps, BLE: 1Mbps, BLE: 2Mbps, IEEE80215.4: 250kbps. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length defined by the PHY and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given predefined PHY and inspects the packets received. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. Radio related events can be logged on UART on demand. CLI can be used to set and get configuration of the app, and to start and stop it. To get started with CLI please send 'help' with a terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + - - - - - - - Range Test with Bluetooth connectivity. It runs on top of Micrium OS RTOS and multiprotocol RAIL. This is a customizable application that demonstrates over the air range of the EFR32. This sample app can act as a Transmitter and a Receiver. The role can be selected in the LCD menu. Flashing this app into two separate boards makes it possible to test the features and specification of the radio. The sample also provides an example how the RAIL API can be used. A menu is displayed in the LCD, which allows the user to see the most important information about the settings and also change some of them. The left button navigates in the menu and the right button selects or changes options. The bottom line always shows what the buttons do in the particular context. In Tx Mode, the user can send packets. Packet length (7..64 bytes) and the number of packets to transmit (from 500 up to continuous) can be set. Output power can be set in the LCD menu, in 0.5dBm steps (power setpoint), between -15..+20dBm. Actual minimum and maximum power may vary in different frequencies as well as the power that is actually set by RAIL. The LCD menu informs the user about the setpoint and the actual power. In the LCD menu, the Power item displays the setpoint first, then actual value. In Rx Mode, the radio listens on the given channel and inspects the packets received. Only packets that are sent with the expected device ID, will be processed. Packet Error Rate, Bit Error Rate and RSSI of the packets is displayed to inform about the quality of the transmission. For both modes, the channel on which the Tx/Rx radio will operate and the device IDs of the transmitters and receiver radio, can be set. Radio related events can be logged on UART on demand. CLI can be used for setting and starting/stoping the application as well, to start with CLI interface send 'help' over terminal. Wireless Gecko mobile app can also be used to control this application over Bluetooth. Currently MicriumOS and FreeRTOS is supported by this sample app. NOTE: Due to the higher current consumption of the continuous radio usage (especially in Rx Mode), it is not recommended to power the boards from a coin cell. Instead, an USB power bank can be used if portability is needed. + + + + + + + diff --git a/app/flex/flex_production_templates.xml b/app/flex/flex_production_templates.xml index 39c9cdc9b7..d205552a8c 100644 --- a/app/flex/flex_production_templates.xml +++ b/app/flex/flex_production_templates.xml @@ -5,7 +5,7 @@ - + @@ -19,7 +19,7 @@ - + @@ -33,7 +33,7 @@ - + @@ -47,7 +47,7 @@ - + @@ -61,7 +61,7 @@ - + @@ -89,7 +89,7 @@ - + @@ -117,7 +117,7 @@ - + @@ -145,7 +145,7 @@ - + @@ -187,7 +187,7 @@ - + @@ -215,7 +215,7 @@ - + @@ -229,7 +229,7 @@ - + @@ -257,7 +257,7 @@ - + @@ -271,7 +271,7 @@ - + @@ -285,7 +285,7 @@ - + @@ -299,7 +299,7 @@ - + @@ -355,7 +355,7 @@ - + @@ -383,7 +383,7 @@ - + diff --git a/app/host/multiprotocol/zigbeed/multiprotocol-container/Dockerfile b/app/host/multiprotocol/zigbeed/multiprotocol-container/Dockerfile index d73e6f0557..06ade760ed 100644 --- a/app/host/multiprotocol/zigbeed/multiprotocol-container/Dockerfile +++ b/app/host/multiprotocol/zigbeed/multiprotocol-container/Dockerfile @@ -3,14 +3,51 @@ ARG BASE_CONTAINER=${SYSTEM_ARCH}/otbr_cpc FROM ${BASE_CONTAINER} ARG SYSTEM_ARCH=arm32v7a # trick to make the build environment have the variable defined -RUN DEBIAN_FRONTEND=noninteractive apt update && apt install -y socat tmux procps libreadline8 systemd init lsb-release libmbedtls-dev +# EMZIGBEE-10110: Disable the "apt install" as we want to avoid fetching packages from the Internet +# for short term. Instead, we are not fetching packages from Nexus and install them locally. +# For long term, we would need to redesign the container build process. +#RUN DEBIAN_FRONTEND=noninteractive apt update && apt install -y socat tmux procps libreadline8 systemd init lsb-release libmbedtls-dev # Install some non-essential software -RUN DEBIAN_FRONTEND=noninteractive apt update && apt install -y nano gdb +#RUN DEBIAN_FRONTEND=noninteractive apt update && apt install -y nano gdb # Install BlueZ -RUN DEBIAN_FRONTEND=noninteractive apt update && apt install -y bluetooth bluez bluez-tools rfkill libbluetooth-dev +#RUN DEBIAN_FRONTEND=noninteractive apt update && apt install -y bluetooth bluez bluez-tools rfkill libbluetooth-dev + +# Copy and Install packages locally +RUN mkdir mp_deb_arm32v7 +RUN mkdir mp_deb_arm64v8 +COPY mp_deb_arm32v7/* mp_deb_arm32v7/ +COPY mp_deb_arm64v8/* mp_deb_arm64v8/ + +# Some packages need to be installed in a certain order and run +# dpkg again at the end to make sure all dependencies are met. +RUN if [ "$SYSTEM_ARCH" = "arm32v7" ]; then \ + mv *.deb mp_deb_arm32v7; \ + dpkg -i mp_deb_arm32v7/linux-libc*.deb; \ + dpkg -i mp_deb_arm32v7/rpcsvc-proto*.deb; \ + dpkg -i mp_deb_arm32v7/perl-modules*.deb; \ + dpkg -i mp_deb_arm32v7/lib*.deb; \ + dpkg -i mp_deb_arm32v7/systemd_*.deb; \ + dpkg -i mp_deb_arm32v7/*.deb; \ + dpkg -i mp_deb_arm32v7/*.deb; \ + elif [ "$SYSTEM_ARCH" = "arm64v8" ]; then \ + mv *.deb mp_deb_arm64v8; \ + dpkg -i mp_deb_arm64v8/linux-libc*.deb; \ + dpkg -i mp_deb_arm64v8/rpcsvc-proto*.deb; \ + dpkg -i mp_deb_arm64v8/perl-modules*.deb; \ + dpkg -i mp_deb_arm64v8/lib*.deb; \ + dpkg -i mp_deb_arm64v8/systemd_*.deb; \ + dpkg -i mp_deb_arm64v8/*.deb; \ + dpkg -i mp_deb_arm64v8/*.deb; \ + fi +# This will resolve the unconfigured packages +RUN apt-get install -f -y + RUN systemctl disable bluetooth.service +# Remove packages after install +RUN rm -fr mp_deb_arm32v7 +RUN rm -fr mp_deb_arm64v8 # Remove "tail -f /var/log/syslog" from shell script RUN sed -i '$ d' /app/etc/docker/docker_entrypoint.sh diff --git a/app/host/multiprotocol/zigbeed/multiprotocol-container/run.sh b/app/host/multiprotocol/zigbeed/multiprotocol-container/run.sh index 1d5a29e6ec..5f3ffca6cd 100644 --- a/app/host/multiprotocol/zigbeed/multiprotocol-container/run.sh +++ b/app/host/multiprotocol/zigbeed/multiprotocol-container/run.sh @@ -82,8 +82,20 @@ while [[ $# -gt 0 ]]; do exit ;; -Z|--zigbee-host) + echo "Starting zigbeed..." docker exec -it multiprotocol systemctl start zigbeed sleep 5 + echo "Checking zigbeed status..." + while + docker exec -it multiprotocol systemctl status zigbeed | grep 'RCP version' + [[ $? -ne 0 ]] + do + sleep 3 + echo "Failed to start zigbeed, restarting..." + echo "(If errors persist, run 'journalctl -fex' inside container for logs.)" + docker exec -it multiprotocol systemctl restart zigbeed + done + echo "Starting Z3Gateway..." docker exec -it multiprotocol /usr/local/bin/Z3Gateway -p ttyZigbeeNCP exit ;; diff --git a/app/mcu_example/app_mcu.properties b/app/mcu_example/app_mcu.properties index 2732e694ef..7d08e4e3c4 100644 --- a/app/mcu_example/app_mcu.properties +++ b/app/mcu_example/app_mcu.properties @@ -3,9 +3,9 @@ id=com.silabs.sdk.mcu label=32-bit MCU SDK description=Silicon Labs 32-bit MCU SDK for EFM32 and EZR32 -version=6.3.0.0 +version=6.3.1.0 supportedParts=mcu.arm.efm32.* mcu.arm.ezr32.* .*wgm16.* -prop.subLabel=MCU\\ 6.3.0.0 +prop.subLabel=MCU\\ 6.3.1.0 # General properties are prepended with "prop." prop.file.templatesFile=mcu_production_templates.xml diff --git a/app/mcu_example/documentation/release-highlights.txt b/app/mcu_example/documentation/release-highlights.txt index 23a95b39ed..e1363d0142 100644 --- a/app/mcu_example/documentation/release-highlights.txt +++ b/app/mcu_example/documentation/release-highlights.txt @@ -1,3 +1,3 @@ -32-Bit MCU SDK 6.3.0.0 -- Added support for BRD2204C board. +32-Bit MCU SDK 6.3.1.0 +- Underlying platform changes only diff --git a/app/mcu_example/mcu_production_demos.xml b/app/mcu_example/mcu_production_demos.xml index 1e544b4a71..e1b433c4a3 100644 --- a/app/mcu_example/mcu_production_demos.xml +++ b/app/mcu_example/mcu_production_demos.xml @@ -1,71 +1,58 @@ - - - - - - - This example project demonstrates a wide range of features of the EFM32TG11 MCU and the SLSTK3301A Starter Kit. + + + + + + + - - - - - - - This example project demonstrates a wide range of features of the EFM32GG11 MCU and the SLSTK3701A Starter Kit. + + + + + + + - - - - - - - This example shows how to use the Micrium OS CANopen stack. It uses the EFM32GG11B starter kit's two CAN peripherals in external loopback mode. It requires CAN expansion board ISO-CAN-EXP REV 1.0 or REV 2.0. This example will, upon the user pressing either push buttons (BTN0, BTN1), update one entry in the CANopen object dictionary of node 1 on the 'can0' bus with a predefined value for each button. Upon changing the value, a PDO message will be triggered, which will be caught by node 2 on the 'can1' bus. Node 2 will in turn update its object dictionary with the received value. The value of the object of both nodes is continuously displayed on the LCD. + + + + + + + - - - - - - - MicriumOS Network example. This example shows how to use the Micrium OS network stack with the ETH peripheral on the EFM32GG11B starter kit. This example will initialize the RMII interface to the external PHY and setup a 100 Mbit connection. - - - - - - - - - - Example usage of microphones and MicriumOS HTTP server -This example shows how to sample data from the microphone and also how to stream that data on a web server using uC/HTTPs. -The audio is sampled from on-kit microphones by using LDMA. The sampled audio waveform is displayed on LCD. Sampling and encoding is performed in the main os task. Configuration can be found in common_declarations.h and config.h. For info on encoding, see IETFs and xiphs rfc6716, rfc7845 and rfc3533. - + + + + + + + - - - - - - - Hall effect demo code for the Si72xx-WD-Kit using a Silicon Labs SLSTK3400A-EFM32HG Starter Kit. You must have the Hall Effect Evaluation kit, Si72xx-WD-Kit, to make use of this demo. The Si72xx-WD-Kit includes two Si7210 sensors mounted on an expansion board (Si72xx-EXP) plus each of the six base part types mounted on small postage-stamp-sized (PS) boards. You must use the Silicon Labs SLSTK3400A-EFM32HG Starter Kit which is included in the Si72xx-WD-Kit. + + + + + + + diff --git a/app/mcu_example/micriumos_webmic/micriumos_webmic.slcp b/app/mcu_example/micriumos_webmic/micriumos_webmic.slcp index 7c25a32761..6d9c469197 100644 --- a/app/mcu_example/micriumos_webmic/micriumos_webmic.slcp +++ b/app/mcu_example/micriumos_webmic/micriumos_webmic.slcp @@ -129,5 +129,4 @@ readme: ui_hints: highlight: readme.md tag: - - hardware:component:eth - - prebuilt_demo \ No newline at end of file + - hardware:component:eth \ No newline at end of file diff --git a/app/wisun/component/app_cli/sl_wisun_app_cli.c b/app/wisun/component/app_cli/sl_wisun_app_cli.c index e4101a8ac5..a529a3211e 100644 --- a/app/wisun/component/app_cli/sl_wisun_app_cli.c +++ b/app/wisun/component/app_cli/sl_wisun_app_cli.c @@ -384,7 +384,7 @@ const app_cli_entry_t app_settings_entries[] = .get_handler = _app_cli_get_phy }, { - .key = "connection_state", + .key = "join_state", .domain = WISUN_CLI_DOMAIN_ID, .value_size = APP_CLI_VALUE_SIZE_UINT8, .input = APP_CLI_INPUT_FLAG_DEFAULT, @@ -435,6 +435,19 @@ const app_cli_entry_t app_settings_entries[] = .get_handler = app_settings_get_ip_address, .description = NULL }, + { + .key = "ip_address_primary_parent", + .domain = WISUN_CLI_DOMAIN_ID, + .value_size = APP_CLI_VALUE_SIZE_NONE, + .input = APP_CLI_INPUT_FLAG_DEFAULT, + .output = APP_CLI_OUTPUT_FLAG_DEFAULT, + .value = NULL, + .input_enum_list = NULL, + .output_enum_list = NULL, + .set_handler = NULL, + .get_handler = app_settings_get_ip_address, + .description = NULL + }, #if defined(SL_CATALOG_WISUN_MODE_SWITCH_PRESENT) { .key = "mode_switch_tx_counter", @@ -578,7 +591,7 @@ void app_disconnect(sl_cli_command_arg_t *arguments) ret = sl_wisun_get_join_state(&join_state); if (ret != SL_STATUS_OK) { - printf("[Failed: Getting joint state failed]\r\n"); + printf("[Failed: Getting join state failed]\r\n"); app_wisun_cli_mutex_unlock(); return; } @@ -822,7 +835,7 @@ static sl_status_t _app_cli_get_phy(char *value_str, sprintf(value_str, "%d", phy.operating_class); // operating mode } else if (strstr(entry->key, "operating_mode")) { - sprintf(value_str, "0x%02x", phy.operating_mode); + sprintf(value_str, "0x%x", phy.operating_mode); } return SL_STATUS_OK; diff --git a/app/wisun/component/iperf/config/sl_iperf_config.h b/app/wisun/component/iperf/config/sl_iperf_config.h index 6dec8793c2..c1e19bdf88 100644 --- a/app/wisun/component/iperf/config/sl_iperf_config.h +++ b/app/wisun/component/iperf/config/sl_iperf_config.h @@ -53,7 +53,7 @@ // Server receiver buffer size // Default value 1450 (UDPv6 size without fragmentation) -#define SL_IPERF_BUFFER_SIZE 1450U +#define SL_IPERF_BUFFER_SIZE 1234U // Set json formated log indent in space count // Default value: 2 diff --git a/app/wisun/component/iperf/sl_iperf_cli.c b/app/wisun/component/iperf/sl_iperf_cli.c index a435dfbe9b..a8ddcfd42b 100644 --- a/app/wisun/component/iperf/sl_iperf_cli.c +++ b/app/wisun/component/iperf/sl_iperf_cli.c @@ -414,6 +414,17 @@ static void _get_domain_key(const char *str_src, char **domain_dst, char **key_dst); +/**************************************************************************//** + * @brief Check argument value of uint16 and uint32 + * @details Helper function + * @param[in] arg_type Argument type + * @param[in] val Value + * @return true Valid value + * @return false Non-valid value + *****************************************************************************/ +static inline bool _check_arg_uint_val(const sl_iperf_cli_arg_type_t arg_type, + const int64_t val); + // ----------------------------------------------------------------------------- // Static Variables // ----------------------------------------------------------------------------- @@ -555,7 +566,7 @@ static sl_iperf_test_t _last_test = { 0U }; /**************************************************************************//** * @brief iPerf CLI set parameter * @details CLI function - * @param arguments Arguments + * @param[in] arguments Arguments *****************************************************************************/ void sl_iperf_cli_set(sl_cli_command_arg_t *arguments) { @@ -565,7 +576,7 @@ void sl_iperf_cli_set(sl_cli_command_arg_t *arguments) char *domain = NULL; char *key = NULL; sl_iperf_cli_property_t * prop = NULL; - uint32_t ui32_val = 0U; + int64_t i_val = 0LL; arg_cnt = (uint8_t) sl_cli_get_argument_count(arguments); @@ -597,7 +608,7 @@ void sl_iperf_cli_set(sl_cli_command_arg_t *arguments) if (key != NULL) { prop = _get_property(domain, key); if (prop == NULL) { - printf("[Not valid iPerf doman and key]\n"); + printf("[Not valid iPerf domain and key]\n"); return; } } @@ -652,17 +663,20 @@ void sl_iperf_cli_set(sl_cli_command_arg_t *arguments) case SL_IPERF_CLI_ARG_TYPE_STRING: prop->setter((void *) arg1_str); break; - case SL_IPERF_CLI_ARG_TYPE_UINT32: - ui32_val = atol(arg1_str); - prop->setter((void *) &ui32_val); - break; case SL_IPERF_CLI_ARG_TYPE_UINT16: - ui32_val = atoi(arg1_str); - prop->setter((void *) &ui32_val); + case SL_IPERF_CLI_ARG_TYPE_UINT32: + i_val = atoll(arg1_str); + if (_check_arg_uint_val(prop->type, i_val)) { + prop->setter((void *) &i_val); + } else { + printf("[Not valid iPerf command argument value]\n"); + } break; default: + printf("[Not valid iPerf command argument type]\n"); break; } + _print_property_val(prop); return; } @@ -673,7 +687,7 @@ void sl_iperf_cli_set(sl_cli_command_arg_t *arguments) /**************************************************************************//** * @brief iPerf CLI get parameter * @details CLI function - * @param arguments Arguments + * @param[in] arguments Arguments *****************************************************************************/ void sl_iperf_cli_get(sl_cli_command_arg_t *arguments) { @@ -714,7 +728,7 @@ void sl_iperf_cli_get(sl_cli_command_arg_t *arguments) if (key != NULL) { prop = _get_property(domain, key); if (prop == NULL) { - printf("[Not valid iPerf doman and key]\n"); + printf("[Not valid iPerf domain and key]\n"); return; } } @@ -856,7 +870,12 @@ static inline const char *_opt_packet_number_getter(void) // buffer length static inline void _opt_buffer_length_setter(void *val) { - _options.buf_len = *(uint16_t*)val; + uint16_t value = *(uint16_t*)val; + if (!value || value > SL_IPERF_BUFFER_SIZE) { + printf("[Not valid buffer size]\n"); + return; + } + _options.buf_len = value; } static inline const char *_opt_buffer_length_getter(void) @@ -867,7 +886,13 @@ static inline const char *_opt_buffer_length_getter(void) // duration static inline void _opt_duration_setter(void *val) { - _options.duration_ms = *(uint16_t*)val * SL_IPERF_TIME_S_TO_MS_ML; + uint32_t val32 = 0UL; + val32 = *(uint32_t*) val * SL_IPERF_TIME_S_TO_MS_ML; + if (val32 > UINT16_MAX) { + printf("[Duration Time value is overflowed]\n"); + } else { + _options.duration_ms = (uint16_t) val32; + } } static inline const char *_opt_duration_getter(void) @@ -878,7 +903,13 @@ static inline const char *_opt_duration_getter(void) // interval static inline void _opt_interval_setter(void *val) { - _options.interval_ms = *(uint16_t*)val * SL_IPERF_TIME_S_TO_MS_ML; + uint32_t val32 = 0UL; + val32 = *(uint32_t*) val * SL_IPERF_TIME_S_TO_MS_ML; + if (val32 > UINT16_MAX) { + printf("[Interval Time value is overflowed]\n"); + } else { + _options.interval_ms = (uint16_t) val32; + } } static inline const char *_opt_interval_getter(void) @@ -1063,3 +1094,14 @@ static void _get_domain_key(const char *str_src, domain_key_buff[SL_IPERF_CLI_MAX_STR_ARG_LEN - 1] = '\0'; } + +static inline bool _check_arg_uint_val(const sl_iperf_cli_arg_type_t arg_type, + const int64_t val) +{ + if (val < 0LL || + (arg_type == SL_IPERF_CLI_ARG_TYPE_UINT32 && val > UINT32_MAX) || + (arg_type == SL_IPERF_CLI_ARG_TYPE_UINT16 && val > UINT16_MAX)) { + return false; + } + return true; +} \ No newline at end of file diff --git a/app/wisun/component/iperf/sl_iperf_udp_clnt.c b/app/wisun/component/iperf/sl_iperf_udp_clnt.c index f5a5a44e1b..3c4cf9ccbc 100644 --- a/app/wisun/component/iperf/sl_iperf_udp_clnt.c +++ b/app/wisun/component/iperf/sl_iperf_udp_clnt.c @@ -47,6 +47,9 @@ // Macros and Typedefs // ----------------------------------------------------------------------------- +/// Client FinACK Receive Timeout +#define SL_IPERF_FINACK_RECV_TIMEOUT_MS 10000UL + /// Client TX parameters typedef struct client_tx_params { /// Packet count @@ -202,7 +205,7 @@ void sl_iperf_test_udp_client(sl_iperf_test_t * test) params.packet_size, &test->conn.srv_addr); } - sl_iperf_delay_ms(100U); + sl_iperf_delay_ms(SL_IPERF_FINACK_RECV_TIMEOUT_MS / SL_IPERF_SERVER_UDP_TX_FINACK_COUNT); } if (!finack_received) { @@ -276,14 +279,11 @@ static void _udp_client_calc_tx(sl_iperf_test_t * const test, } // trim buff size if it's necessary - if (!test->opt.buf_len) { + if (!test->opt.buf_len || test->opt.buf_len > test->conn.buff_size) { test->opt.buf_len = test->conn.buff_size; } tx_info->packet_size = test->opt.buf_len; - if (!tx_info->packet_size) { - return; - } // If packet number is explicitly set if (test->opt.packet_nbr) { diff --git a/app/wisun/component/iperf/sl_iperf_util.c b/app/wisun/component/iperf/sl_iperf_util.c index 41bbd31f59..431eef098c 100644 --- a/app/wisun/component/iperf/sl_iperf_util.c +++ b/app/wisun/component/iperf/sl_iperf_util.c @@ -221,8 +221,8 @@ void sl_iperf_print_test_log_json(sl_iperf_test_t * const test) sl_iperf_log_print(test->log, "%*s\"duration_ms\": %u,\n", __indent(3U), test->opt.duration_ms); sl_iperf_log_print(test->log, "%*s\"win_size\": %u,\n", __indent(3U), test->opt.win_size); sl_iperf_log_print(test->log, "%*s\"persistent\": %s,\n", __indent(3U), _bool_to_json(test->opt.persistent)); - sl_iperf_log_print(test->log, "%*s\"interval_ms\": %u\n", __indent(3U), test->opt.interval_ms); - sl_iperf_log_print(test->log, "%*s\"bw_format\": \"%s\",\n", __indent(3U), test->opt.bw_format); + sl_iperf_log_print(test->log, "%*s\"interval_ms\": %u,\n", __indent(3U), test->opt.interval_ms); + sl_iperf_log_print(test->log, "%*s\"bw_format\": \"%s\"\n", __indent(3U), sl_iperf_opt_bw_format_to_str(test->opt.bw_format)); sl_iperf_log_print(test->log, "%*s},\n", __indent(2U)); sl_iperf_log_print(test->log, "%*s\"statistic\": {\n", __indent(2U)); sl_iperf_log_print(test->log, "%*s\"nbr_calls\": %lu,\n", __indent(3U), test->statistic.nbr_calls); @@ -248,7 +248,7 @@ void sl_iperf_print_test_log_json(sl_iperf_test_t * const test) sl_iperf_log_print(test->log, "%*s\"bandwidth\": %lu,\n", __indent(3U), test->statistic.bandwidth); sl_iperf_log_print(test->log, "%*s\"finack_tot_len\": %lu,\n", __indent(3U), test->statistic.finack_tot_len); sl_iperf_log_print(test->log, "%*s\"finack_duration_ms\": %lu,\n", __indent(3U), test->statistic.finack_duration_ms); - sl_iperf_log_print(test->log, "%*s\"finack_pkt\": %lu,\n", __indent(3U), test->statistic.finack_pkt); + sl_iperf_log_print(test->log, "%*s\"finack_pkt\": %lu\n", __indent(3U), test->statistic.finack_pkt); sl_iperf_log_print(test->log, "%*s}\n", __indent(2U)); sl_iperf_log_print(test->log, "%*s}\n", __indent(1U)); sl_iperf_log_print(test->log, "}\n"); @@ -616,7 +616,14 @@ void sl_iperf_test_calculate_average_bandwidth(sl_iperf_test_t * const test) _data_converter(test->statistic.bytes, SL_IPERF_DATA_KBYTE_TO_BYTE_ML, ¶ms.fval_data); - + if (time_duration_ms) { + // calculate bandwidth for statistic in bits/sec + test->statistic.bandwidth = (uint32_t)(((uint64_t)test->statistic.bytes * SL_IPERF_DATA_BYTE_TO_BIT_ML * + SL_IPERF_TIME_S_TO_MS_ML) / time_duration_ms); + } else { + test->statistic.bandwidth = 0UL; + } + sl_iperf_calc_time_from_ms(¶ms.end_time, time_duration_ms); params.pkt_cnt = test->statistic.tot_packets; params.lost_pkt_curr = test->statistic.udp_lost_pkt; diff --git a/app/wisun/component/ping/sl_wisun_ping_cli.c b/app/wisun/component/ping/sl_wisun_ping_cli.c index dfb9d2832f..5f9a361eb4 100644 --- a/app/wisun/component/ping/sl_wisun_ping_cli.c +++ b/app/wisun/component/ping/sl_wisun_ping_cli.c @@ -73,7 +73,7 @@ void app_ping(sl_cli_command_arg_t *arguments) SL_WISUN_PING_PACKET_COUNT, SL_WISUN_PING_PACKET_SIZE, NULL, NULL)) { - printf("[Failed: ping was not succesful]\n"); + printf("[Failed: ping was not successful]\n"); } app_wisun_cli_mutex_unlock(); diff --git a/app/wisun/documentation/release-highlights.txt b/app/wisun/documentation/release-highlights.txt index 0dbbb68b64..ac2b929547 100644 --- a/app/wisun/documentation/release-highlights.txt +++ b/app/wisun/documentation/release-highlights.txt @@ -1,6 +1,2 @@ -Wi-SUN SDK 1.3.0.0 -- FAN 1.0 certified Router & Border Router -- Perf throughput test tool -- Wi-SUN Configurator -- CLI for certification -- ARIB T108 support +Wi-SUN SDK 1.3.1.0 +- Targeted quality improvements and bug fixes diff --git a/app/wisun/documentation/slWi-SUN_docContent.xml b/app/wisun/documentation/slWi-SUN_docContent.xml index e859b1b57a..0894bb114e 100644 --- a/app/wisun/documentation/slWi-SUN_docContent.xml +++ b/app/wisun/documentation/slWi-SUN_docContent.xml @@ -1,131 +1,131 @@ - - + + + Explains how NVM3 can be used as non-volatile data storage in various protocol implementations. - Explains how NVM3 can be used as non-volatile data storage in various protocol implementations. - + + Describes how to integrate crypto functionality into applications using PSA Crypto compared to Mbed TLS. - Describes how to integrate crypto functionality into applications using PSA Crypto compared to Mbed TLS. - + + Gecko Bootloader v2.x, introduced in GSDK 4.0, contains a number of changes compared to Gecko Bootloader v1.x. This document describes the differences between the versions, including how to configure the new Gecko Bootloader in Simplicity Studio 5. - Gecko Bootloader v2.x, introduced in GSDK 4.0, contains a number of changes compared to Gecko Bootloader v1.x. This document describes the differences between the versions, including how to configure the new Gecko Bootloader in Simplicity Studio 5. - + + Describes the test environment and methods for testing Wi-SUN network performance. The results are intended to provide guidance on design practices and principles as well as expected field performance results. - Describes the test environment and methods for testing Wi-SUN network performance. The results are intended to provide guidance on design practices and principles as well as expected field performance results. - + + Describes how to use the Silicon Labs Wi-SUN Linux border router or the EFR32 standalone border router demonstration. Covers the associated configuration and debugging tools. - Describes how to use the Silicon Labs Wi-SUN Linux border router or the EFR32 standalone border router demonstration. Covers the associated configuration and debugging tools. - + + Describes how to use the Wi-SUN Network Performance Measurement Application from either the LCD output or the CLI, and includes suggestions for improving ping latency in a Wi-SUN network. - Describes how to use the Wi-SUN Network Performance Measurement Application from either the LCD output or the CLI, and includes suggestions for improving ping latency in a Wi-SUN network. - + + Provides an overview and hyperlinks to all packaged documentation. - Provides an overview and hyperlinks to all packaged documentation. - + + Describes how to get started with Wi-SUN development using the Silicon Labs Wi-SUN software development kit (SDK) and Simplicity Studio 5 with a compatible wireless starter kit (WSTK). - Describes how to get started with Wi-SUN development using the Silicon Labs Wi-SUN software development kit (SDK) and Simplicity Studio 5 with a compatible wireless starter kit (WSTK). - + + Contains a comprehensive list of APIs used to interface to the Silicon Labs Wi-SUN stack. - Contains a comprehensive list of APIs used to interface to the Silicon Labs Wi-SUN stack. - + + Reference for those developing applications using the Silicon Labs Wi-SUN SDK. The guide covers guidelines to develop an application on top of Silicon Labs Wi-SUN stack . The purpose of this document is to fill in the gaps between the Silicon Labs Wi-SUN Field Area Network (FAN) API reference, Gecko Platform references, and documentation for the target EFR32xG part. - Reference for those developing applications using the Silicon Labs Wi-SUN SDK. The guide covers guidelines to develop an application on top of Silicon Labs Wi-SUN stack . The purpose of this document is to fill in the gaps between the Silicon Labs Wi-SUN Field Area Network (FAN) API reference, Gecko Platform references, and documentation for the target EFR32xG part. - + + Lists compatibility requirements and sources for all software components in the development environment. Discusses the latest changes to the SiliconLabs Wi-SUN SDK, including added/deleted/deprecated features/API. Reviews fixed and known issues. - Lists compatibility requirements and sources for all software components in the development environment. Discusses the latest changes to the SiliconLabs Wi-SUN SDK, including added/deleted/deprecated features/API. Reviews fixed and known issues. - + + A detailed overview of the changes, additions, and fixes in the Gecko Platform components. The Gecko Platform includes EMLIB, EMDRV, RAIL Library, NVM3, and the component-based infrastructure. - A detailed overview of the changes, additions, and fixes in the Gecko Platform components. The Gecko Platform includes EMLIB, EMDRV, RAIL Library, NVM3, and the component-based infrastructure. - + + Introduces the security concepts that must be considered when implementing an Internet of Things (IoT) system. Using the ioXt Alliance's eight security principles as a structure, it clearly delineates the solutions Silicon Labs provides to support endpoint security and what you must do outside of the Silicon Labs framework. - Introduces the security concepts that must be considered when implementing an Internet of Things (IoT) system. Using the ioXt Alliance's eight security principles as a structure, it clearly delineates the solutions Silicon Labs provides to support endpoint security and what you must do outside of the Silicon Labs framework. - + + Introduces bootloading for Silicon Labs networking devices. Discusses the Gecko Bootloader as well as legacy Ember and Bluetooth bootloaders, and describes the file formats used by each. - Introduces bootloading for Silicon Labs networking devices. Discusses the Gecko Bootloader as well as legacy Ember and Bluetooth bootloaders, and describes the file formats used by each. - + + Introduces non-volatile data storage using flash and the three different storage implementations offered for Silicon Labs microcontrollers and SoCs: Simulated EEPROM, PS Store, and NVM3. - Introduces non-volatile data storage using flash and the three different storage implementations offered for Silicon Labs microcontrollers and SoCs: Simulated EEPROM, PS Store, and NVM3. - + + Describes how and when to use Simplicity Commander's Command-Line Interface. - Describes how and when to use Simplicity Commander's Command-Line Interface. - + + Describes the high-level implementation of the Silicon Labs Gecko Bootloader for EFR32 SoCs and NCPs, and provides information on how to get started using the Gecko Bootloader with Silicon Labs wireless protocol stacks in GSDK 4.0 and higher. - Describes the high-level implementation of the Silicon Labs Gecko Bootloader for EFR32 SoCs and NCPs, and provides information on how to get started using the Gecko Bootloader with Silicon Labs wireless protocol stacks in GSDK 4.0 and higher. diff --git a/app/wisun/esf.properties b/app/wisun/esf.properties index e714ae2ae1..fa6fb8e171 100644 --- a/app/wisun/esf.properties +++ b/app/wisun/esf.properties @@ -3,8 +3,8 @@ id=com.silabs.stack.wisun label=Wi-SUN description=Silicon Labs Wi-SUN SDK -version=1.3.0.0 -prop.subLabel=Wi-SUN\\ 1.3.0.0 +version=1.3.1.0 +prop.subLabel=Wi-SUN\\ 1.3.1.0 # General properties are prepended with "prop." prop.file.templatesFile=wisun_production_templates.xml wisun_br_demos_templates.xml diff --git a/app/wisun/example/wisun_soc_network_measurement/hw_filter_tags.yaml b/app/wisun/example/wisun_soc_network_measurement/hw_filter_tags.yaml index e7482c45d1..b575bed139 100644 --- a/app/wisun/example/wisun_soc_network_measurement/hw_filter_tags.yaml +++ b/app/wisun/example/wisun_soc_network_measurement/hw_filter_tags.yaml @@ -4,7 +4,7 @@ tag: - hardware: device: memory: - flash: 736 + flash: 737 ram: 183 board: rf_bands: diff --git a/app/wisun/wisun_br_demos_demos.xml b/app/wisun/wisun_br_demos_demos.xml index e6eb1b067a..e9f6aa0bc7 100644 --- a/app/wisun/wisun_br_demos_demos.xml +++ b/app/wisun/wisun_br_demos_demos.xml @@ -1,203 +1,203 @@ - - - - - - - The Wi-SUN RCP (Radio CoProcessor) application provides a radio interface to a Linux host. It is meant to be paired with wsbrd (Wi-SUN Network implementation for Linux) to run as a Linux border router device. + + + + + + + - - - - - - - The Wi-SUN RCP (Radio CoProcessor) application provides a radio interface to a Linux host. It is meant to be paired with wsbrd (Wi-SUN Network implementation for Linux) to run as a Linux border router device. + + + + + + + - - - - - - - The Wi-SUN RCP (Radio CoProcessor) application provides a radio interface to a Linux host. It is meant to be paired with wsbrd (Wi-SUN Network implementation for Linux) to run as a Linux border router device. + + + + + + + - - - - - - - The Wi-SUN RCP (Radio CoProcessor) application provides a radio interface to a Linux host. It is meant to be paired with wsbrd (Wi-SUN Network implementation for Linux) to run as a Linux border router device. + + + + + + + - - - - - - - The Wi-SUN RCP (Radio CoProcessor) application provides a radio interface to a Linux host. It is meant to be paired with wsbrd (Wi-SUN Network implementation for Linux) to run as a Linux border router device. + + + + + + + - - - - - - - The Wi-SUN RCP (Radio CoProcessor) application provides a radio interface to a Linux host. It is meant to be paired with wsbrd (Wi-SUN Network implementation for Linux) to run as a Linux border router device. + + + + + + + - - - - - - - The Wi-SUN RCP (Radio CoProcessor) application provides a radio interface to a Linux host. It is meant to be paired with wsbrd (Wi-SUN Network implementation for Linux) to run as a Linux border router device. + + + + + + + - - - - - - - The Wi-SUN RCP (Radio CoProcessor) application provides a radio interface to a Linux host. It is meant to be paired with wsbrd (Wi-SUN Network implementation for Linux) to run as a Linux border router device. + + + + + + + - - - - - - - The Wi-SUN RCP (Radio CoProcessor) application provides a radio interface to a Linux host. It is meant to be paired with wsbrd (Wi-SUN Network implementation for Linux) to run as a Linux border router device. + + + + + + + - - - - - - - The Wi-SUN RCP (Radio CoProcessor) application provides a radio interface to a Linux host. It is meant to be paired with wsbrd (Wi-SUN Network implementation for Linux) to run as a Linux border router device. + + + + + + + - - - - - - - This demo is an out-of-the-box Wi-SUN border router application. It provides a command-line interface to control basic configurations. + + + + + + + - - - - - - - This demo is an out-of-the-box Wi-SUN border router application. It provides a command-line interface to control basic configurations. + + + + + + + - - - - - - - This demo is an out-of-the-box Wi-SUN border router application. It provides a command-line interface to control basic configurations. + + + + + + + - - - - - - - This demo is an out-of-the-box Wi-SUN border router application. It provides a command-line interface to control basic configurations. + + + + + + + - - - - - - - This demo is an out-of-the-box Wi-SUN border router application. It provides a command-line interface to control basic configurations. + + + + + + + - - - - - - - This demo is an out-of-the-box Wi-SUN border router application. It provides a command-line interface to control basic configurations. + + + + + + + - - - - - - - This demo is an out-of-the-box Wi-SUN border router application. It provides a command-line interface to control basic configurations. + + + + + + + - - - - - - - This demo is an out-of-the-box Wi-SUN border router application. It provides a command-line interface to control basic configurations. + + + + + + + - - - - - - - This demo is an out-of-the-box Wi-SUN border router application. It provides a command-line interface to control basic configurations. + + + + + + + - - - - - - - This demo is an out-of-the-box Wi-SUN border router application. It provides a command-line interface to control basic configurations. + + + + + + + diff --git a/app/wisun/wisun_production_demos.xml b/app/wisun/wisun_production_demos.xml index 1e6adb807e..3d46709cf1 100644 --- a/app/wisun/wisun_production_demos.xml +++ b/app/wisun/wisun_production_demos.xml @@ -1,103 +1,103 @@ - - - - - - - The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN stack APIs. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. + + + + + + + - - - - - - - The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN stack APIs. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. + + + + + + + - - - - - - - The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN stack APIs. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. + + + + + + + - - - - - - - The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN stack APIs. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. + + + + + + + - - - - - - - The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN stack APIs. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. + + + + + + + - - - - - - - The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN stack APIs. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. + + + + + + + - - - - - - - The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN stack APIs. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. + + + + + + + - - - - - - - The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN stack APIs. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. + + + + + + + - - - - - - - The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN stack APIs. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. + + + + + + + - - - - - - - The Wi-SUN CLI (Command-Line Interface) sample application allows developers to easily evaluate the Wi-SUN stack APIs. The Wi-SUN command line interface provides a serial interface to a number of the Wi-SUN stack functions. For example, it can be used to connect the Wi-SUN device to a Wi-SUN border router and exchange IP packets. + + + + + + + diff --git a/app/wisun/wisun_production_templates.xml b/app/wisun/wisun_production_templates.xml index a5fece82d2..7d7aefa251 100644 --- a/app/wisun/wisun_production_templates.xml +++ b/app/wisun/wisun_production_templates.xml @@ -22,7 +22,7 @@ - + diff --git a/app/zcl/ha.xml b/app/zcl/ha.xml index 81be9063b2..dd106c61f0 100644 --- a/app/zcl/ha.xml +++ b/app/zcl/ha.xml @@ -114,7 +114,7 @@ limitations under the License. min setpoint dead band remote sensing control sequence of operation - system mode + system mode alarm mask thermostat running mode diff --git a/app/zcl/types.xml b/app/zcl/types.xml index a14758793b..f580bbe0eb 100644 --- a/app/zcl/types.xml +++ b/app/zcl/types.xml @@ -340,6 +340,8 @@ limitations under the License. + + diff --git a/app/zcl/zcl-zap.json b/app/zcl/zcl-zap.json index 7895922406..94907c300f 100644 --- a/app/zcl/zcl-zap.json +++ b/app/zcl/zcl-zap.json @@ -1,6 +1,11 @@ { - "version": "Zigbee Silabs ZCL data", - "xmlRoot": [".", "../../../../app/zcl/"], + "description": "Zigbee Silabs ZCL data", + "category": "zigbee", + "version": 1, + "xmlRoot": [ + ".", + "../../../../app/zcl/" + ], "xmlFile": [ "ami-devices.xml", "ami.xml", @@ -30,9 +35,15 @@ "manufacturersXml": "manufacturers.xml", "options": { "text": { - "defaultResponsePolicy": ["Always", "Conditional", "Never"] + "defaultResponsePolicy": [ + "Always", + "Conditional", + "Never" + ] }, - "bool": ["commandDiscovery"] + "bool": [ + "commandDiscovery" + ] }, "defaults": { "text": { @@ -51,4 +62,4 @@ "STRING", "STRUCT" ] -} +} \ No newline at end of file diff --git a/gecko_sdk.slcs b/gecko_sdk.slcs index 92b78a165c..e849b715dc 100644 --- a/gecko_sdk.slcs +++ b/gecko_sdk.slcs @@ -2,7 +2,7 @@ id: "gecko_sdk" label: "Gecko SDK Suite" description: |- Gecko SDK Suite for EM3xx, EFM32, EZR32 and EFR32 microcontrollers and radios. -sdk_version: "4.1.0" +sdk_version: "4.1.1" specification_version: 7 component_path: - path: "app/amazon/component" diff --git a/hardware/board/component/brd2603a.slcc b/hardware/board/component/brd2603a.slcc index db7d3ad2a7..5264b911e7 100644 --- a/hardware/board/component/brd2603a.slcc +++ b/hardware/board/component/brd2603a.slcc @@ -13,6 +13,7 @@ - name: hardware_board - name: hardware_board_stk - name: hardware_board_from_stk + - name: hardware_board_from_zgm230-dk2603a - name: hardware_board_has_si70xx - name: hardware_board_has_tempsensor - name: hardware_board_has_vcom @@ -47,11 +48,11 @@ - name: SL_BOARD_NAME value: '"BRD2603A"' - name: SL_BOARD_REV - value: '"A00"' + value: '"A01"' - tag: - board:pn:BRD2603 - board:variant:A - - board:revision:A00 + - board:revision:A01 - board:device:zgm230sb27hgn - hardware:has:vcom - hardware:has:pti diff --git a/hardware/board/component/brd2703a.slcc b/hardware/board/component/brd2703a.slcc new file mode 100644 index 0000000000..577cfabac1 --- /dev/null +++ b/hardware/board/component/brd2703a.slcc @@ -0,0 +1,17 @@ +!!omap +- id: brd2703a +- label: BRD2703A +- package: platform +- description: Board support for BRD2703A. +- category: Platform|Board|Starter Kit +- quality: production +- requires: + - name: brd2703a_revision +- provides: + - name: brd2703a + - name: hardware_board_from_stk + - name: hardware_board_from_xg24-ek2703a +- recommends: + - id: brd2703a_a01 +- ui_hints: + visibility: never diff --git a/hardware/board/component/brd2703a_a00.slcc b/hardware/board/component/brd2703a_a00.slcc new file mode 100644 index 0000000000..7993fd466f --- /dev/null +++ b/hardware/board/component/brd2703a_a00.slcc @@ -0,0 +1,50 @@ +!!omap +- id: brd2703a_a00 +- label: BRD2703A rev A00 +- package: platform +- description: Board support for BRD2703A. +- category: Platform|Board|Starter Kit +- quality: production +- requires: + - name: efr32mg24b020f1536im48 + - name: brd2703a_config +- provides: + - name: brd2703a_revision + - name: brd2703a_a00 + - name: hardware_board + - name: hardware_board_stk + - name: hardware_board_has_vcom + - name: hardware_board_has_hfxo + - name: hardware_board_has_lfxo + - name: hardware_board_supports_rf_band_2400 + - name: hardware_board_supports_1_rf_band + - name: hardware_board_default_rf_band + - name: hardware_board_default_rf_band_2400 +- recommends: + - id: iostream_eusart + instance: + - vcom + - id: bootloader_uart_driver + - id: simple_led + instance: + - led0 + - led1 + - id: simple_button + instance: + - btn0 + - btn1 +- template_contribution: [] +- define: + - name: SL_BOARD_NAME + value: '"BRD2703A"' + - name: SL_BOARD_REV + value: '"A00"' +- tag: + - board:pn:BRD2703 + - board:variant:A + - board:revision:A00 + - board:device:efr32mg24b020f1536im48 + - hardware:has:vcom + - hardware:has:pti + - hardware:has:led:2 + - hardware:has:button:2 diff --git a/hardware/board/component/brd2703a_a01.slcc b/hardware/board/component/brd2703a_a01.slcc new file mode 100644 index 0000000000..5c81082a66 --- /dev/null +++ b/hardware/board/component/brd2703a_a01.slcc @@ -0,0 +1,50 @@ +!!omap +- id: brd2703a_a01 +- label: BRD2703A rev A01 +- package: platform +- description: Board support for BRD2703A. +- category: Platform|Board|Starter Kit +- quality: production +- requires: + - name: efr32mg24b210f1536im48 + - name: brd2703a_config +- provides: + - name: brd2703a_revision + - name: brd2703a_a01 + - name: hardware_board + - name: hardware_board_stk + - name: hardware_board_has_vcom + - name: hardware_board_has_hfxo + - name: hardware_board_has_lfxo + - name: hardware_board_supports_rf_band_2400 + - name: hardware_board_supports_1_rf_band + - name: hardware_board_default_rf_band + - name: hardware_board_default_rf_band_2400 +- recommends: + - id: iostream_eusart + instance: + - vcom + - id: bootloader_uart_driver + - id: simple_led + instance: + - led0 + - led1 + - id: simple_button + instance: + - btn0 + - btn1 +- template_contribution: [] +- define: + - name: SL_BOARD_NAME + value: '"BRD2703A"' + - name: SL_BOARD_REV + value: '"A01"' +- tag: + - board:pn:BRD2703 + - board:variant:A + - board:revision:A01 + - board:device:efr32mg24b210f1536im48 + - hardware:has:vcom + - hardware:has:pti + - hardware:has:led:2 + - hardware:has:button:2 diff --git a/hardware/board/component/brd2703a_a02.slcc b/hardware/board/component/brd2703a_a02.slcc new file mode 100644 index 0000000000..427a6924a9 --- /dev/null +++ b/hardware/board/component/brd2703a_a02.slcc @@ -0,0 +1,50 @@ +!!omap +- id: brd2703a_a02 +- label: BRD2703A rev A02 +- package: platform +- description: Board support for BRD2703A. +- category: Platform|Board|Starter Kit +- quality: production +- requires: + - name: efr32mg24b210f1536im48 + - name: brd2703a_config +- provides: + - name: brd2703a_revision + - name: brd2703a_a02 + - name: hardware_board + - name: hardware_board_stk + - name: hardware_board_has_vcom + - name: hardware_board_has_hfxo + - name: hardware_board_has_lfxo + - name: hardware_board_supports_rf_band_2400 + - name: hardware_board_supports_1_rf_band + - name: hardware_board_default_rf_band + - name: hardware_board_default_rf_band_2400 +- recommends: + - id: iostream_eusart + instance: + - vcom + - id: bootloader_uart_driver + - id: simple_led + instance: + - led0 + - led1 + - id: simple_button + instance: + - btn0 + - btn1 +- template_contribution: [] +- define: + - name: SL_BOARD_NAME + value: '"BRD2703A"' + - name: SL_BOARD_REV + value: '"A02"' +- tag: + - board:pn:BRD2703 + - board:variant:A + - board:revision:A02 + - board:device:efr32mg24b210f1536im48 + - hardware:has:vcom + - hardware:has:pti + - hardware:has:led:2 + - hardware:has:button:2 diff --git a/hardware/board/component/brd4109a.slcc b/hardware/board/component/brd4109a.slcc deleted file mode 100644 index 49fa1f705f..0000000000 --- a/hardware/board/component/brd4109a.slcc +++ /dev/null @@ -1,71 +0,0 @@ -!!omap -- id: brd4109a -- label: BRD4109A -- package: platform -- description: Board support for BRD4109A. -- category: Platform|Board|Radio Board -- quality: production -- requires: - - name: efr32bg27c230f768im40 - - name: brd4109a_config - - name: hardware_board_mainboard -- provides: - - name: brd4109a - - name: hardware_board - - name: hardware_board_rb - - name: hardware_board_from_stk - - name: hardware_board_has_si70xx - - name: hardware_board_has_tempsensor - - name: hardware_board_has_vcom - - name: hardware_board_has_spiflash - - name: hardware_board_has_hfxo - - name: hardware_board_has_lfxo - - name: hardware_board_supports_rf_band_2400 - - name: hardware_board_supports_1_rf_band - - name: hardware_board_default_rf_band - - name: hardware_board_default_rf_band_2400 -- recommends: - - id: brd4002a - - id: iostream_eusart - instance: - - vcom - - id: bootloader_uart_driver - - id: i2cspm - instance: - - sensor - - id: ls013b7dh03 - - id: memlcd_eusart - - id: simple_led - instance: - - led0 - - led1 - - id: skrhaae010 - - id: simple_button - instance: - - btn0 - - btn1 - - id: mx25_flash_shutdown_eusart - - id: bootloader_spi_controller_usart_driver - - id: bootloader_spi_peripheral_usart_driver -- template_contribution: - - name: board_default_init - value: sl_board_disable_vcom() -- define: - - name: SL_BOARD_NAME - value: '"BRD4109A"' - - name: SL_BOARD_REV - value: '"A00"' -- tag: - - board:pn:BRD4109 - - board:variant:A - - board:revision:A00 - - board:device:efr32bg27c230f768im40 - - hardware:has:vcom - - hardware:has:pti - - hardware:has:sensor:si7021 - - hardware:has:display:ls013b7dh03 - - hardware:has:led:2 - - hardware:has:joystick:skrhaae010 - - hardware:has:button:2 - - hardware:has:memory:spi:mx25r8035f - - hardware:shares:button:led diff --git a/hardware/board/component/brd4111a.slcc b/hardware/board/component/brd4111a.slcc deleted file mode 100644 index 6ce7dce110..0000000000 --- a/hardware/board/component/brd4111a.slcc +++ /dev/null @@ -1,55 +0,0 @@ -!!omap -- id: brd4111a -- label: BRD4111A -- package: platform -- description: Board support for BRD4111A. -- category: Platform|Board|Radio Board -- quality: production -- requires: - - name: efr32bg27c320f768gj39 - - name: brd4111a_config - - name: hardware_board_mainboard -- provides: - - name: brd4111a - - name: hardware_board - - name: hardware_board_rb - - name: hardware_board_from_stk - - name: hardware_board_has_vcom - - name: hardware_board_has_spiflash - - name: hardware_board_has_hfxo - - name: hardware_board_has_lfxo - - name: hardware_board_supports_rf_band_2400 - - name: hardware_board_supports_1_rf_band - - name: hardware_board_default_rf_band - - name: hardware_board_default_rf_band_2400 -- recommends: - - id: brd4002a - - id: iostream_eusart - instance: - - vcom - - id: bootloader_uart_driver - - id: simple_button - instance: - - btn0 - - btn1 - - id: mx25_flash_shutdown_eusart - - id: bootloader_spi_controller_usart_driver - - id: bootloader_spi_peripheral_usart_driver -- template_contribution: - - name: board_default_init - value: sl_board_disable_vcom() -- define: - - name: SL_BOARD_NAME - value: '"BRD4111A"' - - name: SL_BOARD_REV - value: '"A00"' -- tag: - - board:pn:BRD4111 - - board:variant:A - - board:revision:A00 - - board:device:efr32bg27c320f768gj39 - - hardware:has:vcom - - hardware:has:pti - - hardware:has:led:0 - - hardware:has:button:2 - - hardware:has:memory:spi:mx25r8035f diff --git a/hardware/board/component/brd4113a.slcc b/hardware/board/component/brd4113a.slcc deleted file mode 100644 index d1b1c0a383..0000000000 --- a/hardware/board/component/brd4113a.slcc +++ /dev/null @@ -1,62 +0,0 @@ -!!omap -- id: brd4113a -- label: BRD4113A -- package: platform -- description: Board support for BRD4113A. -- category: Platform|Board|Radio Board -- quality: production -- requires: - - name: efr32bg27c230f768im32 - - name: brd4113a_config - - name: hardware_board_mainboard -- provides: - - name: brd4113a - - name: hardware_board - - name: hardware_board_rb - - name: hardware_board_from_stk - - name: hardware_board_has_vcom - - name: hardware_board_has_spiflash - - name: hardware_board_has_hfxo - - name: hardware_board_has_lfxo - - name: hardware_board_supports_rf_band_2400 - - name: hardware_board_supports_1_rf_band - - name: hardware_board_default_rf_band - - name: hardware_board_default_rf_band_2400 -- recommends: - - id: brd4002a - - id: iostream_eusart - instance: - - vcom - - id: bootloader_uart_driver - - id: simple_led - instance: - - led0 - - led1 - - id: skrhaae010 - - id: simple_button - instance: - - btn0 - - btn1 - - id: mx25_flash_shutdown_eusart - - id: bootloader_spi_controller_usart_driver - - id: bootloader_spi_peripheral_usart_driver -- template_contribution: - - name: board_default_init - value: sl_board_disable_vcom() -- define: - - name: SL_BOARD_NAME - value: '"BRD4113A"' - - name: SL_BOARD_REV - value: '"A00"' -- tag: - - board:pn:BRD4113 - - board:variant:A - - board:revision:A00 - - board:device:efr32bg27c230f768im32 - - hardware:has:vcom - - hardware:has:pti - - hardware:has:led:2 - - hardware:has:joystick:skrhaae010 - - hardware:has:button:2 - - hardware:has:memory:spi:mx25r8035f - - hardware:shares:button:led diff --git a/hardware/board/component/brd4166c.slcc b/hardware/board/component/brd4166c.slcc new file mode 100644 index 0000000000..6a14dae42a --- /dev/null +++ b/hardware/board/component/brd4166c.slcc @@ -0,0 +1,61 @@ +!!omap +- id: brd4166c +- label: BRD4166C +- package: platform +- description: Board support for BRD4166C. +- category: Platform|Board|Thunderboard +- quality: production +- requires: + - name: efr32mg12p332f1024gl125 + - name: brd4166c_config +- provides: + - name: brd4166c + - name: hardware_board + - name: hardware_board_tb + - name: hardware_board_from_tb + - name: hardware_board_has_si70xx + - name: hardware_board_has_tempsensor + - name: hardware_board_has_vcom + - name: hardware_board_has_spiflash + - name: hardware_board_has_hfxo + - name: hardware_board_has_lfxo + - name: hardware_board_supports_rf_band_2400 + - name: hardware_board_supports_1_rf_band + - name: hardware_board_default_rf_band + - name: hardware_board_default_rf_band_2400 +- recommends: + - id: iostream_usart + instance: + - vcom + - id: bootloader_uart_driver + - id: i2cspm + instance: + - sensor + - id: simple_led + instance: + - led0 + - led1 + - id: simple_button + instance: + - btn0 + - btn1 + - id: mx25_flash_shutdown_usart + - id: bootloader_spi_controller_usart_driver + - id: bootloader_spi_peripheral_usart_driver +- template_contribution: [] +- define: + - name: SL_BOARD_NAME + value: '"BRD4166C"' + - name: SL_BOARD_REV + value: '"A01"' +- tag: + - board:pn:BRD4166 + - board:variant:C + - board:revision:A01 + - board:device:efr32mg12p332f1024gl125 + - hardware:has:vcom + - hardware:has:pti + - hardware:has:sensor:si7021 + - hardware:has:led:2 + - hardware:has:button:2 + - hardware:has:memory:spi:mx25r8035f diff --git a/hardware/board/component/brd4196a_a06.slcc b/hardware/board/component/brd4196a_a06.slcc new file mode 100644 index 0000000000..43c58efb6a --- /dev/null +++ b/hardware/board/component/brd4196a_a06.slcc @@ -0,0 +1,60 @@ +!!omap +- id: brd4196a_a06 +- label: BRD4196A rev A06 +- package: platform +- description: Board support for BRD4196A. +- category: Platform|Board|Radio Board +- quality: production +- requires: + - name: efr32mg21b020f1024im32 + - name: brd4196a_config + - name: hardware_board_mainboard +- provides: + - name: brd4196a_revision + - name: brd4196a_a06 + - name: hardware_board + - name: hardware_board_rb + - name: hardware_board_has_vcom + - name: hardware_board_has_hfxo + - name: hardware_board_has_lfxo + - name: hardware_board_supports_rf_band_2400 + - name: hardware_board_supports_1_rf_band + - name: hardware_board_default_rf_band + - name: hardware_board_default_rf_band_2400 +- recommends: + - id: brd4001a + - id: iostream_usart + instance: + - vcom + - id: bootloader_uart_driver + - id: ls013b7dh03 + - id: memlcd_usart + - id: simple_led + instance: + - led0 + - led1 + - id: skrhaae010 + - id: simple_button + instance: + - btn0 + - btn1 + - id: bootloader_spi_peripheral_usart_driver +- template_contribution: + - name: board_default_init + value: sl_board_disable_vcom() +- define: + - name: SL_BOARD_NAME + value: '"BRD4196A"' + - name: SL_BOARD_REV + value: '"A06"' +- tag: + - board:pn:BRD4196 + - board:variant:A + - board:revision:A06 + - board:device:efr32mg21b020f1024im32 + - hardware:has:vcom + - hardware:has:pti + - hardware:has:display:ls013b7dh03 + - hardware:has:led:2 + - hardware:has:joystick:skrhaae010 + - hardware:has:button:2 diff --git a/hardware/board/component/brd4270b.slcc b/hardware/board/component/brd4270b.slcc index c30e28dbc7..dcecc0cf04 100644 --- a/hardware/board/component/brd4270b.slcc +++ b/hardware/board/component/brd4270b.slcc @@ -14,6 +14,7 @@ - name: hardware_board - name: hardware_board_rb - name: hardware_board_from_stk + - name: hardware_board_from_fg25-pk6011a - name: hardware_board_from_fg25-rb4270b - name: hardware_board_has_vcom - name: hardware_board_has_spiflash @@ -50,11 +51,11 @@ - name: SL_BOARD_NAME value: '"BRD4270B"' - name: SL_BOARD_REV - value: '"A00"' + value: '"A04"' - tag: - board:pn:BRD4270 - board:variant:B - - board:revision:A00 + - board:revision:A04 - board:device:efr32fg25b222f1920im56 - hardware:has:vcom - hardware:has:pti diff --git a/hardware/board/component/brd4271a.slcc b/hardware/board/component/brd4271a.slcc index 9bcb65504f..26d4e94a2f 100644 --- a/hardware/board/component/brd4271a.slcc +++ b/hardware/board/component/brd4271a.slcc @@ -14,6 +14,7 @@ - name: hardware_board - name: hardware_board_rb - name: hardware_board_from_stk + - name: hardware_board_from_fg25-pk6012a - name: hardware_board_from_fg25-rb4271a - name: hardware_board_has_vcom - name: hardware_board_has_spiflash @@ -50,11 +51,11 @@ - name: SL_BOARD_NAME value: '"BRD4271A"' - name: SL_BOARD_REV - value: '"A01"' + value: '"A04"' - tag: - board:pn:BRD4271 - board:variant:A - - board:revision:A01 + - board:revision:A04 - board:device:efr32fg25b222f1920im56 - hardware:has:vcom - hardware:has:pti diff --git a/hardware/board/component/brd4272a.slcc b/hardware/board/component/brd4272a.slcc index 537c691563..023184ae48 100644 --- a/hardware/board/component/brd4272a.slcc +++ b/hardware/board/component/brd4272a.slcc @@ -14,8 +14,6 @@ - name: hardware_board - name: hardware_board_rb - name: hardware_board_from_stk - - name: hardware_board_has_si70xx - - name: hardware_board_has_tempsensor - name: hardware_board_has_vcom - name: hardware_board_has_spiflash - name: hardware_board_has_hfxo @@ -30,9 +28,6 @@ instance: - vcom - id: bootloader_euart_driver - - id: i2cspm - instance: - - sensor - id: ls013b7dh03 - id: memlcd_eusart - id: simple_led @@ -62,7 +57,6 @@ - board:device:efr32fg25b222f1920im56 - hardware:has:vcom - hardware:has:pti - - hardware:has:sensor:si7021 - hardware:has:display:ls013b7dh03 - hardware:has:led:2 - hardware:has:button:2 diff --git a/hardware/board/component/brd4273a.slcc b/hardware/board/component/brd4273a.slcc index 6a3ee1340f..82d30bd8c0 100644 --- a/hardware/board/component/brd4273a.slcc +++ b/hardware/board/component/brd4273a.slcc @@ -51,11 +51,11 @@ - name: SL_BOARD_NAME value: '"BRD4273A"' - name: SL_BOARD_REV - value: '"A03"' + value: '"A05"' - tag: - board:pn:BRD4273 - board:variant:A - - board:revision:A03 + - board:revision:A05 - board:device:efr32fg25b222f1920im56 - hardware:has:vcom - hardware:has:pti diff --git a/hardware/board/component/brd4274a.slcc b/hardware/board/component/brd4274a.slcc new file mode 100644 index 0000000000..84efdfa66b --- /dev/null +++ b/hardware/board/component/brd4274a.slcc @@ -0,0 +1,67 @@ +!!omap +- id: brd4274a +- label: BRD4274A +- package: platform +- description: Board support for BRD4274A. +- category: Platform|Board|Radio Board +- quality: production +- requires: + - name: efr32fg25b222f1920im56 + - name: brd4274a_config + - name: hardware_board_mainboard +- provides: + - name: brd4274a + - name: hardware_board + - name: hardware_board_rb + - name: hardware_board_from_stk + - name: hardware_board_from_fg25-rb4274a + - name: hardware_board_has_vcom + - name: hardware_board_has_spiflash + - name: hardware_board_has_eff + - name: hardware_board_has_hfxo + - name: hardware_board_has_lfxo + - name: hardware_board_supports_rf_band_868 + - name: hardware_board_supports_1_rf_band + - name: hardware_board_default_rf_band + - name: hardware_board_default_rf_band_868 +- recommends: + - id: brd4002a + - id: iostream_eusart + instance: + - vcom + - id: bootloader_euart_driver + - id: ls013b7dh03 + - id: memlcd_eusart + - id: simple_led + instance: + - led0 + - led1 + - id: simple_button + instance: + - btn0 + - btn1 + - id: usb_device_driver_dwc_otg_fs + - id: mx25_flash_shutdown_eusart + - id: bootloader_spi_controller_eusart_driver + - id: bootloader_spi_peripheral_eusart_driver +- template_contribution: + - name: board_default_init + value: sl_board_disable_vcom() +- define: + - name: SL_BOARD_NAME + value: '"BRD4274A"' + - name: SL_BOARD_REV + value: '"A02"' +- tag: + - board:pn:BRD4274 + - board:variant:A + - board:revision:A02 + - board:device:efr32fg25b222f1920im56 + - hardware:has:vcom + - hardware:has:pti + - hardware:has:display:ls013b7dh03 + - hardware:has:led:2 + - hardware:has:button:2 + - hardware:has:usb + - hardware:has:memory:spi:mx25r8035f + - hardware:has:radio:eff diff --git a/hardware/board/component/brd4316a.slcc b/hardware/board/component/brd4316a.slcc index 238bcaa4d0..c4feeaa097 100644 --- a/hardware/board/component/brd4316a.slcc +++ b/hardware/board/component/brd4316a.slcc @@ -53,11 +53,11 @@ - name: SL_BOARD_NAME value: '"BRD4316A"' - name: SL_BOARD_REV - value: '"A01"' + value: '"A02"' - tag: - board:pn:BRD4316 - board:variant:A - - board:revision:A01 + - board:revision:A02 - board:device:mgm240pb22vna - hardware:has:vcom - hardware:has:pti diff --git a/hardware/board/component/brd4317a.slcc b/hardware/board/component/brd4317a.slcc index 3908cbee06..a1dce009ec 100644 --- a/hardware/board/component/brd4317a.slcc +++ b/hardware/board/component/brd4317a.slcc @@ -53,11 +53,11 @@ - name: SL_BOARD_NAME value: '"BRD4317A"' - name: SL_BOARD_REV - value: '"A01"' + value: '"A03"' - tag: - board:pn:BRD4317 - board:variant:A - - board:revision:A01 + - board:revision:A03 - board:device:mgm240pb32vna - hardware:has:vcom - hardware:has:pti diff --git a/hardware/board/component/brd4328a.slcc b/hardware/board/component/brd4328a.slcc index 505ae368ff..7dcf6e6270 100644 --- a/hardware/board/component/brd4328a.slcc +++ b/hardware/board/component/brd4328a.slcc @@ -56,11 +56,11 @@ - name: SL_BOARD_NAME value: '"BRD4328A"' - name: SL_BOARD_REV - value: '"A00"' + value: '"A01"' - tag: - board:pn:BRD4328 - board:variant:A - - board:revision:A00 + - board:revision:A01 - board:device:fgm230sb27hgn - hardware:has:vcom - hardware:has:pti diff --git a/hardware/board/component/fg25-rb4270b.slcc b/hardware/board/component/fg25-rb4270b.slcc index aef8b7aacf..c762b527cd 100644 --- a/hardware/board/component/fg25-rb4270b.slcc +++ b/hardware/board/component/fg25-rb4270b.slcc @@ -14,9 +14,9 @@ - name: SL_KIT_NAME value: '"FG25-RB4270B"' - name: SL_KIT_REV - value: '"A00"' + value: '"A02"' - tag: - kit:opn:FG25-RB4270B - kit:pn:RB4270 - kit:variant:B - - kit:revision:A00 + - kit:revision:A02 diff --git a/hardware/board/component/fg25-rb4271a.slcc b/hardware/board/component/fg25-rb4271a.slcc index 5c1223cef0..a9474b9423 100644 --- a/hardware/board/component/fg25-rb4271a.slcc +++ b/hardware/board/component/fg25-rb4271a.slcc @@ -14,9 +14,9 @@ - name: SL_KIT_NAME value: '"FG25-RB4271A"' - name: SL_KIT_REV - value: '"A00"' + value: '"A01"' - tag: - kit:opn:FG25-RB4271A - kit:pn:RB4271 - kit:variant:A - - kit:revision:A00 + - kit:revision:A01 diff --git a/hardware/board/component/fg25-rb4273a.slcc b/hardware/board/component/fg25-rb4273a.slcc index e4e037a656..4e2e2f5b7d 100644 --- a/hardware/board/component/fg25-rb4273a.slcc +++ b/hardware/board/component/fg25-rb4273a.slcc @@ -14,9 +14,9 @@ - name: SL_KIT_NAME value: '"FG25-RB4273A"' - name: SL_KIT_REV - value: '"A00"' + value: '"A02"' - tag: - kit:opn:FG25-RB4273A - kit:pn:RB4273 - kit:variant:A - - kit:revision:A00 + - kit:revision:A02 diff --git a/hardware/board/component/fg25-rb4274a.slcc b/hardware/board/component/fg25-rb4274a.slcc new file mode 100644 index 0000000000..f61bece989 --- /dev/null +++ b/hardware/board/component/fg25-rb4274a.slcc @@ -0,0 +1,22 @@ +!!omap +- id: fg25_rb4274a +- label: FG25-RB4274A +- package: platform +- description: Kit BSP support for the EFR32FG25+EFF01 863-870 MHz +30 dBm Radio Board. +- category: Platform|Board|Kit|Radio Board +- quality: production +- requires: + - name: hardware_board_from_fg25-rb4274a +- provides: + - name: hardware_kit + - name: hardware_kit_rb +- define: + - name: SL_KIT_NAME + value: '"FG25-RB4274A"' + - name: SL_KIT_REV + value: '"A01"' +- tag: + - kit:opn:FG25-RB4274A + - kit:pn:RB4274 + - kit:variant:A + - kit:revision:A01 diff --git a/hardware/board/component/sltb010a.slcc b/hardware/board/component/sltb010a.slcc index 61ce847c49..a0dc63af42 100644 --- a/hardware/board/component/sltb010a.slcc +++ b/hardware/board/component/sltb010a.slcc @@ -14,9 +14,9 @@ - name: SL_KIT_NAME value: '"SLTB010A"' - name: SL_KIT_REV - value: '"A03"' + value: '"A04"' - tag: - kit:opn:SLTB010A - kit:pn:TB010 - kit:variant:A - - kit:revision:A03 + - kit:revision:A04 diff --git a/hardware/board/component/xg24-ek2703a.slcc b/hardware/board/component/xg24-ek2703a.slcc new file mode 100644 index 0000000000..164a5b898a --- /dev/null +++ b/hardware/board/component/xg24-ek2703a.slcc @@ -0,0 +1,22 @@ +!!omap +- id: xg24_ek2703a +- label: XG24-EK2703A +- package: platform +- description: Kit BSP support for the xG24 Explorer Kit. +- category: Platform|Board|Kit|Explorer Kit +- quality: production +- requires: + - name: hardware_board_from_xg24-ek2703a +- provides: + - name: hardware_kit + - name: hardware_kit_ek +- define: + - name: SL_KIT_NAME + value: '"XG24-EK2703A"' + - name: SL_KIT_REV + value: '"A00"' +- tag: + - kit:opn:xG24-EK2703A + - kit:pn:EK2703 + - kit:variant:A + - kit:revision:A00 diff --git a/hardware/board/component/xgm240-rb4316a.slcc b/hardware/board/component/xgm240-rb4316a.slcc index 80f4823809..c5fb646886 100644 --- a/hardware/board/component/xgm240-rb4316a.slcc +++ b/hardware/board/component/xgm240-rb4316a.slcc @@ -14,9 +14,9 @@ - name: SL_KIT_NAME value: '"XGM240-RB4316A"' - name: SL_KIT_REV - value: '"A01"' + value: '"A03"' - tag: - kit:opn:xGM240-RB4316A - kit:pn:RB4316 - kit:variant:A - - kit:revision:A01 + - kit:revision:A03 diff --git a/hardware/board/component/xgm240-rb4317a.slcc b/hardware/board/component/xgm240-rb4317a.slcc index 0f52ca016b..81f9263537 100644 --- a/hardware/board/component/xgm240-rb4317a.slcc +++ b/hardware/board/component/xgm240-rb4317a.slcc @@ -14,9 +14,9 @@ - name: SL_KIT_NAME value: '"XGM240-RB4317A"' - name: SL_KIT_REV - value: '"A01"' + value: '"A03"' - tag: - kit:opn:xGM240-RB4317A - kit:pn:RB4317 - kit:variant:A - - kit:revision:A01 + - kit:revision:A03 diff --git a/hardware/board/component/zgm230-dk2603a.slcc b/hardware/board/component/zgm230-dk2603a.slcc new file mode 100644 index 0000000000..cf24144d81 --- /dev/null +++ b/hardware/board/component/zgm230-dk2603a.slcc @@ -0,0 +1,22 @@ +!!omap +- id: zgm230_dk2603a +- label: ZGM230-DK2603A +- package: platform +- description: Kit BSP support for the Z-Wave 800 Dev Kit. +- category: Platform|Board|Kit|Development Kit +- quality: production +- requires: + - name: hardware_board_from_zgm230-dk2603a +- provides: + - name: hardware_kit + - name: hardware_kit_dk +- define: + - name: SL_KIT_NAME + value: '"ZGM230-DK2603A"' + - name: SL_KIT_REV + value: '"A01"' +- tag: + - kit:opn:ZGM230-DK2603A + - kit:pn:DK2603 + - kit:variant:A + - kit:revision:A01 diff --git a/hardware/board/config/brd2207a/sl_simple_rgb_pwm_led_inst0_config.h b/hardware/board/config/brd2207a/sl_simple_rgb_pwm_led_inst0_config.h deleted file mode 100644 index 226c7cda9e..0000000000 --- a/hardware/board/config/brd2207a/sl_simple_rgb_pwm_led_inst0_config.h +++ /dev/null @@ -1,87 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_INST0_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_INST0 -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_INST0] -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL TIMER2 -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL_NO 2 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_CHANNEL 0 -// TIMER2 CC0 on PA12 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PORT gpioPortA -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PIN 12 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_LOC 1 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_CHANNEL 2 -// TIMER2 CC2 on PA14 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PORT gpioPortA -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PIN 14 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_LOC 1 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_CHANNEL 1 -// TIMER2 CC1 on PA13 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PORT gpioPortA -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PIN 13 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_LOC 1 - -// [TIMER_SL_SIMPLE_RGB_PWM_LED_INST0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H diff --git a/hardware/board/config/brd2207a/sl_simple_rgb_pwm_led_inst1_config.h b/hardware/board/config/brd2207a/sl_simple_rgb_pwm_led_inst1_config.h deleted file mode 100644 index 698767386a..0000000000 --- a/hardware/board/config/brd2207a/sl_simple_rgb_pwm_led_inst1_config.h +++ /dev/null @@ -1,87 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_INST1_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_INST1_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_INST1_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_INST1_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST1_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST1_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST1_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_INST1 -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_INST1] -#define SL_SIMPLE_RGB_PWM_LED_INST1_PERIPHERAL TIMER1 -#define SL_SIMPLE_RGB_PWM_LED_INST1_PERIPHERAL_NO 1 - -#define SL_SIMPLE_RGB_PWM_LED_INST1_RED_CHANNEL 0 -// TIMER1 CC0 on PD6 -#define SL_SIMPLE_RGB_PWM_LED_INST1_RED_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST1_RED_PIN 6 -#define SL_SIMPLE_RGB_PWM_LED_INST1_RED_LOC 4 - -#define SL_SIMPLE_RGB_PWM_LED_INST1_GREEN_CHANNEL 3 -// TIMER1 CC3 on PF12 -#define SL_SIMPLE_RGB_PWM_LED_INST1_GREEN_PORT gpioPortF -#define SL_SIMPLE_RGB_PWM_LED_INST1_GREEN_PIN 12 -#define SL_SIMPLE_RGB_PWM_LED_INST1_GREEN_LOC 5 - -#define SL_SIMPLE_RGB_PWM_LED_INST1_BLUE_CHANNEL 2 -// TIMER1 CC2 on PE12 -#define SL_SIMPLE_RGB_PWM_LED_INST1_BLUE_PORT gpioPortE -#define SL_SIMPLE_RGB_PWM_LED_INST1_BLUE_PIN 12 -#define SL_SIMPLE_RGB_PWM_LED_INST1_BLUE_LOC 1 - -// [TIMER_SL_SIMPLE_RGB_PWM_LED_INST1]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_INST1_CONFIG_H diff --git a/hardware/board/config/brd2207a/sl_simple_rgb_pwm_led_rgb_led0_config.h b/hardware/board/config/brd2207a/sl_simple_rgb_pwm_led_rgb_led0_config.h new file mode 100644 index 0000000000..e693862df1 --- /dev/null +++ b/hardware/board/config/brd2207a/sl_simple_rgb_pwm_led_rgb_led0_config.h @@ -0,0 +1,87 @@ +/***************************************************************************//** + * @file + * @brief Simple RGB PWM Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple RGB PWM LED Configuration +// PWM frequency [Hz] +// Sets the frequency of the PWM signal +// 0 = Don't care +// Default: 10000 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_FREQUENCY 10000 + +// PWM resolution <2-65536> +// Specifies the PWM (dimming) resolution. I.e. if you want a +// dimming resolution that takes the input values from 0 to 99, +// set this value to 100 +// Default: 256 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RESOLUTION 256 + +// Red LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Green LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Blue LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_RGB_PWM_LED_RGB_LED0 +// $[TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0] +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL TIMER2 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL_NO 2 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_CHANNEL 0 +// TIMER2 CC0 on PA12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PORT gpioPortA +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PIN 12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_LOC 1 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_CHANNEL 2 +// TIMER2 CC2 on PA14 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PORT gpioPortA +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PIN 14 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_LOC 1 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_CHANNEL 1 +// TIMER2 CC1 on PA13 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PORT gpioPortA +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PIN 13 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_LOC 1 + +// [TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H diff --git a/hardware/board/config/brd2207a/sl_simple_rgb_pwm_led_rgb_led1_config.h b/hardware/board/config/brd2207a/sl_simple_rgb_pwm_led_rgb_led1_config.h new file mode 100644 index 0000000000..47ef6ac63f --- /dev/null +++ b/hardware/board/config/brd2207a/sl_simple_rgb_pwm_led_rgb_led1_config.h @@ -0,0 +1,87 @@ +/***************************************************************************//** + * @file + * @brief Simple RGB PWM Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_RGB_PWM_LED_RGB_LED1_CONFIG_H +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED1_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple RGB PWM LED Configuration +// PWM frequency [Hz] +// Sets the frequency of the PWM signal +// 0 = Don't care +// Default: 10000 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED1_FREQUENCY 10000 + +// PWM resolution <2-65536> +// Specifies the PWM (dimming) resolution. I.e. if you want a +// dimming resolution that takes the input values from 0 to 99, +// set this value to 100 +// Default: 256 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED1_RESOLUTION 256 + +// Red LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED1_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Green LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED1_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Blue LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED1_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_RGB_PWM_LED_RGB_LED1 +// $[TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED1] +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED1_PERIPHERAL TIMER1 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED1_PERIPHERAL_NO 1 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED1_RED_CHANNEL 0 +// TIMER1 CC0 on PD6 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED1_RED_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED1_RED_PIN 6 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED1_RED_LOC 4 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED1_GREEN_CHANNEL 3 +// TIMER1 CC3 on PF12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED1_GREEN_PORT gpioPortF +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED1_GREEN_PIN 12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED1_GREEN_LOC 5 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED1_BLUE_CHANNEL 2 +// TIMER1 CC2 on PE12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED1_BLUE_PORT gpioPortE +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED1_BLUE_PIN 12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED1_BLUE_LOC 1 + +// [TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_RGB_PWM_LED_RGB_LED1_CONFIG_H diff --git a/hardware/board/config/brd2601a/sl_simple_rgb_pwm_led_inst0_config.h b/hardware/board/config/brd2601a/sl_simple_rgb_pwm_led_inst0_config.h deleted file mode 100644 index 86f935c369..0000000000 --- a/hardware/board/config/brd2601a/sl_simple_rgb_pwm_led_inst0_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_INST0_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_INST0 -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_INST0] -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL TIMER0 -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL_NO 0 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_CHANNEL 0 -// TIMER0 CC0 on PD02 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PIN 2 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_CHANNEL 1 -// TIMER0 CC1 on PA04 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PORT gpioPortA -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PIN 4 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_CHANNEL 2 -// TIMER0 CC2 on PB00 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PORT gpioPortB -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PIN 0 - -// [TIMER_SL_SIMPLE_RGB_PWM_LED_INST0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H diff --git a/hardware/board/config/brd2601a/sl_simple_rgb_pwm_led_rgb_led0_config.h b/hardware/board/config/brd2601a/sl_simple_rgb_pwm_led_rgb_led0_config.h new file mode 100644 index 0000000000..c4ad32ebd8 --- /dev/null +++ b/hardware/board/config/brd2601a/sl_simple_rgb_pwm_led_rgb_led0_config.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief Simple RGB PWM Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple RGB PWM LED Configuration +// PWM frequency [Hz] +// Sets the frequency of the PWM signal +// 0 = Don't care +// Default: 10000 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_FREQUENCY 10000 + +// PWM resolution <2-65536> +// Specifies the PWM (dimming) resolution. I.e. if you want a +// dimming resolution that takes the input values from 0 to 99, +// set this value to 100 +// Default: 256 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RESOLUTION 256 + +// Red LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Green LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Blue LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_RGB_PWM_LED_RGB_LED0 +// $[TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0] +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL TIMER0 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL_NO 0 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_CHANNEL 0 +// TIMER0 CC0 on PD02 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PIN 2 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_CHANNEL 1 +// TIMER0 CC1 on PA04 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PORT gpioPortA +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PIN 4 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_CHANNEL 2 +// TIMER0 CC2 on PB00 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PIN 0 + +// [TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H diff --git a/hardware/board/config/brd2601b/sl_simple_rgb_pwm_led_inst0_config.h b/hardware/board/config/brd2601b/sl_simple_rgb_pwm_led_inst0_config.h deleted file mode 100644 index 86f935c369..0000000000 --- a/hardware/board/config/brd2601b/sl_simple_rgb_pwm_led_inst0_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_INST0_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_INST0 -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_INST0] -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL TIMER0 -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL_NO 0 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_CHANNEL 0 -// TIMER0 CC0 on PD02 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PIN 2 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_CHANNEL 1 -// TIMER0 CC1 on PA04 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PORT gpioPortA -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PIN 4 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_CHANNEL 2 -// TIMER0 CC2 on PB00 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PORT gpioPortB -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PIN 0 - -// [TIMER_SL_SIMPLE_RGB_PWM_LED_INST0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H diff --git a/hardware/board/config/brd2601b/sl_simple_rgb_pwm_led_rgb_led0_config.h b/hardware/board/config/brd2601b/sl_simple_rgb_pwm_led_rgb_led0_config.h new file mode 100644 index 0000000000..c4ad32ebd8 --- /dev/null +++ b/hardware/board/config/brd2601b/sl_simple_rgb_pwm_led_rgb_led0_config.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief Simple RGB PWM Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple RGB PWM LED Configuration +// PWM frequency [Hz] +// Sets the frequency of the PWM signal +// 0 = Don't care +// Default: 10000 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_FREQUENCY 10000 + +// PWM resolution <2-65536> +// Specifies the PWM (dimming) resolution. I.e. if you want a +// dimming resolution that takes the input values from 0 to 99, +// set this value to 100 +// Default: 256 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RESOLUTION 256 + +// Red LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Green LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Blue LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_RGB_PWM_LED_RGB_LED0 +// $[TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0] +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL TIMER0 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL_NO 0 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_CHANNEL 0 +// TIMER0 CC0 on PD02 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PIN 2 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_CHANNEL 1 +// TIMER0 CC1 on PA04 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PORT gpioPortA +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PIN 4 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_CHANNEL 2 +// TIMER0 CC2 on PB00 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PIN 0 + +// [TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H diff --git a/hardware/board/config/brd2603a/sl_simple_rgb_pwm_led_inst0_config.h b/hardware/board/config/brd2603a/sl_simple_rgb_pwm_led_inst0_config.h deleted file mode 100644 index 41bf305971..0000000000 --- a/hardware/board/config/brd2603a/sl_simple_rgb_pwm_led_inst0_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_INST0_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_INST0 -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_INST0] -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL TIMER0 -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL_NO 0 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_CHANNEL 0 -// TIMER0 CC0 on PB01 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PORT gpioPortB -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PIN 1 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_CHANNEL 1 -// TIMER0 CC1 on PA00 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PORT gpioPortA -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PIN 0 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_CHANNEL 2 -// TIMER0 CC2 on PC04 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PORT gpioPortC -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PIN 4 - -// [TIMER_SL_SIMPLE_RGB_PWM_LED_INST0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H diff --git a/hardware/board/config/brd2603a/sl_simple_rgb_pwm_led_rgb_led0_config.h b/hardware/board/config/brd2603a/sl_simple_rgb_pwm_led_rgb_led0_config.h new file mode 100644 index 0000000000..e70418ae8c --- /dev/null +++ b/hardware/board/config/brd2603a/sl_simple_rgb_pwm_led_rgb_led0_config.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief Simple RGB PWM Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple RGB PWM LED Configuration +// PWM frequency [Hz] +// Sets the frequency of the PWM signal +// 0 = Don't care +// Default: 10000 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_FREQUENCY 10000 + +// PWM resolution <2-65536> +// Specifies the PWM (dimming) resolution. I.e. if you want a +// dimming resolution that takes the input values from 0 to 99, +// set this value to 100 +// Default: 256 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RESOLUTION 256 + +// Red LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Green LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Blue LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_RGB_PWM_LED_RGB_LED0 +// $[TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0] +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL TIMER0 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL_NO 0 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_CHANNEL 0 +// TIMER0 CC0 on PB01 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PIN 1 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_CHANNEL 1 +// TIMER0 CC1 on PA00 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PORT gpioPortA +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PIN 0 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_CHANNEL 2 +// TIMER0 CC2 on PC04 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PORT gpioPortC +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PIN 4 + +// [TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H diff --git a/hardware/board/config/brd2703a/btl_euart_driver_cfg.h b/hardware/board/config/brd2703a/btl_euart_driver_cfg.h new file mode 100644 index 0000000000..35c91d95f0 --- /dev/null +++ b/hardware/board/config/brd2703a/btl_euart_driver_cfg.h @@ -0,0 +1,86 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader euart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_EUART_DRIVER_CONFIG_H +#define BTL_EUART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_EUART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_EUART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_EUART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_EUART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_EUART +// $[EUSART_SL_SERIAL_EUART] +#define SL_SERIAL_EUART_PERIPHERAL EUSART1 +#define SL_SERIAL_EUART_PERIPHERAL_NO 1 + +// EUSART1 TX on PA05 +#define SL_SERIAL_EUART_TX_PORT gpioPortA +#define SL_SERIAL_EUART_TX_PIN 5 + +// EUSART1 RX on PA06 +#define SL_SERIAL_EUART_RX_PORT gpioPortA +#define SL_SERIAL_EUART_RX_PIN 6 + +// EUSART1 CTS on PA09 +#define SL_SERIAL_EUART_CTS_PORT gpioPortA +#define SL_SERIAL_EUART_CTS_PIN 9 + +// EUSART1 RTS on PA08 +#define SL_SERIAL_EUART_RTS_PORT gpioPortA +#define SL_SERIAL_EUART_RTS_PIN 8 + +// [EUSART_SL_SERIAL_EUART]$ + + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] + +// [GPIO_SL_VCOM_ENABLE]$ + + +// <<< sl:end pin_tool >>> + +#endif // BTL_EUART_DRIVER_CONFIG_H \ No newline at end of file diff --git a/hardware/board/config/brd2703a/btl_gpio_activation_cfg.h b/hardware/board/config/brd2703a/btl_gpio_activation_cfg.h new file mode 100644 index 0000000000..49c820d52b --- /dev/null +++ b/hardware/board/config/brd2703a/btl_gpio_activation_cfg.h @@ -0,0 +1,49 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader GPIO Activation + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_GPIO_ACTIVATION_CONFIG_H +#define BTL_GPIO_ACTIVATION_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Properties of Bootloader Entry + + +// Active state +// Low +// High +// Default: LOW +// Enter firmware upgrade mode if GPIO pin has this state +#define SL_GPIO_ACTIVATION_POLARITY LOW + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BTL_BUTTON + +// $[GPIO_SL_BTL_BUTTON] +#define SL_BTL_BUTTON_PORT gpioPortB +#define SL_BTL_BUTTON_PIN 2 + +// [GPIO_SL_BTL_BUTTON]$ + +// <<< sl:end pin_tool >>> + + +#endif // BTL_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd2703a/btl_uart_driver_cfg.h b/hardware/board/config/brd2703a/btl_uart_driver_cfg.h new file mode 100644 index 0000000000..50194a2714 --- /dev/null +++ b/hardware/board/config/brd2703a/btl_uart_driver_cfg.h @@ -0,0 +1,87 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Uart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_UART_DRIVER_CONFIG_H +#define BTL_UART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_UART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_UART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_UART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_UART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_UART +// $[USART_SL_SERIAL_UART] +#define SL_SERIAL_UART_PERIPHERAL USART0 +#define SL_SERIAL_UART_PERIPHERAL_NO 0 + +// USART0 TX on PA05 +#define SL_SERIAL_UART_TX_PORT gpioPortA +#define SL_SERIAL_UART_TX_PIN 5 + +// USART0 RX on PA06 +#define SL_SERIAL_UART_RX_PORT gpioPortA +#define SL_SERIAL_UART_RX_PIN 6 + +// USART0 CTS on PA09 +#define SL_SERIAL_UART_CTS_PORT gpioPortA +#define SL_SERIAL_UART_CTS_PIN 9 + +// USART0 RTS on PA08 +#define SL_SERIAL_UART_RTS_PORT gpioPortA +#define SL_SERIAL_UART_RTS_PIN 8 + +// [USART_SL_SERIAL_UART]$ + + + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] + +// [GPIO_SL_VCOM_ENABLE]$ + + +// <<< sl:end pin_tool >>> + +#endif // BTL_UART_DRIVER_CONFIG_H \ No newline at end of file diff --git a/hardware/board/config/brd2703a/iot_flash_cfg_mikroe.h b/hardware/board/config/brd2703a/iot_flash_cfg_mikroe.h new file mode 100644 index 0000000000..05868e3e4c --- /dev/null +++ b/hardware/board/config/brd2703a/iot_flash_cfg_mikroe.h @@ -0,0 +1,136 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_MIKROE_H_ +#define _IOT_FLASH_CFG_MIKROE_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_MIKROE_INST_NUM 0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_MIKROE_INST_TYPE 1 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_MIKROE_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_MIKROE_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_MIKROE_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_MIKROE_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_MIKROE_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_MIKROE_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_MIKROE_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_MIKROE_SPI +// $[USART_IOT_FLASH_CFG_MIKROE_SPI] +#define IOT_FLASH_CFG_MIKROE_SPI_PERIPHERAL USART0 +#define IOT_FLASH_CFG_MIKROE_SPI_PERIPHERAL_NO 0 + +// USART0 TX on PC03 +#define IOT_FLASH_CFG_MIKROE_SPI_TX_PORT gpioPortC +#define IOT_FLASH_CFG_MIKROE_SPI_TX_PIN 3 + +// USART0 RX on PC02 +#define IOT_FLASH_CFG_MIKROE_SPI_RX_PORT gpioPortC +#define IOT_FLASH_CFG_MIKROE_SPI_RX_PIN 2 + +// USART0 CLK on PC01 +#define IOT_FLASH_CFG_MIKROE_SPI_CLK_PORT gpioPortC +#define IOT_FLASH_CFG_MIKROE_SPI_CLK_PIN 1 + +// USART0 CS on PC00 +#define IOT_FLASH_CFG_MIKROE_SPI_CS_PORT gpioPortC +#define IOT_FLASH_CFG_MIKROE_SPI_CS_PIN 0 + +// [USART_IOT_FLASH_CFG_MIKROE_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_MIKROE_H_ */ diff --git a/hardware/board/config/brd4109a_brd4001a/iot_flash_cfg_msc.h b/hardware/board/config/brd2703a/iot_flash_cfg_msc.h similarity index 100% rename from hardware/board/config/brd4109a_brd4001a/iot_flash_cfg_msc.h rename to hardware/board/config/brd2703a/iot_flash_cfg_msc.h diff --git a/hardware/board/config/brd2703a/iot_i2c_cfg_mikroe.h b/hardware/board/config/brd2703a/iot_i2c_cfg_mikroe.h new file mode 100644 index 0000000000..536aca824d --- /dev/null +++ b/hardware/board/config/brd2703a/iot_i2c_cfg_mikroe.h @@ -0,0 +1,106 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_MIKROE_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_MIKROE_H_ +#define _IOT_I2C_CFG_MIKROE_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_MIKROE_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_MIKROE_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_MIKROE_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_MIKROE_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_MIKROE_ENABLE +// $[GPIO_IOT_I2C_CFG_MIKROE_ENABLE] + +// [GPIO_IOT_I2C_CFG_MIKROE_ENABLE]$ + +// IOT_I2C_CFG_MIKROE +// $[I2C_IOT_I2C_CFG_MIKROE] +#define IOT_I2C_CFG_MIKROE_PERIPHERAL I2C0 +#define IOT_I2C_CFG_MIKROE_PERIPHERAL_NO 0 + +// I2C0 SCL on PB04 +#define IOT_I2C_CFG_MIKROE_SCL_PORT gpioPortB +#define IOT_I2C_CFG_MIKROE_SCL_PIN 4 + +// I2C0 SDA on PB05 +#define IOT_I2C_CFG_MIKROE_SDA_PORT gpioPortB +#define IOT_I2C_CFG_MIKROE_SDA_PIN 5 + +// [I2C_IOT_I2C_CFG_MIKROE]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_MIKROE_H_ */ diff --git a/hardware/board/config/brd2703a/iot_i2c_cfg_qwiic.h b/hardware/board/config/brd2703a/iot_i2c_cfg_qwiic.h new file mode 100644 index 0000000000..d0df25f784 --- /dev/null +++ b/hardware/board/config/brd2703a/iot_i2c_cfg_qwiic.h @@ -0,0 +1,106 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_QWIIC_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_QWIIC_H_ +#define _IOT_I2C_CFG_QWIIC_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_QWIIC_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_QWIIC_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_QWIIC_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_QWIIC_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_QWIIC_ENABLE +// $[GPIO_IOT_I2C_CFG_QWIIC_ENABLE] + +// [GPIO_IOT_I2C_CFG_QWIIC_ENABLE]$ + +// IOT_I2C_CFG_QWIIC +// $[I2C_IOT_I2C_CFG_QWIIC] +#define IOT_I2C_CFG_QWIIC_PERIPHERAL I2C1 +#define IOT_I2C_CFG_QWIIC_PERIPHERAL_NO 1 + +// I2C1 SCL on PC04 +#define IOT_I2C_CFG_QWIIC_SCL_PORT gpioPortC +#define IOT_I2C_CFG_QWIIC_SCL_PIN 4 + +// I2C1 SDA on PC05 +#define IOT_I2C_CFG_QWIIC_SDA_PORT gpioPortC +#define IOT_I2C_CFG_QWIIC_SDA_PIN 5 + +// [I2C_IOT_I2C_CFG_QWIIC]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_QWIIC_H_ */ diff --git a/hardware/board/config/brd2703a/iot_pwm_cfg_led0.h b/hardware/board/config/brd2703a/iot_pwm_cfg_led0.h new file mode 100644 index 0000000000..725cc6a0b3 --- /dev/null +++ b/hardware/board/config/brd2703a/iot_pwm_cfg_led0.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED0_H_ +#define _IOT_PWM_CFG_LED0_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED0_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED0 +// $[TIMER_IOT_PWM_CFG_LED0] +#define IOT_PWM_CFG_LED0_PERIPHERAL TIMER0 +#define IOT_PWM_CFG_LED0_PERIPHERAL_NO 0 + +// TIMER0 CC0 on PA04 +#define IOT_PWM_CFG_LED0_CC0_PORT gpioPortA +#define IOT_PWM_CFG_LED0_CC0_PIN 4 + + + +// [TIMER_IOT_PWM_CFG_LED0]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED0_H_ */ diff --git a/hardware/board/config/brd2703a/iot_pwm_cfg_led1.h b/hardware/board/config/brd2703a/iot_pwm_cfg_led1.h new file mode 100644 index 0000000000..58412a6665 --- /dev/null +++ b/hardware/board/config/brd2703a/iot_pwm_cfg_led1.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED1_H_ +#define _IOT_PWM_CFG_LED1_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED1_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED1 +// $[TIMER_IOT_PWM_CFG_LED1] +#define IOT_PWM_CFG_LED1_PERIPHERAL TIMER1 +#define IOT_PWM_CFG_LED1_PERIPHERAL_NO 1 + +// TIMER1 CC0 on PA07 +#define IOT_PWM_CFG_LED1_CC0_PORT gpioPortA +#define IOT_PWM_CFG_LED1_CC0_PIN 7 + + + +// [TIMER_IOT_PWM_CFG_LED1]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED1_H_ */ diff --git a/hardware/board/config/brd2703a/iot_pwm_cfg_mikroe.h b/hardware/board/config/brd2703a/iot_pwm_cfg_mikroe.h new file mode 100644 index 0000000000..ca91eb0acc --- /dev/null +++ b/hardware/board/config/brd2703a/iot_pwm_cfg_mikroe.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_MIKROE_H_ +#define _IOT_PWM_CFG_MIKROE_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_MIKROE_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_MIKROE +// $[TIMER_IOT_PWM_CFG_MIKROE] +#define IOT_PWM_CFG_MIKROE_PERIPHERAL TIMER4 +#define IOT_PWM_CFG_MIKROE_PERIPHERAL_NO 4 + +// TIMER4 CC0 on PA00 +#define IOT_PWM_CFG_MIKROE_CC0_PORT gpioPortA +#define IOT_PWM_CFG_MIKROE_CC0_PIN 0 + + + +// [TIMER_IOT_PWM_CFG_MIKROE]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_MIKROE_H_ */ diff --git a/hardware/board/config/brd2703a/iot_spi_cfg_mikroe.h b/hardware/board/config/brd2703a/iot_spi_cfg_mikroe.h new file mode 100644 index 0000000000..d6aaafbbbd --- /dev/null +++ b/hardware/board/config/brd2703a/iot_spi_cfg_mikroe.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file iot_spi_cfg_inst.h + * @brief Common I/O SPI instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_SPI_CFG_MIKROE_H_ +#define _IOT_SPI_CFG_MIKROE_H_ + +/******************************************************************************* + * SPI Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI General Options + +// Instance number +// Instance number used when iot_spi_open() is called. +// Default: 0 +#define IOT_SPI_CFG_MIKROE_INST_NUM 0 + +// Default SPI bitrate +// Default: 1000000 +#define IOT_SPI_CFG_MIKROE_DEFAULT_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_SPI_CFG_MIKROE_DEFAULT_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_SPI_CFG_MIKROE_DEFAULT_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_SPI_CFG_MIKROE_DEFAULT_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_SPI_CFG_MIKROE_DEFAULT_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_SPI_CFG_MIKROE_DEFAULT_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_SPI_CFG_MIKROE_DEFAULT_SLAVE_START_MODE spidrvSlaveStartImmediate + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_SPI_CFG_MIKROE_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_SPI_CFG_MIKROE +// $[USART_IOT_SPI_CFG_MIKROE] +#define IOT_SPI_CFG_MIKROE_PERIPHERAL USART0 +#define IOT_SPI_CFG_MIKROE_PERIPHERAL_NO 0 + +// USART0 TX on PC03 +#define IOT_SPI_CFG_MIKROE_TX_PORT gpioPortC +#define IOT_SPI_CFG_MIKROE_TX_PIN 3 + +// USART0 RX on PC02 +#define IOT_SPI_CFG_MIKROE_RX_PORT gpioPortC +#define IOT_SPI_CFG_MIKROE_RX_PIN 2 + +// USART0 CLK on PC01 +#define IOT_SPI_CFG_MIKROE_CLK_PORT gpioPortC +#define IOT_SPI_CFG_MIKROE_CLK_PIN 1 + +// USART0 CS on PC00 +#define IOT_SPI_CFG_MIKROE_CS_PORT gpioPortC +#define IOT_SPI_CFG_MIKROE_CS_PIN 0 + +// [USART_IOT_SPI_CFG_MIKROE]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_SPI_CFG_MIKROE_H_ */ diff --git a/hardware/board/config/brd2703a/iot_uart_cfg_loopback.h b/hardware/board/config/brd2703a/iot_uart_cfg_loopback.h new file mode 100644 index 0000000000..9172b135c8 --- /dev/null +++ b/hardware/board/config/brd2703a/iot_uart_cfg_loopback.h @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_LOOPBACK_H_ +#define _IOT_UART_CFG_LOOPBACK_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_LOOPBACK_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_LOOPBACK_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_LOOPBACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_LOOPBACK +// $[USART_IOT_UART_CFG_LOOPBACK] +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL USART0 +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL_NO 0 + +// USART0 TX on PA05 +#define IOT_UART_CFG_LOOPBACK_TX_PORT gpioPortA +#define IOT_UART_CFG_LOOPBACK_TX_PIN 5 + +// USART0 RX on PA06 +#define IOT_UART_CFG_LOOPBACK_RX_PORT gpioPortA +#define IOT_UART_CFG_LOOPBACK_RX_PIN 6 + + + +// USART0 RTS on PA08 +#define IOT_UART_CFG_LOOPBACK_RTS_PORT gpioPortA +#define IOT_UART_CFG_LOOPBACK_RTS_PIN 8 + +// USART0 CTS on PA09 +#define IOT_UART_CFG_LOOPBACK_CTS_PORT gpioPortA +#define IOT_UART_CFG_LOOPBACK_CTS_PIN 9 + +// [USART_IOT_UART_CFG_LOOPBACK]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd2703a/iot_uart_cfg_mikroe.h b/hardware/board/config/brd2703a/iot_uart_cfg_mikroe.h new file mode 100644 index 0000000000..5eeb3f33a8 --- /dev/null +++ b/hardware/board/config/brd2703a/iot_uart_cfg_mikroe.h @@ -0,0 +1,126 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_MIKROE_H_ +#define _IOT_UART_CFG_MIKROE_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_MIKROE_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_MIKROE_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_MIKROE_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_MIKROE_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_MIKROE_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_MIKROE_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_MIKROE_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_MIKROE +// $[USART_IOT_UART_CFG_MIKROE] +#define IOT_UART_CFG_MIKROE_PERIPHERAL USART0 +#define IOT_UART_CFG_MIKROE_PERIPHERAL_NO 0 + +// USART0 TX on PD04 +#define IOT_UART_CFG_MIKROE_TX_PORT gpioPortD +#define IOT_UART_CFG_MIKROE_TX_PIN 4 + +// USART0 RX on PD05 +#define IOT_UART_CFG_MIKROE_RX_PORT gpioPortD +#define IOT_UART_CFG_MIKROE_RX_PIN 5 + + + + + +// [USART_IOT_UART_CFG_MIKROE]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_MIKROE_H_ */ diff --git a/hardware/board/config/brd2703a/iot_uart_cfg_vcom.h b/hardware/board/config/brd2703a/iot_uart_cfg_vcom.h new file mode 100644 index 0000000000..6400706395 --- /dev/null +++ b/hardware/board/config/brd2703a/iot_uart_cfg_vcom.h @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_VCOM_H_ +#define _IOT_UART_CFG_VCOM_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_VCOM_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_VCOM_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_VCOM_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_VCOM_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_VCOM_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_VCOM_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_VCOM_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_VCOM +// $[USART_IOT_UART_CFG_VCOM] +#define IOT_UART_CFG_VCOM_PERIPHERAL USART0 +#define IOT_UART_CFG_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA05 +#define IOT_UART_CFG_VCOM_TX_PORT gpioPortA +#define IOT_UART_CFG_VCOM_TX_PIN 5 + +// USART0 RX on PA06 +#define IOT_UART_CFG_VCOM_RX_PORT gpioPortA +#define IOT_UART_CFG_VCOM_RX_PIN 6 + + + +// USART0 RTS on PA08 +#define IOT_UART_CFG_VCOM_RTS_PORT gpioPortA +#define IOT_UART_CFG_VCOM_RTS_PIN 8 + +// USART0 CTS on PA09 +#define IOT_UART_CFG_VCOM_CTS_PORT gpioPortA +#define IOT_UART_CFG_VCOM_CTS_PIN 9 + +// [USART_IOT_UART_CFG_VCOM]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_VCOM_H_ */ diff --git a/hardware/board/config/brd2703a/sl_board_control_config.h b/hardware/board/config/brd2703a/sl_board_control_config.h new file mode 100644 index 0000000000..ad7793aa7e --- /dev/null +++ b/hardware/board/config/brd2703a/sl_board_control_config.h @@ -0,0 +1,42 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/hardware/board/config/brd2703a/sl_cpc_drv_primary_spi_usart_mikroe_config.h b/hardware/board/config/brd2703a/sl_cpc_drv_primary_spi_usart_mikroe_config.h new file mode 100644 index 0000000000..10fb79458e --- /dev/null +++ b/hardware/board/config/brd2703a/sl_cpc_drv_primary_spi_usart_mikroe_config.h @@ -0,0 +1,94 @@ +/***************************************************************************//** + * @file + * @brief CPC SPI Primary driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_SPI_USART_MIKROE_PRIMARY_CONFIG_H +#define SL_CPC_DRV_SPI_USART_MIKROE_PRIMARY_CONFIG_H +#include "spidrv.h" + +// CPC-Primary SPI Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_SPI_MIKROE_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_SPI_MIKROE_TX_QUEUE_SIZE 10 + +// SPI bit rate +// Default: 1000000 +#define SL_CPC_DRV_SPI_MIKROE_BITRATE 1000000 + +// Receive Interrupt Number on Falling Edge +// Default: 0 +#define SL_CPC_DRV_SPI_MIKROE_RX_IRQ_FALLING_EDGE_INT_NO 0 + +// Receive Interrupt Number on Rising Edge +// Default: 1 +#define SL_CPC_DRV_SPI_MIKROE_RX_IRQ_RISING_EDGE_INT_NO 1 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_SPI_MIKROE_RX_IRQ +// $[GPIO_SL_CPC_DRV_SPI_MIKROE_RX_IRQ] +#define SL_CPC_DRV_SPI_MIKROE_RX_IRQ_PORT gpioPortB +#define SL_CPC_DRV_SPI_MIKROE_RX_IRQ_PIN 1 + +// [GPIO_SL_CPC_DRV_SPI_MIKROE_RX_IRQ]$ + +// SL_CPC_DRV_SPI_MIKROE +// $[USART_SL_CPC_DRV_SPI_MIKROE] +#define SL_CPC_DRV_SPI_MIKROE_PERIPHERAL USART0 +#define SL_CPC_DRV_SPI_MIKROE_PERIPHERAL_NO 0 + +// USART0 TX on PC03 +#define SL_CPC_DRV_SPI_MIKROE_TX_PORT gpioPortC +#define SL_CPC_DRV_SPI_MIKROE_TX_PIN 3 + +// USART0 RX on PC02 +#define SL_CPC_DRV_SPI_MIKROE_RX_PORT gpioPortC +#define SL_CPC_DRV_SPI_MIKROE_RX_PIN 2 + +// USART0 CLK on PC01 +#define SL_CPC_DRV_SPI_MIKROE_CLK_PORT gpioPortC +#define SL_CPC_DRV_SPI_MIKROE_CLK_PIN 1 + +// USART0 CS on PC00 +#define SL_CPC_DRV_SPI_MIKROE_CS_PORT gpioPortC +#define SL_CPC_DRV_SPI_MIKROE_CS_PIN 0 + +// [USART_SL_CPC_DRV_SPI_MIKROE]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_SPI_MIKROE_PRIMARY_CONFIG_H */ diff --git a/hardware/board/config/brd2703a/sl_cpc_drv_primary_uart_usart_mikroe_config.h b/hardware/board/config/brd2703a/sl_cpc_drv_primary_uart_usart_mikroe_config.h new file mode 100644 index 0000000000..73c4662bce --- /dev/null +++ b/hardware/board/config/brd2703a/sl_cpc_drv_primary_uart_usart_mikroe_config.h @@ -0,0 +1,70 @@ +/***************************************************************************//** + * @file + * @brief CPC UART PRIMARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_MIKROE_PRIMARY_CONFIG_H +#define SL_CPC_DRV_UART_USART_MIKROE_PRIMARY_CONFIG_H + +// CPC-Primary UART Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_MIKROE_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_MIKROE_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_MIKROE_BAUDRATE 115200 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_MIKROE +// $[USART_SL_CPC_DRV_UART_MIKROE] +#define SL_CPC_DRV_UART_MIKROE_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_MIKROE_PERIPHERAL_NO 0 + +// USART0 TX on PD04 +#define SL_CPC_DRV_UART_MIKROE_TX_PORT gpioPortD +#define SL_CPC_DRV_UART_MIKROE_TX_PIN 4 + +// USART0 RX on PD05 +#define SL_CPC_DRV_UART_MIKROE_RX_PORT gpioPortD +#define SL_CPC_DRV_UART_MIKROE_RX_PIN 5 + +// [USART_SL_CPC_DRV_UART_MIKROE]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_MIKROE_PRIMARY_CONFIG_H */ diff --git a/hardware/board/config/brd4109a_brd4001a/sl_cpc_drv_primary_uart_usart_vcom_config.h b/hardware/board/config/brd2703a/sl_cpc_drv_primary_uart_usart_vcom_config.h similarity index 100% rename from hardware/board/config/brd4109a_brd4001a/sl_cpc_drv_primary_uart_usart_vcom_config.h rename to hardware/board/config/brd2703a/sl_cpc_drv_primary_uart_usart_vcom_config.h diff --git a/hardware/board/config/brd2703a/sl_cpc_drv_secondary_spi_eusart_mikroe_config.h b/hardware/board/config/brd2703a/sl_cpc_drv_secondary_spi_eusart_mikroe_config.h new file mode 100644 index 0000000000..486c94c444 --- /dev/null +++ b/hardware/board/config/brd2703a/sl_cpc_drv_secondary_spi_eusart_mikroe_config.h @@ -0,0 +1,94 @@ +/***************************************************************************//** + * @file + * @brief CPC SPI SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_SPI_EUSART_MIKROE_SECONDARY_CONFIG_H +#define SL_CPC_DRV_SPI_EUSART_MIKROE_SECONDARY_CONFIG_H +#include "spidrv.h" + +// CPC-Secondary SPI Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_SPI_MIKROE_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_SPI_MIKROE_TX_QUEUE_SIZE 10 + +// SPI bit rate +// Default: 1000000 +#define SL_CPC_DRV_SPI_MIKROE_BITRATE 1000000 + +// Chip Select Interrupt Number on Falling Edge +// Default: 10 +#define SL_CPC_DRV_SPI_MIKROE_CS_FALLING_EDGE_INT_NO 0 + +// Chip Select Interrupt Number on Rising Edge +// Default: 11 +#define SL_CPC_DRV_SPI_MIKROE_CS_RISING_EDGE_INT_NO 1 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_SPI_MIKROE_RX_IRQ +// $[GPIO_SL_CPC_DRV_SPI_MIKROE_RX_IRQ] +#define SL_CPC_DRV_SPI_MIKROE_RX_IRQ_PORT gpioPortB +#define SL_CPC_DRV_SPI_MIKROE_RX_IRQ_PIN 1 + +// [GPIO_SL_CPC_DRV_SPI_MIKROE_RX_IRQ]$ + +// SL_CPC_DRV_SPI_MIKROE +// $[EUSART_SL_CPC_DRV_SPI_MIKROE] +#define SL_CPC_DRV_SPI_MIKROE_PERIPHERAL EUSART1 +#define SL_CPC_DRV_SPI_MIKROE_PERIPHERAL_NO 1 + +// EUSART1 TX on PC03 +#define SL_CPC_DRV_SPI_MIKROE_TX_PORT gpioPortC +#define SL_CPC_DRV_SPI_MIKROE_TX_PIN 3 + +// EUSART1 RX on PC02 +#define SL_CPC_DRV_SPI_MIKROE_RX_PORT gpioPortC +#define SL_CPC_DRV_SPI_MIKROE_RX_PIN 2 + +// EUSART1 SCLK on PC01 +#define SL_CPC_DRV_SPI_MIKROE_SCLK_PORT gpioPortC +#define SL_CPC_DRV_SPI_MIKROE_SCLK_PIN 1 + +// EUSART1 CS on PC00 +#define SL_CPC_DRV_SPI_MIKROE_CS_PORT gpioPortC +#define SL_CPC_DRV_SPI_MIKROE_CS_PIN 0 + +// [EUSART_SL_CPC_DRV_SPI_MIKROE]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_SPI_MIKROE_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd2703a/sl_cpc_drv_secondary_spi_usart_mikroe_config.h b/hardware/board/config/brd2703a/sl_cpc_drv_secondary_spi_usart_mikroe_config.h new file mode 100644 index 0000000000..6147b90de0 --- /dev/null +++ b/hardware/board/config/brd2703a/sl_cpc_drv_secondary_spi_usart_mikroe_config.h @@ -0,0 +1,94 @@ +/***************************************************************************//** + * @file + * @brief CPC SPI SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_SPI_USART_MIKROE_SECONDARY_CONFIG_H +#define SL_CPC_DRV_SPI_USART_MIKROE_SECONDARY_CONFIG_H +#include "spidrv.h" + +// CPC-Secondary SPI Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_SPI_MIKROE_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_SPI_MIKROE_TX_QUEUE_SIZE 10 + +// SPI bit rate +// Default: 1000000 +#define SL_CPC_DRV_SPI_MIKROE_BITRATE 1000000 + +// Chip Select Interrupt Number on Falling Edge +// Default: 10 +#define SL_CPC_DRV_SPI_MIKROE_CS_FALLING_EDGE_INT_NO 0 + +// Chip Select Interrupt Number on Rising Edge +// Default: 11 +#define SL_CPC_DRV_SPI_MIKROE_CS_RISING_EDGE_INT_NO 1 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_SPI_MIKROE_RX_IRQ +// $[GPIO_SL_CPC_DRV_SPI_MIKROE_RX_IRQ] +#define SL_CPC_DRV_SPI_MIKROE_RX_IRQ_PORT gpioPortB +#define SL_CPC_DRV_SPI_MIKROE_RX_IRQ_PIN 1 + +// [GPIO_SL_CPC_DRV_SPI_MIKROE_RX_IRQ]$ + +// SL_CPC_DRV_SPI_MIKROE +// $[USART_SL_CPC_DRV_SPI_MIKROE] +#define SL_CPC_DRV_SPI_MIKROE_PERIPHERAL USART0 +#define SL_CPC_DRV_SPI_MIKROE_PERIPHERAL_NO 0 + +// USART0 TX on PC03 +#define SL_CPC_DRV_SPI_MIKROE_TX_PORT gpioPortC +#define SL_CPC_DRV_SPI_MIKROE_TX_PIN 3 + +// USART0 RX on PC02 +#define SL_CPC_DRV_SPI_MIKROE_RX_PORT gpioPortC +#define SL_CPC_DRV_SPI_MIKROE_RX_PIN 2 + +// USART0 CLK on PC01 +#define SL_CPC_DRV_SPI_MIKROE_CLK_PORT gpioPortC +#define SL_CPC_DRV_SPI_MIKROE_CLK_PIN 1 + +// USART0 CS on PC00 +#define SL_CPC_DRV_SPI_MIKROE_CS_PORT gpioPortC +#define SL_CPC_DRV_SPI_MIKROE_CS_PIN 0 + +// [USART_SL_CPC_DRV_SPI_MIKROE]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_SPI_MIKROE_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd2703a/sl_cpc_drv_secondary_uart_eusart_mikroe_config.h b/hardware/board/config/brd2703a/sl_cpc_drv_secondary_uart_eusart_mikroe_config.h new file mode 100644 index 0000000000..0b42be5391 --- /dev/null +++ b/hardware/board/config/brd2703a/sl_cpc_drv_secondary_uart_eusart_mikroe_config.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_MIKROE_SECONDARY_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_MIKROE_SECONDARY_CONFIG_H + +// CPC - Secondary EUSART Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_MIKROE_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_MIKROE_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_MIKROE_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlNone +#define SL_CPC_DRV_UART_MIKROE_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_MIKROE +// $[EUSART_SL_CPC_DRV_UART_MIKROE] +#define SL_CPC_DRV_UART_MIKROE_PERIPHERAL EUSART1 +#define SL_CPC_DRV_UART_MIKROE_PERIPHERAL_NO 1 + +// EUSART1 TX on PD04 +#define SL_CPC_DRV_UART_MIKROE_TX_PORT gpioPortD +#define SL_CPC_DRV_UART_MIKROE_TX_PIN 4 + +// EUSART1 RX on PD05 +#define SL_CPC_DRV_UART_MIKROE_RX_PORT gpioPortD +#define SL_CPC_DRV_UART_MIKROE_RX_PIN 5 + +// EUSART1 CTS on PA09 +#define SL_CPC_DRV_UART_MIKROE_CTS_PORT gpioPortA +#define SL_CPC_DRV_UART_MIKROE_CTS_PIN 9 + +// EUSART1 RTS on PA08 +#define SL_CPC_DRV_UART_MIKROE_RTS_PORT gpioPortA +#define SL_CPC_DRV_UART_MIKROE_RTS_PIN 8 + +// [EUSART_SL_CPC_DRV_UART_MIKROE]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_MIKROE_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd2703a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h b/hardware/board/config/brd2703a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h new file mode 100644 index 0000000000..7a8e267e97 --- /dev/null +++ b/hardware/board/config/brd2703a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_VCOM_SECONDARY_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_VCOM_SECONDARY_CONFIG_H + +// CPC - Secondary EUSART Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlNone +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[EUSART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL EUSART1 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 1 + +// EUSART1 TX on PA05 +#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_TX_PIN 5 + +// EUSART1 RX on PA06 +#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_RX_PIN 6 + +// EUSART1 CTS on PA09 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 9 + +// EUSART1 RTS on PA08 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 8 + +// [EUSART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd2703a/sl_cpc_drv_secondary_uart_usart_mikroe_config.h b/hardware/board/config/brd2703a/sl_cpc_drv_secondary_uart_usart_mikroe_config.h new file mode 100644 index 0000000000..d487a3e44f --- /dev/null +++ b/hardware/board/config/brd2703a/sl_cpc_drv_secondary_uart_usart_mikroe_config.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief CPC UART SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_MIKROE_SECONDARY_CONFIG_H +#define SL_CPC_DRV_UART_USART_MIKROE_SECONDARY_CONFIG_H + +// CPC - Secondary UART Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_MIKROE_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_MIKROE_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_MIKROE_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_MIKROE_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_MIKROE +// $[USART_SL_CPC_DRV_UART_MIKROE] +#define SL_CPC_DRV_UART_MIKROE_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_MIKROE_PERIPHERAL_NO 0 + +// USART0 TX on PD04 +#define SL_CPC_DRV_UART_MIKROE_TX_PORT gpioPortD +#define SL_CPC_DRV_UART_MIKROE_TX_PIN 4 + +// USART0 RX on PD05 +#define SL_CPC_DRV_UART_MIKROE_RX_PORT gpioPortD +#define SL_CPC_DRV_UART_MIKROE_RX_PIN 5 + +// USART0 CTS on PA09 +#define SL_CPC_DRV_UART_MIKROE_CTS_PORT gpioPortA +#define SL_CPC_DRV_UART_MIKROE_CTS_PIN 9 + +// USART0 RTS on PA08 +#define SL_CPC_DRV_UART_MIKROE_RTS_PORT gpioPortA +#define SL_CPC_DRV_UART_MIKROE_RTS_PIN 8 + +// [USART_SL_CPC_DRV_UART_MIKROE]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_MIKROE_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd2703a/sl_cpc_drv_secondary_uart_usart_vcom_config.h b/hardware/board/config/brd2703a/sl_cpc_drv_secondary_uart_usart_vcom_config.h new file mode 100644 index 0000000000..4371ae942d --- /dev/null +++ b/hardware/board/config/brd2703a/sl_cpc_drv_secondary_uart_usart_vcom_config.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief CPC UART SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_VCOM_SECONDARY_CONFIG_H +#define SL_CPC_DRV_UART_USART_VCOM_SECONDARY_CONFIG_H + +// CPC - Secondary UART Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[USART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA05 +#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_TX_PIN 5 + +// USART0 RX on PA06 +#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_RX_PIN 6 + +// USART0 CTS on PA09 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 9 + +// USART0 RTS on PA08 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 8 + +// [USART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd2703a/sl_device_init_lfxo_config.h b/hardware/board/config/brd2703a/sl_device_init_lfxo_config.h new file mode 100644 index 0000000000..93fb41af03 --- /dev/null +++ b/hardware/board/config/brd2703a/sl_device_init_lfxo_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_LFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuLfxoOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuLfxoOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 63 + +// LFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_LFXO_PRECISION 100 + +// Startup Timeout Delay +// +// 2 cycles +// 256 cycles +// 1K cycles +// 2K cycles +// 4K cycles +// 8K cycles +// 16K cycles +// 32K cycles +// Default: cmuLfxoStartupDelay_4KCycles +#define SL_DEVICE_INIT_LFXO_TIMEOUT cmuLfxoStartupDelay_4KCycles +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/hardware/board/config/brd2703a/sl_i2cspm_mikroe_config.h b/hardware/board/config/brd2703a/sl_i2cspm_mikroe_config.h new file mode 100644 index 0000000000..05ae810b6e --- /dev/null +++ b/hardware/board/config/brd2703a/sl_i2cspm_mikroe_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief I2CSPM Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_I2CSPM_MIKROE_CONFIG_H +#define SL_I2CSPM_MIKROE_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu + +// I2CSPM settings + +// Reference clock frequency +// Frequency in Hz of the reference clock. +// Select 0 to use the frequency of the currently selected clock. +// Default: 0 +#define SL_I2CSPM_MIKROE_REFERENCE_CLOCK 0 + +// Speed mode +// <0=> Standard mode (100kbit/s) +// <1=> Fast mode (400kbit/s) +// <2=> Fast mode plus (1Mbit/s) +// Default: 0 +#define SL_I2CSPM_MIKROE_SPEED_MODE 0 +// end I2CSPM config + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_I2CSPM_MIKROE +// $[I2C_SL_I2CSPM_MIKROE] +#define SL_I2CSPM_MIKROE_PERIPHERAL I2C0 +#define SL_I2CSPM_MIKROE_PERIPHERAL_NO 0 + +// I2C0 SCL on PB04 +#define SL_I2CSPM_MIKROE_SCL_PORT gpioPortB +#define SL_I2CSPM_MIKROE_SCL_PIN 4 + +// I2C0 SDA on PB05 +#define SL_I2CSPM_MIKROE_SDA_PORT gpioPortB +#define SL_I2CSPM_MIKROE_SDA_PIN 5 + +// [I2C_SL_I2CSPM_MIKROE]$ +// <<< sl:end pin_tool >>> + +#endif // SL_I2CSPM_MIKROE_CONFIG_H diff --git a/hardware/board/config/brd2703a/sl_i2cspm_qwiic_config.h b/hardware/board/config/brd2703a/sl_i2cspm_qwiic_config.h new file mode 100644 index 0000000000..31ebf3cf9e --- /dev/null +++ b/hardware/board/config/brd2703a/sl_i2cspm_qwiic_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief I2CSPM Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_I2CSPM_QWIIC_CONFIG_H +#define SL_I2CSPM_QWIIC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu + +// I2CSPM settings + +// Reference clock frequency +// Frequency in Hz of the reference clock. +// Select 0 to use the frequency of the currently selected clock. +// Default: 0 +#define SL_I2CSPM_QWIIC_REFERENCE_CLOCK 0 + +// Speed mode +// <0=> Standard mode (100kbit/s) +// <1=> Fast mode (400kbit/s) +// <2=> Fast mode plus (1Mbit/s) +// Default: 0 +#define SL_I2CSPM_QWIIC_SPEED_MODE 0 +// end I2CSPM config + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_I2CSPM_QWIIC +// $[I2C_SL_I2CSPM_QWIIC] +#define SL_I2CSPM_QWIIC_PERIPHERAL I2C1 +#define SL_I2CSPM_QWIIC_PERIPHERAL_NO 1 + +// I2C1 SCL on PC04 +#define SL_I2CSPM_QWIIC_SCL_PORT gpioPortC +#define SL_I2CSPM_QWIIC_SCL_PIN 4 + +// I2C1 SDA on PC05 +#define SL_I2CSPM_QWIIC_SDA_PORT gpioPortC +#define SL_I2CSPM_QWIIC_SDA_PIN 5 + +// [I2C_SL_I2CSPM_QWIIC]$ +// <<< sl:end pin_tool >>> + +#endif // SL_I2CSPM_QWIIC_CONFIG_H diff --git a/hardware/board/config/brd2703a/sl_iostream_eusart_mikroe_config.h b/hardware/board/config/brd2703a/sl_iostream_eusart_mikroe_config.h new file mode 100644 index 0000000000..2878fe4aee --- /dev/null +++ b/hardware/board/config/brd2703a/sl_iostream_eusart_mikroe_config.h @@ -0,0 +1,107 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_MIKROE_CONFIG_H +#define SL_IOSTREAM_EUSART_MIKROE_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_MIKROE_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_MIKROE_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_IOSTREAM_EUSART_MIKROE_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_IOSTREAM_EUSART_MIKROE_STOP_BITS eusartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: eusartHwFlowControlNone +#define SL_IOSTREAM_EUSART_MIKROE_FLOW_CONTROL_TYPE eusartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_MIKROE_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_MIKROE_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_MIKROE_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_MIKROE +// $[EUSART_SL_IOSTREAM_EUSART_MIKROE] +#define SL_IOSTREAM_EUSART_MIKROE_PERIPHERAL EUSART1 +#define SL_IOSTREAM_EUSART_MIKROE_PERIPHERAL_NO 1 + +// EUSART1 TX on PD04 +#define SL_IOSTREAM_EUSART_MIKROE_TX_PORT gpioPortD +#define SL_IOSTREAM_EUSART_MIKROE_TX_PIN 4 + +// EUSART1 RX on PD05 +#define SL_IOSTREAM_EUSART_MIKROE_RX_PORT gpioPortD +#define SL_IOSTREAM_EUSART_MIKROE_RX_PIN 5 + + + +// [EUSART_SL_IOSTREAM_EUSART_MIKROE]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd2703a/sl_iostream_eusart_vcom_config.h b/hardware/board/config/brd2703a/sl_iostream_eusart_vcom_config.h new file mode 100644 index 0000000000..d60c34ffe2 --- /dev/null +++ b/hardware/board/config/brd2703a/sl_iostream_eusart_vcom_config.h @@ -0,0 +1,113 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_VCOM_CONFIG_H +#define SL_IOSTREAM_EUSART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_VCOM_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_IOSTREAM_EUSART_VCOM_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_IOSTREAM_EUSART_VCOM_STOP_BITS eusartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: eusartHwFlowControlNone +#define SL_IOSTREAM_EUSART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_VCOM +// $[EUSART_SL_IOSTREAM_EUSART_VCOM] +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL EUSART1 +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL_NO 1 + +// EUSART1 TX on PA05 +#define SL_IOSTREAM_EUSART_VCOM_TX_PORT gpioPortA +#define SL_IOSTREAM_EUSART_VCOM_TX_PIN 5 + +// EUSART1 RX on PA06 +#define SL_IOSTREAM_EUSART_VCOM_RX_PORT gpioPortA +#define SL_IOSTREAM_EUSART_VCOM_RX_PIN 6 + +// EUSART1 CTS on PA09 +#define SL_IOSTREAM_EUSART_VCOM_CTS_PORT gpioPortA +#define SL_IOSTREAM_EUSART_VCOM_CTS_PIN 9 + +// EUSART1 RTS on PA08 +#define SL_IOSTREAM_EUSART_VCOM_RTS_PORT gpioPortA +#define SL_IOSTREAM_EUSART_VCOM_RTS_PIN 8 + +// [EUSART_SL_IOSTREAM_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd2703a/sl_iostream_usart_mikroe_config.h b/hardware/board/config/brd2703a/sl_iostream_usart_mikroe_config.h new file mode 100644 index 0000000000..89f729c929 --- /dev/null +++ b/hardware/board/config/brd2703a/sl_iostream_usart_mikroe_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_MIKROE_CONFIG_H +#define SL_IOSTREAM_USART_MIKROE_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_MIKROE_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_MIKROE_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_MIKROE_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_MIKROE_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_MIKROE_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_MIKROE_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_MIKROE_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_MIKROE +// $[USART_SL_IOSTREAM_USART_MIKROE] +#define SL_IOSTREAM_USART_MIKROE_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_MIKROE_PERIPHERAL_NO 0 + +// USART0 TX on PD04 +#define SL_IOSTREAM_USART_MIKROE_TX_PORT gpioPortD +#define SL_IOSTREAM_USART_MIKROE_TX_PIN 4 + +// USART0 RX on PD05 +#define SL_IOSTREAM_USART_MIKROE_RX_PORT gpioPortD +#define SL_IOSTREAM_USART_MIKROE_RX_PIN 5 + + + +// [USART_SL_IOSTREAM_USART_MIKROE]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd2703a/sl_iostream_usart_vcom_config.h b/hardware/board/config/brd2703a/sl_iostream_usart_vcom_config.h new file mode 100644 index 0000000000..8772675a58 --- /dev/null +++ b/hardware/board/config/brd2703a/sl_iostream_usart_vcom_config.h @@ -0,0 +1,109 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H +#define SL_IOSTREAM_USART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_VCOM +// $[USART_SL_IOSTREAM_USART_VCOM] +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA05 +#define SL_IOSTREAM_USART_VCOM_TX_PORT gpioPortA +#define SL_IOSTREAM_USART_VCOM_TX_PIN 5 + +// USART0 RX on PA06 +#define SL_IOSTREAM_USART_VCOM_RX_PORT gpioPortA +#define SL_IOSTREAM_USART_VCOM_RX_PIN 6 + +// USART0 CTS on PA09 +#define SL_IOSTREAM_USART_VCOM_CTS_PORT gpioPortA +#define SL_IOSTREAM_USART_VCOM_CTS_PIN 9 + +// USART0 RTS on PA08 +#define SL_IOSTREAM_USART_VCOM_RTS_PORT gpioPortA +#define SL_IOSTREAM_USART_VCOM_RTS_PIN 8 + +// [USART_SL_IOSTREAM_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd2703a/sl_pwm_init_led0_config.h b/hardware/board/config/brd2703a/sl_pwm_init_led0_config.h new file mode 100644 index 0000000000..15d7a5653f --- /dev/null +++ b/hardware/board/config/brd2703a/sl_pwm_init_led0_config.h @@ -0,0 +1,62 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef PWM_INIT_LED0_CONFIG_H +#define PWM_INIT_LED0_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED0_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED0_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED0 +// $[TIMER_SL_PWM_LED0] +#define SL_PWM_LED0_PERIPHERAL TIMER0 +#define SL_PWM_LED0_PERIPHERAL_NO 0 + +#define SL_PWM_LED0_OUTPUT_CHANNEL 0 +// TIMER0 CC0 on PA04 +#define SL_PWM_LED0_OUTPUT_PORT gpioPortA +#define SL_PWM_LED0_OUTPUT_PIN 4 + +// [TIMER_SL_PWM_LED0]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // PWM_INIT_LED0_CONFIG_H diff --git a/hardware/board/config/brd2703a/sl_pwm_init_led1_config.h b/hardware/board/config/brd2703a/sl_pwm_init_led1_config.h new file mode 100644 index 0000000000..f339c4d4e4 --- /dev/null +++ b/hardware/board/config/brd2703a/sl_pwm_init_led1_config.h @@ -0,0 +1,62 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef PWM_INIT_LED1_CONFIG_H +#define PWM_INIT_LED1_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED1_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED1_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED1 +// $[TIMER_SL_PWM_LED1] +#define SL_PWM_LED1_PERIPHERAL TIMER1 +#define SL_PWM_LED1_PERIPHERAL_NO 1 + +#define SL_PWM_LED1_OUTPUT_CHANNEL 0 +// TIMER1 CC0 on PA07 +#define SL_PWM_LED1_OUTPUT_PORT gpioPortA +#define SL_PWM_LED1_OUTPUT_PIN 7 + +// [TIMER_SL_PWM_LED1]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // PWM_INIT_LED1_CONFIG_H diff --git a/hardware/board/config/brd2703a/sl_pwm_init_mikroe_config.h b/hardware/board/config/brd2703a/sl_pwm_init_mikroe_config.h new file mode 100644 index 0000000000..88f255b85b --- /dev/null +++ b/hardware/board/config/brd2703a/sl_pwm_init_mikroe_config.h @@ -0,0 +1,62 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef PWM_INIT_MIKROE_CONFIG_H +#define PWM_INIT_MIKROE_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_MIKROE_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_MIKROE_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_MIKROE +// $[TIMER_SL_PWM_MIKROE] +#define SL_PWM_MIKROE_PERIPHERAL TIMER4 +#define SL_PWM_MIKROE_PERIPHERAL_NO 4 + +#define SL_PWM_MIKROE_OUTPUT_CHANNEL 0 +// TIMER4 CC0 on PA00 +#define SL_PWM_MIKROE_OUTPUT_PORT gpioPortA +#define SL_PWM_MIKROE_OUTPUT_PIN 0 + +// [TIMER_SL_PWM_MIKROE]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // PWM_INIT_MIKROE_CONFIG_H diff --git a/hardware/board/config/brd2703a/sl_rail_util_pa_config.h b/hardware/board/config/brd2703a/sl_rail_util_pa_config.h new file mode 100644 index 0000000000..9667d438c3 --- /dev/null +++ b/hardware/board/config/brd2703a/sl_rail_util_pa_config.h @@ -0,0 +1,81 @@ +/***************************************************************************//** + * @file + * @brief Power Amplifier configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PA_CONFIG_H +#define SL_RAIL_UTIL_PA_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PA configuration + +// Initial PA Power (deci-dBm, 100 = 10.0 dBm) +// Default: 100 +#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 + +// PA Ramp Time (microseconds) +// <0-65535:1> +// Default: 10 +#define SL_RAIL_UTIL_PA_RAMP_TIME_US 10 + +// Milli-volts on PA supply pin (PA_VDD) +// <0-65535:1> +// Default: 3300 +#define SL_RAIL_UTIL_PA_VOLTAGE_MV 3300 + +// 2.4 GHz PA Selection +// Highest Possible +// High Power (chip-specific) +// Low Power +// Disable +// Default: RAIL_TX_POWER_MODE_2P4GIG_HIGHEST +#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HIGHEST + +// Sub-1 GHz PA Selection +// Disable +// Default: RAIL_TX_POWER_MODE_NONE +#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE + +// Header file containing custom PA curves +// Default: "pa_curves_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" + +// Header file containing PA curve types +// Default: "pa_curve_types_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" + +// Enable PA Calibration +// Default: 0 +#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 0 + +// +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/hardware/board/config/brd2703a/sl_rail_util_pti_config.h b/hardware/board/config/brd2703a/sl_rail_util_pti_config.h new file mode 100644 index 0000000000..2034b4c9d7 --- /dev/null +++ b/hardware/board/config/brd2703a/sl_rail_util_pti_config.h @@ -0,0 +1,73 @@ +/***************************************************************************//** + * @file + * @brief Packet Trace Information configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PTI_CONFIG_H +#define SL_RAIL_UTIL_PTI_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PTI Configuration + +// PTI mode +// UART +// UART onewire +// SPI +// Disabled +// Default: RAIL_PTI_MODE_UART +#define SL_RAIL_UTIL_PTI_MODE RAIL_PTI_MODE_UART + +// PTI Baud Rate (Hertz) +// <147800-20000000:1> +// Default: 1600000 +#define SL_RAIL_UTIL_PTI_BAUD_RATE_HZ 1600000 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_RAIL_UTIL_PTI +// $[PTI_SL_RAIL_UTIL_PTI] +#define SL_RAIL_UTIL_PTI_PERIPHERAL PTI + +// PTI DOUT on PC06 +#define SL_RAIL_UTIL_PTI_DOUT_PORT gpioPortC +#define SL_RAIL_UTIL_PTI_DOUT_PIN 6 + +// PTI DFRAME on PC07 +#define SL_RAIL_UTIL_PTI_DFRAME_PORT gpioPortC +#define SL_RAIL_UTIL_PTI_DFRAME_PIN 7 + + +// [PTI_SL_RAIL_UTIL_PTI]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_RAIL_UTIL_PTI_CONFIG_H diff --git a/hardware/board/config/brd2703a/sl_simple_button_btn0_config.h b/hardware/board/config/brd2703a/sl_simple_button_btn0_config.h new file mode 100644 index 0000000000..a76123e610 --- /dev/null +++ b/hardware/board/config/brd2703a/sl_simple_button_btn0_config.h @@ -0,0 +1,45 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver User Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_BTN0_CONFIG_H +#define SL_SIMPLE_BUTTON_BTN0_CONFIG_H + +#include "em_gpio.h" +#include "sl_simple_button.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// +// Interrupt +// Poll and Debounce +// Poll +// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT +#define SL_SIMPLE_BUTTON_BTN0_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_BUTTON_BTN0 +// $[GPIO_SL_SIMPLE_BUTTON_BTN0] +#define SL_SIMPLE_BUTTON_BTN0_PORT gpioPortB +#define SL_SIMPLE_BUTTON_BTN0_PIN 2 + +// [GPIO_SL_SIMPLE_BUTTON_BTN0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_BUTTON_BTN0_CONFIG_H diff --git a/hardware/board/config/brd2703a/sl_simple_button_btn1_config.h b/hardware/board/config/brd2703a/sl_simple_button_btn1_config.h new file mode 100644 index 0000000000..3a02983572 --- /dev/null +++ b/hardware/board/config/brd2703a/sl_simple_button_btn1_config.h @@ -0,0 +1,45 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver User Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_BTN1_CONFIG_H +#define SL_SIMPLE_BUTTON_BTN1_CONFIG_H + +#include "em_gpio.h" +#include "sl_simple_button.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// +// Interrupt +// Poll and Debounce +// Poll +// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT +#define SL_SIMPLE_BUTTON_BTN1_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_BUTTON_BTN1 +// $[GPIO_SL_SIMPLE_BUTTON_BTN1] +#define SL_SIMPLE_BUTTON_BTN1_PORT gpioPortB +#define SL_SIMPLE_BUTTON_BTN1_PIN 3 + +// [GPIO_SL_SIMPLE_BUTTON_BTN1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_BUTTON_BTN1_CONFIG_H diff --git a/hardware/board/config/brd2703a/sl_simple_led_led0_config.h b/hardware/board/config/brd2703a/sl_simple_led_led0_config.h new file mode 100644 index 0000000000..d74cab070d --- /dev/null +++ b/hardware/board/config/brd2703a/sl_simple_led_led0_config.h @@ -0,0 +1,44 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED0_CONFIG_H +#define SL_SIMPLE_LED_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED0_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED0 +// $[GPIO_SL_SIMPLE_LED_LED0] +#define SL_SIMPLE_LED_LED0_PORT gpioPortA +#define SL_SIMPLE_LED_LED0_PIN 4 + +// [GPIO_SL_SIMPLE_LED_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED0_CONFIG_H diff --git a/hardware/board/config/brd2703a/sl_simple_led_led1_config.h b/hardware/board/config/brd2703a/sl_simple_led_led1_config.h new file mode 100644 index 0000000000..af5baea42e --- /dev/null +++ b/hardware/board/config/brd2703a/sl_simple_led_led1_config.h @@ -0,0 +1,44 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED1_CONFIG_H +#define SL_SIMPLE_LED_LED1_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED1_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED1 +// $[GPIO_SL_SIMPLE_LED_LED1] +#define SL_SIMPLE_LED_LED1_PORT gpioPortA +#define SL_SIMPLE_LED_LED1_PIN 7 + +// [GPIO_SL_SIMPLE_LED_LED1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED1_CONFIG_H diff --git a/hardware/board/config/brd2703a/sl_spidrv_eusart_mikroe_config.h b/hardware/board/config/brd2703a/sl_spidrv_eusart_mikroe_config.h new file mode 100644 index 0000000000..7e5ac9a379 --- /dev/null +++ b/hardware/board/config/brd2703a/sl_spidrv_eusart_mikroe_config.h @@ -0,0 +1,89 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_EUSART_MIKROE_CONFIG_H +#define SL_SPIDRV_EUSART_MIKROE_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_EUSART_MIKROE_BITRATE 1000000 + +// SPI frame length <7-16> +// Default: 8 +#define SL_SPIDRV_EUSART_MIKROE_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_EUSART_MIKROE_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_EUSART_MIKROE_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_EUSART_MIKROE_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_EUSART_MIKROE_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_EUSART_MIKROE_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_EUSART_MIKROE +// $[EUSART_SL_SPIDRV_EUSART_MIKROE] +#define SL_SPIDRV_EUSART_MIKROE_PERIPHERAL EUSART1 +#define SL_SPIDRV_EUSART_MIKROE_PERIPHERAL_NO 1 + +// EUSART1 TX on PC03 +#define SL_SPIDRV_EUSART_MIKROE_TX_PORT gpioPortC +#define SL_SPIDRV_EUSART_MIKROE_TX_PIN 3 + +// EUSART1 RX on PC02 +#define SL_SPIDRV_EUSART_MIKROE_RX_PORT gpioPortC +#define SL_SPIDRV_EUSART_MIKROE_RX_PIN 2 + +// EUSART1 SCLK on PC01 +#define SL_SPIDRV_EUSART_MIKROE_SCLK_PORT gpioPortC +#define SL_SPIDRV_EUSART_MIKROE_SCLK_PIN 1 + +// EUSART1 CS on PC00 +#define SL_SPIDRV_EUSART_MIKROE_CS_PORT gpioPortC +#define SL_SPIDRV_EUSART_MIKROE_CS_PIN 0 + +// [EUSART_SL_SPIDRV_EUSART_MIKROE]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EUSART_MIKROE_CONFIG_HEUSART_ diff --git a/hardware/board/config/brd2703a/sl_spidrv_mikroe_config.h b/hardware/board/config/brd2703a/sl_spidrv_mikroe_config.h new file mode 100644 index 0000000000..b0a283eea8 --- /dev/null +++ b/hardware/board/config/brd2703a/sl_spidrv_mikroe_config.h @@ -0,0 +1,89 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_MIKROE_CONFIG_H +#define SL_SPIDRV_MIKROE_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_MIKROE_BITRATE 1000000 + +// SPI frame length <4-16> +// Default: 8 +#define SL_SPIDRV_MIKROE_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_MIKROE_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_MIKROE_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_MIKROE_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_MIKROE_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_MIKROE_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_MIKROE +// $[USART_SL_SPIDRV_MIKROE] +#define SL_SPIDRV_MIKROE_PERIPHERAL USART0 +#define SL_SPIDRV_MIKROE_PERIPHERAL_NO 0 + +// USART0 TX on PC03 +#define SL_SPIDRV_MIKROE_TX_PORT gpioPortC +#define SL_SPIDRV_MIKROE_TX_PIN 3 + +// USART0 RX on PC02 +#define SL_SPIDRV_MIKROE_RX_PORT gpioPortC +#define SL_SPIDRV_MIKROE_RX_PIN 2 + +// USART0 CLK on PC01 +#define SL_SPIDRV_MIKROE_CLK_PORT gpioPortC +#define SL_SPIDRV_MIKROE_CLK_PIN 1 + +// USART0 CS on PC00 +#define SL_SPIDRV_MIKROE_CS_PORT gpioPortC +#define SL_SPIDRV_MIKROE_CS_PIN 0 + +// [USART_SL_SPIDRV_MIKROE]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_MIKROE_CONFIG_H diff --git a/hardware/board/config/brd2703a/sl_spidrv_usart_mikroe_config.h b/hardware/board/config/brd2703a/sl_spidrv_usart_mikroe_config.h new file mode 100644 index 0000000000..6784e27cf2 --- /dev/null +++ b/hardware/board/config/brd2703a/sl_spidrv_usart_mikroe_config.h @@ -0,0 +1,89 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_USART_MIKROE_CONFIG_H +#define SL_SPIDRV_USART_MIKROE_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_USART_MIKROE_BITRATE 1000000 + +// SPI frame length <4-16> +// Default: 8 +#define SL_SPIDRV_USART_MIKROE_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_USART_MIKROE_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_USART_MIKROE_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_USART_MIKROE_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_USART_MIKROE_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_USART_MIKROE_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_USART_MIKROE +// $[USART_SL_SPIDRV_USART_MIKROE] +#define SL_SPIDRV_USART_MIKROE_PERIPHERAL USART0 +#define SL_SPIDRV_USART_MIKROE_PERIPHERAL_NO 0 + +// USART0 TX on PC03 +#define SL_SPIDRV_USART_MIKROE_TX_PORT gpioPortC +#define SL_SPIDRV_USART_MIKROE_TX_PIN 3 + +// USART0 RX on PC02 +#define SL_SPIDRV_USART_MIKROE_RX_PORT gpioPortC +#define SL_SPIDRV_USART_MIKROE_RX_PIN 2 + +// USART0 CLK on PC01 +#define SL_SPIDRV_USART_MIKROE_CLK_PORT gpioPortC +#define SL_SPIDRV_USART_MIKROE_CLK_PIN 1 + +// USART0 CS on PC00 +#define SL_SPIDRV_USART_MIKROE_CS_PORT gpioPortC +#define SL_SPIDRV_USART_MIKROE_CS_PIN 0 + +// [USART_SL_SPIDRV_USART_MIKROE]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_USART_MIKROE_CONFIG_H diff --git a/hardware/board/config/brd2703a/sl_uartdrv_eusart_mikroe_config.h b/hardware/board/config/brd2703a/sl_uartdrv_eusart_mikroe_config.h new file mode 100644 index 0000000000..c908cd307b --- /dev/null +++ b/hardware/board/config/brd2703a/sl_uartdrv_eusart_mikroe_config.h @@ -0,0 +1,100 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_MIKROE_CONFIG_H +#define SL_UARTDRV_EUSART_MIKROE_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_MIKROE_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_MIKROE_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_MIKROE_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_MIKROE_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHw +#define SL_UARTDRV_EUSART_MIKROE_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_MIKROE_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_MIKROE_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_MIKROE_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_MIKROE_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_MIKROE +// $[EUSART_SL_UARTDRV_EUSART_MIKROE] +#define SL_UARTDRV_EUSART_MIKROE_PERIPHERAL EUSART1 +#define SL_UARTDRV_EUSART_MIKROE_PERIPHERAL_NO 1 + +// EUSART1 TX on PD04 +#define SL_UARTDRV_EUSART_MIKROE_TX_PORT gpioPortD +#define SL_UARTDRV_EUSART_MIKROE_TX_PIN 4 + +// EUSART1 RX on PD05 +#define SL_UARTDRV_EUSART_MIKROE_RX_PORT gpioPortD +#define SL_UARTDRV_EUSART_MIKROE_RX_PIN 5 + + + +// [EUSART_SL_UARTDRV_EUSART_MIKROE]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_MIKROE_CONFIG_H diff --git a/hardware/board/config/brd2703a/sl_uartdrv_eusart_vcom_config.h b/hardware/board/config/brd2703a/sl_uartdrv_eusart_vcom_config.h new file mode 100644 index 0000000000..9817ec48d2 --- /dev/null +++ b/hardware/board/config/brd2703a/sl_uartdrv_eusart_vcom_config.h @@ -0,0 +1,106 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_VCOM_CONFIG_H +#define SL_UARTDRV_EUSART_VCOM_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_VCOM_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_VCOM_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_VCOM_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_VCOM_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHw +#define SL_UARTDRV_EUSART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_VCOM_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_VCOM_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_VCOM +// $[EUSART_SL_UARTDRV_EUSART_VCOM] +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL EUSART1 +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL_NO 1 + +// EUSART1 TX on PA05 +#define SL_UARTDRV_EUSART_VCOM_TX_PORT gpioPortA +#define SL_UARTDRV_EUSART_VCOM_TX_PIN 5 + +// EUSART1 RX on PA06 +#define SL_UARTDRV_EUSART_VCOM_RX_PORT gpioPortA +#define SL_UARTDRV_EUSART_VCOM_RX_PIN 6 + +// EUSART1 CTS on PA09 +#define SL_UARTDRV_EUSART_VCOM_CTS_PORT gpioPortA +#define SL_UARTDRV_EUSART_VCOM_CTS_PIN 9 + +// EUSART1 RTS on PA08 +#define SL_UARTDRV_EUSART_VCOM_RTS_PORT gpioPortA +#define SL_UARTDRV_EUSART_VCOM_RTS_PIN 8 + +// [EUSART_SL_UARTDRV_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd2703a/sl_uartdrv_usart_mikroe_config.h b/hardware/board/config/brd2703a/sl_uartdrv_usart_mikroe_config.h new file mode 100644 index 0000000000..8be5129f31 --- /dev/null +++ b/hardware/board/config/brd2703a/sl_uartdrv_usart_mikroe_config.h @@ -0,0 +1,95 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_MIKROE_CONFIG_H +#define SL_UARTDRV_USART_MIKROE_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_MIKROE_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_MIKROE_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_MIKROE_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHw +#define SL_UARTDRV_USART_MIKROE_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_MIKROE_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_MIKROE_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_MIKROE_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_MIKROE_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_MIKROE +// $[USART_SL_UARTDRV_USART_MIKROE] +#define SL_UARTDRV_USART_MIKROE_PERIPHERAL USART0 +#define SL_UARTDRV_USART_MIKROE_PERIPHERAL_NO 0 + +// USART0 TX on PD04 +#define SL_UARTDRV_USART_MIKROE_TX_PORT gpioPortD +#define SL_UARTDRV_USART_MIKROE_TX_PIN 4 + +// USART0 RX on PD05 +#define SL_UARTDRV_USART_MIKROE_RX_PORT gpioPortD +#define SL_UARTDRV_USART_MIKROE_RX_PIN 5 + + + +// [USART_SL_UARTDRV_USART_MIKROE]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_MIKROE_CONFIG_H diff --git a/hardware/board/config/brd2703a/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd2703a/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 0000000000..b349d26ebb --- /dev/null +++ b/hardware/board/config/brd2703a/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,101 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHw +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART0 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA05 +#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_TX_PIN 5 + +// USART0 RX on PA06 +#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_RX_PIN 6 + +// USART0 CTS on PA09 +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_CTS_PIN 9 + +// USART0 RTS on PA08 +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_RTS_PIN 8 + +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4001a/btl_euart_driver_cfg.h b/hardware/board/config/brd4109a_brd4001a/btl_euart_driver_cfg.h deleted file mode 100644 index 26c00dc406..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/btl_euart_driver_cfg.h +++ /dev/null @@ -1,88 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader euart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_EUART_DRIVER_CONFIG_H -#define BTL_EUART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// EUART settings - -// Baud rate -// Default: 115200 -#define SL_SERIAL_EUART_BAUD_RATE 115200 - -// Hardware flow control -// Default: 0 -#define SL_SERIAL_EUART_FLOW_CONTROL 0 -// - -// Receive buffer size -// <0-2048:1> -// Default: 512 [0-2048] -#define SL_DRIVER_EUART_RX_BUFFER_SIZE 512 - -// Transmit buffer size -// <0-2048:1> -// Default: 128 [0-2048] -#define SL_DRIVER_EUART_TX_BUFFER_SIZE 128 - -// Virtual COM Port -// Default: 0 -#define SL_VCOM_ENABLE 0 -// - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_SERIAL_EUART -// $[EUSART_SL_SERIAL_EUART] -#define SL_SERIAL_EUART_PERIPHERAL EUSART0 -#define SL_SERIAL_EUART_PERIPHERAL_NO 0 - -// EUSART0 TX on PA05 -#define SL_SERIAL_EUART_TX_PORT gpioPortA -#define SL_SERIAL_EUART_TX_PIN 5 - -// EUSART0 RX on PA06 -#define SL_SERIAL_EUART_RX_PORT gpioPortA -#define SL_SERIAL_EUART_RX_PIN 6 - -// EUSART0 CTS on PA00 -#define SL_SERIAL_EUART_CTS_PORT gpioPortA -#define SL_SERIAL_EUART_CTS_PIN 0 - -// EUSART0 RTS on PA07 -#define SL_SERIAL_EUART_RTS_PORT gpioPortA -#define SL_SERIAL_EUART_RTS_PIN 7 - -// [EUSART_SL_SERIAL_EUART]$ - - -// SL_VCOM_ENABLE - -// $[GPIO_SL_VCOM_ENABLE] -#define SL_VCOM_ENABLE_PORT gpioPortB -#define SL_VCOM_ENABLE_PIN 4 - -// [GPIO_SL_VCOM_ENABLE]$ - - -// <<< sl:end pin_tool >>> - -#endif // BTL_EUART_DRIVER_CONFIG_H \ No newline at end of file diff --git a/hardware/board/config/brd4109a_brd4001a/btl_ezsp_gpio_activation_cfg.h b/hardware/board/config/brd4109a_brd4001a/btl_ezsp_gpio_activation_cfg.h deleted file mode 100644 index 12c5b0a5eb..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/btl_ezsp_gpio_activation_cfg.h +++ /dev/null @@ -1,52 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader EZSP GPIO Activation - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_EZSP_GPIO_ACTIVATION_CONFIG_H -#define BTL_EZSP_GPIO_ACTIVATION_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Properties of SPI NCP - -// Active state -// Low -// High -// Default: LOW -// Enter firmware upgrade mode if GPIO pin has this state -#define SL_EZSP_GPIO_ACTIVATION_POLARITY LOW - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_EZSPSPI_HOST_INT -// $[GPIO_SL_EZSPSPI_HOST_INT] -#define SL_EZSPSPI_HOST_INT_PORT gpioPortB -#define SL_EZSPSPI_HOST_INT_PIN 0 - -// [GPIO_SL_EZSPSPI_HOST_INT]$ - -// SL_EZSPSPI_WAKE_INT -// $[GPIO_SL_EZSPSPI_WAKE_INT] -#define SL_EZSPSPI_WAKE_INT_PORT gpioPortB -#define SL_EZSPSPI_WAKE_INT_PIN 1 - -// [GPIO_SL_EZSPSPI_WAKE_INT]$ - -// <<< sl:end pin_tool >>> - -#endif // BTL_EZSP_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4001a/btl_spi_controller_eusart_driver_cfg.h b/hardware/board/config/brd4109a_brd4001a/btl_spi_controller_eusart_driver_cfg.h deleted file mode 100644 index 9176ef3c3c..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/btl_spi_controller_eusart_driver_cfg.h +++ /dev/null @@ -1,68 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader Spi Controller Eusart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H -#define BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// SPI Controller EUSART Driver - -// Frequency -// Default: 6400000 -#define SL_EUSART_EXTFLASH_FREQUENCY 6400000 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_EUSART_EXTFLASH -// $[EUSART_SL_EUSART_EXTFLASH] -#define SL_EUSART_EXTFLASH_PERIPHERAL EUSART0 -#define SL_EUSART_EXTFLASH_PERIPHERAL_NO 0 - -// EUSART0 TX on PC00 -#define SL_EUSART_EXTFLASH_TX_PORT gpioPortC -#define SL_EUSART_EXTFLASH_TX_PIN 0 - -// EUSART0 RX on PC01 -#define SL_EUSART_EXTFLASH_RX_PORT gpioPortC -#define SL_EUSART_EXTFLASH_RX_PIN 1 - -// EUSART0 SCLK on PC02 -#define SL_EUSART_EXTFLASH_SCLK_PORT gpioPortC -#define SL_EUSART_EXTFLASH_SCLK_PIN 2 - -// EUSART0 CS on PA04 -#define SL_EUSART_EXTFLASH_CS_PORT gpioPortA -#define SL_EUSART_EXTFLASH_CS_PIN 4 - -// [EUSART_SL_EUSART_EXTFLASH]$ - -// SL_EXTFLASH_WP -// $[GPIO_SL_EXTFLASH_WP] - -// [GPIO_SL_EXTFLASH_WP]$ - -// SL_EXTFLASH_HOLD -// $[GPIO_SL_EXTFLASH_HOLD] - -// [GPIO_SL_EXTFLASH_HOLD]$ - -// <<< sl:end pin_tool >>> - -#endif // BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4001a/btl_spi_controller_usart_driver_cfg.h b/hardware/board/config/brd4109a_brd4001a/btl_spi_controller_usart_driver_cfg.h deleted file mode 100644 index ac3bd96c27..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/btl_spi_controller_usart_driver_cfg.h +++ /dev/null @@ -1,68 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader Spi Controller Usart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H -#define BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// SPI Controller USART Driver - -// Frequency -// Default: 6400000 -#define SL_USART_EXTFLASH_FREQUENCY 6400000 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_USART_EXTFLASH -// $[USART_SL_USART_EXTFLASH] -#define SL_USART_EXTFLASH_PERIPHERAL USART0 -#define SL_USART_EXTFLASH_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define SL_USART_EXTFLASH_TX_PORT gpioPortC -#define SL_USART_EXTFLASH_TX_PIN 0 - -// USART0 RX on PC01 -#define SL_USART_EXTFLASH_RX_PORT gpioPortC -#define SL_USART_EXTFLASH_RX_PIN 1 - -// USART0 CLK on PC02 -#define SL_USART_EXTFLASH_CLK_PORT gpioPortC -#define SL_USART_EXTFLASH_CLK_PIN 2 - -// USART0 CS on PA04 -#define SL_USART_EXTFLASH_CS_PORT gpioPortA -#define SL_USART_EXTFLASH_CS_PIN 4 - -// [USART_SL_USART_EXTFLASH]$ - -// SL_EXTFLASH_WP -// $[GPIO_SL_EXTFLASH_WP] - -// [GPIO_SL_EXTFLASH_WP]$ - -// SL_EXTFLASH_HOLD -// $[GPIO_SL_EXTFLASH_HOLD] - -// [GPIO_SL_EXTFLASH_HOLD]$ - -// <<< sl:end pin_tool >>> - -#endif // BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4001a/btl_spi_peripheral_eusart_driver_cfg.h b/hardware/board/config/brd4109a_brd4001a/btl_spi_peripheral_eusart_driver_cfg.h deleted file mode 100644 index 718b8cf35d..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/btl_spi_peripheral_eusart_driver_cfg.h +++ /dev/null @@ -1,71 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader Spi Peripheral Eusart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H -#define BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// SPI Peripheral Eusart Driver - -// Receive buffer size:[0-2048] <0-2048> -// Default: 300 -#define SL_SPI_PERIPHERAL_EUSART_RX_BUFFER_SIZE 300 - -// Transmit buffer size:[0-2048] <0-2048> -// Default: 50 -#define SL_SPI_PERIPHERAL_EUSART_TX_BUFFER_SIZE 50 - -// LDMA channel for SPI RX:[0-1] <0-1> -// Default: 0 -#define SL_SPI_PERIPHERAL_EUSART_LDMA_RX_CHANNEL 0 - -// LDMA channel for SPI TX:[0-1] <0-1> -// Default: 1 -#define SL_SPI_PERIPHERAL_EUSART_LDMA_TX_CHANNEL 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_EUSART_SPINCP - -// $[EUSART_SL_EUSART_SPINCP] -#define SL_EUSART_SPINCP_PERIPHERAL EUSART0 -#define SL_EUSART_SPINCP_PERIPHERAL_NO 0 - -// EUSART0 TX on PC00 -#define SL_EUSART_SPINCP_TX_PORT gpioPortC -#define SL_EUSART_SPINCP_TX_PIN 0 - -// EUSART0 RX on PC01 -#define SL_EUSART_SPINCP_RX_PORT gpioPortC -#define SL_EUSART_SPINCP_RX_PIN 1 - -// EUSART0 CS on PC03 -#define SL_EUSART_SPINCP_CS_PORT gpioPortC -#define SL_EUSART_SPINCP_CS_PIN 3 - -// EUSART0 SCLK on PC02 -#define SL_EUSART_SPINCP_SCLK_PORT gpioPortC -#define SL_EUSART_SPINCP_SCLK_PIN 2 - -// [EUSART_SL_EUSART_SPINCP]$ - -// <<< sl:end pin_tool >>> - -#endif // BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4001a/btl_spi_peripheral_usart_driver_cfg.h b/hardware/board/config/brd4109a_brd4001a/btl_spi_peripheral_usart_driver_cfg.h deleted file mode 100644 index 2f8916370e..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/btl_spi_peripheral_usart_driver_cfg.h +++ /dev/null @@ -1,71 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader Spi Peripheral Usart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H -#define BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// SPI Peripheral Usart Driver - -// Receive buffer size:[0-2048] <0-2048> -// Default: 300 -#define SL_SPI_PERIPHERAL_USART_RX_BUFFER_SIZE 300 - -// Transmit buffer size:[0-2048] <0-2048> -// Default: 50 -#define SL_SPI_PERIPHERAL_USART_TX_BUFFER_SIZE 50 - -// LDMA channel for SPI RX:[0-1] <0-1> -// Default: 0 -#define SL_SPI_PERIPHERAL_USART_LDMA_RX_CHANNEL 0 - -// LDMA channel for SPI TX:[0-1] <0-1> -// Default: 1 -#define SL_SPI_PERIPHERAL_USART_LDMA_TX_CHANNEL 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_USART_SPINCP - -// $[USART_SL_USART_SPINCP] -#define SL_USART_SPINCP_PERIPHERAL USART0 -#define SL_USART_SPINCP_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define SL_USART_SPINCP_TX_PORT gpioPortC -#define SL_USART_SPINCP_TX_PIN 0 - -// USART0 RX on PC01 -#define SL_USART_SPINCP_RX_PORT gpioPortC -#define SL_USART_SPINCP_RX_PIN 1 - -// USART0 CS on PC03 -#define SL_USART_SPINCP_CS_PORT gpioPortC -#define SL_USART_SPINCP_CS_PIN 3 - -// USART0 CLK on PC02 -#define SL_USART_SPINCP_CLK_PORT gpioPortC -#define SL_USART_SPINCP_CLK_PIN 2 - -// [USART_SL_USART_SPINCP]$ - -// <<< sl:end pin_tool >>> - -#endif // BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4001a/btl_uart_driver_cfg.h b/hardware/board/config/brd4109a_brd4001a/btl_uart_driver_cfg.h deleted file mode 100644 index 5e74316154..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/btl_uart_driver_cfg.h +++ /dev/null @@ -1,89 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader Uart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_UART_DRIVER_CONFIG_H -#define BTL_UART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// USART settings - -// Baud rate -// Default: 115200 -#define SL_SERIAL_UART_BAUD_RATE 115200 - -// Hardware flow control -// Default: 0 -#define SL_SERIAL_UART_FLOW_CONTROL 0 -// - -// Receive buffer size -// <0-2048:1> -// Default: 512 [0-2048] -#define SL_DRIVER_UART_RX_BUFFER_SIZE 512 - -// Transmit buffer size -// <0-2048:1> -// Default: 128 [0-2048] -#define SL_DRIVER_UART_TX_BUFFER_SIZE 128 - -// Virtual COM Port -// Default: 0 -#define SL_VCOM_ENABLE 0 -// - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_SERIAL_UART -// $[USART_SL_SERIAL_UART] -#define SL_SERIAL_UART_PERIPHERAL USART0 -#define SL_SERIAL_UART_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_SERIAL_UART_TX_PORT gpioPortA -#define SL_SERIAL_UART_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_SERIAL_UART_RX_PORT gpioPortA -#define SL_SERIAL_UART_RX_PIN 6 - -// USART0 CTS on PA00 -#define SL_SERIAL_UART_CTS_PORT gpioPortA -#define SL_SERIAL_UART_CTS_PIN 0 - -// USART0 RTS on PA07 -#define SL_SERIAL_UART_RTS_PORT gpioPortA -#define SL_SERIAL_UART_RTS_PIN 7 - -// [USART_SL_SERIAL_UART]$ - - - -// SL_VCOM_ENABLE - -// $[GPIO_SL_VCOM_ENABLE] -#define SL_VCOM_ENABLE_PORT gpioPortB -#define SL_VCOM_ENABLE_PIN 4 - -// [GPIO_SL_VCOM_ENABLE]$ - - -// <<< sl:end pin_tool >>> - -#endif // BTL_UART_DRIVER_CONFIG_H \ No newline at end of file diff --git a/hardware/board/config/brd4109a_brd4001a/iot_flash_cfg_exp.h b/hardware/board/config/brd4109a_brd4001a/iot_flash_cfg_exp.h deleted file mode 100644 index 1ce8020f40..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/iot_flash_cfg_exp.h +++ /dev/null @@ -1,136 +0,0 @@ -/***************************************************************************//** - * @file iot_flash_cfg_inst.h - * @brief Common I/O flash instance configurations. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_FLASH_CFG_EXP_H_ -#define _IOT_FLASH_CFG_EXP_H_ - -/******************************************************************************* - * Flash Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// Flash General Options - -// Instance number -// Instance number used when iot_flash_open() is called. -// Default: 0 -#define IOT_FLASH_CFG_EXP_INST_NUM 0 - -// Instance type -// <0=> Internal Flash (MSC) -// <1=> External Flash (SPI) -// Specify whether this instance is for internal flash (MSC) -// or an external SPI flash. If external, then you need to setup -// SPI configs below. -// Default: 0 -#define IOT_FLASH_CFG_EXP_INST_TYPE 1 - -// - -// SPI Configuration - -// Default SPI bitrate -// Default: 1000000 -#define IOT_FLASH_CFG_EXP_SPI_BITRATE 1000000 - -// Default SPI frame length <4-16> -// Default: 8 -#define IOT_FLASH_CFG_EXP_SPI_FRAME_LENGTH 8 - -// Default SPI master/slave mode -// Master -// Slave -#define IOT_FLASH_CFG_EXP_SPI_TYPE spidrvMaster - -// Default SPI bit order -// LSB transmitted first -// MSB transmitted first -#define IOT_FLASH_CFG_EXP_SPI_BIT_ORDER spidrvBitOrderMsbFirst - -// Default SPI clock mode -// SPI mode 0: CLKPOL=0, CLKPHA=0 -// SPI mode 1: CLKPOL=0, CLKPHA=1 -// SPI mode 2: CLKPOL=1, CLKPHA=0 -// SPI mode 3: CLKPOL=1, CLKPHA=1 -#define IOT_FLASH_CFG_EXP_SPI_CLOCK_MODE spidrvClockMode0 - -// Default SPI CS control scheme -// CS controlled by the SPI driver -// CS controlled by the application -#define IOT_FLASH_CFG_EXP_SPI_CS_CONTROL spidrvCsControlApplication - -// Default SPI transfer scheme -// Transfer starts immediately -// Transfer starts when the bus is idle -#define IOT_FLASH_CFG_EXP_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * EXTERNAL FLASH: H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_FLASH_CFG_EXP_SPI -// $[USART_IOT_FLASH_CFG_EXP_SPI] -#define IOT_FLASH_CFG_EXP_SPI_PERIPHERAL USART0 -#define IOT_FLASH_CFG_EXP_SPI_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define IOT_FLASH_CFG_EXP_SPI_TX_PORT gpioPortC -#define IOT_FLASH_CFG_EXP_SPI_TX_PIN 0 - -// USART0 RX on PC01 -#define IOT_FLASH_CFG_EXP_SPI_RX_PORT gpioPortC -#define IOT_FLASH_CFG_EXP_SPI_RX_PIN 1 - -// USART0 CLK on PC02 -#define IOT_FLASH_CFG_EXP_SPI_CLK_PORT gpioPortC -#define IOT_FLASH_CFG_EXP_SPI_CLK_PIN 2 - -// USART0 CS on PC03 -#define IOT_FLASH_CFG_EXP_SPI_CS_PORT gpioPortC -#define IOT_FLASH_CFG_EXP_SPI_CS_PIN 3 - -// [USART_IOT_FLASH_CFG_EXP_SPI]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_FLASH_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4109a_brd4001a/iot_flash_cfg_spiflash.h b/hardware/board/config/brd4109a_brd4001a/iot_flash_cfg_spiflash.h deleted file mode 100644 index 96eb0c46c5..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/iot_flash_cfg_spiflash.h +++ /dev/null @@ -1,136 +0,0 @@ -/***************************************************************************//** - * @file iot_flash_cfg_inst.h - * @brief Common I/O flash instance configurations. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_FLASH_CFG_SPIFLASH_H_ -#define _IOT_FLASH_CFG_SPIFLASH_H_ - -/******************************************************************************* - * Flash Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// Flash General Options - -// Instance number -// Instance number used when iot_flash_open() is called. -// Default: 0 -#define IOT_FLASH_CFG_SPIFLASH_INST_NUM 0 - -// Instance type -// <0=> Internal Flash (MSC) -// <1=> External Flash (SPI) -// Specify whether this instance is for internal flash (MSC) -// or an external SPI flash. If external, then you need to setup -// SPI configs below. -// Default: 0 -#define IOT_FLASH_CFG_SPIFLASH_INST_TYPE 1 - -// - -// SPI Configuration - -// Default SPI bitrate -// Default: 1000000 -#define IOT_FLASH_CFG_SPIFLASH_SPI_BITRATE 1000000 - -// Default SPI frame length <4-16> -// Default: 8 -#define IOT_FLASH_CFG_SPIFLASH_SPI_FRAME_LENGTH 8 - -// Default SPI master/slave mode -// Master -// Slave -#define IOT_FLASH_CFG_SPIFLASH_SPI_TYPE spidrvMaster - -// Default SPI bit order -// LSB transmitted first -// MSB transmitted first -#define IOT_FLASH_CFG_SPIFLASH_SPI_BIT_ORDER spidrvBitOrderMsbFirst - -// Default SPI clock mode -// SPI mode 0: CLKPOL=0, CLKPHA=0 -// SPI mode 1: CLKPOL=0, CLKPHA=1 -// SPI mode 2: CLKPOL=1, CLKPHA=0 -// SPI mode 3: CLKPOL=1, CLKPHA=1 -#define IOT_FLASH_CFG_SPIFLASH_SPI_CLOCK_MODE spidrvClockMode0 - -// Default SPI CS control scheme -// CS controlled by the SPI driver -// CS controlled by the application -#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_CONTROL spidrvCsControlApplication - -// Default SPI transfer scheme -// Transfer starts immediately -// Transfer starts when the bus is idle -#define IOT_FLASH_CFG_SPIFLASH_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * EXTERNAL FLASH: H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_FLASH_CFG_SPIFLASH_SPI -// $[USART_IOT_FLASH_CFG_SPIFLASH_SPI] -#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL USART0 -#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PORT gpioPortC -#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PIN 0 - -// USART0 RX on PC01 -#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PORT gpioPortC -#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PIN 1 - -// USART0 CLK on PC02 -#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PORT gpioPortC -#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PIN 2 - -// USART0 CS on PA04 -#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PORT gpioPortA -#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PIN 4 - -// [USART_IOT_FLASH_CFG_SPIFLASH_SPI]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_FLASH_CFG_SPIFLASH_H_ */ diff --git a/hardware/board/config/brd4109a_brd4001a/iot_i2c_cfg_exp.h b/hardware/board/config/brd4109a_brd4001a/iot_i2c_cfg_exp.h deleted file mode 100644 index 5e80a7767b..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/iot_i2c_cfg_exp.h +++ /dev/null @@ -1,108 +0,0 @@ -/***************************************************************************//** - * @file IOT_I2C_CFG_EXP_inst.h - * @brief Common I/O I2C instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_I2C_CFG_EXP_H_ -#define _IOT_I2C_CFG_EXP_H_ - -/******************************************************************************* - * I2C Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// I2C General Options - -// Instance number -// Instance number used when iot_i2c_open() is called. -// Default: 0 -#define IOT_I2C_CFG_EXP_INST_NUM 0 - -// Default timeout (in msec) -// Default: 500 -#define IOT_I2C_CFG_EXP_DEFAULT_TIMEOUT 500 - -// Default bus speed -// <100000=> Standard mode -// <400000=> Fast mode -// <1000000=> Fast plus mode -// <3400000=> High speed mode -// Default: 400000 -#define IOT_I2C_CFG_EXP_DEFAULT_FREQ 400000 - -// Accept NACK -// If the driver receives NACK during a transfer, the transfer is halted -// immediately but it is not considered as an error. Instead, the driver -// returns success status (useful for test purposes). -// Default: 0 -#define IOT_I2C_CFG_EXP_ACCEPT_NACK 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> - -// IOT_I2C_CFG_EXP_ENABLE -// $[GPIO_IOT_I2C_CFG_EXP_ENABLE] -#define IOT_I2C_CFG_EXP_ENABLE_PORT gpioPortB -#define IOT_I2C_CFG_EXP_ENABLE_PIN 0 - -// [GPIO_IOT_I2C_CFG_EXP_ENABLE]$ - -// IOT_I2C_CFG_EXP -// $[I2C_IOT_I2C_CFG_EXP] -#define IOT_I2C_CFG_EXP_PERIPHERAL I2C0 -#define IOT_I2C_CFG_EXP_PERIPHERAL_NO 0 - -// I2C0 SCL on PB02 -#define IOT_I2C_CFG_EXP_SCL_PORT gpioPortB -#define IOT_I2C_CFG_EXP_SCL_PIN 2 - -// I2C0 SDA on PB03 -#define IOT_I2C_CFG_EXP_SDA_PORT gpioPortB -#define IOT_I2C_CFG_EXP_SDA_PIN 3 - -// [I2C_IOT_I2C_CFG_EXP]$ - -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_I2C_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4109a_brd4001a/iot_i2c_cfg_test.h b/hardware/board/config/brd4109a_brd4001a/iot_i2c_cfg_test.h deleted file mode 100644 index 86ef507de4..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/iot_i2c_cfg_test.h +++ /dev/null @@ -1,108 +0,0 @@ -/***************************************************************************//** - * @file IOT_I2C_CFG_TEST_inst.h - * @brief Common I/O I2C instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_I2C_CFG_TEST_H_ -#define _IOT_I2C_CFG_TEST_H_ - -/******************************************************************************* - * I2C Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// I2C General Options - -// Instance number -// Instance number used when iot_i2c_open() is called. -// Default: 0 -#define IOT_I2C_CFG_TEST_INST_NUM 0 - -// Default timeout (in msec) -// Default: 500 -#define IOT_I2C_CFG_TEST_DEFAULT_TIMEOUT 500 - -// Default bus speed -// <100000=> Standard mode -// <400000=> Fast mode -// <1000000=> Fast plus mode -// <3400000=> High speed mode -// Default: 400000 -#define IOT_I2C_CFG_TEST_DEFAULT_FREQ 400000 - -// Accept NACK -// If the driver receives NACK during a transfer, the transfer is halted -// immediately but it is not considered as an error. Instead, the driver -// returns success status (useful for test purposes). -// Default: 0 -#define IOT_I2C_CFG_TEST_ACCEPT_NACK 1 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> - -// IOT_I2C_CFG_TEST_ENABLE -// $[GPIO_IOT_I2C_CFG_TEST_ENABLE] -#define IOT_I2C_CFG_TEST_ENABLE_PORT gpioPortB -#define IOT_I2C_CFG_TEST_ENABLE_PIN 0 - -// [GPIO_IOT_I2C_CFG_TEST_ENABLE]$ - -// IOT_I2C_CFG_TEST -// $[I2C_IOT_I2C_CFG_TEST] -#define IOT_I2C_CFG_TEST_PERIPHERAL I2C0 -#define IOT_I2C_CFG_TEST_PERIPHERAL_NO 0 - -// I2C0 SCL on PB02 -#define IOT_I2C_CFG_TEST_SCL_PORT gpioPortB -#define IOT_I2C_CFG_TEST_SCL_PIN 2 - -// I2C0 SDA on PB03 -#define IOT_I2C_CFG_TEST_SDA_PORT gpioPortB -#define IOT_I2C_CFG_TEST_SDA_PIN 3 - -// [I2C_IOT_I2C_CFG_TEST]$ - -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_I2C_CFG_TEST_H_ */ diff --git a/hardware/board/config/brd4109a_brd4001a/iot_pwm_cfg_exp.h b/hardware/board/config/brd4109a_brd4001a/iot_pwm_cfg_exp.h deleted file mode 100644 index 293a6e41d3..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/iot_pwm_cfg_exp.h +++ /dev/null @@ -1,78 +0,0 @@ -/***************************************************************************//** - * @file iot_pwm_cfg_inst.h - * @brief Common I/O PWM instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_PWM_CFG_EXP_H_ -#define _IOT_PWM_CFG_EXP_H_ - -/******************************************************************************* - * PWM Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// PWM General Options - -// Instance number -// Instance number used when iot_pwm_open() is called. -// Default: 0 -#define IOT_PWM_CFG_EXP_INST_NUM 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_PWM_CFG_EXP -// $[TIMER_IOT_PWM_CFG_EXP] -#define IOT_PWM_CFG_EXP_PERIPHERAL TIMER4 -#define IOT_PWM_CFG_EXP_PERIPHERAL_NO 4 - -// TIMER4 CC0 on PB00 -#define IOT_PWM_CFG_EXP_CC0_PORT gpioPortB -#define IOT_PWM_CFG_EXP_CC0_PIN 0 - - - -// [TIMER_IOT_PWM_CFG_EXP]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_PWM_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4109a_brd4001a/iot_pwm_cfg_led0.h b/hardware/board/config/brd4109a_brd4001a/iot_pwm_cfg_led0.h deleted file mode 100644 index 4046cc7328..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/iot_pwm_cfg_led0.h +++ /dev/null @@ -1,78 +0,0 @@ -/***************************************************************************//** - * @file iot_pwm_cfg_inst.h - * @brief Common I/O PWM instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_PWM_CFG_LED0_H_ -#define _IOT_PWM_CFG_LED0_H_ - -/******************************************************************************* - * PWM Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// PWM General Options - -// Instance number -// Instance number used when iot_pwm_open() is called. -// Default: 0 -#define IOT_PWM_CFG_LED0_INST_NUM 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_PWM_CFG_LED0 -// $[TIMER_IOT_PWM_CFG_LED0] -#define IOT_PWM_CFG_LED0_PERIPHERAL TIMER0 -#define IOT_PWM_CFG_LED0_PERIPHERAL_NO 0 - -// TIMER0 CC0 on PB00 -#define IOT_PWM_CFG_LED0_CC0_PORT gpioPortB -#define IOT_PWM_CFG_LED0_CC0_PIN 0 - - - -// [TIMER_IOT_PWM_CFG_LED0]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_PWM_CFG_LED0_H_ */ diff --git a/hardware/board/config/brd4109a_brd4001a/iot_pwm_cfg_led1.h b/hardware/board/config/brd4109a_brd4001a/iot_pwm_cfg_led1.h deleted file mode 100644 index 16ccf4ba71..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/iot_pwm_cfg_led1.h +++ /dev/null @@ -1,78 +0,0 @@ -/***************************************************************************//** - * @file iot_pwm_cfg_inst.h - * @brief Common I/O PWM instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_PWM_CFG_LED1_H_ -#define _IOT_PWM_CFG_LED1_H_ - -/******************************************************************************* - * PWM Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// PWM General Options - -// Instance number -// Instance number used when iot_pwm_open() is called. -// Default: 0 -#define IOT_PWM_CFG_LED1_INST_NUM 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_PWM_CFG_LED1 -// $[TIMER_IOT_PWM_CFG_LED1] -#define IOT_PWM_CFG_LED1_PERIPHERAL TIMER1 -#define IOT_PWM_CFG_LED1_PERIPHERAL_NO 1 - -// TIMER1 CC0 on PB01 -#define IOT_PWM_CFG_LED1_CC0_PORT gpioPortB -#define IOT_PWM_CFG_LED1_CC0_PIN 1 - - - -// [TIMER_IOT_PWM_CFG_LED1]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_PWM_CFG_LED1_H_ */ diff --git a/hardware/board/config/brd4109a_brd4001a/iot_spi_cfg_exp.h b/hardware/board/config/brd4109a_brd4001a/iot_spi_cfg_exp.h deleted file mode 100644 index af0be6c062..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/iot_spi_cfg_exp.h +++ /dev/null @@ -1,128 +0,0 @@ -/***************************************************************************//** - * @file iot_spi_cfg_inst.h - * @brief Common I/O SPI instance configurations. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_SPI_CFG_EXP_H_ -#define _IOT_SPI_CFG_EXP_H_ - -/******************************************************************************* - * SPI Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// SPI General Options - -// Instance number -// Instance number used when iot_spi_open() is called. -// Default: 0 -#define IOT_SPI_CFG_EXP_INST_NUM 0 - -// Default SPI bitrate -// Default: 1000000 -#define IOT_SPI_CFG_EXP_DEFAULT_BITRATE 1000000 - -// Default SPI frame length <4-16> -// Default: 8 -#define IOT_SPI_CFG_EXP_DEFAULT_FRAME_LENGTH 8 - -// Default SPI master/slave mode -// Master -// Slave -#define IOT_SPI_CFG_EXP_DEFAULT_TYPE spidrvMaster - -// Default SPI bit order -// LSB transmitted first -// MSB transmitted first -#define IOT_SPI_CFG_EXP_DEFAULT_BIT_ORDER spidrvBitOrderMsbFirst - -// Default SPI clock mode -// SPI mode 0: CLKPOL=0, CLKPHA=0 -// SPI mode 1: CLKPOL=0, CLKPHA=1 -// SPI mode 2: CLKPOL=1, CLKPHA=0 -// SPI mode 3: CLKPOL=1, CLKPHA=1 -#define IOT_SPI_CFG_EXP_DEFAULT_CLOCK_MODE spidrvClockMode0 - -// Default SPI CS control scheme -// CS controlled by the SPI driver -// CS controlled by the application -#define IOT_SPI_CFG_EXP_DEFAULT_CS_CONTROL spidrvCsControlApplication - -// Default SPI transfer scheme -// Transfer starts immediately -// Transfer starts when the bus is idle -#define IOT_SPI_CFG_EXP_DEFAULT_SLAVE_START_MODE spidrvSlaveStartImmediate - -// Internal Loopback -// Enable USART Internal loopback -// Default: 0 -#define IOT_SPI_CFG_EXP_LOOPBACK 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_SPI_CFG_EXP -// $[USART_IOT_SPI_CFG_EXP] -#define IOT_SPI_CFG_EXP_PERIPHERAL USART0 -#define IOT_SPI_CFG_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define IOT_SPI_CFG_EXP_TX_PORT gpioPortC -#define IOT_SPI_CFG_EXP_TX_PIN 0 - -// USART0 RX on PC01 -#define IOT_SPI_CFG_EXP_RX_PORT gpioPortC -#define IOT_SPI_CFG_EXP_RX_PIN 1 - -// USART0 CLK on PC02 -#define IOT_SPI_CFG_EXP_CLK_PORT gpioPortC -#define IOT_SPI_CFG_EXP_CLK_PIN 2 - -// USART0 CS on PC03 -#define IOT_SPI_CFG_EXP_CS_PORT gpioPortC -#define IOT_SPI_CFG_EXP_CS_PIN 3 - -// [USART_IOT_SPI_CFG_EXP]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_SPI_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4109a_brd4001a/iot_spi_cfg_loopback.h b/hardware/board/config/brd4109a_brd4001a/iot_spi_cfg_loopback.h deleted file mode 100644 index 88a0ff7895..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/iot_spi_cfg_loopback.h +++ /dev/null @@ -1,128 +0,0 @@ -/***************************************************************************//** - * @file iot_spi_cfg_inst.h - * @brief Common I/O SPI instance configurations. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_SPI_CFG_LOOPBACK_H_ -#define _IOT_SPI_CFG_LOOPBACK_H_ - -/******************************************************************************* - * SPI Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// SPI General Options - -// Instance number -// Instance number used when iot_spi_open() is called. -// Default: 0 -#define IOT_SPI_CFG_LOOPBACK_INST_NUM 0 - -// Default SPI bitrate -// Default: 1000000 -#define IOT_SPI_CFG_LOOPBACK_DEFAULT_BITRATE 1000000 - -// Default SPI frame length <4-16> -// Default: 8 -#define IOT_SPI_CFG_LOOPBACK_DEFAULT_FRAME_LENGTH 8 - -// Default SPI master/slave mode -// Master -// Slave -#define IOT_SPI_CFG_LOOPBACK_DEFAULT_TYPE spidrvMaster - -// Default SPI bit order -// LSB transmitted first -// MSB transmitted first -#define IOT_SPI_CFG_LOOPBACK_DEFAULT_BIT_ORDER spidrvBitOrderMsbFirst - -// Default SPI clock mode -// SPI mode 0: CLKPOL=0, CLKPHA=0 -// SPI mode 1: CLKPOL=0, CLKPHA=1 -// SPI mode 2: CLKPOL=1, CLKPHA=0 -// SPI mode 3: CLKPOL=1, CLKPHA=1 -#define IOT_SPI_CFG_LOOPBACK_DEFAULT_CLOCK_MODE spidrvClockMode0 - -// Default SPI CS control scheme -// CS controlled by the SPI driver -// CS controlled by the application -#define IOT_SPI_CFG_LOOPBACK_DEFAULT_CS_CONTROL spidrvCsControlApplication - -// Default SPI transfer scheme -// Transfer starts immediately -// Transfer starts when the bus is idle -#define IOT_SPI_CFG_LOOPBACK_DEFAULT_SLAVE_START_MODE spidrvSlaveStartImmediate - -// Internal Loopback -// Enable USART Internal loopback -// Default: 0 -#define IOT_SPI_CFG_LOOPBACK_LOOPBACK 1 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_SPI_CFG_LOOPBACK -// $[USART_IOT_SPI_CFG_LOOPBACK] -#define IOT_SPI_CFG_LOOPBACK_PERIPHERAL USART0 -#define IOT_SPI_CFG_LOOPBACK_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define IOT_SPI_CFG_LOOPBACK_TX_PORT gpioPortC -#define IOT_SPI_CFG_LOOPBACK_TX_PIN 0 - -// USART0 RX on PC01 -#define IOT_SPI_CFG_LOOPBACK_RX_PORT gpioPortC -#define IOT_SPI_CFG_LOOPBACK_RX_PIN 1 - -// USART0 CLK on PC02 -#define IOT_SPI_CFG_LOOPBACK_CLK_PORT gpioPortC -#define IOT_SPI_CFG_LOOPBACK_CLK_PIN 2 - -// USART0 CS on PC03 -#define IOT_SPI_CFG_LOOPBACK_CS_PORT gpioPortC -#define IOT_SPI_CFG_LOOPBACK_CS_PIN 3 - -// [USART_IOT_SPI_CFG_LOOPBACK]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_SPI_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4109a_brd4001a/iot_uart_cfg_exp.h b/hardware/board/config/brd4109a_brd4001a/iot_uart_cfg_exp.h deleted file mode 100644 index 02f62b7d87..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/iot_uart_cfg_exp.h +++ /dev/null @@ -1,126 +0,0 @@ -/***************************************************************************//** - * @file iot_uart_cfg_inst.h - * @brief Common I/O UART instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_UART_CFG_EXP_H_ -#define _IOT_UART_CFG_EXP_H_ - -/******************************************************************************* - * UART Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// UART General Options - -// Instance number -// Instance number used when iot_uart_open() is called. -// Default: 0 -#define IOT_UART_CFG_EXP_INST_NUM 0 - -// Default baud rate -// Default: 115200 -#define IOT_UART_CFG_EXP_DEFAULT_BAUDRATE 115200 - -// Default number of data bits -// 4 data bits -// 5 data bits -// 6 data bits -// 7 data bits -// 8 data bits -// Default: usartDatabits8 -#define IOT_UART_CFG_EXP_DEFAULT_DATA_BITS usartDatabits8 - -// Default parity mode -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define IOT_UART_CFG_EXP_DEFAULT_PARITY usartNoParity - -// Default number of stop bits -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define IOT_UART_CFG_EXP_DEFAULT_STOP_BITS usartStopbits1 - -// Default hardware flow control -// None -// CTS -// RTS -// CTS/RTS -// Default: usartHwFlowControlNone -#define IOT_UART_CFG_EXP_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone - - -// Internal Loopback -// Enable USART Internal loopback -// Default: 0 -#define IOT_UART_CFG_EXP_LOOPBACK 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_UART_CFG_EXP -// $[USART_IOT_UART_CFG_EXP] -#define IOT_UART_CFG_EXP_PERIPHERAL USART0 -#define IOT_UART_CFG_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define IOT_UART_CFG_EXP_TX_PORT gpioPortA -#define IOT_UART_CFG_EXP_TX_PIN 5 - -// USART0 RX on PA06 -#define IOT_UART_CFG_EXP_RX_PORT gpioPortA -#define IOT_UART_CFG_EXP_RX_PIN 6 - - - - - -// [USART_IOT_UART_CFG_EXP]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_UART_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4109a_brd4001a/iot_uart_cfg_loopback.h b/hardware/board/config/brd4109a_brd4001a/iot_uart_cfg_loopback.h deleted file mode 100644 index 624fa72d23..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/iot_uart_cfg_loopback.h +++ /dev/null @@ -1,132 +0,0 @@ -/***************************************************************************//** - * @file iot_uart_cfg_inst.h - * @brief Common I/O UART instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_UART_CFG_LOOPBACK_H_ -#define _IOT_UART_CFG_LOOPBACK_H_ - -/******************************************************************************* - * UART Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// UART General Options - -// Instance number -// Instance number used when iot_uart_open() is called. -// Default: 0 -#define IOT_UART_CFG_LOOPBACK_INST_NUM 0 - -// Default baud rate -// Default: 115200 -#define IOT_UART_CFG_LOOPBACK_DEFAULT_BAUDRATE 115200 - -// Default number of data bits -// 4 data bits -// 5 data bits -// 6 data bits -// 7 data bits -// 8 data bits -// Default: usartDatabits8 -#define IOT_UART_CFG_LOOPBACK_DEFAULT_DATA_BITS usartDatabits8 - -// Default parity mode -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define IOT_UART_CFG_LOOPBACK_DEFAULT_PARITY usartNoParity - -// Default number of stop bits -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define IOT_UART_CFG_LOOPBACK_DEFAULT_STOP_BITS usartStopbits1 - -// Default hardware flow control -// None -// CTS -// RTS -// CTS/RTS -// Default: usartHwFlowControlNone -#define IOT_UART_CFG_LOOPBACK_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone - - -// Internal Loopback -// Enable USART Internal loopback -// Default: 0 -#define IOT_UART_CFG_LOOPBACK_LOOPBACK 1 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_UART_CFG_LOOPBACK -// $[USART_IOT_UART_CFG_LOOPBACK] -#define IOT_UART_CFG_LOOPBACK_PERIPHERAL USART0 -#define IOT_UART_CFG_LOOPBACK_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define IOT_UART_CFG_LOOPBACK_TX_PORT gpioPortA -#define IOT_UART_CFG_LOOPBACK_TX_PIN 5 - -// USART0 RX on PA06 -#define IOT_UART_CFG_LOOPBACK_RX_PORT gpioPortA -#define IOT_UART_CFG_LOOPBACK_RX_PIN 6 - - - -// USART0 RTS on PA07 -#define IOT_UART_CFG_LOOPBACK_RTS_PORT gpioPortA -#define IOT_UART_CFG_LOOPBACK_RTS_PIN 7 - -// USART0 CTS on PA00 -#define IOT_UART_CFG_LOOPBACK_CTS_PORT gpioPortA -#define IOT_UART_CFG_LOOPBACK_CTS_PIN 0 - -// [USART_IOT_UART_CFG_LOOPBACK]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_UART_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4109a_brd4001a/iot_uart_cfg_vcom.h b/hardware/board/config/brd4109a_brd4001a/iot_uart_cfg_vcom.h deleted file mode 100644 index 2ec40100c2..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/iot_uart_cfg_vcom.h +++ /dev/null @@ -1,132 +0,0 @@ -/***************************************************************************//** - * @file iot_uart_cfg_inst.h - * @brief Common I/O UART instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_UART_CFG_VCOM_H_ -#define _IOT_UART_CFG_VCOM_H_ - -/******************************************************************************* - * UART Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// UART General Options - -// Instance number -// Instance number used when iot_uart_open() is called. -// Default: 0 -#define IOT_UART_CFG_VCOM_INST_NUM 0 - -// Default baud rate -// Default: 115200 -#define IOT_UART_CFG_VCOM_DEFAULT_BAUDRATE 115200 - -// Default number of data bits -// 4 data bits -// 5 data bits -// 6 data bits -// 7 data bits -// 8 data bits -// Default: usartDatabits8 -#define IOT_UART_CFG_VCOM_DEFAULT_DATA_BITS usartDatabits8 - -// Default parity mode -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define IOT_UART_CFG_VCOM_DEFAULT_PARITY usartNoParity - -// Default number of stop bits -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define IOT_UART_CFG_VCOM_DEFAULT_STOP_BITS usartStopbits1 - -// Default hardware flow control -// None -// CTS -// RTS -// CTS/RTS -// Default: usartHwFlowControlNone -#define IOT_UART_CFG_VCOM_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone - - -// Internal Loopback -// Enable USART Internal loopback -// Default: 0 -#define IOT_UART_CFG_VCOM_LOOPBACK 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_UART_CFG_VCOM -// $[USART_IOT_UART_CFG_VCOM] -#define IOT_UART_CFG_VCOM_PERIPHERAL USART0 -#define IOT_UART_CFG_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define IOT_UART_CFG_VCOM_TX_PORT gpioPortA -#define IOT_UART_CFG_VCOM_TX_PIN 5 - -// USART0 RX on PA06 -#define IOT_UART_CFG_VCOM_RX_PORT gpioPortA -#define IOT_UART_CFG_VCOM_RX_PIN 6 - - - -// USART0 RTS on PA07 -#define IOT_UART_CFG_VCOM_RTS_PORT gpioPortA -#define IOT_UART_CFG_VCOM_RTS_PIN 7 - -// USART0 CTS on PA00 -#define IOT_UART_CFG_VCOM_CTS_PORT gpioPortA -#define IOT_UART_CFG_VCOM_CTS_PIN 0 - -// [USART_IOT_UART_CFG_VCOM]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_UART_CFG_VCOM_H_ */ diff --git a/hardware/board/config/brd4109a_brd4001a/legacy_ncp_spi_config.h b/hardware/board/config/brd4109a_brd4001a/legacy_ncp_spi_config.h deleted file mode 100644 index 7a6c182b08..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/legacy_ncp_spi_config.h +++ /dev/null @@ -1,60 +0,0 @@ -/***************************************************************************//** - * @file - * @brief SPIDRV Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef LEGACY_NCP_SPI_CONFIG_H -#define LEGACY_NCP_SPI_CONFIG_H - -// <<< sl:start pin_tool >>> -// LEGACY_NCP_SPI -// $[USART_LEGACY_NCP_SPI] -#define LEGACY_NCP_SPI_PERIPHERAL USART0 -#define LEGACY_NCP_SPI_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define LEGACY_NCP_SPI_TX_PORT gpioPortC -#define LEGACY_NCP_SPI_TX_PIN 0 - -// USART0 RX on PC01 -#define LEGACY_NCP_SPI_RX_PORT gpioPortC -#define LEGACY_NCP_SPI_RX_PIN 1 - -// USART0 CLK on PC02 -#define LEGACY_NCP_SPI_CLK_PORT gpioPortC -#define LEGACY_NCP_SPI_CLK_PIN 2 - -// USART0 CS on PC03 -#define LEGACY_NCP_SPI_CS_PORT gpioPortC -#define LEGACY_NCP_SPI_CS_PIN 3 - -// [USART_LEGACY_NCP_SPI]$ - -// LEGACY_NCP_SPI_HOST_INT -// $[GPIO_LEGACY_NCP_SPI_HOST_INT] -#define LEGACY_NCP_SPI_HOST_INT_PORT gpioPortB -#define LEGACY_NCP_SPI_HOST_INT_PIN 0 - -// [GPIO_LEGACY_NCP_SPI_HOST_INT]$ - -// LEGACY_NCP_SPI_WAKE_INT -// $[GPIO_LEGACY_NCP_SPI_WAKE_INT] -#define LEGACY_NCP_SPI_WAKE_INT_PORT gpioPortB -#define LEGACY_NCP_SPI_WAKE_INT_PIN 1 - -// [GPIO_LEGACY_NCP_SPI_WAKE_INT]$ -// <<< sl:end pin_tool >>> - -#endif // SL_SPIDRV_EXP_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4001a/sl_board_control_config.h b/hardware/board/config/brd4109a_brd4001a/sl_board_control_config.h deleted file mode 100644 index 7912cfea0c..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_board_control_config.h +++ /dev/null @@ -1,76 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Board Control - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_BOARD_CONTROL_CONFIG_H -#define SL_BOARD_CONTROL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Enable Virtual COM UART -// Default: 0 -#define SL_BOARD_ENABLE_VCOM 0 - -// Enable Display -// Default: 0 -#define SL_BOARD_ENABLE_DISPLAY 0 - -// Enable Relative Humidity and Temperature sensor -// Default: 0 -#define SL_BOARD_ENABLE_SENSOR_RHT 0 - -// Disable SPI Flash -// Default: 1 -#define SL_BOARD_DISABLE_MEMORY_SPI 1 - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_BOARD_ENABLE_VCOM -// $[GPIO_SL_BOARD_ENABLE_VCOM] -#define SL_BOARD_ENABLE_VCOM_PORT gpioPortB -#define SL_BOARD_ENABLE_VCOM_PIN 4 -// [GPIO_SL_BOARD_ENABLE_VCOM]$ - -// SL_BOARD_ENABLE_DISPLAY -// $[GPIO_SL_BOARD_ENABLE_DISPLAY] -#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortC -#define SL_BOARD_ENABLE_DISPLAY_PIN 7 -// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ - -// SL_BOARD_ENABLE_SENSOR_RHT -// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] -#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortC -#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 7 -// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4001a/sl_cpc_drv_primary_spi_usart_exp_config.h b/hardware/board/config/brd4109a_brd4001a/sl_cpc_drv_primary_spi_usart_exp_config.h deleted file mode 100644 index 74a78ebdfc..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_cpc_drv_primary_spi_usart_exp_config.h +++ /dev/null @@ -1,94 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC SPI Primary driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_SPI_USART_EXP_PRIMARY_CONFIG_H -#define SL_CPC_DRV_SPI_USART_EXP_PRIMARY_CONFIG_H -#include "spidrv.h" - -// CPC-Primary SPI Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_SPI_EXP_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_SIZE 10 - -// SPI bit rate -// Default: 1000000 -#define SL_CPC_DRV_SPI_EXP_BITRATE 1000000 - -// Receive Interrupt Number on Falling Edge -// Default: 0 -#define SL_CPC_DRV_SPI_EXP_RX_IRQ_FALLING_EDGE_INT_NO 0 - -// Receive Interrupt Number on Rising Edge -// Default: 1 -#define SL_CPC_DRV_SPI_EXP_RX_IRQ_RISING_EDGE_INT_NO 1 -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_SPI_EXP_RX_IRQ -// $[GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ] -#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PORT gpioPortB -#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PIN 0 - -// [GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ]$ - -// SL_CPC_DRV_SPI_EXP -// $[USART_SL_CPC_DRV_SPI_EXP] -#define SL_CPC_DRV_SPI_EXP_PERIPHERAL USART0 -#define SL_CPC_DRV_SPI_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define SL_CPC_DRV_SPI_EXP_TX_PORT gpioPortC -#define SL_CPC_DRV_SPI_EXP_TX_PIN 0 - -// USART0 RX on PC01 -#define SL_CPC_DRV_SPI_EXP_RX_PORT gpioPortC -#define SL_CPC_DRV_SPI_EXP_RX_PIN 1 - -// USART0 CLK on PC02 -#define SL_CPC_DRV_SPI_EXP_CLK_PORT gpioPortC -#define SL_CPC_DRV_SPI_EXP_CLK_PIN 2 - -// USART0 CS on PC03 -#define SL_CPC_DRV_SPI_EXP_CS_PORT gpioPortC -#define SL_CPC_DRV_SPI_EXP_CS_PIN 3 - -// [USART_SL_CPC_DRV_SPI_EXP]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_SPI_EXP_PRIMARY_CONFIG_H */ diff --git a/hardware/board/config/brd4109a_brd4001a/sl_cpc_drv_primary_uart_usart_exp_config.h b/hardware/board/config/brd4109a_brd4001a/sl_cpc_drv_primary_uart_usart_exp_config.h deleted file mode 100644 index 644f8c29c2..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_cpc_drv_primary_uart_usart_exp_config.h +++ /dev/null @@ -1,70 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC UART PRIMARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_USART_EXP_PRIMARY_CONFIG_H -#define SL_CPC_DRV_UART_USART_EXP_PRIMARY_CONFIG_H - -// CPC-Primary UART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 - -// UART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_EXP -// $[USART_SL_CPC_DRV_UART_EXP] -#define SL_CPC_DRV_UART_EXP_PERIPHERAL USART0 -#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define SL_CPC_DRV_UART_EXP_TX_PORT gpioPortC -#define SL_CPC_DRV_UART_EXP_TX_PIN 0 - -// USART0 RX on PC01 -#define SL_CPC_DRV_UART_EXP_RX_PORT gpioPortC -#define SL_CPC_DRV_UART_EXP_RX_PIN 1 - -// [USART_SL_CPC_DRV_UART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_EXP_PRIMARY_CONFIG_H */ diff --git a/hardware/board/config/brd4109a_brd4001a/sl_cpc_drv_secondary_spi_eusart_exp_config.h b/hardware/board/config/brd4109a_brd4001a/sl_cpc_drv_secondary_spi_eusart_exp_config.h deleted file mode 100644 index b1b1427dfc..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_cpc_drv_secondary_spi_eusart_exp_config.h +++ /dev/null @@ -1,94 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC SPI SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_SPI_EUSART_EXP_SECONDARY_CONFIG_H -#define SL_CPC_DRV_SPI_EUSART_EXP_SECONDARY_CONFIG_H -#include "spidrv.h" - -// CPC-Secondary SPI Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_SPI_EXP_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_SIZE 10 - -// SPI bit rate -// Default: 1000000 -#define SL_CPC_DRV_SPI_EXP_BITRATE 1000000 - -// Chip Select Interrupt Number on Falling Edge -// Default: 10 -#define SL_CPC_DRV_SPI_EXP_CS_FALLING_EDGE_INT_NO 0 - -// Chip Select Interrupt Number on Rising Edge -// Default: 11 -#define SL_CPC_DRV_SPI_EXP_CS_RISING_EDGE_INT_NO 1 -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_SPI_EXP_RX_IRQ -// $[GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ] -#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PORT gpioPortB -#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PIN 0 - -// [GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ]$ - -// SL_CPC_DRV_SPI_EXP -// $[EUSART_SL_CPC_DRV_SPI_EXP] -#define SL_CPC_DRV_SPI_EXP_PERIPHERAL EUSART0 -#define SL_CPC_DRV_SPI_EXP_PERIPHERAL_NO 0 - -// EUSART0 TX on PC00 -#define SL_CPC_DRV_SPI_EXP_TX_PORT gpioPortC -#define SL_CPC_DRV_SPI_EXP_TX_PIN 0 - -// EUSART0 RX on PC01 -#define SL_CPC_DRV_SPI_EXP_RX_PORT gpioPortC -#define SL_CPC_DRV_SPI_EXP_RX_PIN 1 - -// EUSART0 SCLK on PC02 -#define SL_CPC_DRV_SPI_EXP_SCLK_PORT gpioPortC -#define SL_CPC_DRV_SPI_EXP_SCLK_PIN 2 - -// EUSART0 CS on PC03 -#define SL_CPC_DRV_SPI_EXP_CS_PORT gpioPortC -#define SL_CPC_DRV_SPI_EXP_CS_PIN 3 - -// [EUSART_SL_CPC_DRV_SPI_EXP]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_SPI_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4109a_brd4001a/sl_cpc_drv_secondary_spi_usart_exp_config.h b/hardware/board/config/brd4109a_brd4001a/sl_cpc_drv_secondary_spi_usart_exp_config.h deleted file mode 100644 index 9a4b09987e..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_cpc_drv_secondary_spi_usart_exp_config.h +++ /dev/null @@ -1,94 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC SPI SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_SPI_USART_EXP_SECONDARY_CONFIG_H -#define SL_CPC_DRV_SPI_USART_EXP_SECONDARY_CONFIG_H -#include "spidrv.h" - -// CPC-Secondary SPI Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_SPI_EXP_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_SIZE 10 - -// SPI bit rate -// Default: 1000000 -#define SL_CPC_DRV_SPI_EXP_BITRATE 1000000 - -// Chip Select Interrupt Number on Falling Edge -// Default: 10 -#define SL_CPC_DRV_SPI_EXP_CS_FALLING_EDGE_INT_NO 0 - -// Chip Select Interrupt Number on Rising Edge -// Default: 11 -#define SL_CPC_DRV_SPI_EXP_CS_RISING_EDGE_INT_NO 1 -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_SPI_EXP_RX_IRQ -// $[GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ] -#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PORT gpioPortB -#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PIN 0 - -// [GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ]$ - -// SL_CPC_DRV_SPI_EXP -// $[USART_SL_CPC_DRV_SPI_EXP] -#define SL_CPC_DRV_SPI_EXP_PERIPHERAL USART0 -#define SL_CPC_DRV_SPI_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define SL_CPC_DRV_SPI_EXP_TX_PORT gpioPortC -#define SL_CPC_DRV_SPI_EXP_TX_PIN 0 - -// USART0 RX on PC01 -#define SL_CPC_DRV_SPI_EXP_RX_PORT gpioPortC -#define SL_CPC_DRV_SPI_EXP_RX_PIN 1 - -// USART0 CLK on PC02 -#define SL_CPC_DRV_SPI_EXP_CLK_PORT gpioPortC -#define SL_CPC_DRV_SPI_EXP_CLK_PIN 2 - -// USART0 CS on PC03 -#define SL_CPC_DRV_SPI_EXP_CS_PORT gpioPortC -#define SL_CPC_DRV_SPI_EXP_CS_PIN 3 - -// [USART_SL_CPC_DRV_SPI_EXP]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_SPI_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4109a_brd4001a/sl_cpc_drv_secondary_uart_eusart_exp_config.h b/hardware/board/config/brd4109a_brd4001a/sl_cpc_drv_secondary_uart_eusart_exp_config.h deleted file mode 100644 index d3107de59a..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_cpc_drv_secondary_uart_eusart_exp_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC EUSART SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_EUSART_EXP_SECONDARY_CONFIG_H -#define SL_CPC_DRV_UART_EUSART_EXP_SECONDARY_CONFIG_H - -// CPC - Secondary EUSART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 - -// EUSART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 - -// Flow control -// None -// CTS/RTS -// Default: eusartHwFlowControlNone -#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_EXP -// $[EUSART_SL_CPC_DRV_UART_EXP] -#define SL_CPC_DRV_UART_EXP_PERIPHERAL EUSART0 -#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 - -// EUSART0 TX on PC00 -#define SL_CPC_DRV_UART_EXP_TX_PORT gpioPortC -#define SL_CPC_DRV_UART_EXP_TX_PIN 0 - -// EUSART0 RX on PC01 -#define SL_CPC_DRV_UART_EXP_RX_PORT gpioPortC -#define SL_CPC_DRV_UART_EXP_RX_PIN 1 - -// EUSART0 CTS on PC02 -#define SL_CPC_DRV_UART_EXP_CTS_PORT gpioPortC -#define SL_CPC_DRV_UART_EXP_CTS_PIN 2 - -// EUSART0 RTS on PC03 -#define SL_CPC_DRV_UART_EXP_RTS_PORT gpioPortC -#define SL_CPC_DRV_UART_EXP_RTS_PIN 3 - -// [EUSART_SL_CPC_DRV_UART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4109a_brd4001a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h b/hardware/board/config/brd4109a_brd4001a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h deleted file mode 100644 index 161b31ba0f..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC EUSART SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_EUSART_VCOM_SECONDARY_CONFIG_H -#define SL_CPC_DRV_UART_EUSART_VCOM_SECONDARY_CONFIG_H - -// CPC - Secondary EUSART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 - -// EUSART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 - -// Flow control -// None -// CTS/RTS -// Default: eusartHwFlowControlNone -#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_VCOM -// $[EUSART_SL_CPC_DRV_UART_VCOM] -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL EUSART0 -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 - -// EUSART0 TX on PA05 -#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_TX_PIN 5 - -// EUSART0 RX on PA06 -#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_RX_PIN 6 - -// EUSART0 CTS on PA00 -#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_CTS_PIN 0 - -// EUSART0 RTS on PA07 -#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_RTS_PIN 7 - -// [EUSART_SL_CPC_DRV_UART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_VCOM_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4109a_brd4001a/sl_cpc_drv_secondary_uart_usart_exp_config.h b/hardware/board/config/brd4109a_brd4001a/sl_cpc_drv_secondary_uart_usart_exp_config.h deleted file mode 100644 index acce477ea4..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_cpc_drv_secondary_uart_usart_exp_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC UART SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_USART_EXP_SECONDARY_CONFIG_H -#define SL_CPC_DRV_UART_USART_EXP_SECONDARY_CONFIG_H - -// CPC - Secondary UART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 - -// UART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 - -// Flow control -// None -// CTS/RTS -// Default: usartHwFlowControlCtsAndRts -#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_EXP -// $[USART_SL_CPC_DRV_UART_EXP] -#define SL_CPC_DRV_UART_EXP_PERIPHERAL USART0 -#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define SL_CPC_DRV_UART_EXP_TX_PORT gpioPortC -#define SL_CPC_DRV_UART_EXP_TX_PIN 0 - -// USART0 RX on PC01 -#define SL_CPC_DRV_UART_EXP_RX_PORT gpioPortC -#define SL_CPC_DRV_UART_EXP_RX_PIN 1 - -// USART0 CTS on PC02 -#define SL_CPC_DRV_UART_EXP_CTS_PORT gpioPortC -#define SL_CPC_DRV_UART_EXP_CTS_PIN 2 - -// USART0 RTS on PC03 -#define SL_CPC_DRV_UART_EXP_RTS_PORT gpioPortC -#define SL_CPC_DRV_UART_EXP_RTS_PIN 3 - -// [USART_SL_CPC_DRV_UART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4109a_brd4001a/sl_cpc_drv_secondary_uart_usart_vcom_config.h b/hardware/board/config/brd4109a_brd4001a/sl_cpc_drv_secondary_uart_usart_vcom_config.h deleted file mode 100644 index 09649bc5e1..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_cpc_drv_secondary_uart_usart_vcom_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC UART SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_USART_VCOM_SECONDARY_CONFIG_H -#define SL_CPC_DRV_UART_USART_VCOM_SECONDARY_CONFIG_H - -// CPC - Secondary UART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 - -// UART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 - -// Flow control -// None -// CTS/RTS -// Default: usartHwFlowControlCtsAndRts -#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_VCOM -// $[USART_SL_CPC_DRV_UART_VCOM] -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_RX_PIN 6 - -// USART0 CTS on PA00 -#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_CTS_PIN 0 - -// USART0 RTS on PA07 -#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_RTS_PIN 7 - -// [USART_SL_CPC_DRV_UART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_VCOM_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4109a_brd4001a/sl_device_init_hfxo_config.h b/hardware/board/config/brd4109a_brd4001a/sl_device_init_hfxo_config.h deleted file mode 100644 index b0938ac495..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_device_init_hfxo_config.h +++ /dev/null @@ -1,53 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_HFXO Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H -#define SL_DEVICE_INIT_HFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// External sine wave -// Default: cmuHfxoOscMode_Crystal -#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal - -// Frequency <38000000-40000000> -// Default: 38400000 -#define SL_DEVICE_INIT_HFXO_FREQ 38400000 - -// CTUNE <0-255> -// Default: 140 -#define SL_DEVICE_INIT_HFXO_CTUNE 120 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4001a/sl_device_init_lfxo_config.h b/hardware/board/config/brd4109a_brd4001a/sl_device_init_lfxo_config.h deleted file mode 100644 index 0e1f4147bf..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_device_init_lfxo_config.h +++ /dev/null @@ -1,66 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_LFXO Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H -#define SL_DEVICE_INIT_LFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// AC-coupled buffer -// External digital clock -// Default: cmuLfxoOscMode_Crystal -#define SL_DEVICE_INIT_LFXO_MODE cmuLfxoOscMode_Crystal - -// CTUNE <0-127> -// Default: 63 -#define SL_DEVICE_INIT_LFXO_CTUNE 37 - -// LFXO precision in PPM <0-65535> -// Default: 500 -#define SL_DEVICE_INIT_LFXO_PRECISION 100 - -// Startup Timeout Delay -// -// 2 cycles -// 256 cycles -// 1K cycles -// 2K cycles -// 4K cycles -// 8K cycles -// 16K cycles -// 32K cycles -// Default: cmuLfxoStartupDelay_4KCycles -#define SL_DEVICE_INIT_LFXO_TIMEOUT cmuLfxoStartupDelay_4KCycles -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4001a/sl_i2cspm_sensor_config.h b/hardware/board/config/brd4109a_brd4001a/sl_i2cspm_sensor_config.h deleted file mode 100644 index 738fcafa39..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_i2cspm_sensor_config.h +++ /dev/null @@ -1,58 +0,0 @@ -/***************************************************************************//** - * @file - * @brief I2CSPM Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_I2CSPM_SENSOR_CONFIG_H -#define SL_I2CSPM_SENSOR_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu - -// I2CSPM settings - -// Reference clock frequency -// Frequency in Hz of the reference clock. -// Select 0 to use the frequency of the currently selected clock. -// Default: 0 -#define SL_I2CSPM_SENSOR_REFERENCE_CLOCK 0 - -// Speed mode -// <0=> Standard mode (100kbit/s) -// <1=> Fast mode (400kbit/s) -// <2=> Fast mode plus (1Mbit/s) -// Default: 0 -#define SL_I2CSPM_SENSOR_SPEED_MODE 0 -// end I2CSPM config - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_I2CSPM_SENSOR -// $[I2C_SL_I2CSPM_SENSOR] -#define SL_I2CSPM_SENSOR_PERIPHERAL I2C0 -#define SL_I2CSPM_SENSOR_PERIPHERAL_NO 0 - -// I2C0 SCL on PB02 -#define SL_I2CSPM_SENSOR_SCL_PORT gpioPortB -#define SL_I2CSPM_SENSOR_SCL_PIN 2 - -// I2C0 SDA on PB03 -#define SL_I2CSPM_SENSOR_SDA_PORT gpioPortB -#define SL_I2CSPM_SENSOR_SDA_PIN 3 - -// [I2C_SL_I2CSPM_SENSOR]$ -// <<< sl:end pin_tool >>> - -#endif // SL_I2CSPM_SENSOR_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4001a/sl_iostream_eusart_exp_config.h b/hardware/board/config/brd4109a_brd4001a/sl_iostream_eusart_exp_config.h deleted file mode 100644 index 298b5d2c75..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_iostream_eusart_exp_config.h +++ /dev/null @@ -1,107 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_EUSART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_EUSART_EXP_CONFIG_H -#define SL_IOSTREAM_EUSART_EXP_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// EUART settings - -// Enable High frequency mode -// Default: 1 -#define SL_IOSTREAM_EUSART_EXP_ENABLE_HIGH_FREQUENCY 1 - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_EUSART_EXP_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: eusartNoParity -#define SL_IOSTREAM_EUSART_EXP_PARITY eusartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: eusartStopbits1 -#define SL_IOSTREAM_EUSART_EXP_STOP_BITS eusartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: eusartHwFlowControlNone -#define SL_IOSTREAM_EUSART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlNone - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_EUSART_EXP_RX_BUFFER_SIZE 32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_EUSART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_EUSART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_EUSART_EXP -// $[EUSART_SL_IOSTREAM_EUSART_EXP] -#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL EUSART0 -#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL_NO 0 - -// EUSART0 TX on PA05 -#define SL_IOSTREAM_EUSART_EXP_TX_PORT gpioPortA -#define SL_IOSTREAM_EUSART_EXP_TX_PIN 5 - -// EUSART0 RX on PA06 -#define SL_IOSTREAM_EUSART_EXP_RX_PORT gpioPortA -#define SL_IOSTREAM_EUSART_EXP_RX_PIN 6 - - - -// [EUSART_SL_IOSTREAM_EUSART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4109a_brd4001a/sl_iostream_eusart_vcom_config.h b/hardware/board/config/brd4109a_brd4001a/sl_iostream_eusart_vcom_config.h deleted file mode 100644 index 237dca5fe7..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_iostream_eusart_vcom_config.h +++ /dev/null @@ -1,113 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_EUSART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_EUSART_VCOM_CONFIG_H -#define SL_IOSTREAM_EUSART_VCOM_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// EUART settings - -// Enable High frequency mode -// Default: 1 -#define SL_IOSTREAM_EUSART_VCOM_ENABLE_HIGH_FREQUENCY 1 - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_EUSART_VCOM_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: eusartNoParity -#define SL_IOSTREAM_EUSART_VCOM_PARITY eusartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: eusartStopbits1 -#define SL_IOSTREAM_EUSART_VCOM_STOP_BITS eusartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: eusartHwFlowControlNone -#define SL_IOSTREAM_EUSART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_EUSART_VCOM_RX_BUFFER_SIZE 32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_EUSART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_EUSART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_EUSART_VCOM -// $[EUSART_SL_IOSTREAM_EUSART_VCOM] -#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL EUSART0 -#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL_NO 0 - -// EUSART0 TX on PA05 -#define SL_IOSTREAM_EUSART_VCOM_TX_PORT gpioPortA -#define SL_IOSTREAM_EUSART_VCOM_TX_PIN 5 - -// EUSART0 RX on PA06 -#define SL_IOSTREAM_EUSART_VCOM_RX_PORT gpioPortA -#define SL_IOSTREAM_EUSART_VCOM_RX_PIN 6 - -// EUSART0 CTS on PA00 -#define SL_IOSTREAM_EUSART_VCOM_CTS_PORT gpioPortA -#define SL_IOSTREAM_EUSART_VCOM_CTS_PIN 0 - -// EUSART0 RTS on PA07 -#define SL_IOSTREAM_EUSART_VCOM_RTS_PORT gpioPortA -#define SL_IOSTREAM_EUSART_VCOM_RTS_PIN 7 - -// [EUSART_SL_IOSTREAM_EUSART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4109a_brd4001a/sl_iostream_usart_exp_config.h b/hardware/board/config/brd4109a_brd4001a/sl_iostream_usart_exp_config.h deleted file mode 100644 index 8669faa1a4..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_iostream_usart_exp_config.h +++ /dev/null @@ -1,103 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_USART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_USART_EXP_CONFIG_H -#define SL_IOSTREAM_USART_EXP_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// USART settings - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_USART_EXP_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_IOSTREAM_USART_EXP_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_IOSTREAM_USART_EXP_STOP_BITS usartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: usartHwFlowControlNone -#define SL_IOSTREAM_USART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlNone - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_USART_EXP_RX_BUFFER_SIZE 32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_USART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_USART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_USART_EXP -// $[USART_SL_IOSTREAM_USART_EXP] -#define SL_IOSTREAM_USART_EXP_PERIPHERAL USART0 -#define SL_IOSTREAM_USART_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_IOSTREAM_USART_EXP_TX_PORT gpioPortA -#define SL_IOSTREAM_USART_EXP_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_IOSTREAM_USART_EXP_RX_PORT gpioPortA -#define SL_IOSTREAM_USART_EXP_RX_PIN 6 - - - -// [USART_SL_IOSTREAM_USART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4109a_brd4001a/sl_iostream_usart_vcom_config.h b/hardware/board/config/brd4109a_brd4001a/sl_iostream_usart_vcom_config.h deleted file mode 100644 index f67a5a7f97..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_iostream_usart_vcom_config.h +++ /dev/null @@ -1,109 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_USART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H -#define SL_IOSTREAM_USART_VCOM_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// USART settings - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_USART_VCOM_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: usartHwFlowControlNone -#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_USART_VCOM -// $[USART_SL_IOSTREAM_USART_VCOM] -#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART0 -#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_IOSTREAM_USART_VCOM_TX_PORT gpioPortA -#define SL_IOSTREAM_USART_VCOM_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_IOSTREAM_USART_VCOM_RX_PORT gpioPortA -#define SL_IOSTREAM_USART_VCOM_RX_PIN 6 - -// USART0 CTS on PA00 -#define SL_IOSTREAM_USART_VCOM_CTS_PORT gpioPortA -#define SL_IOSTREAM_USART_VCOM_CTS_PIN 0 - -// USART0 RTS on PA07 -#define SL_IOSTREAM_USART_VCOM_RTS_PORT gpioPortA -#define SL_IOSTREAM_USART_VCOM_RTS_PIN 7 - -// [USART_SL_IOSTREAM_USART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4109a_brd4001a/sl_memlcd_eusart_config.h b/hardware/board/config/brd4109a_brd4001a/sl_memlcd_eusart_config.h deleted file mode 100644 index b240556b3c..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_memlcd_eusart_config.h +++ /dev/null @@ -1,53 +0,0 @@ -/***************************************************************************//** - * @file - * @brief SPI abstraction used by memory lcd display - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_MEMLCD_CONFIG_H -#define SL_MEMLCD_CONFIG_H - -// <<< sl:start pin_tool >>> -// SL_MEMLCD_SPI -// $[EUSART_SL_MEMLCD_SPI] -#define SL_MEMLCD_SPI_PERIPHERAL EUSART0 -#define SL_MEMLCD_SPI_PERIPHERAL_NO 0 - -// EUSART0 TX on PC00 -#define SL_MEMLCD_SPI_TX_PORT gpioPortC -#define SL_MEMLCD_SPI_TX_PIN 0 - -// EUSART0 SCLK on PC02 -#define SL_MEMLCD_SPI_SCLK_PORT gpioPortC -#define SL_MEMLCD_SPI_SCLK_PIN 2 - -// [EUSART_SL_MEMLCD_SPI]$ - -// SL_MEMLCD_SPI_CS -// $[GPIO_SL_MEMLCD_SPI_CS] -#define SL_MEMLCD_SPI_CS_PORT gpioPortC -#define SL_MEMLCD_SPI_CS_PIN 6 - -// [GPIO_SL_MEMLCD_SPI_CS]$ - -// SL_MEMLCD_EXTCOMIN -// $[GPIO_SL_MEMLCD_EXTCOMIN] -#define SL_MEMLCD_EXTCOMIN_PORT gpioPortD -#define SL_MEMLCD_EXTCOMIN_PIN 2 - -// [GPIO_SL_MEMLCD_EXTCOMIN]$ - -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4109a_brd4001a/sl_memlcd_usart_config.h b/hardware/board/config/brd4109a_brd4001a/sl_memlcd_usart_config.h deleted file mode 100644 index 2e7d32028e..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_memlcd_usart_config.h +++ /dev/null @@ -1,53 +0,0 @@ -/***************************************************************************//** - * @file - * @brief SPI abstraction used by memory lcd display - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_MEMLCD_CONFIG_H -#define SL_MEMLCD_CONFIG_H - -// <<< sl:start pin_tool >>> -// SL_MEMLCD_SPI -// $[USART_SL_MEMLCD_SPI] -#define SL_MEMLCD_SPI_PERIPHERAL USART0 -#define SL_MEMLCD_SPI_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define SL_MEMLCD_SPI_TX_PORT gpioPortC -#define SL_MEMLCD_SPI_TX_PIN 0 - -// USART0 CLK on PC02 -#define SL_MEMLCD_SPI_CLK_PORT gpioPortC -#define SL_MEMLCD_SPI_CLK_PIN 2 - -// [USART_SL_MEMLCD_SPI]$ - -// SL_MEMLCD_SPI_CS -// $[GPIO_SL_MEMLCD_SPI_CS] -#define SL_MEMLCD_SPI_CS_PORT gpioPortC -#define SL_MEMLCD_SPI_CS_PIN 6 - -// [GPIO_SL_MEMLCD_SPI_CS]$ - -// SL_MEMLCD_EXTCOMIN -// $[GPIO_SL_MEMLCD_EXTCOMIN] -#define SL_MEMLCD_EXTCOMIN_PORT gpioPortD -#define SL_MEMLCD_EXTCOMIN_PIN 2 - -// [GPIO_SL_MEMLCD_EXTCOMIN]$ - -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4109a_brd4001a/sl_mx25_flash_shutdown_eusart_config.h b/hardware/board/config/brd4109a_brd4001a/sl_mx25_flash_shutdown_eusart_config.h deleted file mode 100644 index 1e80a474b3..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_mx25_flash_shutdown_eusart_config.h +++ /dev/null @@ -1,51 +0,0 @@ -/***************************************************************************//** - * @file - * @brief SL_MX25_FLASH_SHUTDOWN_USART Config - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H -#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H - -// <<< sl:start pin_tool >>> -// {eusart signal=TX,RX,SCLK} SL_MX25_FLASH_SHUTDOWN -// [EUSART_SL_MX25_FLASH_SHUTDOWN] -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL EUSART0 -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 - -// EUSART0 TX on PC00 -#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortC -#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 0 - -// EUSART0 RX on PC01 -#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortC -#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 - -// EUSART0 SCLK on PC02 -#define SL_MX25_FLASH_SHUTDOWN_SCLK_PORT gpioPortC -#define SL_MX25_FLASH_SHUTDOWN_SCLK_PIN 2 - -// [EUSART_SL_MX25_FLASH_SHUTDOWN] - -// SL_MX25_FLASH_SHUTDOWN_CS - -// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] -#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortA -#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 - -// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4001a/sl_mx25_flash_shutdown_usart_config.h b/hardware/board/config/brd4109a_brd4001a/sl_mx25_flash_shutdown_usart_config.h deleted file mode 100644 index e80f7982d4..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_mx25_flash_shutdown_usart_config.h +++ /dev/null @@ -1,51 +0,0 @@ -/***************************************************************************//** - * @file - * @brief SL_MX25_FLASH_SHUTDOWN_USART Config - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H -#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H - -// <<< sl:start pin_tool >>> -// {usart signal=TX,RX,CLK} SL_MX25_FLASH_SHUTDOWN -// [USART_SL_MX25_FLASH_SHUTDOWN] -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL USART0 -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortC -#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 0 - -// USART0 RX on PC01 -#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortC -#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 - -// USART0 CLK on PC02 -#define SL_MX25_FLASH_SHUTDOWN_CLK_PORT gpioPortC -#define SL_MX25_FLASH_SHUTDOWN_CLK_PIN 2 - -// [USART_SL_MX25_FLASH_SHUTDOWN] - -// SL_MX25_FLASH_SHUTDOWN_CS - -// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] -#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortA -#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 - -// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4001a/sl_ncp_spidrv_usart_config.h b/hardware/board/config/brd4109a_brd4001a/sl_ncp_spidrv_usart_config.h deleted file mode 100644 index 71fa842005..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_ncp_spidrv_usart_config.h +++ /dev/null @@ -1,94 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Open thread NCP spidrv usart configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_NCP_SPIDRV_USART_CONFIG_H -#define SL_NCP_SPIDRV_USART_CONFIG_H -#include "spidrv.h" - -// NCP spidrv usart Configuration - -// Bit order on the SPI bus -// LSB transmitted first -// MSB transmitted first -#define SL_NCP_SPIDRV_USART_BIT_ORDER spidrvBitOrderMsbFirst - -// SPI clock mode -// SPI mode 0: CLKPOL=0, CLKPHA=0 -// SPI mode 1: CLKPOL=0, CLKPHA=1 -// SPI mode 2: CLKPOL=1, CLKPHA=0 -// SPI mode 3: CLKPOL=1, CLKPHA=1 -#define SL_NCP_SPIDRV_USART_CLOCK_MODE spidrvClockMode0 - -// Chip Select Interrupt Number on Falling Edge -// Default: 10 -#define SL_NCP_SPIDRV_USART_CS_FALLING_EDGE_INT_NO 0 - -// Chip Select Interrupt Number on Rising Edge -// Default: 9 -#define SL_NCP_SPIDRV_USART_CS_RISING_EDGE_INT_NO 1 -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_NCP_SPIDRV_USART_HOST_INT -// $[GPIO_SL_NCP_SPIDRV_USART_HOST_INT] -#define SL_NCP_SPIDRV_USART_HOST_INT_PORT gpioPortB -#define SL_NCP_SPIDRV_USART_HOST_INT_PIN 0 - -// [GPIO_SL_NCP_SPIDRV_USART_HOST_INT]$ - -// SL_NCP_SPIDRV_USART -// $[USART_SL_NCP_SPIDRV_USART] -#define SL_NCP_SPIDRV_USART_PERIPHERAL USART0 -#define SL_NCP_SPIDRV_USART_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define SL_NCP_SPIDRV_USART_TX_PORT gpioPortC -#define SL_NCP_SPIDRV_USART_TX_PIN 0 - -// USART0 RX on PC01 -#define SL_NCP_SPIDRV_USART_RX_PORT gpioPortC -#define SL_NCP_SPIDRV_USART_RX_PIN 1 - -// USART0 CLK on PC02 -#define SL_NCP_SPIDRV_USART_CLK_PORT gpioPortC -#define SL_NCP_SPIDRV_USART_CLK_PIN 2 - -// USART0 CS on PC03 -#define SL_NCP_SPIDRV_USART_CS_PORT gpioPortC -#define SL_NCP_SPIDRV_USART_CS_PIN 3 - -// [USART_SL_NCP_SPIDRV_USART]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_NCP_SPIDRV_USART_CONFIG_H */ diff --git a/hardware/board/config/brd4109a_brd4001a/sl_pwm_init_led0_config.h b/hardware/board/config/brd4109a_brd4001a/sl_pwm_init_led0_config.h deleted file mode 100644 index c3e83a4a81..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_pwm_init_led0_config.h +++ /dev/null @@ -1,62 +0,0 @@ -/***************************************************************************//** - * @file - * @brief PWM Driver - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef PWM_INIT_LED0_CONFIG_H -#define PWM_INIT_LED0_CONFIG_H - -#ifdef __cplusplus -extern "C" { -#endif - -// <<< Use Configuration Wizard in Context Menu >>> - -// PWM configuration - -// PWM frequency [Hz] -// Default: 10000 -#define SL_PWM_LED0_FREQUENCY 10000 - -// Polarity -// Active high -// Active low -// Default: PWM_ACTIVE_HIGH -#define SL_PWM_LED0_POLARITY PWM_ACTIVE_LOW -// end pwm configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_PWM_LED0 -// $[TIMER_SL_PWM_LED0] -#define SL_PWM_LED0_PERIPHERAL TIMER0 -#define SL_PWM_LED0_PERIPHERAL_NO 0 - -#define SL_PWM_LED0_OUTPUT_CHANNEL 0 -// TIMER0 CC0 on PB00 -#define SL_PWM_LED0_OUTPUT_PORT gpioPortB -#define SL_PWM_LED0_OUTPUT_PIN 0 - -// [TIMER_SL_PWM_LED0]$ - -// <<< sl:end pin_tool >>> - -#ifdef __cplusplus -} -#endif - -#endif // PWM_INIT_LED0_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4001a/sl_pwm_init_led1_config.h b/hardware/board/config/brd4109a_brd4001a/sl_pwm_init_led1_config.h deleted file mode 100644 index c77a6773a9..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_pwm_init_led1_config.h +++ /dev/null @@ -1,62 +0,0 @@ -/***************************************************************************//** - * @file - * @brief PWM Driver - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef PWM_INIT_LED1_CONFIG_H -#define PWM_INIT_LED1_CONFIG_H - -#ifdef __cplusplus -extern "C" { -#endif - -// <<< Use Configuration Wizard in Context Menu >>> - -// PWM configuration - -// PWM frequency [Hz] -// Default: 10000 -#define SL_PWM_LED1_FREQUENCY 10000 - -// Polarity -// Active high -// Active low -// Default: PWM_ACTIVE_HIGH -#define SL_PWM_LED1_POLARITY PWM_ACTIVE_LOW -// end pwm configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_PWM_LED1 -// $[TIMER_SL_PWM_LED1] -#define SL_PWM_LED1_PERIPHERAL TIMER1 -#define SL_PWM_LED1_PERIPHERAL_NO 1 - -#define SL_PWM_LED1_OUTPUT_CHANNEL 0 -// TIMER1 CC0 on PB01 -#define SL_PWM_LED1_OUTPUT_PORT gpioPortB -#define SL_PWM_LED1_OUTPUT_PIN 1 - -// [TIMER_SL_PWM_LED1]$ - -// <<< sl:end pin_tool >>> - -#ifdef __cplusplus -} -#endif - -#endif // PWM_INIT_LED1_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4001a/sl_rail_util_pa_config.h b/hardware/board/config/brd4109a_brd4001a/sl_rail_util_pa_config.h deleted file mode 100644 index a1a5fce586..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_rail_util_pa_config.h +++ /dev/null @@ -1,81 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Power Amplifier configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_RAIL_UTIL_PA_CONFIG_H -#define SL_RAIL_UTIL_PA_CONFIG_H - -#include "rail_types.h" - -// <<< Use Configuration Wizard in Context Menu >>> - -// PA Configuration -// Initial PA Power (deci-dBm, 100 = 10.0 dBm) -// Default: 100 -#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 - -// PA Ramp Time (microseconds) -// <0-65535:1> -// Default: 2 -#define SL_RAIL_UTIL_PA_RAMP_TIME_US 2 -// Milli-volts on PA supply pin (PA_VDD) -// <0-65535:1> -// Default: 3300 -#define SL_RAIL_UTIL_PA_VOLTAGE_MV 1800 -// 2.4 GHz PA Selection -// Highest Possible -// High Power (chip-specific) -// Low Power -// Disable -// Default: RAIL_TX_POWER_MODE_2P4GIG_HIGHEST -#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HIGHEST -// Sub-1 GHz PA Selection -// Disable -// Default: RAIL_TX_POWER_MODE_NONE -#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE -// - -// PA Curve Configuration -// Header file containing custom PA curves -// Default: "pa_curves_efr32.h" -#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" -// Header file containing PA curve types -// Default: "pa_curve_types_efr32.h" -#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" -// - -// PA Calibration Configuration -// Apply PA Calibration Factory Offset -// Default: 1 -#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 -// - -// <<< end of configuration section >>> - -#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4001a/sl_rail_util_pti_config.h b/hardware/board/config/brd4109a_brd4001a/sl_rail_util_pti_config.h deleted file mode 100644 index 90431d7936..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_rail_util_pti_config.h +++ /dev/null @@ -1,73 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Packet Trace Information configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_RAIL_UTIL_PTI_CONFIG_H -#define SL_RAIL_UTIL_PTI_CONFIG_H - -#include "rail_types.h" - -// <<< Use Configuration Wizard in Context Menu >>> -// PTI Configuration - -// PTI mode -// UART -// UART onewire -// SPI -// Disabled -// Default: RAIL_PTI_MODE_UART -#define SL_RAIL_UTIL_PTI_MODE RAIL_PTI_MODE_UART - -// PTI Baud Rate (Hertz) -// <147800-20000000:1> -// Default: 1600000 -#define SL_RAIL_UTIL_PTI_BAUD_RATE_HZ 1600000 - -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_RAIL_UTIL_PTI -// $[PTI_SL_RAIL_UTIL_PTI] -#define SL_RAIL_UTIL_PTI_PERIPHERAL PTI - -// PTI DOUT on PC04 -#define SL_RAIL_UTIL_PTI_DOUT_PORT gpioPortC -#define SL_RAIL_UTIL_PTI_DOUT_PIN 4 - -// PTI DFRAME on PC05 -#define SL_RAIL_UTIL_PTI_DFRAME_PORT gpioPortC -#define SL_RAIL_UTIL_PTI_DFRAME_PIN 5 - - -// [PTI_SL_RAIL_UTIL_PTI]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_RAIL_UTIL_PTI_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4001a/sl_simple_led_led0_config.h b/hardware/board/config/brd4109a_brd4001a/sl_simple_led_led0_config.h deleted file mode 100644 index 88613fa73e..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_simple_led_led0_config.h +++ /dev/null @@ -1,44 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_LED_LED0_CONFIG_H -#define SL_SIMPLE_LED_LED0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple LED configuration -// -// Active low -// Active high -// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH -#define SL_SIMPLE_LED_LED0_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_LED_LED0 -// $[GPIO_SL_SIMPLE_LED_LED0] -#define SL_SIMPLE_LED_LED0_PORT gpioPortB -#define SL_SIMPLE_LED_LED0_PIN 0 - -// [GPIO_SL_SIMPLE_LED_LED0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_LED_LED0_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4001a/sl_simple_led_led1_config.h b/hardware/board/config/brd4109a_brd4001a/sl_simple_led_led1_config.h deleted file mode 100644 index 2cbc3cb4dd..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_simple_led_led1_config.h +++ /dev/null @@ -1,44 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_LED_LED1_CONFIG_H -#define SL_SIMPLE_LED_LED1_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple LED configuration -// -// Active low -// Active high -// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH -#define SL_SIMPLE_LED_LED1_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_LED_LED1 -// $[GPIO_SL_SIMPLE_LED_LED1] -#define SL_SIMPLE_LED_LED1_PORT gpioPortB -#define SL_SIMPLE_LED_LED1_PIN 1 - -// [GPIO_SL_SIMPLE_LED_LED1]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_LED_LED1_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4001a/sl_spidrv_eusart_exp_config.h b/hardware/board/config/brd4109a_brd4001a/sl_spidrv_eusart_exp_config.h deleted file mode 100644 index 430ec2f9c5..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_spidrv_eusart_exp_config.h +++ /dev/null @@ -1,89 +0,0 @@ -/***************************************************************************//** - * @file - * @brief SPIDRV_EUSART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SPIDRV_EUSART_EXP_CONFIG_H -#define SL_SPIDRV_EUSART_EXP_CONFIG_H - -#include "spidrv.h" - -// <<< Use Configuration Wizard in Context Menu >>> -// SPIDRV settings - -// SPI bitrate -// Default: 1000000 -#define SL_SPIDRV_EUSART_EXP_BITRATE 1000000 - -// SPI frame length <7-16> -// Default: 8 -#define SL_SPIDRV_EUSART_EXP_FRAME_LENGTH 8 - -// SPI mode -// Master -// Slave -#define SL_SPIDRV_EUSART_EXP_TYPE spidrvMaster - -// Bit order on the SPI bus -// LSB transmitted first -// MSB transmitted first -#define SL_SPIDRV_EUSART_EXP_BIT_ORDER spidrvBitOrderMsbFirst - -// SPI clock mode -// SPI mode 0: CLKPOL=0, CLKPHA=0 -// SPI mode 1: CLKPOL=0, CLKPHA=1 -// SPI mode 2: CLKPOL=1, CLKPHA=0 -// SPI mode 3: CLKPOL=1, CLKPHA=1 -#define SL_SPIDRV_EUSART_EXP_CLOCK_MODE spidrvClockMode0 - -// SPI master chip select (CS) control scheme. -// CS controlled by the SPI driver -// CS controlled by the application -#define SL_SPIDRV_EUSART_EXP_CS_CONTROL spidrvCsControlAuto - -// SPI slave transfer start scheme -// Transfer starts immediately -// Transfer starts when the bus is idle (CS deasserted) -// Only applies if instance type is spidrvSlave -#define SL_SPIDRV_EUSART_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_SPIDRV_EUSART_EXP -// $[EUSART_SL_SPIDRV_EUSART_EXP] -#define SL_SPIDRV_EUSART_EXP_PERIPHERAL EUSART0 -#define SL_SPIDRV_EUSART_EXP_PERIPHERAL_NO 0 - -// EUSART0 TX on PC00 -#define SL_SPIDRV_EUSART_EXP_TX_PORT gpioPortC -#define SL_SPIDRV_EUSART_EXP_TX_PIN 0 - -// EUSART0 RX on PC01 -#define SL_SPIDRV_EUSART_EXP_RX_PORT gpioPortC -#define SL_SPIDRV_EUSART_EXP_RX_PIN 1 - -// EUSART0 SCLK on PC02 -#define SL_SPIDRV_EUSART_EXP_SCLK_PORT gpioPortC -#define SL_SPIDRV_EUSART_EXP_SCLK_PIN 2 - -// EUSART0 CS on PC03 -#define SL_SPIDRV_EUSART_EXP_CS_PORT gpioPortC -#define SL_SPIDRV_EUSART_EXP_CS_PIN 3 - -// [EUSART_SL_SPIDRV_EUSART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif // SL_SPIDRV_EUSART_EXP_CONFIG_HEUSART_ diff --git a/hardware/board/config/brd4109a_brd4001a/sl_spidrv_exp_config.h b/hardware/board/config/brd4109a_brd4001a/sl_spidrv_exp_config.h deleted file mode 100644 index 64cda25258..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_spidrv_exp_config.h +++ /dev/null @@ -1,89 +0,0 @@ -/***************************************************************************//** - * @file - * @brief SPIDRV Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SPIDRV_EXP_CONFIG_H -#define SL_SPIDRV_EXP_CONFIG_H - -#include "spidrv.h" - -// <<< Use Configuration Wizard in Context Menu >>> -// SPIDRV settings - -// SPI bitrate -// Default: 1000000 -#define SL_SPIDRV_EXP_BITRATE 1000000 - -// SPI frame length <4-16> -// Default: 8 -#define SL_SPIDRV_EXP_FRAME_LENGTH 8 - -// SPI mode -// Master -// Slave -#define SL_SPIDRV_EXP_TYPE spidrvMaster - -// Bit order on the SPI bus -// LSB transmitted first -// MSB transmitted first -#define SL_SPIDRV_EXP_BIT_ORDER spidrvBitOrderMsbFirst - -// SPI clock mode -// SPI mode 0: CLKPOL=0, CLKPHA=0 -// SPI mode 1: CLKPOL=0, CLKPHA=1 -// SPI mode 2: CLKPOL=1, CLKPHA=0 -// SPI mode 3: CLKPOL=1, CLKPHA=1 -#define SL_SPIDRV_EXP_CLOCK_MODE spidrvClockMode0 - -// SPI master chip select (CS) control scheme. -// CS controlled by the SPI driver -// CS controlled by the application -#define SL_SPIDRV_EXP_CS_CONTROL spidrvCsControlAuto - -// SPI slave transfer start scheme -// Transfer starts immediately -// Transfer starts when the bus is idle (CS deasserted) -// Only applies if instance type is spidrvSlave -#define SL_SPIDRV_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_SPIDRV_EXP -// $[USART_SL_SPIDRV_EXP] -#define SL_SPIDRV_EXP_PERIPHERAL USART0 -#define SL_SPIDRV_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define SL_SPIDRV_EXP_TX_PORT gpioPortC -#define SL_SPIDRV_EXP_TX_PIN 0 - -// USART0 RX on PC01 -#define SL_SPIDRV_EXP_RX_PORT gpioPortC -#define SL_SPIDRV_EXP_RX_PIN 1 - -// USART0 CLK on PC02 -#define SL_SPIDRV_EXP_CLK_PORT gpioPortC -#define SL_SPIDRV_EXP_CLK_PIN 2 - -// USART0 CS on PC03 -#define SL_SPIDRV_EXP_CS_PORT gpioPortC -#define SL_SPIDRV_EXP_CS_PIN 3 - -// [USART_SL_SPIDRV_EXP]$ -// <<< sl:end pin_tool >>> - -#endif // SL_SPIDRV_EXP_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4001a/sl_spidrv_usart_exp_config.h b/hardware/board/config/brd4109a_brd4001a/sl_spidrv_usart_exp_config.h deleted file mode 100644 index 1d25852768..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_spidrv_usart_exp_config.h +++ /dev/null @@ -1,89 +0,0 @@ -/***************************************************************************//** - * @file - * @brief SPIDRV_USART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SPIDRV_USART_EXP_CONFIG_H -#define SL_SPIDRV_USART_EXP_CONFIG_H - -#include "spidrv.h" - -// <<< Use Configuration Wizard in Context Menu >>> -// SPIDRV settings - -// SPI bitrate -// Default: 1000000 -#define SL_SPIDRV_USART_EXP_BITRATE 1000000 - -// SPI frame length <4-16> -// Default: 8 -#define SL_SPIDRV_USART_EXP_FRAME_LENGTH 8 - -// SPI mode -// Master -// Slave -#define SL_SPIDRV_USART_EXP_TYPE spidrvMaster - -// Bit order on the SPI bus -// LSB transmitted first -// MSB transmitted first -#define SL_SPIDRV_USART_EXP_BIT_ORDER spidrvBitOrderMsbFirst - -// SPI clock mode -// SPI mode 0: CLKPOL=0, CLKPHA=0 -// SPI mode 1: CLKPOL=0, CLKPHA=1 -// SPI mode 2: CLKPOL=1, CLKPHA=0 -// SPI mode 3: CLKPOL=1, CLKPHA=1 -#define SL_SPIDRV_USART_EXP_CLOCK_MODE spidrvClockMode0 - -// SPI master chip select (CS) control scheme. -// CS controlled by the SPI driver -// CS controlled by the application -#define SL_SPIDRV_USART_EXP_CS_CONTROL spidrvCsControlAuto - -// SPI slave transfer start scheme -// Transfer starts immediately -// Transfer starts when the bus is idle (CS deasserted) -// Only applies if instance type is spidrvSlave -#define SL_SPIDRV_USART_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_SPIDRV_USART_EXP -// $[USART_SL_SPIDRV_USART_EXP] -#define SL_SPIDRV_USART_EXP_PERIPHERAL USART0 -#define SL_SPIDRV_USART_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define SL_SPIDRV_USART_EXP_TX_PORT gpioPortC -#define SL_SPIDRV_USART_EXP_TX_PIN 0 - -// USART0 RX on PC01 -#define SL_SPIDRV_USART_EXP_RX_PORT gpioPortC -#define SL_SPIDRV_USART_EXP_RX_PIN 1 - -// USART0 CLK on PC02 -#define SL_SPIDRV_USART_EXP_CLK_PORT gpioPortC -#define SL_SPIDRV_USART_EXP_CLK_PIN 2 - -// USART0 CS on PC03 -#define SL_SPIDRV_USART_EXP_CS_PORT gpioPortC -#define SL_SPIDRV_USART_EXP_CS_PIN 3 - -// [USART_SL_SPIDRV_USART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif // SL_SPIDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4109a_brd4001a/sl_uartdrv_eusart_exp_config.h deleted file mode 100644 index a89e4ccc3e..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ /dev/null @@ -1,100 +0,0 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV_EUSART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_UARTDRV_EUSART_EXP_CONFIG_H -#define SL_UARTDRV_EUSART_EXP_CONFIG_H - -#include "em_eusart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// EUSART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_EUSART_EXP_BAUDRATE 115200 - -// Low frequency mode -// True -// False -#define SL_UARTDRV_EUSART_EXP_LF_MODE false - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: eusartNoParity -#define SL_UARTDRV_EUSART_EXP_PARITY eusartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: eusartStopbits1 -#define SL_UARTDRV_EUSART_EXP_STOP_BITS eusartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHw -#define SL_UARTDRV_EUSART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Oversampling disabled -// Default: eusartOVS16 -#define SL_UARTDRV_EUSART_EXP_OVERSAMPLING eusartOVS16 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// False -// True -// Default: eusartMajorityVoteEnable -#define SL_UARTDRV_EUSART_EXP_MVDIS eusartMajorityVoteEnable - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_EUSART_EXP_RX_BUFFER_SIZE 6 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_EUSART_EXP_TX_BUFFER_SIZE 6 -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_EUSART_EXP -// $[EUSART_SL_UARTDRV_EUSART_EXP] -#define SL_UARTDRV_EUSART_EXP_PERIPHERAL EUSART0 -#define SL_UARTDRV_EUSART_EXP_PERIPHERAL_NO 0 - -// EUSART0 TX on PA05 -#define SL_UARTDRV_EUSART_EXP_TX_PORT gpioPortA -#define SL_UARTDRV_EUSART_EXP_TX_PIN 5 - -// EUSART0 RX on PA06 -#define SL_UARTDRV_EUSART_EXP_RX_PORT gpioPortA -#define SL_UARTDRV_EUSART_EXP_RX_PIN 6 - - - -// [EUSART_SL_UARTDRV_EUSART_EXP]$ -// <<< sl:end pin_tool >>> -#endif // SL_UARTDRV_EUSART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4001a/sl_uartdrv_eusart_vcom_config.h b/hardware/board/config/brd4109a_brd4001a/sl_uartdrv_eusart_vcom_config.h deleted file mode 100644 index be1494fb96..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_uartdrv_eusart_vcom_config.h +++ /dev/null @@ -1,106 +0,0 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV_EUSART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_UARTDRV_EUSART_VCOM_CONFIG_H -#define SL_UARTDRV_EUSART_VCOM_CONFIG_H - -#include "em_eusart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// EUSART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_EUSART_VCOM_BAUDRATE 115200 - -// Low frequency mode -// True -// False -#define SL_UARTDRV_EUSART_VCOM_LF_MODE false - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: eusartNoParity -#define SL_UARTDRV_EUSART_VCOM_PARITY eusartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: eusartStopbits1 -#define SL_UARTDRV_EUSART_VCOM_STOP_BITS eusartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHw -#define SL_UARTDRV_EUSART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Oversampling disabled -// Default: eusartOVS16 -#define SL_UARTDRV_EUSART_VCOM_OVERSAMPLING eusartOVS16 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// False -// True -// Default: eusartMajorityVoteEnable -#define SL_UARTDRV_EUSART_VCOM_MVDIS eusartMajorityVoteEnable - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_EUSART_VCOM_RX_BUFFER_SIZE 6 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_EUSART_VCOM_TX_BUFFER_SIZE 6 -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_EUSART_VCOM -// $[EUSART_SL_UARTDRV_EUSART_VCOM] -#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL EUSART0 -#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL_NO 0 - -// EUSART0 TX on PA05 -#define SL_UARTDRV_EUSART_VCOM_TX_PORT gpioPortA -#define SL_UARTDRV_EUSART_VCOM_TX_PIN 5 - -// EUSART0 RX on PA06 -#define SL_UARTDRV_EUSART_VCOM_RX_PORT gpioPortA -#define SL_UARTDRV_EUSART_VCOM_RX_PIN 6 - -// EUSART0 CTS on PA00 -#define SL_UARTDRV_EUSART_VCOM_CTS_PORT gpioPortA -#define SL_UARTDRV_EUSART_VCOM_CTS_PIN 0 - -// EUSART0 RTS on PA07 -#define SL_UARTDRV_EUSART_VCOM_RTS_PORT gpioPortA -#define SL_UARTDRV_EUSART_VCOM_RTS_PIN 7 - -// [EUSART_SL_UARTDRV_EUSART_VCOM]$ -// <<< sl:end pin_tool >>> -#endif // SL_UARTDRV_EUSART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4109a_brd4001a/sl_uartdrv_usart_exp_config.h deleted file mode 100644 index 02662139f3..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_uartdrv_usart_exp_config.h +++ /dev/null @@ -1,95 +0,0 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV_USART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_UARTDRV_USART_EXP_CONFIG_H -#define SL_UARTDRV_USART_EXP_CONFIG_H - -#include "em_usart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// UART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_USART_EXP_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_UARTDRV_USART_EXP_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_UARTDRV_USART_EXP_STOP_BITS usartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHw -#define SL_UARTDRV_USART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Default: usartOVS16 -#define SL_UARTDRV_USART_EXP_OVERSAMPLING usartOVS4 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// True -// False -#define SL_UARTDRV_USART_EXP_MVDIS false - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_USART_EXP_RX_BUFFER_SIZE 6 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_USART_EXP_TX_BUFFER_SIZE 6 - -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_USART_EXP -// $[USART_SL_UARTDRV_USART_EXP] -#define SL_UARTDRV_USART_EXP_PERIPHERAL USART0 -#define SL_UARTDRV_USART_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_UARTDRV_USART_EXP_TX_PORT gpioPortA -#define SL_UARTDRV_USART_EXP_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_UARTDRV_USART_EXP_RX_PORT gpioPortA -#define SL_UARTDRV_USART_EXP_RX_PIN 6 - - - -// [USART_SL_UARTDRV_USART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif // SL_UARTDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4001a/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd4109a_brd4001a/sl_uartdrv_usart_vcom_config.h deleted file mode 100644 index 1ee69f20fe..0000000000 --- a/hardware/board/config/brd4109a_brd4001a/sl_uartdrv_usart_vcom_config.h +++ /dev/null @@ -1,101 +0,0 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV_USART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H -#define SL_UARTDRV_USART_VCOM_CONFIG_H - -#include "em_usart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// UART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHw -#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Default: usartOVS16 -#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// True -// False -#define SL_UARTDRV_USART_VCOM_MVDIS false - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 6 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 6 - -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_USART_VCOM -// $[USART_SL_UARTDRV_USART_VCOM] -#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART0 -#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortA -#define SL_UARTDRV_USART_VCOM_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortA -#define SL_UARTDRV_USART_VCOM_RX_PIN 6 - -// USART0 CTS on PA00 -#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA -#define SL_UARTDRV_USART_VCOM_CTS_PIN 0 - -// USART0 RTS on PA07 -#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA -#define SL_UARTDRV_USART_VCOM_RTS_PIN 7 - -// [USART_SL_UARTDRV_USART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4002a/btl_euart_driver_cfg.h b/hardware/board/config/brd4109a_brd4002a/btl_euart_driver_cfg.h deleted file mode 100644 index 26c00dc406..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/btl_euart_driver_cfg.h +++ /dev/null @@ -1,88 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader euart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_EUART_DRIVER_CONFIG_H -#define BTL_EUART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// EUART settings - -// Baud rate -// Default: 115200 -#define SL_SERIAL_EUART_BAUD_RATE 115200 - -// Hardware flow control -// Default: 0 -#define SL_SERIAL_EUART_FLOW_CONTROL 0 -// - -// Receive buffer size -// <0-2048:1> -// Default: 512 [0-2048] -#define SL_DRIVER_EUART_RX_BUFFER_SIZE 512 - -// Transmit buffer size -// <0-2048:1> -// Default: 128 [0-2048] -#define SL_DRIVER_EUART_TX_BUFFER_SIZE 128 - -// Virtual COM Port -// Default: 0 -#define SL_VCOM_ENABLE 0 -// - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_SERIAL_EUART -// $[EUSART_SL_SERIAL_EUART] -#define SL_SERIAL_EUART_PERIPHERAL EUSART0 -#define SL_SERIAL_EUART_PERIPHERAL_NO 0 - -// EUSART0 TX on PA05 -#define SL_SERIAL_EUART_TX_PORT gpioPortA -#define SL_SERIAL_EUART_TX_PIN 5 - -// EUSART0 RX on PA06 -#define SL_SERIAL_EUART_RX_PORT gpioPortA -#define SL_SERIAL_EUART_RX_PIN 6 - -// EUSART0 CTS on PA00 -#define SL_SERIAL_EUART_CTS_PORT gpioPortA -#define SL_SERIAL_EUART_CTS_PIN 0 - -// EUSART0 RTS on PA07 -#define SL_SERIAL_EUART_RTS_PORT gpioPortA -#define SL_SERIAL_EUART_RTS_PIN 7 - -// [EUSART_SL_SERIAL_EUART]$ - - -// SL_VCOM_ENABLE - -// $[GPIO_SL_VCOM_ENABLE] -#define SL_VCOM_ENABLE_PORT gpioPortB -#define SL_VCOM_ENABLE_PIN 4 - -// [GPIO_SL_VCOM_ENABLE]$ - - -// <<< sl:end pin_tool >>> - -#endif // BTL_EUART_DRIVER_CONFIG_H \ No newline at end of file diff --git a/hardware/board/config/brd4109a_brd4002a/btl_ezsp_gpio_activation_cfg.h b/hardware/board/config/brd4109a_brd4002a/btl_ezsp_gpio_activation_cfg.h deleted file mode 100644 index 12c5b0a5eb..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/btl_ezsp_gpio_activation_cfg.h +++ /dev/null @@ -1,52 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader EZSP GPIO Activation - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_EZSP_GPIO_ACTIVATION_CONFIG_H -#define BTL_EZSP_GPIO_ACTIVATION_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Properties of SPI NCP - -// Active state -// Low -// High -// Default: LOW -// Enter firmware upgrade mode if GPIO pin has this state -#define SL_EZSP_GPIO_ACTIVATION_POLARITY LOW - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_EZSPSPI_HOST_INT -// $[GPIO_SL_EZSPSPI_HOST_INT] -#define SL_EZSPSPI_HOST_INT_PORT gpioPortB -#define SL_EZSPSPI_HOST_INT_PIN 0 - -// [GPIO_SL_EZSPSPI_HOST_INT]$ - -// SL_EZSPSPI_WAKE_INT -// $[GPIO_SL_EZSPSPI_WAKE_INT] -#define SL_EZSPSPI_WAKE_INT_PORT gpioPortB -#define SL_EZSPSPI_WAKE_INT_PIN 1 - -// [GPIO_SL_EZSPSPI_WAKE_INT]$ - -// <<< sl:end pin_tool >>> - -#endif // BTL_EZSP_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4002a/btl_spi_controller_eusart_driver_cfg.h b/hardware/board/config/brd4109a_brd4002a/btl_spi_controller_eusart_driver_cfg.h deleted file mode 100644 index 9176ef3c3c..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/btl_spi_controller_eusart_driver_cfg.h +++ /dev/null @@ -1,68 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader Spi Controller Eusart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H -#define BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// SPI Controller EUSART Driver - -// Frequency -// Default: 6400000 -#define SL_EUSART_EXTFLASH_FREQUENCY 6400000 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_EUSART_EXTFLASH -// $[EUSART_SL_EUSART_EXTFLASH] -#define SL_EUSART_EXTFLASH_PERIPHERAL EUSART0 -#define SL_EUSART_EXTFLASH_PERIPHERAL_NO 0 - -// EUSART0 TX on PC00 -#define SL_EUSART_EXTFLASH_TX_PORT gpioPortC -#define SL_EUSART_EXTFLASH_TX_PIN 0 - -// EUSART0 RX on PC01 -#define SL_EUSART_EXTFLASH_RX_PORT gpioPortC -#define SL_EUSART_EXTFLASH_RX_PIN 1 - -// EUSART0 SCLK on PC02 -#define SL_EUSART_EXTFLASH_SCLK_PORT gpioPortC -#define SL_EUSART_EXTFLASH_SCLK_PIN 2 - -// EUSART0 CS on PA04 -#define SL_EUSART_EXTFLASH_CS_PORT gpioPortA -#define SL_EUSART_EXTFLASH_CS_PIN 4 - -// [EUSART_SL_EUSART_EXTFLASH]$ - -// SL_EXTFLASH_WP -// $[GPIO_SL_EXTFLASH_WP] - -// [GPIO_SL_EXTFLASH_WP]$ - -// SL_EXTFLASH_HOLD -// $[GPIO_SL_EXTFLASH_HOLD] - -// [GPIO_SL_EXTFLASH_HOLD]$ - -// <<< sl:end pin_tool >>> - -#endif // BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4002a/btl_spi_controller_usart_driver_cfg.h b/hardware/board/config/brd4109a_brd4002a/btl_spi_controller_usart_driver_cfg.h deleted file mode 100644 index ac3bd96c27..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/btl_spi_controller_usart_driver_cfg.h +++ /dev/null @@ -1,68 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader Spi Controller Usart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H -#define BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// SPI Controller USART Driver - -// Frequency -// Default: 6400000 -#define SL_USART_EXTFLASH_FREQUENCY 6400000 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_USART_EXTFLASH -// $[USART_SL_USART_EXTFLASH] -#define SL_USART_EXTFLASH_PERIPHERAL USART0 -#define SL_USART_EXTFLASH_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define SL_USART_EXTFLASH_TX_PORT gpioPortC -#define SL_USART_EXTFLASH_TX_PIN 0 - -// USART0 RX on PC01 -#define SL_USART_EXTFLASH_RX_PORT gpioPortC -#define SL_USART_EXTFLASH_RX_PIN 1 - -// USART0 CLK on PC02 -#define SL_USART_EXTFLASH_CLK_PORT gpioPortC -#define SL_USART_EXTFLASH_CLK_PIN 2 - -// USART0 CS on PA04 -#define SL_USART_EXTFLASH_CS_PORT gpioPortA -#define SL_USART_EXTFLASH_CS_PIN 4 - -// [USART_SL_USART_EXTFLASH]$ - -// SL_EXTFLASH_WP -// $[GPIO_SL_EXTFLASH_WP] - -// [GPIO_SL_EXTFLASH_WP]$ - -// SL_EXTFLASH_HOLD -// $[GPIO_SL_EXTFLASH_HOLD] - -// [GPIO_SL_EXTFLASH_HOLD]$ - -// <<< sl:end pin_tool >>> - -#endif // BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4002a/btl_spi_peripheral_eusart_driver_cfg.h b/hardware/board/config/brd4109a_brd4002a/btl_spi_peripheral_eusart_driver_cfg.h deleted file mode 100644 index 718b8cf35d..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/btl_spi_peripheral_eusart_driver_cfg.h +++ /dev/null @@ -1,71 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader Spi Peripheral Eusart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H -#define BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// SPI Peripheral Eusart Driver - -// Receive buffer size:[0-2048] <0-2048> -// Default: 300 -#define SL_SPI_PERIPHERAL_EUSART_RX_BUFFER_SIZE 300 - -// Transmit buffer size:[0-2048] <0-2048> -// Default: 50 -#define SL_SPI_PERIPHERAL_EUSART_TX_BUFFER_SIZE 50 - -// LDMA channel for SPI RX:[0-1] <0-1> -// Default: 0 -#define SL_SPI_PERIPHERAL_EUSART_LDMA_RX_CHANNEL 0 - -// LDMA channel for SPI TX:[0-1] <0-1> -// Default: 1 -#define SL_SPI_PERIPHERAL_EUSART_LDMA_TX_CHANNEL 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_EUSART_SPINCP - -// $[EUSART_SL_EUSART_SPINCP] -#define SL_EUSART_SPINCP_PERIPHERAL EUSART0 -#define SL_EUSART_SPINCP_PERIPHERAL_NO 0 - -// EUSART0 TX on PC00 -#define SL_EUSART_SPINCP_TX_PORT gpioPortC -#define SL_EUSART_SPINCP_TX_PIN 0 - -// EUSART0 RX on PC01 -#define SL_EUSART_SPINCP_RX_PORT gpioPortC -#define SL_EUSART_SPINCP_RX_PIN 1 - -// EUSART0 CS on PC03 -#define SL_EUSART_SPINCP_CS_PORT gpioPortC -#define SL_EUSART_SPINCP_CS_PIN 3 - -// EUSART0 SCLK on PC02 -#define SL_EUSART_SPINCP_SCLK_PORT gpioPortC -#define SL_EUSART_SPINCP_SCLK_PIN 2 - -// [EUSART_SL_EUSART_SPINCP]$ - -// <<< sl:end pin_tool >>> - -#endif // BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4002a/btl_spi_peripheral_usart_driver_cfg.h b/hardware/board/config/brd4109a_brd4002a/btl_spi_peripheral_usart_driver_cfg.h deleted file mode 100644 index 2f8916370e..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/btl_spi_peripheral_usart_driver_cfg.h +++ /dev/null @@ -1,71 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader Spi Peripheral Usart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H -#define BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// SPI Peripheral Usart Driver - -// Receive buffer size:[0-2048] <0-2048> -// Default: 300 -#define SL_SPI_PERIPHERAL_USART_RX_BUFFER_SIZE 300 - -// Transmit buffer size:[0-2048] <0-2048> -// Default: 50 -#define SL_SPI_PERIPHERAL_USART_TX_BUFFER_SIZE 50 - -// LDMA channel for SPI RX:[0-1] <0-1> -// Default: 0 -#define SL_SPI_PERIPHERAL_USART_LDMA_RX_CHANNEL 0 - -// LDMA channel for SPI TX:[0-1] <0-1> -// Default: 1 -#define SL_SPI_PERIPHERAL_USART_LDMA_TX_CHANNEL 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_USART_SPINCP - -// $[USART_SL_USART_SPINCP] -#define SL_USART_SPINCP_PERIPHERAL USART0 -#define SL_USART_SPINCP_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define SL_USART_SPINCP_TX_PORT gpioPortC -#define SL_USART_SPINCP_TX_PIN 0 - -// USART0 RX on PC01 -#define SL_USART_SPINCP_RX_PORT gpioPortC -#define SL_USART_SPINCP_RX_PIN 1 - -// USART0 CS on PC03 -#define SL_USART_SPINCP_CS_PORT gpioPortC -#define SL_USART_SPINCP_CS_PIN 3 - -// USART0 CLK on PC02 -#define SL_USART_SPINCP_CLK_PORT gpioPortC -#define SL_USART_SPINCP_CLK_PIN 2 - -// [USART_SL_USART_SPINCP]$ - -// <<< sl:end pin_tool >>> - -#endif // BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4002a/btl_uart_driver_cfg.h b/hardware/board/config/brd4109a_brd4002a/btl_uart_driver_cfg.h deleted file mode 100644 index 5e74316154..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/btl_uart_driver_cfg.h +++ /dev/null @@ -1,89 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader Uart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_UART_DRIVER_CONFIG_H -#define BTL_UART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// USART settings - -// Baud rate -// Default: 115200 -#define SL_SERIAL_UART_BAUD_RATE 115200 - -// Hardware flow control -// Default: 0 -#define SL_SERIAL_UART_FLOW_CONTROL 0 -// - -// Receive buffer size -// <0-2048:1> -// Default: 512 [0-2048] -#define SL_DRIVER_UART_RX_BUFFER_SIZE 512 - -// Transmit buffer size -// <0-2048:1> -// Default: 128 [0-2048] -#define SL_DRIVER_UART_TX_BUFFER_SIZE 128 - -// Virtual COM Port -// Default: 0 -#define SL_VCOM_ENABLE 0 -// - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_SERIAL_UART -// $[USART_SL_SERIAL_UART] -#define SL_SERIAL_UART_PERIPHERAL USART0 -#define SL_SERIAL_UART_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_SERIAL_UART_TX_PORT gpioPortA -#define SL_SERIAL_UART_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_SERIAL_UART_RX_PORT gpioPortA -#define SL_SERIAL_UART_RX_PIN 6 - -// USART0 CTS on PA00 -#define SL_SERIAL_UART_CTS_PORT gpioPortA -#define SL_SERIAL_UART_CTS_PIN 0 - -// USART0 RTS on PA07 -#define SL_SERIAL_UART_RTS_PORT gpioPortA -#define SL_SERIAL_UART_RTS_PIN 7 - -// [USART_SL_SERIAL_UART]$ - - - -// SL_VCOM_ENABLE - -// $[GPIO_SL_VCOM_ENABLE] -#define SL_VCOM_ENABLE_PORT gpioPortB -#define SL_VCOM_ENABLE_PIN 4 - -// [GPIO_SL_VCOM_ENABLE]$ - - -// <<< sl:end pin_tool >>> - -#endif // BTL_UART_DRIVER_CONFIG_H \ No newline at end of file diff --git a/hardware/board/config/brd4109a_brd4002a/iot_flash_cfg_exp.h b/hardware/board/config/brd4109a_brd4002a/iot_flash_cfg_exp.h deleted file mode 100644 index 1ce8020f40..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/iot_flash_cfg_exp.h +++ /dev/null @@ -1,136 +0,0 @@ -/***************************************************************************//** - * @file iot_flash_cfg_inst.h - * @brief Common I/O flash instance configurations. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_FLASH_CFG_EXP_H_ -#define _IOT_FLASH_CFG_EXP_H_ - -/******************************************************************************* - * Flash Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// Flash General Options - -// Instance number -// Instance number used when iot_flash_open() is called. -// Default: 0 -#define IOT_FLASH_CFG_EXP_INST_NUM 0 - -// Instance type -// <0=> Internal Flash (MSC) -// <1=> External Flash (SPI) -// Specify whether this instance is for internal flash (MSC) -// or an external SPI flash. If external, then you need to setup -// SPI configs below. -// Default: 0 -#define IOT_FLASH_CFG_EXP_INST_TYPE 1 - -// - -// SPI Configuration - -// Default SPI bitrate -// Default: 1000000 -#define IOT_FLASH_CFG_EXP_SPI_BITRATE 1000000 - -// Default SPI frame length <4-16> -// Default: 8 -#define IOT_FLASH_CFG_EXP_SPI_FRAME_LENGTH 8 - -// Default SPI master/slave mode -// Master -// Slave -#define IOT_FLASH_CFG_EXP_SPI_TYPE spidrvMaster - -// Default SPI bit order -// LSB transmitted first -// MSB transmitted first -#define IOT_FLASH_CFG_EXP_SPI_BIT_ORDER spidrvBitOrderMsbFirst - -// Default SPI clock mode -// SPI mode 0: CLKPOL=0, CLKPHA=0 -// SPI mode 1: CLKPOL=0, CLKPHA=1 -// SPI mode 2: CLKPOL=1, CLKPHA=0 -// SPI mode 3: CLKPOL=1, CLKPHA=1 -#define IOT_FLASH_CFG_EXP_SPI_CLOCK_MODE spidrvClockMode0 - -// Default SPI CS control scheme -// CS controlled by the SPI driver -// CS controlled by the application -#define IOT_FLASH_CFG_EXP_SPI_CS_CONTROL spidrvCsControlApplication - -// Default SPI transfer scheme -// Transfer starts immediately -// Transfer starts when the bus is idle -#define IOT_FLASH_CFG_EXP_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * EXTERNAL FLASH: H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_FLASH_CFG_EXP_SPI -// $[USART_IOT_FLASH_CFG_EXP_SPI] -#define IOT_FLASH_CFG_EXP_SPI_PERIPHERAL USART0 -#define IOT_FLASH_CFG_EXP_SPI_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define IOT_FLASH_CFG_EXP_SPI_TX_PORT gpioPortC -#define IOT_FLASH_CFG_EXP_SPI_TX_PIN 0 - -// USART0 RX on PC01 -#define IOT_FLASH_CFG_EXP_SPI_RX_PORT gpioPortC -#define IOT_FLASH_CFG_EXP_SPI_RX_PIN 1 - -// USART0 CLK on PC02 -#define IOT_FLASH_CFG_EXP_SPI_CLK_PORT gpioPortC -#define IOT_FLASH_CFG_EXP_SPI_CLK_PIN 2 - -// USART0 CS on PC03 -#define IOT_FLASH_CFG_EXP_SPI_CS_PORT gpioPortC -#define IOT_FLASH_CFG_EXP_SPI_CS_PIN 3 - -// [USART_IOT_FLASH_CFG_EXP_SPI]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_FLASH_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4109a_brd4002a/iot_flash_cfg_spiflash.h b/hardware/board/config/brd4109a_brd4002a/iot_flash_cfg_spiflash.h deleted file mode 100644 index 96eb0c46c5..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/iot_flash_cfg_spiflash.h +++ /dev/null @@ -1,136 +0,0 @@ -/***************************************************************************//** - * @file iot_flash_cfg_inst.h - * @brief Common I/O flash instance configurations. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_FLASH_CFG_SPIFLASH_H_ -#define _IOT_FLASH_CFG_SPIFLASH_H_ - -/******************************************************************************* - * Flash Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// Flash General Options - -// Instance number -// Instance number used when iot_flash_open() is called. -// Default: 0 -#define IOT_FLASH_CFG_SPIFLASH_INST_NUM 0 - -// Instance type -// <0=> Internal Flash (MSC) -// <1=> External Flash (SPI) -// Specify whether this instance is for internal flash (MSC) -// or an external SPI flash. If external, then you need to setup -// SPI configs below. -// Default: 0 -#define IOT_FLASH_CFG_SPIFLASH_INST_TYPE 1 - -// - -// SPI Configuration - -// Default SPI bitrate -// Default: 1000000 -#define IOT_FLASH_CFG_SPIFLASH_SPI_BITRATE 1000000 - -// Default SPI frame length <4-16> -// Default: 8 -#define IOT_FLASH_CFG_SPIFLASH_SPI_FRAME_LENGTH 8 - -// Default SPI master/slave mode -// Master -// Slave -#define IOT_FLASH_CFG_SPIFLASH_SPI_TYPE spidrvMaster - -// Default SPI bit order -// LSB transmitted first -// MSB transmitted first -#define IOT_FLASH_CFG_SPIFLASH_SPI_BIT_ORDER spidrvBitOrderMsbFirst - -// Default SPI clock mode -// SPI mode 0: CLKPOL=0, CLKPHA=0 -// SPI mode 1: CLKPOL=0, CLKPHA=1 -// SPI mode 2: CLKPOL=1, CLKPHA=0 -// SPI mode 3: CLKPOL=1, CLKPHA=1 -#define IOT_FLASH_CFG_SPIFLASH_SPI_CLOCK_MODE spidrvClockMode0 - -// Default SPI CS control scheme -// CS controlled by the SPI driver -// CS controlled by the application -#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_CONTROL spidrvCsControlApplication - -// Default SPI transfer scheme -// Transfer starts immediately -// Transfer starts when the bus is idle -#define IOT_FLASH_CFG_SPIFLASH_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * EXTERNAL FLASH: H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_FLASH_CFG_SPIFLASH_SPI -// $[USART_IOT_FLASH_CFG_SPIFLASH_SPI] -#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL USART0 -#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PORT gpioPortC -#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PIN 0 - -// USART0 RX on PC01 -#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PORT gpioPortC -#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PIN 1 - -// USART0 CLK on PC02 -#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PORT gpioPortC -#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PIN 2 - -// USART0 CS on PA04 -#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PORT gpioPortA -#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PIN 4 - -// [USART_IOT_FLASH_CFG_SPIFLASH_SPI]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_FLASH_CFG_SPIFLASH_H_ */ diff --git a/hardware/board/config/brd4109a_brd4002a/iot_i2c_cfg_exp.h b/hardware/board/config/brd4109a_brd4002a/iot_i2c_cfg_exp.h deleted file mode 100644 index 5e80a7767b..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/iot_i2c_cfg_exp.h +++ /dev/null @@ -1,108 +0,0 @@ -/***************************************************************************//** - * @file IOT_I2C_CFG_EXP_inst.h - * @brief Common I/O I2C instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_I2C_CFG_EXP_H_ -#define _IOT_I2C_CFG_EXP_H_ - -/******************************************************************************* - * I2C Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// I2C General Options - -// Instance number -// Instance number used when iot_i2c_open() is called. -// Default: 0 -#define IOT_I2C_CFG_EXP_INST_NUM 0 - -// Default timeout (in msec) -// Default: 500 -#define IOT_I2C_CFG_EXP_DEFAULT_TIMEOUT 500 - -// Default bus speed -// <100000=> Standard mode -// <400000=> Fast mode -// <1000000=> Fast plus mode -// <3400000=> High speed mode -// Default: 400000 -#define IOT_I2C_CFG_EXP_DEFAULT_FREQ 400000 - -// Accept NACK -// If the driver receives NACK during a transfer, the transfer is halted -// immediately but it is not considered as an error. Instead, the driver -// returns success status (useful for test purposes). -// Default: 0 -#define IOT_I2C_CFG_EXP_ACCEPT_NACK 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> - -// IOT_I2C_CFG_EXP_ENABLE -// $[GPIO_IOT_I2C_CFG_EXP_ENABLE] -#define IOT_I2C_CFG_EXP_ENABLE_PORT gpioPortB -#define IOT_I2C_CFG_EXP_ENABLE_PIN 0 - -// [GPIO_IOT_I2C_CFG_EXP_ENABLE]$ - -// IOT_I2C_CFG_EXP -// $[I2C_IOT_I2C_CFG_EXP] -#define IOT_I2C_CFG_EXP_PERIPHERAL I2C0 -#define IOT_I2C_CFG_EXP_PERIPHERAL_NO 0 - -// I2C0 SCL on PB02 -#define IOT_I2C_CFG_EXP_SCL_PORT gpioPortB -#define IOT_I2C_CFG_EXP_SCL_PIN 2 - -// I2C0 SDA on PB03 -#define IOT_I2C_CFG_EXP_SDA_PORT gpioPortB -#define IOT_I2C_CFG_EXP_SDA_PIN 3 - -// [I2C_IOT_I2C_CFG_EXP]$ - -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_I2C_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4109a_brd4002a/iot_i2c_cfg_test.h b/hardware/board/config/brd4109a_brd4002a/iot_i2c_cfg_test.h deleted file mode 100644 index 86ef507de4..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/iot_i2c_cfg_test.h +++ /dev/null @@ -1,108 +0,0 @@ -/***************************************************************************//** - * @file IOT_I2C_CFG_TEST_inst.h - * @brief Common I/O I2C instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_I2C_CFG_TEST_H_ -#define _IOT_I2C_CFG_TEST_H_ - -/******************************************************************************* - * I2C Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// I2C General Options - -// Instance number -// Instance number used when iot_i2c_open() is called. -// Default: 0 -#define IOT_I2C_CFG_TEST_INST_NUM 0 - -// Default timeout (in msec) -// Default: 500 -#define IOT_I2C_CFG_TEST_DEFAULT_TIMEOUT 500 - -// Default bus speed -// <100000=> Standard mode -// <400000=> Fast mode -// <1000000=> Fast plus mode -// <3400000=> High speed mode -// Default: 400000 -#define IOT_I2C_CFG_TEST_DEFAULT_FREQ 400000 - -// Accept NACK -// If the driver receives NACK during a transfer, the transfer is halted -// immediately but it is not considered as an error. Instead, the driver -// returns success status (useful for test purposes). -// Default: 0 -#define IOT_I2C_CFG_TEST_ACCEPT_NACK 1 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> - -// IOT_I2C_CFG_TEST_ENABLE -// $[GPIO_IOT_I2C_CFG_TEST_ENABLE] -#define IOT_I2C_CFG_TEST_ENABLE_PORT gpioPortB -#define IOT_I2C_CFG_TEST_ENABLE_PIN 0 - -// [GPIO_IOT_I2C_CFG_TEST_ENABLE]$ - -// IOT_I2C_CFG_TEST -// $[I2C_IOT_I2C_CFG_TEST] -#define IOT_I2C_CFG_TEST_PERIPHERAL I2C0 -#define IOT_I2C_CFG_TEST_PERIPHERAL_NO 0 - -// I2C0 SCL on PB02 -#define IOT_I2C_CFG_TEST_SCL_PORT gpioPortB -#define IOT_I2C_CFG_TEST_SCL_PIN 2 - -// I2C0 SDA on PB03 -#define IOT_I2C_CFG_TEST_SDA_PORT gpioPortB -#define IOT_I2C_CFG_TEST_SDA_PIN 3 - -// [I2C_IOT_I2C_CFG_TEST]$ - -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_I2C_CFG_TEST_H_ */ diff --git a/hardware/board/config/brd4109a_brd4002a/iot_pwm_cfg_exp.h b/hardware/board/config/brd4109a_brd4002a/iot_pwm_cfg_exp.h deleted file mode 100644 index 293a6e41d3..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/iot_pwm_cfg_exp.h +++ /dev/null @@ -1,78 +0,0 @@ -/***************************************************************************//** - * @file iot_pwm_cfg_inst.h - * @brief Common I/O PWM instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_PWM_CFG_EXP_H_ -#define _IOT_PWM_CFG_EXP_H_ - -/******************************************************************************* - * PWM Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// PWM General Options - -// Instance number -// Instance number used when iot_pwm_open() is called. -// Default: 0 -#define IOT_PWM_CFG_EXP_INST_NUM 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_PWM_CFG_EXP -// $[TIMER_IOT_PWM_CFG_EXP] -#define IOT_PWM_CFG_EXP_PERIPHERAL TIMER4 -#define IOT_PWM_CFG_EXP_PERIPHERAL_NO 4 - -// TIMER4 CC0 on PB00 -#define IOT_PWM_CFG_EXP_CC0_PORT gpioPortB -#define IOT_PWM_CFG_EXP_CC0_PIN 0 - - - -// [TIMER_IOT_PWM_CFG_EXP]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_PWM_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4109a_brd4002a/iot_pwm_cfg_led0.h b/hardware/board/config/brd4109a_brd4002a/iot_pwm_cfg_led0.h deleted file mode 100644 index 4046cc7328..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/iot_pwm_cfg_led0.h +++ /dev/null @@ -1,78 +0,0 @@ -/***************************************************************************//** - * @file iot_pwm_cfg_inst.h - * @brief Common I/O PWM instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_PWM_CFG_LED0_H_ -#define _IOT_PWM_CFG_LED0_H_ - -/******************************************************************************* - * PWM Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// PWM General Options - -// Instance number -// Instance number used when iot_pwm_open() is called. -// Default: 0 -#define IOT_PWM_CFG_LED0_INST_NUM 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_PWM_CFG_LED0 -// $[TIMER_IOT_PWM_CFG_LED0] -#define IOT_PWM_CFG_LED0_PERIPHERAL TIMER0 -#define IOT_PWM_CFG_LED0_PERIPHERAL_NO 0 - -// TIMER0 CC0 on PB00 -#define IOT_PWM_CFG_LED0_CC0_PORT gpioPortB -#define IOT_PWM_CFG_LED0_CC0_PIN 0 - - - -// [TIMER_IOT_PWM_CFG_LED0]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_PWM_CFG_LED0_H_ */ diff --git a/hardware/board/config/brd4109a_brd4002a/iot_pwm_cfg_led1.h b/hardware/board/config/brd4109a_brd4002a/iot_pwm_cfg_led1.h deleted file mode 100644 index 16ccf4ba71..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/iot_pwm_cfg_led1.h +++ /dev/null @@ -1,78 +0,0 @@ -/***************************************************************************//** - * @file iot_pwm_cfg_inst.h - * @brief Common I/O PWM instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_PWM_CFG_LED1_H_ -#define _IOT_PWM_CFG_LED1_H_ - -/******************************************************************************* - * PWM Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// PWM General Options - -// Instance number -// Instance number used when iot_pwm_open() is called. -// Default: 0 -#define IOT_PWM_CFG_LED1_INST_NUM 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_PWM_CFG_LED1 -// $[TIMER_IOT_PWM_CFG_LED1] -#define IOT_PWM_CFG_LED1_PERIPHERAL TIMER1 -#define IOT_PWM_CFG_LED1_PERIPHERAL_NO 1 - -// TIMER1 CC0 on PB01 -#define IOT_PWM_CFG_LED1_CC0_PORT gpioPortB -#define IOT_PWM_CFG_LED1_CC0_PIN 1 - - - -// [TIMER_IOT_PWM_CFG_LED1]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_PWM_CFG_LED1_H_ */ diff --git a/hardware/board/config/brd4109a_brd4002a/iot_spi_cfg_exp.h b/hardware/board/config/brd4109a_brd4002a/iot_spi_cfg_exp.h deleted file mode 100644 index af0be6c062..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/iot_spi_cfg_exp.h +++ /dev/null @@ -1,128 +0,0 @@ -/***************************************************************************//** - * @file iot_spi_cfg_inst.h - * @brief Common I/O SPI instance configurations. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_SPI_CFG_EXP_H_ -#define _IOT_SPI_CFG_EXP_H_ - -/******************************************************************************* - * SPI Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// SPI General Options - -// Instance number -// Instance number used when iot_spi_open() is called. -// Default: 0 -#define IOT_SPI_CFG_EXP_INST_NUM 0 - -// Default SPI bitrate -// Default: 1000000 -#define IOT_SPI_CFG_EXP_DEFAULT_BITRATE 1000000 - -// Default SPI frame length <4-16> -// Default: 8 -#define IOT_SPI_CFG_EXP_DEFAULT_FRAME_LENGTH 8 - -// Default SPI master/slave mode -// Master -// Slave -#define IOT_SPI_CFG_EXP_DEFAULT_TYPE spidrvMaster - -// Default SPI bit order -// LSB transmitted first -// MSB transmitted first -#define IOT_SPI_CFG_EXP_DEFAULT_BIT_ORDER spidrvBitOrderMsbFirst - -// Default SPI clock mode -// SPI mode 0: CLKPOL=0, CLKPHA=0 -// SPI mode 1: CLKPOL=0, CLKPHA=1 -// SPI mode 2: CLKPOL=1, CLKPHA=0 -// SPI mode 3: CLKPOL=1, CLKPHA=1 -#define IOT_SPI_CFG_EXP_DEFAULT_CLOCK_MODE spidrvClockMode0 - -// Default SPI CS control scheme -// CS controlled by the SPI driver -// CS controlled by the application -#define IOT_SPI_CFG_EXP_DEFAULT_CS_CONTROL spidrvCsControlApplication - -// Default SPI transfer scheme -// Transfer starts immediately -// Transfer starts when the bus is idle -#define IOT_SPI_CFG_EXP_DEFAULT_SLAVE_START_MODE spidrvSlaveStartImmediate - -// Internal Loopback -// Enable USART Internal loopback -// Default: 0 -#define IOT_SPI_CFG_EXP_LOOPBACK 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_SPI_CFG_EXP -// $[USART_IOT_SPI_CFG_EXP] -#define IOT_SPI_CFG_EXP_PERIPHERAL USART0 -#define IOT_SPI_CFG_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define IOT_SPI_CFG_EXP_TX_PORT gpioPortC -#define IOT_SPI_CFG_EXP_TX_PIN 0 - -// USART0 RX on PC01 -#define IOT_SPI_CFG_EXP_RX_PORT gpioPortC -#define IOT_SPI_CFG_EXP_RX_PIN 1 - -// USART0 CLK on PC02 -#define IOT_SPI_CFG_EXP_CLK_PORT gpioPortC -#define IOT_SPI_CFG_EXP_CLK_PIN 2 - -// USART0 CS on PC03 -#define IOT_SPI_CFG_EXP_CS_PORT gpioPortC -#define IOT_SPI_CFG_EXP_CS_PIN 3 - -// [USART_IOT_SPI_CFG_EXP]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_SPI_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4109a_brd4002a/iot_spi_cfg_loopback.h b/hardware/board/config/brd4109a_brd4002a/iot_spi_cfg_loopback.h deleted file mode 100644 index 88a0ff7895..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/iot_spi_cfg_loopback.h +++ /dev/null @@ -1,128 +0,0 @@ -/***************************************************************************//** - * @file iot_spi_cfg_inst.h - * @brief Common I/O SPI instance configurations. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_SPI_CFG_LOOPBACK_H_ -#define _IOT_SPI_CFG_LOOPBACK_H_ - -/******************************************************************************* - * SPI Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// SPI General Options - -// Instance number -// Instance number used when iot_spi_open() is called. -// Default: 0 -#define IOT_SPI_CFG_LOOPBACK_INST_NUM 0 - -// Default SPI bitrate -// Default: 1000000 -#define IOT_SPI_CFG_LOOPBACK_DEFAULT_BITRATE 1000000 - -// Default SPI frame length <4-16> -// Default: 8 -#define IOT_SPI_CFG_LOOPBACK_DEFAULT_FRAME_LENGTH 8 - -// Default SPI master/slave mode -// Master -// Slave -#define IOT_SPI_CFG_LOOPBACK_DEFAULT_TYPE spidrvMaster - -// Default SPI bit order -// LSB transmitted first -// MSB transmitted first -#define IOT_SPI_CFG_LOOPBACK_DEFAULT_BIT_ORDER spidrvBitOrderMsbFirst - -// Default SPI clock mode -// SPI mode 0: CLKPOL=0, CLKPHA=0 -// SPI mode 1: CLKPOL=0, CLKPHA=1 -// SPI mode 2: CLKPOL=1, CLKPHA=0 -// SPI mode 3: CLKPOL=1, CLKPHA=1 -#define IOT_SPI_CFG_LOOPBACK_DEFAULT_CLOCK_MODE spidrvClockMode0 - -// Default SPI CS control scheme -// CS controlled by the SPI driver -// CS controlled by the application -#define IOT_SPI_CFG_LOOPBACK_DEFAULT_CS_CONTROL spidrvCsControlApplication - -// Default SPI transfer scheme -// Transfer starts immediately -// Transfer starts when the bus is idle -#define IOT_SPI_CFG_LOOPBACK_DEFAULT_SLAVE_START_MODE spidrvSlaveStartImmediate - -// Internal Loopback -// Enable USART Internal loopback -// Default: 0 -#define IOT_SPI_CFG_LOOPBACK_LOOPBACK 1 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_SPI_CFG_LOOPBACK -// $[USART_IOT_SPI_CFG_LOOPBACK] -#define IOT_SPI_CFG_LOOPBACK_PERIPHERAL USART0 -#define IOT_SPI_CFG_LOOPBACK_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define IOT_SPI_CFG_LOOPBACK_TX_PORT gpioPortC -#define IOT_SPI_CFG_LOOPBACK_TX_PIN 0 - -// USART0 RX on PC01 -#define IOT_SPI_CFG_LOOPBACK_RX_PORT gpioPortC -#define IOT_SPI_CFG_LOOPBACK_RX_PIN 1 - -// USART0 CLK on PC02 -#define IOT_SPI_CFG_LOOPBACK_CLK_PORT gpioPortC -#define IOT_SPI_CFG_LOOPBACK_CLK_PIN 2 - -// USART0 CS on PC03 -#define IOT_SPI_CFG_LOOPBACK_CS_PORT gpioPortC -#define IOT_SPI_CFG_LOOPBACK_CS_PIN 3 - -// [USART_IOT_SPI_CFG_LOOPBACK]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_SPI_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4109a_brd4002a/iot_uart_cfg_exp.h b/hardware/board/config/brd4109a_brd4002a/iot_uart_cfg_exp.h deleted file mode 100644 index 02f62b7d87..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/iot_uart_cfg_exp.h +++ /dev/null @@ -1,126 +0,0 @@ -/***************************************************************************//** - * @file iot_uart_cfg_inst.h - * @brief Common I/O UART instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_UART_CFG_EXP_H_ -#define _IOT_UART_CFG_EXP_H_ - -/******************************************************************************* - * UART Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// UART General Options - -// Instance number -// Instance number used when iot_uart_open() is called. -// Default: 0 -#define IOT_UART_CFG_EXP_INST_NUM 0 - -// Default baud rate -// Default: 115200 -#define IOT_UART_CFG_EXP_DEFAULT_BAUDRATE 115200 - -// Default number of data bits -// 4 data bits -// 5 data bits -// 6 data bits -// 7 data bits -// 8 data bits -// Default: usartDatabits8 -#define IOT_UART_CFG_EXP_DEFAULT_DATA_BITS usartDatabits8 - -// Default parity mode -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define IOT_UART_CFG_EXP_DEFAULT_PARITY usartNoParity - -// Default number of stop bits -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define IOT_UART_CFG_EXP_DEFAULT_STOP_BITS usartStopbits1 - -// Default hardware flow control -// None -// CTS -// RTS -// CTS/RTS -// Default: usartHwFlowControlNone -#define IOT_UART_CFG_EXP_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone - - -// Internal Loopback -// Enable USART Internal loopback -// Default: 0 -#define IOT_UART_CFG_EXP_LOOPBACK 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_UART_CFG_EXP -// $[USART_IOT_UART_CFG_EXP] -#define IOT_UART_CFG_EXP_PERIPHERAL USART0 -#define IOT_UART_CFG_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define IOT_UART_CFG_EXP_TX_PORT gpioPortA -#define IOT_UART_CFG_EXP_TX_PIN 5 - -// USART0 RX on PA06 -#define IOT_UART_CFG_EXP_RX_PORT gpioPortA -#define IOT_UART_CFG_EXP_RX_PIN 6 - - - - - -// [USART_IOT_UART_CFG_EXP]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_UART_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4109a_brd4002a/iot_uart_cfg_loopback.h b/hardware/board/config/brd4109a_brd4002a/iot_uart_cfg_loopback.h deleted file mode 100644 index 624fa72d23..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/iot_uart_cfg_loopback.h +++ /dev/null @@ -1,132 +0,0 @@ -/***************************************************************************//** - * @file iot_uart_cfg_inst.h - * @brief Common I/O UART instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_UART_CFG_LOOPBACK_H_ -#define _IOT_UART_CFG_LOOPBACK_H_ - -/******************************************************************************* - * UART Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// UART General Options - -// Instance number -// Instance number used when iot_uart_open() is called. -// Default: 0 -#define IOT_UART_CFG_LOOPBACK_INST_NUM 0 - -// Default baud rate -// Default: 115200 -#define IOT_UART_CFG_LOOPBACK_DEFAULT_BAUDRATE 115200 - -// Default number of data bits -// 4 data bits -// 5 data bits -// 6 data bits -// 7 data bits -// 8 data bits -// Default: usartDatabits8 -#define IOT_UART_CFG_LOOPBACK_DEFAULT_DATA_BITS usartDatabits8 - -// Default parity mode -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define IOT_UART_CFG_LOOPBACK_DEFAULT_PARITY usartNoParity - -// Default number of stop bits -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define IOT_UART_CFG_LOOPBACK_DEFAULT_STOP_BITS usartStopbits1 - -// Default hardware flow control -// None -// CTS -// RTS -// CTS/RTS -// Default: usartHwFlowControlNone -#define IOT_UART_CFG_LOOPBACK_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone - - -// Internal Loopback -// Enable USART Internal loopback -// Default: 0 -#define IOT_UART_CFG_LOOPBACK_LOOPBACK 1 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_UART_CFG_LOOPBACK -// $[USART_IOT_UART_CFG_LOOPBACK] -#define IOT_UART_CFG_LOOPBACK_PERIPHERAL USART0 -#define IOT_UART_CFG_LOOPBACK_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define IOT_UART_CFG_LOOPBACK_TX_PORT gpioPortA -#define IOT_UART_CFG_LOOPBACK_TX_PIN 5 - -// USART0 RX on PA06 -#define IOT_UART_CFG_LOOPBACK_RX_PORT gpioPortA -#define IOT_UART_CFG_LOOPBACK_RX_PIN 6 - - - -// USART0 RTS on PA07 -#define IOT_UART_CFG_LOOPBACK_RTS_PORT gpioPortA -#define IOT_UART_CFG_LOOPBACK_RTS_PIN 7 - -// USART0 CTS on PA00 -#define IOT_UART_CFG_LOOPBACK_CTS_PORT gpioPortA -#define IOT_UART_CFG_LOOPBACK_CTS_PIN 0 - -// [USART_IOT_UART_CFG_LOOPBACK]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_UART_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4109a_brd4002a/iot_uart_cfg_vcom.h b/hardware/board/config/brd4109a_brd4002a/iot_uart_cfg_vcom.h deleted file mode 100644 index 2ec40100c2..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/iot_uart_cfg_vcom.h +++ /dev/null @@ -1,132 +0,0 @@ -/***************************************************************************//** - * @file iot_uart_cfg_inst.h - * @brief Common I/O UART instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_UART_CFG_VCOM_H_ -#define _IOT_UART_CFG_VCOM_H_ - -/******************************************************************************* - * UART Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// UART General Options - -// Instance number -// Instance number used when iot_uart_open() is called. -// Default: 0 -#define IOT_UART_CFG_VCOM_INST_NUM 0 - -// Default baud rate -// Default: 115200 -#define IOT_UART_CFG_VCOM_DEFAULT_BAUDRATE 115200 - -// Default number of data bits -// 4 data bits -// 5 data bits -// 6 data bits -// 7 data bits -// 8 data bits -// Default: usartDatabits8 -#define IOT_UART_CFG_VCOM_DEFAULT_DATA_BITS usartDatabits8 - -// Default parity mode -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define IOT_UART_CFG_VCOM_DEFAULT_PARITY usartNoParity - -// Default number of stop bits -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define IOT_UART_CFG_VCOM_DEFAULT_STOP_BITS usartStopbits1 - -// Default hardware flow control -// None -// CTS -// RTS -// CTS/RTS -// Default: usartHwFlowControlNone -#define IOT_UART_CFG_VCOM_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone - - -// Internal Loopback -// Enable USART Internal loopback -// Default: 0 -#define IOT_UART_CFG_VCOM_LOOPBACK 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_UART_CFG_VCOM -// $[USART_IOT_UART_CFG_VCOM] -#define IOT_UART_CFG_VCOM_PERIPHERAL USART0 -#define IOT_UART_CFG_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define IOT_UART_CFG_VCOM_TX_PORT gpioPortA -#define IOT_UART_CFG_VCOM_TX_PIN 5 - -// USART0 RX on PA06 -#define IOT_UART_CFG_VCOM_RX_PORT gpioPortA -#define IOT_UART_CFG_VCOM_RX_PIN 6 - - - -// USART0 RTS on PA07 -#define IOT_UART_CFG_VCOM_RTS_PORT gpioPortA -#define IOT_UART_CFG_VCOM_RTS_PIN 7 - -// USART0 CTS on PA00 -#define IOT_UART_CFG_VCOM_CTS_PORT gpioPortA -#define IOT_UART_CFG_VCOM_CTS_PIN 0 - -// [USART_IOT_UART_CFG_VCOM]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_UART_CFG_VCOM_H_ */ diff --git a/hardware/board/config/brd4109a_brd4002a/legacy_ncp_spi_config.h b/hardware/board/config/brd4109a_brd4002a/legacy_ncp_spi_config.h deleted file mode 100644 index 7a6c182b08..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/legacy_ncp_spi_config.h +++ /dev/null @@ -1,60 +0,0 @@ -/***************************************************************************//** - * @file - * @brief SPIDRV Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef LEGACY_NCP_SPI_CONFIG_H -#define LEGACY_NCP_SPI_CONFIG_H - -// <<< sl:start pin_tool >>> -// LEGACY_NCP_SPI -// $[USART_LEGACY_NCP_SPI] -#define LEGACY_NCP_SPI_PERIPHERAL USART0 -#define LEGACY_NCP_SPI_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define LEGACY_NCP_SPI_TX_PORT gpioPortC -#define LEGACY_NCP_SPI_TX_PIN 0 - -// USART0 RX on PC01 -#define LEGACY_NCP_SPI_RX_PORT gpioPortC -#define LEGACY_NCP_SPI_RX_PIN 1 - -// USART0 CLK on PC02 -#define LEGACY_NCP_SPI_CLK_PORT gpioPortC -#define LEGACY_NCP_SPI_CLK_PIN 2 - -// USART0 CS on PC03 -#define LEGACY_NCP_SPI_CS_PORT gpioPortC -#define LEGACY_NCP_SPI_CS_PIN 3 - -// [USART_LEGACY_NCP_SPI]$ - -// LEGACY_NCP_SPI_HOST_INT -// $[GPIO_LEGACY_NCP_SPI_HOST_INT] -#define LEGACY_NCP_SPI_HOST_INT_PORT gpioPortB -#define LEGACY_NCP_SPI_HOST_INT_PIN 0 - -// [GPIO_LEGACY_NCP_SPI_HOST_INT]$ - -// LEGACY_NCP_SPI_WAKE_INT -// $[GPIO_LEGACY_NCP_SPI_WAKE_INT] -#define LEGACY_NCP_SPI_WAKE_INT_PORT gpioPortB -#define LEGACY_NCP_SPI_WAKE_INT_PIN 1 - -// [GPIO_LEGACY_NCP_SPI_WAKE_INT]$ -// <<< sl:end pin_tool >>> - -#endif // SL_SPIDRV_EXP_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4002a/sl_board_control_config.h b/hardware/board/config/brd4109a_brd4002a/sl_board_control_config.h deleted file mode 100644 index 7912cfea0c..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_board_control_config.h +++ /dev/null @@ -1,76 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Board Control - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_BOARD_CONTROL_CONFIG_H -#define SL_BOARD_CONTROL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Enable Virtual COM UART -// Default: 0 -#define SL_BOARD_ENABLE_VCOM 0 - -// Enable Display -// Default: 0 -#define SL_BOARD_ENABLE_DISPLAY 0 - -// Enable Relative Humidity and Temperature sensor -// Default: 0 -#define SL_BOARD_ENABLE_SENSOR_RHT 0 - -// Disable SPI Flash -// Default: 1 -#define SL_BOARD_DISABLE_MEMORY_SPI 1 - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_BOARD_ENABLE_VCOM -// $[GPIO_SL_BOARD_ENABLE_VCOM] -#define SL_BOARD_ENABLE_VCOM_PORT gpioPortB -#define SL_BOARD_ENABLE_VCOM_PIN 4 -// [GPIO_SL_BOARD_ENABLE_VCOM]$ - -// SL_BOARD_ENABLE_DISPLAY -// $[GPIO_SL_BOARD_ENABLE_DISPLAY] -#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortC -#define SL_BOARD_ENABLE_DISPLAY_PIN 7 -// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ - -// SL_BOARD_ENABLE_SENSOR_RHT -// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] -#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortC -#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 7 -// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_primary_spi_usart_exp_config.h b/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_primary_spi_usart_exp_config.h deleted file mode 100644 index 74a78ebdfc..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_primary_spi_usart_exp_config.h +++ /dev/null @@ -1,94 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC SPI Primary driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_SPI_USART_EXP_PRIMARY_CONFIG_H -#define SL_CPC_DRV_SPI_USART_EXP_PRIMARY_CONFIG_H -#include "spidrv.h" - -// CPC-Primary SPI Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_SPI_EXP_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_SIZE 10 - -// SPI bit rate -// Default: 1000000 -#define SL_CPC_DRV_SPI_EXP_BITRATE 1000000 - -// Receive Interrupt Number on Falling Edge -// Default: 0 -#define SL_CPC_DRV_SPI_EXP_RX_IRQ_FALLING_EDGE_INT_NO 0 - -// Receive Interrupt Number on Rising Edge -// Default: 1 -#define SL_CPC_DRV_SPI_EXP_RX_IRQ_RISING_EDGE_INT_NO 1 -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_SPI_EXP_RX_IRQ -// $[GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ] -#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PORT gpioPortB -#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PIN 0 - -// [GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ]$ - -// SL_CPC_DRV_SPI_EXP -// $[USART_SL_CPC_DRV_SPI_EXP] -#define SL_CPC_DRV_SPI_EXP_PERIPHERAL USART0 -#define SL_CPC_DRV_SPI_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define SL_CPC_DRV_SPI_EXP_TX_PORT gpioPortC -#define SL_CPC_DRV_SPI_EXP_TX_PIN 0 - -// USART0 RX on PC01 -#define SL_CPC_DRV_SPI_EXP_RX_PORT gpioPortC -#define SL_CPC_DRV_SPI_EXP_RX_PIN 1 - -// USART0 CLK on PC02 -#define SL_CPC_DRV_SPI_EXP_CLK_PORT gpioPortC -#define SL_CPC_DRV_SPI_EXP_CLK_PIN 2 - -// USART0 CS on PC03 -#define SL_CPC_DRV_SPI_EXP_CS_PORT gpioPortC -#define SL_CPC_DRV_SPI_EXP_CS_PIN 3 - -// [USART_SL_CPC_DRV_SPI_EXP]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_SPI_EXP_PRIMARY_CONFIG_H */ diff --git a/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_primary_uart_usart_exp_config.h b/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_primary_uart_usart_exp_config.h deleted file mode 100644 index 644f8c29c2..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_primary_uart_usart_exp_config.h +++ /dev/null @@ -1,70 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC UART PRIMARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_USART_EXP_PRIMARY_CONFIG_H -#define SL_CPC_DRV_UART_USART_EXP_PRIMARY_CONFIG_H - -// CPC-Primary UART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 - -// UART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_EXP -// $[USART_SL_CPC_DRV_UART_EXP] -#define SL_CPC_DRV_UART_EXP_PERIPHERAL USART0 -#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define SL_CPC_DRV_UART_EXP_TX_PORT gpioPortC -#define SL_CPC_DRV_UART_EXP_TX_PIN 0 - -// USART0 RX on PC01 -#define SL_CPC_DRV_UART_EXP_RX_PORT gpioPortC -#define SL_CPC_DRV_UART_EXP_RX_PIN 1 - -// [USART_SL_CPC_DRV_UART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_EXP_PRIMARY_CONFIG_H */ diff --git a/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_primary_uart_usart_vcom_config.h b/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_primary_uart_usart_vcom_config.h deleted file mode 100644 index 7d51f4a7be..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_primary_uart_usart_vcom_config.h +++ /dev/null @@ -1,70 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC UART PRIMARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_USART_VCOM_PRIMARY_CONFIG_H -#define SL_CPC_DRV_UART_USART_VCOM_PRIMARY_CONFIG_H - -// CPC-Primary UART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 - -// UART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_VCOM -// $[USART_SL_CPC_DRV_UART_VCOM] -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_RX_PIN 6 - -// [USART_SL_CPC_DRV_UART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_VCOM_PRIMARY_CONFIG_H */ diff --git a/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_secondary_spi_eusart_exp_config.h b/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_secondary_spi_eusart_exp_config.h deleted file mode 100644 index b1b1427dfc..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_secondary_spi_eusart_exp_config.h +++ /dev/null @@ -1,94 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC SPI SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_SPI_EUSART_EXP_SECONDARY_CONFIG_H -#define SL_CPC_DRV_SPI_EUSART_EXP_SECONDARY_CONFIG_H -#include "spidrv.h" - -// CPC-Secondary SPI Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_SPI_EXP_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_SIZE 10 - -// SPI bit rate -// Default: 1000000 -#define SL_CPC_DRV_SPI_EXP_BITRATE 1000000 - -// Chip Select Interrupt Number on Falling Edge -// Default: 10 -#define SL_CPC_DRV_SPI_EXP_CS_FALLING_EDGE_INT_NO 0 - -// Chip Select Interrupt Number on Rising Edge -// Default: 11 -#define SL_CPC_DRV_SPI_EXP_CS_RISING_EDGE_INT_NO 1 -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_SPI_EXP_RX_IRQ -// $[GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ] -#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PORT gpioPortB -#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PIN 0 - -// [GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ]$ - -// SL_CPC_DRV_SPI_EXP -// $[EUSART_SL_CPC_DRV_SPI_EXP] -#define SL_CPC_DRV_SPI_EXP_PERIPHERAL EUSART0 -#define SL_CPC_DRV_SPI_EXP_PERIPHERAL_NO 0 - -// EUSART0 TX on PC00 -#define SL_CPC_DRV_SPI_EXP_TX_PORT gpioPortC -#define SL_CPC_DRV_SPI_EXP_TX_PIN 0 - -// EUSART0 RX on PC01 -#define SL_CPC_DRV_SPI_EXP_RX_PORT gpioPortC -#define SL_CPC_DRV_SPI_EXP_RX_PIN 1 - -// EUSART0 SCLK on PC02 -#define SL_CPC_DRV_SPI_EXP_SCLK_PORT gpioPortC -#define SL_CPC_DRV_SPI_EXP_SCLK_PIN 2 - -// EUSART0 CS on PC03 -#define SL_CPC_DRV_SPI_EXP_CS_PORT gpioPortC -#define SL_CPC_DRV_SPI_EXP_CS_PIN 3 - -// [EUSART_SL_CPC_DRV_SPI_EXP]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_SPI_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_secondary_spi_usart_exp_config.h b/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_secondary_spi_usart_exp_config.h deleted file mode 100644 index 9a4b09987e..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_secondary_spi_usart_exp_config.h +++ /dev/null @@ -1,94 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC SPI SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_SPI_USART_EXP_SECONDARY_CONFIG_H -#define SL_CPC_DRV_SPI_USART_EXP_SECONDARY_CONFIG_H -#include "spidrv.h" - -// CPC-Secondary SPI Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_SPI_EXP_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_SIZE 10 - -// SPI bit rate -// Default: 1000000 -#define SL_CPC_DRV_SPI_EXP_BITRATE 1000000 - -// Chip Select Interrupt Number on Falling Edge -// Default: 10 -#define SL_CPC_DRV_SPI_EXP_CS_FALLING_EDGE_INT_NO 0 - -// Chip Select Interrupt Number on Rising Edge -// Default: 11 -#define SL_CPC_DRV_SPI_EXP_CS_RISING_EDGE_INT_NO 1 -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_SPI_EXP_RX_IRQ -// $[GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ] -#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PORT gpioPortB -#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PIN 0 - -// [GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ]$ - -// SL_CPC_DRV_SPI_EXP -// $[USART_SL_CPC_DRV_SPI_EXP] -#define SL_CPC_DRV_SPI_EXP_PERIPHERAL USART0 -#define SL_CPC_DRV_SPI_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define SL_CPC_DRV_SPI_EXP_TX_PORT gpioPortC -#define SL_CPC_DRV_SPI_EXP_TX_PIN 0 - -// USART0 RX on PC01 -#define SL_CPC_DRV_SPI_EXP_RX_PORT gpioPortC -#define SL_CPC_DRV_SPI_EXP_RX_PIN 1 - -// USART0 CLK on PC02 -#define SL_CPC_DRV_SPI_EXP_CLK_PORT gpioPortC -#define SL_CPC_DRV_SPI_EXP_CLK_PIN 2 - -// USART0 CS on PC03 -#define SL_CPC_DRV_SPI_EXP_CS_PORT gpioPortC -#define SL_CPC_DRV_SPI_EXP_CS_PIN 3 - -// [USART_SL_CPC_DRV_SPI_EXP]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_SPI_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_secondary_uart_eusart_exp_config.h b/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_secondary_uart_eusart_exp_config.h deleted file mode 100644 index d3107de59a..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_secondary_uart_eusart_exp_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC EUSART SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_EUSART_EXP_SECONDARY_CONFIG_H -#define SL_CPC_DRV_UART_EUSART_EXP_SECONDARY_CONFIG_H - -// CPC - Secondary EUSART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 - -// EUSART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 - -// Flow control -// None -// CTS/RTS -// Default: eusartHwFlowControlNone -#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_EXP -// $[EUSART_SL_CPC_DRV_UART_EXP] -#define SL_CPC_DRV_UART_EXP_PERIPHERAL EUSART0 -#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 - -// EUSART0 TX on PC00 -#define SL_CPC_DRV_UART_EXP_TX_PORT gpioPortC -#define SL_CPC_DRV_UART_EXP_TX_PIN 0 - -// EUSART0 RX on PC01 -#define SL_CPC_DRV_UART_EXP_RX_PORT gpioPortC -#define SL_CPC_DRV_UART_EXP_RX_PIN 1 - -// EUSART0 CTS on PC02 -#define SL_CPC_DRV_UART_EXP_CTS_PORT gpioPortC -#define SL_CPC_DRV_UART_EXP_CTS_PIN 2 - -// EUSART0 RTS on PC03 -#define SL_CPC_DRV_UART_EXP_RTS_PORT gpioPortC -#define SL_CPC_DRV_UART_EXP_RTS_PIN 3 - -// [EUSART_SL_CPC_DRV_UART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h b/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h deleted file mode 100644 index 161b31ba0f..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC EUSART SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_EUSART_VCOM_SECONDARY_CONFIG_H -#define SL_CPC_DRV_UART_EUSART_VCOM_SECONDARY_CONFIG_H - -// CPC - Secondary EUSART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 - -// EUSART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 - -// Flow control -// None -// CTS/RTS -// Default: eusartHwFlowControlNone -#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_VCOM -// $[EUSART_SL_CPC_DRV_UART_VCOM] -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL EUSART0 -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 - -// EUSART0 TX on PA05 -#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_TX_PIN 5 - -// EUSART0 RX on PA06 -#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_RX_PIN 6 - -// EUSART0 CTS on PA00 -#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_CTS_PIN 0 - -// EUSART0 RTS on PA07 -#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_RTS_PIN 7 - -// [EUSART_SL_CPC_DRV_UART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_VCOM_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_secondary_uart_usart_exp_config.h b/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_secondary_uart_usart_exp_config.h deleted file mode 100644 index acce477ea4..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_secondary_uart_usart_exp_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC UART SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_USART_EXP_SECONDARY_CONFIG_H -#define SL_CPC_DRV_UART_USART_EXP_SECONDARY_CONFIG_H - -// CPC - Secondary UART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 - -// UART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 - -// Flow control -// None -// CTS/RTS -// Default: usartHwFlowControlCtsAndRts -#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_EXP -// $[USART_SL_CPC_DRV_UART_EXP] -#define SL_CPC_DRV_UART_EXP_PERIPHERAL USART0 -#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define SL_CPC_DRV_UART_EXP_TX_PORT gpioPortC -#define SL_CPC_DRV_UART_EXP_TX_PIN 0 - -// USART0 RX on PC01 -#define SL_CPC_DRV_UART_EXP_RX_PORT gpioPortC -#define SL_CPC_DRV_UART_EXP_RX_PIN 1 - -// USART0 CTS on PC02 -#define SL_CPC_DRV_UART_EXP_CTS_PORT gpioPortC -#define SL_CPC_DRV_UART_EXP_CTS_PIN 2 - -// USART0 RTS on PC03 -#define SL_CPC_DRV_UART_EXP_RTS_PORT gpioPortC -#define SL_CPC_DRV_UART_EXP_RTS_PIN 3 - -// [USART_SL_CPC_DRV_UART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_secondary_uart_usart_vcom_config.h b/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_secondary_uart_usart_vcom_config.h deleted file mode 100644 index 09649bc5e1..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_cpc_drv_secondary_uart_usart_vcom_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC UART SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_USART_VCOM_SECONDARY_CONFIG_H -#define SL_CPC_DRV_UART_USART_VCOM_SECONDARY_CONFIG_H - -// CPC - Secondary UART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 - -// UART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 - -// Flow control -// None -// CTS/RTS -// Default: usartHwFlowControlCtsAndRts -#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_VCOM -// $[USART_SL_CPC_DRV_UART_VCOM] -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_RX_PIN 6 - -// USART0 CTS on PA00 -#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_CTS_PIN 0 - -// USART0 RTS on PA07 -#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_RTS_PIN 7 - -// [USART_SL_CPC_DRV_UART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_VCOM_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4109a_brd4002a/sl_device_init_hfxo_config.h b/hardware/board/config/brd4109a_brd4002a/sl_device_init_hfxo_config.h deleted file mode 100644 index b0938ac495..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_device_init_hfxo_config.h +++ /dev/null @@ -1,53 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_HFXO Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H -#define SL_DEVICE_INIT_HFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// External sine wave -// Default: cmuHfxoOscMode_Crystal -#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal - -// Frequency <38000000-40000000> -// Default: 38400000 -#define SL_DEVICE_INIT_HFXO_FREQ 38400000 - -// CTUNE <0-255> -// Default: 140 -#define SL_DEVICE_INIT_HFXO_CTUNE 120 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4002a/sl_device_init_lfxo_config.h b/hardware/board/config/brd4109a_brd4002a/sl_device_init_lfxo_config.h deleted file mode 100644 index 0e1f4147bf..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_device_init_lfxo_config.h +++ /dev/null @@ -1,66 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_LFXO Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H -#define SL_DEVICE_INIT_LFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// AC-coupled buffer -// External digital clock -// Default: cmuLfxoOscMode_Crystal -#define SL_DEVICE_INIT_LFXO_MODE cmuLfxoOscMode_Crystal - -// CTUNE <0-127> -// Default: 63 -#define SL_DEVICE_INIT_LFXO_CTUNE 37 - -// LFXO precision in PPM <0-65535> -// Default: 500 -#define SL_DEVICE_INIT_LFXO_PRECISION 100 - -// Startup Timeout Delay -// -// 2 cycles -// 256 cycles -// 1K cycles -// 2K cycles -// 4K cycles -// 8K cycles -// 16K cycles -// 32K cycles -// Default: cmuLfxoStartupDelay_4KCycles -#define SL_DEVICE_INIT_LFXO_TIMEOUT cmuLfxoStartupDelay_4KCycles -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4002a/sl_i2cspm_sensor_config.h b/hardware/board/config/brd4109a_brd4002a/sl_i2cspm_sensor_config.h deleted file mode 100644 index 738fcafa39..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_i2cspm_sensor_config.h +++ /dev/null @@ -1,58 +0,0 @@ -/***************************************************************************//** - * @file - * @brief I2CSPM Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_I2CSPM_SENSOR_CONFIG_H -#define SL_I2CSPM_SENSOR_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu - -// I2CSPM settings - -// Reference clock frequency -// Frequency in Hz of the reference clock. -// Select 0 to use the frequency of the currently selected clock. -// Default: 0 -#define SL_I2CSPM_SENSOR_REFERENCE_CLOCK 0 - -// Speed mode -// <0=> Standard mode (100kbit/s) -// <1=> Fast mode (400kbit/s) -// <2=> Fast mode plus (1Mbit/s) -// Default: 0 -#define SL_I2CSPM_SENSOR_SPEED_MODE 0 -// end I2CSPM config - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_I2CSPM_SENSOR -// $[I2C_SL_I2CSPM_SENSOR] -#define SL_I2CSPM_SENSOR_PERIPHERAL I2C0 -#define SL_I2CSPM_SENSOR_PERIPHERAL_NO 0 - -// I2C0 SCL on PB02 -#define SL_I2CSPM_SENSOR_SCL_PORT gpioPortB -#define SL_I2CSPM_SENSOR_SCL_PIN 2 - -// I2C0 SDA on PB03 -#define SL_I2CSPM_SENSOR_SDA_PORT gpioPortB -#define SL_I2CSPM_SENSOR_SDA_PIN 3 - -// [I2C_SL_I2CSPM_SENSOR]$ -// <<< sl:end pin_tool >>> - -#endif // SL_I2CSPM_SENSOR_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4002a/sl_iostream_eusart_exp_config.h b/hardware/board/config/brd4109a_brd4002a/sl_iostream_eusart_exp_config.h deleted file mode 100644 index 298b5d2c75..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_iostream_eusart_exp_config.h +++ /dev/null @@ -1,107 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_EUSART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_EUSART_EXP_CONFIG_H -#define SL_IOSTREAM_EUSART_EXP_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// EUART settings - -// Enable High frequency mode -// Default: 1 -#define SL_IOSTREAM_EUSART_EXP_ENABLE_HIGH_FREQUENCY 1 - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_EUSART_EXP_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: eusartNoParity -#define SL_IOSTREAM_EUSART_EXP_PARITY eusartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: eusartStopbits1 -#define SL_IOSTREAM_EUSART_EXP_STOP_BITS eusartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: eusartHwFlowControlNone -#define SL_IOSTREAM_EUSART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlNone - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_EUSART_EXP_RX_BUFFER_SIZE 32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_EUSART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_EUSART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_EUSART_EXP -// $[EUSART_SL_IOSTREAM_EUSART_EXP] -#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL EUSART0 -#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL_NO 0 - -// EUSART0 TX on PA05 -#define SL_IOSTREAM_EUSART_EXP_TX_PORT gpioPortA -#define SL_IOSTREAM_EUSART_EXP_TX_PIN 5 - -// EUSART0 RX on PA06 -#define SL_IOSTREAM_EUSART_EXP_RX_PORT gpioPortA -#define SL_IOSTREAM_EUSART_EXP_RX_PIN 6 - - - -// [EUSART_SL_IOSTREAM_EUSART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4109a_brd4002a/sl_iostream_eusart_vcom_config.h b/hardware/board/config/brd4109a_brd4002a/sl_iostream_eusart_vcom_config.h deleted file mode 100644 index 237dca5fe7..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_iostream_eusart_vcom_config.h +++ /dev/null @@ -1,113 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_EUSART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_EUSART_VCOM_CONFIG_H -#define SL_IOSTREAM_EUSART_VCOM_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// EUART settings - -// Enable High frequency mode -// Default: 1 -#define SL_IOSTREAM_EUSART_VCOM_ENABLE_HIGH_FREQUENCY 1 - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_EUSART_VCOM_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: eusartNoParity -#define SL_IOSTREAM_EUSART_VCOM_PARITY eusartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: eusartStopbits1 -#define SL_IOSTREAM_EUSART_VCOM_STOP_BITS eusartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: eusartHwFlowControlNone -#define SL_IOSTREAM_EUSART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_EUSART_VCOM_RX_BUFFER_SIZE 32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_EUSART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_EUSART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_EUSART_VCOM -// $[EUSART_SL_IOSTREAM_EUSART_VCOM] -#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL EUSART0 -#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL_NO 0 - -// EUSART0 TX on PA05 -#define SL_IOSTREAM_EUSART_VCOM_TX_PORT gpioPortA -#define SL_IOSTREAM_EUSART_VCOM_TX_PIN 5 - -// EUSART0 RX on PA06 -#define SL_IOSTREAM_EUSART_VCOM_RX_PORT gpioPortA -#define SL_IOSTREAM_EUSART_VCOM_RX_PIN 6 - -// EUSART0 CTS on PA00 -#define SL_IOSTREAM_EUSART_VCOM_CTS_PORT gpioPortA -#define SL_IOSTREAM_EUSART_VCOM_CTS_PIN 0 - -// EUSART0 RTS on PA07 -#define SL_IOSTREAM_EUSART_VCOM_RTS_PORT gpioPortA -#define SL_IOSTREAM_EUSART_VCOM_RTS_PIN 7 - -// [EUSART_SL_IOSTREAM_EUSART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4109a_brd4002a/sl_iostream_usart_exp_config.h b/hardware/board/config/brd4109a_brd4002a/sl_iostream_usart_exp_config.h deleted file mode 100644 index 8669faa1a4..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_iostream_usart_exp_config.h +++ /dev/null @@ -1,103 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_USART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_USART_EXP_CONFIG_H -#define SL_IOSTREAM_USART_EXP_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// USART settings - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_USART_EXP_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_IOSTREAM_USART_EXP_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_IOSTREAM_USART_EXP_STOP_BITS usartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: usartHwFlowControlNone -#define SL_IOSTREAM_USART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlNone - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_USART_EXP_RX_BUFFER_SIZE 32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_USART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_USART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_USART_EXP -// $[USART_SL_IOSTREAM_USART_EXP] -#define SL_IOSTREAM_USART_EXP_PERIPHERAL USART0 -#define SL_IOSTREAM_USART_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_IOSTREAM_USART_EXP_TX_PORT gpioPortA -#define SL_IOSTREAM_USART_EXP_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_IOSTREAM_USART_EXP_RX_PORT gpioPortA -#define SL_IOSTREAM_USART_EXP_RX_PIN 6 - - - -// [USART_SL_IOSTREAM_USART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4109a_brd4002a/sl_iostream_usart_vcom_config.h b/hardware/board/config/brd4109a_brd4002a/sl_iostream_usart_vcom_config.h deleted file mode 100644 index f67a5a7f97..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_iostream_usart_vcom_config.h +++ /dev/null @@ -1,109 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_USART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H -#define SL_IOSTREAM_USART_VCOM_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// USART settings - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_USART_VCOM_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: usartHwFlowControlNone -#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_USART_VCOM -// $[USART_SL_IOSTREAM_USART_VCOM] -#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART0 -#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_IOSTREAM_USART_VCOM_TX_PORT gpioPortA -#define SL_IOSTREAM_USART_VCOM_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_IOSTREAM_USART_VCOM_RX_PORT gpioPortA -#define SL_IOSTREAM_USART_VCOM_RX_PIN 6 - -// USART0 CTS on PA00 -#define SL_IOSTREAM_USART_VCOM_CTS_PORT gpioPortA -#define SL_IOSTREAM_USART_VCOM_CTS_PIN 0 - -// USART0 RTS on PA07 -#define SL_IOSTREAM_USART_VCOM_RTS_PORT gpioPortA -#define SL_IOSTREAM_USART_VCOM_RTS_PIN 7 - -// [USART_SL_IOSTREAM_USART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4109a_brd4002a/sl_joystick_config.h b/hardware/board/config/brd4109a_brd4002a/sl_joystick_config.h deleted file mode 100644 index da2344ee46..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_joystick_config.h +++ /dev/null @@ -1,114 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Joystick Driver User Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_JOYSTICK_CONFIG_H -#define SL_JOYSTICK_CONFIG_H - -#include "em_gpio.h" - -// <<< Use Configuration Wizard in Context Menu >>> - -// Joystick Voltage value Configuration - -// Reference voltage value for analog Joystick signal -// Vref magnitude expressed in millivolts. As per Joystick Hardware on Wireless Pro Kit, Vref = AVDD = 3300 mV -// Default: 3300 -#define REFERENCE_VOLTAGE 3300 - -// Center position mV value -// Default: 3 -#define JOYSTICK_MV_C 3 - -// North position mV value -// Default: 2831 -#define JOYSTICK_MV_N 2831 - -// East position mV value -// Default: 2533 -#define JOYSTICK_MV_E 2533 - -// South position mV value -// Default: 1650 -#define JOYSTICK_MV_S 1650 - -// West position mV value -// Default: 1980 -#define JOYSTICK_MV_W 1980 - -// Joystick error mV value when enabled for Cardinal Directions only -// This value will not be used when joystick is enabled for secondary directions -// Default: 150 -#define JOYSTICK_MV_ERR_CARDINAL_ONLY 150 - -// Enable secondary directions -// Enables secondary directions (NW, NE, SW, SE) -// Note: Joystick Hardware on Wireless Pro Kit does not support Secondary directions -#ifndef ENABLE_SECONDARY_DIRECTIONS -#define ENABLE_SECONDARY_DIRECTIONS 1 -#endif -// Northeast position mV value -// Default: 2247 -#define JOYSTICK_MV_NE 2247 - -// Northwest position mV value -// Default: 1801 -#define JOYSTICK_MV_NW 1801 - -// Southeast position mV value -// Default: 1433 -#define JOYSTICK_MV_SE 1433 - -// Southwest position mV value -// Default: 1238 -#define JOYSTICK_MV_SW 1238 - -// Joystick error mV value when enabled for Cardinal and Secondary Directions -// Default: 75 -#define JOYSTICK_MV_ERR_CARDINAL_AND_SECONDARY 75 - -// end Joystick direction secondary directions selection - -// end Joystick Voltage value Configuration - -// Joystick signal sampling rate Configuration - -// Joystick signal sampling rate [samples/second] -// Sets the sampling rate for Joystick signal -// <50000=> 100 samples/second -// <5000=> 1000 samples/second -// <1000=> 5000 samples/second -// <500=> 10000 samples/second -// <200=> 25000 samples/second -// Default: 50000 -#define TIMER_CYCLES 50000 - -// end Joystick signal sampling rate Configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_JOYSTICK -// $[GPIO_SL_JOYSTICK] -#define SL_JOYSTICK_PORT gpioPortD -#define SL_JOYSTICK_PIN 3 - -// [GPIO_SL_JOYSTICK]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_JOYSTICK_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4002a/sl_memlcd_eusart_config.h b/hardware/board/config/brd4109a_brd4002a/sl_memlcd_eusart_config.h deleted file mode 100644 index b240556b3c..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_memlcd_eusart_config.h +++ /dev/null @@ -1,53 +0,0 @@ -/***************************************************************************//** - * @file - * @brief SPI abstraction used by memory lcd display - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_MEMLCD_CONFIG_H -#define SL_MEMLCD_CONFIG_H - -// <<< sl:start pin_tool >>> -// SL_MEMLCD_SPI -// $[EUSART_SL_MEMLCD_SPI] -#define SL_MEMLCD_SPI_PERIPHERAL EUSART0 -#define SL_MEMLCD_SPI_PERIPHERAL_NO 0 - -// EUSART0 TX on PC00 -#define SL_MEMLCD_SPI_TX_PORT gpioPortC -#define SL_MEMLCD_SPI_TX_PIN 0 - -// EUSART0 SCLK on PC02 -#define SL_MEMLCD_SPI_SCLK_PORT gpioPortC -#define SL_MEMLCD_SPI_SCLK_PIN 2 - -// [EUSART_SL_MEMLCD_SPI]$ - -// SL_MEMLCD_SPI_CS -// $[GPIO_SL_MEMLCD_SPI_CS] -#define SL_MEMLCD_SPI_CS_PORT gpioPortC -#define SL_MEMLCD_SPI_CS_PIN 6 - -// [GPIO_SL_MEMLCD_SPI_CS]$ - -// SL_MEMLCD_EXTCOMIN -// $[GPIO_SL_MEMLCD_EXTCOMIN] -#define SL_MEMLCD_EXTCOMIN_PORT gpioPortD -#define SL_MEMLCD_EXTCOMIN_PIN 2 - -// [GPIO_SL_MEMLCD_EXTCOMIN]$ - -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4109a_brd4002a/sl_memlcd_usart_config.h b/hardware/board/config/brd4109a_brd4002a/sl_memlcd_usart_config.h deleted file mode 100644 index 2e7d32028e..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_memlcd_usart_config.h +++ /dev/null @@ -1,53 +0,0 @@ -/***************************************************************************//** - * @file - * @brief SPI abstraction used by memory lcd display - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_MEMLCD_CONFIG_H -#define SL_MEMLCD_CONFIG_H - -// <<< sl:start pin_tool >>> -// SL_MEMLCD_SPI -// $[USART_SL_MEMLCD_SPI] -#define SL_MEMLCD_SPI_PERIPHERAL USART0 -#define SL_MEMLCD_SPI_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define SL_MEMLCD_SPI_TX_PORT gpioPortC -#define SL_MEMLCD_SPI_TX_PIN 0 - -// USART0 CLK on PC02 -#define SL_MEMLCD_SPI_CLK_PORT gpioPortC -#define SL_MEMLCD_SPI_CLK_PIN 2 - -// [USART_SL_MEMLCD_SPI]$ - -// SL_MEMLCD_SPI_CS -// $[GPIO_SL_MEMLCD_SPI_CS] -#define SL_MEMLCD_SPI_CS_PORT gpioPortC -#define SL_MEMLCD_SPI_CS_PIN 6 - -// [GPIO_SL_MEMLCD_SPI_CS]$ - -// SL_MEMLCD_EXTCOMIN -// $[GPIO_SL_MEMLCD_EXTCOMIN] -#define SL_MEMLCD_EXTCOMIN_PORT gpioPortD -#define SL_MEMLCD_EXTCOMIN_PIN 2 - -// [GPIO_SL_MEMLCD_EXTCOMIN]$ - -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4109a_brd4002a/sl_mx25_flash_shutdown_eusart_config.h b/hardware/board/config/brd4109a_brd4002a/sl_mx25_flash_shutdown_eusart_config.h deleted file mode 100644 index 1e80a474b3..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_mx25_flash_shutdown_eusart_config.h +++ /dev/null @@ -1,51 +0,0 @@ -/***************************************************************************//** - * @file - * @brief SL_MX25_FLASH_SHUTDOWN_USART Config - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H -#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H - -// <<< sl:start pin_tool >>> -// {eusart signal=TX,RX,SCLK} SL_MX25_FLASH_SHUTDOWN -// [EUSART_SL_MX25_FLASH_SHUTDOWN] -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL EUSART0 -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 - -// EUSART0 TX on PC00 -#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortC -#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 0 - -// EUSART0 RX on PC01 -#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortC -#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 - -// EUSART0 SCLK on PC02 -#define SL_MX25_FLASH_SHUTDOWN_SCLK_PORT gpioPortC -#define SL_MX25_FLASH_SHUTDOWN_SCLK_PIN 2 - -// [EUSART_SL_MX25_FLASH_SHUTDOWN] - -// SL_MX25_FLASH_SHUTDOWN_CS - -// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] -#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortA -#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 - -// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4002a/sl_mx25_flash_shutdown_usart_config.h b/hardware/board/config/brd4109a_brd4002a/sl_mx25_flash_shutdown_usart_config.h deleted file mode 100644 index e80f7982d4..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_mx25_flash_shutdown_usart_config.h +++ /dev/null @@ -1,51 +0,0 @@ -/***************************************************************************//** - * @file - * @brief SL_MX25_FLASH_SHUTDOWN_USART Config - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H -#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H - -// <<< sl:start pin_tool >>> -// {usart signal=TX,RX,CLK} SL_MX25_FLASH_SHUTDOWN -// [USART_SL_MX25_FLASH_SHUTDOWN] -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL USART0 -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortC -#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 0 - -// USART0 RX on PC01 -#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortC -#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 - -// USART0 CLK on PC02 -#define SL_MX25_FLASH_SHUTDOWN_CLK_PORT gpioPortC -#define SL_MX25_FLASH_SHUTDOWN_CLK_PIN 2 - -// [USART_SL_MX25_FLASH_SHUTDOWN] - -// SL_MX25_FLASH_SHUTDOWN_CS - -// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] -#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortA -#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 - -// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4002a/sl_ncp_spidrv_usart_config.h b/hardware/board/config/brd4109a_brd4002a/sl_ncp_spidrv_usart_config.h deleted file mode 100644 index 71fa842005..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_ncp_spidrv_usart_config.h +++ /dev/null @@ -1,94 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Open thread NCP spidrv usart configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_NCP_SPIDRV_USART_CONFIG_H -#define SL_NCP_SPIDRV_USART_CONFIG_H -#include "spidrv.h" - -// NCP spidrv usart Configuration - -// Bit order on the SPI bus -// LSB transmitted first -// MSB transmitted first -#define SL_NCP_SPIDRV_USART_BIT_ORDER spidrvBitOrderMsbFirst - -// SPI clock mode -// SPI mode 0: CLKPOL=0, CLKPHA=0 -// SPI mode 1: CLKPOL=0, CLKPHA=1 -// SPI mode 2: CLKPOL=1, CLKPHA=0 -// SPI mode 3: CLKPOL=1, CLKPHA=1 -#define SL_NCP_SPIDRV_USART_CLOCK_MODE spidrvClockMode0 - -// Chip Select Interrupt Number on Falling Edge -// Default: 10 -#define SL_NCP_SPIDRV_USART_CS_FALLING_EDGE_INT_NO 0 - -// Chip Select Interrupt Number on Rising Edge -// Default: 9 -#define SL_NCP_SPIDRV_USART_CS_RISING_EDGE_INT_NO 1 -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_NCP_SPIDRV_USART_HOST_INT -// $[GPIO_SL_NCP_SPIDRV_USART_HOST_INT] -#define SL_NCP_SPIDRV_USART_HOST_INT_PORT gpioPortB -#define SL_NCP_SPIDRV_USART_HOST_INT_PIN 0 - -// [GPIO_SL_NCP_SPIDRV_USART_HOST_INT]$ - -// SL_NCP_SPIDRV_USART -// $[USART_SL_NCP_SPIDRV_USART] -#define SL_NCP_SPIDRV_USART_PERIPHERAL USART0 -#define SL_NCP_SPIDRV_USART_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define SL_NCP_SPIDRV_USART_TX_PORT gpioPortC -#define SL_NCP_SPIDRV_USART_TX_PIN 0 - -// USART0 RX on PC01 -#define SL_NCP_SPIDRV_USART_RX_PORT gpioPortC -#define SL_NCP_SPIDRV_USART_RX_PIN 1 - -// USART0 CLK on PC02 -#define SL_NCP_SPIDRV_USART_CLK_PORT gpioPortC -#define SL_NCP_SPIDRV_USART_CLK_PIN 2 - -// USART0 CS on PC03 -#define SL_NCP_SPIDRV_USART_CS_PORT gpioPortC -#define SL_NCP_SPIDRV_USART_CS_PIN 3 - -// [USART_SL_NCP_SPIDRV_USART]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_NCP_SPIDRV_USART_CONFIG_H */ diff --git a/hardware/board/config/brd4109a_brd4002a/sl_pwm_init_led0_config.h b/hardware/board/config/brd4109a_brd4002a/sl_pwm_init_led0_config.h deleted file mode 100644 index c3e83a4a81..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_pwm_init_led0_config.h +++ /dev/null @@ -1,62 +0,0 @@ -/***************************************************************************//** - * @file - * @brief PWM Driver - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef PWM_INIT_LED0_CONFIG_H -#define PWM_INIT_LED0_CONFIG_H - -#ifdef __cplusplus -extern "C" { -#endif - -// <<< Use Configuration Wizard in Context Menu >>> - -// PWM configuration - -// PWM frequency [Hz] -// Default: 10000 -#define SL_PWM_LED0_FREQUENCY 10000 - -// Polarity -// Active high -// Active low -// Default: PWM_ACTIVE_HIGH -#define SL_PWM_LED0_POLARITY PWM_ACTIVE_LOW -// end pwm configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_PWM_LED0 -// $[TIMER_SL_PWM_LED0] -#define SL_PWM_LED0_PERIPHERAL TIMER0 -#define SL_PWM_LED0_PERIPHERAL_NO 0 - -#define SL_PWM_LED0_OUTPUT_CHANNEL 0 -// TIMER0 CC0 on PB00 -#define SL_PWM_LED0_OUTPUT_PORT gpioPortB -#define SL_PWM_LED0_OUTPUT_PIN 0 - -// [TIMER_SL_PWM_LED0]$ - -// <<< sl:end pin_tool >>> - -#ifdef __cplusplus -} -#endif - -#endif // PWM_INIT_LED0_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4002a/sl_pwm_init_led1_config.h b/hardware/board/config/brd4109a_brd4002a/sl_pwm_init_led1_config.h deleted file mode 100644 index c77a6773a9..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_pwm_init_led1_config.h +++ /dev/null @@ -1,62 +0,0 @@ -/***************************************************************************//** - * @file - * @brief PWM Driver - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef PWM_INIT_LED1_CONFIG_H -#define PWM_INIT_LED1_CONFIG_H - -#ifdef __cplusplus -extern "C" { -#endif - -// <<< Use Configuration Wizard in Context Menu >>> - -// PWM configuration - -// PWM frequency [Hz] -// Default: 10000 -#define SL_PWM_LED1_FREQUENCY 10000 - -// Polarity -// Active high -// Active low -// Default: PWM_ACTIVE_HIGH -#define SL_PWM_LED1_POLARITY PWM_ACTIVE_LOW -// end pwm configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_PWM_LED1 -// $[TIMER_SL_PWM_LED1] -#define SL_PWM_LED1_PERIPHERAL TIMER1 -#define SL_PWM_LED1_PERIPHERAL_NO 1 - -#define SL_PWM_LED1_OUTPUT_CHANNEL 0 -// TIMER1 CC0 on PB01 -#define SL_PWM_LED1_OUTPUT_PORT gpioPortB -#define SL_PWM_LED1_OUTPUT_PIN 1 - -// [TIMER_SL_PWM_LED1]$ - -// <<< sl:end pin_tool >>> - -#ifdef __cplusplus -} -#endif - -#endif // PWM_INIT_LED1_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4002a/sl_rail_util_pa_config.h b/hardware/board/config/brd4109a_brd4002a/sl_rail_util_pa_config.h deleted file mode 100644 index a1a5fce586..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_rail_util_pa_config.h +++ /dev/null @@ -1,81 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Power Amplifier configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_RAIL_UTIL_PA_CONFIG_H -#define SL_RAIL_UTIL_PA_CONFIG_H - -#include "rail_types.h" - -// <<< Use Configuration Wizard in Context Menu >>> - -// PA Configuration -// Initial PA Power (deci-dBm, 100 = 10.0 dBm) -// Default: 100 -#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 - -// PA Ramp Time (microseconds) -// <0-65535:1> -// Default: 2 -#define SL_RAIL_UTIL_PA_RAMP_TIME_US 2 -// Milli-volts on PA supply pin (PA_VDD) -// <0-65535:1> -// Default: 3300 -#define SL_RAIL_UTIL_PA_VOLTAGE_MV 1800 -// 2.4 GHz PA Selection -// Highest Possible -// High Power (chip-specific) -// Low Power -// Disable -// Default: RAIL_TX_POWER_MODE_2P4GIG_HIGHEST -#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HIGHEST -// Sub-1 GHz PA Selection -// Disable -// Default: RAIL_TX_POWER_MODE_NONE -#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE -// - -// PA Curve Configuration -// Header file containing custom PA curves -// Default: "pa_curves_efr32.h" -#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" -// Header file containing PA curve types -// Default: "pa_curve_types_efr32.h" -#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" -// - -// PA Calibration Configuration -// Apply PA Calibration Factory Offset -// Default: 1 -#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 -// - -// <<< end of configuration section >>> - -#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4002a/sl_rail_util_pti_config.h b/hardware/board/config/brd4109a_brd4002a/sl_rail_util_pti_config.h deleted file mode 100644 index 90431d7936..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_rail_util_pti_config.h +++ /dev/null @@ -1,73 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Packet Trace Information configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_RAIL_UTIL_PTI_CONFIG_H -#define SL_RAIL_UTIL_PTI_CONFIG_H - -#include "rail_types.h" - -// <<< Use Configuration Wizard in Context Menu >>> -// PTI Configuration - -// PTI mode -// UART -// UART onewire -// SPI -// Disabled -// Default: RAIL_PTI_MODE_UART -#define SL_RAIL_UTIL_PTI_MODE RAIL_PTI_MODE_UART - -// PTI Baud Rate (Hertz) -// <147800-20000000:1> -// Default: 1600000 -#define SL_RAIL_UTIL_PTI_BAUD_RATE_HZ 1600000 - -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_RAIL_UTIL_PTI -// $[PTI_SL_RAIL_UTIL_PTI] -#define SL_RAIL_UTIL_PTI_PERIPHERAL PTI - -// PTI DOUT on PC04 -#define SL_RAIL_UTIL_PTI_DOUT_PORT gpioPortC -#define SL_RAIL_UTIL_PTI_DOUT_PIN 4 - -// PTI DFRAME on PC05 -#define SL_RAIL_UTIL_PTI_DFRAME_PORT gpioPortC -#define SL_RAIL_UTIL_PTI_DFRAME_PIN 5 - - -// [PTI_SL_RAIL_UTIL_PTI]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_RAIL_UTIL_PTI_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4002a/sl_simple_led_led0_config.h b/hardware/board/config/brd4109a_brd4002a/sl_simple_led_led0_config.h deleted file mode 100644 index 88613fa73e..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_simple_led_led0_config.h +++ /dev/null @@ -1,44 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_LED_LED0_CONFIG_H -#define SL_SIMPLE_LED_LED0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple LED configuration -// -// Active low -// Active high -// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH -#define SL_SIMPLE_LED_LED0_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_LED_LED0 -// $[GPIO_SL_SIMPLE_LED_LED0] -#define SL_SIMPLE_LED_LED0_PORT gpioPortB -#define SL_SIMPLE_LED_LED0_PIN 0 - -// [GPIO_SL_SIMPLE_LED_LED0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_LED_LED0_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4002a/sl_simple_led_led1_config.h b/hardware/board/config/brd4109a_brd4002a/sl_simple_led_led1_config.h deleted file mode 100644 index 2cbc3cb4dd..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_simple_led_led1_config.h +++ /dev/null @@ -1,44 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_LED_LED1_CONFIG_H -#define SL_SIMPLE_LED_LED1_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple LED configuration -// -// Active low -// Active high -// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH -#define SL_SIMPLE_LED_LED1_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_LED_LED1 -// $[GPIO_SL_SIMPLE_LED_LED1] -#define SL_SIMPLE_LED_LED1_PORT gpioPortB -#define SL_SIMPLE_LED_LED1_PIN 1 - -// [GPIO_SL_SIMPLE_LED_LED1]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_LED_LED1_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4002a/sl_spidrv_eusart_exp_config.h b/hardware/board/config/brd4109a_brd4002a/sl_spidrv_eusart_exp_config.h deleted file mode 100644 index 430ec2f9c5..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_spidrv_eusart_exp_config.h +++ /dev/null @@ -1,89 +0,0 @@ -/***************************************************************************//** - * @file - * @brief SPIDRV_EUSART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SPIDRV_EUSART_EXP_CONFIG_H -#define SL_SPIDRV_EUSART_EXP_CONFIG_H - -#include "spidrv.h" - -// <<< Use Configuration Wizard in Context Menu >>> -// SPIDRV settings - -// SPI bitrate -// Default: 1000000 -#define SL_SPIDRV_EUSART_EXP_BITRATE 1000000 - -// SPI frame length <7-16> -// Default: 8 -#define SL_SPIDRV_EUSART_EXP_FRAME_LENGTH 8 - -// SPI mode -// Master -// Slave -#define SL_SPIDRV_EUSART_EXP_TYPE spidrvMaster - -// Bit order on the SPI bus -// LSB transmitted first -// MSB transmitted first -#define SL_SPIDRV_EUSART_EXP_BIT_ORDER spidrvBitOrderMsbFirst - -// SPI clock mode -// SPI mode 0: CLKPOL=0, CLKPHA=0 -// SPI mode 1: CLKPOL=0, CLKPHA=1 -// SPI mode 2: CLKPOL=1, CLKPHA=0 -// SPI mode 3: CLKPOL=1, CLKPHA=1 -#define SL_SPIDRV_EUSART_EXP_CLOCK_MODE spidrvClockMode0 - -// SPI master chip select (CS) control scheme. -// CS controlled by the SPI driver -// CS controlled by the application -#define SL_SPIDRV_EUSART_EXP_CS_CONTROL spidrvCsControlAuto - -// SPI slave transfer start scheme -// Transfer starts immediately -// Transfer starts when the bus is idle (CS deasserted) -// Only applies if instance type is spidrvSlave -#define SL_SPIDRV_EUSART_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_SPIDRV_EUSART_EXP -// $[EUSART_SL_SPIDRV_EUSART_EXP] -#define SL_SPIDRV_EUSART_EXP_PERIPHERAL EUSART0 -#define SL_SPIDRV_EUSART_EXP_PERIPHERAL_NO 0 - -// EUSART0 TX on PC00 -#define SL_SPIDRV_EUSART_EXP_TX_PORT gpioPortC -#define SL_SPIDRV_EUSART_EXP_TX_PIN 0 - -// EUSART0 RX on PC01 -#define SL_SPIDRV_EUSART_EXP_RX_PORT gpioPortC -#define SL_SPIDRV_EUSART_EXP_RX_PIN 1 - -// EUSART0 SCLK on PC02 -#define SL_SPIDRV_EUSART_EXP_SCLK_PORT gpioPortC -#define SL_SPIDRV_EUSART_EXP_SCLK_PIN 2 - -// EUSART0 CS on PC03 -#define SL_SPIDRV_EUSART_EXP_CS_PORT gpioPortC -#define SL_SPIDRV_EUSART_EXP_CS_PIN 3 - -// [EUSART_SL_SPIDRV_EUSART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif // SL_SPIDRV_EUSART_EXP_CONFIG_HEUSART_ diff --git a/hardware/board/config/brd4109a_brd4002a/sl_spidrv_exp_config.h b/hardware/board/config/brd4109a_brd4002a/sl_spidrv_exp_config.h deleted file mode 100644 index 64cda25258..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_spidrv_exp_config.h +++ /dev/null @@ -1,89 +0,0 @@ -/***************************************************************************//** - * @file - * @brief SPIDRV Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SPIDRV_EXP_CONFIG_H -#define SL_SPIDRV_EXP_CONFIG_H - -#include "spidrv.h" - -// <<< Use Configuration Wizard in Context Menu >>> -// SPIDRV settings - -// SPI bitrate -// Default: 1000000 -#define SL_SPIDRV_EXP_BITRATE 1000000 - -// SPI frame length <4-16> -// Default: 8 -#define SL_SPIDRV_EXP_FRAME_LENGTH 8 - -// SPI mode -// Master -// Slave -#define SL_SPIDRV_EXP_TYPE spidrvMaster - -// Bit order on the SPI bus -// LSB transmitted first -// MSB transmitted first -#define SL_SPIDRV_EXP_BIT_ORDER spidrvBitOrderMsbFirst - -// SPI clock mode -// SPI mode 0: CLKPOL=0, CLKPHA=0 -// SPI mode 1: CLKPOL=0, CLKPHA=1 -// SPI mode 2: CLKPOL=1, CLKPHA=0 -// SPI mode 3: CLKPOL=1, CLKPHA=1 -#define SL_SPIDRV_EXP_CLOCK_MODE spidrvClockMode0 - -// SPI master chip select (CS) control scheme. -// CS controlled by the SPI driver -// CS controlled by the application -#define SL_SPIDRV_EXP_CS_CONTROL spidrvCsControlAuto - -// SPI slave transfer start scheme -// Transfer starts immediately -// Transfer starts when the bus is idle (CS deasserted) -// Only applies if instance type is spidrvSlave -#define SL_SPIDRV_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_SPIDRV_EXP -// $[USART_SL_SPIDRV_EXP] -#define SL_SPIDRV_EXP_PERIPHERAL USART0 -#define SL_SPIDRV_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define SL_SPIDRV_EXP_TX_PORT gpioPortC -#define SL_SPIDRV_EXP_TX_PIN 0 - -// USART0 RX on PC01 -#define SL_SPIDRV_EXP_RX_PORT gpioPortC -#define SL_SPIDRV_EXP_RX_PIN 1 - -// USART0 CLK on PC02 -#define SL_SPIDRV_EXP_CLK_PORT gpioPortC -#define SL_SPIDRV_EXP_CLK_PIN 2 - -// USART0 CS on PC03 -#define SL_SPIDRV_EXP_CS_PORT gpioPortC -#define SL_SPIDRV_EXP_CS_PIN 3 - -// [USART_SL_SPIDRV_EXP]$ -// <<< sl:end pin_tool >>> - -#endif // SL_SPIDRV_EXP_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4002a/sl_spidrv_usart_exp_config.h b/hardware/board/config/brd4109a_brd4002a/sl_spidrv_usart_exp_config.h deleted file mode 100644 index 1d25852768..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_spidrv_usart_exp_config.h +++ /dev/null @@ -1,89 +0,0 @@ -/***************************************************************************//** - * @file - * @brief SPIDRV_USART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SPIDRV_USART_EXP_CONFIG_H -#define SL_SPIDRV_USART_EXP_CONFIG_H - -#include "spidrv.h" - -// <<< Use Configuration Wizard in Context Menu >>> -// SPIDRV settings - -// SPI bitrate -// Default: 1000000 -#define SL_SPIDRV_USART_EXP_BITRATE 1000000 - -// SPI frame length <4-16> -// Default: 8 -#define SL_SPIDRV_USART_EXP_FRAME_LENGTH 8 - -// SPI mode -// Master -// Slave -#define SL_SPIDRV_USART_EXP_TYPE spidrvMaster - -// Bit order on the SPI bus -// LSB transmitted first -// MSB transmitted first -#define SL_SPIDRV_USART_EXP_BIT_ORDER spidrvBitOrderMsbFirst - -// SPI clock mode -// SPI mode 0: CLKPOL=0, CLKPHA=0 -// SPI mode 1: CLKPOL=0, CLKPHA=1 -// SPI mode 2: CLKPOL=1, CLKPHA=0 -// SPI mode 3: CLKPOL=1, CLKPHA=1 -#define SL_SPIDRV_USART_EXP_CLOCK_MODE spidrvClockMode0 - -// SPI master chip select (CS) control scheme. -// CS controlled by the SPI driver -// CS controlled by the application -#define SL_SPIDRV_USART_EXP_CS_CONTROL spidrvCsControlAuto - -// SPI slave transfer start scheme -// Transfer starts immediately -// Transfer starts when the bus is idle (CS deasserted) -// Only applies if instance type is spidrvSlave -#define SL_SPIDRV_USART_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_SPIDRV_USART_EXP -// $[USART_SL_SPIDRV_USART_EXP] -#define SL_SPIDRV_USART_EXP_PERIPHERAL USART0 -#define SL_SPIDRV_USART_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define SL_SPIDRV_USART_EXP_TX_PORT gpioPortC -#define SL_SPIDRV_USART_EXP_TX_PIN 0 - -// USART0 RX on PC01 -#define SL_SPIDRV_USART_EXP_RX_PORT gpioPortC -#define SL_SPIDRV_USART_EXP_RX_PIN 1 - -// USART0 CLK on PC02 -#define SL_SPIDRV_USART_EXP_CLK_PORT gpioPortC -#define SL_SPIDRV_USART_EXP_CLK_PIN 2 - -// USART0 CS on PC03 -#define SL_SPIDRV_USART_EXP_CS_PORT gpioPortC -#define SL_SPIDRV_USART_EXP_CS_PIN 3 - -// [USART_SL_SPIDRV_USART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif // SL_SPIDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4109a_brd4002a/sl_uartdrv_eusart_exp_config.h deleted file mode 100644 index a89e4ccc3e..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ /dev/null @@ -1,100 +0,0 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV_EUSART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_UARTDRV_EUSART_EXP_CONFIG_H -#define SL_UARTDRV_EUSART_EXP_CONFIG_H - -#include "em_eusart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// EUSART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_EUSART_EXP_BAUDRATE 115200 - -// Low frequency mode -// True -// False -#define SL_UARTDRV_EUSART_EXP_LF_MODE false - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: eusartNoParity -#define SL_UARTDRV_EUSART_EXP_PARITY eusartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: eusartStopbits1 -#define SL_UARTDRV_EUSART_EXP_STOP_BITS eusartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHw -#define SL_UARTDRV_EUSART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Oversampling disabled -// Default: eusartOVS16 -#define SL_UARTDRV_EUSART_EXP_OVERSAMPLING eusartOVS16 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// False -// True -// Default: eusartMajorityVoteEnable -#define SL_UARTDRV_EUSART_EXP_MVDIS eusartMajorityVoteEnable - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_EUSART_EXP_RX_BUFFER_SIZE 6 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_EUSART_EXP_TX_BUFFER_SIZE 6 -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_EUSART_EXP -// $[EUSART_SL_UARTDRV_EUSART_EXP] -#define SL_UARTDRV_EUSART_EXP_PERIPHERAL EUSART0 -#define SL_UARTDRV_EUSART_EXP_PERIPHERAL_NO 0 - -// EUSART0 TX on PA05 -#define SL_UARTDRV_EUSART_EXP_TX_PORT gpioPortA -#define SL_UARTDRV_EUSART_EXP_TX_PIN 5 - -// EUSART0 RX on PA06 -#define SL_UARTDRV_EUSART_EXP_RX_PORT gpioPortA -#define SL_UARTDRV_EUSART_EXP_RX_PIN 6 - - - -// [EUSART_SL_UARTDRV_EUSART_EXP]$ -// <<< sl:end pin_tool >>> -#endif // SL_UARTDRV_EUSART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4002a/sl_uartdrv_eusart_vcom_config.h b/hardware/board/config/brd4109a_brd4002a/sl_uartdrv_eusart_vcom_config.h deleted file mode 100644 index be1494fb96..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_uartdrv_eusart_vcom_config.h +++ /dev/null @@ -1,106 +0,0 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV_EUSART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_UARTDRV_EUSART_VCOM_CONFIG_H -#define SL_UARTDRV_EUSART_VCOM_CONFIG_H - -#include "em_eusart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// EUSART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_EUSART_VCOM_BAUDRATE 115200 - -// Low frequency mode -// True -// False -#define SL_UARTDRV_EUSART_VCOM_LF_MODE false - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: eusartNoParity -#define SL_UARTDRV_EUSART_VCOM_PARITY eusartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: eusartStopbits1 -#define SL_UARTDRV_EUSART_VCOM_STOP_BITS eusartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHw -#define SL_UARTDRV_EUSART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Oversampling disabled -// Default: eusartOVS16 -#define SL_UARTDRV_EUSART_VCOM_OVERSAMPLING eusartOVS16 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// False -// True -// Default: eusartMajorityVoteEnable -#define SL_UARTDRV_EUSART_VCOM_MVDIS eusartMajorityVoteEnable - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_EUSART_VCOM_RX_BUFFER_SIZE 6 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_EUSART_VCOM_TX_BUFFER_SIZE 6 -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_EUSART_VCOM -// $[EUSART_SL_UARTDRV_EUSART_VCOM] -#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL EUSART0 -#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL_NO 0 - -// EUSART0 TX on PA05 -#define SL_UARTDRV_EUSART_VCOM_TX_PORT gpioPortA -#define SL_UARTDRV_EUSART_VCOM_TX_PIN 5 - -// EUSART0 RX on PA06 -#define SL_UARTDRV_EUSART_VCOM_RX_PORT gpioPortA -#define SL_UARTDRV_EUSART_VCOM_RX_PIN 6 - -// EUSART0 CTS on PA00 -#define SL_UARTDRV_EUSART_VCOM_CTS_PORT gpioPortA -#define SL_UARTDRV_EUSART_VCOM_CTS_PIN 0 - -// EUSART0 RTS on PA07 -#define SL_UARTDRV_EUSART_VCOM_RTS_PORT gpioPortA -#define SL_UARTDRV_EUSART_VCOM_RTS_PIN 7 - -// [EUSART_SL_UARTDRV_EUSART_VCOM]$ -// <<< sl:end pin_tool >>> -#endif // SL_UARTDRV_EUSART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4109a_brd4002a/sl_uartdrv_usart_exp_config.h deleted file mode 100644 index 02662139f3..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_uartdrv_usart_exp_config.h +++ /dev/null @@ -1,95 +0,0 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV_USART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_UARTDRV_USART_EXP_CONFIG_H -#define SL_UARTDRV_USART_EXP_CONFIG_H - -#include "em_usart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// UART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_USART_EXP_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_UARTDRV_USART_EXP_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_UARTDRV_USART_EXP_STOP_BITS usartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHw -#define SL_UARTDRV_USART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Default: usartOVS16 -#define SL_UARTDRV_USART_EXP_OVERSAMPLING usartOVS4 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// True -// False -#define SL_UARTDRV_USART_EXP_MVDIS false - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_USART_EXP_RX_BUFFER_SIZE 6 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_USART_EXP_TX_BUFFER_SIZE 6 - -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_USART_EXP -// $[USART_SL_UARTDRV_USART_EXP] -#define SL_UARTDRV_USART_EXP_PERIPHERAL USART0 -#define SL_UARTDRV_USART_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_UARTDRV_USART_EXP_TX_PORT gpioPortA -#define SL_UARTDRV_USART_EXP_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_UARTDRV_USART_EXP_RX_PORT gpioPortA -#define SL_UARTDRV_USART_EXP_RX_PIN 6 - - - -// [USART_SL_UARTDRV_USART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif // SL_UARTDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4002a/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd4109a_brd4002a/sl_uartdrv_usart_vcom_config.h deleted file mode 100644 index 1ee69f20fe..0000000000 --- a/hardware/board/config/brd4109a_brd4002a/sl_uartdrv_usart_vcom_config.h +++ /dev/null @@ -1,101 +0,0 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV_USART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H -#define SL_UARTDRV_USART_VCOM_CONFIG_H - -#include "em_usart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// UART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHw -#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Default: usartOVS16 -#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// True -// False -#define SL_UARTDRV_USART_VCOM_MVDIS false - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 6 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 6 - -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_USART_VCOM -// $[USART_SL_UARTDRV_USART_VCOM] -#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART0 -#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortA -#define SL_UARTDRV_USART_VCOM_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortA -#define SL_UARTDRV_USART_VCOM_RX_PIN 6 - -// USART0 CTS on PA00 -#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA -#define SL_UARTDRV_USART_VCOM_CTS_PIN 0 - -// USART0 RTS on PA07 -#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA -#define SL_UARTDRV_USART_VCOM_RTS_PIN 7 - -// [USART_SL_UARTDRV_USART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4001a/btl_euart_driver_cfg.h b/hardware/board/config/brd4111a_brd4001a/btl_euart_driver_cfg.h deleted file mode 100644 index 850c0169c0..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/btl_euart_driver_cfg.h +++ /dev/null @@ -1,88 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader euart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_EUART_DRIVER_CONFIG_H -#define BTL_EUART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// EUART settings - -// Baud rate -// Default: 115200 -#define SL_SERIAL_EUART_BAUD_RATE 115200 - -// Hardware flow control -// Default: 0 -#define SL_SERIAL_EUART_FLOW_CONTROL 0 -// - -// Receive buffer size -// <0-2048:1> -// Default: 512 [0-2048] -#define SL_DRIVER_EUART_RX_BUFFER_SIZE 512 - -// Transmit buffer size -// <0-2048:1> -// Default: 128 [0-2048] -#define SL_DRIVER_EUART_TX_BUFFER_SIZE 128 - -// Virtual COM Port -// Default: 0 -#define SL_VCOM_ENABLE 0 -// - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_SERIAL_EUART -// $[EUSART_SL_SERIAL_EUART] -#define SL_SERIAL_EUART_PERIPHERAL EUSART0 -#define SL_SERIAL_EUART_PERIPHERAL_NO 0 - -// EUSART0 TX on PA05 -#define SL_SERIAL_EUART_TX_PORT gpioPortA -#define SL_SERIAL_EUART_TX_PIN 5 - -// EUSART0 RX on PA06 -#define SL_SERIAL_EUART_RX_PORT gpioPortA -#define SL_SERIAL_EUART_RX_PIN 6 - -// EUSART0 CTS on PA04 -#define SL_SERIAL_EUART_CTS_PORT gpioPortA -#define SL_SERIAL_EUART_CTS_PIN 4 - -// EUSART0 RTS on PA00 -#define SL_SERIAL_EUART_RTS_PORT gpioPortA -#define SL_SERIAL_EUART_RTS_PIN 0 - -// [EUSART_SL_SERIAL_EUART]$ - - -// SL_VCOM_ENABLE - -// $[GPIO_SL_VCOM_ENABLE] -#define SL_VCOM_ENABLE_PORT gpioPortC -#define SL_VCOM_ENABLE_PIN 3 - -// [GPIO_SL_VCOM_ENABLE]$ - - -// <<< sl:end pin_tool >>> - -#endif // BTL_EUART_DRIVER_CONFIG_H \ No newline at end of file diff --git a/hardware/board/config/brd4111a_brd4001a/btl_ezsp_gpio_activation_cfg.h b/hardware/board/config/brd4111a_brd4001a/btl_ezsp_gpio_activation_cfg.h deleted file mode 100644 index 620a881b5e..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/btl_ezsp_gpio_activation_cfg.h +++ /dev/null @@ -1,52 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader EZSP GPIO Activation - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_EZSP_GPIO_ACTIVATION_CONFIG_H -#define BTL_EZSP_GPIO_ACTIVATION_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Properties of SPI NCP - -// Active state -// Low -// High -// Default: LOW -// Enter firmware upgrade mode if GPIO pin has this state -#define SL_EZSP_GPIO_ACTIVATION_POLARITY LOW - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_EZSPSPI_HOST_INT -// $[GPIO_SL_EZSPSPI_HOST_INT] -#define SL_EZSPSPI_HOST_INT_PORT gpioPortC -#define SL_EZSPSPI_HOST_INT_PIN 5 - -// [GPIO_SL_EZSPSPI_HOST_INT]$ - -// SL_EZSPSPI_WAKE_INT -// $[GPIO_SL_EZSPSPI_WAKE_INT] -#define SL_EZSPSPI_WAKE_INT_PORT gpioPortC -#define SL_EZSPSPI_WAKE_INT_PIN 4 - -// [GPIO_SL_EZSPSPI_WAKE_INT]$ - -// <<< sl:end pin_tool >>> - -#endif // BTL_EZSP_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4001a/btl_gpio_activation_cfg.h b/hardware/board/config/brd4111a_brd4001a/btl_gpio_activation_cfg.h deleted file mode 100644 index 51573b25df..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/btl_gpio_activation_cfg.h +++ /dev/null @@ -1,49 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader GPIO Activation - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_GPIO_ACTIVATION_CONFIG_H -#define BTL_GPIO_ACTIVATION_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Properties of Bootloader Entry - - -// Active state -// Low -// High -// Default: LOW -// Enter firmware upgrade mode if GPIO pin has this state -#define SL_GPIO_ACTIVATION_POLARITY LOW - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_BTL_BUTTON - -// $[GPIO_SL_BTL_BUTTON] -#define SL_BTL_BUTTON_PORT gpioPortC -#define SL_BTL_BUTTON_PIN 5 - -// [GPIO_SL_BTL_BUTTON]$ - -// <<< sl:end pin_tool >>> - - -#endif // BTL_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4001a/btl_spi_controller_eusart_driver_cfg.h b/hardware/board/config/brd4111a_brd4001a/btl_spi_controller_eusart_driver_cfg.h deleted file mode 100644 index 308060ef81..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/btl_spi_controller_eusart_driver_cfg.h +++ /dev/null @@ -1,68 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader Spi Controller Eusart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H -#define BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// SPI Controller EUSART Driver - -// Frequency -// Default: 6400000 -#define SL_EUSART_EXTFLASH_FREQUENCY 6400000 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_EUSART_EXTFLASH -// $[EUSART_SL_EUSART_EXTFLASH] -#define SL_EUSART_EXTFLASH_PERIPHERAL EUSART0 -#define SL_EUSART_EXTFLASH_PERIPHERAL_NO 0 - -// EUSART0 TX on PB00 -#define SL_EUSART_EXTFLASH_TX_PORT gpioPortB -#define SL_EUSART_EXTFLASH_TX_PIN 0 - -// EUSART0 RX on PB01 -#define SL_EUSART_EXTFLASH_RX_PORT gpioPortB -#define SL_EUSART_EXTFLASH_RX_PIN 1 - -// EUSART0 SCLK on PB02 -#define SL_EUSART_EXTFLASH_SCLK_PORT gpioPortB -#define SL_EUSART_EXTFLASH_SCLK_PIN 2 - -// EUSART0 CS on PC02 -#define SL_EUSART_EXTFLASH_CS_PORT gpioPortC -#define SL_EUSART_EXTFLASH_CS_PIN 2 - -// [EUSART_SL_EUSART_EXTFLASH]$ - -// SL_EXTFLASH_WP -// $[GPIO_SL_EXTFLASH_WP] - -// [GPIO_SL_EXTFLASH_WP]$ - -// SL_EXTFLASH_HOLD -// $[GPIO_SL_EXTFLASH_HOLD] - -// [GPIO_SL_EXTFLASH_HOLD]$ - -// <<< sl:end pin_tool >>> - -#endif // BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4001a/btl_spi_controller_usart_driver_cfg.h b/hardware/board/config/brd4111a_brd4001a/btl_spi_controller_usart_driver_cfg.h deleted file mode 100644 index 6ac5f54418..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/btl_spi_controller_usart_driver_cfg.h +++ /dev/null @@ -1,68 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader Spi Controller Usart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H -#define BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// SPI Controller USART Driver - -// Frequency -// Default: 6400000 -#define SL_USART_EXTFLASH_FREQUENCY 6400000 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_USART_EXTFLASH -// $[USART_SL_USART_EXTFLASH] -#define SL_USART_EXTFLASH_PERIPHERAL USART0 -#define SL_USART_EXTFLASH_PERIPHERAL_NO 0 - -// USART0 TX on PB00 -#define SL_USART_EXTFLASH_TX_PORT gpioPortB -#define SL_USART_EXTFLASH_TX_PIN 0 - -// USART0 RX on PB01 -#define SL_USART_EXTFLASH_RX_PORT gpioPortB -#define SL_USART_EXTFLASH_RX_PIN 1 - -// USART0 CLK on PB02 -#define SL_USART_EXTFLASH_CLK_PORT gpioPortB -#define SL_USART_EXTFLASH_CLK_PIN 2 - -// USART0 CS on PC02 -#define SL_USART_EXTFLASH_CS_PORT gpioPortC -#define SL_USART_EXTFLASH_CS_PIN 2 - -// [USART_SL_USART_EXTFLASH]$ - -// SL_EXTFLASH_WP -// $[GPIO_SL_EXTFLASH_WP] - -// [GPIO_SL_EXTFLASH_WP]$ - -// SL_EXTFLASH_HOLD -// $[GPIO_SL_EXTFLASH_HOLD] - -// [GPIO_SL_EXTFLASH_HOLD]$ - -// <<< sl:end pin_tool >>> - -#endif // BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4001a/btl_uart_driver_cfg.h b/hardware/board/config/brd4111a_brd4001a/btl_uart_driver_cfg.h deleted file mode 100644 index 602dc337c0..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/btl_uart_driver_cfg.h +++ /dev/null @@ -1,89 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader Uart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_UART_DRIVER_CONFIG_H -#define BTL_UART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// USART settings - -// Baud rate -// Default: 115200 -#define SL_SERIAL_UART_BAUD_RATE 115200 - -// Hardware flow control -// Default: 0 -#define SL_SERIAL_UART_FLOW_CONTROL 0 -// - -// Receive buffer size -// <0-2048:1> -// Default: 512 [0-2048] -#define SL_DRIVER_UART_RX_BUFFER_SIZE 512 - -// Transmit buffer size -// <0-2048:1> -// Default: 128 [0-2048] -#define SL_DRIVER_UART_TX_BUFFER_SIZE 128 - -// Virtual COM Port -// Default: 0 -#define SL_VCOM_ENABLE 0 -// - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_SERIAL_UART -// $[USART_SL_SERIAL_UART] -#define SL_SERIAL_UART_PERIPHERAL USART0 -#define SL_SERIAL_UART_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_SERIAL_UART_TX_PORT gpioPortA -#define SL_SERIAL_UART_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_SERIAL_UART_RX_PORT gpioPortA -#define SL_SERIAL_UART_RX_PIN 6 - -// USART0 CTS on PA04 -#define SL_SERIAL_UART_CTS_PORT gpioPortA -#define SL_SERIAL_UART_CTS_PIN 4 - -// USART0 RTS on PA00 -#define SL_SERIAL_UART_RTS_PORT gpioPortA -#define SL_SERIAL_UART_RTS_PIN 0 - -// [USART_SL_SERIAL_UART]$ - - - -// SL_VCOM_ENABLE - -// $[GPIO_SL_VCOM_ENABLE] -#define SL_VCOM_ENABLE_PORT gpioPortC -#define SL_VCOM_ENABLE_PIN 3 - -// [GPIO_SL_VCOM_ENABLE]$ - - -// <<< sl:end pin_tool >>> - -#endif // BTL_UART_DRIVER_CONFIG_H \ No newline at end of file diff --git a/hardware/board/config/brd4111a_brd4001a/iot_flash_cfg_spiflash.h b/hardware/board/config/brd4111a_brd4001a/iot_flash_cfg_spiflash.h deleted file mode 100644 index 3b634d9b08..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/iot_flash_cfg_spiflash.h +++ /dev/null @@ -1,136 +0,0 @@ -/***************************************************************************//** - * @file iot_flash_cfg_inst.h - * @brief Common I/O flash instance configurations. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_FLASH_CFG_SPIFLASH_H_ -#define _IOT_FLASH_CFG_SPIFLASH_H_ - -/******************************************************************************* - * Flash Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// Flash General Options - -// Instance number -// Instance number used when iot_flash_open() is called. -// Default: 0 -#define IOT_FLASH_CFG_SPIFLASH_INST_NUM 0 - -// Instance type -// <0=> Internal Flash (MSC) -// <1=> External Flash (SPI) -// Specify whether this instance is for internal flash (MSC) -// or an external SPI flash. If external, then you need to setup -// SPI configs below. -// Default: 0 -#define IOT_FLASH_CFG_SPIFLASH_INST_TYPE 1 - -// - -// SPI Configuration - -// Default SPI bitrate -// Default: 1000000 -#define IOT_FLASH_CFG_SPIFLASH_SPI_BITRATE 1000000 - -// Default SPI frame length <4-16> -// Default: 8 -#define IOT_FLASH_CFG_SPIFLASH_SPI_FRAME_LENGTH 8 - -// Default SPI master/slave mode -// Master -// Slave -#define IOT_FLASH_CFG_SPIFLASH_SPI_TYPE spidrvMaster - -// Default SPI bit order -// LSB transmitted first -// MSB transmitted first -#define IOT_FLASH_CFG_SPIFLASH_SPI_BIT_ORDER spidrvBitOrderMsbFirst - -// Default SPI clock mode -// SPI mode 0: CLKPOL=0, CLKPHA=0 -// SPI mode 1: CLKPOL=0, CLKPHA=1 -// SPI mode 2: CLKPOL=1, CLKPHA=0 -// SPI mode 3: CLKPOL=1, CLKPHA=1 -#define IOT_FLASH_CFG_SPIFLASH_SPI_CLOCK_MODE spidrvClockMode0 - -// Default SPI CS control scheme -// CS controlled by the SPI driver -// CS controlled by the application -#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_CONTROL spidrvCsControlApplication - -// Default SPI transfer scheme -// Transfer starts immediately -// Transfer starts when the bus is idle -#define IOT_FLASH_CFG_SPIFLASH_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * EXTERNAL FLASH: H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_FLASH_CFG_SPIFLASH_SPI -// $[USART_IOT_FLASH_CFG_SPIFLASH_SPI] -#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL USART0 -#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL_NO 0 - -// USART0 TX on PB00 -#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PORT gpioPortB -#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PIN 0 - -// USART0 RX on PB01 -#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PORT gpioPortB -#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PIN 1 - -// USART0 CLK on PB02 -#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PORT gpioPortB -#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PIN 2 - -// USART0 CS on PC02 -#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PORT gpioPortC -#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PIN 2 - -// [USART_IOT_FLASH_CFG_SPIFLASH_SPI]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_FLASH_CFG_SPIFLASH_H_ */ diff --git a/hardware/board/config/brd4111a_brd4001a/iot_pwm_cfg_exp.h b/hardware/board/config/brd4111a_brd4001a/iot_pwm_cfg_exp.h deleted file mode 100644 index 306f255589..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/iot_pwm_cfg_exp.h +++ /dev/null @@ -1,78 +0,0 @@ -/***************************************************************************//** - * @file iot_pwm_cfg_inst.h - * @brief Common I/O PWM instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_PWM_CFG_EXP_H_ -#define _IOT_PWM_CFG_EXP_H_ - -/******************************************************************************* - * PWM Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// PWM General Options - -// Instance number -// Instance number used when iot_pwm_open() is called. -// Default: 0 -#define IOT_PWM_CFG_EXP_INST_NUM 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_PWM_CFG_EXP -// $[TIMER_IOT_PWM_CFG_EXP] -#define IOT_PWM_CFG_EXP_PERIPHERAL TIMER3 -#define IOT_PWM_CFG_EXP_PERIPHERAL_NO 3 - -// TIMER3 CC0 on PC05 -#define IOT_PWM_CFG_EXP_CC0_PORT gpioPortC -#define IOT_PWM_CFG_EXP_CC0_PIN 5 - - - -// [TIMER_IOT_PWM_CFG_EXP]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_PWM_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4111a_brd4001a/iot_uart_cfg_exp.h b/hardware/board/config/brd4111a_brd4001a/iot_uart_cfg_exp.h deleted file mode 100644 index 02f62b7d87..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/iot_uart_cfg_exp.h +++ /dev/null @@ -1,126 +0,0 @@ -/***************************************************************************//** - * @file iot_uart_cfg_inst.h - * @brief Common I/O UART instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_UART_CFG_EXP_H_ -#define _IOT_UART_CFG_EXP_H_ - -/******************************************************************************* - * UART Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// UART General Options - -// Instance number -// Instance number used when iot_uart_open() is called. -// Default: 0 -#define IOT_UART_CFG_EXP_INST_NUM 0 - -// Default baud rate -// Default: 115200 -#define IOT_UART_CFG_EXP_DEFAULT_BAUDRATE 115200 - -// Default number of data bits -// 4 data bits -// 5 data bits -// 6 data bits -// 7 data bits -// 8 data bits -// Default: usartDatabits8 -#define IOT_UART_CFG_EXP_DEFAULT_DATA_BITS usartDatabits8 - -// Default parity mode -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define IOT_UART_CFG_EXP_DEFAULT_PARITY usartNoParity - -// Default number of stop bits -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define IOT_UART_CFG_EXP_DEFAULT_STOP_BITS usartStopbits1 - -// Default hardware flow control -// None -// CTS -// RTS -// CTS/RTS -// Default: usartHwFlowControlNone -#define IOT_UART_CFG_EXP_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone - - -// Internal Loopback -// Enable USART Internal loopback -// Default: 0 -#define IOT_UART_CFG_EXP_LOOPBACK 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_UART_CFG_EXP -// $[USART_IOT_UART_CFG_EXP] -#define IOT_UART_CFG_EXP_PERIPHERAL USART0 -#define IOT_UART_CFG_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define IOT_UART_CFG_EXP_TX_PORT gpioPortA -#define IOT_UART_CFG_EXP_TX_PIN 5 - -// USART0 RX on PA06 -#define IOT_UART_CFG_EXP_RX_PORT gpioPortA -#define IOT_UART_CFG_EXP_RX_PIN 6 - - - - - -// [USART_IOT_UART_CFG_EXP]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_UART_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4111a_brd4001a/iot_uart_cfg_loopback.h b/hardware/board/config/brd4111a_brd4001a/iot_uart_cfg_loopback.h deleted file mode 100644 index c426e68b97..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/iot_uart_cfg_loopback.h +++ /dev/null @@ -1,132 +0,0 @@ -/***************************************************************************//** - * @file iot_uart_cfg_inst.h - * @brief Common I/O UART instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_UART_CFG_LOOPBACK_H_ -#define _IOT_UART_CFG_LOOPBACK_H_ - -/******************************************************************************* - * UART Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// UART General Options - -// Instance number -// Instance number used when iot_uart_open() is called. -// Default: 0 -#define IOT_UART_CFG_LOOPBACK_INST_NUM 0 - -// Default baud rate -// Default: 115200 -#define IOT_UART_CFG_LOOPBACK_DEFAULT_BAUDRATE 115200 - -// Default number of data bits -// 4 data bits -// 5 data bits -// 6 data bits -// 7 data bits -// 8 data bits -// Default: usartDatabits8 -#define IOT_UART_CFG_LOOPBACK_DEFAULT_DATA_BITS usartDatabits8 - -// Default parity mode -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define IOT_UART_CFG_LOOPBACK_DEFAULT_PARITY usartNoParity - -// Default number of stop bits -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define IOT_UART_CFG_LOOPBACK_DEFAULT_STOP_BITS usartStopbits1 - -// Default hardware flow control -// None -// CTS -// RTS -// CTS/RTS -// Default: usartHwFlowControlNone -#define IOT_UART_CFG_LOOPBACK_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone - - -// Internal Loopback -// Enable USART Internal loopback -// Default: 0 -#define IOT_UART_CFG_LOOPBACK_LOOPBACK 1 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_UART_CFG_LOOPBACK -// $[USART_IOT_UART_CFG_LOOPBACK] -#define IOT_UART_CFG_LOOPBACK_PERIPHERAL USART0 -#define IOT_UART_CFG_LOOPBACK_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define IOT_UART_CFG_LOOPBACK_TX_PORT gpioPortA -#define IOT_UART_CFG_LOOPBACK_TX_PIN 5 - -// USART0 RX on PA06 -#define IOT_UART_CFG_LOOPBACK_RX_PORT gpioPortA -#define IOT_UART_CFG_LOOPBACK_RX_PIN 6 - - - -// USART0 RTS on PA00 -#define IOT_UART_CFG_LOOPBACK_RTS_PORT gpioPortA -#define IOT_UART_CFG_LOOPBACK_RTS_PIN 0 - -// USART0 CTS on PA04 -#define IOT_UART_CFG_LOOPBACK_CTS_PORT gpioPortA -#define IOT_UART_CFG_LOOPBACK_CTS_PIN 4 - -// [USART_IOT_UART_CFG_LOOPBACK]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_UART_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4111a_brd4001a/iot_uart_cfg_vcom.h b/hardware/board/config/brd4111a_brd4001a/iot_uart_cfg_vcom.h deleted file mode 100644 index e8b6e6e185..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/iot_uart_cfg_vcom.h +++ /dev/null @@ -1,132 +0,0 @@ -/***************************************************************************//** - * @file iot_uart_cfg_inst.h - * @brief Common I/O UART instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_UART_CFG_VCOM_H_ -#define _IOT_UART_CFG_VCOM_H_ - -/******************************************************************************* - * UART Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// UART General Options - -// Instance number -// Instance number used when iot_uart_open() is called. -// Default: 0 -#define IOT_UART_CFG_VCOM_INST_NUM 0 - -// Default baud rate -// Default: 115200 -#define IOT_UART_CFG_VCOM_DEFAULT_BAUDRATE 115200 - -// Default number of data bits -// 4 data bits -// 5 data bits -// 6 data bits -// 7 data bits -// 8 data bits -// Default: usartDatabits8 -#define IOT_UART_CFG_VCOM_DEFAULT_DATA_BITS usartDatabits8 - -// Default parity mode -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define IOT_UART_CFG_VCOM_DEFAULT_PARITY usartNoParity - -// Default number of stop bits -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define IOT_UART_CFG_VCOM_DEFAULT_STOP_BITS usartStopbits1 - -// Default hardware flow control -// None -// CTS -// RTS -// CTS/RTS -// Default: usartHwFlowControlNone -#define IOT_UART_CFG_VCOM_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone - - -// Internal Loopback -// Enable USART Internal loopback -// Default: 0 -#define IOT_UART_CFG_VCOM_LOOPBACK 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_UART_CFG_VCOM -// $[USART_IOT_UART_CFG_VCOM] -#define IOT_UART_CFG_VCOM_PERIPHERAL USART0 -#define IOT_UART_CFG_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define IOT_UART_CFG_VCOM_TX_PORT gpioPortA -#define IOT_UART_CFG_VCOM_TX_PIN 5 - -// USART0 RX on PA06 -#define IOT_UART_CFG_VCOM_RX_PORT gpioPortA -#define IOT_UART_CFG_VCOM_RX_PIN 6 - - - -// USART0 RTS on PA00 -#define IOT_UART_CFG_VCOM_RTS_PORT gpioPortA -#define IOT_UART_CFG_VCOM_RTS_PIN 0 - -// USART0 CTS on PA04 -#define IOT_UART_CFG_VCOM_CTS_PORT gpioPortA -#define IOT_UART_CFG_VCOM_CTS_PIN 4 - -// [USART_IOT_UART_CFG_VCOM]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_UART_CFG_VCOM_H_ */ diff --git a/hardware/board/config/brd4111a_brd4001a/sl_board_control_config.h b/hardware/board/config/brd4111a_brd4001a/sl_board_control_config.h deleted file mode 100644 index 7959f2d516..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/sl_board_control_config.h +++ /dev/null @@ -1,56 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Board Control - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_BOARD_CONTROL_CONFIG_H -#define SL_BOARD_CONTROL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Enable Virtual COM UART -// Default: 0 -#define SL_BOARD_ENABLE_VCOM 0 - -// Disable SPI Flash -// Default: 1 -#define SL_BOARD_DISABLE_MEMORY_SPI 1 - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_BOARD_ENABLE_VCOM -// $[GPIO_SL_BOARD_ENABLE_VCOM] -#define SL_BOARD_ENABLE_VCOM_PORT gpioPortC -#define SL_BOARD_ENABLE_VCOM_PIN 3 -// [GPIO_SL_BOARD_ENABLE_VCOM]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4001a/sl_cpc_drv_primary_uart_usart_exp_config.h b/hardware/board/config/brd4111a_brd4001a/sl_cpc_drv_primary_uart_usart_exp_config.h deleted file mode 100644 index 28f701fc44..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/sl_cpc_drv_primary_uart_usart_exp_config.h +++ /dev/null @@ -1,70 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC UART PRIMARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_USART_EXP_PRIMARY_CONFIG_H -#define SL_CPC_DRV_UART_USART_EXP_PRIMARY_CONFIG_H - -// CPC-Primary UART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 - -// UART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_EXP -// $[USART_SL_CPC_DRV_UART_EXP] -#define SL_CPC_DRV_UART_EXP_PERIPHERAL USART0 -#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_CPC_DRV_UART_EXP_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_CPC_DRV_UART_EXP_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_RX_PIN 6 - -// [USART_SL_CPC_DRV_UART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_EXP_PRIMARY_CONFIG_H */ diff --git a/hardware/board/config/brd4111a_brd4001a/sl_cpc_drv_primary_uart_usart_vcom_config.h b/hardware/board/config/brd4111a_brd4001a/sl_cpc_drv_primary_uart_usart_vcom_config.h deleted file mode 100644 index 7d51f4a7be..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/sl_cpc_drv_primary_uart_usart_vcom_config.h +++ /dev/null @@ -1,70 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC UART PRIMARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_USART_VCOM_PRIMARY_CONFIG_H -#define SL_CPC_DRV_UART_USART_VCOM_PRIMARY_CONFIG_H - -// CPC-Primary UART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 - -// UART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_VCOM -// $[USART_SL_CPC_DRV_UART_VCOM] -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_RX_PIN 6 - -// [USART_SL_CPC_DRV_UART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_VCOM_PRIMARY_CONFIG_H */ diff --git a/hardware/board/config/brd4111a_brd4001a/sl_cpc_drv_secondary_uart_eusart_exp_config.h b/hardware/board/config/brd4111a_brd4001a/sl_cpc_drv_secondary_uart_eusart_exp_config.h deleted file mode 100644 index b6b264813c..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/sl_cpc_drv_secondary_uart_eusart_exp_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC EUSART SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_EUSART_EXP_SECONDARY_CONFIG_H -#define SL_CPC_DRV_UART_EUSART_EXP_SECONDARY_CONFIG_H - -// CPC - Secondary EUSART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 - -// EUSART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 - -// Flow control -// None -// CTS/RTS -// Default: eusartHwFlowControlNone -#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_EXP -// $[EUSART_SL_CPC_DRV_UART_EXP] -#define SL_CPC_DRV_UART_EXP_PERIPHERAL EUSART0 -#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 - -// EUSART0 TX on PA05 -#define SL_CPC_DRV_UART_EXP_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_TX_PIN 5 - -// EUSART0 RX on PA06 -#define SL_CPC_DRV_UART_EXP_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_RX_PIN 6 - -// EUSART0 CTS on PA04 -#define SL_CPC_DRV_UART_EXP_CTS_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_CTS_PIN 4 - -// EUSART0 RTS on PA00 -#define SL_CPC_DRV_UART_EXP_RTS_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_RTS_PIN 0 - -// [EUSART_SL_CPC_DRV_UART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4111a_brd4001a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h b/hardware/board/config/brd4111a_brd4001a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h deleted file mode 100644 index a124e6f6fe..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC EUSART SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_EUSART_VCOM_SECONDARY_CONFIG_H -#define SL_CPC_DRV_UART_EUSART_VCOM_SECONDARY_CONFIG_H - -// CPC - Secondary EUSART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 - -// EUSART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 - -// Flow control -// None -// CTS/RTS -// Default: eusartHwFlowControlNone -#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_VCOM -// $[EUSART_SL_CPC_DRV_UART_VCOM] -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL EUSART0 -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 - -// EUSART0 TX on PA05 -#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_TX_PIN 5 - -// EUSART0 RX on PA06 -#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_RX_PIN 6 - -// EUSART0 CTS on PA04 -#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_CTS_PIN 4 - -// EUSART0 RTS on PA00 -#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_RTS_PIN 0 - -// [EUSART_SL_CPC_DRV_UART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_VCOM_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4111a_brd4001a/sl_cpc_drv_secondary_uart_usart_exp_config.h b/hardware/board/config/brd4111a_brd4001a/sl_cpc_drv_secondary_uart_usart_exp_config.h deleted file mode 100644 index ea3a86d650..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/sl_cpc_drv_secondary_uart_usart_exp_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC UART SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_USART_EXP_SECONDARY_CONFIG_H -#define SL_CPC_DRV_UART_USART_EXP_SECONDARY_CONFIG_H - -// CPC - Secondary UART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 - -// UART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 - -// Flow control -// None -// CTS/RTS -// Default: usartHwFlowControlCtsAndRts -#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_EXP -// $[USART_SL_CPC_DRV_UART_EXP] -#define SL_CPC_DRV_UART_EXP_PERIPHERAL USART0 -#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_CPC_DRV_UART_EXP_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_CPC_DRV_UART_EXP_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_RX_PIN 6 - -// USART0 CTS on PA04 -#define SL_CPC_DRV_UART_EXP_CTS_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_CTS_PIN 4 - -// USART0 RTS on PA00 -#define SL_CPC_DRV_UART_EXP_RTS_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_RTS_PIN 0 - -// [USART_SL_CPC_DRV_UART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4111a_brd4001a/sl_cpc_drv_secondary_uart_usart_vcom_config.h b/hardware/board/config/brd4111a_brd4001a/sl_cpc_drv_secondary_uart_usart_vcom_config.h deleted file mode 100644 index d164acc395..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/sl_cpc_drv_secondary_uart_usart_vcom_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC UART SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_USART_VCOM_SECONDARY_CONFIG_H -#define SL_CPC_DRV_UART_USART_VCOM_SECONDARY_CONFIG_H - -// CPC - Secondary UART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 - -// UART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 - -// Flow control -// None -// CTS/RTS -// Default: usartHwFlowControlCtsAndRts -#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_VCOM -// $[USART_SL_CPC_DRV_UART_VCOM] -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_RX_PIN 6 - -// USART0 CTS on PA04 -#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_CTS_PIN 4 - -// USART0 RTS on PA00 -#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_RTS_PIN 0 - -// [USART_SL_CPC_DRV_UART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_VCOM_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4111a_brd4001a/sl_device_init_hfxo_config.h b/hardware/board/config/brd4111a_brd4001a/sl_device_init_hfxo_config.h deleted file mode 100644 index b0938ac495..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/sl_device_init_hfxo_config.h +++ /dev/null @@ -1,53 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_HFXO Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H -#define SL_DEVICE_INIT_HFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// External sine wave -// Default: cmuHfxoOscMode_Crystal -#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal - -// Frequency <38000000-40000000> -// Default: 38400000 -#define SL_DEVICE_INIT_HFXO_FREQ 38400000 - -// CTUNE <0-255> -// Default: 140 -#define SL_DEVICE_INIT_HFXO_CTUNE 120 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4001a/sl_device_init_lfxo_config.h b/hardware/board/config/brd4111a_brd4001a/sl_device_init_lfxo_config.h deleted file mode 100644 index 0e1f4147bf..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/sl_device_init_lfxo_config.h +++ /dev/null @@ -1,66 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_LFXO Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H -#define SL_DEVICE_INIT_LFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// AC-coupled buffer -// External digital clock -// Default: cmuLfxoOscMode_Crystal -#define SL_DEVICE_INIT_LFXO_MODE cmuLfxoOscMode_Crystal - -// CTUNE <0-127> -// Default: 63 -#define SL_DEVICE_INIT_LFXO_CTUNE 37 - -// LFXO precision in PPM <0-65535> -// Default: 500 -#define SL_DEVICE_INIT_LFXO_PRECISION 100 - -// Startup Timeout Delay -// -// 2 cycles -// 256 cycles -// 1K cycles -// 2K cycles -// 4K cycles -// 8K cycles -// 16K cycles -// 32K cycles -// Default: cmuLfxoStartupDelay_4KCycles -#define SL_DEVICE_INIT_LFXO_TIMEOUT cmuLfxoStartupDelay_4KCycles -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4001a/sl_iostream_eusart_exp_config.h b/hardware/board/config/brd4111a_brd4001a/sl_iostream_eusart_exp_config.h deleted file mode 100644 index 298b5d2c75..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/sl_iostream_eusart_exp_config.h +++ /dev/null @@ -1,107 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_EUSART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_EUSART_EXP_CONFIG_H -#define SL_IOSTREAM_EUSART_EXP_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// EUART settings - -// Enable High frequency mode -// Default: 1 -#define SL_IOSTREAM_EUSART_EXP_ENABLE_HIGH_FREQUENCY 1 - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_EUSART_EXP_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: eusartNoParity -#define SL_IOSTREAM_EUSART_EXP_PARITY eusartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: eusartStopbits1 -#define SL_IOSTREAM_EUSART_EXP_STOP_BITS eusartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: eusartHwFlowControlNone -#define SL_IOSTREAM_EUSART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlNone - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_EUSART_EXP_RX_BUFFER_SIZE 32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_EUSART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_EUSART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_EUSART_EXP -// $[EUSART_SL_IOSTREAM_EUSART_EXP] -#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL EUSART0 -#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL_NO 0 - -// EUSART0 TX on PA05 -#define SL_IOSTREAM_EUSART_EXP_TX_PORT gpioPortA -#define SL_IOSTREAM_EUSART_EXP_TX_PIN 5 - -// EUSART0 RX on PA06 -#define SL_IOSTREAM_EUSART_EXP_RX_PORT gpioPortA -#define SL_IOSTREAM_EUSART_EXP_RX_PIN 6 - - - -// [EUSART_SL_IOSTREAM_EUSART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4111a_brd4001a/sl_iostream_eusart_vcom_config.h b/hardware/board/config/brd4111a_brd4001a/sl_iostream_eusart_vcom_config.h deleted file mode 100644 index aa477c44ff..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/sl_iostream_eusart_vcom_config.h +++ /dev/null @@ -1,113 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_EUSART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_EUSART_VCOM_CONFIG_H -#define SL_IOSTREAM_EUSART_VCOM_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// EUART settings - -// Enable High frequency mode -// Default: 1 -#define SL_IOSTREAM_EUSART_VCOM_ENABLE_HIGH_FREQUENCY 1 - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_EUSART_VCOM_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: eusartNoParity -#define SL_IOSTREAM_EUSART_VCOM_PARITY eusartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: eusartStopbits1 -#define SL_IOSTREAM_EUSART_VCOM_STOP_BITS eusartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: eusartHwFlowControlNone -#define SL_IOSTREAM_EUSART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_EUSART_VCOM_RX_BUFFER_SIZE 32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_EUSART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_EUSART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_EUSART_VCOM -// $[EUSART_SL_IOSTREAM_EUSART_VCOM] -#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL EUSART0 -#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL_NO 0 - -// EUSART0 TX on PA05 -#define SL_IOSTREAM_EUSART_VCOM_TX_PORT gpioPortA -#define SL_IOSTREAM_EUSART_VCOM_TX_PIN 5 - -// EUSART0 RX on PA06 -#define SL_IOSTREAM_EUSART_VCOM_RX_PORT gpioPortA -#define SL_IOSTREAM_EUSART_VCOM_RX_PIN 6 - -// EUSART0 CTS on PA04 -#define SL_IOSTREAM_EUSART_VCOM_CTS_PORT gpioPortA -#define SL_IOSTREAM_EUSART_VCOM_CTS_PIN 4 - -// EUSART0 RTS on PA00 -#define SL_IOSTREAM_EUSART_VCOM_RTS_PORT gpioPortA -#define SL_IOSTREAM_EUSART_VCOM_RTS_PIN 0 - -// [EUSART_SL_IOSTREAM_EUSART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4111a_brd4001a/sl_iostream_usart_exp_config.h b/hardware/board/config/brd4111a_brd4001a/sl_iostream_usart_exp_config.h deleted file mode 100644 index 8669faa1a4..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/sl_iostream_usart_exp_config.h +++ /dev/null @@ -1,103 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_USART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_USART_EXP_CONFIG_H -#define SL_IOSTREAM_USART_EXP_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// USART settings - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_USART_EXP_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_IOSTREAM_USART_EXP_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_IOSTREAM_USART_EXP_STOP_BITS usartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: usartHwFlowControlNone -#define SL_IOSTREAM_USART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlNone - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_USART_EXP_RX_BUFFER_SIZE 32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_USART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_USART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_USART_EXP -// $[USART_SL_IOSTREAM_USART_EXP] -#define SL_IOSTREAM_USART_EXP_PERIPHERAL USART0 -#define SL_IOSTREAM_USART_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_IOSTREAM_USART_EXP_TX_PORT gpioPortA -#define SL_IOSTREAM_USART_EXP_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_IOSTREAM_USART_EXP_RX_PORT gpioPortA -#define SL_IOSTREAM_USART_EXP_RX_PIN 6 - - - -// [USART_SL_IOSTREAM_USART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4111a_brd4001a/sl_iostream_usart_vcom_config.h b/hardware/board/config/brd4111a_brd4001a/sl_iostream_usart_vcom_config.h deleted file mode 100644 index fa080aaeb7..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/sl_iostream_usart_vcom_config.h +++ /dev/null @@ -1,109 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_USART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H -#define SL_IOSTREAM_USART_VCOM_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// USART settings - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_USART_VCOM_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: usartHwFlowControlNone -#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_USART_VCOM -// $[USART_SL_IOSTREAM_USART_VCOM] -#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART0 -#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_IOSTREAM_USART_VCOM_TX_PORT gpioPortA -#define SL_IOSTREAM_USART_VCOM_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_IOSTREAM_USART_VCOM_RX_PORT gpioPortA -#define SL_IOSTREAM_USART_VCOM_RX_PIN 6 - -// USART0 CTS on PA04 -#define SL_IOSTREAM_USART_VCOM_CTS_PORT gpioPortA -#define SL_IOSTREAM_USART_VCOM_CTS_PIN 4 - -// USART0 RTS on PA00 -#define SL_IOSTREAM_USART_VCOM_RTS_PORT gpioPortA -#define SL_IOSTREAM_USART_VCOM_RTS_PIN 0 - -// [USART_SL_IOSTREAM_USART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4111a_brd4001a/sl_mx25_flash_shutdown_eusart_config.h b/hardware/board/config/brd4111a_brd4001a/sl_mx25_flash_shutdown_eusart_config.h deleted file mode 100644 index 3d804d2bea..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/sl_mx25_flash_shutdown_eusart_config.h +++ /dev/null @@ -1,51 +0,0 @@ -/***************************************************************************//** - * @file - * @brief SL_MX25_FLASH_SHUTDOWN_USART Config - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H -#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H - -// <<< sl:start pin_tool >>> -// {eusart signal=TX,RX,SCLK} SL_MX25_FLASH_SHUTDOWN -// [EUSART_SL_MX25_FLASH_SHUTDOWN] -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL EUSART0 -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 - -// EUSART0 TX on PB00 -#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortB -#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 0 - -// EUSART0 RX on PB01 -#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortB -#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 - -// EUSART0 SCLK on PB02 -#define SL_MX25_FLASH_SHUTDOWN_SCLK_PORT gpioPortB -#define SL_MX25_FLASH_SHUTDOWN_SCLK_PIN 2 - -// [EUSART_SL_MX25_FLASH_SHUTDOWN] - -// SL_MX25_FLASH_SHUTDOWN_CS - -// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] -#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortC -#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 2 - -// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4001a/sl_mx25_flash_shutdown_usart_config.h b/hardware/board/config/brd4111a_brd4001a/sl_mx25_flash_shutdown_usart_config.h deleted file mode 100644 index 06eb2da111..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/sl_mx25_flash_shutdown_usart_config.h +++ /dev/null @@ -1,51 +0,0 @@ -/***************************************************************************//** - * @file - * @brief SL_MX25_FLASH_SHUTDOWN_USART Config - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H -#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H - -// <<< sl:start pin_tool >>> -// {usart signal=TX,RX,CLK} SL_MX25_FLASH_SHUTDOWN -// [USART_SL_MX25_FLASH_SHUTDOWN] -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL USART0 -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 - -// USART0 TX on PB00 -#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortB -#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 0 - -// USART0 RX on PB01 -#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortB -#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 - -// USART0 CLK on PB02 -#define SL_MX25_FLASH_SHUTDOWN_CLK_PORT gpioPortB -#define SL_MX25_FLASH_SHUTDOWN_CLK_PIN 2 - -// [USART_SL_MX25_FLASH_SHUTDOWN] - -// SL_MX25_FLASH_SHUTDOWN_CS - -// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] -#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortC -#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 2 - -// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4001a/sl_rail_util_pa_config.h b/hardware/board/config/brd4111a_brd4001a/sl_rail_util_pa_config.h deleted file mode 100644 index 7c14e2f342..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/sl_rail_util_pa_config.h +++ /dev/null @@ -1,81 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Power Amplifier configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_RAIL_UTIL_PA_CONFIG_H -#define SL_RAIL_UTIL_PA_CONFIG_H - -#include "rail_types.h" - -// <<< Use Configuration Wizard in Context Menu >>> - -// PA Configuration -// Initial PA Power (deci-dBm, 100 = 10.0 dBm) -// Default: 100 -#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 - -// PA Ramp Time (microseconds) -// <0-65535:1> -// Default: 2 -#define SL_RAIL_UTIL_PA_RAMP_TIME_US 2 -// Milli-volts on PA supply pin (PA_VDD) -// <0-65535:1> -// Default: 3300 -#define SL_RAIL_UTIL_PA_VOLTAGE_MV 3300 -// 2.4 GHz PA Selection -// Highest Possible -// High Power (chip-specific) -// Low Power -// Disable -// Default: RAIL_TX_POWER_MODE_2P4GIG_HIGHEST -#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HIGHEST -// Sub-1 GHz PA Selection -// Disable -// Default: RAIL_TX_POWER_MODE_NONE -#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE -// - -// PA Curve Configuration -// Header file containing custom PA curves -// Default: "pa_curves_efr32.h" -#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" -// Header file containing PA curve types -// Default: "pa_curve_types_efr32.h" -#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" -// - -// PA Calibration Configuration -// Apply PA Calibration Factory Offset -// Default: 1 -#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 -// - -// <<< end of configuration section >>> - -#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4001a/sl_rail_util_pti_config.h b/hardware/board/config/brd4111a_brd4001a/sl_rail_util_pti_config.h deleted file mode 100644 index ce4bb0db27..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/sl_rail_util_pti_config.h +++ /dev/null @@ -1,73 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Packet Trace Information configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_RAIL_UTIL_PTI_CONFIG_H -#define SL_RAIL_UTIL_PTI_CONFIG_H - -#include "rail_types.h" - -// <<< Use Configuration Wizard in Context Menu >>> -// PTI Configuration - -// PTI mode -// UART -// UART onewire -// SPI -// Disabled -// Default: RAIL_PTI_MODE_UART -#define SL_RAIL_UTIL_PTI_MODE RAIL_PTI_MODE_UART - -// PTI Baud Rate (Hertz) -// <147800-20000000:1> -// Default: 1600000 -#define SL_RAIL_UTIL_PTI_BAUD_RATE_HZ 1600000 - -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_RAIL_UTIL_PTI -// $[PTI_SL_RAIL_UTIL_PTI] -#define SL_RAIL_UTIL_PTI_PERIPHERAL PTI - -// PTI DOUT on PC00 -#define SL_RAIL_UTIL_PTI_DOUT_PORT gpioPortC -#define SL_RAIL_UTIL_PTI_DOUT_PIN 0 - -// PTI DFRAME on PC01 -#define SL_RAIL_UTIL_PTI_DFRAME_PORT gpioPortC -#define SL_RAIL_UTIL_PTI_DFRAME_PIN 1 - - -// [PTI_SL_RAIL_UTIL_PTI]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_RAIL_UTIL_PTI_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4001a/sl_simple_button_btn0_config.h b/hardware/board/config/brd4111a_brd4001a/sl_simple_button_btn0_config.h deleted file mode 100644 index aab8db6f10..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/sl_simple_button_btn0_config.h +++ /dev/null @@ -1,45 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple Button Driver User Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_BUTTON_BTN0_CONFIG_H -#define SL_SIMPLE_BUTTON_BTN0_CONFIG_H - -#include "em_gpio.h" -#include "sl_simple_button.h" - -// <<< Use Configuration Wizard in Context Menu >>> - -// -// Interrupt -// Poll and Debounce -// Poll -// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT -#define SL_SIMPLE_BUTTON_BTN0_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_BUTTON_BTN0 -// $[GPIO_SL_SIMPLE_BUTTON_BTN0] -#define SL_SIMPLE_BUTTON_BTN0_PORT gpioPortC -#define SL_SIMPLE_BUTTON_BTN0_PIN 5 - -// [GPIO_SL_SIMPLE_BUTTON_BTN0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_BUTTON_BTN0_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4001a/sl_simple_button_btn1_config.h b/hardware/board/config/brd4111a_brd4001a/sl_simple_button_btn1_config.h deleted file mode 100644 index 2a9fde7738..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/sl_simple_button_btn1_config.h +++ /dev/null @@ -1,45 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple Button Driver User Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_BUTTON_BTN1_CONFIG_H -#define SL_SIMPLE_BUTTON_BTN1_CONFIG_H - -#include "em_gpio.h" -#include "sl_simple_button.h" - -// <<< Use Configuration Wizard in Context Menu >>> - -// -// Interrupt -// Poll and Debounce -// Poll -// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT -#define SL_SIMPLE_BUTTON_BTN1_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_BUTTON_BTN1 -// $[GPIO_SL_SIMPLE_BUTTON_BTN1] -#define SL_SIMPLE_BUTTON_BTN1_PORT gpioPortC -#define SL_SIMPLE_BUTTON_BTN1_PIN 4 - -// [GPIO_SL_SIMPLE_BUTTON_BTN1]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_BUTTON_BTN1_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4111a_brd4001a/sl_uartdrv_eusart_exp_config.h deleted file mode 100644 index a89e4ccc3e..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ /dev/null @@ -1,100 +0,0 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV_EUSART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_UARTDRV_EUSART_EXP_CONFIG_H -#define SL_UARTDRV_EUSART_EXP_CONFIG_H - -#include "em_eusart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// EUSART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_EUSART_EXP_BAUDRATE 115200 - -// Low frequency mode -// True -// False -#define SL_UARTDRV_EUSART_EXP_LF_MODE false - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: eusartNoParity -#define SL_UARTDRV_EUSART_EXP_PARITY eusartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: eusartStopbits1 -#define SL_UARTDRV_EUSART_EXP_STOP_BITS eusartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHw -#define SL_UARTDRV_EUSART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Oversampling disabled -// Default: eusartOVS16 -#define SL_UARTDRV_EUSART_EXP_OVERSAMPLING eusartOVS16 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// False -// True -// Default: eusartMajorityVoteEnable -#define SL_UARTDRV_EUSART_EXP_MVDIS eusartMajorityVoteEnable - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_EUSART_EXP_RX_BUFFER_SIZE 6 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_EUSART_EXP_TX_BUFFER_SIZE 6 -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_EUSART_EXP -// $[EUSART_SL_UARTDRV_EUSART_EXP] -#define SL_UARTDRV_EUSART_EXP_PERIPHERAL EUSART0 -#define SL_UARTDRV_EUSART_EXP_PERIPHERAL_NO 0 - -// EUSART0 TX on PA05 -#define SL_UARTDRV_EUSART_EXP_TX_PORT gpioPortA -#define SL_UARTDRV_EUSART_EXP_TX_PIN 5 - -// EUSART0 RX on PA06 -#define SL_UARTDRV_EUSART_EXP_RX_PORT gpioPortA -#define SL_UARTDRV_EUSART_EXP_RX_PIN 6 - - - -// [EUSART_SL_UARTDRV_EUSART_EXP]$ -// <<< sl:end pin_tool >>> -#endif // SL_UARTDRV_EUSART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4001a/sl_uartdrv_eusart_vcom_config.h b/hardware/board/config/brd4111a_brd4001a/sl_uartdrv_eusart_vcom_config.h deleted file mode 100644 index a37bc4e70b..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/sl_uartdrv_eusart_vcom_config.h +++ /dev/null @@ -1,106 +0,0 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV_EUSART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_UARTDRV_EUSART_VCOM_CONFIG_H -#define SL_UARTDRV_EUSART_VCOM_CONFIG_H - -#include "em_eusart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// EUSART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_EUSART_VCOM_BAUDRATE 115200 - -// Low frequency mode -// True -// False -#define SL_UARTDRV_EUSART_VCOM_LF_MODE false - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: eusartNoParity -#define SL_UARTDRV_EUSART_VCOM_PARITY eusartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: eusartStopbits1 -#define SL_UARTDRV_EUSART_VCOM_STOP_BITS eusartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHw -#define SL_UARTDRV_EUSART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Oversampling disabled -// Default: eusartOVS16 -#define SL_UARTDRV_EUSART_VCOM_OVERSAMPLING eusartOVS16 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// False -// True -// Default: eusartMajorityVoteEnable -#define SL_UARTDRV_EUSART_VCOM_MVDIS eusartMajorityVoteEnable - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_EUSART_VCOM_RX_BUFFER_SIZE 6 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_EUSART_VCOM_TX_BUFFER_SIZE 6 -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_EUSART_VCOM -// $[EUSART_SL_UARTDRV_EUSART_VCOM] -#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL EUSART0 -#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL_NO 0 - -// EUSART0 TX on PA05 -#define SL_UARTDRV_EUSART_VCOM_TX_PORT gpioPortA -#define SL_UARTDRV_EUSART_VCOM_TX_PIN 5 - -// EUSART0 RX on PA06 -#define SL_UARTDRV_EUSART_VCOM_RX_PORT gpioPortA -#define SL_UARTDRV_EUSART_VCOM_RX_PIN 6 - -// EUSART0 CTS on PA04 -#define SL_UARTDRV_EUSART_VCOM_CTS_PORT gpioPortA -#define SL_UARTDRV_EUSART_VCOM_CTS_PIN 4 - -// EUSART0 RTS on PA00 -#define SL_UARTDRV_EUSART_VCOM_RTS_PORT gpioPortA -#define SL_UARTDRV_EUSART_VCOM_RTS_PIN 0 - -// [EUSART_SL_UARTDRV_EUSART_VCOM]$ -// <<< sl:end pin_tool >>> -#endif // SL_UARTDRV_EUSART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4111a_brd4001a/sl_uartdrv_usart_exp_config.h deleted file mode 100644 index 02662139f3..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/sl_uartdrv_usart_exp_config.h +++ /dev/null @@ -1,95 +0,0 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV_USART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_UARTDRV_USART_EXP_CONFIG_H -#define SL_UARTDRV_USART_EXP_CONFIG_H - -#include "em_usart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// UART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_USART_EXP_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_UARTDRV_USART_EXP_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_UARTDRV_USART_EXP_STOP_BITS usartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHw -#define SL_UARTDRV_USART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Default: usartOVS16 -#define SL_UARTDRV_USART_EXP_OVERSAMPLING usartOVS4 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// True -// False -#define SL_UARTDRV_USART_EXP_MVDIS false - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_USART_EXP_RX_BUFFER_SIZE 6 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_USART_EXP_TX_BUFFER_SIZE 6 - -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_USART_EXP -// $[USART_SL_UARTDRV_USART_EXP] -#define SL_UARTDRV_USART_EXP_PERIPHERAL USART0 -#define SL_UARTDRV_USART_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_UARTDRV_USART_EXP_TX_PORT gpioPortA -#define SL_UARTDRV_USART_EXP_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_UARTDRV_USART_EXP_RX_PORT gpioPortA -#define SL_UARTDRV_USART_EXP_RX_PIN 6 - - - -// [USART_SL_UARTDRV_USART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif // SL_UARTDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4001a/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd4111a_brd4001a/sl_uartdrv_usart_vcom_config.h deleted file mode 100644 index e0cc8cbeac..0000000000 --- a/hardware/board/config/brd4111a_brd4001a/sl_uartdrv_usart_vcom_config.h +++ /dev/null @@ -1,101 +0,0 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV_USART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H -#define SL_UARTDRV_USART_VCOM_CONFIG_H - -#include "em_usart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// UART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHw -#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Default: usartOVS16 -#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// True -// False -#define SL_UARTDRV_USART_VCOM_MVDIS false - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 6 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 6 - -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_USART_VCOM -// $[USART_SL_UARTDRV_USART_VCOM] -#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART0 -#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortA -#define SL_UARTDRV_USART_VCOM_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortA -#define SL_UARTDRV_USART_VCOM_RX_PIN 6 - -// USART0 CTS on PA04 -#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA -#define SL_UARTDRV_USART_VCOM_CTS_PIN 4 - -// USART0 RTS on PA00 -#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA -#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 - -// [USART_SL_UARTDRV_USART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4002a/btl_euart_driver_cfg.h b/hardware/board/config/brd4111a_brd4002a/btl_euart_driver_cfg.h deleted file mode 100644 index 850c0169c0..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/btl_euart_driver_cfg.h +++ /dev/null @@ -1,88 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader euart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_EUART_DRIVER_CONFIG_H -#define BTL_EUART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// EUART settings - -// Baud rate -// Default: 115200 -#define SL_SERIAL_EUART_BAUD_RATE 115200 - -// Hardware flow control -// Default: 0 -#define SL_SERIAL_EUART_FLOW_CONTROL 0 -// - -// Receive buffer size -// <0-2048:1> -// Default: 512 [0-2048] -#define SL_DRIVER_EUART_RX_BUFFER_SIZE 512 - -// Transmit buffer size -// <0-2048:1> -// Default: 128 [0-2048] -#define SL_DRIVER_EUART_TX_BUFFER_SIZE 128 - -// Virtual COM Port -// Default: 0 -#define SL_VCOM_ENABLE 0 -// - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_SERIAL_EUART -// $[EUSART_SL_SERIAL_EUART] -#define SL_SERIAL_EUART_PERIPHERAL EUSART0 -#define SL_SERIAL_EUART_PERIPHERAL_NO 0 - -// EUSART0 TX on PA05 -#define SL_SERIAL_EUART_TX_PORT gpioPortA -#define SL_SERIAL_EUART_TX_PIN 5 - -// EUSART0 RX on PA06 -#define SL_SERIAL_EUART_RX_PORT gpioPortA -#define SL_SERIAL_EUART_RX_PIN 6 - -// EUSART0 CTS on PA04 -#define SL_SERIAL_EUART_CTS_PORT gpioPortA -#define SL_SERIAL_EUART_CTS_PIN 4 - -// EUSART0 RTS on PA00 -#define SL_SERIAL_EUART_RTS_PORT gpioPortA -#define SL_SERIAL_EUART_RTS_PIN 0 - -// [EUSART_SL_SERIAL_EUART]$ - - -// SL_VCOM_ENABLE - -// $[GPIO_SL_VCOM_ENABLE] -#define SL_VCOM_ENABLE_PORT gpioPortC -#define SL_VCOM_ENABLE_PIN 3 - -// [GPIO_SL_VCOM_ENABLE]$ - - -// <<< sl:end pin_tool >>> - -#endif // BTL_EUART_DRIVER_CONFIG_H \ No newline at end of file diff --git a/hardware/board/config/brd4111a_brd4002a/btl_ezsp_gpio_activation_cfg.h b/hardware/board/config/brd4111a_brd4002a/btl_ezsp_gpio_activation_cfg.h deleted file mode 100644 index 620a881b5e..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/btl_ezsp_gpio_activation_cfg.h +++ /dev/null @@ -1,52 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader EZSP GPIO Activation - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_EZSP_GPIO_ACTIVATION_CONFIG_H -#define BTL_EZSP_GPIO_ACTIVATION_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Properties of SPI NCP - -// Active state -// Low -// High -// Default: LOW -// Enter firmware upgrade mode if GPIO pin has this state -#define SL_EZSP_GPIO_ACTIVATION_POLARITY LOW - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_EZSPSPI_HOST_INT -// $[GPIO_SL_EZSPSPI_HOST_INT] -#define SL_EZSPSPI_HOST_INT_PORT gpioPortC -#define SL_EZSPSPI_HOST_INT_PIN 5 - -// [GPIO_SL_EZSPSPI_HOST_INT]$ - -// SL_EZSPSPI_WAKE_INT -// $[GPIO_SL_EZSPSPI_WAKE_INT] -#define SL_EZSPSPI_WAKE_INT_PORT gpioPortC -#define SL_EZSPSPI_WAKE_INT_PIN 4 - -// [GPIO_SL_EZSPSPI_WAKE_INT]$ - -// <<< sl:end pin_tool >>> - -#endif // BTL_EZSP_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4002a/btl_gpio_activation_cfg.h b/hardware/board/config/brd4111a_brd4002a/btl_gpio_activation_cfg.h deleted file mode 100644 index 51573b25df..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/btl_gpio_activation_cfg.h +++ /dev/null @@ -1,49 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader GPIO Activation - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_GPIO_ACTIVATION_CONFIG_H -#define BTL_GPIO_ACTIVATION_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Properties of Bootloader Entry - - -// Active state -// Low -// High -// Default: LOW -// Enter firmware upgrade mode if GPIO pin has this state -#define SL_GPIO_ACTIVATION_POLARITY LOW - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_BTL_BUTTON - -// $[GPIO_SL_BTL_BUTTON] -#define SL_BTL_BUTTON_PORT gpioPortC -#define SL_BTL_BUTTON_PIN 5 - -// [GPIO_SL_BTL_BUTTON]$ - -// <<< sl:end pin_tool >>> - - -#endif // BTL_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4002a/btl_spi_controller_eusart_driver_cfg.h b/hardware/board/config/brd4111a_brd4002a/btl_spi_controller_eusart_driver_cfg.h deleted file mode 100644 index 308060ef81..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/btl_spi_controller_eusart_driver_cfg.h +++ /dev/null @@ -1,68 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader Spi Controller Eusart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H -#define BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// SPI Controller EUSART Driver - -// Frequency -// Default: 6400000 -#define SL_EUSART_EXTFLASH_FREQUENCY 6400000 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_EUSART_EXTFLASH -// $[EUSART_SL_EUSART_EXTFLASH] -#define SL_EUSART_EXTFLASH_PERIPHERAL EUSART0 -#define SL_EUSART_EXTFLASH_PERIPHERAL_NO 0 - -// EUSART0 TX on PB00 -#define SL_EUSART_EXTFLASH_TX_PORT gpioPortB -#define SL_EUSART_EXTFLASH_TX_PIN 0 - -// EUSART0 RX on PB01 -#define SL_EUSART_EXTFLASH_RX_PORT gpioPortB -#define SL_EUSART_EXTFLASH_RX_PIN 1 - -// EUSART0 SCLK on PB02 -#define SL_EUSART_EXTFLASH_SCLK_PORT gpioPortB -#define SL_EUSART_EXTFLASH_SCLK_PIN 2 - -// EUSART0 CS on PC02 -#define SL_EUSART_EXTFLASH_CS_PORT gpioPortC -#define SL_EUSART_EXTFLASH_CS_PIN 2 - -// [EUSART_SL_EUSART_EXTFLASH]$ - -// SL_EXTFLASH_WP -// $[GPIO_SL_EXTFLASH_WP] - -// [GPIO_SL_EXTFLASH_WP]$ - -// SL_EXTFLASH_HOLD -// $[GPIO_SL_EXTFLASH_HOLD] - -// [GPIO_SL_EXTFLASH_HOLD]$ - -// <<< sl:end pin_tool >>> - -#endif // BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4002a/btl_spi_controller_usart_driver_cfg.h b/hardware/board/config/brd4111a_brd4002a/btl_spi_controller_usart_driver_cfg.h deleted file mode 100644 index 6ac5f54418..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/btl_spi_controller_usart_driver_cfg.h +++ /dev/null @@ -1,68 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader Spi Controller Usart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H -#define BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// SPI Controller USART Driver - -// Frequency -// Default: 6400000 -#define SL_USART_EXTFLASH_FREQUENCY 6400000 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_USART_EXTFLASH -// $[USART_SL_USART_EXTFLASH] -#define SL_USART_EXTFLASH_PERIPHERAL USART0 -#define SL_USART_EXTFLASH_PERIPHERAL_NO 0 - -// USART0 TX on PB00 -#define SL_USART_EXTFLASH_TX_PORT gpioPortB -#define SL_USART_EXTFLASH_TX_PIN 0 - -// USART0 RX on PB01 -#define SL_USART_EXTFLASH_RX_PORT gpioPortB -#define SL_USART_EXTFLASH_RX_PIN 1 - -// USART0 CLK on PB02 -#define SL_USART_EXTFLASH_CLK_PORT gpioPortB -#define SL_USART_EXTFLASH_CLK_PIN 2 - -// USART0 CS on PC02 -#define SL_USART_EXTFLASH_CS_PORT gpioPortC -#define SL_USART_EXTFLASH_CS_PIN 2 - -// [USART_SL_USART_EXTFLASH]$ - -// SL_EXTFLASH_WP -// $[GPIO_SL_EXTFLASH_WP] - -// [GPIO_SL_EXTFLASH_WP]$ - -// SL_EXTFLASH_HOLD -// $[GPIO_SL_EXTFLASH_HOLD] - -// [GPIO_SL_EXTFLASH_HOLD]$ - -// <<< sl:end pin_tool >>> - -#endif // BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4002a/btl_uart_driver_cfg.h b/hardware/board/config/brd4111a_brd4002a/btl_uart_driver_cfg.h deleted file mode 100644 index 602dc337c0..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/btl_uart_driver_cfg.h +++ /dev/null @@ -1,89 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader Uart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_UART_DRIVER_CONFIG_H -#define BTL_UART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// USART settings - -// Baud rate -// Default: 115200 -#define SL_SERIAL_UART_BAUD_RATE 115200 - -// Hardware flow control -// Default: 0 -#define SL_SERIAL_UART_FLOW_CONTROL 0 -// - -// Receive buffer size -// <0-2048:1> -// Default: 512 [0-2048] -#define SL_DRIVER_UART_RX_BUFFER_SIZE 512 - -// Transmit buffer size -// <0-2048:1> -// Default: 128 [0-2048] -#define SL_DRIVER_UART_TX_BUFFER_SIZE 128 - -// Virtual COM Port -// Default: 0 -#define SL_VCOM_ENABLE 0 -// - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_SERIAL_UART -// $[USART_SL_SERIAL_UART] -#define SL_SERIAL_UART_PERIPHERAL USART0 -#define SL_SERIAL_UART_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_SERIAL_UART_TX_PORT gpioPortA -#define SL_SERIAL_UART_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_SERIAL_UART_RX_PORT gpioPortA -#define SL_SERIAL_UART_RX_PIN 6 - -// USART0 CTS on PA04 -#define SL_SERIAL_UART_CTS_PORT gpioPortA -#define SL_SERIAL_UART_CTS_PIN 4 - -// USART0 RTS on PA00 -#define SL_SERIAL_UART_RTS_PORT gpioPortA -#define SL_SERIAL_UART_RTS_PIN 0 - -// [USART_SL_SERIAL_UART]$ - - - -// SL_VCOM_ENABLE - -// $[GPIO_SL_VCOM_ENABLE] -#define SL_VCOM_ENABLE_PORT gpioPortC -#define SL_VCOM_ENABLE_PIN 3 - -// [GPIO_SL_VCOM_ENABLE]$ - - -// <<< sl:end pin_tool >>> - -#endif // BTL_UART_DRIVER_CONFIG_H \ No newline at end of file diff --git a/hardware/board/config/brd4111a_brd4002a/iot_flash_cfg_spiflash.h b/hardware/board/config/brd4111a_brd4002a/iot_flash_cfg_spiflash.h deleted file mode 100644 index 3b634d9b08..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/iot_flash_cfg_spiflash.h +++ /dev/null @@ -1,136 +0,0 @@ -/***************************************************************************//** - * @file iot_flash_cfg_inst.h - * @brief Common I/O flash instance configurations. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_FLASH_CFG_SPIFLASH_H_ -#define _IOT_FLASH_CFG_SPIFLASH_H_ - -/******************************************************************************* - * Flash Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// Flash General Options - -// Instance number -// Instance number used when iot_flash_open() is called. -// Default: 0 -#define IOT_FLASH_CFG_SPIFLASH_INST_NUM 0 - -// Instance type -// <0=> Internal Flash (MSC) -// <1=> External Flash (SPI) -// Specify whether this instance is for internal flash (MSC) -// or an external SPI flash. If external, then you need to setup -// SPI configs below. -// Default: 0 -#define IOT_FLASH_CFG_SPIFLASH_INST_TYPE 1 - -// - -// SPI Configuration - -// Default SPI bitrate -// Default: 1000000 -#define IOT_FLASH_CFG_SPIFLASH_SPI_BITRATE 1000000 - -// Default SPI frame length <4-16> -// Default: 8 -#define IOT_FLASH_CFG_SPIFLASH_SPI_FRAME_LENGTH 8 - -// Default SPI master/slave mode -// Master -// Slave -#define IOT_FLASH_CFG_SPIFLASH_SPI_TYPE spidrvMaster - -// Default SPI bit order -// LSB transmitted first -// MSB transmitted first -#define IOT_FLASH_CFG_SPIFLASH_SPI_BIT_ORDER spidrvBitOrderMsbFirst - -// Default SPI clock mode -// SPI mode 0: CLKPOL=0, CLKPHA=0 -// SPI mode 1: CLKPOL=0, CLKPHA=1 -// SPI mode 2: CLKPOL=1, CLKPHA=0 -// SPI mode 3: CLKPOL=1, CLKPHA=1 -#define IOT_FLASH_CFG_SPIFLASH_SPI_CLOCK_MODE spidrvClockMode0 - -// Default SPI CS control scheme -// CS controlled by the SPI driver -// CS controlled by the application -#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_CONTROL spidrvCsControlApplication - -// Default SPI transfer scheme -// Transfer starts immediately -// Transfer starts when the bus is idle -#define IOT_FLASH_CFG_SPIFLASH_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * EXTERNAL FLASH: H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_FLASH_CFG_SPIFLASH_SPI -// $[USART_IOT_FLASH_CFG_SPIFLASH_SPI] -#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL USART0 -#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL_NO 0 - -// USART0 TX on PB00 -#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PORT gpioPortB -#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PIN 0 - -// USART0 RX on PB01 -#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PORT gpioPortB -#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PIN 1 - -// USART0 CLK on PB02 -#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PORT gpioPortB -#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PIN 2 - -// USART0 CS on PC02 -#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PORT gpioPortC -#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PIN 2 - -// [USART_IOT_FLASH_CFG_SPIFLASH_SPI]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_FLASH_CFG_SPIFLASH_H_ */ diff --git a/hardware/board/config/brd4111a_brd4002a/iot_pwm_cfg_exp.h b/hardware/board/config/brd4111a_brd4002a/iot_pwm_cfg_exp.h deleted file mode 100644 index 306f255589..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/iot_pwm_cfg_exp.h +++ /dev/null @@ -1,78 +0,0 @@ -/***************************************************************************//** - * @file iot_pwm_cfg_inst.h - * @brief Common I/O PWM instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_PWM_CFG_EXP_H_ -#define _IOT_PWM_CFG_EXP_H_ - -/******************************************************************************* - * PWM Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// PWM General Options - -// Instance number -// Instance number used when iot_pwm_open() is called. -// Default: 0 -#define IOT_PWM_CFG_EXP_INST_NUM 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_PWM_CFG_EXP -// $[TIMER_IOT_PWM_CFG_EXP] -#define IOT_PWM_CFG_EXP_PERIPHERAL TIMER3 -#define IOT_PWM_CFG_EXP_PERIPHERAL_NO 3 - -// TIMER3 CC0 on PC05 -#define IOT_PWM_CFG_EXP_CC0_PORT gpioPortC -#define IOT_PWM_CFG_EXP_CC0_PIN 5 - - - -// [TIMER_IOT_PWM_CFG_EXP]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_PWM_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4111a_brd4002a/iot_uart_cfg_exp.h b/hardware/board/config/brd4111a_brd4002a/iot_uart_cfg_exp.h deleted file mode 100644 index 02f62b7d87..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/iot_uart_cfg_exp.h +++ /dev/null @@ -1,126 +0,0 @@ -/***************************************************************************//** - * @file iot_uart_cfg_inst.h - * @brief Common I/O UART instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_UART_CFG_EXP_H_ -#define _IOT_UART_CFG_EXP_H_ - -/******************************************************************************* - * UART Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// UART General Options - -// Instance number -// Instance number used when iot_uart_open() is called. -// Default: 0 -#define IOT_UART_CFG_EXP_INST_NUM 0 - -// Default baud rate -// Default: 115200 -#define IOT_UART_CFG_EXP_DEFAULT_BAUDRATE 115200 - -// Default number of data bits -// 4 data bits -// 5 data bits -// 6 data bits -// 7 data bits -// 8 data bits -// Default: usartDatabits8 -#define IOT_UART_CFG_EXP_DEFAULT_DATA_BITS usartDatabits8 - -// Default parity mode -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define IOT_UART_CFG_EXP_DEFAULT_PARITY usartNoParity - -// Default number of stop bits -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define IOT_UART_CFG_EXP_DEFAULT_STOP_BITS usartStopbits1 - -// Default hardware flow control -// None -// CTS -// RTS -// CTS/RTS -// Default: usartHwFlowControlNone -#define IOT_UART_CFG_EXP_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone - - -// Internal Loopback -// Enable USART Internal loopback -// Default: 0 -#define IOT_UART_CFG_EXP_LOOPBACK 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_UART_CFG_EXP -// $[USART_IOT_UART_CFG_EXP] -#define IOT_UART_CFG_EXP_PERIPHERAL USART0 -#define IOT_UART_CFG_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define IOT_UART_CFG_EXP_TX_PORT gpioPortA -#define IOT_UART_CFG_EXP_TX_PIN 5 - -// USART0 RX on PA06 -#define IOT_UART_CFG_EXP_RX_PORT gpioPortA -#define IOT_UART_CFG_EXP_RX_PIN 6 - - - - - -// [USART_IOT_UART_CFG_EXP]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_UART_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4111a_brd4002a/iot_uart_cfg_loopback.h b/hardware/board/config/brd4111a_brd4002a/iot_uart_cfg_loopback.h deleted file mode 100644 index c426e68b97..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/iot_uart_cfg_loopback.h +++ /dev/null @@ -1,132 +0,0 @@ -/***************************************************************************//** - * @file iot_uart_cfg_inst.h - * @brief Common I/O UART instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_UART_CFG_LOOPBACK_H_ -#define _IOT_UART_CFG_LOOPBACK_H_ - -/******************************************************************************* - * UART Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// UART General Options - -// Instance number -// Instance number used when iot_uart_open() is called. -// Default: 0 -#define IOT_UART_CFG_LOOPBACK_INST_NUM 0 - -// Default baud rate -// Default: 115200 -#define IOT_UART_CFG_LOOPBACK_DEFAULT_BAUDRATE 115200 - -// Default number of data bits -// 4 data bits -// 5 data bits -// 6 data bits -// 7 data bits -// 8 data bits -// Default: usartDatabits8 -#define IOT_UART_CFG_LOOPBACK_DEFAULT_DATA_BITS usartDatabits8 - -// Default parity mode -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define IOT_UART_CFG_LOOPBACK_DEFAULT_PARITY usartNoParity - -// Default number of stop bits -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define IOT_UART_CFG_LOOPBACK_DEFAULT_STOP_BITS usartStopbits1 - -// Default hardware flow control -// None -// CTS -// RTS -// CTS/RTS -// Default: usartHwFlowControlNone -#define IOT_UART_CFG_LOOPBACK_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone - - -// Internal Loopback -// Enable USART Internal loopback -// Default: 0 -#define IOT_UART_CFG_LOOPBACK_LOOPBACK 1 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_UART_CFG_LOOPBACK -// $[USART_IOT_UART_CFG_LOOPBACK] -#define IOT_UART_CFG_LOOPBACK_PERIPHERAL USART0 -#define IOT_UART_CFG_LOOPBACK_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define IOT_UART_CFG_LOOPBACK_TX_PORT gpioPortA -#define IOT_UART_CFG_LOOPBACK_TX_PIN 5 - -// USART0 RX on PA06 -#define IOT_UART_CFG_LOOPBACK_RX_PORT gpioPortA -#define IOT_UART_CFG_LOOPBACK_RX_PIN 6 - - - -// USART0 RTS on PA00 -#define IOT_UART_CFG_LOOPBACK_RTS_PORT gpioPortA -#define IOT_UART_CFG_LOOPBACK_RTS_PIN 0 - -// USART0 CTS on PA04 -#define IOT_UART_CFG_LOOPBACK_CTS_PORT gpioPortA -#define IOT_UART_CFG_LOOPBACK_CTS_PIN 4 - -// [USART_IOT_UART_CFG_LOOPBACK]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_UART_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4111a_brd4002a/iot_uart_cfg_vcom.h b/hardware/board/config/brd4111a_brd4002a/iot_uart_cfg_vcom.h deleted file mode 100644 index e8b6e6e185..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/iot_uart_cfg_vcom.h +++ /dev/null @@ -1,132 +0,0 @@ -/***************************************************************************//** - * @file iot_uart_cfg_inst.h - * @brief Common I/O UART instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_UART_CFG_VCOM_H_ -#define _IOT_UART_CFG_VCOM_H_ - -/******************************************************************************* - * UART Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// UART General Options - -// Instance number -// Instance number used when iot_uart_open() is called. -// Default: 0 -#define IOT_UART_CFG_VCOM_INST_NUM 0 - -// Default baud rate -// Default: 115200 -#define IOT_UART_CFG_VCOM_DEFAULT_BAUDRATE 115200 - -// Default number of data bits -// 4 data bits -// 5 data bits -// 6 data bits -// 7 data bits -// 8 data bits -// Default: usartDatabits8 -#define IOT_UART_CFG_VCOM_DEFAULT_DATA_BITS usartDatabits8 - -// Default parity mode -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define IOT_UART_CFG_VCOM_DEFAULT_PARITY usartNoParity - -// Default number of stop bits -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define IOT_UART_CFG_VCOM_DEFAULT_STOP_BITS usartStopbits1 - -// Default hardware flow control -// None -// CTS -// RTS -// CTS/RTS -// Default: usartHwFlowControlNone -#define IOT_UART_CFG_VCOM_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone - - -// Internal Loopback -// Enable USART Internal loopback -// Default: 0 -#define IOT_UART_CFG_VCOM_LOOPBACK 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_UART_CFG_VCOM -// $[USART_IOT_UART_CFG_VCOM] -#define IOT_UART_CFG_VCOM_PERIPHERAL USART0 -#define IOT_UART_CFG_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define IOT_UART_CFG_VCOM_TX_PORT gpioPortA -#define IOT_UART_CFG_VCOM_TX_PIN 5 - -// USART0 RX on PA06 -#define IOT_UART_CFG_VCOM_RX_PORT gpioPortA -#define IOT_UART_CFG_VCOM_RX_PIN 6 - - - -// USART0 RTS on PA00 -#define IOT_UART_CFG_VCOM_RTS_PORT gpioPortA -#define IOT_UART_CFG_VCOM_RTS_PIN 0 - -// USART0 CTS on PA04 -#define IOT_UART_CFG_VCOM_CTS_PORT gpioPortA -#define IOT_UART_CFG_VCOM_CTS_PIN 4 - -// [USART_IOT_UART_CFG_VCOM]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_UART_CFG_VCOM_H_ */ diff --git a/hardware/board/config/brd4111a_brd4002a/sl_board_control_config.h b/hardware/board/config/brd4111a_brd4002a/sl_board_control_config.h deleted file mode 100644 index 7959f2d516..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/sl_board_control_config.h +++ /dev/null @@ -1,56 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Board Control - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_BOARD_CONTROL_CONFIG_H -#define SL_BOARD_CONTROL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Enable Virtual COM UART -// Default: 0 -#define SL_BOARD_ENABLE_VCOM 0 - -// Disable SPI Flash -// Default: 1 -#define SL_BOARD_DISABLE_MEMORY_SPI 1 - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_BOARD_ENABLE_VCOM -// $[GPIO_SL_BOARD_ENABLE_VCOM] -#define SL_BOARD_ENABLE_VCOM_PORT gpioPortC -#define SL_BOARD_ENABLE_VCOM_PIN 3 -// [GPIO_SL_BOARD_ENABLE_VCOM]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4002a/sl_cpc_drv_primary_uart_usart_exp_config.h b/hardware/board/config/brd4111a_brd4002a/sl_cpc_drv_primary_uart_usart_exp_config.h deleted file mode 100644 index 28f701fc44..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/sl_cpc_drv_primary_uart_usart_exp_config.h +++ /dev/null @@ -1,70 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC UART PRIMARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_USART_EXP_PRIMARY_CONFIG_H -#define SL_CPC_DRV_UART_USART_EXP_PRIMARY_CONFIG_H - -// CPC-Primary UART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 - -// UART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_EXP -// $[USART_SL_CPC_DRV_UART_EXP] -#define SL_CPC_DRV_UART_EXP_PERIPHERAL USART0 -#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_CPC_DRV_UART_EXP_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_CPC_DRV_UART_EXP_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_RX_PIN 6 - -// [USART_SL_CPC_DRV_UART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_EXP_PRIMARY_CONFIG_H */ diff --git a/hardware/board/config/brd4111a_brd4002a/sl_cpc_drv_primary_uart_usart_vcom_config.h b/hardware/board/config/brd4111a_brd4002a/sl_cpc_drv_primary_uart_usart_vcom_config.h deleted file mode 100644 index 7d51f4a7be..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/sl_cpc_drv_primary_uart_usart_vcom_config.h +++ /dev/null @@ -1,70 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC UART PRIMARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_USART_VCOM_PRIMARY_CONFIG_H -#define SL_CPC_DRV_UART_USART_VCOM_PRIMARY_CONFIG_H - -// CPC-Primary UART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 - -// UART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_VCOM -// $[USART_SL_CPC_DRV_UART_VCOM] -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_RX_PIN 6 - -// [USART_SL_CPC_DRV_UART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_VCOM_PRIMARY_CONFIG_H */ diff --git a/hardware/board/config/brd4111a_brd4002a/sl_cpc_drv_secondary_uart_eusart_exp_config.h b/hardware/board/config/brd4111a_brd4002a/sl_cpc_drv_secondary_uart_eusart_exp_config.h deleted file mode 100644 index b6b264813c..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/sl_cpc_drv_secondary_uart_eusart_exp_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC EUSART SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_EUSART_EXP_SECONDARY_CONFIG_H -#define SL_CPC_DRV_UART_EUSART_EXP_SECONDARY_CONFIG_H - -// CPC - Secondary EUSART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 - -// EUSART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 - -// Flow control -// None -// CTS/RTS -// Default: eusartHwFlowControlNone -#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_EXP -// $[EUSART_SL_CPC_DRV_UART_EXP] -#define SL_CPC_DRV_UART_EXP_PERIPHERAL EUSART0 -#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 - -// EUSART0 TX on PA05 -#define SL_CPC_DRV_UART_EXP_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_TX_PIN 5 - -// EUSART0 RX on PA06 -#define SL_CPC_DRV_UART_EXP_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_RX_PIN 6 - -// EUSART0 CTS on PA04 -#define SL_CPC_DRV_UART_EXP_CTS_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_CTS_PIN 4 - -// EUSART0 RTS on PA00 -#define SL_CPC_DRV_UART_EXP_RTS_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_RTS_PIN 0 - -// [EUSART_SL_CPC_DRV_UART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4111a_brd4002a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h b/hardware/board/config/brd4111a_brd4002a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h deleted file mode 100644 index a124e6f6fe..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC EUSART SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_EUSART_VCOM_SECONDARY_CONFIG_H -#define SL_CPC_DRV_UART_EUSART_VCOM_SECONDARY_CONFIG_H - -// CPC - Secondary EUSART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 - -// EUSART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 - -// Flow control -// None -// CTS/RTS -// Default: eusartHwFlowControlNone -#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_VCOM -// $[EUSART_SL_CPC_DRV_UART_VCOM] -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL EUSART0 -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 - -// EUSART0 TX on PA05 -#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_TX_PIN 5 - -// EUSART0 RX on PA06 -#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_RX_PIN 6 - -// EUSART0 CTS on PA04 -#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_CTS_PIN 4 - -// EUSART0 RTS on PA00 -#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_RTS_PIN 0 - -// [EUSART_SL_CPC_DRV_UART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_VCOM_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4111a_brd4002a/sl_cpc_drv_secondary_uart_usart_exp_config.h b/hardware/board/config/brd4111a_brd4002a/sl_cpc_drv_secondary_uart_usart_exp_config.h deleted file mode 100644 index ea3a86d650..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/sl_cpc_drv_secondary_uart_usart_exp_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC UART SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_USART_EXP_SECONDARY_CONFIG_H -#define SL_CPC_DRV_UART_USART_EXP_SECONDARY_CONFIG_H - -// CPC - Secondary UART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 - -// UART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 - -// Flow control -// None -// CTS/RTS -// Default: usartHwFlowControlCtsAndRts -#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_EXP -// $[USART_SL_CPC_DRV_UART_EXP] -#define SL_CPC_DRV_UART_EXP_PERIPHERAL USART0 -#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_CPC_DRV_UART_EXP_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_CPC_DRV_UART_EXP_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_RX_PIN 6 - -// USART0 CTS on PA04 -#define SL_CPC_DRV_UART_EXP_CTS_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_CTS_PIN 4 - -// USART0 RTS on PA00 -#define SL_CPC_DRV_UART_EXP_RTS_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_RTS_PIN 0 - -// [USART_SL_CPC_DRV_UART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4111a_brd4002a/sl_cpc_drv_secondary_uart_usart_vcom_config.h b/hardware/board/config/brd4111a_brd4002a/sl_cpc_drv_secondary_uart_usart_vcom_config.h deleted file mode 100644 index d164acc395..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/sl_cpc_drv_secondary_uart_usart_vcom_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC UART SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_USART_VCOM_SECONDARY_CONFIG_H -#define SL_CPC_DRV_UART_USART_VCOM_SECONDARY_CONFIG_H - -// CPC - Secondary UART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 - -// UART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 - -// Flow control -// None -// CTS/RTS -// Default: usartHwFlowControlCtsAndRts -#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_VCOM -// $[USART_SL_CPC_DRV_UART_VCOM] -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_RX_PIN 6 - -// USART0 CTS on PA04 -#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_CTS_PIN 4 - -// USART0 RTS on PA00 -#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_RTS_PIN 0 - -// [USART_SL_CPC_DRV_UART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_VCOM_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4111a_brd4002a/sl_device_init_hfxo_config.h b/hardware/board/config/brd4111a_brd4002a/sl_device_init_hfxo_config.h deleted file mode 100644 index b0938ac495..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/sl_device_init_hfxo_config.h +++ /dev/null @@ -1,53 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_HFXO Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H -#define SL_DEVICE_INIT_HFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// External sine wave -// Default: cmuHfxoOscMode_Crystal -#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal - -// Frequency <38000000-40000000> -// Default: 38400000 -#define SL_DEVICE_INIT_HFXO_FREQ 38400000 - -// CTUNE <0-255> -// Default: 140 -#define SL_DEVICE_INIT_HFXO_CTUNE 120 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4002a/sl_device_init_lfxo_config.h b/hardware/board/config/brd4111a_brd4002a/sl_device_init_lfxo_config.h deleted file mode 100644 index 0e1f4147bf..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/sl_device_init_lfxo_config.h +++ /dev/null @@ -1,66 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_LFXO Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H -#define SL_DEVICE_INIT_LFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// AC-coupled buffer -// External digital clock -// Default: cmuLfxoOscMode_Crystal -#define SL_DEVICE_INIT_LFXO_MODE cmuLfxoOscMode_Crystal - -// CTUNE <0-127> -// Default: 63 -#define SL_DEVICE_INIT_LFXO_CTUNE 37 - -// LFXO precision in PPM <0-65535> -// Default: 500 -#define SL_DEVICE_INIT_LFXO_PRECISION 100 - -// Startup Timeout Delay -// -// 2 cycles -// 256 cycles -// 1K cycles -// 2K cycles -// 4K cycles -// 8K cycles -// 16K cycles -// 32K cycles -// Default: cmuLfxoStartupDelay_4KCycles -#define SL_DEVICE_INIT_LFXO_TIMEOUT cmuLfxoStartupDelay_4KCycles -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4002a/sl_iostream_eusart_exp_config.h b/hardware/board/config/brd4111a_brd4002a/sl_iostream_eusart_exp_config.h deleted file mode 100644 index 298b5d2c75..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/sl_iostream_eusart_exp_config.h +++ /dev/null @@ -1,107 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_EUSART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_EUSART_EXP_CONFIG_H -#define SL_IOSTREAM_EUSART_EXP_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// EUART settings - -// Enable High frequency mode -// Default: 1 -#define SL_IOSTREAM_EUSART_EXP_ENABLE_HIGH_FREQUENCY 1 - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_EUSART_EXP_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: eusartNoParity -#define SL_IOSTREAM_EUSART_EXP_PARITY eusartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: eusartStopbits1 -#define SL_IOSTREAM_EUSART_EXP_STOP_BITS eusartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: eusartHwFlowControlNone -#define SL_IOSTREAM_EUSART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlNone - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_EUSART_EXP_RX_BUFFER_SIZE 32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_EUSART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_EUSART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_EUSART_EXP -// $[EUSART_SL_IOSTREAM_EUSART_EXP] -#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL EUSART0 -#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL_NO 0 - -// EUSART0 TX on PA05 -#define SL_IOSTREAM_EUSART_EXP_TX_PORT gpioPortA -#define SL_IOSTREAM_EUSART_EXP_TX_PIN 5 - -// EUSART0 RX on PA06 -#define SL_IOSTREAM_EUSART_EXP_RX_PORT gpioPortA -#define SL_IOSTREAM_EUSART_EXP_RX_PIN 6 - - - -// [EUSART_SL_IOSTREAM_EUSART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4111a_brd4002a/sl_iostream_eusart_vcom_config.h b/hardware/board/config/brd4111a_brd4002a/sl_iostream_eusart_vcom_config.h deleted file mode 100644 index aa477c44ff..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/sl_iostream_eusart_vcom_config.h +++ /dev/null @@ -1,113 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_EUSART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_EUSART_VCOM_CONFIG_H -#define SL_IOSTREAM_EUSART_VCOM_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// EUART settings - -// Enable High frequency mode -// Default: 1 -#define SL_IOSTREAM_EUSART_VCOM_ENABLE_HIGH_FREQUENCY 1 - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_EUSART_VCOM_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: eusartNoParity -#define SL_IOSTREAM_EUSART_VCOM_PARITY eusartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: eusartStopbits1 -#define SL_IOSTREAM_EUSART_VCOM_STOP_BITS eusartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: eusartHwFlowControlNone -#define SL_IOSTREAM_EUSART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_EUSART_VCOM_RX_BUFFER_SIZE 32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_EUSART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_EUSART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_EUSART_VCOM -// $[EUSART_SL_IOSTREAM_EUSART_VCOM] -#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL EUSART0 -#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL_NO 0 - -// EUSART0 TX on PA05 -#define SL_IOSTREAM_EUSART_VCOM_TX_PORT gpioPortA -#define SL_IOSTREAM_EUSART_VCOM_TX_PIN 5 - -// EUSART0 RX on PA06 -#define SL_IOSTREAM_EUSART_VCOM_RX_PORT gpioPortA -#define SL_IOSTREAM_EUSART_VCOM_RX_PIN 6 - -// EUSART0 CTS on PA04 -#define SL_IOSTREAM_EUSART_VCOM_CTS_PORT gpioPortA -#define SL_IOSTREAM_EUSART_VCOM_CTS_PIN 4 - -// EUSART0 RTS on PA00 -#define SL_IOSTREAM_EUSART_VCOM_RTS_PORT gpioPortA -#define SL_IOSTREAM_EUSART_VCOM_RTS_PIN 0 - -// [EUSART_SL_IOSTREAM_EUSART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4111a_brd4002a/sl_iostream_usart_exp_config.h b/hardware/board/config/brd4111a_brd4002a/sl_iostream_usart_exp_config.h deleted file mode 100644 index 8669faa1a4..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/sl_iostream_usart_exp_config.h +++ /dev/null @@ -1,103 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_USART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_USART_EXP_CONFIG_H -#define SL_IOSTREAM_USART_EXP_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// USART settings - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_USART_EXP_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_IOSTREAM_USART_EXP_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_IOSTREAM_USART_EXP_STOP_BITS usartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: usartHwFlowControlNone -#define SL_IOSTREAM_USART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlNone - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_USART_EXP_RX_BUFFER_SIZE 32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_USART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_USART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_USART_EXP -// $[USART_SL_IOSTREAM_USART_EXP] -#define SL_IOSTREAM_USART_EXP_PERIPHERAL USART0 -#define SL_IOSTREAM_USART_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_IOSTREAM_USART_EXP_TX_PORT gpioPortA -#define SL_IOSTREAM_USART_EXP_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_IOSTREAM_USART_EXP_RX_PORT gpioPortA -#define SL_IOSTREAM_USART_EXP_RX_PIN 6 - - - -// [USART_SL_IOSTREAM_USART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4111a_brd4002a/sl_iostream_usart_vcom_config.h b/hardware/board/config/brd4111a_brd4002a/sl_iostream_usart_vcom_config.h deleted file mode 100644 index fa080aaeb7..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/sl_iostream_usart_vcom_config.h +++ /dev/null @@ -1,109 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_USART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H -#define SL_IOSTREAM_USART_VCOM_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// USART settings - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_USART_VCOM_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: usartHwFlowControlNone -#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_USART_VCOM -// $[USART_SL_IOSTREAM_USART_VCOM] -#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART0 -#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_IOSTREAM_USART_VCOM_TX_PORT gpioPortA -#define SL_IOSTREAM_USART_VCOM_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_IOSTREAM_USART_VCOM_RX_PORT gpioPortA -#define SL_IOSTREAM_USART_VCOM_RX_PIN 6 - -// USART0 CTS on PA04 -#define SL_IOSTREAM_USART_VCOM_CTS_PORT gpioPortA -#define SL_IOSTREAM_USART_VCOM_CTS_PIN 4 - -// USART0 RTS on PA00 -#define SL_IOSTREAM_USART_VCOM_RTS_PORT gpioPortA -#define SL_IOSTREAM_USART_VCOM_RTS_PIN 0 - -// [USART_SL_IOSTREAM_USART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4111a_brd4002a/sl_mx25_flash_shutdown_eusart_config.h b/hardware/board/config/brd4111a_brd4002a/sl_mx25_flash_shutdown_eusart_config.h deleted file mode 100644 index 3d804d2bea..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/sl_mx25_flash_shutdown_eusart_config.h +++ /dev/null @@ -1,51 +0,0 @@ -/***************************************************************************//** - * @file - * @brief SL_MX25_FLASH_SHUTDOWN_USART Config - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H -#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H - -// <<< sl:start pin_tool >>> -// {eusart signal=TX,RX,SCLK} SL_MX25_FLASH_SHUTDOWN -// [EUSART_SL_MX25_FLASH_SHUTDOWN] -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL EUSART0 -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 - -// EUSART0 TX on PB00 -#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortB -#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 0 - -// EUSART0 RX on PB01 -#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortB -#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 - -// EUSART0 SCLK on PB02 -#define SL_MX25_FLASH_SHUTDOWN_SCLK_PORT gpioPortB -#define SL_MX25_FLASH_SHUTDOWN_SCLK_PIN 2 - -// [EUSART_SL_MX25_FLASH_SHUTDOWN] - -// SL_MX25_FLASH_SHUTDOWN_CS - -// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] -#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortC -#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 2 - -// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4002a/sl_mx25_flash_shutdown_usart_config.h b/hardware/board/config/brd4111a_brd4002a/sl_mx25_flash_shutdown_usart_config.h deleted file mode 100644 index 06eb2da111..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/sl_mx25_flash_shutdown_usart_config.h +++ /dev/null @@ -1,51 +0,0 @@ -/***************************************************************************//** - * @file - * @brief SL_MX25_FLASH_SHUTDOWN_USART Config - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H -#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H - -// <<< sl:start pin_tool >>> -// {usart signal=TX,RX,CLK} SL_MX25_FLASH_SHUTDOWN -// [USART_SL_MX25_FLASH_SHUTDOWN] -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL USART0 -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 - -// USART0 TX on PB00 -#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortB -#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 0 - -// USART0 RX on PB01 -#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortB -#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 - -// USART0 CLK on PB02 -#define SL_MX25_FLASH_SHUTDOWN_CLK_PORT gpioPortB -#define SL_MX25_FLASH_SHUTDOWN_CLK_PIN 2 - -// [USART_SL_MX25_FLASH_SHUTDOWN] - -// SL_MX25_FLASH_SHUTDOWN_CS - -// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] -#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortC -#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 2 - -// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4002a/sl_rail_util_pa_config.h b/hardware/board/config/brd4111a_brd4002a/sl_rail_util_pa_config.h deleted file mode 100644 index 7c14e2f342..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/sl_rail_util_pa_config.h +++ /dev/null @@ -1,81 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Power Amplifier configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_RAIL_UTIL_PA_CONFIG_H -#define SL_RAIL_UTIL_PA_CONFIG_H - -#include "rail_types.h" - -// <<< Use Configuration Wizard in Context Menu >>> - -// PA Configuration -// Initial PA Power (deci-dBm, 100 = 10.0 dBm) -// Default: 100 -#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 - -// PA Ramp Time (microseconds) -// <0-65535:1> -// Default: 2 -#define SL_RAIL_UTIL_PA_RAMP_TIME_US 2 -// Milli-volts on PA supply pin (PA_VDD) -// <0-65535:1> -// Default: 3300 -#define SL_RAIL_UTIL_PA_VOLTAGE_MV 3300 -// 2.4 GHz PA Selection -// Highest Possible -// High Power (chip-specific) -// Low Power -// Disable -// Default: RAIL_TX_POWER_MODE_2P4GIG_HIGHEST -#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HIGHEST -// Sub-1 GHz PA Selection -// Disable -// Default: RAIL_TX_POWER_MODE_NONE -#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE -// - -// PA Curve Configuration -// Header file containing custom PA curves -// Default: "pa_curves_efr32.h" -#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" -// Header file containing PA curve types -// Default: "pa_curve_types_efr32.h" -#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" -// - -// PA Calibration Configuration -// Apply PA Calibration Factory Offset -// Default: 1 -#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 -// - -// <<< end of configuration section >>> - -#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4002a/sl_rail_util_pti_config.h b/hardware/board/config/brd4111a_brd4002a/sl_rail_util_pti_config.h deleted file mode 100644 index ce4bb0db27..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/sl_rail_util_pti_config.h +++ /dev/null @@ -1,73 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Packet Trace Information configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_RAIL_UTIL_PTI_CONFIG_H -#define SL_RAIL_UTIL_PTI_CONFIG_H - -#include "rail_types.h" - -// <<< Use Configuration Wizard in Context Menu >>> -// PTI Configuration - -// PTI mode -// UART -// UART onewire -// SPI -// Disabled -// Default: RAIL_PTI_MODE_UART -#define SL_RAIL_UTIL_PTI_MODE RAIL_PTI_MODE_UART - -// PTI Baud Rate (Hertz) -// <147800-20000000:1> -// Default: 1600000 -#define SL_RAIL_UTIL_PTI_BAUD_RATE_HZ 1600000 - -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_RAIL_UTIL_PTI -// $[PTI_SL_RAIL_UTIL_PTI] -#define SL_RAIL_UTIL_PTI_PERIPHERAL PTI - -// PTI DOUT on PC00 -#define SL_RAIL_UTIL_PTI_DOUT_PORT gpioPortC -#define SL_RAIL_UTIL_PTI_DOUT_PIN 0 - -// PTI DFRAME on PC01 -#define SL_RAIL_UTIL_PTI_DFRAME_PORT gpioPortC -#define SL_RAIL_UTIL_PTI_DFRAME_PIN 1 - - -// [PTI_SL_RAIL_UTIL_PTI]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_RAIL_UTIL_PTI_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4002a/sl_simple_button_btn0_config.h b/hardware/board/config/brd4111a_brd4002a/sl_simple_button_btn0_config.h deleted file mode 100644 index aab8db6f10..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/sl_simple_button_btn0_config.h +++ /dev/null @@ -1,45 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple Button Driver User Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_BUTTON_BTN0_CONFIG_H -#define SL_SIMPLE_BUTTON_BTN0_CONFIG_H - -#include "em_gpio.h" -#include "sl_simple_button.h" - -// <<< Use Configuration Wizard in Context Menu >>> - -// -// Interrupt -// Poll and Debounce -// Poll -// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT -#define SL_SIMPLE_BUTTON_BTN0_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_BUTTON_BTN0 -// $[GPIO_SL_SIMPLE_BUTTON_BTN0] -#define SL_SIMPLE_BUTTON_BTN0_PORT gpioPortC -#define SL_SIMPLE_BUTTON_BTN0_PIN 5 - -// [GPIO_SL_SIMPLE_BUTTON_BTN0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_BUTTON_BTN0_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4002a/sl_simple_button_btn1_config.h b/hardware/board/config/brd4111a_brd4002a/sl_simple_button_btn1_config.h deleted file mode 100644 index 2a9fde7738..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/sl_simple_button_btn1_config.h +++ /dev/null @@ -1,45 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple Button Driver User Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_BUTTON_BTN1_CONFIG_H -#define SL_SIMPLE_BUTTON_BTN1_CONFIG_H - -#include "em_gpio.h" -#include "sl_simple_button.h" - -// <<< Use Configuration Wizard in Context Menu >>> - -// -// Interrupt -// Poll and Debounce -// Poll -// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT -#define SL_SIMPLE_BUTTON_BTN1_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_BUTTON_BTN1 -// $[GPIO_SL_SIMPLE_BUTTON_BTN1] -#define SL_SIMPLE_BUTTON_BTN1_PORT gpioPortC -#define SL_SIMPLE_BUTTON_BTN1_PIN 4 - -// [GPIO_SL_SIMPLE_BUTTON_BTN1]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_BUTTON_BTN1_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4111a_brd4002a/sl_uartdrv_eusart_exp_config.h deleted file mode 100644 index a89e4ccc3e..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ /dev/null @@ -1,100 +0,0 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV_EUSART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_UARTDRV_EUSART_EXP_CONFIG_H -#define SL_UARTDRV_EUSART_EXP_CONFIG_H - -#include "em_eusart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// EUSART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_EUSART_EXP_BAUDRATE 115200 - -// Low frequency mode -// True -// False -#define SL_UARTDRV_EUSART_EXP_LF_MODE false - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: eusartNoParity -#define SL_UARTDRV_EUSART_EXP_PARITY eusartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: eusartStopbits1 -#define SL_UARTDRV_EUSART_EXP_STOP_BITS eusartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHw -#define SL_UARTDRV_EUSART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Oversampling disabled -// Default: eusartOVS16 -#define SL_UARTDRV_EUSART_EXP_OVERSAMPLING eusartOVS16 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// False -// True -// Default: eusartMajorityVoteEnable -#define SL_UARTDRV_EUSART_EXP_MVDIS eusartMajorityVoteEnable - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_EUSART_EXP_RX_BUFFER_SIZE 6 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_EUSART_EXP_TX_BUFFER_SIZE 6 -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_EUSART_EXP -// $[EUSART_SL_UARTDRV_EUSART_EXP] -#define SL_UARTDRV_EUSART_EXP_PERIPHERAL EUSART0 -#define SL_UARTDRV_EUSART_EXP_PERIPHERAL_NO 0 - -// EUSART0 TX on PA05 -#define SL_UARTDRV_EUSART_EXP_TX_PORT gpioPortA -#define SL_UARTDRV_EUSART_EXP_TX_PIN 5 - -// EUSART0 RX on PA06 -#define SL_UARTDRV_EUSART_EXP_RX_PORT gpioPortA -#define SL_UARTDRV_EUSART_EXP_RX_PIN 6 - - - -// [EUSART_SL_UARTDRV_EUSART_EXP]$ -// <<< sl:end pin_tool >>> -#endif // SL_UARTDRV_EUSART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4002a/sl_uartdrv_eusart_vcom_config.h b/hardware/board/config/brd4111a_brd4002a/sl_uartdrv_eusart_vcom_config.h deleted file mode 100644 index a37bc4e70b..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/sl_uartdrv_eusart_vcom_config.h +++ /dev/null @@ -1,106 +0,0 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV_EUSART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_UARTDRV_EUSART_VCOM_CONFIG_H -#define SL_UARTDRV_EUSART_VCOM_CONFIG_H - -#include "em_eusart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// EUSART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_EUSART_VCOM_BAUDRATE 115200 - -// Low frequency mode -// True -// False -#define SL_UARTDRV_EUSART_VCOM_LF_MODE false - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: eusartNoParity -#define SL_UARTDRV_EUSART_VCOM_PARITY eusartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: eusartStopbits1 -#define SL_UARTDRV_EUSART_VCOM_STOP_BITS eusartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHw -#define SL_UARTDRV_EUSART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Oversampling disabled -// Default: eusartOVS16 -#define SL_UARTDRV_EUSART_VCOM_OVERSAMPLING eusartOVS16 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// False -// True -// Default: eusartMajorityVoteEnable -#define SL_UARTDRV_EUSART_VCOM_MVDIS eusartMajorityVoteEnable - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_EUSART_VCOM_RX_BUFFER_SIZE 6 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_EUSART_VCOM_TX_BUFFER_SIZE 6 -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_EUSART_VCOM -// $[EUSART_SL_UARTDRV_EUSART_VCOM] -#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL EUSART0 -#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL_NO 0 - -// EUSART0 TX on PA05 -#define SL_UARTDRV_EUSART_VCOM_TX_PORT gpioPortA -#define SL_UARTDRV_EUSART_VCOM_TX_PIN 5 - -// EUSART0 RX on PA06 -#define SL_UARTDRV_EUSART_VCOM_RX_PORT gpioPortA -#define SL_UARTDRV_EUSART_VCOM_RX_PIN 6 - -// EUSART0 CTS on PA04 -#define SL_UARTDRV_EUSART_VCOM_CTS_PORT gpioPortA -#define SL_UARTDRV_EUSART_VCOM_CTS_PIN 4 - -// EUSART0 RTS on PA00 -#define SL_UARTDRV_EUSART_VCOM_RTS_PORT gpioPortA -#define SL_UARTDRV_EUSART_VCOM_RTS_PIN 0 - -// [EUSART_SL_UARTDRV_EUSART_VCOM]$ -// <<< sl:end pin_tool >>> -#endif // SL_UARTDRV_EUSART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4111a_brd4002a/sl_uartdrv_usart_exp_config.h deleted file mode 100644 index 02662139f3..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/sl_uartdrv_usart_exp_config.h +++ /dev/null @@ -1,95 +0,0 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV_USART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_UARTDRV_USART_EXP_CONFIG_H -#define SL_UARTDRV_USART_EXP_CONFIG_H - -#include "em_usart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// UART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_USART_EXP_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_UARTDRV_USART_EXP_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_UARTDRV_USART_EXP_STOP_BITS usartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHw -#define SL_UARTDRV_USART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Default: usartOVS16 -#define SL_UARTDRV_USART_EXP_OVERSAMPLING usartOVS4 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// True -// False -#define SL_UARTDRV_USART_EXP_MVDIS false - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_USART_EXP_RX_BUFFER_SIZE 6 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_USART_EXP_TX_BUFFER_SIZE 6 - -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_USART_EXP -// $[USART_SL_UARTDRV_USART_EXP] -#define SL_UARTDRV_USART_EXP_PERIPHERAL USART0 -#define SL_UARTDRV_USART_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_UARTDRV_USART_EXP_TX_PORT gpioPortA -#define SL_UARTDRV_USART_EXP_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_UARTDRV_USART_EXP_RX_PORT gpioPortA -#define SL_UARTDRV_USART_EXP_RX_PIN 6 - - - -// [USART_SL_UARTDRV_USART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif // SL_UARTDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4002a/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd4111a_brd4002a/sl_uartdrv_usart_vcom_config.h deleted file mode 100644 index e0cc8cbeac..0000000000 --- a/hardware/board/config/brd4111a_brd4002a/sl_uartdrv_usart_vcom_config.h +++ /dev/null @@ -1,101 +0,0 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV_USART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H -#define SL_UARTDRV_USART_VCOM_CONFIG_H - -#include "em_usart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// UART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHw -#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Default: usartOVS16 -#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// True -// False -#define SL_UARTDRV_USART_VCOM_MVDIS false - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 6 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 6 - -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_USART_VCOM -// $[USART_SL_UARTDRV_USART_VCOM] -#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART0 -#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA05 -#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortA -#define SL_UARTDRV_USART_VCOM_TX_PIN 5 - -// USART0 RX on PA06 -#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortA -#define SL_UARTDRV_USART_VCOM_RX_PIN 6 - -// USART0 CTS on PA04 -#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA -#define SL_UARTDRV_USART_VCOM_CTS_PIN 4 - -// USART0 RTS on PA00 -#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA -#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 - -// [USART_SL_UARTDRV_USART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4001a/btl_euart_driver_cfg.h b/hardware/board/config/brd4113a_brd4001a/btl_euart_driver_cfg.h deleted file mode 100644 index bfe614d22d..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/btl_euart_driver_cfg.h +++ /dev/null @@ -1,82 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader euart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_EUART_DRIVER_CONFIG_H -#define BTL_EUART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// EUART settings - -// Baud rate -// Default: 115200 -#define SL_SERIAL_EUART_BAUD_RATE 115200 - -// Hardware flow control -// Default: 0 -#define SL_SERIAL_EUART_FLOW_CONTROL 0 -// - -// Receive buffer size -// <0-2048:1> -// Default: 512 [0-2048] -#define SL_DRIVER_EUART_RX_BUFFER_SIZE 512 - -// Transmit buffer size -// <0-2048:1> -// Default: 128 [0-2048] -#define SL_DRIVER_EUART_TX_BUFFER_SIZE 128 - -// Virtual COM Port -// Default: 0 -#define SL_VCOM_ENABLE 0 -// - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_SERIAL_EUART -// $[EUSART_SL_SERIAL_EUART] -#define SL_SERIAL_EUART_PERIPHERAL EUSART0 -#define SL_SERIAL_EUART_PERIPHERAL_NO 0 - -// EUSART0 TX on PA00 -#define SL_SERIAL_EUART_TX_PORT gpioPortA -#define SL_SERIAL_EUART_TX_PIN 0 - -// EUSART0 RX on PA04 -#define SL_SERIAL_EUART_RX_PORT gpioPortA -#define SL_SERIAL_EUART_RX_PIN 4 - - - -// [EUSART_SL_SERIAL_EUART]$ - - -// SL_VCOM_ENABLE - -// $[GPIO_SL_VCOM_ENABLE] -#define SL_VCOM_ENABLE_PORT gpioPortC -#define SL_VCOM_ENABLE_PIN 3 - -// [GPIO_SL_VCOM_ENABLE]$ - - -// <<< sl:end pin_tool >>> - -#endif // BTL_EUART_DRIVER_CONFIG_H \ No newline at end of file diff --git a/hardware/board/config/brd4113a_brd4001a/btl_ezsp_gpio_activation_cfg.h b/hardware/board/config/brd4113a_brd4001a/btl_ezsp_gpio_activation_cfg.h deleted file mode 100644 index 620a881b5e..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/btl_ezsp_gpio_activation_cfg.h +++ /dev/null @@ -1,52 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader EZSP GPIO Activation - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_EZSP_GPIO_ACTIVATION_CONFIG_H -#define BTL_EZSP_GPIO_ACTIVATION_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Properties of SPI NCP - -// Active state -// Low -// High -// Default: LOW -// Enter firmware upgrade mode if GPIO pin has this state -#define SL_EZSP_GPIO_ACTIVATION_POLARITY LOW - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_EZSPSPI_HOST_INT -// $[GPIO_SL_EZSPSPI_HOST_INT] -#define SL_EZSPSPI_HOST_INT_PORT gpioPortC -#define SL_EZSPSPI_HOST_INT_PIN 5 - -// [GPIO_SL_EZSPSPI_HOST_INT]$ - -// SL_EZSPSPI_WAKE_INT -// $[GPIO_SL_EZSPSPI_WAKE_INT] -#define SL_EZSPSPI_WAKE_INT_PORT gpioPortC -#define SL_EZSPSPI_WAKE_INT_PIN 4 - -// [GPIO_SL_EZSPSPI_WAKE_INT]$ - -// <<< sl:end pin_tool >>> - -#endif // BTL_EZSP_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4001a/btl_gpio_activation_cfg.h b/hardware/board/config/brd4113a_brd4001a/btl_gpio_activation_cfg.h deleted file mode 100644 index 51573b25df..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/btl_gpio_activation_cfg.h +++ /dev/null @@ -1,49 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader GPIO Activation - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_GPIO_ACTIVATION_CONFIG_H -#define BTL_GPIO_ACTIVATION_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Properties of Bootloader Entry - - -// Active state -// Low -// High -// Default: LOW -// Enter firmware upgrade mode if GPIO pin has this state -#define SL_GPIO_ACTIVATION_POLARITY LOW - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_BTL_BUTTON - -// $[GPIO_SL_BTL_BUTTON] -#define SL_BTL_BUTTON_PORT gpioPortC -#define SL_BTL_BUTTON_PIN 5 - -// [GPIO_SL_BTL_BUTTON]$ - -// <<< sl:end pin_tool >>> - - -#endif // BTL_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4001a/btl_spi_controller_eusart_driver_cfg.h b/hardware/board/config/brd4113a_brd4001a/btl_spi_controller_eusart_driver_cfg.h deleted file mode 100644 index 308060ef81..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/btl_spi_controller_eusart_driver_cfg.h +++ /dev/null @@ -1,68 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader Spi Controller Eusart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H -#define BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// SPI Controller EUSART Driver - -// Frequency -// Default: 6400000 -#define SL_EUSART_EXTFLASH_FREQUENCY 6400000 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_EUSART_EXTFLASH -// $[EUSART_SL_EUSART_EXTFLASH] -#define SL_EUSART_EXTFLASH_PERIPHERAL EUSART0 -#define SL_EUSART_EXTFLASH_PERIPHERAL_NO 0 - -// EUSART0 TX on PB00 -#define SL_EUSART_EXTFLASH_TX_PORT gpioPortB -#define SL_EUSART_EXTFLASH_TX_PIN 0 - -// EUSART0 RX on PB01 -#define SL_EUSART_EXTFLASH_RX_PORT gpioPortB -#define SL_EUSART_EXTFLASH_RX_PIN 1 - -// EUSART0 SCLK on PB02 -#define SL_EUSART_EXTFLASH_SCLK_PORT gpioPortB -#define SL_EUSART_EXTFLASH_SCLK_PIN 2 - -// EUSART0 CS on PC02 -#define SL_EUSART_EXTFLASH_CS_PORT gpioPortC -#define SL_EUSART_EXTFLASH_CS_PIN 2 - -// [EUSART_SL_EUSART_EXTFLASH]$ - -// SL_EXTFLASH_WP -// $[GPIO_SL_EXTFLASH_WP] - -// [GPIO_SL_EXTFLASH_WP]$ - -// SL_EXTFLASH_HOLD -// $[GPIO_SL_EXTFLASH_HOLD] - -// [GPIO_SL_EXTFLASH_HOLD]$ - -// <<< sl:end pin_tool >>> - -#endif // BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4001a/btl_spi_controller_usart_driver_cfg.h b/hardware/board/config/brd4113a_brd4001a/btl_spi_controller_usart_driver_cfg.h deleted file mode 100644 index 6ac5f54418..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/btl_spi_controller_usart_driver_cfg.h +++ /dev/null @@ -1,68 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader Spi Controller Usart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H -#define BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// SPI Controller USART Driver - -// Frequency -// Default: 6400000 -#define SL_USART_EXTFLASH_FREQUENCY 6400000 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_USART_EXTFLASH -// $[USART_SL_USART_EXTFLASH] -#define SL_USART_EXTFLASH_PERIPHERAL USART0 -#define SL_USART_EXTFLASH_PERIPHERAL_NO 0 - -// USART0 TX on PB00 -#define SL_USART_EXTFLASH_TX_PORT gpioPortB -#define SL_USART_EXTFLASH_TX_PIN 0 - -// USART0 RX on PB01 -#define SL_USART_EXTFLASH_RX_PORT gpioPortB -#define SL_USART_EXTFLASH_RX_PIN 1 - -// USART0 CLK on PB02 -#define SL_USART_EXTFLASH_CLK_PORT gpioPortB -#define SL_USART_EXTFLASH_CLK_PIN 2 - -// USART0 CS on PC02 -#define SL_USART_EXTFLASH_CS_PORT gpioPortC -#define SL_USART_EXTFLASH_CS_PIN 2 - -// [USART_SL_USART_EXTFLASH]$ - -// SL_EXTFLASH_WP -// $[GPIO_SL_EXTFLASH_WP] - -// [GPIO_SL_EXTFLASH_WP]$ - -// SL_EXTFLASH_HOLD -// $[GPIO_SL_EXTFLASH_HOLD] - -// [GPIO_SL_EXTFLASH_HOLD]$ - -// <<< sl:end pin_tool >>> - -#endif // BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4001a/btl_uart_driver_cfg.h b/hardware/board/config/brd4113a_brd4001a/btl_uart_driver_cfg.h deleted file mode 100644 index db68887cd0..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/btl_uart_driver_cfg.h +++ /dev/null @@ -1,83 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader Uart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_UART_DRIVER_CONFIG_H -#define BTL_UART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// USART settings - -// Baud rate -// Default: 115200 -#define SL_SERIAL_UART_BAUD_RATE 115200 - -// Hardware flow control -// Default: 0 -#define SL_SERIAL_UART_FLOW_CONTROL 0 -// - -// Receive buffer size -// <0-2048:1> -// Default: 512 [0-2048] -#define SL_DRIVER_UART_RX_BUFFER_SIZE 512 - -// Transmit buffer size -// <0-2048:1> -// Default: 128 [0-2048] -#define SL_DRIVER_UART_TX_BUFFER_SIZE 128 - -// Virtual COM Port -// Default: 0 -#define SL_VCOM_ENABLE 0 -// - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_SERIAL_UART -// $[USART_SL_SERIAL_UART] -#define SL_SERIAL_UART_PERIPHERAL USART0 -#define SL_SERIAL_UART_PERIPHERAL_NO 0 - -// USART0 TX on PA00 -#define SL_SERIAL_UART_TX_PORT gpioPortA -#define SL_SERIAL_UART_TX_PIN 0 - -// USART0 RX on PA04 -#define SL_SERIAL_UART_RX_PORT gpioPortA -#define SL_SERIAL_UART_RX_PIN 4 - - - -// [USART_SL_SERIAL_UART]$ - - - -// SL_VCOM_ENABLE - -// $[GPIO_SL_VCOM_ENABLE] -#define SL_VCOM_ENABLE_PORT gpioPortC -#define SL_VCOM_ENABLE_PIN 3 - -// [GPIO_SL_VCOM_ENABLE]$ - - -// <<< sl:end pin_tool >>> - -#endif // BTL_UART_DRIVER_CONFIG_H \ No newline at end of file diff --git a/hardware/board/config/brd4113a_brd4001a/iot_flash_cfg_spiflash.h b/hardware/board/config/brd4113a_brd4001a/iot_flash_cfg_spiflash.h deleted file mode 100644 index 3b634d9b08..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/iot_flash_cfg_spiflash.h +++ /dev/null @@ -1,136 +0,0 @@ -/***************************************************************************//** - * @file iot_flash_cfg_inst.h - * @brief Common I/O flash instance configurations. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_FLASH_CFG_SPIFLASH_H_ -#define _IOT_FLASH_CFG_SPIFLASH_H_ - -/******************************************************************************* - * Flash Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// Flash General Options - -// Instance number -// Instance number used when iot_flash_open() is called. -// Default: 0 -#define IOT_FLASH_CFG_SPIFLASH_INST_NUM 0 - -// Instance type -// <0=> Internal Flash (MSC) -// <1=> External Flash (SPI) -// Specify whether this instance is for internal flash (MSC) -// or an external SPI flash. If external, then you need to setup -// SPI configs below. -// Default: 0 -#define IOT_FLASH_CFG_SPIFLASH_INST_TYPE 1 - -// - -// SPI Configuration - -// Default SPI bitrate -// Default: 1000000 -#define IOT_FLASH_CFG_SPIFLASH_SPI_BITRATE 1000000 - -// Default SPI frame length <4-16> -// Default: 8 -#define IOT_FLASH_CFG_SPIFLASH_SPI_FRAME_LENGTH 8 - -// Default SPI master/slave mode -// Master -// Slave -#define IOT_FLASH_CFG_SPIFLASH_SPI_TYPE spidrvMaster - -// Default SPI bit order -// LSB transmitted first -// MSB transmitted first -#define IOT_FLASH_CFG_SPIFLASH_SPI_BIT_ORDER spidrvBitOrderMsbFirst - -// Default SPI clock mode -// SPI mode 0: CLKPOL=0, CLKPHA=0 -// SPI mode 1: CLKPOL=0, CLKPHA=1 -// SPI mode 2: CLKPOL=1, CLKPHA=0 -// SPI mode 3: CLKPOL=1, CLKPHA=1 -#define IOT_FLASH_CFG_SPIFLASH_SPI_CLOCK_MODE spidrvClockMode0 - -// Default SPI CS control scheme -// CS controlled by the SPI driver -// CS controlled by the application -#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_CONTROL spidrvCsControlApplication - -// Default SPI transfer scheme -// Transfer starts immediately -// Transfer starts when the bus is idle -#define IOT_FLASH_CFG_SPIFLASH_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * EXTERNAL FLASH: H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_FLASH_CFG_SPIFLASH_SPI -// $[USART_IOT_FLASH_CFG_SPIFLASH_SPI] -#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL USART0 -#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL_NO 0 - -// USART0 TX on PB00 -#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PORT gpioPortB -#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PIN 0 - -// USART0 RX on PB01 -#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PORT gpioPortB -#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PIN 1 - -// USART0 CLK on PB02 -#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PORT gpioPortB -#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PIN 2 - -// USART0 CS on PC02 -#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PORT gpioPortC -#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PIN 2 - -// [USART_IOT_FLASH_CFG_SPIFLASH_SPI]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_FLASH_CFG_SPIFLASH_H_ */ diff --git a/hardware/board/config/brd4113a_brd4001a/iot_pwm_cfg_exp.h b/hardware/board/config/brd4113a_brd4001a/iot_pwm_cfg_exp.h deleted file mode 100644 index 306f255589..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/iot_pwm_cfg_exp.h +++ /dev/null @@ -1,78 +0,0 @@ -/***************************************************************************//** - * @file iot_pwm_cfg_inst.h - * @brief Common I/O PWM instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_PWM_CFG_EXP_H_ -#define _IOT_PWM_CFG_EXP_H_ - -/******************************************************************************* - * PWM Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// PWM General Options - -// Instance number -// Instance number used when iot_pwm_open() is called. -// Default: 0 -#define IOT_PWM_CFG_EXP_INST_NUM 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_PWM_CFG_EXP -// $[TIMER_IOT_PWM_CFG_EXP] -#define IOT_PWM_CFG_EXP_PERIPHERAL TIMER3 -#define IOT_PWM_CFG_EXP_PERIPHERAL_NO 3 - -// TIMER3 CC0 on PC05 -#define IOT_PWM_CFG_EXP_CC0_PORT gpioPortC -#define IOT_PWM_CFG_EXP_CC0_PIN 5 - - - -// [TIMER_IOT_PWM_CFG_EXP]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_PWM_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4113a_brd4001a/iot_pwm_cfg_led0.h b/hardware/board/config/brd4113a_brd4001a/iot_pwm_cfg_led0.h deleted file mode 100644 index 8281baf8c7..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/iot_pwm_cfg_led0.h +++ /dev/null @@ -1,78 +0,0 @@ -/***************************************************************************//** - * @file iot_pwm_cfg_inst.h - * @brief Common I/O PWM instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_PWM_CFG_LED0_H_ -#define _IOT_PWM_CFG_LED0_H_ - -/******************************************************************************* - * PWM Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// PWM General Options - -// Instance number -// Instance number used when iot_pwm_open() is called. -// Default: 0 -#define IOT_PWM_CFG_LED0_INST_NUM 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_PWM_CFG_LED0 -// $[TIMER_IOT_PWM_CFG_LED0] -#define IOT_PWM_CFG_LED0_PERIPHERAL TIMER0 -#define IOT_PWM_CFG_LED0_PERIPHERAL_NO 0 - -// TIMER0 CC0 on PC05 -#define IOT_PWM_CFG_LED0_CC0_PORT gpioPortC -#define IOT_PWM_CFG_LED0_CC0_PIN 5 - - - -// [TIMER_IOT_PWM_CFG_LED0]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_PWM_CFG_LED0_H_ */ diff --git a/hardware/board/config/brd4113a_brd4001a/iot_pwm_cfg_led1.h b/hardware/board/config/brd4113a_brd4001a/iot_pwm_cfg_led1.h deleted file mode 100644 index 5437b9bda9..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/iot_pwm_cfg_led1.h +++ /dev/null @@ -1,78 +0,0 @@ -/***************************************************************************//** - * @file iot_pwm_cfg_inst.h - * @brief Common I/O PWM instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_PWM_CFG_LED1_H_ -#define _IOT_PWM_CFG_LED1_H_ - -/******************************************************************************* - * PWM Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// PWM General Options - -// Instance number -// Instance number used when iot_pwm_open() is called. -// Default: 0 -#define IOT_PWM_CFG_LED1_INST_NUM 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_PWM_CFG_LED1 -// $[TIMER_IOT_PWM_CFG_LED1] -#define IOT_PWM_CFG_LED1_PERIPHERAL TIMER1 -#define IOT_PWM_CFG_LED1_PERIPHERAL_NO 1 - -// TIMER1 CC0 on PC04 -#define IOT_PWM_CFG_LED1_CC0_PORT gpioPortC -#define IOT_PWM_CFG_LED1_CC0_PIN 4 - - - -// [TIMER_IOT_PWM_CFG_LED1]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_PWM_CFG_LED1_H_ */ diff --git a/hardware/board/config/brd4113a_brd4001a/iot_uart_cfg_exp.h b/hardware/board/config/brd4113a_brd4001a/iot_uart_cfg_exp.h deleted file mode 100644 index abe3e154ae..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/iot_uart_cfg_exp.h +++ /dev/null @@ -1,126 +0,0 @@ -/***************************************************************************//** - * @file iot_uart_cfg_inst.h - * @brief Common I/O UART instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_UART_CFG_EXP_H_ -#define _IOT_UART_CFG_EXP_H_ - -/******************************************************************************* - * UART Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// UART General Options - -// Instance number -// Instance number used when iot_uart_open() is called. -// Default: 0 -#define IOT_UART_CFG_EXP_INST_NUM 0 - -// Default baud rate -// Default: 115200 -#define IOT_UART_CFG_EXP_DEFAULT_BAUDRATE 115200 - -// Default number of data bits -// 4 data bits -// 5 data bits -// 6 data bits -// 7 data bits -// 8 data bits -// Default: usartDatabits8 -#define IOT_UART_CFG_EXP_DEFAULT_DATA_BITS usartDatabits8 - -// Default parity mode -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define IOT_UART_CFG_EXP_DEFAULT_PARITY usartNoParity - -// Default number of stop bits -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define IOT_UART_CFG_EXP_DEFAULT_STOP_BITS usartStopbits1 - -// Default hardware flow control -// None -// CTS -// RTS -// CTS/RTS -// Default: usartHwFlowControlNone -#define IOT_UART_CFG_EXP_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone - - -// Internal Loopback -// Enable USART Internal loopback -// Default: 0 -#define IOT_UART_CFG_EXP_LOOPBACK 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_UART_CFG_EXP -// $[USART_IOT_UART_CFG_EXP] -#define IOT_UART_CFG_EXP_PERIPHERAL USART0 -#define IOT_UART_CFG_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PA00 -#define IOT_UART_CFG_EXP_TX_PORT gpioPortA -#define IOT_UART_CFG_EXP_TX_PIN 0 - -// USART0 RX on PA04 -#define IOT_UART_CFG_EXP_RX_PORT gpioPortA -#define IOT_UART_CFG_EXP_RX_PIN 4 - - - - - -// [USART_IOT_UART_CFG_EXP]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_UART_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4113a_brd4001a/iot_uart_cfg_loopback.h b/hardware/board/config/brd4113a_brd4001a/iot_uart_cfg_loopback.h deleted file mode 100644 index 5de3406c56..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/iot_uart_cfg_loopback.h +++ /dev/null @@ -1,126 +0,0 @@ -/***************************************************************************//** - * @file iot_uart_cfg_inst.h - * @brief Common I/O UART instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_UART_CFG_LOOPBACK_H_ -#define _IOT_UART_CFG_LOOPBACK_H_ - -/******************************************************************************* - * UART Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// UART General Options - -// Instance number -// Instance number used when iot_uart_open() is called. -// Default: 0 -#define IOT_UART_CFG_LOOPBACK_INST_NUM 0 - -// Default baud rate -// Default: 115200 -#define IOT_UART_CFG_LOOPBACK_DEFAULT_BAUDRATE 115200 - -// Default number of data bits -// 4 data bits -// 5 data bits -// 6 data bits -// 7 data bits -// 8 data bits -// Default: usartDatabits8 -#define IOT_UART_CFG_LOOPBACK_DEFAULT_DATA_BITS usartDatabits8 - -// Default parity mode -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define IOT_UART_CFG_LOOPBACK_DEFAULT_PARITY usartNoParity - -// Default number of stop bits -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define IOT_UART_CFG_LOOPBACK_DEFAULT_STOP_BITS usartStopbits1 - -// Default hardware flow control -// None -// CTS -// RTS -// CTS/RTS -// Default: usartHwFlowControlNone -#define IOT_UART_CFG_LOOPBACK_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone - - -// Internal Loopback -// Enable USART Internal loopback -// Default: 0 -#define IOT_UART_CFG_LOOPBACK_LOOPBACK 1 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_UART_CFG_LOOPBACK -// $[USART_IOT_UART_CFG_LOOPBACK] -#define IOT_UART_CFG_LOOPBACK_PERIPHERAL USART0 -#define IOT_UART_CFG_LOOPBACK_PERIPHERAL_NO 0 - -// USART0 TX on PA00 -#define IOT_UART_CFG_LOOPBACK_TX_PORT gpioPortA -#define IOT_UART_CFG_LOOPBACK_TX_PIN 0 - -// USART0 RX on PA04 -#define IOT_UART_CFG_LOOPBACK_RX_PORT gpioPortA -#define IOT_UART_CFG_LOOPBACK_RX_PIN 4 - - - - - -// [USART_IOT_UART_CFG_LOOPBACK]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_UART_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4113a_brd4001a/iot_uart_cfg_vcom.h b/hardware/board/config/brd4113a_brd4001a/iot_uart_cfg_vcom.h deleted file mode 100644 index ad8c064b91..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/iot_uart_cfg_vcom.h +++ /dev/null @@ -1,126 +0,0 @@ -/***************************************************************************//** - * @file iot_uart_cfg_inst.h - * @brief Common I/O UART instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_UART_CFG_VCOM_H_ -#define _IOT_UART_CFG_VCOM_H_ - -/******************************************************************************* - * UART Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// UART General Options - -// Instance number -// Instance number used when iot_uart_open() is called. -// Default: 0 -#define IOT_UART_CFG_VCOM_INST_NUM 0 - -// Default baud rate -// Default: 115200 -#define IOT_UART_CFG_VCOM_DEFAULT_BAUDRATE 115200 - -// Default number of data bits -// 4 data bits -// 5 data bits -// 6 data bits -// 7 data bits -// 8 data bits -// Default: usartDatabits8 -#define IOT_UART_CFG_VCOM_DEFAULT_DATA_BITS usartDatabits8 - -// Default parity mode -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define IOT_UART_CFG_VCOM_DEFAULT_PARITY usartNoParity - -// Default number of stop bits -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define IOT_UART_CFG_VCOM_DEFAULT_STOP_BITS usartStopbits1 - -// Default hardware flow control -// None -// CTS -// RTS -// CTS/RTS -// Default: usartHwFlowControlNone -#define IOT_UART_CFG_VCOM_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone - - -// Internal Loopback -// Enable USART Internal loopback -// Default: 0 -#define IOT_UART_CFG_VCOM_LOOPBACK 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_UART_CFG_VCOM -// $[USART_IOT_UART_CFG_VCOM] -#define IOT_UART_CFG_VCOM_PERIPHERAL USART0 -#define IOT_UART_CFG_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA00 -#define IOT_UART_CFG_VCOM_TX_PORT gpioPortA -#define IOT_UART_CFG_VCOM_TX_PIN 0 - -// USART0 RX on PA04 -#define IOT_UART_CFG_VCOM_RX_PORT gpioPortA -#define IOT_UART_CFG_VCOM_RX_PIN 4 - - - - - -// [USART_IOT_UART_CFG_VCOM]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_UART_CFG_VCOM_H_ */ diff --git a/hardware/board/config/brd4113a_brd4001a/sl_board_control_config.h b/hardware/board/config/brd4113a_brd4001a/sl_board_control_config.h deleted file mode 100644 index 7959f2d516..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_board_control_config.h +++ /dev/null @@ -1,56 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Board Control - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_BOARD_CONTROL_CONFIG_H -#define SL_BOARD_CONTROL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Enable Virtual COM UART -// Default: 0 -#define SL_BOARD_ENABLE_VCOM 0 - -// Disable SPI Flash -// Default: 1 -#define SL_BOARD_DISABLE_MEMORY_SPI 1 - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_BOARD_ENABLE_VCOM -// $[GPIO_SL_BOARD_ENABLE_VCOM] -#define SL_BOARD_ENABLE_VCOM_PORT gpioPortC -#define SL_BOARD_ENABLE_VCOM_PIN 3 -// [GPIO_SL_BOARD_ENABLE_VCOM]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4001a/sl_cpc_drv_primary_uart_usart_exp_config.h b/hardware/board/config/brd4113a_brd4001a/sl_cpc_drv_primary_uart_usart_exp_config.h deleted file mode 100644 index f6ba810055..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_cpc_drv_primary_uart_usart_exp_config.h +++ /dev/null @@ -1,70 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC UART PRIMARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_USART_EXP_PRIMARY_CONFIG_H -#define SL_CPC_DRV_UART_USART_EXP_PRIMARY_CONFIG_H - -// CPC-Primary UART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 - -// UART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_EXP -// $[USART_SL_CPC_DRV_UART_EXP] -#define SL_CPC_DRV_UART_EXP_PERIPHERAL USART0 -#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PA00 -#define SL_CPC_DRV_UART_EXP_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_TX_PIN 0 - -// USART0 RX on PA04 -#define SL_CPC_DRV_UART_EXP_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_RX_PIN 4 - -// [USART_SL_CPC_DRV_UART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_EXP_PRIMARY_CONFIG_H */ diff --git a/hardware/board/config/brd4113a_brd4001a/sl_cpc_drv_primary_uart_usart_vcom_config.h b/hardware/board/config/brd4113a_brd4001a/sl_cpc_drv_primary_uart_usart_vcom_config.h deleted file mode 100644 index 7fd233d3f7..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_cpc_drv_primary_uart_usart_vcom_config.h +++ /dev/null @@ -1,70 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC UART PRIMARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_USART_VCOM_PRIMARY_CONFIG_H -#define SL_CPC_DRV_UART_USART_VCOM_PRIMARY_CONFIG_H - -// CPC-Primary UART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 - -// UART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_VCOM -// $[USART_SL_CPC_DRV_UART_VCOM] -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA00 -#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_TX_PIN 0 - -// USART0 RX on PA04 -#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_RX_PIN 4 - -// [USART_SL_CPC_DRV_UART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_VCOM_PRIMARY_CONFIG_H */ diff --git a/hardware/board/config/brd4113a_brd4001a/sl_cpc_drv_secondary_uart_eusart_exp_config.h b/hardware/board/config/brd4113a_brd4001a/sl_cpc_drv_secondary_uart_eusart_exp_config.h deleted file mode 100644 index 79cd709be0..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_cpc_drv_secondary_uart_eusart_exp_config.h +++ /dev/null @@ -1,78 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC EUSART SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_EUSART_EXP_SECONDARY_CONFIG_H -#define SL_CPC_DRV_UART_EUSART_EXP_SECONDARY_CONFIG_H - -// CPC - Secondary EUSART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 - -// EUSART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 - -// Flow control -// None -// CTS/RTS -// Default: eusartHwFlowControlNone -#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_EXP -// $[EUSART_SL_CPC_DRV_UART_EXP] -#define SL_CPC_DRV_UART_EXP_PERIPHERAL EUSART0 -#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 - -// EUSART0 TX on PA00 -#define SL_CPC_DRV_UART_EXP_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_TX_PIN 0 - -// EUSART0 RX on PA04 -#define SL_CPC_DRV_UART_EXP_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_RX_PIN 4 - - - -// [EUSART_SL_CPC_DRV_UART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4113a_brd4001a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h b/hardware/board/config/brd4113a_brd4001a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h deleted file mode 100644 index a745607924..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h +++ /dev/null @@ -1,78 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC EUSART SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_EUSART_VCOM_SECONDARY_CONFIG_H -#define SL_CPC_DRV_UART_EUSART_VCOM_SECONDARY_CONFIG_H - -// CPC - Secondary EUSART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 - -// EUSART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 - -// Flow control -// None -// CTS/RTS -// Default: eusartHwFlowControlNone -#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_VCOM -// $[EUSART_SL_CPC_DRV_UART_VCOM] -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL EUSART0 -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 - -// EUSART0 TX on PA00 -#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_TX_PIN 0 - -// EUSART0 RX on PA04 -#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_RX_PIN 4 - - - -// [EUSART_SL_CPC_DRV_UART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_VCOM_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4113a_brd4001a/sl_cpc_drv_secondary_uart_usart_exp_config.h b/hardware/board/config/brd4113a_brd4001a/sl_cpc_drv_secondary_uart_usart_exp_config.h deleted file mode 100644 index 5805023087..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_cpc_drv_secondary_uart_usart_exp_config.h +++ /dev/null @@ -1,78 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC UART SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_USART_EXP_SECONDARY_CONFIG_H -#define SL_CPC_DRV_UART_USART_EXP_SECONDARY_CONFIG_H - -// CPC - Secondary UART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 - -// UART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 - -// Flow control -// None -// CTS/RTS -// Default: usartHwFlowControlCtsAndRts -#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_EXP -// $[USART_SL_CPC_DRV_UART_EXP] -#define SL_CPC_DRV_UART_EXP_PERIPHERAL USART0 -#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PA00 -#define SL_CPC_DRV_UART_EXP_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_TX_PIN 0 - -// USART0 RX on PA04 -#define SL_CPC_DRV_UART_EXP_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_RX_PIN 4 - - - -// [USART_SL_CPC_DRV_UART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4113a_brd4001a/sl_cpc_drv_secondary_uart_usart_vcom_config.h b/hardware/board/config/brd4113a_brd4001a/sl_cpc_drv_secondary_uart_usart_vcom_config.h deleted file mode 100644 index 7139445bb0..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_cpc_drv_secondary_uart_usart_vcom_config.h +++ /dev/null @@ -1,78 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC UART SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_USART_VCOM_SECONDARY_CONFIG_H -#define SL_CPC_DRV_UART_USART_VCOM_SECONDARY_CONFIG_H - -// CPC - Secondary UART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 - -// UART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 - -// Flow control -// None -// CTS/RTS -// Default: usartHwFlowControlCtsAndRts -#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_VCOM -// $[USART_SL_CPC_DRV_UART_VCOM] -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA00 -#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_TX_PIN 0 - -// USART0 RX on PA04 -#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_RX_PIN 4 - - - -// [USART_SL_CPC_DRV_UART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_VCOM_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4113a_brd4001a/sl_device_init_hfxo_config.h b/hardware/board/config/brd4113a_brd4001a/sl_device_init_hfxo_config.h deleted file mode 100644 index b0938ac495..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_device_init_hfxo_config.h +++ /dev/null @@ -1,53 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_HFXO Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H -#define SL_DEVICE_INIT_HFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// External sine wave -// Default: cmuHfxoOscMode_Crystal -#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal - -// Frequency <38000000-40000000> -// Default: 38400000 -#define SL_DEVICE_INIT_HFXO_FREQ 38400000 - -// CTUNE <0-255> -// Default: 140 -#define SL_DEVICE_INIT_HFXO_CTUNE 120 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4001a/sl_device_init_lfxo_config.h b/hardware/board/config/brd4113a_brd4001a/sl_device_init_lfxo_config.h deleted file mode 100644 index 0e1f4147bf..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_device_init_lfxo_config.h +++ /dev/null @@ -1,66 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_LFXO Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H -#define SL_DEVICE_INIT_LFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// AC-coupled buffer -// External digital clock -// Default: cmuLfxoOscMode_Crystal -#define SL_DEVICE_INIT_LFXO_MODE cmuLfxoOscMode_Crystal - -// CTUNE <0-127> -// Default: 63 -#define SL_DEVICE_INIT_LFXO_CTUNE 37 - -// LFXO precision in PPM <0-65535> -// Default: 500 -#define SL_DEVICE_INIT_LFXO_PRECISION 100 - -// Startup Timeout Delay -// -// 2 cycles -// 256 cycles -// 1K cycles -// 2K cycles -// 4K cycles -// 8K cycles -// 16K cycles -// 32K cycles -// Default: cmuLfxoStartupDelay_4KCycles -#define SL_DEVICE_INIT_LFXO_TIMEOUT cmuLfxoStartupDelay_4KCycles -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4001a/sl_iostream_eusart_exp_config.h b/hardware/board/config/brd4113a_brd4001a/sl_iostream_eusart_exp_config.h deleted file mode 100644 index a73dea84df..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_iostream_eusart_exp_config.h +++ /dev/null @@ -1,107 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_EUSART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_EUSART_EXP_CONFIG_H -#define SL_IOSTREAM_EUSART_EXP_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// EUART settings - -// Enable High frequency mode -// Default: 1 -#define SL_IOSTREAM_EUSART_EXP_ENABLE_HIGH_FREQUENCY 1 - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_EUSART_EXP_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: eusartNoParity -#define SL_IOSTREAM_EUSART_EXP_PARITY eusartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: eusartStopbits1 -#define SL_IOSTREAM_EUSART_EXP_STOP_BITS eusartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: eusartHwFlowControlNone -#define SL_IOSTREAM_EUSART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlNone - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_EUSART_EXP_RX_BUFFER_SIZE 32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_EUSART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_EUSART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_EUSART_EXP -// $[EUSART_SL_IOSTREAM_EUSART_EXP] -#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL EUSART0 -#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL_NO 0 - -// EUSART0 TX on PA00 -#define SL_IOSTREAM_EUSART_EXP_TX_PORT gpioPortA -#define SL_IOSTREAM_EUSART_EXP_TX_PIN 0 - -// EUSART0 RX on PA04 -#define SL_IOSTREAM_EUSART_EXP_RX_PORT gpioPortA -#define SL_IOSTREAM_EUSART_EXP_RX_PIN 4 - - - -// [EUSART_SL_IOSTREAM_EUSART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4113a_brd4001a/sl_iostream_eusart_vcom_config.h b/hardware/board/config/brd4113a_brd4001a/sl_iostream_eusart_vcom_config.h deleted file mode 100644 index fd2d36c93f..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_iostream_eusart_vcom_config.h +++ /dev/null @@ -1,107 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_EUSART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_EUSART_VCOM_CONFIG_H -#define SL_IOSTREAM_EUSART_VCOM_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// EUART settings - -// Enable High frequency mode -// Default: 1 -#define SL_IOSTREAM_EUSART_VCOM_ENABLE_HIGH_FREQUENCY 1 - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_EUSART_VCOM_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: eusartNoParity -#define SL_IOSTREAM_EUSART_VCOM_PARITY eusartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: eusartStopbits1 -#define SL_IOSTREAM_EUSART_VCOM_STOP_BITS eusartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: eusartHwFlowControlNone -#define SL_IOSTREAM_EUSART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlNone - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_EUSART_VCOM_RX_BUFFER_SIZE 32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_EUSART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_EUSART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_EUSART_VCOM -// $[EUSART_SL_IOSTREAM_EUSART_VCOM] -#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL EUSART0 -#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL_NO 0 - -// EUSART0 TX on PA00 -#define SL_IOSTREAM_EUSART_VCOM_TX_PORT gpioPortA -#define SL_IOSTREAM_EUSART_VCOM_TX_PIN 0 - -// EUSART0 RX on PA04 -#define SL_IOSTREAM_EUSART_VCOM_RX_PORT gpioPortA -#define SL_IOSTREAM_EUSART_VCOM_RX_PIN 4 - - - -// [EUSART_SL_IOSTREAM_EUSART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4113a_brd4001a/sl_iostream_usart_exp_config.h b/hardware/board/config/brd4113a_brd4001a/sl_iostream_usart_exp_config.h deleted file mode 100644 index f46ecf2199..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_iostream_usart_exp_config.h +++ /dev/null @@ -1,103 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_USART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_USART_EXP_CONFIG_H -#define SL_IOSTREAM_USART_EXP_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// USART settings - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_USART_EXP_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_IOSTREAM_USART_EXP_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_IOSTREAM_USART_EXP_STOP_BITS usartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: usartHwFlowControlNone -#define SL_IOSTREAM_USART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlNone - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_USART_EXP_RX_BUFFER_SIZE 32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_USART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_USART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_USART_EXP -// $[USART_SL_IOSTREAM_USART_EXP] -#define SL_IOSTREAM_USART_EXP_PERIPHERAL USART0 -#define SL_IOSTREAM_USART_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PA00 -#define SL_IOSTREAM_USART_EXP_TX_PORT gpioPortA -#define SL_IOSTREAM_USART_EXP_TX_PIN 0 - -// USART0 RX on PA04 -#define SL_IOSTREAM_USART_EXP_RX_PORT gpioPortA -#define SL_IOSTREAM_USART_EXP_RX_PIN 4 - - - -// [USART_SL_IOSTREAM_USART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4113a_brd4001a/sl_iostream_usart_vcom_config.h b/hardware/board/config/brd4113a_brd4001a/sl_iostream_usart_vcom_config.h deleted file mode 100644 index 32956fefb4..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_iostream_usart_vcom_config.h +++ /dev/null @@ -1,103 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_USART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H -#define SL_IOSTREAM_USART_VCOM_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// USART settings - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_USART_VCOM_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: usartHwFlowControlNone -#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlNone - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_USART_VCOM -// $[USART_SL_IOSTREAM_USART_VCOM] -#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART0 -#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA00 -#define SL_IOSTREAM_USART_VCOM_TX_PORT gpioPortA -#define SL_IOSTREAM_USART_VCOM_TX_PIN 0 - -// USART0 RX on PA04 -#define SL_IOSTREAM_USART_VCOM_RX_PORT gpioPortA -#define SL_IOSTREAM_USART_VCOM_RX_PIN 4 - - - -// [USART_SL_IOSTREAM_USART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4113a_brd4001a/sl_mx25_flash_shutdown_eusart_config.h b/hardware/board/config/brd4113a_brd4001a/sl_mx25_flash_shutdown_eusart_config.h deleted file mode 100644 index 3d804d2bea..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_mx25_flash_shutdown_eusart_config.h +++ /dev/null @@ -1,51 +0,0 @@ -/***************************************************************************//** - * @file - * @brief SL_MX25_FLASH_SHUTDOWN_USART Config - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H -#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H - -// <<< sl:start pin_tool >>> -// {eusart signal=TX,RX,SCLK} SL_MX25_FLASH_SHUTDOWN -// [EUSART_SL_MX25_FLASH_SHUTDOWN] -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL EUSART0 -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 - -// EUSART0 TX on PB00 -#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortB -#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 0 - -// EUSART0 RX on PB01 -#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortB -#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 - -// EUSART0 SCLK on PB02 -#define SL_MX25_FLASH_SHUTDOWN_SCLK_PORT gpioPortB -#define SL_MX25_FLASH_SHUTDOWN_SCLK_PIN 2 - -// [EUSART_SL_MX25_FLASH_SHUTDOWN] - -// SL_MX25_FLASH_SHUTDOWN_CS - -// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] -#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortC -#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 2 - -// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4001a/sl_mx25_flash_shutdown_usart_config.h b/hardware/board/config/brd4113a_brd4001a/sl_mx25_flash_shutdown_usart_config.h deleted file mode 100644 index 06eb2da111..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_mx25_flash_shutdown_usart_config.h +++ /dev/null @@ -1,51 +0,0 @@ -/***************************************************************************//** - * @file - * @brief SL_MX25_FLASH_SHUTDOWN_USART Config - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H -#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H - -// <<< sl:start pin_tool >>> -// {usart signal=TX,RX,CLK} SL_MX25_FLASH_SHUTDOWN -// [USART_SL_MX25_FLASH_SHUTDOWN] -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL USART0 -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 - -// USART0 TX on PB00 -#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortB -#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 0 - -// USART0 RX on PB01 -#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortB -#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 - -// USART0 CLK on PB02 -#define SL_MX25_FLASH_SHUTDOWN_CLK_PORT gpioPortB -#define SL_MX25_FLASH_SHUTDOWN_CLK_PIN 2 - -// [USART_SL_MX25_FLASH_SHUTDOWN] - -// SL_MX25_FLASH_SHUTDOWN_CS - -// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] -#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortC -#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 2 - -// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4001a/sl_pwm_init_led0_config.h b/hardware/board/config/brd4113a_brd4001a/sl_pwm_init_led0_config.h deleted file mode 100644 index 332e1922a8..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_pwm_init_led0_config.h +++ /dev/null @@ -1,62 +0,0 @@ -/***************************************************************************//** - * @file - * @brief PWM Driver - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef PWM_INIT_LED0_CONFIG_H -#define PWM_INIT_LED0_CONFIG_H - -#ifdef __cplusplus -extern "C" { -#endif - -// <<< Use Configuration Wizard in Context Menu >>> - -// PWM configuration - -// PWM frequency [Hz] -// Default: 10000 -#define SL_PWM_LED0_FREQUENCY 10000 - -// Polarity -// Active high -// Active low -// Default: PWM_ACTIVE_HIGH -#define SL_PWM_LED0_POLARITY PWM_ACTIVE_LOW -// end pwm configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_PWM_LED0 -// $[TIMER_SL_PWM_LED0] -#define SL_PWM_LED0_PERIPHERAL TIMER0 -#define SL_PWM_LED0_PERIPHERAL_NO 0 - -#define SL_PWM_LED0_OUTPUT_CHANNEL 0 -// TIMER0 CC0 on PC05 -#define SL_PWM_LED0_OUTPUT_PORT gpioPortC -#define SL_PWM_LED0_OUTPUT_PIN 5 - -// [TIMER_SL_PWM_LED0]$ - -// <<< sl:end pin_tool >>> - -#ifdef __cplusplus -} -#endif - -#endif // PWM_INIT_LED0_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4001a/sl_pwm_init_led1_config.h b/hardware/board/config/brd4113a_brd4001a/sl_pwm_init_led1_config.h deleted file mode 100644 index 1618231e43..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_pwm_init_led1_config.h +++ /dev/null @@ -1,62 +0,0 @@ -/***************************************************************************//** - * @file - * @brief PWM Driver - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef PWM_INIT_LED1_CONFIG_H -#define PWM_INIT_LED1_CONFIG_H - -#ifdef __cplusplus -extern "C" { -#endif - -// <<< Use Configuration Wizard in Context Menu >>> - -// PWM configuration - -// PWM frequency [Hz] -// Default: 10000 -#define SL_PWM_LED1_FREQUENCY 10000 - -// Polarity -// Active high -// Active low -// Default: PWM_ACTIVE_HIGH -#define SL_PWM_LED1_POLARITY PWM_ACTIVE_LOW -// end pwm configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_PWM_LED1 -// $[TIMER_SL_PWM_LED1] -#define SL_PWM_LED1_PERIPHERAL TIMER1 -#define SL_PWM_LED1_PERIPHERAL_NO 1 - -#define SL_PWM_LED1_OUTPUT_CHANNEL 0 -// TIMER1 CC0 on PC04 -#define SL_PWM_LED1_OUTPUT_PORT gpioPortC -#define SL_PWM_LED1_OUTPUT_PIN 4 - -// [TIMER_SL_PWM_LED1]$ - -// <<< sl:end pin_tool >>> - -#ifdef __cplusplus -} -#endif - -#endif // PWM_INIT_LED1_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4001a/sl_rail_util_pa_config.h b/hardware/board/config/brd4113a_brd4001a/sl_rail_util_pa_config.h deleted file mode 100644 index a1a5fce586..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_rail_util_pa_config.h +++ /dev/null @@ -1,81 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Power Amplifier configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_RAIL_UTIL_PA_CONFIG_H -#define SL_RAIL_UTIL_PA_CONFIG_H - -#include "rail_types.h" - -// <<< Use Configuration Wizard in Context Menu >>> - -// PA Configuration -// Initial PA Power (deci-dBm, 100 = 10.0 dBm) -// Default: 100 -#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 - -// PA Ramp Time (microseconds) -// <0-65535:1> -// Default: 2 -#define SL_RAIL_UTIL_PA_RAMP_TIME_US 2 -// Milli-volts on PA supply pin (PA_VDD) -// <0-65535:1> -// Default: 3300 -#define SL_RAIL_UTIL_PA_VOLTAGE_MV 1800 -// 2.4 GHz PA Selection -// Highest Possible -// High Power (chip-specific) -// Low Power -// Disable -// Default: RAIL_TX_POWER_MODE_2P4GIG_HIGHEST -#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HIGHEST -// Sub-1 GHz PA Selection -// Disable -// Default: RAIL_TX_POWER_MODE_NONE -#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE -// - -// PA Curve Configuration -// Header file containing custom PA curves -// Default: "pa_curves_efr32.h" -#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" -// Header file containing PA curve types -// Default: "pa_curve_types_efr32.h" -#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" -// - -// PA Calibration Configuration -// Apply PA Calibration Factory Offset -// Default: 1 -#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 -// - -// <<< end of configuration section >>> - -#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4001a/sl_rail_util_pti_config.h b/hardware/board/config/brd4113a_brd4001a/sl_rail_util_pti_config.h deleted file mode 100644 index ce4bb0db27..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_rail_util_pti_config.h +++ /dev/null @@ -1,73 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Packet Trace Information configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_RAIL_UTIL_PTI_CONFIG_H -#define SL_RAIL_UTIL_PTI_CONFIG_H - -#include "rail_types.h" - -// <<< Use Configuration Wizard in Context Menu >>> -// PTI Configuration - -// PTI mode -// UART -// UART onewire -// SPI -// Disabled -// Default: RAIL_PTI_MODE_UART -#define SL_RAIL_UTIL_PTI_MODE RAIL_PTI_MODE_UART - -// PTI Baud Rate (Hertz) -// <147800-20000000:1> -// Default: 1600000 -#define SL_RAIL_UTIL_PTI_BAUD_RATE_HZ 1600000 - -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_RAIL_UTIL_PTI -// $[PTI_SL_RAIL_UTIL_PTI] -#define SL_RAIL_UTIL_PTI_PERIPHERAL PTI - -// PTI DOUT on PC00 -#define SL_RAIL_UTIL_PTI_DOUT_PORT gpioPortC -#define SL_RAIL_UTIL_PTI_DOUT_PIN 0 - -// PTI DFRAME on PC01 -#define SL_RAIL_UTIL_PTI_DFRAME_PORT gpioPortC -#define SL_RAIL_UTIL_PTI_DFRAME_PIN 1 - - -// [PTI_SL_RAIL_UTIL_PTI]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_RAIL_UTIL_PTI_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4001a/sl_simple_button_btn0_config.h b/hardware/board/config/brd4113a_brd4001a/sl_simple_button_btn0_config.h deleted file mode 100644 index aab8db6f10..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_simple_button_btn0_config.h +++ /dev/null @@ -1,45 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple Button Driver User Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_BUTTON_BTN0_CONFIG_H -#define SL_SIMPLE_BUTTON_BTN0_CONFIG_H - -#include "em_gpio.h" -#include "sl_simple_button.h" - -// <<< Use Configuration Wizard in Context Menu >>> - -// -// Interrupt -// Poll and Debounce -// Poll -// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT -#define SL_SIMPLE_BUTTON_BTN0_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_BUTTON_BTN0 -// $[GPIO_SL_SIMPLE_BUTTON_BTN0] -#define SL_SIMPLE_BUTTON_BTN0_PORT gpioPortC -#define SL_SIMPLE_BUTTON_BTN0_PIN 5 - -// [GPIO_SL_SIMPLE_BUTTON_BTN0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_BUTTON_BTN0_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4001a/sl_simple_button_btn1_config.h b/hardware/board/config/brd4113a_brd4001a/sl_simple_button_btn1_config.h deleted file mode 100644 index 2a9fde7738..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_simple_button_btn1_config.h +++ /dev/null @@ -1,45 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple Button Driver User Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_BUTTON_BTN1_CONFIG_H -#define SL_SIMPLE_BUTTON_BTN1_CONFIG_H - -#include "em_gpio.h" -#include "sl_simple_button.h" - -// <<< Use Configuration Wizard in Context Menu >>> - -// -// Interrupt -// Poll and Debounce -// Poll -// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT -#define SL_SIMPLE_BUTTON_BTN1_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_BUTTON_BTN1 -// $[GPIO_SL_SIMPLE_BUTTON_BTN1] -#define SL_SIMPLE_BUTTON_BTN1_PORT gpioPortC -#define SL_SIMPLE_BUTTON_BTN1_PIN 4 - -// [GPIO_SL_SIMPLE_BUTTON_BTN1]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_BUTTON_BTN1_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4001a/sl_simple_led_led0_config.h b/hardware/board/config/brd4113a_brd4001a/sl_simple_led_led0_config.h deleted file mode 100644 index 154539fe03..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_simple_led_led0_config.h +++ /dev/null @@ -1,44 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_LED_LED0_CONFIG_H -#define SL_SIMPLE_LED_LED0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple LED configuration -// -// Active low -// Active high -// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH -#define SL_SIMPLE_LED_LED0_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_LED_LED0 -// $[GPIO_SL_SIMPLE_LED_LED0] -#define SL_SIMPLE_LED_LED0_PORT gpioPortC -#define SL_SIMPLE_LED_LED0_PIN 5 - -// [GPIO_SL_SIMPLE_LED_LED0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_LED_LED0_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4001a/sl_simple_led_led1_config.h b/hardware/board/config/brd4113a_brd4001a/sl_simple_led_led1_config.h deleted file mode 100644 index 80d3300858..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_simple_led_led1_config.h +++ /dev/null @@ -1,44 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_LED_LED1_CONFIG_H -#define SL_SIMPLE_LED_LED1_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple LED configuration -// -// Active low -// Active high -// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH -#define SL_SIMPLE_LED_LED1_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_LED_LED1 -// $[GPIO_SL_SIMPLE_LED_LED1] -#define SL_SIMPLE_LED_LED1_PORT gpioPortC -#define SL_SIMPLE_LED_LED1_PIN 4 - -// [GPIO_SL_SIMPLE_LED_LED1]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_LED_LED1_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4113a_brd4001a/sl_uartdrv_eusart_exp_config.h deleted file mode 100644 index aa885fd1fa..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_uartdrv_eusart_exp_config.h +++ /dev/null @@ -1,100 +0,0 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV_EUSART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_UARTDRV_EUSART_EXP_CONFIG_H -#define SL_UARTDRV_EUSART_EXP_CONFIG_H - -#include "em_eusart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// EUSART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_EUSART_EXP_BAUDRATE 115200 - -// Low frequency mode -// True -// False -#define SL_UARTDRV_EUSART_EXP_LF_MODE false - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: eusartNoParity -#define SL_UARTDRV_EUSART_EXP_PARITY eusartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: eusartStopbits1 -#define SL_UARTDRV_EUSART_EXP_STOP_BITS eusartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHw -#define SL_UARTDRV_EUSART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Oversampling disabled -// Default: eusartOVS16 -#define SL_UARTDRV_EUSART_EXP_OVERSAMPLING eusartOVS16 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// False -// True -// Default: eusartMajorityVoteEnable -#define SL_UARTDRV_EUSART_EXP_MVDIS eusartMajorityVoteEnable - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_EUSART_EXP_RX_BUFFER_SIZE 6 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_EUSART_EXP_TX_BUFFER_SIZE 6 -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_EUSART_EXP -// $[EUSART_SL_UARTDRV_EUSART_EXP] -#define SL_UARTDRV_EUSART_EXP_PERIPHERAL EUSART0 -#define SL_UARTDRV_EUSART_EXP_PERIPHERAL_NO 0 - -// EUSART0 TX on PA00 -#define SL_UARTDRV_EUSART_EXP_TX_PORT gpioPortA -#define SL_UARTDRV_EUSART_EXP_TX_PIN 0 - -// EUSART0 RX on PA04 -#define SL_UARTDRV_EUSART_EXP_RX_PORT gpioPortA -#define SL_UARTDRV_EUSART_EXP_RX_PIN 4 - - - -// [EUSART_SL_UARTDRV_EUSART_EXP]$ -// <<< sl:end pin_tool >>> -#endif // SL_UARTDRV_EUSART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4001a/sl_uartdrv_eusart_vcom_config.h b/hardware/board/config/brd4113a_brd4001a/sl_uartdrv_eusart_vcom_config.h deleted file mode 100644 index 8ae6362907..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_uartdrv_eusart_vcom_config.h +++ /dev/null @@ -1,100 +0,0 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV_EUSART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_UARTDRV_EUSART_VCOM_CONFIG_H -#define SL_UARTDRV_EUSART_VCOM_CONFIG_H - -#include "em_eusart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// EUSART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_EUSART_VCOM_BAUDRATE 115200 - -// Low frequency mode -// True -// False -#define SL_UARTDRV_EUSART_VCOM_LF_MODE false - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: eusartNoParity -#define SL_UARTDRV_EUSART_VCOM_PARITY eusartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: eusartStopbits1 -#define SL_UARTDRV_EUSART_VCOM_STOP_BITS eusartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHw -#define SL_UARTDRV_EUSART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlNone - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Oversampling disabled -// Default: eusartOVS16 -#define SL_UARTDRV_EUSART_VCOM_OVERSAMPLING eusartOVS16 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// False -// True -// Default: eusartMajorityVoteEnable -#define SL_UARTDRV_EUSART_VCOM_MVDIS eusartMajorityVoteEnable - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_EUSART_VCOM_RX_BUFFER_SIZE 6 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_EUSART_VCOM_TX_BUFFER_SIZE 6 -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_EUSART_VCOM -// $[EUSART_SL_UARTDRV_EUSART_VCOM] -#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL EUSART0 -#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL_NO 0 - -// EUSART0 TX on PA00 -#define SL_UARTDRV_EUSART_VCOM_TX_PORT gpioPortA -#define SL_UARTDRV_EUSART_VCOM_TX_PIN 0 - -// EUSART0 RX on PA04 -#define SL_UARTDRV_EUSART_VCOM_RX_PORT gpioPortA -#define SL_UARTDRV_EUSART_VCOM_RX_PIN 4 - - - -// [EUSART_SL_UARTDRV_EUSART_VCOM]$ -// <<< sl:end pin_tool >>> -#endif // SL_UARTDRV_EUSART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4001a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4113a_brd4001a/sl_uartdrv_usart_exp_config.h deleted file mode 100644 index d147c8e264..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_uartdrv_usart_exp_config.h +++ /dev/null @@ -1,95 +0,0 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV_USART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_UARTDRV_USART_EXP_CONFIG_H -#define SL_UARTDRV_USART_EXP_CONFIG_H - -#include "em_usart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// UART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_USART_EXP_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_UARTDRV_USART_EXP_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_UARTDRV_USART_EXP_STOP_BITS usartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHw -#define SL_UARTDRV_USART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Default: usartOVS16 -#define SL_UARTDRV_USART_EXP_OVERSAMPLING usartOVS4 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// True -// False -#define SL_UARTDRV_USART_EXP_MVDIS false - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_USART_EXP_RX_BUFFER_SIZE 6 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_USART_EXP_TX_BUFFER_SIZE 6 - -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_USART_EXP -// $[USART_SL_UARTDRV_USART_EXP] -#define SL_UARTDRV_USART_EXP_PERIPHERAL USART0 -#define SL_UARTDRV_USART_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PA00 -#define SL_UARTDRV_USART_EXP_TX_PORT gpioPortA -#define SL_UARTDRV_USART_EXP_TX_PIN 0 - -// USART0 RX on PA04 -#define SL_UARTDRV_USART_EXP_RX_PORT gpioPortA -#define SL_UARTDRV_USART_EXP_RX_PIN 4 - - - -// [USART_SL_UARTDRV_USART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif // SL_UARTDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4001a/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd4113a_brd4001a/sl_uartdrv_usart_vcom_config.h deleted file mode 100644 index 6f63b9a2ea..0000000000 --- a/hardware/board/config/brd4113a_brd4001a/sl_uartdrv_usart_vcom_config.h +++ /dev/null @@ -1,95 +0,0 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV_USART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H -#define SL_UARTDRV_USART_VCOM_CONFIG_H - -#include "em_usart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// UART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHw -#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlNone - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Default: usartOVS16 -#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// True -// False -#define SL_UARTDRV_USART_VCOM_MVDIS false - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 6 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 6 - -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_USART_VCOM -// $[USART_SL_UARTDRV_USART_VCOM] -#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART0 -#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA00 -#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortA -#define SL_UARTDRV_USART_VCOM_TX_PIN 0 - -// USART0 RX on PA04 -#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortA -#define SL_UARTDRV_USART_VCOM_RX_PIN 4 - - - -// [USART_SL_UARTDRV_USART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4002a/btl_euart_driver_cfg.h b/hardware/board/config/brd4113a_brd4002a/btl_euart_driver_cfg.h deleted file mode 100644 index bfe614d22d..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/btl_euart_driver_cfg.h +++ /dev/null @@ -1,82 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader euart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_EUART_DRIVER_CONFIG_H -#define BTL_EUART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// EUART settings - -// Baud rate -// Default: 115200 -#define SL_SERIAL_EUART_BAUD_RATE 115200 - -// Hardware flow control -// Default: 0 -#define SL_SERIAL_EUART_FLOW_CONTROL 0 -// - -// Receive buffer size -// <0-2048:1> -// Default: 512 [0-2048] -#define SL_DRIVER_EUART_RX_BUFFER_SIZE 512 - -// Transmit buffer size -// <0-2048:1> -// Default: 128 [0-2048] -#define SL_DRIVER_EUART_TX_BUFFER_SIZE 128 - -// Virtual COM Port -// Default: 0 -#define SL_VCOM_ENABLE 0 -// - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_SERIAL_EUART -// $[EUSART_SL_SERIAL_EUART] -#define SL_SERIAL_EUART_PERIPHERAL EUSART0 -#define SL_SERIAL_EUART_PERIPHERAL_NO 0 - -// EUSART0 TX on PA00 -#define SL_SERIAL_EUART_TX_PORT gpioPortA -#define SL_SERIAL_EUART_TX_PIN 0 - -// EUSART0 RX on PA04 -#define SL_SERIAL_EUART_RX_PORT gpioPortA -#define SL_SERIAL_EUART_RX_PIN 4 - - - -// [EUSART_SL_SERIAL_EUART]$ - - -// SL_VCOM_ENABLE - -// $[GPIO_SL_VCOM_ENABLE] -#define SL_VCOM_ENABLE_PORT gpioPortC -#define SL_VCOM_ENABLE_PIN 3 - -// [GPIO_SL_VCOM_ENABLE]$ - - -// <<< sl:end pin_tool >>> - -#endif // BTL_EUART_DRIVER_CONFIG_H \ No newline at end of file diff --git a/hardware/board/config/brd4113a_brd4002a/btl_ezsp_gpio_activation_cfg.h b/hardware/board/config/brd4113a_brd4002a/btl_ezsp_gpio_activation_cfg.h deleted file mode 100644 index 620a881b5e..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/btl_ezsp_gpio_activation_cfg.h +++ /dev/null @@ -1,52 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader EZSP GPIO Activation - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_EZSP_GPIO_ACTIVATION_CONFIG_H -#define BTL_EZSP_GPIO_ACTIVATION_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Properties of SPI NCP - -// Active state -// Low -// High -// Default: LOW -// Enter firmware upgrade mode if GPIO pin has this state -#define SL_EZSP_GPIO_ACTIVATION_POLARITY LOW - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_EZSPSPI_HOST_INT -// $[GPIO_SL_EZSPSPI_HOST_INT] -#define SL_EZSPSPI_HOST_INT_PORT gpioPortC -#define SL_EZSPSPI_HOST_INT_PIN 5 - -// [GPIO_SL_EZSPSPI_HOST_INT]$ - -// SL_EZSPSPI_WAKE_INT -// $[GPIO_SL_EZSPSPI_WAKE_INT] -#define SL_EZSPSPI_WAKE_INT_PORT gpioPortC -#define SL_EZSPSPI_WAKE_INT_PIN 4 - -// [GPIO_SL_EZSPSPI_WAKE_INT]$ - -// <<< sl:end pin_tool >>> - -#endif // BTL_EZSP_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4002a/btl_gpio_activation_cfg.h b/hardware/board/config/brd4113a_brd4002a/btl_gpio_activation_cfg.h deleted file mode 100644 index 51573b25df..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/btl_gpio_activation_cfg.h +++ /dev/null @@ -1,49 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader GPIO Activation - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_GPIO_ACTIVATION_CONFIG_H -#define BTL_GPIO_ACTIVATION_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Properties of Bootloader Entry - - -// Active state -// Low -// High -// Default: LOW -// Enter firmware upgrade mode if GPIO pin has this state -#define SL_GPIO_ACTIVATION_POLARITY LOW - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_BTL_BUTTON - -// $[GPIO_SL_BTL_BUTTON] -#define SL_BTL_BUTTON_PORT gpioPortC -#define SL_BTL_BUTTON_PIN 5 - -// [GPIO_SL_BTL_BUTTON]$ - -// <<< sl:end pin_tool >>> - - -#endif // BTL_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4002a/btl_spi_controller_eusart_driver_cfg.h b/hardware/board/config/brd4113a_brd4002a/btl_spi_controller_eusart_driver_cfg.h deleted file mode 100644 index 308060ef81..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/btl_spi_controller_eusart_driver_cfg.h +++ /dev/null @@ -1,68 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader Spi Controller Eusart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H -#define BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// SPI Controller EUSART Driver - -// Frequency -// Default: 6400000 -#define SL_EUSART_EXTFLASH_FREQUENCY 6400000 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_EUSART_EXTFLASH -// $[EUSART_SL_EUSART_EXTFLASH] -#define SL_EUSART_EXTFLASH_PERIPHERAL EUSART0 -#define SL_EUSART_EXTFLASH_PERIPHERAL_NO 0 - -// EUSART0 TX on PB00 -#define SL_EUSART_EXTFLASH_TX_PORT gpioPortB -#define SL_EUSART_EXTFLASH_TX_PIN 0 - -// EUSART0 RX on PB01 -#define SL_EUSART_EXTFLASH_RX_PORT gpioPortB -#define SL_EUSART_EXTFLASH_RX_PIN 1 - -// EUSART0 SCLK on PB02 -#define SL_EUSART_EXTFLASH_SCLK_PORT gpioPortB -#define SL_EUSART_EXTFLASH_SCLK_PIN 2 - -// EUSART0 CS on PC02 -#define SL_EUSART_EXTFLASH_CS_PORT gpioPortC -#define SL_EUSART_EXTFLASH_CS_PIN 2 - -// [EUSART_SL_EUSART_EXTFLASH]$ - -// SL_EXTFLASH_WP -// $[GPIO_SL_EXTFLASH_WP] - -// [GPIO_SL_EXTFLASH_WP]$ - -// SL_EXTFLASH_HOLD -// $[GPIO_SL_EXTFLASH_HOLD] - -// [GPIO_SL_EXTFLASH_HOLD]$ - -// <<< sl:end pin_tool >>> - -#endif // BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4002a/btl_spi_controller_usart_driver_cfg.h b/hardware/board/config/brd4113a_brd4002a/btl_spi_controller_usart_driver_cfg.h deleted file mode 100644 index 6ac5f54418..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/btl_spi_controller_usart_driver_cfg.h +++ /dev/null @@ -1,68 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader Spi Controller Usart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H -#define BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// SPI Controller USART Driver - -// Frequency -// Default: 6400000 -#define SL_USART_EXTFLASH_FREQUENCY 6400000 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_USART_EXTFLASH -// $[USART_SL_USART_EXTFLASH] -#define SL_USART_EXTFLASH_PERIPHERAL USART0 -#define SL_USART_EXTFLASH_PERIPHERAL_NO 0 - -// USART0 TX on PB00 -#define SL_USART_EXTFLASH_TX_PORT gpioPortB -#define SL_USART_EXTFLASH_TX_PIN 0 - -// USART0 RX on PB01 -#define SL_USART_EXTFLASH_RX_PORT gpioPortB -#define SL_USART_EXTFLASH_RX_PIN 1 - -// USART0 CLK on PB02 -#define SL_USART_EXTFLASH_CLK_PORT gpioPortB -#define SL_USART_EXTFLASH_CLK_PIN 2 - -// USART0 CS on PC02 -#define SL_USART_EXTFLASH_CS_PORT gpioPortC -#define SL_USART_EXTFLASH_CS_PIN 2 - -// [USART_SL_USART_EXTFLASH]$ - -// SL_EXTFLASH_WP -// $[GPIO_SL_EXTFLASH_WP] - -// [GPIO_SL_EXTFLASH_WP]$ - -// SL_EXTFLASH_HOLD -// $[GPIO_SL_EXTFLASH_HOLD] - -// [GPIO_SL_EXTFLASH_HOLD]$ - -// <<< sl:end pin_tool >>> - -#endif // BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4002a/btl_uart_driver_cfg.h b/hardware/board/config/brd4113a_brd4002a/btl_uart_driver_cfg.h deleted file mode 100644 index db68887cd0..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/btl_uart_driver_cfg.h +++ /dev/null @@ -1,83 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader Uart Driver - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_UART_DRIVER_CONFIG_H -#define BTL_UART_DRIVER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// USART settings - -// Baud rate -// Default: 115200 -#define SL_SERIAL_UART_BAUD_RATE 115200 - -// Hardware flow control -// Default: 0 -#define SL_SERIAL_UART_FLOW_CONTROL 0 -// - -// Receive buffer size -// <0-2048:1> -// Default: 512 [0-2048] -#define SL_DRIVER_UART_RX_BUFFER_SIZE 512 - -// Transmit buffer size -// <0-2048:1> -// Default: 128 [0-2048] -#define SL_DRIVER_UART_TX_BUFFER_SIZE 128 - -// Virtual COM Port -// Default: 0 -#define SL_VCOM_ENABLE 0 -// - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_SERIAL_UART -// $[USART_SL_SERIAL_UART] -#define SL_SERIAL_UART_PERIPHERAL USART0 -#define SL_SERIAL_UART_PERIPHERAL_NO 0 - -// USART0 TX on PA00 -#define SL_SERIAL_UART_TX_PORT gpioPortA -#define SL_SERIAL_UART_TX_PIN 0 - -// USART0 RX on PA04 -#define SL_SERIAL_UART_RX_PORT gpioPortA -#define SL_SERIAL_UART_RX_PIN 4 - - - -// [USART_SL_SERIAL_UART]$ - - - -// SL_VCOM_ENABLE - -// $[GPIO_SL_VCOM_ENABLE] -#define SL_VCOM_ENABLE_PORT gpioPortC -#define SL_VCOM_ENABLE_PIN 3 - -// [GPIO_SL_VCOM_ENABLE]$ - - -// <<< sl:end pin_tool >>> - -#endif // BTL_UART_DRIVER_CONFIG_H \ No newline at end of file diff --git a/hardware/board/config/brd4113a_brd4002a/iot_flash_cfg_spiflash.h b/hardware/board/config/brd4113a_brd4002a/iot_flash_cfg_spiflash.h deleted file mode 100644 index 3b634d9b08..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/iot_flash_cfg_spiflash.h +++ /dev/null @@ -1,136 +0,0 @@ -/***************************************************************************//** - * @file iot_flash_cfg_inst.h - * @brief Common I/O flash instance configurations. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_FLASH_CFG_SPIFLASH_H_ -#define _IOT_FLASH_CFG_SPIFLASH_H_ - -/******************************************************************************* - * Flash Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// Flash General Options - -// Instance number -// Instance number used when iot_flash_open() is called. -// Default: 0 -#define IOT_FLASH_CFG_SPIFLASH_INST_NUM 0 - -// Instance type -// <0=> Internal Flash (MSC) -// <1=> External Flash (SPI) -// Specify whether this instance is for internal flash (MSC) -// or an external SPI flash. If external, then you need to setup -// SPI configs below. -// Default: 0 -#define IOT_FLASH_CFG_SPIFLASH_INST_TYPE 1 - -// - -// SPI Configuration - -// Default SPI bitrate -// Default: 1000000 -#define IOT_FLASH_CFG_SPIFLASH_SPI_BITRATE 1000000 - -// Default SPI frame length <4-16> -// Default: 8 -#define IOT_FLASH_CFG_SPIFLASH_SPI_FRAME_LENGTH 8 - -// Default SPI master/slave mode -// Master -// Slave -#define IOT_FLASH_CFG_SPIFLASH_SPI_TYPE spidrvMaster - -// Default SPI bit order -// LSB transmitted first -// MSB transmitted first -#define IOT_FLASH_CFG_SPIFLASH_SPI_BIT_ORDER spidrvBitOrderMsbFirst - -// Default SPI clock mode -// SPI mode 0: CLKPOL=0, CLKPHA=0 -// SPI mode 1: CLKPOL=0, CLKPHA=1 -// SPI mode 2: CLKPOL=1, CLKPHA=0 -// SPI mode 3: CLKPOL=1, CLKPHA=1 -#define IOT_FLASH_CFG_SPIFLASH_SPI_CLOCK_MODE spidrvClockMode0 - -// Default SPI CS control scheme -// CS controlled by the SPI driver -// CS controlled by the application -#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_CONTROL spidrvCsControlApplication - -// Default SPI transfer scheme -// Transfer starts immediately -// Transfer starts when the bus is idle -#define IOT_FLASH_CFG_SPIFLASH_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * EXTERNAL FLASH: H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_FLASH_CFG_SPIFLASH_SPI -// $[USART_IOT_FLASH_CFG_SPIFLASH_SPI] -#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL USART0 -#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL_NO 0 - -// USART0 TX on PB00 -#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PORT gpioPortB -#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PIN 0 - -// USART0 RX on PB01 -#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PORT gpioPortB -#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PIN 1 - -// USART0 CLK on PB02 -#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PORT gpioPortB -#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PIN 2 - -// USART0 CS on PC02 -#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PORT gpioPortC -#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PIN 2 - -// [USART_IOT_FLASH_CFG_SPIFLASH_SPI]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_FLASH_CFG_SPIFLASH_H_ */ diff --git a/hardware/board/config/brd4113a_brd4002a/iot_pwm_cfg_exp.h b/hardware/board/config/brd4113a_brd4002a/iot_pwm_cfg_exp.h deleted file mode 100644 index 306f255589..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/iot_pwm_cfg_exp.h +++ /dev/null @@ -1,78 +0,0 @@ -/***************************************************************************//** - * @file iot_pwm_cfg_inst.h - * @brief Common I/O PWM instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_PWM_CFG_EXP_H_ -#define _IOT_PWM_CFG_EXP_H_ - -/******************************************************************************* - * PWM Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// PWM General Options - -// Instance number -// Instance number used when iot_pwm_open() is called. -// Default: 0 -#define IOT_PWM_CFG_EXP_INST_NUM 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_PWM_CFG_EXP -// $[TIMER_IOT_PWM_CFG_EXP] -#define IOT_PWM_CFG_EXP_PERIPHERAL TIMER3 -#define IOT_PWM_CFG_EXP_PERIPHERAL_NO 3 - -// TIMER3 CC0 on PC05 -#define IOT_PWM_CFG_EXP_CC0_PORT gpioPortC -#define IOT_PWM_CFG_EXP_CC0_PIN 5 - - - -// [TIMER_IOT_PWM_CFG_EXP]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_PWM_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4113a_brd4002a/iot_pwm_cfg_led0.h b/hardware/board/config/brd4113a_brd4002a/iot_pwm_cfg_led0.h deleted file mode 100644 index 8281baf8c7..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/iot_pwm_cfg_led0.h +++ /dev/null @@ -1,78 +0,0 @@ -/***************************************************************************//** - * @file iot_pwm_cfg_inst.h - * @brief Common I/O PWM instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_PWM_CFG_LED0_H_ -#define _IOT_PWM_CFG_LED0_H_ - -/******************************************************************************* - * PWM Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// PWM General Options - -// Instance number -// Instance number used when iot_pwm_open() is called. -// Default: 0 -#define IOT_PWM_CFG_LED0_INST_NUM 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_PWM_CFG_LED0 -// $[TIMER_IOT_PWM_CFG_LED0] -#define IOT_PWM_CFG_LED0_PERIPHERAL TIMER0 -#define IOT_PWM_CFG_LED0_PERIPHERAL_NO 0 - -// TIMER0 CC0 on PC05 -#define IOT_PWM_CFG_LED0_CC0_PORT gpioPortC -#define IOT_PWM_CFG_LED0_CC0_PIN 5 - - - -// [TIMER_IOT_PWM_CFG_LED0]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_PWM_CFG_LED0_H_ */ diff --git a/hardware/board/config/brd4113a_brd4002a/iot_pwm_cfg_led1.h b/hardware/board/config/brd4113a_brd4002a/iot_pwm_cfg_led1.h deleted file mode 100644 index 5437b9bda9..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/iot_pwm_cfg_led1.h +++ /dev/null @@ -1,78 +0,0 @@ -/***************************************************************************//** - * @file iot_pwm_cfg_inst.h - * @brief Common I/O PWM instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_PWM_CFG_LED1_H_ -#define _IOT_PWM_CFG_LED1_H_ - -/******************************************************************************* - * PWM Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// PWM General Options - -// Instance number -// Instance number used when iot_pwm_open() is called. -// Default: 0 -#define IOT_PWM_CFG_LED1_INST_NUM 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_PWM_CFG_LED1 -// $[TIMER_IOT_PWM_CFG_LED1] -#define IOT_PWM_CFG_LED1_PERIPHERAL TIMER1 -#define IOT_PWM_CFG_LED1_PERIPHERAL_NO 1 - -// TIMER1 CC0 on PC04 -#define IOT_PWM_CFG_LED1_CC0_PORT gpioPortC -#define IOT_PWM_CFG_LED1_CC0_PIN 4 - - - -// [TIMER_IOT_PWM_CFG_LED1]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_PWM_CFG_LED1_H_ */ diff --git a/hardware/board/config/brd4113a_brd4002a/iot_uart_cfg_exp.h b/hardware/board/config/brd4113a_brd4002a/iot_uart_cfg_exp.h deleted file mode 100644 index abe3e154ae..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/iot_uart_cfg_exp.h +++ /dev/null @@ -1,126 +0,0 @@ -/***************************************************************************//** - * @file iot_uart_cfg_inst.h - * @brief Common I/O UART instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_UART_CFG_EXP_H_ -#define _IOT_UART_CFG_EXP_H_ - -/******************************************************************************* - * UART Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// UART General Options - -// Instance number -// Instance number used when iot_uart_open() is called. -// Default: 0 -#define IOT_UART_CFG_EXP_INST_NUM 0 - -// Default baud rate -// Default: 115200 -#define IOT_UART_CFG_EXP_DEFAULT_BAUDRATE 115200 - -// Default number of data bits -// 4 data bits -// 5 data bits -// 6 data bits -// 7 data bits -// 8 data bits -// Default: usartDatabits8 -#define IOT_UART_CFG_EXP_DEFAULT_DATA_BITS usartDatabits8 - -// Default parity mode -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define IOT_UART_CFG_EXP_DEFAULT_PARITY usartNoParity - -// Default number of stop bits -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define IOT_UART_CFG_EXP_DEFAULT_STOP_BITS usartStopbits1 - -// Default hardware flow control -// None -// CTS -// RTS -// CTS/RTS -// Default: usartHwFlowControlNone -#define IOT_UART_CFG_EXP_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone - - -// Internal Loopback -// Enable USART Internal loopback -// Default: 0 -#define IOT_UART_CFG_EXP_LOOPBACK 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_UART_CFG_EXP -// $[USART_IOT_UART_CFG_EXP] -#define IOT_UART_CFG_EXP_PERIPHERAL USART0 -#define IOT_UART_CFG_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PA00 -#define IOT_UART_CFG_EXP_TX_PORT gpioPortA -#define IOT_UART_CFG_EXP_TX_PIN 0 - -// USART0 RX on PA04 -#define IOT_UART_CFG_EXP_RX_PORT gpioPortA -#define IOT_UART_CFG_EXP_RX_PIN 4 - - - - - -// [USART_IOT_UART_CFG_EXP]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_UART_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4113a_brd4002a/iot_uart_cfg_loopback.h b/hardware/board/config/brd4113a_brd4002a/iot_uart_cfg_loopback.h deleted file mode 100644 index 5de3406c56..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/iot_uart_cfg_loopback.h +++ /dev/null @@ -1,126 +0,0 @@ -/***************************************************************************//** - * @file iot_uart_cfg_inst.h - * @brief Common I/O UART instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_UART_CFG_LOOPBACK_H_ -#define _IOT_UART_CFG_LOOPBACK_H_ - -/******************************************************************************* - * UART Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// UART General Options - -// Instance number -// Instance number used when iot_uart_open() is called. -// Default: 0 -#define IOT_UART_CFG_LOOPBACK_INST_NUM 0 - -// Default baud rate -// Default: 115200 -#define IOT_UART_CFG_LOOPBACK_DEFAULT_BAUDRATE 115200 - -// Default number of data bits -// 4 data bits -// 5 data bits -// 6 data bits -// 7 data bits -// 8 data bits -// Default: usartDatabits8 -#define IOT_UART_CFG_LOOPBACK_DEFAULT_DATA_BITS usartDatabits8 - -// Default parity mode -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define IOT_UART_CFG_LOOPBACK_DEFAULT_PARITY usartNoParity - -// Default number of stop bits -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define IOT_UART_CFG_LOOPBACK_DEFAULT_STOP_BITS usartStopbits1 - -// Default hardware flow control -// None -// CTS -// RTS -// CTS/RTS -// Default: usartHwFlowControlNone -#define IOT_UART_CFG_LOOPBACK_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone - - -// Internal Loopback -// Enable USART Internal loopback -// Default: 0 -#define IOT_UART_CFG_LOOPBACK_LOOPBACK 1 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_UART_CFG_LOOPBACK -// $[USART_IOT_UART_CFG_LOOPBACK] -#define IOT_UART_CFG_LOOPBACK_PERIPHERAL USART0 -#define IOT_UART_CFG_LOOPBACK_PERIPHERAL_NO 0 - -// USART0 TX on PA00 -#define IOT_UART_CFG_LOOPBACK_TX_PORT gpioPortA -#define IOT_UART_CFG_LOOPBACK_TX_PIN 0 - -// USART0 RX on PA04 -#define IOT_UART_CFG_LOOPBACK_RX_PORT gpioPortA -#define IOT_UART_CFG_LOOPBACK_RX_PIN 4 - - - - - -// [USART_IOT_UART_CFG_LOOPBACK]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_UART_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4113a_brd4002a/iot_uart_cfg_vcom.h b/hardware/board/config/brd4113a_brd4002a/iot_uart_cfg_vcom.h deleted file mode 100644 index ad8c064b91..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/iot_uart_cfg_vcom.h +++ /dev/null @@ -1,126 +0,0 @@ -/***************************************************************************//** - * @file iot_uart_cfg_inst.h - * @brief Common I/O UART instance configuration. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#ifndef _IOT_UART_CFG_VCOM_H_ -#define _IOT_UART_CFG_VCOM_H_ - -/******************************************************************************* - * UART Default Configs - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// UART General Options - -// Instance number -// Instance number used when iot_uart_open() is called. -// Default: 0 -#define IOT_UART_CFG_VCOM_INST_NUM 0 - -// Default baud rate -// Default: 115200 -#define IOT_UART_CFG_VCOM_DEFAULT_BAUDRATE 115200 - -// Default number of data bits -// 4 data bits -// 5 data bits -// 6 data bits -// 7 data bits -// 8 data bits -// Default: usartDatabits8 -#define IOT_UART_CFG_VCOM_DEFAULT_DATA_BITS usartDatabits8 - -// Default parity mode -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define IOT_UART_CFG_VCOM_DEFAULT_PARITY usartNoParity - -// Default number of stop bits -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define IOT_UART_CFG_VCOM_DEFAULT_STOP_BITS usartStopbits1 - -// Default hardware flow control -// None -// CTS -// RTS -// CTS/RTS -// Default: usartHwFlowControlNone -#define IOT_UART_CFG_VCOM_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone - - -// Internal Loopback -// Enable USART Internal loopback -// Default: 0 -#define IOT_UART_CFG_VCOM_LOOPBACK 0 - -// - -// <<< end of configuration section >>> - -/******************************************************************************* - * H/W PERIPHERAL CONFIG - ******************************************************************************/ - -// <<< sl:start pin_tool >>> -// IOT_UART_CFG_VCOM -// $[USART_IOT_UART_CFG_VCOM] -#define IOT_UART_CFG_VCOM_PERIPHERAL USART0 -#define IOT_UART_CFG_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA00 -#define IOT_UART_CFG_VCOM_TX_PORT gpioPortA -#define IOT_UART_CFG_VCOM_TX_PIN 0 - -// USART0 RX on PA04 -#define IOT_UART_CFG_VCOM_RX_PORT gpioPortA -#define IOT_UART_CFG_VCOM_RX_PIN 4 - - - - - -// [USART_IOT_UART_CFG_VCOM]$ -// <<< sl:end pin_tool >>> - -/******************************************************************************* - * SAFE GUARD - ******************************************************************************/ - -#endif /* _IOT_UART_CFG_VCOM_H_ */ diff --git a/hardware/board/config/brd4113a_brd4002a/sl_board_control_config.h b/hardware/board/config/brd4113a_brd4002a/sl_board_control_config.h deleted file mode 100644 index 7959f2d516..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_board_control_config.h +++ /dev/null @@ -1,56 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Board Control - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_BOARD_CONTROL_CONFIG_H -#define SL_BOARD_CONTROL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Enable Virtual COM UART -// Default: 0 -#define SL_BOARD_ENABLE_VCOM 0 - -// Disable SPI Flash -// Default: 1 -#define SL_BOARD_DISABLE_MEMORY_SPI 1 - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_BOARD_ENABLE_VCOM -// $[GPIO_SL_BOARD_ENABLE_VCOM] -#define SL_BOARD_ENABLE_VCOM_PORT gpioPortC -#define SL_BOARD_ENABLE_VCOM_PIN 3 -// [GPIO_SL_BOARD_ENABLE_VCOM]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4002a/sl_cpc_drv_primary_uart_usart_exp_config.h b/hardware/board/config/brd4113a_brd4002a/sl_cpc_drv_primary_uart_usart_exp_config.h deleted file mode 100644 index f6ba810055..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_cpc_drv_primary_uart_usart_exp_config.h +++ /dev/null @@ -1,70 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC UART PRIMARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_USART_EXP_PRIMARY_CONFIG_H -#define SL_CPC_DRV_UART_USART_EXP_PRIMARY_CONFIG_H - -// CPC-Primary UART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 - -// UART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_EXP -// $[USART_SL_CPC_DRV_UART_EXP] -#define SL_CPC_DRV_UART_EXP_PERIPHERAL USART0 -#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PA00 -#define SL_CPC_DRV_UART_EXP_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_TX_PIN 0 - -// USART0 RX on PA04 -#define SL_CPC_DRV_UART_EXP_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_RX_PIN 4 - -// [USART_SL_CPC_DRV_UART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_EXP_PRIMARY_CONFIG_H */ diff --git a/hardware/board/config/brd4113a_brd4002a/sl_cpc_drv_primary_uart_usart_vcom_config.h b/hardware/board/config/brd4113a_brd4002a/sl_cpc_drv_primary_uart_usart_vcom_config.h deleted file mode 100644 index 7fd233d3f7..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_cpc_drv_primary_uart_usart_vcom_config.h +++ /dev/null @@ -1,70 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC UART PRIMARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_USART_VCOM_PRIMARY_CONFIG_H -#define SL_CPC_DRV_UART_USART_VCOM_PRIMARY_CONFIG_H - -// CPC-Primary UART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 - -// UART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_VCOM -// $[USART_SL_CPC_DRV_UART_VCOM] -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA00 -#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_TX_PIN 0 - -// USART0 RX on PA04 -#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_RX_PIN 4 - -// [USART_SL_CPC_DRV_UART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_VCOM_PRIMARY_CONFIG_H */ diff --git a/hardware/board/config/brd4113a_brd4002a/sl_cpc_drv_secondary_uart_eusart_exp_config.h b/hardware/board/config/brd4113a_brd4002a/sl_cpc_drv_secondary_uart_eusart_exp_config.h deleted file mode 100644 index 79cd709be0..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_cpc_drv_secondary_uart_eusart_exp_config.h +++ /dev/null @@ -1,78 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC EUSART SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_EUSART_EXP_SECONDARY_CONFIG_H -#define SL_CPC_DRV_UART_EUSART_EXP_SECONDARY_CONFIG_H - -// CPC - Secondary EUSART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 - -// EUSART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 - -// Flow control -// None -// CTS/RTS -// Default: eusartHwFlowControlNone -#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_EXP -// $[EUSART_SL_CPC_DRV_UART_EXP] -#define SL_CPC_DRV_UART_EXP_PERIPHERAL EUSART0 -#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 - -// EUSART0 TX on PA00 -#define SL_CPC_DRV_UART_EXP_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_TX_PIN 0 - -// EUSART0 RX on PA04 -#define SL_CPC_DRV_UART_EXP_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_RX_PIN 4 - - - -// [EUSART_SL_CPC_DRV_UART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4113a_brd4002a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h b/hardware/board/config/brd4113a_brd4002a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h deleted file mode 100644 index a745607924..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h +++ /dev/null @@ -1,78 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC EUSART SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_EUSART_VCOM_SECONDARY_CONFIG_H -#define SL_CPC_DRV_UART_EUSART_VCOM_SECONDARY_CONFIG_H - -// CPC - Secondary EUSART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 - -// EUSART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 - -// Flow control -// None -// CTS/RTS -// Default: eusartHwFlowControlNone -#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_VCOM -// $[EUSART_SL_CPC_DRV_UART_VCOM] -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL EUSART0 -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 - -// EUSART0 TX on PA00 -#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_TX_PIN 0 - -// EUSART0 RX on PA04 -#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_RX_PIN 4 - - - -// [EUSART_SL_CPC_DRV_UART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_VCOM_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4113a_brd4002a/sl_cpc_drv_secondary_uart_usart_exp_config.h b/hardware/board/config/brd4113a_brd4002a/sl_cpc_drv_secondary_uart_usart_exp_config.h deleted file mode 100644 index 5805023087..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_cpc_drv_secondary_uart_usart_exp_config.h +++ /dev/null @@ -1,78 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC UART SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_USART_EXP_SECONDARY_CONFIG_H -#define SL_CPC_DRV_UART_USART_EXP_SECONDARY_CONFIG_H - -// CPC - Secondary UART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 - -// UART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 - -// Flow control -// None -// CTS/RTS -// Default: usartHwFlowControlCtsAndRts -#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_EXP -// $[USART_SL_CPC_DRV_UART_EXP] -#define SL_CPC_DRV_UART_EXP_PERIPHERAL USART0 -#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PA00 -#define SL_CPC_DRV_UART_EXP_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_TX_PIN 0 - -// USART0 RX on PA04 -#define SL_CPC_DRV_UART_EXP_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_EXP_RX_PIN 4 - - - -// [USART_SL_CPC_DRV_UART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4113a_brd4002a/sl_cpc_drv_secondary_uart_usart_vcom_config.h b/hardware/board/config/brd4113a_brd4002a/sl_cpc_drv_secondary_uart_usart_vcom_config.h deleted file mode 100644 index 7139445bb0..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_cpc_drv_secondary_uart_usart_vcom_config.h +++ /dev/null @@ -1,78 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CPC UART SECONDARY driver configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CPC_DRV_UART_USART_VCOM_SECONDARY_CONFIG_H -#define SL_CPC_DRV_UART_USART_VCOM_SECONDARY_CONFIG_H - -// CPC - Secondary UART Driver Configuration - -// Number of frame that can be queued in the driver receive queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 - -// Number of frame that can be queued in the driver transmit queue -// Default: 10 -#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 - -// UART Baudrate -// Default: 115200 -#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 - -// Flow control -// None -// CTS/RTS -// Default: usartHwFlowControlCtsAndRts -#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_CPC_DRV_UART_VCOM -// $[USART_SL_CPC_DRV_UART_VCOM] -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 -#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA00 -#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_TX_PIN 0 - -// USART0 RX on PA04 -#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA -#define SL_CPC_DRV_UART_VCOM_RX_PIN 4 - - - -// [USART_SL_CPC_DRV_UART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif /* SL_CPC_DRV_UART_VCOM_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4113a_brd4002a/sl_device_init_hfxo_config.h b/hardware/board/config/brd4113a_brd4002a/sl_device_init_hfxo_config.h deleted file mode 100644 index b0938ac495..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_device_init_hfxo_config.h +++ /dev/null @@ -1,53 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_HFXO Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H -#define SL_DEVICE_INIT_HFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// External sine wave -// Default: cmuHfxoOscMode_Crystal -#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal - -// Frequency <38000000-40000000> -// Default: 38400000 -#define SL_DEVICE_INIT_HFXO_FREQ 38400000 - -// CTUNE <0-255> -// Default: 140 -#define SL_DEVICE_INIT_HFXO_CTUNE 120 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4002a/sl_device_init_lfxo_config.h b/hardware/board/config/brd4113a_brd4002a/sl_device_init_lfxo_config.h deleted file mode 100644 index 0e1f4147bf..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_device_init_lfxo_config.h +++ /dev/null @@ -1,66 +0,0 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_LFXO Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H -#define SL_DEVICE_INIT_LFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// AC-coupled buffer -// External digital clock -// Default: cmuLfxoOscMode_Crystal -#define SL_DEVICE_INIT_LFXO_MODE cmuLfxoOscMode_Crystal - -// CTUNE <0-127> -// Default: 63 -#define SL_DEVICE_INIT_LFXO_CTUNE 37 - -// LFXO precision in PPM <0-65535> -// Default: 500 -#define SL_DEVICE_INIT_LFXO_PRECISION 100 - -// Startup Timeout Delay -// -// 2 cycles -// 256 cycles -// 1K cycles -// 2K cycles -// 4K cycles -// 8K cycles -// 16K cycles -// 32K cycles -// Default: cmuLfxoStartupDelay_4KCycles -#define SL_DEVICE_INIT_LFXO_TIMEOUT cmuLfxoStartupDelay_4KCycles -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4002a/sl_iostream_eusart_exp_config.h b/hardware/board/config/brd4113a_brd4002a/sl_iostream_eusart_exp_config.h deleted file mode 100644 index a73dea84df..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_iostream_eusart_exp_config.h +++ /dev/null @@ -1,107 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_EUSART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_EUSART_EXP_CONFIG_H -#define SL_IOSTREAM_EUSART_EXP_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// EUART settings - -// Enable High frequency mode -// Default: 1 -#define SL_IOSTREAM_EUSART_EXP_ENABLE_HIGH_FREQUENCY 1 - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_EUSART_EXP_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: eusartNoParity -#define SL_IOSTREAM_EUSART_EXP_PARITY eusartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: eusartStopbits1 -#define SL_IOSTREAM_EUSART_EXP_STOP_BITS eusartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: eusartHwFlowControlNone -#define SL_IOSTREAM_EUSART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlNone - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_EUSART_EXP_RX_BUFFER_SIZE 32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_EUSART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_EUSART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_EUSART_EXP -// $[EUSART_SL_IOSTREAM_EUSART_EXP] -#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL EUSART0 -#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL_NO 0 - -// EUSART0 TX on PA00 -#define SL_IOSTREAM_EUSART_EXP_TX_PORT gpioPortA -#define SL_IOSTREAM_EUSART_EXP_TX_PIN 0 - -// EUSART0 RX on PA04 -#define SL_IOSTREAM_EUSART_EXP_RX_PORT gpioPortA -#define SL_IOSTREAM_EUSART_EXP_RX_PIN 4 - - - -// [EUSART_SL_IOSTREAM_EUSART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4113a_brd4002a/sl_iostream_eusart_vcom_config.h b/hardware/board/config/brd4113a_brd4002a/sl_iostream_eusart_vcom_config.h deleted file mode 100644 index fd2d36c93f..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_iostream_eusart_vcom_config.h +++ /dev/null @@ -1,107 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_EUSART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_EUSART_VCOM_CONFIG_H -#define SL_IOSTREAM_EUSART_VCOM_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// EUART settings - -// Enable High frequency mode -// Default: 1 -#define SL_IOSTREAM_EUSART_VCOM_ENABLE_HIGH_FREQUENCY 1 - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_EUSART_VCOM_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: eusartNoParity -#define SL_IOSTREAM_EUSART_VCOM_PARITY eusartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: eusartStopbits1 -#define SL_IOSTREAM_EUSART_VCOM_STOP_BITS eusartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: eusartHwFlowControlNone -#define SL_IOSTREAM_EUSART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlNone - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_EUSART_VCOM_RX_BUFFER_SIZE 32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_EUSART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_EUSART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_EUSART_VCOM -// $[EUSART_SL_IOSTREAM_EUSART_VCOM] -#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL EUSART0 -#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL_NO 0 - -// EUSART0 TX on PA00 -#define SL_IOSTREAM_EUSART_VCOM_TX_PORT gpioPortA -#define SL_IOSTREAM_EUSART_VCOM_TX_PIN 0 - -// EUSART0 RX on PA04 -#define SL_IOSTREAM_EUSART_VCOM_RX_PORT gpioPortA -#define SL_IOSTREAM_EUSART_VCOM_RX_PIN 4 - - - -// [EUSART_SL_IOSTREAM_EUSART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4113a_brd4002a/sl_iostream_usart_exp_config.h b/hardware/board/config/brd4113a_brd4002a/sl_iostream_usart_exp_config.h deleted file mode 100644 index f46ecf2199..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_iostream_usart_exp_config.h +++ /dev/null @@ -1,103 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_USART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_USART_EXP_CONFIG_H -#define SL_IOSTREAM_USART_EXP_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// USART settings - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_USART_EXP_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_IOSTREAM_USART_EXP_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_IOSTREAM_USART_EXP_STOP_BITS usartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: usartHwFlowControlNone -#define SL_IOSTREAM_USART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlNone - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_USART_EXP_RX_BUFFER_SIZE 32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_USART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_USART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_USART_EXP -// $[USART_SL_IOSTREAM_USART_EXP] -#define SL_IOSTREAM_USART_EXP_PERIPHERAL USART0 -#define SL_IOSTREAM_USART_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PA00 -#define SL_IOSTREAM_USART_EXP_TX_PORT gpioPortA -#define SL_IOSTREAM_USART_EXP_TX_PIN 0 - -// USART0 RX on PA04 -#define SL_IOSTREAM_USART_EXP_RX_PORT gpioPortA -#define SL_IOSTREAM_USART_EXP_RX_PIN 4 - - - -// [USART_SL_IOSTREAM_USART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4113a_brd4002a/sl_iostream_usart_vcom_config.h b/hardware/board/config/brd4113a_brd4002a/sl_iostream_usart_vcom_config.h deleted file mode 100644 index 32956fefb4..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_iostream_usart_vcom_config.h +++ /dev/null @@ -1,103 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_USART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H -#define SL_IOSTREAM_USART_VCOM_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// USART settings - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_USART_VCOM_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: usartHwFlowControlNone -#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlNone - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_USART_VCOM -// $[USART_SL_IOSTREAM_USART_VCOM] -#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART0 -#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA00 -#define SL_IOSTREAM_USART_VCOM_TX_PORT gpioPortA -#define SL_IOSTREAM_USART_VCOM_TX_PIN 0 - -// USART0 RX on PA04 -#define SL_IOSTREAM_USART_VCOM_RX_PORT gpioPortA -#define SL_IOSTREAM_USART_VCOM_RX_PIN 4 - - - -// [USART_SL_IOSTREAM_USART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/hardware/board/config/brd4113a_brd4002a/sl_joystick_config.h b/hardware/board/config/brd4113a_brd4002a/sl_joystick_config.h deleted file mode 100644 index 8cd6d8c470..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_joystick_config.h +++ /dev/null @@ -1,114 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Joystick Driver User Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_JOYSTICK_CONFIG_H -#define SL_JOYSTICK_CONFIG_H - -#include "em_gpio.h" - -// <<< Use Configuration Wizard in Context Menu >>> - -// Joystick Voltage value Configuration - -// Reference voltage value for analog Joystick signal -// Vref magnitude expressed in millivolts. As per Joystick Hardware on Wireless Pro Kit, Vref = AVDD = 3300 mV -// Default: 3300 -#define REFERENCE_VOLTAGE 3300 - -// Center position mV value -// Default: 3 -#define JOYSTICK_MV_C 3 - -// North position mV value -// Default: 2831 -#define JOYSTICK_MV_N 2831 - -// East position mV value -// Default: 2533 -#define JOYSTICK_MV_E 2533 - -// South position mV value -// Default: 1650 -#define JOYSTICK_MV_S 1650 - -// West position mV value -// Default: 1980 -#define JOYSTICK_MV_W 1980 - -// Joystick error mV value when enabled for Cardinal Directions only -// This value will not be used when joystick is enabled for secondary directions -// Default: 150 -#define JOYSTICK_MV_ERR_CARDINAL_ONLY 150 - -// Enable secondary directions -// Enables secondary directions (NW, NE, SW, SE) -// Note: Joystick Hardware on Wireless Pro Kit does not support Secondary directions -#ifndef ENABLE_SECONDARY_DIRECTIONS -#define ENABLE_SECONDARY_DIRECTIONS 1 -#endif -// Northeast position mV value -// Default: 2247 -#define JOYSTICK_MV_NE 2247 - -// Northwest position mV value -// Default: 1801 -#define JOYSTICK_MV_NW 1801 - -// Southeast position mV value -// Default: 1433 -#define JOYSTICK_MV_SE 1433 - -// Southwest position mV value -// Default: 1238 -#define JOYSTICK_MV_SW 1238 - -// Joystick error mV value when enabled for Cardinal and Secondary Directions -// Default: 75 -#define JOYSTICK_MV_ERR_CARDINAL_AND_SECONDARY 75 - -// end Joystick direction secondary directions selection - -// end Joystick Voltage value Configuration - -// Joystick signal sampling rate Configuration - -// Joystick signal sampling rate [samples/second] -// Sets the sampling rate for Joystick signal -// <50000=> 100 samples/second -// <5000=> 1000 samples/second -// <1000=> 5000 samples/second -// <500=> 10000 samples/second -// <200=> 25000 samples/second -// Default: 50000 -#define TIMER_CYCLES 50000 - -// end Joystick signal sampling rate Configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_JOYSTICK -// $[GPIO_SL_JOYSTICK] -#define SL_JOYSTICK_PORT gpioPortD -#define SL_JOYSTICK_PIN 2 - -// [GPIO_SL_JOYSTICK]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_JOYSTICK_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4002a/sl_mx25_flash_shutdown_eusart_config.h b/hardware/board/config/brd4113a_brd4002a/sl_mx25_flash_shutdown_eusart_config.h deleted file mode 100644 index 3d804d2bea..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_mx25_flash_shutdown_eusart_config.h +++ /dev/null @@ -1,51 +0,0 @@ -/***************************************************************************//** - * @file - * @brief SL_MX25_FLASH_SHUTDOWN_USART Config - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H -#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H - -// <<< sl:start pin_tool >>> -// {eusart signal=TX,RX,SCLK} SL_MX25_FLASH_SHUTDOWN -// [EUSART_SL_MX25_FLASH_SHUTDOWN] -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL EUSART0 -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 - -// EUSART0 TX on PB00 -#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortB -#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 0 - -// EUSART0 RX on PB01 -#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortB -#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 - -// EUSART0 SCLK on PB02 -#define SL_MX25_FLASH_SHUTDOWN_SCLK_PORT gpioPortB -#define SL_MX25_FLASH_SHUTDOWN_SCLK_PIN 2 - -// [EUSART_SL_MX25_FLASH_SHUTDOWN] - -// SL_MX25_FLASH_SHUTDOWN_CS - -// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] -#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortC -#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 2 - -// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4002a/sl_mx25_flash_shutdown_usart_config.h b/hardware/board/config/brd4113a_brd4002a/sl_mx25_flash_shutdown_usart_config.h deleted file mode 100644 index 06eb2da111..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_mx25_flash_shutdown_usart_config.h +++ /dev/null @@ -1,51 +0,0 @@ -/***************************************************************************//** - * @file - * @brief SL_MX25_FLASH_SHUTDOWN_USART Config - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H -#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H - -// <<< sl:start pin_tool >>> -// {usart signal=TX,RX,CLK} SL_MX25_FLASH_SHUTDOWN -// [USART_SL_MX25_FLASH_SHUTDOWN] -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL USART0 -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 - -// USART0 TX on PB00 -#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortB -#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 0 - -// USART0 RX on PB01 -#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortB -#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 - -// USART0 CLK on PB02 -#define SL_MX25_FLASH_SHUTDOWN_CLK_PORT gpioPortB -#define SL_MX25_FLASH_SHUTDOWN_CLK_PIN 2 - -// [USART_SL_MX25_FLASH_SHUTDOWN] - -// SL_MX25_FLASH_SHUTDOWN_CS - -// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] -#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortC -#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 2 - -// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4002a/sl_pwm_init_led0_config.h b/hardware/board/config/brd4113a_brd4002a/sl_pwm_init_led0_config.h deleted file mode 100644 index 332e1922a8..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_pwm_init_led0_config.h +++ /dev/null @@ -1,62 +0,0 @@ -/***************************************************************************//** - * @file - * @brief PWM Driver - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef PWM_INIT_LED0_CONFIG_H -#define PWM_INIT_LED0_CONFIG_H - -#ifdef __cplusplus -extern "C" { -#endif - -// <<< Use Configuration Wizard in Context Menu >>> - -// PWM configuration - -// PWM frequency [Hz] -// Default: 10000 -#define SL_PWM_LED0_FREQUENCY 10000 - -// Polarity -// Active high -// Active low -// Default: PWM_ACTIVE_HIGH -#define SL_PWM_LED0_POLARITY PWM_ACTIVE_LOW -// end pwm configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_PWM_LED0 -// $[TIMER_SL_PWM_LED0] -#define SL_PWM_LED0_PERIPHERAL TIMER0 -#define SL_PWM_LED0_PERIPHERAL_NO 0 - -#define SL_PWM_LED0_OUTPUT_CHANNEL 0 -// TIMER0 CC0 on PC05 -#define SL_PWM_LED0_OUTPUT_PORT gpioPortC -#define SL_PWM_LED0_OUTPUT_PIN 5 - -// [TIMER_SL_PWM_LED0]$ - -// <<< sl:end pin_tool >>> - -#ifdef __cplusplus -} -#endif - -#endif // PWM_INIT_LED0_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4002a/sl_pwm_init_led1_config.h b/hardware/board/config/brd4113a_brd4002a/sl_pwm_init_led1_config.h deleted file mode 100644 index 1618231e43..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_pwm_init_led1_config.h +++ /dev/null @@ -1,62 +0,0 @@ -/***************************************************************************//** - * @file - * @brief PWM Driver - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef PWM_INIT_LED1_CONFIG_H -#define PWM_INIT_LED1_CONFIG_H - -#ifdef __cplusplus -extern "C" { -#endif - -// <<< Use Configuration Wizard in Context Menu >>> - -// PWM configuration - -// PWM frequency [Hz] -// Default: 10000 -#define SL_PWM_LED1_FREQUENCY 10000 - -// Polarity -// Active high -// Active low -// Default: PWM_ACTIVE_HIGH -#define SL_PWM_LED1_POLARITY PWM_ACTIVE_LOW -// end pwm configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_PWM_LED1 -// $[TIMER_SL_PWM_LED1] -#define SL_PWM_LED1_PERIPHERAL TIMER1 -#define SL_PWM_LED1_PERIPHERAL_NO 1 - -#define SL_PWM_LED1_OUTPUT_CHANNEL 0 -// TIMER1 CC0 on PC04 -#define SL_PWM_LED1_OUTPUT_PORT gpioPortC -#define SL_PWM_LED1_OUTPUT_PIN 4 - -// [TIMER_SL_PWM_LED1]$ - -// <<< sl:end pin_tool >>> - -#ifdef __cplusplus -} -#endif - -#endif // PWM_INIT_LED1_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4002a/sl_rail_util_pa_config.h b/hardware/board/config/brd4113a_brd4002a/sl_rail_util_pa_config.h deleted file mode 100644 index a1a5fce586..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_rail_util_pa_config.h +++ /dev/null @@ -1,81 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Power Amplifier configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_RAIL_UTIL_PA_CONFIG_H -#define SL_RAIL_UTIL_PA_CONFIG_H - -#include "rail_types.h" - -// <<< Use Configuration Wizard in Context Menu >>> - -// PA Configuration -// Initial PA Power (deci-dBm, 100 = 10.0 dBm) -// Default: 100 -#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 - -// PA Ramp Time (microseconds) -// <0-65535:1> -// Default: 2 -#define SL_RAIL_UTIL_PA_RAMP_TIME_US 2 -// Milli-volts on PA supply pin (PA_VDD) -// <0-65535:1> -// Default: 3300 -#define SL_RAIL_UTIL_PA_VOLTAGE_MV 1800 -// 2.4 GHz PA Selection -// Highest Possible -// High Power (chip-specific) -// Low Power -// Disable -// Default: RAIL_TX_POWER_MODE_2P4GIG_HIGHEST -#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HIGHEST -// Sub-1 GHz PA Selection -// Disable -// Default: RAIL_TX_POWER_MODE_NONE -#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE -// - -// PA Curve Configuration -// Header file containing custom PA curves -// Default: "pa_curves_efr32.h" -#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" -// Header file containing PA curve types -// Default: "pa_curve_types_efr32.h" -#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" -// - -// PA Calibration Configuration -// Apply PA Calibration Factory Offset -// Default: 1 -#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 -// - -// <<< end of configuration section >>> - -#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4002a/sl_rail_util_pti_config.h b/hardware/board/config/brd4113a_brd4002a/sl_rail_util_pti_config.h deleted file mode 100644 index ce4bb0db27..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_rail_util_pti_config.h +++ /dev/null @@ -1,73 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Packet Trace Information configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_RAIL_UTIL_PTI_CONFIG_H -#define SL_RAIL_UTIL_PTI_CONFIG_H - -#include "rail_types.h" - -// <<< Use Configuration Wizard in Context Menu >>> -// PTI Configuration - -// PTI mode -// UART -// UART onewire -// SPI -// Disabled -// Default: RAIL_PTI_MODE_UART -#define SL_RAIL_UTIL_PTI_MODE RAIL_PTI_MODE_UART - -// PTI Baud Rate (Hertz) -// <147800-20000000:1> -// Default: 1600000 -#define SL_RAIL_UTIL_PTI_BAUD_RATE_HZ 1600000 - -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_RAIL_UTIL_PTI -// $[PTI_SL_RAIL_UTIL_PTI] -#define SL_RAIL_UTIL_PTI_PERIPHERAL PTI - -// PTI DOUT on PC00 -#define SL_RAIL_UTIL_PTI_DOUT_PORT gpioPortC -#define SL_RAIL_UTIL_PTI_DOUT_PIN 0 - -// PTI DFRAME on PC01 -#define SL_RAIL_UTIL_PTI_DFRAME_PORT gpioPortC -#define SL_RAIL_UTIL_PTI_DFRAME_PIN 1 - - -// [PTI_SL_RAIL_UTIL_PTI]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_RAIL_UTIL_PTI_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4002a/sl_simple_button_btn0_config.h b/hardware/board/config/brd4113a_brd4002a/sl_simple_button_btn0_config.h deleted file mode 100644 index aab8db6f10..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_simple_button_btn0_config.h +++ /dev/null @@ -1,45 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple Button Driver User Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_BUTTON_BTN0_CONFIG_H -#define SL_SIMPLE_BUTTON_BTN0_CONFIG_H - -#include "em_gpio.h" -#include "sl_simple_button.h" - -// <<< Use Configuration Wizard in Context Menu >>> - -// -// Interrupt -// Poll and Debounce -// Poll -// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT -#define SL_SIMPLE_BUTTON_BTN0_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_BUTTON_BTN0 -// $[GPIO_SL_SIMPLE_BUTTON_BTN0] -#define SL_SIMPLE_BUTTON_BTN0_PORT gpioPortC -#define SL_SIMPLE_BUTTON_BTN0_PIN 5 - -// [GPIO_SL_SIMPLE_BUTTON_BTN0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_BUTTON_BTN0_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4002a/sl_simple_button_btn1_config.h b/hardware/board/config/brd4113a_brd4002a/sl_simple_button_btn1_config.h deleted file mode 100644 index 2a9fde7738..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_simple_button_btn1_config.h +++ /dev/null @@ -1,45 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple Button Driver User Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_BUTTON_BTN1_CONFIG_H -#define SL_SIMPLE_BUTTON_BTN1_CONFIG_H - -#include "em_gpio.h" -#include "sl_simple_button.h" - -// <<< Use Configuration Wizard in Context Menu >>> - -// -// Interrupt -// Poll and Debounce -// Poll -// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT -#define SL_SIMPLE_BUTTON_BTN1_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_BUTTON_BTN1 -// $[GPIO_SL_SIMPLE_BUTTON_BTN1] -#define SL_SIMPLE_BUTTON_BTN1_PORT gpioPortC -#define SL_SIMPLE_BUTTON_BTN1_PIN 4 - -// [GPIO_SL_SIMPLE_BUTTON_BTN1]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_BUTTON_BTN1_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4002a/sl_simple_led_led0_config.h b/hardware/board/config/brd4113a_brd4002a/sl_simple_led_led0_config.h deleted file mode 100644 index 154539fe03..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_simple_led_led0_config.h +++ /dev/null @@ -1,44 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_LED_LED0_CONFIG_H -#define SL_SIMPLE_LED_LED0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple LED configuration -// -// Active low -// Active high -// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH -#define SL_SIMPLE_LED_LED0_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_LED_LED0 -// $[GPIO_SL_SIMPLE_LED_LED0] -#define SL_SIMPLE_LED_LED0_PORT gpioPortC -#define SL_SIMPLE_LED_LED0_PIN 5 - -// [GPIO_SL_SIMPLE_LED_LED0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_LED_LED0_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4002a/sl_simple_led_led1_config.h b/hardware/board/config/brd4113a_brd4002a/sl_simple_led_led1_config.h deleted file mode 100644 index 80d3300858..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_simple_led_led1_config.h +++ /dev/null @@ -1,44 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_LED_LED1_CONFIG_H -#define SL_SIMPLE_LED_LED1_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple LED configuration -// -// Active low -// Active high -// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH -#define SL_SIMPLE_LED_LED1_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_LED_LED1 -// $[GPIO_SL_SIMPLE_LED_LED1] -#define SL_SIMPLE_LED_LED1_PORT gpioPortC -#define SL_SIMPLE_LED_LED1_PIN 4 - -// [GPIO_SL_SIMPLE_LED_LED1]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_LED_LED1_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4113a_brd4002a/sl_uartdrv_eusart_exp_config.h deleted file mode 100644 index aa885fd1fa..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_uartdrv_eusart_exp_config.h +++ /dev/null @@ -1,100 +0,0 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV_EUSART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_UARTDRV_EUSART_EXP_CONFIG_H -#define SL_UARTDRV_EUSART_EXP_CONFIG_H - -#include "em_eusart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// EUSART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_EUSART_EXP_BAUDRATE 115200 - -// Low frequency mode -// True -// False -#define SL_UARTDRV_EUSART_EXP_LF_MODE false - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: eusartNoParity -#define SL_UARTDRV_EUSART_EXP_PARITY eusartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: eusartStopbits1 -#define SL_UARTDRV_EUSART_EXP_STOP_BITS eusartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHw -#define SL_UARTDRV_EUSART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Oversampling disabled -// Default: eusartOVS16 -#define SL_UARTDRV_EUSART_EXP_OVERSAMPLING eusartOVS16 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// False -// True -// Default: eusartMajorityVoteEnable -#define SL_UARTDRV_EUSART_EXP_MVDIS eusartMajorityVoteEnable - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_EUSART_EXP_RX_BUFFER_SIZE 6 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_EUSART_EXP_TX_BUFFER_SIZE 6 -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_EUSART_EXP -// $[EUSART_SL_UARTDRV_EUSART_EXP] -#define SL_UARTDRV_EUSART_EXP_PERIPHERAL EUSART0 -#define SL_UARTDRV_EUSART_EXP_PERIPHERAL_NO 0 - -// EUSART0 TX on PA00 -#define SL_UARTDRV_EUSART_EXP_TX_PORT gpioPortA -#define SL_UARTDRV_EUSART_EXP_TX_PIN 0 - -// EUSART0 RX on PA04 -#define SL_UARTDRV_EUSART_EXP_RX_PORT gpioPortA -#define SL_UARTDRV_EUSART_EXP_RX_PIN 4 - - - -// [EUSART_SL_UARTDRV_EUSART_EXP]$ -// <<< sl:end pin_tool >>> -#endif // SL_UARTDRV_EUSART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4002a/sl_uartdrv_eusart_vcom_config.h b/hardware/board/config/brd4113a_brd4002a/sl_uartdrv_eusart_vcom_config.h deleted file mode 100644 index 8ae6362907..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_uartdrv_eusart_vcom_config.h +++ /dev/null @@ -1,100 +0,0 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV_EUSART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_UARTDRV_EUSART_VCOM_CONFIG_H -#define SL_UARTDRV_EUSART_VCOM_CONFIG_H - -#include "em_eusart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// EUSART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_EUSART_VCOM_BAUDRATE 115200 - -// Low frequency mode -// True -// False -#define SL_UARTDRV_EUSART_VCOM_LF_MODE false - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: eusartNoParity -#define SL_UARTDRV_EUSART_VCOM_PARITY eusartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: eusartStopbits1 -#define SL_UARTDRV_EUSART_VCOM_STOP_BITS eusartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHw -#define SL_UARTDRV_EUSART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlNone - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Oversampling disabled -// Default: eusartOVS16 -#define SL_UARTDRV_EUSART_VCOM_OVERSAMPLING eusartOVS16 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// False -// True -// Default: eusartMajorityVoteEnable -#define SL_UARTDRV_EUSART_VCOM_MVDIS eusartMajorityVoteEnable - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_EUSART_VCOM_RX_BUFFER_SIZE 6 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_EUSART_VCOM_TX_BUFFER_SIZE 6 -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_EUSART_VCOM -// $[EUSART_SL_UARTDRV_EUSART_VCOM] -#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL EUSART0 -#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL_NO 0 - -// EUSART0 TX on PA00 -#define SL_UARTDRV_EUSART_VCOM_TX_PORT gpioPortA -#define SL_UARTDRV_EUSART_VCOM_TX_PIN 0 - -// EUSART0 RX on PA04 -#define SL_UARTDRV_EUSART_VCOM_RX_PORT gpioPortA -#define SL_UARTDRV_EUSART_VCOM_RX_PIN 4 - - - -// [EUSART_SL_UARTDRV_EUSART_VCOM]$ -// <<< sl:end pin_tool >>> -#endif // SL_UARTDRV_EUSART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4002a/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4113a_brd4002a/sl_uartdrv_usart_exp_config.h deleted file mode 100644 index d147c8e264..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_uartdrv_usart_exp_config.h +++ /dev/null @@ -1,95 +0,0 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV_USART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_UARTDRV_USART_EXP_CONFIG_H -#define SL_UARTDRV_USART_EXP_CONFIG_H - -#include "em_usart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// UART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_USART_EXP_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_UARTDRV_USART_EXP_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_UARTDRV_USART_EXP_STOP_BITS usartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHw -#define SL_UARTDRV_USART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Default: usartOVS16 -#define SL_UARTDRV_USART_EXP_OVERSAMPLING usartOVS4 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// True -// False -#define SL_UARTDRV_USART_EXP_MVDIS false - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_USART_EXP_RX_BUFFER_SIZE 6 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_USART_EXP_TX_BUFFER_SIZE 6 - -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_USART_EXP -// $[USART_SL_UARTDRV_USART_EXP] -#define SL_UARTDRV_USART_EXP_PERIPHERAL USART0 -#define SL_UARTDRV_USART_EXP_PERIPHERAL_NO 0 - -// USART0 TX on PA00 -#define SL_UARTDRV_USART_EXP_TX_PORT gpioPortA -#define SL_UARTDRV_USART_EXP_TX_PIN 0 - -// USART0 RX on PA04 -#define SL_UARTDRV_USART_EXP_RX_PORT gpioPortA -#define SL_UARTDRV_USART_EXP_RX_PIN 4 - - - -// [USART_SL_UARTDRV_USART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif // SL_UARTDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4002a/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd4113a_brd4002a/sl_uartdrv_usart_vcom_config.h deleted file mode 100644 index 6f63b9a2ea..0000000000 --- a/hardware/board/config/brd4113a_brd4002a/sl_uartdrv_usart_vcom_config.h +++ /dev/null @@ -1,95 +0,0 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV_USART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H -#define SL_UARTDRV_USART_VCOM_CONFIG_H - -#include "em_usart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// UART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHw -#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlNone - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Default: usartOVS16 -#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// True -// False -#define SL_UARTDRV_USART_VCOM_MVDIS false - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 6 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 6 - -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_USART_VCOM -// $[USART_SL_UARTDRV_USART_VCOM] -#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART0 -#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 0 - -// USART0 TX on PA00 -#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortA -#define SL_UARTDRV_USART_VCOM_TX_PIN 0 - -// USART0 RX on PA04 -#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortA -#define SL_UARTDRV_USART_VCOM_RX_PIN 4 - - - -// [USART_SL_UARTDRV_USART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4166a/iot_pwm_cfg_exp.h b/hardware/board/config/brd4166a/iot_pwm_cfg_exp.h new file mode 100644 index 0000000000..dcdf696b00 --- /dev/null +++ b/hardware/board/config/brd4166a/iot_pwm_cfg_exp.h @@ -0,0 +1,79 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_EXP_H_ +#define _IOT_PWM_CFG_EXP_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_EXP_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_EXP +// $[TIMER_IOT_PWM_CFG_EXP] +#define IOT_PWM_CFG_EXP_PERIPHERAL WTIMER0 +#define IOT_PWM_CFG_EXP_PERIPHERAL_NO 0 + +// WTIMER0 CC0 on PA6 +#define IOT_PWM_CFG_EXP_CC0_PORT gpioPortA +#define IOT_PWM_CFG_EXP_CC0_PIN 6 +#define IOT_PWM_CFG_EXP_CC0_LOC 6 + + + +// [TIMER_IOT_PWM_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4166a/sl_simple_rgb_pwm_led_inst0_config.h b/hardware/board/config/brd4166a/sl_simple_rgb_pwm_led_inst0_config.h deleted file mode 100644 index 4eb29f872e..0000000000 --- a/hardware/board/config/brd4166a/sl_simple_rgb_pwm_led_inst0_config.h +++ /dev/null @@ -1,87 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_INST0_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_HIGH - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_HIGH - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_HIGH -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_INST0 -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_INST0] -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL TIMER0 -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL_NO 0 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_CHANNEL 0 -// TIMER0 CC0 on PD11 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PIN 11 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_LOC 19 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_CHANNEL 1 -// TIMER0 CC1 on PD12 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PIN 12 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_LOC 19 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_CHANNEL 2 -// TIMER0 CC2 on PD13 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PIN 13 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_LOC 19 - -// [TIMER_SL_SIMPLE_RGB_PWM_LED_INST0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H diff --git a/hardware/board/config/brd4166a/sl_simple_rgb_pwm_led_rgb_led0_config.h b/hardware/board/config/brd4166a/sl_simple_rgb_pwm_led_rgb_led0_config.h new file mode 100644 index 0000000000..50919cc898 --- /dev/null +++ b/hardware/board/config/brd4166a/sl_simple_rgb_pwm_led_rgb_led0_config.h @@ -0,0 +1,87 @@ +/***************************************************************************//** + * @file + * @brief Simple RGB PWM Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple RGB PWM LED Configuration +// PWM frequency [Hz] +// Sets the frequency of the PWM signal +// 0 = Don't care +// Default: 10000 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_FREQUENCY 10000 + +// PWM resolution <2-65536> +// Specifies the PWM (dimming) resolution. I.e. if you want a +// dimming resolution that takes the input values from 0 to 99, +// set this value to 100 +// Default: 256 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RESOLUTION 256 + +// Red LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_HIGH + +// Green LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_HIGH + +// Blue LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_RGB_PWM_LED_RGB_LED0 +// $[TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0] +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL TIMER0 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL_NO 0 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_CHANNEL 0 +// TIMER0 CC0 on PD11 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PIN 11 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_LOC 19 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_CHANNEL 1 +// TIMER0 CC1 on PD12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PIN 12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_LOC 19 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_CHANNEL 2 +// TIMER0 CC2 on PD13 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PIN 13 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_LOC 19 + +// [TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H diff --git a/hardware/board/config/brd4166c/btl_ezsp_gpio_activation_cfg.h b/hardware/board/config/brd4166c/btl_ezsp_gpio_activation_cfg.h new file mode 100644 index 0000000000..ef925855a7 --- /dev/null +++ b/hardware/board/config/brd4166c/btl_ezsp_gpio_activation_cfg.h @@ -0,0 +1,52 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader EZSP GPIO Activation + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_EZSP_GPIO_ACTIVATION_CONFIG_H +#define BTL_EZSP_GPIO_ACTIVATION_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Properties of SPI NCP + +// Active state +// Low +// High +// Default: LOW +// Enter firmware upgrade mode if GPIO pin has this state +#define SL_EZSP_GPIO_ACTIVATION_POLARITY LOW + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_EZSPSPI_HOST_INT +// $[GPIO_SL_EZSPSPI_HOST_INT] +#define SL_EZSPSPI_HOST_INT_PORT gpioPortA +#define SL_EZSPSPI_HOST_INT_PIN 6 + +// [GPIO_SL_EZSPSPI_HOST_INT]$ + +// SL_EZSPSPI_WAKE_INT +// $[GPIO_SL_EZSPSPI_WAKE_INT] +#define SL_EZSPSPI_WAKE_INT_PORT gpioPortA +#define SL_EZSPSPI_WAKE_INT_PIN 7 + +// [GPIO_SL_EZSPSPI_WAKE_INT]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_EZSP_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4166c/btl_gpio_activation_cfg.h b/hardware/board/config/brd4166c/btl_gpio_activation_cfg.h new file mode 100644 index 0000000000..e40f137046 --- /dev/null +++ b/hardware/board/config/brd4166c/btl_gpio_activation_cfg.h @@ -0,0 +1,49 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader GPIO Activation + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_GPIO_ACTIVATION_CONFIG_H +#define BTL_GPIO_ACTIVATION_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Properties of Bootloader Entry + + +// Active state +// Low +// High +// Default: LOW +// Enter firmware upgrade mode if GPIO pin has this state +#define SL_GPIO_ACTIVATION_POLARITY LOW + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BTL_BUTTON + +// $[GPIO_SL_BTL_BUTTON] +#define SL_BTL_BUTTON_PORT gpioPortD +#define SL_BTL_BUTTON_PIN 14 + +// [GPIO_SL_BTL_BUTTON]$ + +// <<< sl:end pin_tool >>> + + +#endif // BTL_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4166c/btl_spi_controller_usart_driver_cfg.h b/hardware/board/config/brd4166c/btl_spi_controller_usart_driver_cfg.h new file mode 100644 index 0000000000..454bedeeb7 --- /dev/null +++ b/hardware/board/config/brd4166c/btl_spi_controller_usart_driver_cfg.h @@ -0,0 +1,72 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Controller Usart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H +#define BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Controller USART Driver + +// Frequency +// Default: 6400000 +#define SL_USART_EXTFLASH_FREQUENCY 6400000 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_USART_EXTFLASH +// $[USART_SL_USART_EXTFLASH] +#define SL_USART_EXTFLASH_PERIPHERAL USART2 +#define SL_USART_EXTFLASH_PERIPHERAL_NO 2 + +// USART2 TX on PK0 +#define SL_USART_EXTFLASH_TX_PORT gpioPortK +#define SL_USART_EXTFLASH_TX_PIN 0 +#define SL_USART_EXTFLASH_TX_LOC 29 + +// USART2 RX on PK2 +#define SL_USART_EXTFLASH_RX_PORT gpioPortK +#define SL_USART_EXTFLASH_RX_PIN 2 +#define SL_USART_EXTFLASH_RX_LOC 30 + +// USART2 CLK on PF7 +#define SL_USART_EXTFLASH_CLK_PORT gpioPortF +#define SL_USART_EXTFLASH_CLK_PIN 7 +#define SL_USART_EXTFLASH_CLK_LOC 18 + +// USART2 CS on PK1 +#define SL_USART_EXTFLASH_CS_PORT gpioPortK +#define SL_USART_EXTFLASH_CS_PIN 1 +#define SL_USART_EXTFLASH_CS_LOC 27 + +// [USART_SL_USART_EXTFLASH]$ + +// SL_EXTFLASH_WP +// $[GPIO_SL_EXTFLASH_WP] + +// [GPIO_SL_EXTFLASH_WP]$ + +// SL_EXTFLASH_HOLD +// $[GPIO_SL_EXTFLASH_HOLD] + +// [GPIO_SL_EXTFLASH_HOLD]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_CONTROLLER_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4166c/btl_spi_peripheral_usart_driver_cfg.h b/hardware/board/config/brd4166c/btl_spi_peripheral_usart_driver_cfg.h new file mode 100644 index 0000000000..d2e0ce9e77 --- /dev/null +++ b/hardware/board/config/brd4166c/btl_spi_peripheral_usart_driver_cfg.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Peripheral Usart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H +#define BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Peripheral Usart Driver + +// Receive buffer size:[0-2048] <0-2048> +// Default: 300 +#define SL_SPI_PERIPHERAL_USART_RX_BUFFER_SIZE 300 + +// Transmit buffer size:[0-2048] <0-2048> +// Default: 50 +#define SL_SPI_PERIPHERAL_USART_TX_BUFFER_SIZE 50 + +// LDMA channel for SPI RX:[0-1] <0-1> +// Default: 0 +#define SL_SPI_PERIPHERAL_USART_LDMA_RX_CHANNEL 0 + +// LDMA channel for SPI TX:[0-1] <0-1> +// Default: 1 +#define SL_SPI_PERIPHERAL_USART_LDMA_TX_CHANNEL 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_USART_SPINCP + +// $[USART_SL_USART_SPINCP] +#define SL_USART_SPINCP_PERIPHERAL USART2 +#define SL_USART_SPINCP_PERIPHERAL_NO 2 + +// USART2 TX on PK0 +#define SL_USART_SPINCP_TX_PORT gpioPortK +#define SL_USART_SPINCP_TX_PIN 0 +#define SL_USART_SPINCP_TX_LOC 29 + +// USART2 RX on PK2 +#define SL_USART_SPINCP_RX_PORT gpioPortK +#define SL_USART_SPINCP_RX_PIN 2 +#define SL_USART_SPINCP_RX_LOC 30 + +// USART2 CS on PA5 +#define SL_USART_SPINCP_CS_PORT gpioPortA +#define SL_USART_SPINCP_CS_PIN 5 +#define SL_USART_SPINCP_CS_LOC 29 + +// USART2 CLK on PF7 +#define SL_USART_SPINCP_CLK_PORT gpioPortF +#define SL_USART_SPINCP_CLK_PIN 7 +#define SL_USART_SPINCP_CLK_LOC 18 + +// [USART_SL_USART_SPINCP]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_PERIPHERAL_USART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4166c/btl_uart_driver_cfg.h b/hardware/board/config/brd4166c/btl_uart_driver_cfg.h new file mode 100644 index 0000000000..14b2f008f1 --- /dev/null +++ b/hardware/board/config/brd4166c/btl_uart_driver_cfg.h @@ -0,0 +1,91 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Uart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_UART_DRIVER_CONFIG_H +#define BTL_UART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_UART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_UART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_UART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_UART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_UART +// $[USART_SL_SERIAL_UART] +#define SL_SERIAL_UART_PERIPHERAL USART0 +#define SL_SERIAL_UART_PERIPHERAL_NO 0 + +// USART0 TX on PA0 +#define SL_SERIAL_UART_TX_PORT gpioPortA +#define SL_SERIAL_UART_TX_PIN 0 +#define SL_SERIAL_UART_TX_LOC 0 + +// USART0 RX on PA1 +#define SL_SERIAL_UART_RX_PORT gpioPortA +#define SL_SERIAL_UART_RX_PIN 1 +#define SL_SERIAL_UART_RX_LOC 0 + +// USART0 CTS on PA2 +#define SL_SERIAL_UART_CTS_PORT gpioPortA +#define SL_SERIAL_UART_CTS_PIN 2 +#define SL_SERIAL_UART_CTS_LOC 30 + +// USART0 RTS on PA3 +#define SL_SERIAL_UART_RTS_PORT gpioPortA +#define SL_SERIAL_UART_RTS_PIN 3 +#define SL_SERIAL_UART_RTS_LOC 30 + +// [USART_SL_SERIAL_UART]$ + + + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] + +// [GPIO_SL_VCOM_ENABLE]$ + + +// <<< sl:end pin_tool >>> + +#endif // BTL_UART_DRIVER_CONFIG_H \ No newline at end of file diff --git a/hardware/board/config/brd4166c/iot_flash_cfg_exp.h b/hardware/board/config/brd4166c/iot_flash_cfg_exp.h new file mode 100644 index 0000000000..d23854dc02 --- /dev/null +++ b/hardware/board/config/brd4166c/iot_flash_cfg_exp.h @@ -0,0 +1,140 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_EXP_H_ +#define _IOT_FLASH_CFG_EXP_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_EXP_INST_NUM 0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_EXP_INST_TYPE 1 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_EXP_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_EXP_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_EXP_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_EXP_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_EXP_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_EXP_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_EXP_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_EXP_SPI +// $[USART_IOT_FLASH_CFG_EXP_SPI] +#define IOT_FLASH_CFG_EXP_SPI_PERIPHERAL USART2 +#define IOT_FLASH_CFG_EXP_SPI_PERIPHERAL_NO 2 + +// USART2 TX on PK0 +#define IOT_FLASH_CFG_EXP_SPI_TX_PORT gpioPortK +#define IOT_FLASH_CFG_EXP_SPI_TX_PIN 0 +#define IOT_FLASH_CFG_EXP_SPI_TX_LOC 29 + +// USART2 RX on PK2 +#define IOT_FLASH_CFG_EXP_SPI_RX_PORT gpioPortK +#define IOT_FLASH_CFG_EXP_SPI_RX_PIN 2 +#define IOT_FLASH_CFG_EXP_SPI_RX_LOC 30 + +// USART2 CLK on PF7 +#define IOT_FLASH_CFG_EXP_SPI_CLK_PORT gpioPortF +#define IOT_FLASH_CFG_EXP_SPI_CLK_PIN 7 +#define IOT_FLASH_CFG_EXP_SPI_CLK_LOC 18 + +// USART2 CS on PA5 +#define IOT_FLASH_CFG_EXP_SPI_CS_PORT gpioPortA +#define IOT_FLASH_CFG_EXP_SPI_CS_PIN 5 +#define IOT_FLASH_CFG_EXP_SPI_CS_LOC 29 + +// [USART_IOT_FLASH_CFG_EXP_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4109a_brd4002a/iot_flash_cfg_msc.h b/hardware/board/config/brd4166c/iot_flash_cfg_msc.h similarity index 100% rename from hardware/board/config/brd4109a_brd4002a/iot_flash_cfg_msc.h rename to hardware/board/config/brd4166c/iot_flash_cfg_msc.h diff --git a/hardware/board/config/brd4166c/iot_flash_cfg_spiflash.h b/hardware/board/config/brd4166c/iot_flash_cfg_spiflash.h new file mode 100644 index 0000000000..7f5ed99db2 --- /dev/null +++ b/hardware/board/config/brd4166c/iot_flash_cfg_spiflash.h @@ -0,0 +1,140 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_SPIFLASH_H_ +#define _IOT_FLASH_CFG_SPIFLASH_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_SPIFLASH_INST_NUM 0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_SPIFLASH_INST_TYPE 1 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_SPIFLASH_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_SPIFLASH_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_SPIFLASH_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_SPIFLASH_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_SPIFLASH_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_SPIFLASH_SPI +// $[USART_IOT_FLASH_CFG_SPIFLASH_SPI] +#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL USART2 +#define IOT_FLASH_CFG_SPIFLASH_SPI_PERIPHERAL_NO 2 + +// USART2 TX on PK0 +#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PORT gpioPortK +#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_PIN 0 +#define IOT_FLASH_CFG_SPIFLASH_SPI_TX_LOC 29 + +// USART2 RX on PK2 +#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PORT gpioPortK +#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_PIN 2 +#define IOT_FLASH_CFG_SPIFLASH_SPI_RX_LOC 30 + +// USART2 CLK on PF7 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PORT gpioPortF +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_PIN 7 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CLK_LOC 18 + +// USART2 CS on PK1 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PORT gpioPortK +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_PIN 1 +#define IOT_FLASH_CFG_SPIFLASH_SPI_CS_LOC 27 + +// [USART_IOT_FLASH_CFG_SPIFLASH_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_SPIFLASH_H_ */ diff --git a/hardware/board/config/brd4166c/iot_i2c_cfg_exp.h b/hardware/board/config/brd4166c/iot_i2c_cfg_exp.h new file mode 100644 index 0000000000..dbd952349e --- /dev/null +++ b/hardware/board/config/brd4166c/iot_i2c_cfg_exp.h @@ -0,0 +1,110 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_EXP_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_EXP_H_ +#define _IOT_I2C_CFG_EXP_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_EXP_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_EXP_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_EXP_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_EXP_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_EXP_ENABLE +// $[GPIO_IOT_I2C_CFG_EXP_ENABLE] +#define IOT_I2C_CFG_EXP_ENABLE_PORT gpioPortA +#define IOT_I2C_CFG_EXP_ENABLE_PIN 6 + +// [GPIO_IOT_I2C_CFG_EXP_ENABLE]$ + +// IOT_I2C_CFG_EXP +// $[I2C_IOT_I2C_CFG_EXP] +#define IOT_I2C_CFG_EXP_PERIPHERAL I2C0 +#define IOT_I2C_CFG_EXP_PERIPHERAL_NO 0 + +// I2C0 SCL on PC11 +#define IOT_I2C_CFG_EXP_SCL_PORT gpioPortC +#define IOT_I2C_CFG_EXP_SCL_PIN 11 +#define IOT_I2C_CFG_EXP_SCL_LOC 15 + +// I2C0 SDA on PC10 +#define IOT_I2C_CFG_EXP_SDA_PORT gpioPortC +#define IOT_I2C_CFG_EXP_SDA_PIN 10 +#define IOT_I2C_CFG_EXP_SDA_LOC 15 + +// [I2C_IOT_I2C_CFG_EXP]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4166c/iot_i2c_cfg_sensor.h b/hardware/board/config/brd4166c/iot_i2c_cfg_sensor.h new file mode 100644 index 0000000000..9294a53074 --- /dev/null +++ b/hardware/board/config/brd4166c/iot_i2c_cfg_sensor.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_SENSOR_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_SENSOR_H_ +#define _IOT_I2C_CFG_SENSOR_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_SENSOR_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_SENSOR_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_SENSOR_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_SENSOR_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_SENSOR_ENABLE +// $[GPIO_IOT_I2C_CFG_SENSOR_ENABLE] + +// [GPIO_IOT_I2C_CFG_SENSOR_ENABLE]$ + +// IOT_I2C_CFG_SENSOR +// $[I2C_IOT_I2C_CFG_SENSOR] +#define IOT_I2C_CFG_SENSOR_PERIPHERAL I2C1 +#define IOT_I2C_CFG_SENSOR_PERIPHERAL_NO 1 + +// I2C1 SCL on PC5 +#define IOT_I2C_CFG_SENSOR_SCL_PORT gpioPortC +#define IOT_I2C_CFG_SENSOR_SCL_PIN 5 +#define IOT_I2C_CFG_SENSOR_SCL_LOC 17 + +// I2C1 SDA on PC4 +#define IOT_I2C_CFG_SENSOR_SDA_PORT gpioPortC +#define IOT_I2C_CFG_SENSOR_SDA_PIN 4 +#define IOT_I2C_CFG_SENSOR_SDA_LOC 17 + +// [I2C_IOT_I2C_CFG_SENSOR]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_SENSOR_H_ */ diff --git a/hardware/board/config/brd4166c/iot_i2c_cfg_sensor_env.h b/hardware/board/config/brd4166c/iot_i2c_cfg_sensor_env.h new file mode 100644 index 0000000000..adc18f91e6 --- /dev/null +++ b/hardware/board/config/brd4166c/iot_i2c_cfg_sensor_env.h @@ -0,0 +1,108 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_SENSOR_ENV_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_SENSOR_ENV_H_ +#define _IOT_I2C_CFG_SENSOR_ENV_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_SENSOR_ENV_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_SENSOR_ENV_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_SENSOR_ENV_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_SENSOR_ENV_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_SENSOR_ENV_ENABLE +// $[GPIO_IOT_I2C_CFG_SENSOR_ENV_ENABLE] + +// [GPIO_IOT_I2C_CFG_SENSOR_ENV_ENABLE]$ + +// IOT_I2C_CFG_SENSOR_ENV +// $[I2C_IOT_I2C_CFG_SENSOR_ENV] +#define IOT_I2C_CFG_SENSOR_ENV_PERIPHERAL I2C1 +#define IOT_I2C_CFG_SENSOR_ENV_PERIPHERAL_NO 1 + +// I2C1 SCL on PC5 +#define IOT_I2C_CFG_SENSOR_ENV_SCL_PORT gpioPortC +#define IOT_I2C_CFG_SENSOR_ENV_SCL_PIN 5 +#define IOT_I2C_CFG_SENSOR_ENV_SCL_LOC 17 + +// I2C1 SDA on PC4 +#define IOT_I2C_CFG_SENSOR_ENV_SDA_PORT gpioPortC +#define IOT_I2C_CFG_SENSOR_ENV_SDA_PIN 4 +#define IOT_I2C_CFG_SENSOR_ENV_SDA_LOC 17 + +// [I2C_IOT_I2C_CFG_SENSOR_ENV]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_SENSOR_ENV_H_ */ diff --git a/hardware/board/config/brd4166c/iot_i2c_cfg_test.h b/hardware/board/config/brd4166c/iot_i2c_cfg_test.h new file mode 100644 index 0000000000..21598b5275 --- /dev/null +++ b/hardware/board/config/brd4166c/iot_i2c_cfg_test.h @@ -0,0 +1,110 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_TEST_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_TEST_H_ +#define _IOT_I2C_CFG_TEST_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_TEST_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_TEST_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_TEST_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_TEST_ACCEPT_NACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_TEST_ENABLE +// $[GPIO_IOT_I2C_CFG_TEST_ENABLE] +#define IOT_I2C_CFG_TEST_ENABLE_PORT gpioPortA +#define IOT_I2C_CFG_TEST_ENABLE_PIN 6 + +// [GPIO_IOT_I2C_CFG_TEST_ENABLE]$ + +// IOT_I2C_CFG_TEST +// $[I2C_IOT_I2C_CFG_TEST] +#define IOT_I2C_CFG_TEST_PERIPHERAL I2C0 +#define IOT_I2C_CFG_TEST_PERIPHERAL_NO 0 + +// I2C0 SCL on PC11 +#define IOT_I2C_CFG_TEST_SCL_PORT gpioPortC +#define IOT_I2C_CFG_TEST_SCL_PIN 11 +#define IOT_I2C_CFG_TEST_SCL_LOC 15 + +// I2C0 SDA on PC10 +#define IOT_I2C_CFG_TEST_SDA_PORT gpioPortC +#define IOT_I2C_CFG_TEST_SDA_PIN 10 +#define IOT_I2C_CFG_TEST_SDA_LOC 15 + +// [I2C_IOT_I2C_CFG_TEST]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_TEST_H_ */ diff --git a/hardware/board/config/brd4166c/iot_pwm_cfg_exp.h b/hardware/board/config/brd4166c/iot_pwm_cfg_exp.h new file mode 100644 index 0000000000..dcdf696b00 --- /dev/null +++ b/hardware/board/config/brd4166c/iot_pwm_cfg_exp.h @@ -0,0 +1,79 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_EXP_H_ +#define _IOT_PWM_CFG_EXP_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_EXP_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_EXP +// $[TIMER_IOT_PWM_CFG_EXP] +#define IOT_PWM_CFG_EXP_PERIPHERAL WTIMER0 +#define IOT_PWM_CFG_EXP_PERIPHERAL_NO 0 + +// WTIMER0 CC0 on PA6 +#define IOT_PWM_CFG_EXP_CC0_PORT gpioPortA +#define IOT_PWM_CFG_EXP_CC0_PIN 6 +#define IOT_PWM_CFG_EXP_CC0_LOC 6 + + + +// [TIMER_IOT_PWM_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4166c/iot_pwm_cfg_led0.h b/hardware/board/config/brd4166c/iot_pwm_cfg_led0.h new file mode 100644 index 0000000000..9b9be67d5e --- /dev/null +++ b/hardware/board/config/brd4166c/iot_pwm_cfg_led0.h @@ -0,0 +1,79 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED0_H_ +#define _IOT_PWM_CFG_LED0_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED0_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED0 +// $[TIMER_IOT_PWM_CFG_LED0] +#define IOT_PWM_CFG_LED0_PERIPHERAL WTIMER0 +#define IOT_PWM_CFG_LED0_PERIPHERAL_NO 0 + + +// WTIMER0 CC1 on PD8 +#define IOT_PWM_CFG_LED0_CC1_PORT gpioPortD +#define IOT_PWM_CFG_LED0_CC1_PIN 8 +#define IOT_PWM_CFG_LED0_CC1_LOC 30 + + +// [TIMER_IOT_PWM_CFG_LED0]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED0_H_ */ diff --git a/hardware/board/config/brd4166c/iot_spi_cfg_exp.h b/hardware/board/config/brd4166c/iot_spi_cfg_exp.h new file mode 100644 index 0000000000..12dd294e93 --- /dev/null +++ b/hardware/board/config/brd4166c/iot_spi_cfg_exp.h @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file iot_spi_cfg_inst.h + * @brief Common I/O SPI instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_SPI_CFG_EXP_H_ +#define _IOT_SPI_CFG_EXP_H_ + +/******************************************************************************* + * SPI Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI General Options + +// Instance number +// Instance number used when iot_spi_open() is called. +// Default: 0 +#define IOT_SPI_CFG_EXP_INST_NUM 0 + +// Default SPI bitrate +// Default: 1000000 +#define IOT_SPI_CFG_EXP_DEFAULT_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_SPI_CFG_EXP_DEFAULT_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_SPI_CFG_EXP_DEFAULT_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_SPI_CFG_EXP_DEFAULT_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_SPI_CFG_EXP_DEFAULT_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_SPI_CFG_EXP_DEFAULT_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_SPI_CFG_EXP_DEFAULT_SLAVE_START_MODE spidrvSlaveStartImmediate + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_SPI_CFG_EXP_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_SPI_CFG_EXP +// $[USART_IOT_SPI_CFG_EXP] +#define IOT_SPI_CFG_EXP_PERIPHERAL USART2 +#define IOT_SPI_CFG_EXP_PERIPHERAL_NO 2 + +// USART2 TX on PK0 +#define IOT_SPI_CFG_EXP_TX_PORT gpioPortK +#define IOT_SPI_CFG_EXP_TX_PIN 0 +#define IOT_SPI_CFG_EXP_TX_LOC 29 + +// USART2 RX on PK2 +#define IOT_SPI_CFG_EXP_RX_PORT gpioPortK +#define IOT_SPI_CFG_EXP_RX_PIN 2 +#define IOT_SPI_CFG_EXP_RX_LOC 30 + +// USART2 CLK on PF7 +#define IOT_SPI_CFG_EXP_CLK_PORT gpioPortF +#define IOT_SPI_CFG_EXP_CLK_PIN 7 +#define IOT_SPI_CFG_EXP_CLK_LOC 18 + +// USART2 CS on PA5 +#define IOT_SPI_CFG_EXP_CS_PORT gpioPortA +#define IOT_SPI_CFG_EXP_CS_PIN 5 +#define IOT_SPI_CFG_EXP_CS_LOC 29 + +// [USART_IOT_SPI_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_SPI_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4166c/iot_spi_cfg_loopback.h b/hardware/board/config/brd4166c/iot_spi_cfg_loopback.h new file mode 100644 index 0000000000..19db328f42 --- /dev/null +++ b/hardware/board/config/brd4166c/iot_spi_cfg_loopback.h @@ -0,0 +1,132 @@ +/***************************************************************************//** + * @file iot_spi_cfg_inst.h + * @brief Common I/O SPI instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_SPI_CFG_LOOPBACK_H_ +#define _IOT_SPI_CFG_LOOPBACK_H_ + +/******************************************************************************* + * SPI Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI General Options + +// Instance number +// Instance number used when iot_spi_open() is called. +// Default: 0 +#define IOT_SPI_CFG_LOOPBACK_INST_NUM 0 + +// Default SPI bitrate +// Default: 1000000 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_SPI_CFG_LOOPBACK_DEFAULT_SLAVE_START_MODE spidrvSlaveStartImmediate + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_SPI_CFG_LOOPBACK_LOOPBACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_SPI_CFG_LOOPBACK +// $[USART_IOT_SPI_CFG_LOOPBACK] +#define IOT_SPI_CFG_LOOPBACK_PERIPHERAL USART2 +#define IOT_SPI_CFG_LOOPBACK_PERIPHERAL_NO 2 + +// USART2 TX on PK0 +#define IOT_SPI_CFG_LOOPBACK_TX_PORT gpioPortK +#define IOT_SPI_CFG_LOOPBACK_TX_PIN 0 +#define IOT_SPI_CFG_LOOPBACK_TX_LOC 29 + +// USART2 RX on PK2 +#define IOT_SPI_CFG_LOOPBACK_RX_PORT gpioPortK +#define IOT_SPI_CFG_LOOPBACK_RX_PIN 2 +#define IOT_SPI_CFG_LOOPBACK_RX_LOC 30 + +// USART2 CLK on PF7 +#define IOT_SPI_CFG_LOOPBACK_CLK_PORT gpioPortF +#define IOT_SPI_CFG_LOOPBACK_CLK_PIN 7 +#define IOT_SPI_CFG_LOOPBACK_CLK_LOC 18 + +// USART2 CS on PA5 +#define IOT_SPI_CFG_LOOPBACK_CS_PORT gpioPortA +#define IOT_SPI_CFG_LOOPBACK_CS_PIN 5 +#define IOT_SPI_CFG_LOOPBACK_CS_LOC 29 + +// [USART_IOT_SPI_CFG_LOOPBACK]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_SPI_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4166c/iot_uart_cfg_exp.h b/hardware/board/config/brd4166c/iot_uart_cfg_exp.h new file mode 100644 index 0000000000..e8f376ddca --- /dev/null +++ b/hardware/board/config/brd4166c/iot_uart_cfg_exp.h @@ -0,0 +1,128 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_EXP_H_ +#define _IOT_UART_CFG_EXP_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_EXP_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_EXP_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_EXP_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_EXP_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_EXP_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_EXP_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_EXP_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_EXP +// $[USART_IOT_UART_CFG_EXP] +#define IOT_UART_CFG_EXP_PERIPHERAL USART0 +#define IOT_UART_CFG_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PF3 +#define IOT_UART_CFG_EXP_TX_PORT gpioPortF +#define IOT_UART_CFG_EXP_TX_PIN 3 +#define IOT_UART_CFG_EXP_TX_LOC 27 + +// USART0 RX on PF4 +#define IOT_UART_CFG_EXP_RX_PORT gpioPortF +#define IOT_UART_CFG_EXP_RX_PIN 4 +#define IOT_UART_CFG_EXP_RX_LOC 27 + + + + + +// [USART_IOT_UART_CFG_EXP]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4166c/iot_uart_cfg_loopback.h b/hardware/board/config/brd4166c/iot_uart_cfg_loopback.h new file mode 100644 index 0000000000..fc1807db12 --- /dev/null +++ b/hardware/board/config/brd4166c/iot_uart_cfg_loopback.h @@ -0,0 +1,136 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_LOOPBACK_H_ +#define _IOT_UART_CFG_LOOPBACK_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_LOOPBACK_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_LOOPBACK_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_LOOPBACK_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_LOOPBACK_LOOPBACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_LOOPBACK +// $[USART_IOT_UART_CFG_LOOPBACK] +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL USART0 +#define IOT_UART_CFG_LOOPBACK_PERIPHERAL_NO 0 + +// USART0 TX on PA0 +#define IOT_UART_CFG_LOOPBACK_TX_PORT gpioPortA +#define IOT_UART_CFG_LOOPBACK_TX_PIN 0 +#define IOT_UART_CFG_LOOPBACK_TX_LOC 0 + +// USART0 RX on PA1 +#define IOT_UART_CFG_LOOPBACK_RX_PORT gpioPortA +#define IOT_UART_CFG_LOOPBACK_RX_PIN 1 +#define IOT_UART_CFG_LOOPBACK_RX_LOC 0 + + + +// USART0 RTS on PA3 +#define IOT_UART_CFG_LOOPBACK_RTS_PORT gpioPortA +#define IOT_UART_CFG_LOOPBACK_RTS_PIN 3 +#define IOT_UART_CFG_LOOPBACK_RTS_LOC 30 + +// USART0 CTS on PA2 +#define IOT_UART_CFG_LOOPBACK_CTS_PORT gpioPortA +#define IOT_UART_CFG_LOOPBACK_CTS_PIN 2 +#define IOT_UART_CFG_LOOPBACK_CTS_LOC 30 + +// [USART_IOT_UART_CFG_LOOPBACK]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_LOOPBACK_H_ */ diff --git a/hardware/board/config/brd4166c/iot_uart_cfg_vcom.h b/hardware/board/config/brd4166c/iot_uart_cfg_vcom.h new file mode 100644 index 0000000000..4b97081c2c --- /dev/null +++ b/hardware/board/config/brd4166c/iot_uart_cfg_vcom.h @@ -0,0 +1,136 @@ +/***************************************************************************//** + * @file iot_uart_cfg_inst.h + * @brief Common I/O UART instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_UART_CFG_VCOM_H_ +#define _IOT_UART_CFG_VCOM_H_ + +/******************************************************************************* + * UART Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// UART General Options + +// Instance number +// Instance number used when iot_uart_open() is called. +// Default: 0 +#define IOT_UART_CFG_VCOM_INST_NUM 0 + +// Default baud rate +// Default: 115200 +#define IOT_UART_CFG_VCOM_DEFAULT_BAUDRATE 115200 + +// Default number of data bits +// 4 data bits +// 5 data bits +// 6 data bits +// 7 data bits +// 8 data bits +// Default: usartDatabits8 +#define IOT_UART_CFG_VCOM_DEFAULT_DATA_BITS usartDatabits8 + +// Default parity mode +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define IOT_UART_CFG_VCOM_DEFAULT_PARITY usartNoParity + +// Default number of stop bits +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define IOT_UART_CFG_VCOM_DEFAULT_STOP_BITS usartStopbits1 + +// Default hardware flow control +// None +// CTS +// RTS +// CTS/RTS +// Default: usartHwFlowControlNone +#define IOT_UART_CFG_VCOM_DEFAULT_FLOW_CONTROL_TYPE usartHwFlowControlNone + + +// Internal Loopback +// Enable USART Internal loopback +// Default: 0 +#define IOT_UART_CFG_VCOM_LOOPBACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_UART_CFG_VCOM +// $[USART_IOT_UART_CFG_VCOM] +#define IOT_UART_CFG_VCOM_PERIPHERAL USART0 +#define IOT_UART_CFG_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA0 +#define IOT_UART_CFG_VCOM_TX_PORT gpioPortA +#define IOT_UART_CFG_VCOM_TX_PIN 0 +#define IOT_UART_CFG_VCOM_TX_LOC 0 + +// USART0 RX on PA1 +#define IOT_UART_CFG_VCOM_RX_PORT gpioPortA +#define IOT_UART_CFG_VCOM_RX_PIN 1 +#define IOT_UART_CFG_VCOM_RX_LOC 0 + + + +// USART0 RTS on PA3 +#define IOT_UART_CFG_VCOM_RTS_PORT gpioPortA +#define IOT_UART_CFG_VCOM_RTS_PIN 3 +#define IOT_UART_CFG_VCOM_RTS_LOC 30 + +// USART0 CTS on PA2 +#define IOT_UART_CFG_VCOM_CTS_PORT gpioPortA +#define IOT_UART_CFG_VCOM_CTS_PIN 2 +#define IOT_UART_CFG_VCOM_CTS_LOC 30 + +// [USART_IOT_UART_CFG_VCOM]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_UART_CFG_VCOM_H_ */ diff --git a/hardware/board/config/brd4166c/legacy_ncp_spi_config.h b/hardware/board/config/brd4166c/legacy_ncp_spi_config.h new file mode 100644 index 0000000000..ad379c95f4 --- /dev/null +++ b/hardware/board/config/brd4166c/legacy_ncp_spi_config.h @@ -0,0 +1,64 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef LEGACY_NCP_SPI_CONFIG_H +#define LEGACY_NCP_SPI_CONFIG_H + +// <<< sl:start pin_tool >>> +// LEGACY_NCP_SPI +// $[USART_LEGACY_NCP_SPI] +#define LEGACY_NCP_SPI_PERIPHERAL USART2 +#define LEGACY_NCP_SPI_PERIPHERAL_NO 2 + +// USART2 TX on PK0 +#define LEGACY_NCP_SPI_TX_PORT gpioPortK +#define LEGACY_NCP_SPI_TX_PIN 0 +#define LEGACY_NCP_SPI_TX_LOC 29 + +// USART2 RX on PK2 +#define LEGACY_NCP_SPI_RX_PORT gpioPortK +#define LEGACY_NCP_SPI_RX_PIN 2 +#define LEGACY_NCP_SPI_RX_LOC 30 + +// USART2 CLK on PF7 +#define LEGACY_NCP_SPI_CLK_PORT gpioPortF +#define LEGACY_NCP_SPI_CLK_PIN 7 +#define LEGACY_NCP_SPI_CLK_LOC 18 + +// USART2 CS on PA5 +#define LEGACY_NCP_SPI_CS_PORT gpioPortA +#define LEGACY_NCP_SPI_CS_PIN 5 +#define LEGACY_NCP_SPI_CS_LOC 29 + +// [USART_LEGACY_NCP_SPI]$ + +// LEGACY_NCP_SPI_HOST_INT +// $[GPIO_LEGACY_NCP_SPI_HOST_INT] +#define LEGACY_NCP_SPI_HOST_INT_PORT gpioPortA +#define LEGACY_NCP_SPI_HOST_INT_PIN 6 + +// [GPIO_LEGACY_NCP_SPI_HOST_INT]$ + +// LEGACY_NCP_SPI_WAKE_INT +// $[GPIO_LEGACY_NCP_SPI_WAKE_INT] +#define LEGACY_NCP_SPI_WAKE_INT_PORT gpioPortA +#define LEGACY_NCP_SPI_WAKE_INT_PIN 7 + +// [GPIO_LEGACY_NCP_SPI_WAKE_INT]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EXP_CONFIG_H diff --git a/hardware/board/config/brd4166c/sl_board_control_config.h b/hardware/board/config/brd4166c/sl_board_control_config.h new file mode 100644 index 0000000000..ec38ce187d --- /dev/null +++ b/hardware/board/config/brd4166c/sl_board_control_config.h @@ -0,0 +1,56 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortF +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 9 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/hardware/board/config/brd4166c/sl_cpc_drv_primary_spi_usart_exp_config.h b/hardware/board/config/brd4166c/sl_cpc_drv_primary_spi_usart_exp_config.h new file mode 100644 index 0000000000..13ec14cb1f --- /dev/null +++ b/hardware/board/config/brd4166c/sl_cpc_drv_primary_spi_usart_exp_config.h @@ -0,0 +1,98 @@ +/***************************************************************************//** + * @file + * @brief CPC SPI Primary driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_SPI_USART_EXP_PRIMARY_CONFIG_H +#define SL_CPC_DRV_SPI_USART_EXP_PRIMARY_CONFIG_H +#include "spidrv.h" + +// CPC-Primary SPI Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_SPI_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_SIZE 10 + +// SPI bit rate +// Default: 1000000 +#define SL_CPC_DRV_SPI_EXP_BITRATE 1000000 + +// Receive Interrupt Number on Falling Edge +// Default: 0 +#define SL_CPC_DRV_SPI_EXP_CS_FALLING_EDGE_INT_NO 0 + +// Receive Interrupt Number on Rising Edge +// Default: 1 +#define SL_CPC_DRV_SPI_EXP_CS_RISING_EDGE_INT_NO 1 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_SPI_EXP_RX_IRQ +// $[GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ] +#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PORT gpioPortA +#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PIN 6 + +// [GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ]$ + +// SL_CPC_DRV_SPI_EXP +// $[USART_SL_CPC_DRV_SPI_EXP] +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL USART2 +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL_NO 2 + +// USART2 TX on PK0 +#define SL_CPC_DRV_SPI_EXP_TX_PORT gpioPortK +#define SL_CPC_DRV_SPI_EXP_TX_PIN 0 +#define SL_CPC_DRV_SPI_EXP_TX_LOC 29 + +// USART2 RX on PK2 +#define SL_CPC_DRV_SPI_EXP_RX_PORT gpioPortK +#define SL_CPC_DRV_SPI_EXP_RX_PIN 2 +#define SL_CPC_DRV_SPI_EXP_RX_LOC 30 + +// USART2 CLK on PF7 +#define SL_CPC_DRV_SPI_EXP_CLK_PORT gpioPortF +#define SL_CPC_DRV_SPI_EXP_CLK_PIN 7 +#define SL_CPC_DRV_SPI_EXP_CLK_LOC 18 + +// USART2 CS on PA5 +#define SL_CPC_DRV_SPI_EXP_CS_PORT gpioPortA +#define SL_CPC_DRV_SPI_EXP_CS_PIN 5 +#define SL_CPC_DRV_SPI_EXP_CS_LOC 29 + +// [USART_SL_CPC_DRV_SPI_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_SPI_EXP_PRIMARY_CONFIG_H */ diff --git a/hardware/board/config/brd4166c/sl_cpc_drv_primary_uart_usart_exp_config.h b/hardware/board/config/brd4166c/sl_cpc_drv_primary_uart_usart_exp_config.h new file mode 100644 index 0000000000..30d979c132 --- /dev/null +++ b/hardware/board/config/brd4166c/sl_cpc_drv_primary_uart_usart_exp_config.h @@ -0,0 +1,72 @@ +/***************************************************************************//** + * @file + * @brief CPC UART PRIMARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UAR_USARTT_EXP_PRIMARY_CONFIG_H +#define SL_CPC_DRV_UART_USART_EXP_PRIMARY_CONFIG_H + +// CPC-Primary UART Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_EXP +// $[USART_SL_CPC_DRV_UART_EXP] +#define SL_CPC_DRV_UART_EXP_PERIPHERAL USART2 +#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 2 + +// USART2 TX on PK0 +#define SL_CPC_DRV_UART_EXP_TX_PORT gpioPortK +#define SL_CPC_DRV_UART_EXP_TX_PIN 0 +#define SL_CPC_DRV_UART_EXP_TX_LOC 29 + +// USART2 RX on PK2 +#define SL_CPC_DRV_UART_EXP_RX_PORT gpioPortK +#define SL_CPC_DRV_UART_EXP_RX_PIN 2 +#define SL_CPC_DRV_UART_EXP_RX_LOC 30 + +// [USART_SL_CPC_DRV_UART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_EXP_PRIMARY_CONFIG_H */ diff --git a/hardware/board/config/brd4166c/sl_cpc_drv_primary_uart_usart_vcom_config.h b/hardware/board/config/brd4166c/sl_cpc_drv_primary_uart_usart_vcom_config.h new file mode 100644 index 0000000000..bedd33f842 --- /dev/null +++ b/hardware/board/config/brd4166c/sl_cpc_drv_primary_uart_usart_vcom_config.h @@ -0,0 +1,72 @@ +/***************************************************************************//** + * @file + * @brief CPC UART PRIMARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UAR_USARTT_VCOM_PRIMARY_CONFIG_H +#define SL_CPC_DRV_UART_USART_VCOM_PRIMARY_CONFIG_H + +// CPC-Primary UART Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[USART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA0 +#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_TX_PIN 0 +#define SL_CPC_DRV_UART_VCOM_TX_LOC 0 + +// USART0 RX on PA1 +#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_RX_PIN 1 +#define SL_CPC_DRV_UART_VCOM_RX_LOC 0 + +// [USART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_PRIMARY_CONFIG_H */ diff --git a/hardware/board/config/brd4166c/sl_cpc_drv_secondary_spi_usart_exp_config.h b/hardware/board/config/brd4166c/sl_cpc_drv_secondary_spi_usart_exp_config.h new file mode 100644 index 0000000000..a93b721f9b --- /dev/null +++ b/hardware/board/config/brd4166c/sl_cpc_drv_secondary_spi_usart_exp_config.h @@ -0,0 +1,98 @@ +/***************************************************************************//** + * @file + * @brief CPC SPI SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_SPI_USART_EXP_SECONDARY_CONFIG_H +#define SL_CPC_DRV_SPI_USART_EXP_SECONDARY_CONFIG_H +#include "spidrv.h" + +// CPC-Secondary SPI Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_SPI_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_SIZE 10 + +// SPI bit rate +// Default: 1000000 +#define SL_CPC_DRV_SPI_EXP_BITRATE 1000000 + +// Chip Select Interrupt Number on Falling Edge +// Default: 10 +#define SL_CPC_DRV_SPI_EXP_CS_FALLING_EDGE_INT_NO 4 + +// Chip Select Interrupt Number on Rising Edge +// Default: 11 +#define SL_CPC_DRV_SPI_EXP_CS_RISING_EDGE_INT_NO 5 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_SPI_EXP_RX_IRQ +// $[GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ] +#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PORT gpioPortA +#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PIN 6 + +// [GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ]$ + +// SL_CPC_DRV_SPI_EXP +// $[USART_SL_CPC_DRV_SPI_EXP] +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL USART2 +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL_NO 2 + +// USART2 TX on PK0 +#define SL_CPC_DRV_SPI_EXP_TX_PORT gpioPortK +#define SL_CPC_DRV_SPI_EXP_TX_PIN 0 +#define SL_CPC_DRV_SPI_EXP_TX_LOC 29 + +// USART2 RX on PK2 +#define SL_CPC_DRV_SPI_EXP_RX_PORT gpioPortK +#define SL_CPC_DRV_SPI_EXP_RX_PIN 2 +#define SL_CPC_DRV_SPI_EXP_RX_LOC 30 + +// USART2 CLK on PF7 +#define SL_CPC_DRV_SPI_EXP_CLK_PORT gpioPortF +#define SL_CPC_DRV_SPI_EXP_CLK_PIN 7 +#define SL_CPC_DRV_SPI_EXP_CLK_LOC 18 + +// USART2 CS on PA5 +#define SL_CPC_DRV_SPI_EXP_CS_PORT gpioPortA +#define SL_CPC_DRV_SPI_EXP_CS_PIN 5 +#define SL_CPC_DRV_SPI_EXP_CS_LOC 29 + +// [USART_SL_CPC_DRV_SPI_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_SPI_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4166c/sl_cpc_drv_secondary_uart_usart_exp_config.h b/hardware/board/config/brd4166c/sl_cpc_drv_secondary_uart_usart_exp_config.h new file mode 100644 index 0000000000..292b1a14c2 --- /dev/null +++ b/hardware/board/config/brd4166c/sl_cpc_drv_secondary_uart_usart_exp_config.h @@ -0,0 +1,88 @@ +/***************************************************************************//** + * @file + * @brief CPC UART SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_EXP_SECONDARY_CONFIG_H +#define SL_CPC_DRV_UART_USART_EXP_SECONDARY_CONFIG_H + +// CPC - Secondary UART Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_EXP +// $[USART_SL_CPC_DRV_UART_EXP] +#define SL_CPC_DRV_UART_EXP_PERIPHERAL USART2 +#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 2 + +// USART2 TX on PK0 +#define SL_CPC_DRV_UART_EXP_TX_PORT gpioPortK +#define SL_CPC_DRV_UART_EXP_TX_PIN 0 +#define SL_CPC_DRV_UART_EXP_TX_LOC 29 + +// USART2 RX on PK2 +#define SL_CPC_DRV_UART_EXP_RX_PORT gpioPortK +#define SL_CPC_DRV_UART_EXP_RX_PIN 2 +#define SL_CPC_DRV_UART_EXP_RX_LOC 30 + +// USART2 CTS on PF7 +#define SL_CPC_DRV_UART_EXP_CTS_PORT gpioPortF +#define SL_CPC_DRV_UART_EXP_CTS_PIN 7 +#define SL_CPC_DRV_UART_EXP_CTS_LOC 16 + +// USART2 RTS on PA5 +#define SL_CPC_DRV_UART_EXP_RTS_PORT gpioPortA +#define SL_CPC_DRV_UART_EXP_RTS_PIN 5 +#define SL_CPC_DRV_UART_EXP_RTS_LOC 27 + +// [USART_SL_CPC_DRV_UART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4166c/sl_cpc_drv_secondary_uart_usart_vcom_config.h b/hardware/board/config/brd4166c/sl_cpc_drv_secondary_uart_usart_vcom_config.h new file mode 100644 index 0000000000..a09a453592 --- /dev/null +++ b/hardware/board/config/brd4166c/sl_cpc_drv_secondary_uart_usart_vcom_config.h @@ -0,0 +1,88 @@ +/***************************************************************************//** + * @file + * @brief CPC UART SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_USART_VCOM_SECONDARY_CONFIG_H +#define SL_CPC_DRV_UART_USART_VCOM_SECONDARY_CONFIG_H + +// CPC - Secondary UART Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// UART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: usartHwFlowControlCtsAndRts +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[USART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL USART0 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA0 +#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_TX_PIN 0 +#define SL_CPC_DRV_UART_VCOM_TX_LOC 0 + +// USART0 RX on PA1 +#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_RX_PIN 1 +#define SL_CPC_DRV_UART_VCOM_RX_LOC 0 + +// USART0 CTS on PA2 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 2 +#define SL_CPC_DRV_UART_VCOM_CTS_LOC 30 + +// USART0 RTS on PA3 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 3 +#define SL_CPC_DRV_UART_VCOM_RTS_LOC 30 + +// [USART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4166c/sl_device_init_hfxo_config.h b/hardware/board/config/brd4166c/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..bcb2be609d --- /dev/null +++ b/hardware/board/config/brd4166c/sl_device_init_hfxo_config.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuOscMode_Crystal + +// Frequency <38000000-40000000> +// Default: 38400000 +#define SL_DEVICE_INIT_HFXO_FREQ 38400000 + +// CTUNE <0-511> +// Default: 360 +#define SL_DEVICE_INIT_HFXO_CTUNE 332 + +// Advanced Configurations +// Auto-start HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSTART false + +// Auto-select HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSELECT false + +// + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/board/config/brd4166c/sl_device_init_lfxo_config.h b/hardware/board/config/brd4166c/sl_device_init_lfxo_config.h new file mode 100644 index 0000000000..d4b79b3d88 --- /dev/null +++ b/hardware/board/config/brd4166c/sl_device_init_lfxo_config.h @@ -0,0 +1,67 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_LFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 32 + +// LFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_LFXO_PRECISION 100 + +// Startup Timeout Delay +// +// <_CMU_LFXOCTRL_TIMEOUT_2CYCLES=> 2 cycles +// <_CMU_LFXOCTRL_TIMEOUT_256CYCLES=> 256 cycles +// <_CMU_LFXOCTRL_TIMEOUT_1KCYCLES=> 1K cycles +// <_CMU_LFXOCTRL_TIMEOUT_2KCYCLES=> 2K cycles +// <_CMU_LFXOCTRL_TIMEOUT_4KCYCLES=> 4K cycles +// <_CMU_LFXOCTRL_TIMEOUT_8KCYCLES=> 8K cycles +// <_CMU_LFXOCTRL_TIMEOUT_16KCYCLES=> 16K cycles +// <_CMU_LFXOCTRL_TIMEOUT_32KCYCLES=> 32K cycles +// <_CMU_LFXOCTRL_TIMEOUT_DEFAULT=> Default +// Default: _CMU_LFXOCTRL_TIMEOUT_DEFAULT +#define SL_DEVICE_INIT_LFXO_TIMEOUT _CMU_LFXOCTRL_TIMEOUT_DEFAULT +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/hardware/board/config/brd4166c/sl_i2cspm_sensor_config.h b/hardware/board/config/brd4166c/sl_i2cspm_sensor_config.h new file mode 100644 index 0000000000..b03f77aa3d --- /dev/null +++ b/hardware/board/config/brd4166c/sl_i2cspm_sensor_config.h @@ -0,0 +1,60 @@ +/***************************************************************************//** + * @file + * @brief I2CSPM Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_I2CSPM_SENSOR_CONFIG_H +#define SL_I2CSPM_SENSOR_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu + +// I2CSPM settings + +// Reference clock frequency +// Frequency in Hz of the reference clock. +// Select 0 to use the frequency of the currently selected clock. +// Default: 0 +#define SL_I2CSPM_SENSOR_REFERENCE_CLOCK 0 + +// Speed mode +// <0=> Standard mode (100kbit/s) +// <1=> Fast mode (400kbit/s) +// <2=> Fast mode plus (1Mbit/s) +// Default: 0 +#define SL_I2CSPM_SENSOR_SPEED_MODE 0 +// end I2CSPM config + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_I2CSPM_SENSOR +// $[I2C_SL_I2CSPM_SENSOR] +#define SL_I2CSPM_SENSOR_PERIPHERAL I2C1 +#define SL_I2CSPM_SENSOR_PERIPHERAL_NO 1 + +// I2C1 SCL on PC5 +#define SL_I2CSPM_SENSOR_SCL_PORT gpioPortC +#define SL_I2CSPM_SENSOR_SCL_PIN 5 +#define SL_I2CSPM_SENSOR_SCL_LOC 17 + +// I2C1 SDA on PC4 +#define SL_I2CSPM_SENSOR_SDA_PORT gpioPortC +#define SL_I2CSPM_SENSOR_SDA_PIN 4 +#define SL_I2CSPM_SENSOR_SDA_LOC 17 + +// [I2C_SL_I2CSPM_SENSOR]$ +// <<< sl:end pin_tool >>> + +#endif // SL_I2CSPM_SENSOR_CONFIG_H diff --git a/hardware/board/config/brd4166c/sl_i2cspm_sensor_env_config.h b/hardware/board/config/brd4166c/sl_i2cspm_sensor_env_config.h new file mode 100644 index 0000000000..c28fc6a259 --- /dev/null +++ b/hardware/board/config/brd4166c/sl_i2cspm_sensor_env_config.h @@ -0,0 +1,60 @@ +/***************************************************************************//** + * @file + * @brief I2CSPM Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_I2CSPM_SENSOR_ENV_CONFIG_H +#define SL_I2CSPM_SENSOR_ENV_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu + +// I2CSPM settings + +// Reference clock frequency +// Frequency in Hz of the reference clock. +// Select 0 to use the frequency of the currently selected clock. +// Default: 0 +#define SL_I2CSPM_SENSOR_ENV_REFERENCE_CLOCK 0 + +// Speed mode +// <0=> Standard mode (100kbit/s) +// <1=> Fast mode (400kbit/s) +// <2=> Fast mode plus (1Mbit/s) +// Default: 0 +#define SL_I2CSPM_SENSOR_ENV_SPEED_MODE 0 +// end I2CSPM config + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_I2CSPM_SENSOR_ENV +// $[I2C_SL_I2CSPM_SENSOR_ENV] +#define SL_I2CSPM_SENSOR_ENV_PERIPHERAL I2C1 +#define SL_I2CSPM_SENSOR_ENV_PERIPHERAL_NO 1 + +// I2C1 SCL on PC5 +#define SL_I2CSPM_SENSOR_ENV_SCL_PORT gpioPortC +#define SL_I2CSPM_SENSOR_ENV_SCL_PIN 5 +#define SL_I2CSPM_SENSOR_ENV_SCL_LOC 17 + +// I2C1 SDA on PC4 +#define SL_I2CSPM_SENSOR_ENV_SDA_PORT gpioPortC +#define SL_I2CSPM_SENSOR_ENV_SDA_PIN 4 +#define SL_I2CSPM_SENSOR_ENV_SDA_LOC 17 + +// [I2C_SL_I2CSPM_SENSOR_ENV]$ +// <<< sl:end pin_tool >>> + +#endif // SL_I2CSPM_SENSOR_ENV_CONFIG_H diff --git a/hardware/board/config/brd4166c/sl_iostream_leuart_exp_config.h b/hardware/board/config/brd4166c/sl_iostream_leuart_exp_config.h new file mode 100644 index 0000000000..732abbde5e --- /dev/null +++ b/hardware/board/config/brd4166c/sl_iostream_leuart_exp_config.h @@ -0,0 +1,96 @@ +/***************************************************************************/ /** + * @file + * @brief SL_IOSTREAM_LEUART Config. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_IOSTREAM_LEUART_EXP_CONFIG_H +#define SL_IOSTREAM_LEUART_EXP_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// LEUART settings + +// Baud rate +// Default: 9600 +#define SL_IOSTREAM_LEUART_EXP_BAUDRATE 9600 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: leuartNoParity +#define SL_IOSTREAM_LEUART_EXP_PARITY leuartNoParity + +// Number of stop bits to use. +// 1 stop bits +// 2 stop bits +// Default: leuartStopbits1 +#define SL_IOSTREAM_LEUART_EXP_STOP_BITS leuartStopbits1 + +// Flow control +// None +// Software Flow control (XON/XOFF) +// Default: uartFlowControlNone +#define SL_IOSTREAM_LEUART_EXP_FLOW_CONTROL_TYPE uartFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_LEUART_EXP_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n; It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_LEUART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_LEUART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_LEUART_EXP +// $[LEUART_SL_IOSTREAM_LEUART_EXP] +#define SL_IOSTREAM_LEUART_EXP_PERIPHERAL LEUART0 +#define SL_IOSTREAM_LEUART_EXP_PERIPHERAL_NO 0 + +// LEUART0 TX on PF3 +#define SL_IOSTREAM_LEUART_EXP_TX_PORT gpioPortF +#define SL_IOSTREAM_LEUART_EXP_TX_PIN 3 +#define SL_IOSTREAM_LEUART_EXP_TX_LOC 27 + +// LEUART0 RX on PF4 +#define SL_IOSTREAM_LEUART_EXP_RX_PORT gpioPortF +#define SL_IOSTREAM_LEUART_EXP_RX_PIN 4 +#define SL_IOSTREAM_LEUART_EXP_RX_LOC 27 + +// [LEUART_SL_IOSTREAM_LEUART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4166c/sl_iostream_leuart_vcom_config.h b/hardware/board/config/brd4166c/sl_iostream_leuart_vcom_config.h new file mode 100644 index 0000000000..4ff343dd76 --- /dev/null +++ b/hardware/board/config/brd4166c/sl_iostream_leuart_vcom_config.h @@ -0,0 +1,96 @@ +/***************************************************************************/ /** + * @file + * @brief SL_IOSTREAM_LEUART Config. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_IOSTREAM_LEUART_VCOM_CONFIG_H +#define SL_IOSTREAM_LEUART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// LEUART settings + +// Baud rate +// Default: 9600 +#define SL_IOSTREAM_LEUART_VCOM_BAUDRATE 9600 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: leuartNoParity +#define SL_IOSTREAM_LEUART_VCOM_PARITY leuartNoParity + +// Number of stop bits to use. +// 1 stop bits +// 2 stop bits +// Default: leuartStopbits1 +#define SL_IOSTREAM_LEUART_VCOM_STOP_BITS leuartStopbits1 + +// Flow control +// None +// Software Flow control (XON/XOFF) +// Default: uartFlowControlNone +#define SL_IOSTREAM_LEUART_VCOM_FLOW_CONTROL_TYPE uartFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_LEUART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n; It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_LEUART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_LEUART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_LEUART_VCOM +// $[LEUART_SL_IOSTREAM_LEUART_VCOM] +#define SL_IOSTREAM_LEUART_VCOM_PERIPHERAL LEUART0 +#define SL_IOSTREAM_LEUART_VCOM_PERIPHERAL_NO 0 + +// LEUART0 TX on PA0 +#define SL_IOSTREAM_LEUART_VCOM_TX_PORT gpioPortA +#define SL_IOSTREAM_LEUART_VCOM_TX_PIN 0 +#define SL_IOSTREAM_LEUART_VCOM_TX_LOC 0 + +// LEUART0 RX on PA1 +#define SL_IOSTREAM_LEUART_VCOM_RX_PORT gpioPortA +#define SL_IOSTREAM_LEUART_VCOM_RX_PIN 1 +#define SL_IOSTREAM_LEUART_VCOM_RX_LOC 0 + +// [LEUART_SL_IOSTREAM_LEUART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4166c/sl_iostream_usart_exp_config.h b/hardware/board/config/brd4166c/sl_iostream_usart_exp_config.h new file mode 100644 index 0000000000..85e5603c54 --- /dev/null +++ b/hardware/board/config/brd4166c/sl_iostream_usart_exp_config.h @@ -0,0 +1,105 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_EXP_CONFIG_H +#define SL_IOSTREAM_USART_EXP_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_EXP_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_EXP_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_EXP_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_EXP_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_EXP +// $[USART_SL_IOSTREAM_USART_EXP] +#define SL_IOSTREAM_USART_EXP_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PF3 +#define SL_IOSTREAM_USART_EXP_TX_PORT gpioPortF +#define SL_IOSTREAM_USART_EXP_TX_PIN 3 +#define SL_IOSTREAM_USART_EXP_TX_LOC 27 + +// USART0 RX on PF4 +#define SL_IOSTREAM_USART_EXP_RX_PORT gpioPortF +#define SL_IOSTREAM_USART_EXP_RX_PIN 4 +#define SL_IOSTREAM_USART_EXP_RX_LOC 27 + + + +// [USART_SL_IOSTREAM_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4166c/sl_iostream_usart_vcom_config.h b/hardware/board/config/brd4166c/sl_iostream_usart_vcom_config.h new file mode 100644 index 0000000000..def0f653e6 --- /dev/null +++ b/hardware/board/config/brd4166c/sl_iostream_usart_vcom_config.h @@ -0,0 +1,113 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H +#define SL_IOSTREAM_USART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_VCOM +// $[USART_SL_IOSTREAM_USART_VCOM] +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA0 +#define SL_IOSTREAM_USART_VCOM_TX_PORT gpioPortA +#define SL_IOSTREAM_USART_VCOM_TX_PIN 0 +#define SL_IOSTREAM_USART_VCOM_TX_LOC 0 + +// USART0 RX on PA1 +#define SL_IOSTREAM_USART_VCOM_RX_PORT gpioPortA +#define SL_IOSTREAM_USART_VCOM_RX_PIN 1 +#define SL_IOSTREAM_USART_VCOM_RX_LOC 0 + +// USART0 CTS on PA2 +#define SL_IOSTREAM_USART_VCOM_CTS_PORT gpioPortA +#define SL_IOSTREAM_USART_VCOM_CTS_PIN 2 +#define SL_IOSTREAM_USART_VCOM_CTS_LOC 30 + +// USART0 RTS on PA3 +#define SL_IOSTREAM_USART_VCOM_RTS_PORT gpioPortA +#define SL_IOSTREAM_USART_VCOM_RTS_PIN 3 +#define SL_IOSTREAM_USART_VCOM_RTS_LOC 30 + +// [USART_SL_IOSTREAM_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4166c/sl_mx25_flash_shutdown_usart_config.h b/hardware/board/config/brd4166c/sl_mx25_flash_shutdown_usart_config.h new file mode 100644 index 0000000000..2724fe4e42 --- /dev/null +++ b/hardware/board/config/brd4166c/sl_mx25_flash_shutdown_usart_config.h @@ -0,0 +1,54 @@ +/***************************************************************************//** + * @file + * @brief SL_MX25_FLASH_SHUTDOWN_USART Config + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H +#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H + +// <<< sl:start pin_tool >>> +// {usart signal=TX,RX,CLK} SL_MX25_FLASH_SHUTDOWN +// [USART_SL_MX25_FLASH_SHUTDOWN] +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL USART2 +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 2 + +// USART2 TX on PK0 +#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortK +#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 0 +#define SL_MX25_FLASH_SHUTDOWN_TX_LOC 29 + +// USART2 RX on PK2 +#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortK +#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 2 +#define SL_MX25_FLASH_SHUTDOWN_RX_LOC 30 + +// USART2 CLK on PF7 +#define SL_MX25_FLASH_SHUTDOWN_CLK_PORT gpioPortF +#define SL_MX25_FLASH_SHUTDOWN_CLK_PIN 7 +#define SL_MX25_FLASH_SHUTDOWN_CLK_LOC 18 + +// [USART_SL_MX25_FLASH_SHUTDOWN] + +// SL_MX25_FLASH_SHUTDOWN_CS + +// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] +#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortK +#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 1 + +// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4166c/sl_ncp_spidrv_usart_config.h b/hardware/board/config/brd4166c/sl_ncp_spidrv_usart_config.h new file mode 100644 index 0000000000..f453fb4249 --- /dev/null +++ b/hardware/board/config/brd4166c/sl_ncp_spidrv_usart_config.h @@ -0,0 +1,98 @@ +/***************************************************************************//** + * @file + * @brief Open thread NCP spidrv usart configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_NCP_SPIDRV_USART_CONFIG_H +#define SL_NCP_SPIDRV_USART_CONFIG_H +#include "spidrv.h" + +// NCP spidrv usart Configuration + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_NCP_SPIDRV_USART_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_NCP_SPIDRV_USART_CLOCK_MODE spidrvClockMode0 + +// Chip Select Interrupt Number on Falling Edge +// Default: 10 +#define SL_NCP_SPIDRV_USART_CS_FALLING_EDGE_INT_NO 4 + +// Chip Select Interrupt Number on Rising Edge +// Default: 9 +#define SL_NCP_SPIDRV_USART_CS_RISING_EDGE_INT_NO 5 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_NCP_SPIDRV_USART_HOST_INT +// $[GPIO_SL_NCP_SPIDRV_USART_HOST_INT] +#define SL_NCP_SPIDRV_USART_HOST_INT_PORT gpioPortA +#define SL_NCP_SPIDRV_USART_HOST_INT_PIN 6 + +// [GPIO_SL_NCP_SPIDRV_USART_HOST_INT]$ + +// SL_NCP_SPIDRV_USART +// $[USART_SL_NCP_SPIDRV_USART] +#define SL_NCP_SPIDRV_USART_PERIPHERAL USART2 +#define SL_NCP_SPIDRV_USART_PERIPHERAL_NO 2 + +// USART2 TX on PK0 +#define SL_NCP_SPIDRV_USART_TX_PORT gpioPortK +#define SL_NCP_SPIDRV_USART_TX_PIN 0 +#define SL_NCP_SPIDRV_USART_TX_LOC 29 + +// USART2 RX on PK2 +#define SL_NCP_SPIDRV_USART_RX_PORT gpioPortK +#define SL_NCP_SPIDRV_USART_RX_PIN 2 +#define SL_NCP_SPIDRV_USART_RX_LOC 30 + +// USART2 CLK on PF7 +#define SL_NCP_SPIDRV_USART_CLK_PORT gpioPortF +#define SL_NCP_SPIDRV_USART_CLK_PIN 7 +#define SL_NCP_SPIDRV_USART_CLK_LOC 18 + +// USART2 CS on PA5 +#define SL_NCP_SPIDRV_USART_CS_PORT gpioPortA +#define SL_NCP_SPIDRV_USART_CS_PIN 5 +#define SL_NCP_SPIDRV_USART_CS_LOC 29 + +// [USART_SL_NCP_SPIDRV_USART]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_NCP_SPIDRV_USART_CONFIG_H */ diff --git a/hardware/board/config/brd4166c/sl_pwm_init_led0_config.h b/hardware/board/config/brd4166c/sl_pwm_init_led0_config.h new file mode 100644 index 0000000000..a6bdf4288c --- /dev/null +++ b/hardware/board/config/brd4166c/sl_pwm_init_led0_config.h @@ -0,0 +1,63 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef PWM_INIT_LED0_CONFIG_H +#define PWM_INIT_LED0_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED0_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED0_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED0 +// $[TIMER_SL_PWM_LED0] +#define SL_PWM_LED0_PERIPHERAL WTIMER0 +#define SL_PWM_LED0_PERIPHERAL_NO 0 + +#define SL_PWM_LED0_OUTPUT_CHANNEL 1 +// WTIMER0 CC1 on PD8 +#define SL_PWM_LED0_OUTPUT_PORT gpioPortD +#define SL_PWM_LED0_OUTPUT_PIN 8 +#define SL_PWM_LED0_OUTPUT_LOC 30 + +// [TIMER_SL_PWM_LED0]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // PWM_INIT_LED0_CONFIG_H diff --git a/hardware/board/config/brd4166c/sl_rail_util_pa_config.h b/hardware/board/config/brd4166c/sl_rail_util_pa_config.h new file mode 100644 index 0000000000..d2115c77af --- /dev/null +++ b/hardware/board/config/brd4166c/sl_rail_util_pa_config.h @@ -0,0 +1,80 @@ +/***************************************************************************//** + * @file + * @brief Power Amplifier configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PA_CONFIG_H +#define SL_RAIL_UTIL_PA_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// PA Configuration +// Initial PA Power (deci-dBm, 100 = 10.0 dBm) +// Default: 100 +#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 +// PA Ramp Time (microseconds) +// <0-65535:1> +// Default: 10 +#define SL_RAIL_UTIL_PA_RAMP_TIME_US 10 +// Milli-volts on PA supply pin (PA_VDD) +// <0-65535:1> +// Default: 3300 +#define SL_RAIL_UTIL_PA_VOLTAGE_MV 1800 +// 2.4 GHz PA Selection +// High Power +// Low Power +// Disable +// Default: RAIL_TX_POWER_MODE_2P4GIG_HP +#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HP +// Sub-1 GHz PA Selection +// Enable +// Disable +// Default: RAIL_TX_POWER_MODE_SUBGIG +#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE +// + +// PA Curve Configuration +// Header file containing custom PA curves +// Default: "pa_curves_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" +// Header file containing PA curve types +// Default: "pa_curve_types_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" +// + +// PA Calibration Configuration +// Apply PA Calibration Factory Offset +// Default: 1 +#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 +// + +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/hardware/board/config/brd4166c/sl_rail_util_pti_config.h b/hardware/board/config/brd4166c/sl_rail_util_pti_config.h new file mode 100644 index 0000000000..e5ea09f6f5 --- /dev/null +++ b/hardware/board/config/brd4166c/sl_rail_util_pti_config.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file + * @brief Packet Trace Information configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PTI_CONFIG_H +#define SL_RAIL_UTIL_PTI_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PTI Configuration + +// PTI mode +// UART +// UART onewire +// SPI +// Disabled +// Default: RAIL_PTI_MODE_UART +#define SL_RAIL_UTIL_PTI_MODE RAIL_PTI_MODE_UART + +// PTI Baud Rate (Hertz) +// <147800-20000000:1> +// Default: 1600000 +#define SL_RAIL_UTIL_PTI_BAUD_RATE_HZ 1600000 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_RAIL_UTIL_PTI +// $[PTI_SL_RAIL_UTIL_PTI] +#define SL_RAIL_UTIL_PTI_PERIPHERAL PTI + +// PTI DOUT on PB12 +#define SL_RAIL_UTIL_PTI_DOUT_PORT gpioPortB +#define SL_RAIL_UTIL_PTI_DOUT_PIN 12 +#define SL_RAIL_UTIL_PTI_DOUT_LOC 6 + +// PTI DFRAME on PB13 +#define SL_RAIL_UTIL_PTI_DFRAME_PORT gpioPortB +#define SL_RAIL_UTIL_PTI_DFRAME_PIN 13 +#define SL_RAIL_UTIL_PTI_DFRAME_LOC 6 + + +// [PTI_SL_RAIL_UTIL_PTI]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_RAIL_UTIL_PTI_CONFIG_H diff --git a/hardware/board/config/brd4166c/sl_simple_button_btn0_config.h b/hardware/board/config/brd4166c/sl_simple_button_btn0_config.h new file mode 100644 index 0000000000..e4c59004af --- /dev/null +++ b/hardware/board/config/brd4166c/sl_simple_button_btn0_config.h @@ -0,0 +1,45 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver User Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_BTN0_CONFIG_H +#define SL_SIMPLE_BUTTON_BTN0_CONFIG_H + +#include "em_gpio.h" +#include "sl_simple_button.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// +// Interrupt +// Poll and Debounce +// Poll +// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT +#define SL_SIMPLE_BUTTON_BTN0_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_BUTTON_BTN0 +// $[GPIO_SL_SIMPLE_BUTTON_BTN0] +#define SL_SIMPLE_BUTTON_BTN0_PORT gpioPortD +#define SL_SIMPLE_BUTTON_BTN0_PIN 14 + +// [GPIO_SL_SIMPLE_BUTTON_BTN0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_BUTTON_BTN0_CONFIG_H diff --git a/hardware/board/config/brd4166c/sl_simple_button_btn1_config.h b/hardware/board/config/brd4166c/sl_simple_button_btn1_config.h new file mode 100644 index 0000000000..9730dfd938 --- /dev/null +++ b/hardware/board/config/brd4166c/sl_simple_button_btn1_config.h @@ -0,0 +1,45 @@ +/***************************************************************************//** + * @file + * @brief Simple Button Driver User Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_BUTTON_BTN1_CONFIG_H +#define SL_SIMPLE_BUTTON_BTN1_CONFIG_H + +#include "em_gpio.h" +#include "sl_simple_button.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// +// Interrupt +// Poll and Debounce +// Poll +// Default: SL_SIMPLE_BUTTON_MODE_INTERRUPT +#define SL_SIMPLE_BUTTON_BTN1_MODE SL_SIMPLE_BUTTON_MODE_INTERRUPT +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_BUTTON_BTN1 +// $[GPIO_SL_SIMPLE_BUTTON_BTN1] +#define SL_SIMPLE_BUTTON_BTN1_PORT gpioPortD +#define SL_SIMPLE_BUTTON_BTN1_PIN 15 + +// [GPIO_SL_SIMPLE_BUTTON_BTN1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_BUTTON_BTN1_CONFIG_H diff --git a/hardware/board/config/brd4166c/sl_simple_led_led0_config.h b/hardware/board/config/brd4166c/sl_simple_led_led0_config.h new file mode 100644 index 0000000000..93122f9958 --- /dev/null +++ b/hardware/board/config/brd4166c/sl_simple_led_led0_config.h @@ -0,0 +1,44 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED0_CONFIG_H +#define SL_SIMPLE_LED_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED0_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED0 +// $[GPIO_SL_SIMPLE_LED_LED0] +#define SL_SIMPLE_LED_LED0_PORT gpioPortD +#define SL_SIMPLE_LED_LED0_PIN 8 + +// [GPIO_SL_SIMPLE_LED_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED0_CONFIG_H diff --git a/hardware/board/config/brd4166c/sl_simple_led_led1_config.h b/hardware/board/config/brd4166c/sl_simple_led_led1_config.h new file mode 100644 index 0000000000..c97cc9ed3c --- /dev/null +++ b/hardware/board/config/brd4166c/sl_simple_led_led1_config.h @@ -0,0 +1,44 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED1_CONFIG_H +#define SL_SIMPLE_LED_LED1_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED1_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED1 +// $[GPIO_SL_SIMPLE_LED_LED1] +#define SL_SIMPLE_LED_LED1_PORT gpioPortD +#define SL_SIMPLE_LED_LED1_PIN 9 + +// [GPIO_SL_SIMPLE_LED_LED1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED1_CONFIG_H diff --git a/hardware/board/config/brd4166c/sl_spidrv_exp_config.h b/hardware/board/config/brd4166c/sl_spidrv_exp_config.h new file mode 100644 index 0000000000..4435c80ff0 --- /dev/null +++ b/hardware/board/config/brd4166c/sl_spidrv_exp_config.h @@ -0,0 +1,93 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_EXP_CONFIG_H +#define SL_SPIDRV_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_EXP_BITRATE 1000000 + +// SPI frame length <4-16> +// Default: 8 +#define SL_SPIDRV_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_EXP +// $[USART_SL_SPIDRV_EXP] +#define SL_SPIDRV_EXP_PERIPHERAL USART2 +#define SL_SPIDRV_EXP_PERIPHERAL_NO 2 + +// USART2 TX on PK0 +#define SL_SPIDRV_EXP_TX_PORT gpioPortK +#define SL_SPIDRV_EXP_TX_PIN 0 +#define SL_SPIDRV_EXP_TX_LOC 29 + +// USART2 RX on PK2 +#define SL_SPIDRV_EXP_RX_PORT gpioPortK +#define SL_SPIDRV_EXP_RX_PIN 2 +#define SL_SPIDRV_EXP_RX_LOC 30 + +// USART2 CLK on PF7 +#define SL_SPIDRV_EXP_CLK_PORT gpioPortF +#define SL_SPIDRV_EXP_CLK_PIN 7 +#define SL_SPIDRV_EXP_CLK_LOC 18 + +// USART2 CS on PA5 +#define SL_SPIDRV_EXP_CS_PORT gpioPortA +#define SL_SPIDRV_EXP_CS_PIN 5 +#define SL_SPIDRV_EXP_CS_LOC 29 + +// [USART_SL_SPIDRV_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EXP_CONFIG_H diff --git a/hardware/board/config/brd4166c/sl_spidrv_usart_exp_config.h b/hardware/board/config/brd4166c/sl_spidrv_usart_exp_config.h new file mode 100644 index 0000000000..9abf2eb3cc --- /dev/null +++ b/hardware/board/config/brd4166c/sl_spidrv_usart_exp_config.h @@ -0,0 +1,93 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_USART_EXP_CONFIG_H +#define SL_SPIDRV_USART_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_USART_EXP_BITRATE 1000000 + +// SPI frame length <4-16> +// Default: 8 +#define SL_SPIDRV_USART_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_USART_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_USART_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_USART_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_USART_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_USART_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_EXP +// $[USART_SL_SPIDRV_EXP] +#define SL_SPIDRV_EXP_PERIPHERAL USART2 +#define SL_SPIDRV_EXP_PERIPHERAL_NO 2 + +// USART2 TX on PK0 +#define SL_SPIDRV_EXP_TX_PORT gpioPortK +#define SL_SPIDRV_EXP_TX_PIN 0 +#define SL_SPIDRV_EXP_TX_LOC 29 + +// USART2 RX on PK2 +#define SL_SPIDRV_EXP_RX_PORT gpioPortK +#define SL_SPIDRV_EXP_RX_PIN 2 +#define SL_SPIDRV_EXP_RX_LOC 30 + +// USART2 CLK on PF7 +#define SL_SPIDRV_EXP_CLK_PORT gpioPortF +#define SL_SPIDRV_EXP_CLK_PIN 7 +#define SL_SPIDRV_EXP_CLK_LOC 18 + +// USART2 CS on PA5 +#define SL_SPIDRV_EXP_CS_PORT gpioPortA +#define SL_SPIDRV_EXP_CS_PIN 5 +#define SL_SPIDRV_EXP_CS_LOC 29 + +// [USART_SL_SPIDRV_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4166c/sl_uartdrv_leuart_exp_config.h b/hardware/board/config/brd4166c/sl_uartdrv_leuart_exp_config.h new file mode 100644 index 0000000000..3c9a90d504 --- /dev/null +++ b/hardware/board/config/brd4166c/sl_uartdrv_leuart_exp_config.h @@ -0,0 +1,87 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_LEUART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_LEUART_EXP_CONFIG_H +#define SL_UARTDRV_LEUART_EXP_CONFIG_H + +#include "em_leuart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_LEUART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: leuartNoParity +#define SL_UARTDRV_LEUART_EXP_PARITY leuartNoParity + +// Number of stop bits to use. +// 1 stop bits +// 2 stop bits +// Default: leuartStopbits1 +#define SL_UARTDRV_LEUART_EXP_STOP_BITS leuartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHw +#define SL_UARTDRV_LEUART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_LEUART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_LEUART_EXP_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_LEUART_EXP +// $[LEUART_SL_UARTDRV_LEUART_EXP] +#define SL_UARTDRV_LEUART_EXP_PERIPHERAL LEUART0 +#define SL_UARTDRV_LEUART_EXP_PERIPHERAL_NO 0 + +// LEUART0 TX on PF3 +#define SL_UARTDRV_LEUART_EXP_TX_PORT gpioPortF +#define SL_UARTDRV_LEUART_EXP_TX_PIN 3 +#define SL_UARTDRV_LEUART_EXP_TX_LOC 27 + +// LEUART0 RX on PF4 +#define SL_UARTDRV_LEUART_EXP_RX_PORT gpioPortF +#define SL_UARTDRV_LEUART_EXP_RX_PIN 4 +#define SL_UARTDRV_LEUART_EXP_RX_LOC 27 + +// [LEUART_SL_UARTDRV_LEUART_EXP]$ +// SL_UARTDRV_LEUART_EXP_CTS +// $[GPIO_SL_UARTDRV_LEUART_EXP_CTS] + +// [GPIO_SL_UARTDRV_LEUART_EXP_CTS]$ + +// SL_UARTDRV_LEUART_EXP_RTS +// $[GPIO_SL_UARTDRV_LEUART_EXP_RTS] + +// [GPIO_SL_UARTDRV_LEUART_EXP_RTS]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_LEUART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4166c/sl_uartdrv_leuart_vcom_config.h b/hardware/board/config/brd4166c/sl_uartdrv_leuart_vcom_config.h new file mode 100644 index 0000000000..941d247809 --- /dev/null +++ b/hardware/board/config/brd4166c/sl_uartdrv_leuart_vcom_config.h @@ -0,0 +1,87 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_LEUART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_LEUART_VCOM_CONFIG_H +#define SL_UARTDRV_LEUART_VCOM_CONFIG_H + +#include "em_leuart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_LEUART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: leuartNoParity +#define SL_UARTDRV_LEUART_VCOM_PARITY leuartNoParity + +// Number of stop bits to use. +// 1 stop bits +// 2 stop bits +// Default: leuartStopbits1 +#define SL_UARTDRV_LEUART_VCOM_STOP_BITS leuartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHw +#define SL_UARTDRV_LEUART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlSw + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_LEUART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_LEUART_VCOM_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_LEUART_VCOM +// $[LEUART_SL_UARTDRV_LEUART_VCOM] +#define SL_UARTDRV_LEUART_VCOM_PERIPHERAL LEUART0 +#define SL_UARTDRV_LEUART_VCOM_PERIPHERAL_NO 0 + +// LEUART0 TX on PA0 +#define SL_UARTDRV_LEUART_VCOM_TX_PORT gpioPortA +#define SL_UARTDRV_LEUART_VCOM_TX_PIN 0 +#define SL_UARTDRV_LEUART_VCOM_TX_LOC 0 + +// LEUART0 RX on PA1 +#define SL_UARTDRV_LEUART_VCOM_RX_PORT gpioPortA +#define SL_UARTDRV_LEUART_VCOM_RX_PIN 1 +#define SL_UARTDRV_LEUART_VCOM_RX_LOC 0 + +// [LEUART_SL_UARTDRV_LEUART_VCOM]$ +// SL_UARTDRV_LEUART_VCOM_CTS +// $[GPIO_SL_UARTDRV_LEUART_VCOM_CTS] + +// [GPIO_SL_UARTDRV_LEUART_VCOM_CTS]$ + +// SL_UARTDRV_LEUART_VCOM_RTS +// $[GPIO_SL_UARTDRV_LEUART_VCOM_RTS] + +// [GPIO_SL_UARTDRV_LEUART_VCOM_RTS]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_LEUART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4166c/sl_uartdrv_usart_exp_config.h b/hardware/board/config/brd4166c/sl_uartdrv_usart_exp_config.h new file mode 100644 index 0000000000..a883de6b39 --- /dev/null +++ b/hardware/board/config/brd4166c/sl_uartdrv_usart_exp_config.h @@ -0,0 +1,95 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_EXP_CONFIG_H +#define SL_UARTDRV_USART_EXP_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_EXP_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_EXP_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHw +#define SL_UARTDRV_USART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_EXP_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_EXP_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_EXP +// $[USART_SL_UARTDRV_USART_EXP] +#define SL_UARTDRV_USART_EXP_PERIPHERAL USART0 +#define SL_UARTDRV_USART_EXP_PERIPHERAL_NO 0 + +// USART0 TX on PF3 +#define SL_UARTDRV_USART_EXP_TX_PORT gpioPortF +#define SL_UARTDRV_USART_EXP_TX_PIN 3 +#define SL_UARTDRV_USART_EXP_TX_LOC 27 + +// USART0 RX on PF4 +#define SL_UARTDRV_USART_EXP_RX_PORT gpioPortF +#define SL_UARTDRV_USART_EXP_RX_PIN 4 +#define SL_UARTDRV_USART_EXP_RX_LOC 27 + + + +// [USART_SL_UARTDRV_USART_EXP]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_USART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4166c/sl_uartdrv_usart_vcom_config.h b/hardware/board/config/brd4166c/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 0000000000..4dfd5e6180 --- /dev/null +++ b/hardware/board/config/brd4166c/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHw +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlSw + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART0 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 0 + +// USART0 TX on PA0 +#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_TX_PIN 0 +#define SL_UARTDRV_USART_VCOM_TX_LOC 0 + +// USART0 RX on PA1 +#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_RX_PIN 1 +#define SL_UARTDRV_USART_VCOM_RX_LOC 0 + +// USART0 CTS on PA2 +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_CTS_PIN 2 +#define SL_UARTDRV_USART_VCOM_CTS_LOC 30 + +// USART0 RTS on PA3 +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_RTS_PIN 3 +#define SL_UARTDRV_USART_VCOM_RTS_LOC 30 + +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4200a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h b/hardware/board/config/brd4200a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h deleted file mode 100644 index 047e862cdf..0000000000 --- a/hardware/board/config/brd4200a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h +++ /dev/null @@ -1,87 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_INST0_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_INST0 -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_INST0] -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL TIMER0 -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL_NO 0 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_CHANNEL 0 -// TIMER0 CC0 on PD10 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PIN 10 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_LOC 18 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_CHANNEL 1 -// TIMER0 CC1 on PD11 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PIN 11 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_LOC 18 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_CHANNEL 2 -// TIMER0 CC2 on PD12 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PIN 12 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_LOC 18 - -// [TIMER_SL_SIMPLE_RGB_PWM_LED_INST0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H diff --git a/hardware/board/config/brd4200a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h b/hardware/board/config/brd4200a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h new file mode 100644 index 0000000000..86fc036813 --- /dev/null +++ b/hardware/board/config/brd4200a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h @@ -0,0 +1,87 @@ +/***************************************************************************//** + * @file + * @brief Simple RGB PWM Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple RGB PWM LED Configuration +// PWM frequency [Hz] +// Sets the frequency of the PWM signal +// 0 = Don't care +// Default: 10000 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_FREQUENCY 10000 + +// PWM resolution <2-65536> +// Specifies the PWM (dimming) resolution. I.e. if you want a +// dimming resolution that takes the input values from 0 to 99, +// set this value to 100 +// Default: 256 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RESOLUTION 256 + +// Red LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Green LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Blue LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_RGB_PWM_LED_RGB_LED0 +// $[TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0] +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL TIMER0 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL_NO 0 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_CHANNEL 0 +// TIMER0 CC0 on PD10 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PIN 10 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_LOC 18 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_CHANNEL 1 +// TIMER0 CC1 on PD11 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PIN 11 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_LOC 18 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_CHANNEL 2 +// TIMER0 CC2 on PD12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PIN 12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_LOC 18 + +// [TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H diff --git a/hardware/board/config/brd4200a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h b/hardware/board/config/brd4200a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h deleted file mode 100644 index 047e862cdf..0000000000 --- a/hardware/board/config/brd4200a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h +++ /dev/null @@ -1,87 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_INST0_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_INST0 -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_INST0] -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL TIMER0 -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL_NO 0 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_CHANNEL 0 -// TIMER0 CC0 on PD10 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PIN 10 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_LOC 18 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_CHANNEL 1 -// TIMER0 CC1 on PD11 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PIN 11 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_LOC 18 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_CHANNEL 2 -// TIMER0 CC2 on PD12 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PIN 12 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_LOC 18 - -// [TIMER_SL_SIMPLE_RGB_PWM_LED_INST0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H diff --git a/hardware/board/config/brd4200a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h b/hardware/board/config/brd4200a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h new file mode 100644 index 0000000000..86fc036813 --- /dev/null +++ b/hardware/board/config/brd4200a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h @@ -0,0 +1,87 @@ +/***************************************************************************//** + * @file + * @brief Simple RGB PWM Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple RGB PWM LED Configuration +// PWM frequency [Hz] +// Sets the frequency of the PWM signal +// 0 = Don't care +// Default: 10000 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_FREQUENCY 10000 + +// PWM resolution <2-65536> +// Specifies the PWM (dimming) resolution. I.e. if you want a +// dimming resolution that takes the input values from 0 to 99, +// set this value to 100 +// Default: 256 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RESOLUTION 256 + +// Red LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Green LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Blue LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_RGB_PWM_LED_RGB_LED0 +// $[TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0] +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL TIMER0 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL_NO 0 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_CHANNEL 0 +// TIMER0 CC0 on PD10 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PIN 10 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_LOC 18 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_CHANNEL 1 +// TIMER0 CC1 on PD11 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PIN 11 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_LOC 18 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_CHANNEL 2 +// TIMER0 CC2 on PD12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PIN 12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_LOC 18 + +// [TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H diff --git a/hardware/board/config/brd4202a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h b/hardware/board/config/brd4202a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h deleted file mode 100644 index 047e862cdf..0000000000 --- a/hardware/board/config/brd4202a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h +++ /dev/null @@ -1,87 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_INST0_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_INST0 -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_INST0] -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL TIMER0 -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL_NO 0 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_CHANNEL 0 -// TIMER0 CC0 on PD10 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PIN 10 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_LOC 18 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_CHANNEL 1 -// TIMER0 CC1 on PD11 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PIN 11 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_LOC 18 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_CHANNEL 2 -// TIMER0 CC2 on PD12 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PIN 12 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_LOC 18 - -// [TIMER_SL_SIMPLE_RGB_PWM_LED_INST0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H diff --git a/hardware/board/config/brd4202a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h b/hardware/board/config/brd4202a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h new file mode 100644 index 0000000000..86fc036813 --- /dev/null +++ b/hardware/board/config/brd4202a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h @@ -0,0 +1,87 @@ +/***************************************************************************//** + * @file + * @brief Simple RGB PWM Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple RGB PWM LED Configuration +// PWM frequency [Hz] +// Sets the frequency of the PWM signal +// 0 = Don't care +// Default: 10000 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_FREQUENCY 10000 + +// PWM resolution <2-65536> +// Specifies the PWM (dimming) resolution. I.e. if you want a +// dimming resolution that takes the input values from 0 to 99, +// set this value to 100 +// Default: 256 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RESOLUTION 256 + +// Red LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Green LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Blue LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_RGB_PWM_LED_RGB_LED0 +// $[TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0] +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL TIMER0 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL_NO 0 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_CHANNEL 0 +// TIMER0 CC0 on PD10 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PIN 10 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_LOC 18 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_CHANNEL 1 +// TIMER0 CC1 on PD11 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PIN 11 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_LOC 18 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_CHANNEL 2 +// TIMER0 CC2 on PD12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PIN 12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_LOC 18 + +// [TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H diff --git a/hardware/board/config/brd4202a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h b/hardware/board/config/brd4202a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h deleted file mode 100644 index 047e862cdf..0000000000 --- a/hardware/board/config/brd4202a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h +++ /dev/null @@ -1,87 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_INST0_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_INST0 -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_INST0] -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL TIMER0 -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL_NO 0 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_CHANNEL 0 -// TIMER0 CC0 on PD10 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PIN 10 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_LOC 18 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_CHANNEL 1 -// TIMER0 CC1 on PD11 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PIN 11 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_LOC 18 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_CHANNEL 2 -// TIMER0 CC2 on PD12 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PIN 12 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_LOC 18 - -// [TIMER_SL_SIMPLE_RGB_PWM_LED_INST0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H diff --git a/hardware/board/config/brd4202a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h b/hardware/board/config/brd4202a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h new file mode 100644 index 0000000000..86fc036813 --- /dev/null +++ b/hardware/board/config/brd4202a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h @@ -0,0 +1,87 @@ +/***************************************************************************//** + * @file + * @brief Simple RGB PWM Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple RGB PWM LED Configuration +// PWM frequency [Hz] +// Sets the frequency of the PWM signal +// 0 = Don't care +// Default: 10000 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_FREQUENCY 10000 + +// PWM resolution <2-65536> +// Specifies the PWM (dimming) resolution. I.e. if you want a +// dimming resolution that takes the input values from 0 to 99, +// set this value to 100 +// Default: 256 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RESOLUTION 256 + +// Red LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Green LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Blue LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_RGB_PWM_LED_RGB_LED0 +// $[TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0] +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL TIMER0 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL_NO 0 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_CHANNEL 0 +// TIMER0 CC0 on PD10 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PIN 10 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_LOC 18 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_CHANNEL 1 +// TIMER0 CC1 on PD11 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PIN 11 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_LOC 18 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_CHANNEL 2 +// TIMER0 CC2 on PD12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PIN 12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_LOC 18 + +// [TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H diff --git a/hardware/board/config/brd4203a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h b/hardware/board/config/brd4203a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h deleted file mode 100644 index 047e862cdf..0000000000 --- a/hardware/board/config/brd4203a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h +++ /dev/null @@ -1,87 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_INST0_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_INST0 -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_INST0] -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL TIMER0 -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL_NO 0 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_CHANNEL 0 -// TIMER0 CC0 on PD10 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PIN 10 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_LOC 18 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_CHANNEL 1 -// TIMER0 CC1 on PD11 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PIN 11 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_LOC 18 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_CHANNEL 2 -// TIMER0 CC2 on PD12 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PIN 12 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_LOC 18 - -// [TIMER_SL_SIMPLE_RGB_PWM_LED_INST0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H diff --git a/hardware/board/config/brd4203a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h b/hardware/board/config/brd4203a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h new file mode 100644 index 0000000000..86fc036813 --- /dev/null +++ b/hardware/board/config/brd4203a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h @@ -0,0 +1,87 @@ +/***************************************************************************//** + * @file + * @brief Simple RGB PWM Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple RGB PWM LED Configuration +// PWM frequency [Hz] +// Sets the frequency of the PWM signal +// 0 = Don't care +// Default: 10000 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_FREQUENCY 10000 + +// PWM resolution <2-65536> +// Specifies the PWM (dimming) resolution. I.e. if you want a +// dimming resolution that takes the input values from 0 to 99, +// set this value to 100 +// Default: 256 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RESOLUTION 256 + +// Red LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Green LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Blue LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_RGB_PWM_LED_RGB_LED0 +// $[TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0] +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL TIMER0 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL_NO 0 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_CHANNEL 0 +// TIMER0 CC0 on PD10 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PIN 10 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_LOC 18 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_CHANNEL 1 +// TIMER0 CC1 on PD11 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PIN 11 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_LOC 18 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_CHANNEL 2 +// TIMER0 CC2 on PD12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PIN 12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_LOC 18 + +// [TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H diff --git a/hardware/board/config/brd4203a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h b/hardware/board/config/brd4203a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h deleted file mode 100644 index 047e862cdf..0000000000 --- a/hardware/board/config/brd4203a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h +++ /dev/null @@ -1,87 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_INST0_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_INST0 -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_INST0] -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL TIMER0 -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL_NO 0 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_CHANNEL 0 -// TIMER0 CC0 on PD10 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PIN 10 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_LOC 18 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_CHANNEL 1 -// TIMER0 CC1 on PD11 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PIN 11 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_LOC 18 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_CHANNEL 2 -// TIMER0 CC2 on PD12 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PIN 12 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_LOC 18 - -// [TIMER_SL_SIMPLE_RGB_PWM_LED_INST0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H diff --git a/hardware/board/config/brd4203a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h b/hardware/board/config/brd4203a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h new file mode 100644 index 0000000000..86fc036813 --- /dev/null +++ b/hardware/board/config/brd4203a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h @@ -0,0 +1,87 @@ +/***************************************************************************//** + * @file + * @brief Simple RGB PWM Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple RGB PWM LED Configuration +// PWM frequency [Hz] +// Sets the frequency of the PWM signal +// 0 = Don't care +// Default: 10000 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_FREQUENCY 10000 + +// PWM resolution <2-65536> +// Specifies the PWM (dimming) resolution. I.e. if you want a +// dimming resolution that takes the input values from 0 to 99, +// set this value to 100 +// Default: 256 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RESOLUTION 256 + +// Red LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Green LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Blue LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_RGB_PWM_LED_RGB_LED0 +// $[TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0] +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL TIMER0 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL_NO 0 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_CHANNEL 0 +// TIMER0 CC0 on PD10 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PIN 10 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_LOC 18 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_CHANNEL 1 +// TIMER0 CC1 on PD11 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PIN 11 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_LOC 18 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_CHANNEL 2 +// TIMER0 CC2 on PD12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PIN 12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_LOC 18 + +// [TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H diff --git a/hardware/board/config/brd4205a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h b/hardware/board/config/brd4205a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h deleted file mode 100644 index dcb06e3f9d..0000000000 --- a/hardware/board/config/brd4205a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_INST0_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_INST0 -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_INST0] -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL TIMER0 -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL_NO 0 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_CHANNEL 0 -// TIMER0 CC0 on PB04 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PORT gpioPortB -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PIN 4 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_CHANNEL 1 -// TIMER0 CC1 on PB05 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PORT gpioPortB -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PIN 5 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_CHANNEL 2 -// TIMER0 CC2 on PB06 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PORT gpioPortB -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PIN 6 - -// [TIMER_SL_SIMPLE_RGB_PWM_LED_INST0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H diff --git a/hardware/board/config/brd4205a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h b/hardware/board/config/brd4205a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h new file mode 100644 index 0000000000..512cfe4a0a --- /dev/null +++ b/hardware/board/config/brd4205a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief Simple RGB PWM Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple RGB PWM LED Configuration +// PWM frequency [Hz] +// Sets the frequency of the PWM signal +// 0 = Don't care +// Default: 10000 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_FREQUENCY 10000 + +// PWM resolution <2-65536> +// Specifies the PWM (dimming) resolution. I.e. if you want a +// dimming resolution that takes the input values from 0 to 99, +// set this value to 100 +// Default: 256 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RESOLUTION 256 + +// Red LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Green LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Blue LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_RGB_PWM_LED_RGB_LED0 +// $[TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0] +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL TIMER0 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL_NO 0 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_CHANNEL 0 +// TIMER0 CC0 on PB04 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PIN 4 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_CHANNEL 1 +// TIMER0 CC1 on PB05 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PIN 5 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_CHANNEL 2 +// TIMER0 CC2 on PB06 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PIN 6 + +// [TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H diff --git a/hardware/board/config/brd4205a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h b/hardware/board/config/brd4205a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h deleted file mode 100644 index dcb06e3f9d..0000000000 --- a/hardware/board/config/brd4205a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_INST0_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_INST0 -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_INST0] -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL TIMER0 -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL_NO 0 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_CHANNEL 0 -// TIMER0 CC0 on PB04 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PORT gpioPortB -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PIN 4 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_CHANNEL 1 -// TIMER0 CC1 on PB05 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PORT gpioPortB -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PIN 5 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_CHANNEL 2 -// TIMER0 CC2 on PB06 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PORT gpioPortB -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PIN 6 - -// [TIMER_SL_SIMPLE_RGB_PWM_LED_INST0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H diff --git a/hardware/board/config/brd4205a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h b/hardware/board/config/brd4205a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h new file mode 100644 index 0000000000..512cfe4a0a --- /dev/null +++ b/hardware/board/config/brd4205a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief Simple RGB PWM Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple RGB PWM LED Configuration +// PWM frequency [Hz] +// Sets the frequency of the PWM signal +// 0 = Don't care +// Default: 10000 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_FREQUENCY 10000 + +// PWM resolution <2-65536> +// Specifies the PWM (dimming) resolution. I.e. if you want a +// dimming resolution that takes the input values from 0 to 99, +// set this value to 100 +// Default: 256 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RESOLUTION 256 + +// Red LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Green LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Blue LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_RGB_PWM_LED_RGB_LED0 +// $[TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0] +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL TIMER0 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL_NO 0 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_CHANNEL 0 +// TIMER0 CC0 on PB04 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PIN 4 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_CHANNEL 1 +// TIMER0 CC1 on PB05 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PIN 5 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_CHANNEL 2 +// TIMER0 CC2 on PB06 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PIN 6 + +// [TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H diff --git a/hardware/board/config/brd4205b_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h b/hardware/board/config/brd4205b_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h deleted file mode 100644 index dcb06e3f9d..0000000000 --- a/hardware/board/config/brd4205b_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_INST0_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_INST0 -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_INST0] -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL TIMER0 -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL_NO 0 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_CHANNEL 0 -// TIMER0 CC0 on PB04 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PORT gpioPortB -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PIN 4 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_CHANNEL 1 -// TIMER0 CC1 on PB05 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PORT gpioPortB -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PIN 5 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_CHANNEL 2 -// TIMER0 CC2 on PB06 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PORT gpioPortB -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PIN 6 - -// [TIMER_SL_SIMPLE_RGB_PWM_LED_INST0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H diff --git a/hardware/board/config/brd4205b_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h b/hardware/board/config/brd4205b_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h new file mode 100644 index 0000000000..512cfe4a0a --- /dev/null +++ b/hardware/board/config/brd4205b_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief Simple RGB PWM Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple RGB PWM LED Configuration +// PWM frequency [Hz] +// Sets the frequency of the PWM signal +// 0 = Don't care +// Default: 10000 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_FREQUENCY 10000 + +// PWM resolution <2-65536> +// Specifies the PWM (dimming) resolution. I.e. if you want a +// dimming resolution that takes the input values from 0 to 99, +// set this value to 100 +// Default: 256 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RESOLUTION 256 + +// Red LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Green LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Blue LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_RGB_PWM_LED_RGB_LED0 +// $[TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0] +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL TIMER0 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL_NO 0 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_CHANNEL 0 +// TIMER0 CC0 on PB04 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PIN 4 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_CHANNEL 1 +// TIMER0 CC1 on PB05 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PIN 5 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_CHANNEL 2 +// TIMER0 CC2 on PB06 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PIN 6 + +// [TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H diff --git a/hardware/board/config/brd4205b_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h b/hardware/board/config/brd4205b_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h deleted file mode 100644 index dcb06e3f9d..0000000000 --- a/hardware/board/config/brd4205b_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_INST0_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_INST0 -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_INST0] -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL TIMER0 -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL_NO 0 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_CHANNEL 0 -// TIMER0 CC0 on PB04 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PORT gpioPortB -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PIN 4 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_CHANNEL 1 -// TIMER0 CC1 on PB05 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PORT gpioPortB -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PIN 5 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_CHANNEL 2 -// TIMER0 CC2 on PB06 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PORT gpioPortB -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PIN 6 - -// [TIMER_SL_SIMPLE_RGB_PWM_LED_INST0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H diff --git a/hardware/board/config/brd4205b_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h b/hardware/board/config/brd4205b_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h new file mode 100644 index 0000000000..512cfe4a0a --- /dev/null +++ b/hardware/board/config/brd4205b_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief Simple RGB PWM Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple RGB PWM LED Configuration +// PWM frequency [Hz] +// Sets the frequency of the PWM signal +// 0 = Don't care +// Default: 10000 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_FREQUENCY 10000 + +// PWM resolution <2-65536> +// Specifies the PWM (dimming) resolution. I.e. if you want a +// dimming resolution that takes the input values from 0 to 99, +// set this value to 100 +// Default: 256 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RESOLUTION 256 + +// Red LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Green LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Blue LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_RGB_PWM_LED_RGB_LED0 +// $[TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0] +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL TIMER0 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL_NO 0 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_CHANNEL 0 +// TIMER0 CC0 on PB04 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PIN 4 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_CHANNEL 1 +// TIMER0 CC1 on PB05 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PIN 5 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_CHANNEL 2 +// TIMER0 CC2 on PB06 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PIN 6 + +// [TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H diff --git a/hardware/board/config/brd4207a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h b/hardware/board/config/brd4207a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h deleted file mode 100644 index 047e862cdf..0000000000 --- a/hardware/board/config/brd4207a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h +++ /dev/null @@ -1,87 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_INST0_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_INST0 -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_INST0] -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL TIMER0 -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL_NO 0 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_CHANNEL 0 -// TIMER0 CC0 on PD10 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PIN 10 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_LOC 18 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_CHANNEL 1 -// TIMER0 CC1 on PD11 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PIN 11 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_LOC 18 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_CHANNEL 2 -// TIMER0 CC2 on PD12 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PIN 12 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_LOC 18 - -// [TIMER_SL_SIMPLE_RGB_PWM_LED_INST0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H diff --git a/hardware/board/config/brd4207a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h b/hardware/board/config/brd4207a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h new file mode 100644 index 0000000000..86fc036813 --- /dev/null +++ b/hardware/board/config/brd4207a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h @@ -0,0 +1,87 @@ +/***************************************************************************//** + * @file + * @brief Simple RGB PWM Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple RGB PWM LED Configuration +// PWM frequency [Hz] +// Sets the frequency of the PWM signal +// 0 = Don't care +// Default: 10000 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_FREQUENCY 10000 + +// PWM resolution <2-65536> +// Specifies the PWM (dimming) resolution. I.e. if you want a +// dimming resolution that takes the input values from 0 to 99, +// set this value to 100 +// Default: 256 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RESOLUTION 256 + +// Red LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Green LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Blue LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_RGB_PWM_LED_RGB_LED0 +// $[TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0] +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL TIMER0 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL_NO 0 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_CHANNEL 0 +// TIMER0 CC0 on PD10 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PIN 10 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_LOC 18 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_CHANNEL 1 +// TIMER0 CC1 on PD11 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PIN 11 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_LOC 18 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_CHANNEL 2 +// TIMER0 CC2 on PD12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PIN 12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_LOC 18 + +// [TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H diff --git a/hardware/board/config/brd4207a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h b/hardware/board/config/brd4207a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h deleted file mode 100644 index 047e862cdf..0000000000 --- a/hardware/board/config/brd4207a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h +++ /dev/null @@ -1,87 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_INST0_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_INST0 -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_INST0] -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL TIMER0 -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL_NO 0 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_CHANNEL 0 -// TIMER0 CC0 on PD10 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PIN 10 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_LOC 18 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_CHANNEL 1 -// TIMER0 CC1 on PD11 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PIN 11 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_LOC 18 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_CHANNEL 2 -// TIMER0 CC2 on PD12 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PIN 12 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_LOC 18 - -// [TIMER_SL_SIMPLE_RGB_PWM_LED_INST0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H diff --git a/hardware/board/config/brd4207a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h b/hardware/board/config/brd4207a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h new file mode 100644 index 0000000000..86fc036813 --- /dev/null +++ b/hardware/board/config/brd4207a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h @@ -0,0 +1,87 @@ +/***************************************************************************//** + * @file + * @brief Simple RGB PWM Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple RGB PWM LED Configuration +// PWM frequency [Hz] +// Sets the frequency of the PWM signal +// 0 = Don't care +// Default: 10000 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_FREQUENCY 10000 + +// PWM resolution <2-65536> +// Specifies the PWM (dimming) resolution. I.e. if you want a +// dimming resolution that takes the input values from 0 to 99, +// set this value to 100 +// Default: 256 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RESOLUTION 256 + +// Red LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Green LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Blue LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_RGB_PWM_LED_RGB_LED0 +// $[TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0] +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL TIMER0 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL_NO 0 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_CHANNEL 0 +// TIMER0 CC0 on PD10 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PIN 10 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_LOC 18 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_CHANNEL 1 +// TIMER0 CC1 on PD11 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PIN 11 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_LOC 18 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_CHANNEL 2 +// TIMER0 CC2 on PD12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PIN 12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_LOC 18 + +// [TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H diff --git a/hardware/board/config/brd4209a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h b/hardware/board/config/brd4209a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h deleted file mode 100644 index 047e862cdf..0000000000 --- a/hardware/board/config/brd4209a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h +++ /dev/null @@ -1,87 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_INST0_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_INST0 -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_INST0] -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL TIMER0 -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL_NO 0 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_CHANNEL 0 -// TIMER0 CC0 on PD10 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PIN 10 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_LOC 18 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_CHANNEL 1 -// TIMER0 CC1 on PD11 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PIN 11 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_LOC 18 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_CHANNEL 2 -// TIMER0 CC2 on PD12 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PIN 12 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_LOC 18 - -// [TIMER_SL_SIMPLE_RGB_PWM_LED_INST0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H diff --git a/hardware/board/config/brd4209a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h b/hardware/board/config/brd4209a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h new file mode 100644 index 0000000000..86fc036813 --- /dev/null +++ b/hardware/board/config/brd4209a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h @@ -0,0 +1,87 @@ +/***************************************************************************//** + * @file + * @brief Simple RGB PWM Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple RGB PWM LED Configuration +// PWM frequency [Hz] +// Sets the frequency of the PWM signal +// 0 = Don't care +// Default: 10000 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_FREQUENCY 10000 + +// PWM resolution <2-65536> +// Specifies the PWM (dimming) resolution. I.e. if you want a +// dimming resolution that takes the input values from 0 to 99, +// set this value to 100 +// Default: 256 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RESOLUTION 256 + +// Red LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Green LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Blue LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_RGB_PWM_LED_RGB_LED0 +// $[TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0] +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL TIMER0 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL_NO 0 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_CHANNEL 0 +// TIMER0 CC0 on PD10 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PIN 10 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_LOC 18 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_CHANNEL 1 +// TIMER0 CC1 on PD11 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PIN 11 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_LOC 18 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_CHANNEL 2 +// TIMER0 CC2 on PD12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PIN 12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_LOC 18 + +// [TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H diff --git a/hardware/board/config/brd4209a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h b/hardware/board/config/brd4209a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h deleted file mode 100644 index 047e862cdf..0000000000 --- a/hardware/board/config/brd4209a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h +++ /dev/null @@ -1,87 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_INST0_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_INST0 -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_INST0] -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL TIMER0 -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL_NO 0 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_CHANNEL 0 -// TIMER0 CC0 on PD10 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PIN 10 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_LOC 18 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_CHANNEL 1 -// TIMER0 CC1 on PD11 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PIN 11 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_LOC 18 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_CHANNEL 2 -// TIMER0 CC2 on PD12 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PORT gpioPortD -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PIN 12 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_LOC 18 - -// [TIMER_SL_SIMPLE_RGB_PWM_LED_INST0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H diff --git a/hardware/board/config/brd4209a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h b/hardware/board/config/brd4209a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h new file mode 100644 index 0000000000..86fc036813 --- /dev/null +++ b/hardware/board/config/brd4209a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h @@ -0,0 +1,87 @@ +/***************************************************************************//** + * @file + * @brief Simple RGB PWM Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple RGB PWM LED Configuration +// PWM frequency [Hz] +// Sets the frequency of the PWM signal +// 0 = Don't care +// Default: 10000 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_FREQUENCY 10000 + +// PWM resolution <2-65536> +// Specifies the PWM (dimming) resolution. I.e. if you want a +// dimming resolution that takes the input values from 0 to 99, +// set this value to 100 +// Default: 256 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RESOLUTION 256 + +// Red LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Green LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Blue LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_RGB_PWM_LED_RGB_LED0 +// $[TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0] +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL TIMER0 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL_NO 0 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_CHANNEL 0 +// TIMER0 CC0 on PD10 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PIN 10 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_LOC 18 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_CHANNEL 1 +// TIMER0 CC1 on PD11 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PIN 11 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_LOC 18 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_CHANNEL 2 +// TIMER0 CC2 on PD12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PORT gpioPortD +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PIN 12 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_LOC 18 + +// [TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H diff --git a/hardware/board/config/brd4272a_brd4001a/btl_ezsp_gpio_activation_cfg.h b/hardware/board/config/brd4272a_brd4001a/btl_ezsp_gpio_activation_cfg.h deleted file mode 100644 index c8016ffd03..0000000000 --- a/hardware/board/config/brd4272a_brd4001a/btl_ezsp_gpio_activation_cfg.h +++ /dev/null @@ -1,52 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader EZSP GPIO Activation - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_EZSP_GPIO_ACTIVATION_CONFIG_H -#define BTL_EZSP_GPIO_ACTIVATION_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Properties of SPI NCP - -// Active state -// Low -// High -// Default: LOW -// Enter firmware upgrade mode if GPIO pin has this state -#define SL_EZSP_GPIO_ACTIVATION_POLARITY LOW - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_EZSPSPI_HOST_INT -// $[GPIO_SL_EZSPSPI_HOST_INT] -#define SL_EZSPSPI_HOST_INT_PORT gpioPortA -#define SL_EZSPSPI_HOST_INT_PIN 5 - -// [GPIO_SL_EZSPSPI_HOST_INT]$ - -// SL_EZSPSPI_WAKE_INT -// $[GPIO_SL_EZSPSPI_WAKE_INT] -#define SL_EZSPSPI_WAKE_INT_PORT gpioPortD -#define SL_EZSPSPI_WAKE_INT_PIN 2 - -// [GPIO_SL_EZSPSPI_WAKE_INT]$ - -// <<< sl:end pin_tool >>> - -#endif // BTL_EZSP_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4272a_brd4001a/sl_board_control_config.h b/hardware/board/config/brd4272a_brd4001a/sl_board_control_config.h index 7e397c16da..e6c097ee72 100644 --- a/hardware/board/config/brd4272a_brd4001a/sl_board_control_config.h +++ b/hardware/board/config/brd4272a_brd4001a/sl_board_control_config.h @@ -41,10 +41,6 @@ // Default: 0 #define SL_BOARD_ENABLE_DISPLAY 0 -// Enable Relative Humidity and Temperature sensor -// Default: 0 -#define SL_BOARD_ENABLE_SENSOR_RHT 0 - // Disable SPI Flash // Default: 1 #define SL_BOARD_DISABLE_MEMORY_SPI 1 @@ -65,12 +61,6 @@ #define SL_BOARD_ENABLE_DISPLAY_PIN 5 // [GPIO_SL_BOARD_ENABLE_DISPLAY]$ -// SL_BOARD_ENABLE_SENSOR_RHT -// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] -#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortC -#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 8 -// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ - // <<< sl:end pin_tool >>> #endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/hardware/board/config/brd4272a_brd4001a/sl_i2cspm_sensor_config.h b/hardware/board/config/brd4272a_brd4001a/sl_i2cspm_sensor_config.h deleted file mode 100644 index 738fcafa39..0000000000 --- a/hardware/board/config/brd4272a_brd4001a/sl_i2cspm_sensor_config.h +++ /dev/null @@ -1,58 +0,0 @@ -/***************************************************************************//** - * @file - * @brief I2CSPM Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_I2CSPM_SENSOR_CONFIG_H -#define SL_I2CSPM_SENSOR_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu - -// I2CSPM settings - -// Reference clock frequency -// Frequency in Hz of the reference clock. -// Select 0 to use the frequency of the currently selected clock. -// Default: 0 -#define SL_I2CSPM_SENSOR_REFERENCE_CLOCK 0 - -// Speed mode -// <0=> Standard mode (100kbit/s) -// <1=> Fast mode (400kbit/s) -// <2=> Fast mode plus (1Mbit/s) -// Default: 0 -#define SL_I2CSPM_SENSOR_SPEED_MODE 0 -// end I2CSPM config - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_I2CSPM_SENSOR -// $[I2C_SL_I2CSPM_SENSOR] -#define SL_I2CSPM_SENSOR_PERIPHERAL I2C0 -#define SL_I2CSPM_SENSOR_PERIPHERAL_NO 0 - -// I2C0 SCL on PB02 -#define SL_I2CSPM_SENSOR_SCL_PORT gpioPortB -#define SL_I2CSPM_SENSOR_SCL_PIN 2 - -// I2C0 SDA on PB03 -#define SL_I2CSPM_SENSOR_SDA_PORT gpioPortB -#define SL_I2CSPM_SENSOR_SDA_PIN 3 - -// [I2C_SL_I2CSPM_SENSOR]$ -// <<< sl:end pin_tool >>> - -#endif // SL_I2CSPM_SENSOR_CONFIG_H diff --git a/hardware/board/config/brd4272a_brd4001a/sl_memlcd_eusart_config.h b/hardware/board/config/brd4272a_brd4001a/sl_memlcd_eusart_config.h index 98e9e81201..2ec869c464 100644 --- a/hardware/board/config/brd4272a_brd4001a/sl_memlcd_eusart_config.h +++ b/hardware/board/config/brd4272a_brd4001a/sl_memlcd_eusart_config.h @@ -44,7 +44,7 @@ // SL_MEMLCD_EXTCOMIN // $[GPIO_SL_MEMLCD_EXTCOMIN] #define SL_MEMLCD_EXTCOMIN_PORT gpioPortC -#define SL_MEMLCD_EXTCOMIN_PIN 9 +#define SL_MEMLCD_EXTCOMIN_PIN 8 // [GPIO_SL_MEMLCD_EXTCOMIN]$ diff --git a/hardware/board/config/brd4272a_brd4001a/sl_usbd_driver_config.h b/hardware/board/config/brd4272a_brd4001a/sl_usbd_driver_config.h new file mode 100644 index 0000000000..005a845bd2 --- /dev/null +++ b/hardware/board/config/brd4272a_brd4001a/sl_usbd_driver_config.h @@ -0,0 +1,30 @@ +/***************************************************************************//** + * @file + * @brief USBD Hardware Configuration + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_USBD_DRIVER_CONFIG_H +#define SL_USBD_DRIVER_CONFIG_H + +// <<< sl:start pin_tool >>> +// SL_USBD_DRIVER_VBUS_SENSE +// $[GPIO_SL_USBD_DRIVER_VBUS_SENSE] +#define SL_USBD_DRIVER_VBUS_SENSE_PORT gpioPortD +#define SL_USBD_DRIVER_VBUS_SENSE_PIN 2 + +// [GPIO_SL_USBD_DRIVER_VBUS_SENSE]$ +// <<< sl:end pin_tool >>> + +#endif // SL_USBD_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4272a_brd4002a/btl_ezsp_gpio_activation_cfg.h b/hardware/board/config/brd4272a_brd4002a/btl_ezsp_gpio_activation_cfg.h deleted file mode 100644 index c8016ffd03..0000000000 --- a/hardware/board/config/brd4272a_brd4002a/btl_ezsp_gpio_activation_cfg.h +++ /dev/null @@ -1,52 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Configuration header for bootloader EZSP GPIO Activation - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_EZSP_GPIO_ACTIVATION_CONFIG_H -#define BTL_EZSP_GPIO_ACTIVATION_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Properties of SPI NCP - -// Active state -// Low -// High -// Default: LOW -// Enter firmware upgrade mode if GPIO pin has this state -#define SL_EZSP_GPIO_ACTIVATION_POLARITY LOW - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_EZSPSPI_HOST_INT -// $[GPIO_SL_EZSPSPI_HOST_INT] -#define SL_EZSPSPI_HOST_INT_PORT gpioPortA -#define SL_EZSPSPI_HOST_INT_PIN 5 - -// [GPIO_SL_EZSPSPI_HOST_INT]$ - -// SL_EZSPSPI_WAKE_INT -// $[GPIO_SL_EZSPSPI_WAKE_INT] -#define SL_EZSPSPI_WAKE_INT_PORT gpioPortD -#define SL_EZSPSPI_WAKE_INT_PIN 2 - -// [GPIO_SL_EZSPSPI_WAKE_INT]$ - -// <<< sl:end pin_tool >>> - -#endif // BTL_EZSP_GPIO_ACTIVATION_CONFIG_H diff --git a/hardware/board/config/brd4272a_brd4002a/sl_board_control_config.h b/hardware/board/config/brd4272a_brd4002a/sl_board_control_config.h index 7e397c16da..e6c097ee72 100644 --- a/hardware/board/config/brd4272a_brd4002a/sl_board_control_config.h +++ b/hardware/board/config/brd4272a_brd4002a/sl_board_control_config.h @@ -41,10 +41,6 @@ // Default: 0 #define SL_BOARD_ENABLE_DISPLAY 0 -// Enable Relative Humidity and Temperature sensor -// Default: 0 -#define SL_BOARD_ENABLE_SENSOR_RHT 0 - // Disable SPI Flash // Default: 1 #define SL_BOARD_DISABLE_MEMORY_SPI 1 @@ -65,12 +61,6 @@ #define SL_BOARD_ENABLE_DISPLAY_PIN 5 // [GPIO_SL_BOARD_ENABLE_DISPLAY]$ -// SL_BOARD_ENABLE_SENSOR_RHT -// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] -#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortC -#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 8 -// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ - // <<< sl:end pin_tool >>> #endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/hardware/board/config/brd4272a_brd4002a/sl_i2cspm_sensor_config.h b/hardware/board/config/brd4272a_brd4002a/sl_i2cspm_sensor_config.h deleted file mode 100644 index 738fcafa39..0000000000 --- a/hardware/board/config/brd4272a_brd4002a/sl_i2cspm_sensor_config.h +++ /dev/null @@ -1,58 +0,0 @@ -/***************************************************************************//** - * @file - * @brief I2CSPM Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_I2CSPM_SENSOR_CONFIG_H -#define SL_I2CSPM_SENSOR_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu - -// I2CSPM settings - -// Reference clock frequency -// Frequency in Hz of the reference clock. -// Select 0 to use the frequency of the currently selected clock. -// Default: 0 -#define SL_I2CSPM_SENSOR_REFERENCE_CLOCK 0 - -// Speed mode -// <0=> Standard mode (100kbit/s) -// <1=> Fast mode (400kbit/s) -// <2=> Fast mode plus (1Mbit/s) -// Default: 0 -#define SL_I2CSPM_SENSOR_SPEED_MODE 0 -// end I2CSPM config - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_I2CSPM_SENSOR -// $[I2C_SL_I2CSPM_SENSOR] -#define SL_I2CSPM_SENSOR_PERIPHERAL I2C0 -#define SL_I2CSPM_SENSOR_PERIPHERAL_NO 0 - -// I2C0 SCL on PB02 -#define SL_I2CSPM_SENSOR_SCL_PORT gpioPortB -#define SL_I2CSPM_SENSOR_SCL_PIN 2 - -// I2C0 SDA on PB03 -#define SL_I2CSPM_SENSOR_SDA_PORT gpioPortB -#define SL_I2CSPM_SENSOR_SDA_PIN 3 - -// [I2C_SL_I2CSPM_SENSOR]$ -// <<< sl:end pin_tool >>> - -#endif // SL_I2CSPM_SENSOR_CONFIG_H diff --git a/hardware/board/config/brd4272a_brd4002a/sl_memlcd_eusart_config.h b/hardware/board/config/brd4272a_brd4002a/sl_memlcd_eusart_config.h index 98e9e81201..2ec869c464 100644 --- a/hardware/board/config/brd4272a_brd4002a/sl_memlcd_eusart_config.h +++ b/hardware/board/config/brd4272a_brd4002a/sl_memlcd_eusart_config.h @@ -44,7 +44,7 @@ // SL_MEMLCD_EXTCOMIN // $[GPIO_SL_MEMLCD_EXTCOMIN] #define SL_MEMLCD_EXTCOMIN_PORT gpioPortC -#define SL_MEMLCD_EXTCOMIN_PIN 9 +#define SL_MEMLCD_EXTCOMIN_PIN 8 // [GPIO_SL_MEMLCD_EXTCOMIN]$ diff --git a/hardware/board/config/brd4272a_brd4002a/sl_usbd_driver_config.h b/hardware/board/config/brd4272a_brd4002a/sl_usbd_driver_config.h new file mode 100644 index 0000000000..005a845bd2 --- /dev/null +++ b/hardware/board/config/brd4272a_brd4002a/sl_usbd_driver_config.h @@ -0,0 +1,30 @@ +/***************************************************************************//** + * @file + * @brief USBD Hardware Configuration + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_USBD_DRIVER_CONFIG_H +#define SL_USBD_DRIVER_CONFIG_H + +// <<< sl:start pin_tool >>> +// SL_USBD_DRIVER_VBUS_SENSE +// $[GPIO_SL_USBD_DRIVER_VBUS_SENSE] +#define SL_USBD_DRIVER_VBUS_SENSE_PORT gpioPortD +#define SL_USBD_DRIVER_VBUS_SENSE_PIN 2 + +// [GPIO_SL_USBD_DRIVER_VBUS_SENSE]$ +// <<< sl:end pin_tool >>> + +#endif // SL_USBD_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4273a_brd4001a/sl_rail_util_eff_config.h b/hardware/board/config/brd4273a_brd4001a/sl_rail_util_eff_config.h index 432078484d..f34e43c03c 100644 --- a/hardware/board/config/brd4273a_brd4001a/sl_rail_util_eff_config.h +++ b/hardware/board/config/brd4273a_brd4001a/sl_rail_util_eff_config.h @@ -100,11 +100,11 @@ // Default: 50 #define RAIL_UTIL_EFF_MAX_TX_DUTY_CYCLE 50 // Temperature of EFF above which transmit is not allowed, in degrees Kelvin -// <1-373:1> +// <1-398:1> // Default: 373 #define SL_RAIL_UTIL_EFF_TEMPERATURE_THRESHOLD_EFF_DEGREES_K 373 -// Chip's internal temperature above which continuous transmit is aborted, in degrees Kelvin -// <1-373:1> +// Chip's internal temperature above which transmit is not allowed, in degrees Kelvin +// <1-398:1> // Default: 373 #define SL_RAIL_UTIL_EFF_TEMPERATURE_THRESHOLD_INTERNAL_DEGREES_K 373 // diff --git a/hardware/board/config/brd4273a_brd4002a/sl_rail_util_eff_config.h b/hardware/board/config/brd4273a_brd4002a/sl_rail_util_eff_config.h index 432078484d..f34e43c03c 100644 --- a/hardware/board/config/brd4273a_brd4002a/sl_rail_util_eff_config.h +++ b/hardware/board/config/brd4273a_brd4002a/sl_rail_util_eff_config.h @@ -100,11 +100,11 @@ // Default: 50 #define RAIL_UTIL_EFF_MAX_TX_DUTY_CYCLE 50 // Temperature of EFF above which transmit is not allowed, in degrees Kelvin -// <1-373:1> +// <1-398:1> // Default: 373 #define SL_RAIL_UTIL_EFF_TEMPERATURE_THRESHOLD_EFF_DEGREES_K 373 -// Chip's internal temperature above which continuous transmit is aborted, in degrees Kelvin -// <1-373:1> +// Chip's internal temperature above which transmit is not allowed, in degrees Kelvin +// <1-398:1> // Default: 373 #define SL_RAIL_UTIL_EFF_TEMPERATURE_THRESHOLD_INTERNAL_DEGREES_K 373 // diff --git a/hardware/board/config/brd4274a_brd4001a/btl_euart_driver_cfg.h b/hardware/board/config/brd4274a_brd4001a/btl_euart_driver_cfg.h new file mode 100644 index 0000000000..8aa666844c --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/btl_euart_driver_cfg.h @@ -0,0 +1,88 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader euart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_EUART_DRIVER_CONFIG_H +#define BTL_EUART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_EUART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_EUART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_EUART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_EUART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_EUART +// $[EUSART_SL_SERIAL_EUART] +#define SL_SERIAL_EUART_PERIPHERAL EUSART0 +#define SL_SERIAL_EUART_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_SERIAL_EUART_TX_PORT gpioPortA +#define SL_SERIAL_EUART_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_SERIAL_EUART_RX_PORT gpioPortA +#define SL_SERIAL_EUART_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_SERIAL_EUART_CTS_PORT gpioPortA +#define SL_SERIAL_EUART_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_SERIAL_EUART_RTS_PORT gpioPortA +#define SL_SERIAL_EUART_RTS_PIN 0 + +// [EUSART_SL_SERIAL_EUART]$ + + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] +#define SL_VCOM_ENABLE_PORT gpioPortA +#define SL_VCOM_ENABLE_PIN 11 + +// [GPIO_SL_VCOM_ENABLE]$ + + +// <<< sl:end pin_tool >>> + +#endif // BTL_EUART_DRIVER_CONFIG_H \ No newline at end of file diff --git a/hardware/board/config/brd4109a_brd4001a/btl_gpio_activation_cfg.h b/hardware/board/config/brd4274a_brd4001a/btl_gpio_activation_cfg.h similarity index 100% rename from hardware/board/config/brd4109a_brd4001a/btl_gpio_activation_cfg.h rename to hardware/board/config/brd4274a_brd4001a/btl_gpio_activation_cfg.h diff --git a/hardware/board/config/brd4274a_brd4001a/btl_spi_controller_eusart_driver_cfg.h b/hardware/board/config/brd4274a_brd4001a/btl_spi_controller_eusart_driver_cfg.h new file mode 100644 index 0000000000..e20e00a304 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/btl_spi_controller_eusart_driver_cfg.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Controller Eusart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H +#define BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Controller EUSART Driver + +// Frequency +// Default: 6400000 +#define SL_EUSART_EXTFLASH_FREQUENCY 6400000 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_EUSART_EXTFLASH +// $[EUSART_SL_EUSART_EXTFLASH] +#define SL_EUSART_EXTFLASH_PERIPHERAL EUSART1 +#define SL_EUSART_EXTFLASH_PERIPHERAL_NO 1 + +// EUSART1 TX on PC00 +#define SL_EUSART_EXTFLASH_TX_PORT gpioPortC +#define SL_EUSART_EXTFLASH_TX_PIN 0 + +// EUSART1 RX on PC01 +#define SL_EUSART_EXTFLASH_RX_PORT gpioPortC +#define SL_EUSART_EXTFLASH_RX_PIN 1 + +// EUSART1 SCLK on PC02 +#define SL_EUSART_EXTFLASH_SCLK_PORT gpioPortC +#define SL_EUSART_EXTFLASH_SCLK_PIN 2 + +// EUSART1 CS on PA04 +#define SL_EUSART_EXTFLASH_CS_PORT gpioPortA +#define SL_EUSART_EXTFLASH_CS_PIN 4 + +// [EUSART_SL_EUSART_EXTFLASH]$ + +// SL_EXTFLASH_WP +// $[GPIO_SL_EXTFLASH_WP] + +// [GPIO_SL_EXTFLASH_WP]$ + +// SL_EXTFLASH_HOLD +// $[GPIO_SL_EXTFLASH_HOLD] + +// [GPIO_SL_EXTFLASH_HOLD]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4001a/btl_spi_peripheral_eusart_driver_cfg.h b/hardware/board/config/brd4274a_brd4001a/btl_spi_peripheral_eusart_driver_cfg.h new file mode 100644 index 0000000000..6499f8230a --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/btl_spi_peripheral_eusart_driver_cfg.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Peripheral Eusart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H +#define BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Peripheral Eusart Driver + +// Receive buffer size:[0-2048] <0-2048> +// Default: 300 +#define SL_SPI_PERIPHERAL_EUSART_RX_BUFFER_SIZE 300 + +// Transmit buffer size:[0-2048] <0-2048> +// Default: 50 +#define SL_SPI_PERIPHERAL_EUSART_TX_BUFFER_SIZE 50 + +// LDMA channel for SPI RX:[0-1] <0-1> +// Default: 0 +#define SL_SPI_PERIPHERAL_EUSART_LDMA_RX_CHANNEL 0 + +// LDMA channel for SPI TX:[0-1] <0-1> +// Default: 1 +#define SL_SPI_PERIPHERAL_EUSART_LDMA_TX_CHANNEL 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_EUSART_SPINCP + +// $[EUSART_SL_EUSART_SPINCP] +#define SL_EUSART_SPINCP_PERIPHERAL EUSART1 +#define SL_EUSART_SPINCP_PERIPHERAL_NO 1 + +// EUSART1 TX on PC00 +#define SL_EUSART_SPINCP_TX_PORT gpioPortC +#define SL_EUSART_SPINCP_TX_PIN 0 + +// EUSART1 RX on PC01 +#define SL_EUSART_SPINCP_RX_PORT gpioPortC +#define SL_EUSART_SPINCP_RX_PIN 1 + +// EUSART1 CS on PB04 +#define SL_EUSART_SPINCP_CS_PORT gpioPortB +#define SL_EUSART_SPINCP_CS_PIN 4 + +// EUSART1 SCLK on PC02 +#define SL_EUSART_SPINCP_SCLK_PORT gpioPortC +#define SL_EUSART_SPINCP_SCLK_PIN 2 + +// [EUSART_SL_EUSART_SPINCP]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4001a/iot_flash_cfg_msc.h b/hardware/board/config/brd4274a_brd4001a/iot_flash_cfg_msc.h similarity index 100% rename from hardware/board/config/brd4111a_brd4001a/iot_flash_cfg_msc.h rename to hardware/board/config/brd4274a_brd4001a/iot_flash_cfg_msc.h diff --git a/hardware/board/config/brd4274a_brd4001a/iot_i2c_cfg_exp.h b/hardware/board/config/brd4274a_brd4001a/iot_i2c_cfg_exp.h new file mode 100644 index 0000000000..95a5cec31d --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/iot_i2c_cfg_exp.h @@ -0,0 +1,106 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_EXP_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_EXP_H_ +#define _IOT_I2C_CFG_EXP_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_EXP_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_EXP_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_EXP_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_EXP_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_EXP_ENABLE +// $[GPIO_IOT_I2C_CFG_EXP_ENABLE] + +// [GPIO_IOT_I2C_CFG_EXP_ENABLE]$ + +// IOT_I2C_CFG_EXP +// $[I2C_IOT_I2C_CFG_EXP] +#define IOT_I2C_CFG_EXP_PERIPHERAL I2C0 +#define IOT_I2C_CFG_EXP_PERIPHERAL_NO 0 + +// I2C0 SCL on PB02 +#define IOT_I2C_CFG_EXP_SCL_PORT gpioPortB +#define IOT_I2C_CFG_EXP_SCL_PIN 2 + +// I2C0 SDA on PB03 +#define IOT_I2C_CFG_EXP_SDA_PORT gpioPortB +#define IOT_I2C_CFG_EXP_SDA_PIN 3 + +// [I2C_IOT_I2C_CFG_EXP]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4109a_brd4001a/iot_i2c_cfg_sensor.h b/hardware/board/config/brd4274a_brd4001a/iot_i2c_cfg_sensor.h similarity index 100% rename from hardware/board/config/brd4109a_brd4001a/iot_i2c_cfg_sensor.h rename to hardware/board/config/brd4274a_brd4001a/iot_i2c_cfg_sensor.h diff --git a/hardware/board/config/brd4274a_brd4001a/iot_i2c_cfg_test.h b/hardware/board/config/brd4274a_brd4001a/iot_i2c_cfg_test.h new file mode 100644 index 0000000000..e4669959e0 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/iot_i2c_cfg_test.h @@ -0,0 +1,106 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_TEST_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_TEST_H_ +#define _IOT_I2C_CFG_TEST_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_TEST_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_TEST_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_TEST_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_TEST_ACCEPT_NACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_TEST_ENABLE +// $[GPIO_IOT_I2C_CFG_TEST_ENABLE] + +// [GPIO_IOT_I2C_CFG_TEST_ENABLE]$ + +// IOT_I2C_CFG_TEST +// $[I2C_IOT_I2C_CFG_TEST] +#define IOT_I2C_CFG_TEST_PERIPHERAL I2C0 +#define IOT_I2C_CFG_TEST_PERIPHERAL_NO 0 + +// I2C0 SCL on PB02 +#define IOT_I2C_CFG_TEST_SCL_PORT gpioPortB +#define IOT_I2C_CFG_TEST_SCL_PIN 2 + +// I2C0 SDA on PB03 +#define IOT_I2C_CFG_TEST_SDA_PORT gpioPortB +#define IOT_I2C_CFG_TEST_SDA_PIN 3 + +// [I2C_IOT_I2C_CFG_TEST]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_TEST_H_ */ diff --git a/hardware/board/config/brd4274a_brd4001a/iot_pwm_cfg_led0.h b/hardware/board/config/brd4274a_brd4001a/iot_pwm_cfg_led0.h new file mode 100644 index 0000000000..af22fd6100 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/iot_pwm_cfg_led0.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED0_H_ +#define _IOT_PWM_CFG_LED0_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED0_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED0 +// $[TIMER_IOT_PWM_CFG_LED0] +#define IOT_PWM_CFG_LED0_PERIPHERAL TIMER0 +#define IOT_PWM_CFG_LED0_PERIPHERAL_NO 0 + +// TIMER0 CC0 on PA05 +#define IOT_PWM_CFG_LED0_CC0_PORT gpioPortA +#define IOT_PWM_CFG_LED0_CC0_PIN 5 + + + +// [TIMER_IOT_PWM_CFG_LED0]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED0_H_ */ diff --git a/hardware/board/config/brd4274a_brd4001a/iot_pwm_cfg_led1.h b/hardware/board/config/brd4274a_brd4001a/iot_pwm_cfg_led1.h new file mode 100644 index 0000000000..b0766a1044 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/iot_pwm_cfg_led1.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED1_H_ +#define _IOT_PWM_CFG_LED1_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED1_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED1 +// $[TIMER_IOT_PWM_CFG_LED1] +#define IOT_PWM_CFG_LED1_PERIPHERAL TIMER1 +#define IOT_PWM_CFG_LED1_PERIPHERAL_NO 1 + +// TIMER1 CC0 on PA06 +#define IOT_PWM_CFG_LED1_CC0_PORT gpioPortA +#define IOT_PWM_CFG_LED1_CC0_PIN 6 + + + +// [TIMER_IOT_PWM_CFG_LED1]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED1_H_ */ diff --git a/hardware/board/config/brd4274a_brd4001a/sl_board_control_config.h b/hardware/board/config/brd4274a_brd4001a/sl_board_control_config.h new file mode 100644 index 0000000000..e6c097ee72 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/sl_board_control_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 0 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortA +#define SL_BOARD_ENABLE_VCOM_PIN 11 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortB +#define SL_BOARD_ENABLE_DISPLAY_PIN 5 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4001a/sl_cpc_drv_secondary_spi_eusart_exp_config.h b/hardware/board/config/brd4274a_brd4001a/sl_cpc_drv_secondary_spi_eusart_exp_config.h new file mode 100644 index 0000000000..35d116925d --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/sl_cpc_drv_secondary_spi_eusart_exp_config.h @@ -0,0 +1,94 @@ +/***************************************************************************//** + * @file + * @brief CPC SPI SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_SPI_EUSART_EXP_SECONDARY_CONFIG_H +#define SL_CPC_DRV_SPI_EUSART_EXP_SECONDARY_CONFIG_H +#include "spidrv.h" + +// CPC-Secondary SPI Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_SPI_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_SIZE 10 + +// SPI bit rate +// Default: 1000000 +#define SL_CPC_DRV_SPI_EXP_BITRATE 1000000 + +// Chip Select Interrupt Number on Falling Edge +// Default: 10 +#define SL_CPC_DRV_SPI_EXP_CS_FALLING_EDGE_INT_NO 4 + +// Chip Select Interrupt Number on Rising Edge +// Default: 11 +#define SL_CPC_DRV_SPI_EXP_CS_RISING_EDGE_INT_NO 5 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_SPI_EXP_RX_IRQ +// $[GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ] +#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PORT gpioPortB +#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PIN 2 + +// [GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ]$ + +// SL_CPC_DRV_SPI_EXP +// $[EUSART_SL_CPC_DRV_SPI_EXP] +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL EUSART1 +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PC00 +#define SL_CPC_DRV_SPI_EXP_TX_PORT gpioPortC +#define SL_CPC_DRV_SPI_EXP_TX_PIN 0 + +// EUSART1 RX on PC01 +#define SL_CPC_DRV_SPI_EXP_RX_PORT gpioPortC +#define SL_CPC_DRV_SPI_EXP_RX_PIN 1 + +// EUSART1 SCLK on PC02 +#define SL_CPC_DRV_SPI_EXP_SCLK_PORT gpioPortC +#define SL_CPC_DRV_SPI_EXP_SCLK_PIN 2 + +// EUSART1 CS on PB04 +#define SL_CPC_DRV_SPI_EXP_CS_PORT gpioPortB +#define SL_CPC_DRV_SPI_EXP_CS_PIN 4 + +// [EUSART_SL_CPC_DRV_SPI_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_SPI_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4274a_brd4001a/sl_cpc_drv_secondary_uart_eusart_exp_config.h b/hardware/board/config/brd4274a_brd4001a/sl_cpc_drv_secondary_uart_eusart_exp_config.h new file mode 100644 index 0000000000..4b175f13e3 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/sl_cpc_drv_secondary_uart_eusart_exp_config.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_EXP_SECONDARY_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_EXP_SECONDARY_CONFIG_H + +// CPC - Secondary EUSART Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlNone +#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_EXP +// $[EUSART_SL_CPC_DRV_UART_EXP] +#define SL_CPC_DRV_UART_EXP_PERIPHERAL EUSART1 +#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PC00 +#define SL_CPC_DRV_UART_EXP_TX_PORT gpioPortC +#define SL_CPC_DRV_UART_EXP_TX_PIN 0 + +// EUSART1 RX on PC01 +#define SL_CPC_DRV_UART_EXP_RX_PORT gpioPortC +#define SL_CPC_DRV_UART_EXP_RX_PIN 1 + +// EUSART1 CTS on PC02 +#define SL_CPC_DRV_UART_EXP_CTS_PORT gpioPortC +#define SL_CPC_DRV_UART_EXP_CTS_PIN 2 + +// EUSART1 RTS on PB04 +#define SL_CPC_DRV_UART_EXP_RTS_PORT gpioPortB +#define SL_CPC_DRV_UART_EXP_RTS_PIN 4 + +// [EUSART_SL_CPC_DRV_UART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4274a_brd4001a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h b/hardware/board/config/brd4274a_brd4001a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h new file mode 100644 index 0000000000..3cdf1d349b --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_VCOM_SECONDARY_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_VCOM_SECONDARY_CONFIG_H + +// CPC - Secondary EUSART Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlNone +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[EUSART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL EUSART0 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 0 + +// [EUSART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4274a_brd4001a/sl_device_init_hfxo_config.h b/hardware/board/config/brd4274a_brd4001a/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..c3dc821a7b --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/sl_device_init_hfxo_config.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// External sine wave +// Default: cmuHfxoOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal + +// Frequency <38000000-40000000> +// Default: 39000000 +#define SL_DEVICE_INIT_HFXO_FREQ 39000000 + +// CTUNE <0-255> +// Default: 140 +#define SL_DEVICE_INIT_HFXO_CTUNE 105 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4001a/sl_device_init_lfxo_config.h b/hardware/board/config/brd4274a_brd4001a/sl_device_init_lfxo_config.h new file mode 100644 index 0000000000..5d2cee4142 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/sl_device_init_lfxo_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_LFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuLfxoOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuLfxoOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 36 + +// LFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_LFXO_PRECISION 100 + +// Startup Timeout Delay +// +// 2 cycles +// 256 cycles +// 1K cycles +// 2K cycles +// 4K cycles +// 8K cycles +// 16K cycles +// 32K cycles +// Default: cmuLfxoStartupDelay_4KCycles +#define SL_DEVICE_INIT_LFXO_TIMEOUT cmuLfxoStartupDelay_4KCycles +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4001a/sl_iostream_eusart_exp_config.h b/hardware/board/config/brd4274a_brd4001a/sl_iostream_eusart_exp_config.h new file mode 100644 index 0000000000..cbe96bbdcb --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/sl_iostream_eusart_exp_config.h @@ -0,0 +1,107 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_EXP_CONFIG_H +#define SL_IOSTREAM_EUSART_EXP_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_EXP_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_IOSTREAM_EUSART_EXP_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_IOSTREAM_EUSART_EXP_STOP_BITS eusartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: eusartHwFlowControlNone +#define SL_IOSTREAM_EUSART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_EXP_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_EXP +// $[EUSART_SL_IOSTREAM_EUSART_EXP] +#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL EUSART0 +#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_IOSTREAM_EUSART_EXP_TX_PORT gpioPortA +#define SL_IOSTREAM_EUSART_EXP_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_IOSTREAM_EUSART_EXP_RX_PORT gpioPortA +#define SL_IOSTREAM_EUSART_EXP_RX_PIN 9 + + + +// [EUSART_SL_IOSTREAM_EUSART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4274a_brd4001a/sl_iostream_eusart_vcom_config.h b/hardware/board/config/brd4274a_brd4001a/sl_iostream_eusart_vcom_config.h new file mode 100644 index 0000000000..db8ecd8a79 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/sl_iostream_eusart_vcom_config.h @@ -0,0 +1,113 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_VCOM_CONFIG_H +#define SL_IOSTREAM_EUSART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_VCOM_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_IOSTREAM_EUSART_VCOM_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_IOSTREAM_EUSART_VCOM_STOP_BITS eusartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: eusartHwFlowControlNone +#define SL_IOSTREAM_EUSART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_VCOM +// $[EUSART_SL_IOSTREAM_EUSART_VCOM] +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL EUSART0 +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_IOSTREAM_EUSART_VCOM_TX_PORT gpioPortA +#define SL_IOSTREAM_EUSART_VCOM_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_IOSTREAM_EUSART_VCOM_RX_PORT gpioPortA +#define SL_IOSTREAM_EUSART_VCOM_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_IOSTREAM_EUSART_VCOM_CTS_PORT gpioPortA +#define SL_IOSTREAM_EUSART_VCOM_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_IOSTREAM_EUSART_VCOM_RTS_PORT gpioPortA +#define SL_IOSTREAM_EUSART_VCOM_RTS_PIN 0 + +// [EUSART_SL_IOSTREAM_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4274a_brd4001a/sl_memlcd_eusart_config.h b/hardware/board/config/brd4274a_brd4001a/sl_memlcd_eusart_config.h new file mode 100644 index 0000000000..7f330a1a6e --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/sl_memlcd_eusart_config.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file + * @brief SPI abstraction used by memory lcd display + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_MEMLCD_CONFIG_H +#define SL_MEMLCD_CONFIG_H + +// <<< sl:start pin_tool >>> +// SL_MEMLCD_SPI +// $[EUSART_SL_MEMLCD_SPI] +#define SL_MEMLCD_SPI_PERIPHERAL EUSART1 +#define SL_MEMLCD_SPI_PERIPHERAL_NO 1 + +// EUSART1 TX on PC00 +#define SL_MEMLCD_SPI_TX_PORT gpioPortC +#define SL_MEMLCD_SPI_TX_PIN 0 + +// EUSART1 SCLK on PC02 +#define SL_MEMLCD_SPI_SCLK_PORT gpioPortC +#define SL_MEMLCD_SPI_SCLK_PIN 2 + +// [EUSART_SL_MEMLCD_SPI]$ + +// SL_MEMLCD_SPI_CS +// $[GPIO_SL_MEMLCD_SPI_CS] +#define SL_MEMLCD_SPI_CS_PORT gpioPortD +#define SL_MEMLCD_SPI_CS_PIN 5 + +// [GPIO_SL_MEMLCD_SPI_CS]$ + +// SL_MEMLCD_EXTCOMIN +// $[GPIO_SL_MEMLCD_EXTCOMIN] +#define SL_MEMLCD_EXTCOMIN_PORT gpioPortA +#define SL_MEMLCD_EXTCOMIN_PIN 7 + +// [GPIO_SL_MEMLCD_EXTCOMIN]$ + +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4274a_brd4001a/sl_mx25_flash_shutdown_eusart_config.h b/hardware/board/config/brd4274a_brd4001a/sl_mx25_flash_shutdown_eusart_config.h new file mode 100644 index 0000000000..fd2ae0a41f --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/sl_mx25_flash_shutdown_eusart_config.h @@ -0,0 +1,51 @@ +/***************************************************************************//** + * @file + * @brief SL_MX25_FLASH_SHUTDOWN_USART Config + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H +#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H + +// <<< sl:start pin_tool >>> +// {eusart signal=TX,RX,SCLK} SL_MX25_FLASH_SHUTDOWN +// [EUSART_SL_MX25_FLASH_SHUTDOWN] +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL EUSART1 +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 1 + +// EUSART1 TX on PC00 +#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 0 + +// EUSART1 RX on PC01 +#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 + +// EUSART1 SCLK on PC02 +#define SL_MX25_FLASH_SHUTDOWN_SCLK_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_SCLK_PIN 2 + +// [EUSART_SL_MX25_FLASH_SHUTDOWN] + +// SL_MX25_FLASH_SHUTDOWN_CS + +// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] +#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortA +#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 + +// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4001a/sl_pwm_init_led0_config.h b/hardware/board/config/brd4274a_brd4001a/sl_pwm_init_led0_config.h new file mode 100644 index 0000000000..6102dad789 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/sl_pwm_init_led0_config.h @@ -0,0 +1,62 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef PWM_INIT_LED0_CONFIG_H +#define PWM_INIT_LED0_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED0_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED0_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED0 +// $[TIMER_SL_PWM_LED0] +#define SL_PWM_LED0_PERIPHERAL TIMER0 +#define SL_PWM_LED0_PERIPHERAL_NO 0 + +#define SL_PWM_LED0_OUTPUT_CHANNEL 0 +// TIMER0 CC0 on PA05 +#define SL_PWM_LED0_OUTPUT_PORT gpioPortA +#define SL_PWM_LED0_OUTPUT_PIN 5 + +// [TIMER_SL_PWM_LED0]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // PWM_INIT_LED0_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4001a/sl_pwm_init_led1_config.h b/hardware/board/config/brd4274a_brd4001a/sl_pwm_init_led1_config.h new file mode 100644 index 0000000000..4aabf9cda7 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/sl_pwm_init_led1_config.h @@ -0,0 +1,62 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef PWM_INIT_LED1_CONFIG_H +#define PWM_INIT_LED1_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED1_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED1_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED1 +// $[TIMER_SL_PWM_LED1] +#define SL_PWM_LED1_PERIPHERAL TIMER1 +#define SL_PWM_LED1_PERIPHERAL_NO 1 + +#define SL_PWM_LED1_OUTPUT_CHANNEL 0 +// TIMER1 CC0 on PA06 +#define SL_PWM_LED1_OUTPUT_PORT gpioPortA +#define SL_PWM_LED1_OUTPUT_PIN 6 + +// [TIMER_SL_PWM_LED1]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // PWM_INIT_LED1_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4001a/sl_rail_util_eff_config.h b/hardware/board/config/brd4274a_brd4001a/sl_rail_util_eff_config.h new file mode 100644 index 0000000000..f34e43c03c --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/sl_rail_util_eff_config.h @@ -0,0 +1,166 @@ +/***************************************************************************//** + * @file + * @brief RAIL Util for EFF0 configuration file. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_EFF_CONFIG_H +#define SL_RAIL_UTIL_EFF_CONFIG_H + +#include "em_gpio.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// EFF Configuration +// Select connected EFF device +// No connected EFF device +// EFF01Z11 +// EFF01A12 +// Default: RAIL_EFF_DEVICE_EFF01A12 +#define SL_RAIL_UTIL_EFF_DEVICE RAIL_EFF_DEVICE_EFF01A12 +// Enable Rural LNA Mode +// Default: 1 +#define SL_RAIL_UTIL_EFF_LNA_MODE_RURAL_ENABLE 1 +// Enable Urban LNA Mode +// Default: 1 +#define SL_RAIL_UTIL_EFF_LNA_MODE_URBAN_ENABLE 1 +// Enable Bypass LNA Mode +// Default: 1 +#define SL_RAIL_UTIL_EFF_LNA_MODE_BYPASS_ENABLE 1 +// Trip point between rural and urban modes, in millivolts. +// <5-1250:1> +// Default: 120 +#define SL_RAIL_UTIL_EFF_RURAL_URBAN_MV 120 +// Trip point between urban and bypass modes, in millivolts. +// <5-1250:1> +// Default: 130 +#define SL_RAIL_UTIL_EFF_URBAN_BYPASS_MV 130 +// Length of time to stay in urban mode before transitioning to rural mode, in milliseconds. +// <1-105000:1> +// Default: 30000 +#define SL_RAIL_UTIL_EFF_URBAN_DWELL_TIME_MS 30000 +// Length of time to stay in bypass mode before transitioning to urban or rural mode, in milliseconds. +// <1-105000:1> +// Default: 30000 +#define SL_RAIL_UTIL_EFF_BYPASS_DWELL_TIME_MS 30000 +// Target for CLPC slow loop, in milliwatts. +// <5-2000:1> +// Default: 630 +#define SL_RAIL_UTIL_EFF_CLPC_SLOW_LOOP_TARGET 630 +// Relationship between delta-GAINDIG/delta-power to find new GAINDIG value +// <1-100:1> +// Default: 100 +#define SL_RAIL_UTIL_EFF_CLPC_SLOW_LOOP_SLOPE 100 +// Target for CLPC fast loop, in millivolts. +// <5-1500:1> +// Default: 700 +#define SL_RAIL_UTIL_EFF_CLPC_FAST_LOOP_TARGET 700 +// Relationship between delta-GAINDIG/delta-AUXADC to find new GAINDIG value +// <1-100:1> +// Default: 100 +#define SL_RAIL_UTIL_EFF_CLPC_FAST_LOOP_SLOPE 99 +// Select CLPC mode +// Disable CLPC power control. Flare modes will only be transmit/receive. +// Allow mode changes/measurements, but no power changes +// Allow only Slow loop power changes +// Allow only Fast loop power changes +// Allow full power control +// Default: RAIL_EFF_CLPC_POWER_BOTH +#define SL_RAIL_UTIL_EFF_CLPC_ENABLE RAIL_EFF_CLPC_MODE_CHANGE +// Maximum continuous transfer power in dBm +// <20-30:1> +// Default: 20 +#define RAIL_UTIL_EFF_MAX_TX_CONTINUOUS_POWER_DBM 20 +// Maximum transmit duty cycle as a percentage +// <10-100:1> +// Default: 50 +#define RAIL_UTIL_EFF_MAX_TX_DUTY_CYCLE 50 +// Temperature of EFF above which transmit is not allowed, in degrees Kelvin +// <1-398:1> +// Default: 373 +#define SL_RAIL_UTIL_EFF_TEMPERATURE_THRESHOLD_EFF_DEGREES_K 373 +// Chip's internal temperature above which transmit is not allowed, in degrees Kelvin +// <1-398:1> +// Default: 373 +#define SL_RAIL_UTIL_EFF_TEMPERATURE_THRESHOLD_INTERNAL_DEGREES_K 373 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// CTRL0 GPIO +// SL_RAIL_UTIL_EFF_CTRL0 +// $[GPIO_SL_RAIL_UTIL_EFF_CTRL0] +#define SL_RAIL_UTIL_EFF_CTRL0_PORT gpioPortC +#define SL_RAIL_UTIL_EFF_CTRL0_PIN 4 + +// [GPIO_SL_RAIL_UTIL_EFF_CTRL0]$ + +// CTRL1 GPIO +// SL_RAIL_UTIL_EFF_CTRL1 +// $[GPIO_SL_RAIL_UTIL_EFF_CTRL1] +#define SL_RAIL_UTIL_EFF_CTRL1_PORT gpioPortC +#define SL_RAIL_UTIL_EFF_CTRL1_PIN 5 + +// [GPIO_SL_RAIL_UTIL_EFF_CTRL1]$ + +// CTRL2 GPIO +// SL_RAIL_UTIL_EFF_CTRL2 +// $[GPIO_SL_RAIL_UTIL_EFF_CTRL2] +#define SL_RAIL_UTIL_EFF_CTRL2_PORT gpioPortC +#define SL_RAIL_UTIL_EFF_CTRL2_PIN 6 + +// [GPIO_SL_RAIL_UTIL_EFF_CTRL2]$ + +// CTRL3 GPIO +// SL_RAIL_UTIL_EFF_CTRL3 +// $[GPIO_SL_RAIL_UTIL_EFF_CTRL3] +#define SL_RAIL_UTIL_EFF_CTRL3_PORT gpioPortC +#define SL_RAIL_UTIL_EFF_CTRL3_PIN 7 + +// [GPIO_SL_RAIL_UTIL_EFF_CTRL3]$ + +// TEST GPIO +// SL_RAIL_UTIL_EFF_TEST +// $[GPIO_SL_RAIL_UTIL_EFF_TEST] +#define SL_RAIL_UTIL_EFF_TEST_PORT gpioPortC +#define SL_RAIL_UTIL_EFF_TEST_PIN 3 + +// [GPIO_SL_RAIL_UTIL_EFF_TEST]$ + +// SENSE GPIO +// SL_RAIL_UTIL_EFF_SENSE +// $[GPIO_SL_RAIL_UTIL_EFF_SENSE] +#define SL_RAIL_UTIL_EFF_SENSE_PORT gpioPortC +#define SL_RAIL_UTIL_EFF_SENSE_PIN 8 + +// [GPIO_SL_RAIL_UTIL_EFF_SENSE]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_RAIL_UTIL_EFF_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4001a/sl_rail_util_pa_config.h b/hardware/board/config/brd4274a_brd4001a/sl_rail_util_pa_config.h new file mode 100644 index 0000000000..b0bde82184 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/sl_rail_util_pa_config.h @@ -0,0 +1,82 @@ +/***************************************************************************//** + * @file + * @brief Power Amplifier configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PA_CONFIG_H +#define SL_RAIL_UTIL_PA_CONFIG_H + +#include "rail_chip_specific.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PA configuration + +// Initial PA Power (deci-dBm, 100 = 10.0 dBm) +// Default: 100 +#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 + +// PA Ramp Time (microseconds) +// <0-65535:1> +// Default: 10 +#define SL_RAIL_UTIL_PA_RAMP_TIME_US 10 + +// Milli-volts on PA supply pin (PA_VDD) +// <0-65535:1> +// Default: 3600 +#define SL_RAIL_UTIL_PA_VOLTAGE_MV 3600 + +// 2.4 GHz PA Selection +// Highest Possible +// High Power (chip-specific) +// Medium Power (chip-specific) +// Low Power +// Disable +// Default: RAIL_TX_POWER_MODE_2P4GIG_HIGHEST +#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_NONE + +// Sub-1 GHz PA Selection +// Disable +// Default: RAIL_TX_POWER_MODE_NONE +#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_SUBGIG_HIGHEST + +// Header file containing custom PA curves +// Default: "pa_curves_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" + +// Header file containing PA curve types +// Default: "pa_curve_types_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" + +// Enable PA Calibration +// Default: 0 +#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 0 + +// +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4001a/sl_rail_util_pti_config.h b/hardware/board/config/brd4274a_brd4001a/sl_rail_util_pti_config.h new file mode 100644 index 0000000000..1ae930e38f --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/sl_rail_util_pti_config.h @@ -0,0 +1,73 @@ +/***************************************************************************//** + * @file + * @brief Packet Trace Information configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PTI_CONFIG_H +#define SL_RAIL_UTIL_PTI_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PTI Configuration + +// PTI mode +// UART +// UART onewire +// SPI +// Disabled +// Default: RAIL_PTI_MODE_UART +#define SL_RAIL_UTIL_PTI_MODE RAIL_PTI_MODE_UART + +// PTI Baud Rate (Hertz) +// <147800-20000000:1> +// Default: 1600000 +#define SL_RAIL_UTIL_PTI_BAUD_RATE_HZ 1600000 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_RAIL_UTIL_PTI +// $[PTI_SL_RAIL_UTIL_PTI] +#define SL_RAIL_UTIL_PTI_PERIPHERAL PTI + +// PTI DOUT on PD03 +#define SL_RAIL_UTIL_PTI_DOUT_PORT gpioPortD +#define SL_RAIL_UTIL_PTI_DOUT_PIN 3 + +// PTI DFRAME on PD04 +#define SL_RAIL_UTIL_PTI_DFRAME_PORT gpioPortD +#define SL_RAIL_UTIL_PTI_DFRAME_PIN 4 + + +// [PTI_SL_RAIL_UTIL_PTI]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_RAIL_UTIL_PTI_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4001a/sl_simple_button_btn0_config.h b/hardware/board/config/brd4274a_brd4001a/sl_simple_button_btn0_config.h similarity index 100% rename from hardware/board/config/brd4109a_brd4001a/sl_simple_button_btn0_config.h rename to hardware/board/config/brd4274a_brd4001a/sl_simple_button_btn0_config.h diff --git a/hardware/board/config/brd4109a_brd4001a/sl_simple_button_btn1_config.h b/hardware/board/config/brd4274a_brd4001a/sl_simple_button_btn1_config.h similarity index 100% rename from hardware/board/config/brd4109a_brd4001a/sl_simple_button_btn1_config.h rename to hardware/board/config/brd4274a_brd4001a/sl_simple_button_btn1_config.h diff --git a/hardware/board/config/brd4274a_brd4001a/sl_simple_led_led0_config.h b/hardware/board/config/brd4274a_brd4001a/sl_simple_led_led0_config.h new file mode 100644 index 0000000000..fe98957dcb --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/sl_simple_led_led0_config.h @@ -0,0 +1,44 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED0_CONFIG_H +#define SL_SIMPLE_LED_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED0_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED0 +// $[GPIO_SL_SIMPLE_LED_LED0] +#define SL_SIMPLE_LED_LED0_PORT gpioPortA +#define SL_SIMPLE_LED_LED0_PIN 5 + +// [GPIO_SL_SIMPLE_LED_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED0_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4001a/sl_simple_led_led1_config.h b/hardware/board/config/brd4274a_brd4001a/sl_simple_led_led1_config.h new file mode 100644 index 0000000000..aa9c5c343d --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/sl_simple_led_led1_config.h @@ -0,0 +1,44 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED1_CONFIG_H +#define SL_SIMPLE_LED_LED1_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED1_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED1 +// $[GPIO_SL_SIMPLE_LED_LED1] +#define SL_SIMPLE_LED_LED1_PORT gpioPortA +#define SL_SIMPLE_LED_LED1_PIN 6 + +// [GPIO_SL_SIMPLE_LED_LED1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED1_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4001a/sl_spidrv_eusart_exp_config.h b/hardware/board/config/brd4274a_brd4001a/sl_spidrv_eusart_exp_config.h new file mode 100644 index 0000000000..69cbb27a77 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/sl_spidrv_eusart_exp_config.h @@ -0,0 +1,89 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_EUSART_EXP_CONFIG_H +#define SL_SPIDRV_EUSART_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_EUSART_EXP_BITRATE 1000000 + +// SPI frame length <7-16> +// Default: 8 +#define SL_SPIDRV_EUSART_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_EUSART_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_EUSART_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_EUSART_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_EUSART_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_EUSART_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_EUSART_EXP +// $[EUSART_SL_SPIDRV_EUSART_EXP] +#define SL_SPIDRV_EUSART_EXP_PERIPHERAL EUSART1 +#define SL_SPIDRV_EUSART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PC00 +#define SL_SPIDRV_EUSART_EXP_TX_PORT gpioPortC +#define SL_SPIDRV_EUSART_EXP_TX_PIN 0 + +// EUSART1 RX on PC01 +#define SL_SPIDRV_EUSART_EXP_RX_PORT gpioPortC +#define SL_SPIDRV_EUSART_EXP_RX_PIN 1 + +// EUSART1 SCLK on PC02 +#define SL_SPIDRV_EUSART_EXP_SCLK_PORT gpioPortC +#define SL_SPIDRV_EUSART_EXP_SCLK_PIN 2 + +// EUSART1 CS on PB04 +#define SL_SPIDRV_EUSART_EXP_CS_PORT gpioPortB +#define SL_SPIDRV_EUSART_EXP_CS_PIN 4 + +// [EUSART_SL_SPIDRV_EUSART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EUSART_EXP_CONFIG_HEUSART_ diff --git a/hardware/board/config/brd4274a_brd4001a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4274a_brd4001a/sl_uartdrv_eusart_exp_config.h new file mode 100644 index 0000000000..1db46bd885 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/sl_uartdrv_eusart_exp_config.h @@ -0,0 +1,100 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_EXP_CONFIG_H +#define SL_UARTDRV_EUSART_EXP_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_EXP_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_EXP_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_EXP_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_EXP_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHw +#define SL_UARTDRV_EUSART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_EXP_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_EXP_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_EXP +// $[EUSART_SL_UARTDRV_EUSART_EXP] +#define SL_UARTDRV_EUSART_EXP_PERIPHERAL EUSART0 +#define SL_UARTDRV_EUSART_EXP_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_UARTDRV_EUSART_EXP_TX_PORT gpioPortA +#define SL_UARTDRV_EUSART_EXP_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_UARTDRV_EUSART_EXP_RX_PORT gpioPortA +#define SL_UARTDRV_EUSART_EXP_RX_PIN 9 + + + +// [EUSART_SL_UARTDRV_EUSART_EXP]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4001a/sl_uartdrv_eusart_vcom_config.h b/hardware/board/config/brd4274a_brd4001a/sl_uartdrv_eusart_vcom_config.h new file mode 100644 index 0000000000..7db0d36941 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/sl_uartdrv_eusart_vcom_config.h @@ -0,0 +1,106 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_VCOM_CONFIG_H +#define SL_UARTDRV_EUSART_VCOM_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_VCOM_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_VCOM_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_VCOM_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_VCOM_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHw +#define SL_UARTDRV_EUSART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_VCOM_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_VCOM_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_VCOM +// $[EUSART_SL_UARTDRV_EUSART_VCOM] +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL EUSART0 +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_UARTDRV_EUSART_VCOM_TX_PORT gpioPortA +#define SL_UARTDRV_EUSART_VCOM_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_UARTDRV_EUSART_VCOM_RX_PORT gpioPortA +#define SL_UARTDRV_EUSART_VCOM_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_VCOM_CTS_PORT gpioPortA +#define SL_UARTDRV_EUSART_VCOM_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_VCOM_RTS_PORT gpioPortA +#define SL_UARTDRV_EUSART_VCOM_RTS_PIN 0 + +// [EUSART_SL_UARTDRV_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4001a/sl_usbd_driver_config.h b/hardware/board/config/brd4274a_brd4001a/sl_usbd_driver_config.h new file mode 100644 index 0000000000..005a845bd2 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4001a/sl_usbd_driver_config.h @@ -0,0 +1,30 @@ +/***************************************************************************//** + * @file + * @brief USBD Hardware Configuration + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_USBD_DRIVER_CONFIG_H +#define SL_USBD_DRIVER_CONFIG_H + +// <<< sl:start pin_tool >>> +// SL_USBD_DRIVER_VBUS_SENSE +// $[GPIO_SL_USBD_DRIVER_VBUS_SENSE] +#define SL_USBD_DRIVER_VBUS_SENSE_PORT gpioPortD +#define SL_USBD_DRIVER_VBUS_SENSE_PIN 2 + +// [GPIO_SL_USBD_DRIVER_VBUS_SENSE]$ +// <<< sl:end pin_tool >>> + +#endif // SL_USBD_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4002a/btl_euart_driver_cfg.h b/hardware/board/config/brd4274a_brd4002a/btl_euart_driver_cfg.h new file mode 100644 index 0000000000..8aa666844c --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/btl_euart_driver_cfg.h @@ -0,0 +1,88 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader euart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_EUART_DRIVER_CONFIG_H +#define BTL_EUART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Baud rate +// Default: 115200 +#define SL_SERIAL_EUART_BAUD_RATE 115200 + +// Hardware flow control +// Default: 0 +#define SL_SERIAL_EUART_FLOW_CONTROL 0 +// + +// Receive buffer size +// <0-2048:1> +// Default: 512 [0-2048] +#define SL_DRIVER_EUART_RX_BUFFER_SIZE 512 + +// Transmit buffer size +// <0-2048:1> +// Default: 128 [0-2048] +#define SL_DRIVER_EUART_TX_BUFFER_SIZE 128 + +// Virtual COM Port +// Default: 0 +#define SL_VCOM_ENABLE 0 +// + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SERIAL_EUART +// $[EUSART_SL_SERIAL_EUART] +#define SL_SERIAL_EUART_PERIPHERAL EUSART0 +#define SL_SERIAL_EUART_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_SERIAL_EUART_TX_PORT gpioPortA +#define SL_SERIAL_EUART_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_SERIAL_EUART_RX_PORT gpioPortA +#define SL_SERIAL_EUART_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_SERIAL_EUART_CTS_PORT gpioPortA +#define SL_SERIAL_EUART_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_SERIAL_EUART_RTS_PORT gpioPortA +#define SL_SERIAL_EUART_RTS_PIN 0 + +// [EUSART_SL_SERIAL_EUART]$ + + +// SL_VCOM_ENABLE + +// $[GPIO_SL_VCOM_ENABLE] +#define SL_VCOM_ENABLE_PORT gpioPortA +#define SL_VCOM_ENABLE_PIN 11 + +// [GPIO_SL_VCOM_ENABLE]$ + + +// <<< sl:end pin_tool >>> + +#endif // BTL_EUART_DRIVER_CONFIG_H \ No newline at end of file diff --git a/hardware/board/config/brd4109a_brd4002a/btl_gpio_activation_cfg.h b/hardware/board/config/brd4274a_brd4002a/btl_gpio_activation_cfg.h similarity index 100% rename from hardware/board/config/brd4109a_brd4002a/btl_gpio_activation_cfg.h rename to hardware/board/config/brd4274a_brd4002a/btl_gpio_activation_cfg.h diff --git a/hardware/board/config/brd4274a_brd4002a/btl_spi_controller_eusart_driver_cfg.h b/hardware/board/config/brd4274a_brd4002a/btl_spi_controller_eusart_driver_cfg.h new file mode 100644 index 0000000000..e20e00a304 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/btl_spi_controller_eusart_driver_cfg.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Controller Eusart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H +#define BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Controller EUSART Driver + +// Frequency +// Default: 6400000 +#define SL_EUSART_EXTFLASH_FREQUENCY 6400000 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_EUSART_EXTFLASH +// $[EUSART_SL_EUSART_EXTFLASH] +#define SL_EUSART_EXTFLASH_PERIPHERAL EUSART1 +#define SL_EUSART_EXTFLASH_PERIPHERAL_NO 1 + +// EUSART1 TX on PC00 +#define SL_EUSART_EXTFLASH_TX_PORT gpioPortC +#define SL_EUSART_EXTFLASH_TX_PIN 0 + +// EUSART1 RX on PC01 +#define SL_EUSART_EXTFLASH_RX_PORT gpioPortC +#define SL_EUSART_EXTFLASH_RX_PIN 1 + +// EUSART1 SCLK on PC02 +#define SL_EUSART_EXTFLASH_SCLK_PORT gpioPortC +#define SL_EUSART_EXTFLASH_SCLK_PIN 2 + +// EUSART1 CS on PA04 +#define SL_EUSART_EXTFLASH_CS_PORT gpioPortA +#define SL_EUSART_EXTFLASH_CS_PIN 4 + +// [EUSART_SL_EUSART_EXTFLASH]$ + +// SL_EXTFLASH_WP +// $[GPIO_SL_EXTFLASH_WP] + +// [GPIO_SL_EXTFLASH_WP]$ + +// SL_EXTFLASH_HOLD +// $[GPIO_SL_EXTFLASH_HOLD] + +// [GPIO_SL_EXTFLASH_HOLD]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_CONTROLLER_EUSART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4002a/btl_spi_peripheral_eusart_driver_cfg.h b/hardware/board/config/brd4274a_brd4002a/btl_spi_peripheral_eusart_driver_cfg.h new file mode 100644 index 0000000000..6499f8230a --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/btl_spi_peripheral_eusart_driver_cfg.h @@ -0,0 +1,71 @@ +/***************************************************************************//** + * @file + * @brief Configuration header for bootloader Spi Peripheral Eusart Driver + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H +#define BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SPI Peripheral Eusart Driver + +// Receive buffer size:[0-2048] <0-2048> +// Default: 300 +#define SL_SPI_PERIPHERAL_EUSART_RX_BUFFER_SIZE 300 + +// Transmit buffer size:[0-2048] <0-2048> +// Default: 50 +#define SL_SPI_PERIPHERAL_EUSART_TX_BUFFER_SIZE 50 + +// LDMA channel for SPI RX:[0-1] <0-1> +// Default: 0 +#define SL_SPI_PERIPHERAL_EUSART_LDMA_RX_CHANNEL 0 + +// LDMA channel for SPI TX:[0-1] <0-1> +// Default: 1 +#define SL_SPI_PERIPHERAL_EUSART_LDMA_TX_CHANNEL 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_EUSART_SPINCP + +// $[EUSART_SL_EUSART_SPINCP] +#define SL_EUSART_SPINCP_PERIPHERAL EUSART1 +#define SL_EUSART_SPINCP_PERIPHERAL_NO 1 + +// EUSART1 TX on PC00 +#define SL_EUSART_SPINCP_TX_PORT gpioPortC +#define SL_EUSART_SPINCP_TX_PIN 0 + +// EUSART1 RX on PC01 +#define SL_EUSART_SPINCP_RX_PORT gpioPortC +#define SL_EUSART_SPINCP_RX_PIN 1 + +// EUSART1 CS on PB04 +#define SL_EUSART_SPINCP_CS_PORT gpioPortB +#define SL_EUSART_SPINCP_CS_PIN 4 + +// EUSART1 SCLK on PC02 +#define SL_EUSART_SPINCP_SCLK_PORT gpioPortC +#define SL_EUSART_SPINCP_SCLK_PIN 2 + +// [EUSART_SL_EUSART_SPINCP]$ + +// <<< sl:end pin_tool >>> + +#endif // BTL_SPI_PERIPHERAL_EUSART_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4111a_brd4002a/iot_flash_cfg_msc.h b/hardware/board/config/brd4274a_brd4002a/iot_flash_cfg_msc.h similarity index 100% rename from hardware/board/config/brd4111a_brd4002a/iot_flash_cfg_msc.h rename to hardware/board/config/brd4274a_brd4002a/iot_flash_cfg_msc.h diff --git a/hardware/board/config/brd4274a_brd4002a/iot_i2c_cfg_exp.h b/hardware/board/config/brd4274a_brd4002a/iot_i2c_cfg_exp.h new file mode 100644 index 0000000000..95a5cec31d --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/iot_i2c_cfg_exp.h @@ -0,0 +1,106 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_EXP_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_EXP_H_ +#define _IOT_I2C_CFG_EXP_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_EXP_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_EXP_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_EXP_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_EXP_ACCEPT_NACK 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_EXP_ENABLE +// $[GPIO_IOT_I2C_CFG_EXP_ENABLE] + +// [GPIO_IOT_I2C_CFG_EXP_ENABLE]$ + +// IOT_I2C_CFG_EXP +// $[I2C_IOT_I2C_CFG_EXP] +#define IOT_I2C_CFG_EXP_PERIPHERAL I2C0 +#define IOT_I2C_CFG_EXP_PERIPHERAL_NO 0 + +// I2C0 SCL on PB02 +#define IOT_I2C_CFG_EXP_SCL_PORT gpioPortB +#define IOT_I2C_CFG_EXP_SCL_PIN 2 + +// I2C0 SDA on PB03 +#define IOT_I2C_CFG_EXP_SDA_PORT gpioPortB +#define IOT_I2C_CFG_EXP_SDA_PIN 3 + +// [I2C_IOT_I2C_CFG_EXP]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_EXP_H_ */ diff --git a/hardware/board/config/brd4109a_brd4002a/iot_i2c_cfg_sensor.h b/hardware/board/config/brd4274a_brd4002a/iot_i2c_cfg_sensor.h similarity index 100% rename from hardware/board/config/brd4109a_brd4002a/iot_i2c_cfg_sensor.h rename to hardware/board/config/brd4274a_brd4002a/iot_i2c_cfg_sensor.h diff --git a/hardware/board/config/brd4274a_brd4002a/iot_i2c_cfg_test.h b/hardware/board/config/brd4274a_brd4002a/iot_i2c_cfg_test.h new file mode 100644 index 0000000000..e4669959e0 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/iot_i2c_cfg_test.h @@ -0,0 +1,106 @@ +/***************************************************************************//** + * @file IOT_I2C_CFG_TEST_inst.h + * @brief Common I/O I2C instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_I2C_CFG_TEST_H_ +#define _IOT_I2C_CFG_TEST_H_ + +/******************************************************************************* + * I2C Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// I2C General Options + +// Instance number +// Instance number used when iot_i2c_open() is called. +// Default: 0 +#define IOT_I2C_CFG_TEST_INST_NUM 0 + +// Default timeout (in msec) +// Default: 500 +#define IOT_I2C_CFG_TEST_DEFAULT_TIMEOUT 500 + +// Default bus speed +// <100000=> Standard mode +// <400000=> Fast mode +// <1000000=> Fast plus mode +// <3400000=> High speed mode +// Default: 400000 +#define IOT_I2C_CFG_TEST_DEFAULT_FREQ 400000 + +// Accept NACK +// If the driver receives NACK during a transfer, the transfer is halted +// immediately but it is not considered as an error. Instead, the driver +// returns success status (useful for test purposes). +// Default: 0 +#define IOT_I2C_CFG_TEST_ACCEPT_NACK 1 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> + +// IOT_I2C_CFG_TEST_ENABLE +// $[GPIO_IOT_I2C_CFG_TEST_ENABLE] + +// [GPIO_IOT_I2C_CFG_TEST_ENABLE]$ + +// IOT_I2C_CFG_TEST +// $[I2C_IOT_I2C_CFG_TEST] +#define IOT_I2C_CFG_TEST_PERIPHERAL I2C0 +#define IOT_I2C_CFG_TEST_PERIPHERAL_NO 0 + +// I2C0 SCL on PB02 +#define IOT_I2C_CFG_TEST_SCL_PORT gpioPortB +#define IOT_I2C_CFG_TEST_SCL_PIN 2 + +// I2C0 SDA on PB03 +#define IOT_I2C_CFG_TEST_SDA_PORT gpioPortB +#define IOT_I2C_CFG_TEST_SDA_PIN 3 + +// [I2C_IOT_I2C_CFG_TEST]$ + +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_I2C_CFG_TEST_H_ */ diff --git a/hardware/board/config/brd4274a_brd4002a/iot_pwm_cfg_led0.h b/hardware/board/config/brd4274a_brd4002a/iot_pwm_cfg_led0.h new file mode 100644 index 0000000000..af22fd6100 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/iot_pwm_cfg_led0.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED0_H_ +#define _IOT_PWM_CFG_LED0_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED0_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED0 +// $[TIMER_IOT_PWM_CFG_LED0] +#define IOT_PWM_CFG_LED0_PERIPHERAL TIMER0 +#define IOT_PWM_CFG_LED0_PERIPHERAL_NO 0 + +// TIMER0 CC0 on PA05 +#define IOT_PWM_CFG_LED0_CC0_PORT gpioPortA +#define IOT_PWM_CFG_LED0_CC0_PIN 5 + + + +// [TIMER_IOT_PWM_CFG_LED0]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED0_H_ */ diff --git a/hardware/board/config/brd4274a_brd4002a/iot_pwm_cfg_led1.h b/hardware/board/config/brd4274a_brd4002a/iot_pwm_cfg_led1.h new file mode 100644 index 0000000000..b0766a1044 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/iot_pwm_cfg_led1.h @@ -0,0 +1,78 @@ +/***************************************************************************//** + * @file iot_pwm_cfg_inst.h + * @brief Common I/O PWM instance configuration. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_PWM_CFG_LED1_H_ +#define _IOT_PWM_CFG_LED1_H_ + +/******************************************************************************* + * PWM Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM General Options + +// Instance number +// Instance number used when iot_pwm_open() is called. +// Default: 0 +#define IOT_PWM_CFG_LED1_INST_NUM 0 + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_PWM_CFG_LED1 +// $[TIMER_IOT_PWM_CFG_LED1] +#define IOT_PWM_CFG_LED1_PERIPHERAL TIMER1 +#define IOT_PWM_CFG_LED1_PERIPHERAL_NO 1 + +// TIMER1 CC0 on PA06 +#define IOT_PWM_CFG_LED1_CC0_PORT gpioPortA +#define IOT_PWM_CFG_LED1_CC0_PIN 6 + + + +// [TIMER_IOT_PWM_CFG_LED1]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_PWM_CFG_LED1_H_ */ diff --git a/hardware/board/config/brd4274a_brd4002a/sl_board_control_config.h b/hardware/board/config/brd4274a_brd4002a/sl_board_control_config.h new file mode 100644 index 0000000000..e6c097ee72 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/sl_board_control_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 0 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortA +#define SL_BOARD_ENABLE_VCOM_PIN 11 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortB +#define SL_BOARD_ENABLE_DISPLAY_PIN 5 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4002a/sl_cpc_drv_secondary_spi_eusart_exp_config.h b/hardware/board/config/brd4274a_brd4002a/sl_cpc_drv_secondary_spi_eusart_exp_config.h new file mode 100644 index 0000000000..35d116925d --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/sl_cpc_drv_secondary_spi_eusart_exp_config.h @@ -0,0 +1,94 @@ +/***************************************************************************//** + * @file + * @brief CPC SPI SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_SPI_EUSART_EXP_SECONDARY_CONFIG_H +#define SL_CPC_DRV_SPI_EUSART_EXP_SECONDARY_CONFIG_H +#include "spidrv.h" + +// CPC-Secondary SPI Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_SPI_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_SPI_EXP_TX_QUEUE_SIZE 10 + +// SPI bit rate +// Default: 1000000 +#define SL_CPC_DRV_SPI_EXP_BITRATE 1000000 + +// Chip Select Interrupt Number on Falling Edge +// Default: 10 +#define SL_CPC_DRV_SPI_EXP_CS_FALLING_EDGE_INT_NO 4 + +// Chip Select Interrupt Number on Rising Edge +// Default: 11 +#define SL_CPC_DRV_SPI_EXP_CS_RISING_EDGE_INT_NO 5 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_SPI_EXP_RX_IRQ +// $[GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ] +#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PORT gpioPortB +#define SL_CPC_DRV_SPI_EXP_RX_IRQ_PIN 2 + +// [GPIO_SL_CPC_DRV_SPI_EXP_RX_IRQ]$ + +// SL_CPC_DRV_SPI_EXP +// $[EUSART_SL_CPC_DRV_SPI_EXP] +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL EUSART1 +#define SL_CPC_DRV_SPI_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PC00 +#define SL_CPC_DRV_SPI_EXP_TX_PORT gpioPortC +#define SL_CPC_DRV_SPI_EXP_TX_PIN 0 + +// EUSART1 RX on PC01 +#define SL_CPC_DRV_SPI_EXP_RX_PORT gpioPortC +#define SL_CPC_DRV_SPI_EXP_RX_PIN 1 + +// EUSART1 SCLK on PC02 +#define SL_CPC_DRV_SPI_EXP_SCLK_PORT gpioPortC +#define SL_CPC_DRV_SPI_EXP_SCLK_PIN 2 + +// EUSART1 CS on PB04 +#define SL_CPC_DRV_SPI_EXP_CS_PORT gpioPortB +#define SL_CPC_DRV_SPI_EXP_CS_PIN 4 + +// [EUSART_SL_CPC_DRV_SPI_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_SPI_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4274a_brd4002a/sl_cpc_drv_secondary_uart_eusart_exp_config.h b/hardware/board/config/brd4274a_brd4002a/sl_cpc_drv_secondary_uart_eusart_exp_config.h new file mode 100644 index 0000000000..4b175f13e3 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/sl_cpc_drv_secondary_uart_eusart_exp_config.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_EXP_SECONDARY_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_EXP_SECONDARY_CONFIG_H + +// CPC - Secondary EUSART Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_EXP_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_EXP_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlNone +#define SL_CPC_DRV_UART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_EXP +// $[EUSART_SL_CPC_DRV_UART_EXP] +#define SL_CPC_DRV_UART_EXP_PERIPHERAL EUSART1 +#define SL_CPC_DRV_UART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PC00 +#define SL_CPC_DRV_UART_EXP_TX_PORT gpioPortC +#define SL_CPC_DRV_UART_EXP_TX_PIN 0 + +// EUSART1 RX on PC01 +#define SL_CPC_DRV_UART_EXP_RX_PORT gpioPortC +#define SL_CPC_DRV_UART_EXP_RX_PIN 1 + +// EUSART1 CTS on PC02 +#define SL_CPC_DRV_UART_EXP_CTS_PORT gpioPortC +#define SL_CPC_DRV_UART_EXP_CTS_PIN 2 + +// EUSART1 RTS on PB04 +#define SL_CPC_DRV_UART_EXP_RTS_PORT gpioPortB +#define SL_CPC_DRV_UART_EXP_RTS_PIN 4 + +// [EUSART_SL_CPC_DRV_UART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_EXP_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4274a_brd4002a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h b/hardware/board/config/brd4274a_brd4002a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h new file mode 100644 index 0000000000..3cdf1d349b --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief CPC EUSART SECONDARY driver configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_CPC_DRV_UART_EUSART_VCOM_SECONDARY_CONFIG_H +#define SL_CPC_DRV_UART_EUSART_VCOM_SECONDARY_CONFIG_H + +// CPC - Secondary EUSART Driver Configuration + +// Number of frame that can be queued in the driver receive queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_RX_QUEUE_SIZE 10 + +// Number of frame that can be queued in the driver transmit queue +// Default: 10 +#define SL_CPC_DRV_UART_VCOM_TX_QUEUE_SIZE 10 + +// EUSART Baudrate +// Default: 115200 +#define SL_CPC_DRV_UART_VCOM_BAUDRATE 115200 + +// Flow control +// None +// CTS/RTS +// Default: eusartHwFlowControlNone +#define SL_CPC_DRV_UART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_CPC_DRV_UART_VCOM +// $[EUSART_SL_CPC_DRV_UART_VCOM] +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL EUSART0 +#define SL_CPC_DRV_UART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_CPC_DRV_UART_VCOM_TX_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_CPC_DRV_UART_VCOM_RX_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_CPC_DRV_UART_VCOM_CTS_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_CPC_DRV_UART_VCOM_RTS_PORT gpioPortA +#define SL_CPC_DRV_UART_VCOM_RTS_PIN 0 + +// [EUSART_SL_CPC_DRV_UART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif /* SL_CPC_DRV_UART_VCOM_SECONDARY_CONFIG_H */ diff --git a/hardware/board/config/brd4274a_brd4002a/sl_device_init_hfxo_config.h b/hardware/board/config/brd4274a_brd4002a/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..c3dc821a7b --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/sl_device_init_hfxo_config.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// External sine wave +// Default: cmuHfxoOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal + +// Frequency <38000000-40000000> +// Default: 39000000 +#define SL_DEVICE_INIT_HFXO_FREQ 39000000 + +// CTUNE <0-255> +// Default: 140 +#define SL_DEVICE_INIT_HFXO_CTUNE 105 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4002a/sl_device_init_lfxo_config.h b/hardware/board/config/brd4274a_brd4002a/sl_device_init_lfxo_config.h new file mode 100644 index 0000000000..5d2cee4142 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/sl_device_init_lfxo_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_LFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuLfxoOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuLfxoOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 36 + +// LFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_LFXO_PRECISION 100 + +// Startup Timeout Delay +// +// 2 cycles +// 256 cycles +// 1K cycles +// 2K cycles +// 4K cycles +// 8K cycles +// 16K cycles +// 32K cycles +// Default: cmuLfxoStartupDelay_4KCycles +#define SL_DEVICE_INIT_LFXO_TIMEOUT cmuLfxoStartupDelay_4KCycles +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4002a/sl_iostream_eusart_exp_config.h b/hardware/board/config/brd4274a_brd4002a/sl_iostream_eusart_exp_config.h new file mode 100644 index 0000000000..cbe96bbdcb --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/sl_iostream_eusart_exp_config.h @@ -0,0 +1,107 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_EXP_CONFIG_H +#define SL_IOSTREAM_EUSART_EXP_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_EXP_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_EXP_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_IOSTREAM_EUSART_EXP_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_IOSTREAM_EUSART_EXP_STOP_BITS eusartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: eusartHwFlowControlNone +#define SL_IOSTREAM_EUSART_EXP_FLOW_CONTROL_TYPE eusartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_EXP_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_EXP_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_EXP_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_EXP +// $[EUSART_SL_IOSTREAM_EUSART_EXP] +#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL EUSART0 +#define SL_IOSTREAM_EUSART_EXP_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_IOSTREAM_EUSART_EXP_TX_PORT gpioPortA +#define SL_IOSTREAM_EUSART_EXP_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_IOSTREAM_EUSART_EXP_RX_PORT gpioPortA +#define SL_IOSTREAM_EUSART_EXP_RX_PIN 9 + + + +// [EUSART_SL_IOSTREAM_EUSART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4274a_brd4002a/sl_iostream_eusart_vcom_config.h b/hardware/board/config/brd4274a_brd4002a/sl_iostream_eusart_vcom_config.h new file mode 100644 index 0000000000..db8ecd8a79 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/sl_iostream_eusart_vcom_config.h @@ -0,0 +1,113 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_EUSART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_EUSART_VCOM_CONFIG_H +#define SL_IOSTREAM_EUSART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EUART settings + +// Enable High frequency mode +// Default: 1 +#define SL_IOSTREAM_EUSART_VCOM_ENABLE_HIGH_FREQUENCY 1 + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_EUSART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_IOSTREAM_EUSART_VCOM_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_IOSTREAM_EUSART_VCOM_STOP_BITS eusartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: eusartHwFlowControlNone +#define SL_IOSTREAM_EUSART_VCOM_FLOW_CONTROL_TYPE eusartHwFlowControlCtsAndRts + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_EUSART_VCOM_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_EUSART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_EUSART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_EUSART_VCOM +// $[EUSART_SL_IOSTREAM_EUSART_VCOM] +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL EUSART0 +#define SL_IOSTREAM_EUSART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_IOSTREAM_EUSART_VCOM_TX_PORT gpioPortA +#define SL_IOSTREAM_EUSART_VCOM_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_IOSTREAM_EUSART_VCOM_RX_PORT gpioPortA +#define SL_IOSTREAM_EUSART_VCOM_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_IOSTREAM_EUSART_VCOM_CTS_PORT gpioPortA +#define SL_IOSTREAM_EUSART_VCOM_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_IOSTREAM_EUSART_VCOM_RTS_PORT gpioPortA +#define SL_IOSTREAM_EUSART_VCOM_RTS_PIN 0 + +// [EUSART_SL_IOSTREAM_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4274a_brd4002a/sl_memlcd_eusart_config.h b/hardware/board/config/brd4274a_brd4002a/sl_memlcd_eusart_config.h new file mode 100644 index 0000000000..7f330a1a6e --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/sl_memlcd_eusart_config.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file + * @brief SPI abstraction used by memory lcd display + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_MEMLCD_CONFIG_H +#define SL_MEMLCD_CONFIG_H + +// <<< sl:start pin_tool >>> +// SL_MEMLCD_SPI +// $[EUSART_SL_MEMLCD_SPI] +#define SL_MEMLCD_SPI_PERIPHERAL EUSART1 +#define SL_MEMLCD_SPI_PERIPHERAL_NO 1 + +// EUSART1 TX on PC00 +#define SL_MEMLCD_SPI_TX_PORT gpioPortC +#define SL_MEMLCD_SPI_TX_PIN 0 + +// EUSART1 SCLK on PC02 +#define SL_MEMLCD_SPI_SCLK_PORT gpioPortC +#define SL_MEMLCD_SPI_SCLK_PIN 2 + +// [EUSART_SL_MEMLCD_SPI]$ + +// SL_MEMLCD_SPI_CS +// $[GPIO_SL_MEMLCD_SPI_CS] +#define SL_MEMLCD_SPI_CS_PORT gpioPortD +#define SL_MEMLCD_SPI_CS_PIN 5 + +// [GPIO_SL_MEMLCD_SPI_CS]$ + +// SL_MEMLCD_EXTCOMIN +// $[GPIO_SL_MEMLCD_EXTCOMIN] +#define SL_MEMLCD_EXTCOMIN_PORT gpioPortA +#define SL_MEMLCD_EXTCOMIN_PIN 7 + +// [GPIO_SL_MEMLCD_EXTCOMIN]$ + +// <<< sl:end pin_tool >>> + +#endif diff --git a/hardware/board/config/brd4274a_brd4002a/sl_mx25_flash_shutdown_eusart_config.h b/hardware/board/config/brd4274a_brd4002a/sl_mx25_flash_shutdown_eusart_config.h new file mode 100644 index 0000000000..fd2ae0a41f --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/sl_mx25_flash_shutdown_eusart_config.h @@ -0,0 +1,51 @@ +/***************************************************************************//** + * @file + * @brief SL_MX25_FLASH_SHUTDOWN_USART Config + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H +#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H + +// <<< sl:start pin_tool >>> +// {eusart signal=TX,RX,SCLK} SL_MX25_FLASH_SHUTDOWN +// [EUSART_SL_MX25_FLASH_SHUTDOWN] +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL EUSART1 +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 1 + +// EUSART1 TX on PC00 +#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 0 + +// EUSART1 RX on PC01 +#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 + +// EUSART1 SCLK on PC02 +#define SL_MX25_FLASH_SHUTDOWN_SCLK_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_SCLK_PIN 2 + +// [EUSART_SL_MX25_FLASH_SHUTDOWN] + +// SL_MX25_FLASH_SHUTDOWN_CS + +// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] +#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortA +#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 + +// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4002a/sl_pwm_init_led0_config.h b/hardware/board/config/brd4274a_brd4002a/sl_pwm_init_led0_config.h new file mode 100644 index 0000000000..6102dad789 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/sl_pwm_init_led0_config.h @@ -0,0 +1,62 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef PWM_INIT_LED0_CONFIG_H +#define PWM_INIT_LED0_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED0_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED0_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED0 +// $[TIMER_SL_PWM_LED0] +#define SL_PWM_LED0_PERIPHERAL TIMER0 +#define SL_PWM_LED0_PERIPHERAL_NO 0 + +#define SL_PWM_LED0_OUTPUT_CHANNEL 0 +// TIMER0 CC0 on PA05 +#define SL_PWM_LED0_OUTPUT_PORT gpioPortA +#define SL_PWM_LED0_OUTPUT_PIN 5 + +// [TIMER_SL_PWM_LED0]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // PWM_INIT_LED0_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4002a/sl_pwm_init_led1_config.h b/hardware/board/config/brd4274a_brd4002a/sl_pwm_init_led1_config.h new file mode 100644 index 0000000000..4aabf9cda7 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/sl_pwm_init_led1_config.h @@ -0,0 +1,62 @@ +/***************************************************************************//** + * @file + * @brief PWM Driver + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef PWM_INIT_LED1_CONFIG_H +#define PWM_INIT_LED1_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// PWM configuration + +// PWM frequency [Hz] +// Default: 10000 +#define SL_PWM_LED1_FREQUENCY 10000 + +// Polarity +// Active high +// Active low +// Default: PWM_ACTIVE_HIGH +#define SL_PWM_LED1_POLARITY PWM_ACTIVE_HIGH +// end pwm configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_PWM_LED1 +// $[TIMER_SL_PWM_LED1] +#define SL_PWM_LED1_PERIPHERAL TIMER1 +#define SL_PWM_LED1_PERIPHERAL_NO 1 + +#define SL_PWM_LED1_OUTPUT_CHANNEL 0 +// TIMER1 CC0 on PA06 +#define SL_PWM_LED1_OUTPUT_PORT gpioPortA +#define SL_PWM_LED1_OUTPUT_PIN 6 + +// [TIMER_SL_PWM_LED1]$ + +// <<< sl:end pin_tool >>> + +#ifdef __cplusplus +} +#endif + +#endif // PWM_INIT_LED1_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4002a/sl_rail_util_eff_config.h b/hardware/board/config/brd4274a_brd4002a/sl_rail_util_eff_config.h new file mode 100644 index 0000000000..f34e43c03c --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/sl_rail_util_eff_config.h @@ -0,0 +1,166 @@ +/***************************************************************************//** + * @file + * @brief RAIL Util for EFF0 configuration file. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_EFF_CONFIG_H +#define SL_RAIL_UTIL_EFF_CONFIG_H + +#include "em_gpio.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// EFF Configuration +// Select connected EFF device +// No connected EFF device +// EFF01Z11 +// EFF01A12 +// Default: RAIL_EFF_DEVICE_EFF01A12 +#define SL_RAIL_UTIL_EFF_DEVICE RAIL_EFF_DEVICE_EFF01A12 +// Enable Rural LNA Mode +// Default: 1 +#define SL_RAIL_UTIL_EFF_LNA_MODE_RURAL_ENABLE 1 +// Enable Urban LNA Mode +// Default: 1 +#define SL_RAIL_UTIL_EFF_LNA_MODE_URBAN_ENABLE 1 +// Enable Bypass LNA Mode +// Default: 1 +#define SL_RAIL_UTIL_EFF_LNA_MODE_BYPASS_ENABLE 1 +// Trip point between rural and urban modes, in millivolts. +// <5-1250:1> +// Default: 120 +#define SL_RAIL_UTIL_EFF_RURAL_URBAN_MV 120 +// Trip point between urban and bypass modes, in millivolts. +// <5-1250:1> +// Default: 130 +#define SL_RAIL_UTIL_EFF_URBAN_BYPASS_MV 130 +// Length of time to stay in urban mode before transitioning to rural mode, in milliseconds. +// <1-105000:1> +// Default: 30000 +#define SL_RAIL_UTIL_EFF_URBAN_DWELL_TIME_MS 30000 +// Length of time to stay in bypass mode before transitioning to urban or rural mode, in milliseconds. +// <1-105000:1> +// Default: 30000 +#define SL_RAIL_UTIL_EFF_BYPASS_DWELL_TIME_MS 30000 +// Target for CLPC slow loop, in milliwatts. +// <5-2000:1> +// Default: 630 +#define SL_RAIL_UTIL_EFF_CLPC_SLOW_LOOP_TARGET 630 +// Relationship between delta-GAINDIG/delta-power to find new GAINDIG value +// <1-100:1> +// Default: 100 +#define SL_RAIL_UTIL_EFF_CLPC_SLOW_LOOP_SLOPE 100 +// Target for CLPC fast loop, in millivolts. +// <5-1500:1> +// Default: 700 +#define SL_RAIL_UTIL_EFF_CLPC_FAST_LOOP_TARGET 700 +// Relationship between delta-GAINDIG/delta-AUXADC to find new GAINDIG value +// <1-100:1> +// Default: 100 +#define SL_RAIL_UTIL_EFF_CLPC_FAST_LOOP_SLOPE 99 +// Select CLPC mode +// Disable CLPC power control. Flare modes will only be transmit/receive. +// Allow mode changes/measurements, but no power changes +// Allow only Slow loop power changes +// Allow only Fast loop power changes +// Allow full power control +// Default: RAIL_EFF_CLPC_POWER_BOTH +#define SL_RAIL_UTIL_EFF_CLPC_ENABLE RAIL_EFF_CLPC_MODE_CHANGE +// Maximum continuous transfer power in dBm +// <20-30:1> +// Default: 20 +#define RAIL_UTIL_EFF_MAX_TX_CONTINUOUS_POWER_DBM 20 +// Maximum transmit duty cycle as a percentage +// <10-100:1> +// Default: 50 +#define RAIL_UTIL_EFF_MAX_TX_DUTY_CYCLE 50 +// Temperature of EFF above which transmit is not allowed, in degrees Kelvin +// <1-398:1> +// Default: 373 +#define SL_RAIL_UTIL_EFF_TEMPERATURE_THRESHOLD_EFF_DEGREES_K 373 +// Chip's internal temperature above which transmit is not allowed, in degrees Kelvin +// <1-398:1> +// Default: 373 +#define SL_RAIL_UTIL_EFF_TEMPERATURE_THRESHOLD_INTERNAL_DEGREES_K 373 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// CTRL0 GPIO +// SL_RAIL_UTIL_EFF_CTRL0 +// $[GPIO_SL_RAIL_UTIL_EFF_CTRL0] +#define SL_RAIL_UTIL_EFF_CTRL0_PORT gpioPortC +#define SL_RAIL_UTIL_EFF_CTRL0_PIN 4 + +// [GPIO_SL_RAIL_UTIL_EFF_CTRL0]$ + +// CTRL1 GPIO +// SL_RAIL_UTIL_EFF_CTRL1 +// $[GPIO_SL_RAIL_UTIL_EFF_CTRL1] +#define SL_RAIL_UTIL_EFF_CTRL1_PORT gpioPortC +#define SL_RAIL_UTIL_EFF_CTRL1_PIN 5 + +// [GPIO_SL_RAIL_UTIL_EFF_CTRL1]$ + +// CTRL2 GPIO +// SL_RAIL_UTIL_EFF_CTRL2 +// $[GPIO_SL_RAIL_UTIL_EFF_CTRL2] +#define SL_RAIL_UTIL_EFF_CTRL2_PORT gpioPortC +#define SL_RAIL_UTIL_EFF_CTRL2_PIN 6 + +// [GPIO_SL_RAIL_UTIL_EFF_CTRL2]$ + +// CTRL3 GPIO +// SL_RAIL_UTIL_EFF_CTRL3 +// $[GPIO_SL_RAIL_UTIL_EFF_CTRL3] +#define SL_RAIL_UTIL_EFF_CTRL3_PORT gpioPortC +#define SL_RAIL_UTIL_EFF_CTRL3_PIN 7 + +// [GPIO_SL_RAIL_UTIL_EFF_CTRL3]$ + +// TEST GPIO +// SL_RAIL_UTIL_EFF_TEST +// $[GPIO_SL_RAIL_UTIL_EFF_TEST] +#define SL_RAIL_UTIL_EFF_TEST_PORT gpioPortC +#define SL_RAIL_UTIL_EFF_TEST_PIN 3 + +// [GPIO_SL_RAIL_UTIL_EFF_TEST]$ + +// SENSE GPIO +// SL_RAIL_UTIL_EFF_SENSE +// $[GPIO_SL_RAIL_UTIL_EFF_SENSE] +#define SL_RAIL_UTIL_EFF_SENSE_PORT gpioPortC +#define SL_RAIL_UTIL_EFF_SENSE_PIN 8 + +// [GPIO_SL_RAIL_UTIL_EFF_SENSE]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_RAIL_UTIL_EFF_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4002a/sl_rail_util_pa_config.h b/hardware/board/config/brd4274a_brd4002a/sl_rail_util_pa_config.h new file mode 100644 index 0000000000..b0bde82184 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/sl_rail_util_pa_config.h @@ -0,0 +1,82 @@ +/***************************************************************************//** + * @file + * @brief Power Amplifier configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PA_CONFIG_H +#define SL_RAIL_UTIL_PA_CONFIG_H + +#include "rail_chip_specific.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PA configuration + +// Initial PA Power (deci-dBm, 100 = 10.0 dBm) +// Default: 100 +#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 + +// PA Ramp Time (microseconds) +// <0-65535:1> +// Default: 10 +#define SL_RAIL_UTIL_PA_RAMP_TIME_US 10 + +// Milli-volts on PA supply pin (PA_VDD) +// <0-65535:1> +// Default: 3600 +#define SL_RAIL_UTIL_PA_VOLTAGE_MV 3600 + +// 2.4 GHz PA Selection +// Highest Possible +// High Power (chip-specific) +// Medium Power (chip-specific) +// Low Power +// Disable +// Default: RAIL_TX_POWER_MODE_2P4GIG_HIGHEST +#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_NONE + +// Sub-1 GHz PA Selection +// Disable +// Default: RAIL_TX_POWER_MODE_NONE +#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_SUBGIG_HIGHEST + +// Header file containing custom PA curves +// Default: "pa_curves_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" + +// Header file containing PA curve types +// Default: "pa_curve_types_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" + +// Enable PA Calibration +// Default: 0 +#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 0 + +// +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4002a/sl_rail_util_pti_config.h b/hardware/board/config/brd4274a_brd4002a/sl_rail_util_pti_config.h new file mode 100644 index 0000000000..1ae930e38f --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/sl_rail_util_pti_config.h @@ -0,0 +1,73 @@ +/***************************************************************************//** + * @file + * @brief Packet Trace Information configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PTI_CONFIG_H +#define SL_RAIL_UTIL_PTI_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PTI Configuration + +// PTI mode +// UART +// UART onewire +// SPI +// Disabled +// Default: RAIL_PTI_MODE_UART +#define SL_RAIL_UTIL_PTI_MODE RAIL_PTI_MODE_UART + +// PTI Baud Rate (Hertz) +// <147800-20000000:1> +// Default: 1600000 +#define SL_RAIL_UTIL_PTI_BAUD_RATE_HZ 1600000 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_RAIL_UTIL_PTI +// $[PTI_SL_RAIL_UTIL_PTI] +#define SL_RAIL_UTIL_PTI_PERIPHERAL PTI + +// PTI DOUT on PD03 +#define SL_RAIL_UTIL_PTI_DOUT_PORT gpioPortD +#define SL_RAIL_UTIL_PTI_DOUT_PIN 3 + +// PTI DFRAME on PD04 +#define SL_RAIL_UTIL_PTI_DFRAME_PORT gpioPortD +#define SL_RAIL_UTIL_PTI_DFRAME_PIN 4 + + +// [PTI_SL_RAIL_UTIL_PTI]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_RAIL_UTIL_PTI_CONFIG_H diff --git a/hardware/board/config/brd4109a_brd4002a/sl_simple_button_btn0_config.h b/hardware/board/config/brd4274a_brd4002a/sl_simple_button_btn0_config.h similarity index 100% rename from hardware/board/config/brd4109a_brd4002a/sl_simple_button_btn0_config.h rename to hardware/board/config/brd4274a_brd4002a/sl_simple_button_btn0_config.h diff --git a/hardware/board/config/brd4109a_brd4002a/sl_simple_button_btn1_config.h b/hardware/board/config/brd4274a_brd4002a/sl_simple_button_btn1_config.h similarity index 100% rename from hardware/board/config/brd4109a_brd4002a/sl_simple_button_btn1_config.h rename to hardware/board/config/brd4274a_brd4002a/sl_simple_button_btn1_config.h diff --git a/hardware/board/config/brd4274a_brd4002a/sl_simple_led_led0_config.h b/hardware/board/config/brd4274a_brd4002a/sl_simple_led_led0_config.h new file mode 100644 index 0000000000..fe98957dcb --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/sl_simple_led_led0_config.h @@ -0,0 +1,44 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED0_CONFIG_H +#define SL_SIMPLE_LED_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED0_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED0 +// $[GPIO_SL_SIMPLE_LED_LED0] +#define SL_SIMPLE_LED_LED0_PORT gpioPortA +#define SL_SIMPLE_LED_LED0_PIN 5 + +// [GPIO_SL_SIMPLE_LED_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED0_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4002a/sl_simple_led_led1_config.h b/hardware/board/config/brd4274a_brd4002a/sl_simple_led_led1_config.h new file mode 100644 index 0000000000..aa9c5c343d --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/sl_simple_led_led1_config.h @@ -0,0 +1,44 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED1_CONFIG_H +#define SL_SIMPLE_LED_LED1_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED1_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED1 +// $[GPIO_SL_SIMPLE_LED_LED1] +#define SL_SIMPLE_LED_LED1_PORT gpioPortA +#define SL_SIMPLE_LED_LED1_PIN 6 + +// [GPIO_SL_SIMPLE_LED_LED1]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED1_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4002a/sl_spidrv_eusart_exp_config.h b/hardware/board/config/brd4274a_brd4002a/sl_spidrv_eusart_exp_config.h new file mode 100644 index 0000000000..69cbb27a77 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/sl_spidrv_eusart_exp_config.h @@ -0,0 +1,89 @@ +/***************************************************************************//** + * @file + * @brief SPIDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SPIDRV_EUSART_EXP_CONFIG_H +#define SL_SPIDRV_EUSART_EXP_CONFIG_H + +#include "spidrv.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// SPIDRV settings + +// SPI bitrate +// Default: 1000000 +#define SL_SPIDRV_EUSART_EXP_BITRATE 1000000 + +// SPI frame length <7-16> +// Default: 8 +#define SL_SPIDRV_EUSART_EXP_FRAME_LENGTH 8 + +// SPI mode +// Master +// Slave +#define SL_SPIDRV_EUSART_EXP_TYPE spidrvMaster + +// Bit order on the SPI bus +// LSB transmitted first +// MSB transmitted first +#define SL_SPIDRV_EUSART_EXP_BIT_ORDER spidrvBitOrderMsbFirst + +// SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define SL_SPIDRV_EUSART_EXP_CLOCK_MODE spidrvClockMode0 + +// SPI master chip select (CS) control scheme. +// CS controlled by the SPI driver +// CS controlled by the application +#define SL_SPIDRV_EUSART_EXP_CS_CONTROL spidrvCsControlAuto + +// SPI slave transfer start scheme +// Transfer starts immediately +// Transfer starts when the bus is idle (CS deasserted) +// Only applies if instance type is spidrvSlave +#define SL_SPIDRV_EUSART_EXP_SLAVE_START_MODE spidrvSlaveStartImmediate +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_SPIDRV_EUSART_EXP +// $[EUSART_SL_SPIDRV_EUSART_EXP] +#define SL_SPIDRV_EUSART_EXP_PERIPHERAL EUSART1 +#define SL_SPIDRV_EUSART_EXP_PERIPHERAL_NO 1 + +// EUSART1 TX on PC00 +#define SL_SPIDRV_EUSART_EXP_TX_PORT gpioPortC +#define SL_SPIDRV_EUSART_EXP_TX_PIN 0 + +// EUSART1 RX on PC01 +#define SL_SPIDRV_EUSART_EXP_RX_PORT gpioPortC +#define SL_SPIDRV_EUSART_EXP_RX_PIN 1 + +// EUSART1 SCLK on PC02 +#define SL_SPIDRV_EUSART_EXP_SCLK_PORT gpioPortC +#define SL_SPIDRV_EUSART_EXP_SCLK_PIN 2 + +// EUSART1 CS on PB04 +#define SL_SPIDRV_EUSART_EXP_CS_PORT gpioPortB +#define SL_SPIDRV_EUSART_EXP_CS_PIN 4 + +// [EUSART_SL_SPIDRV_EUSART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_SPIDRV_EUSART_EXP_CONFIG_HEUSART_ diff --git a/hardware/board/config/brd4274a_brd4002a/sl_uartdrv_eusart_exp_config.h b/hardware/board/config/brd4274a_brd4002a/sl_uartdrv_eusart_exp_config.h new file mode 100644 index 0000000000..1db46bd885 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/sl_uartdrv_eusart_exp_config.h @@ -0,0 +1,100 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_EXP_CONFIG_H +#define SL_UARTDRV_EUSART_EXP_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_EXP_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_EXP_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_EXP_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_EXP_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHw +#define SL_UARTDRV_EUSART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_EXP_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_EXP_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_EXP_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_EXP +// $[EUSART_SL_UARTDRV_EUSART_EXP] +#define SL_UARTDRV_EUSART_EXP_PERIPHERAL EUSART0 +#define SL_UARTDRV_EUSART_EXP_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_UARTDRV_EUSART_EXP_TX_PORT gpioPortA +#define SL_UARTDRV_EUSART_EXP_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_UARTDRV_EUSART_EXP_RX_PORT gpioPortA +#define SL_UARTDRV_EUSART_EXP_RX_PIN 9 + + + +// [EUSART_SL_UARTDRV_EUSART_EXP]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_EXP_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4002a/sl_uartdrv_eusart_vcom_config.h b/hardware/board/config/brd4274a_brd4002a/sl_uartdrv_eusart_vcom_config.h new file mode 100644 index 0000000000..7db0d36941 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/sl_uartdrv_eusart_vcom_config.h @@ -0,0 +1,106 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV_EUSART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_EUSART_VCOM_CONFIG_H +#define SL_UARTDRV_EUSART_VCOM_CONFIG_H + +#include "em_eusart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// EUSART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_EUSART_VCOM_BAUDRATE 115200 + +// Low frequency mode +// True +// False +#define SL_UARTDRV_EUSART_VCOM_LF_MODE false + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: eusartNoParity +#define SL_UARTDRV_EUSART_VCOM_PARITY eusartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: eusartStopbits1 +#define SL_UARTDRV_EUSART_VCOM_STOP_BITS eusartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHw +#define SL_UARTDRV_EUSART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlHwUart + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Oversampling disabled +// Default: eusartOVS16 +#define SL_UARTDRV_EUSART_VCOM_OVERSAMPLING eusartOVS16 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// False +// True +// Default: eusartMajorityVoteEnable +#define SL_UARTDRV_EUSART_VCOM_MVDIS eusartMajorityVoteEnable + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_EUSART_VCOM_TX_BUFFER_SIZE 6 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_EUSART_VCOM +// $[EUSART_SL_UARTDRV_EUSART_VCOM] +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL EUSART0 +#define SL_UARTDRV_EUSART_VCOM_PERIPHERAL_NO 0 + +// EUSART0 TX on PA08 +#define SL_UARTDRV_EUSART_VCOM_TX_PORT gpioPortA +#define SL_UARTDRV_EUSART_VCOM_TX_PIN 8 + +// EUSART0 RX on PA09 +#define SL_UARTDRV_EUSART_VCOM_RX_PORT gpioPortA +#define SL_UARTDRV_EUSART_VCOM_RX_PIN 9 + +// EUSART0 CTS on PA10 +#define SL_UARTDRV_EUSART_VCOM_CTS_PORT gpioPortA +#define SL_UARTDRV_EUSART_VCOM_CTS_PIN 10 + +// EUSART0 RTS on PA00 +#define SL_UARTDRV_EUSART_VCOM_RTS_PORT gpioPortA +#define SL_UARTDRV_EUSART_VCOM_RTS_PIN 0 + +// [EUSART_SL_UARTDRV_EUSART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_EUSART_VCOM_CONFIG_H diff --git a/hardware/board/config/brd4274a_brd4002a/sl_usbd_driver_config.h b/hardware/board/config/brd4274a_brd4002a/sl_usbd_driver_config.h new file mode 100644 index 0000000000..005a845bd2 --- /dev/null +++ b/hardware/board/config/brd4274a_brd4002a/sl_usbd_driver_config.h @@ -0,0 +1,30 @@ +/***************************************************************************//** + * @file + * @brief USBD Hardware Configuration + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_USBD_DRIVER_CONFIG_H +#define SL_USBD_DRIVER_CONFIG_H + +// <<< sl:start pin_tool >>> +// SL_USBD_DRIVER_VBUS_SENSE +// $[GPIO_SL_USBD_DRIVER_VBUS_SENSE] +#define SL_USBD_DRIVER_VBUS_SENSE_PORT gpioPortD +#define SL_USBD_DRIVER_VBUS_SENSE_PIN 2 + +// [GPIO_SL_USBD_DRIVER_VBUS_SENSE]$ +// <<< sl:end pin_tool >>> + +#endif // SL_USBD_DRIVER_CONFIG_H diff --git a/hardware/board/config/brd4328a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h b/hardware/board/config/brd4328a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h deleted file mode 100644 index dcb06e3f9d..0000000000 --- a/hardware/board/config/brd4328a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_INST0_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_INST0 -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_INST0] -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL TIMER0 -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL_NO 0 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_CHANNEL 0 -// TIMER0 CC0 on PB04 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PORT gpioPortB -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PIN 4 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_CHANNEL 1 -// TIMER0 CC1 on PB05 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PORT gpioPortB -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PIN 5 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_CHANNEL 2 -// TIMER0 CC2 on PB06 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PORT gpioPortB -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PIN 6 - -// [TIMER_SL_SIMPLE_RGB_PWM_LED_INST0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H diff --git a/hardware/board/config/brd4328a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h b/hardware/board/config/brd4328a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h new file mode 100644 index 0000000000..512cfe4a0a --- /dev/null +++ b/hardware/board/config/brd4328a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief Simple RGB PWM Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple RGB PWM LED Configuration +// PWM frequency [Hz] +// Sets the frequency of the PWM signal +// 0 = Don't care +// Default: 10000 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_FREQUENCY 10000 + +// PWM resolution <2-65536> +// Specifies the PWM (dimming) resolution. I.e. if you want a +// dimming resolution that takes the input values from 0 to 99, +// set this value to 100 +// Default: 256 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RESOLUTION 256 + +// Red LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Green LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Blue LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_RGB_PWM_LED_RGB_LED0 +// $[TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0] +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL TIMER0 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL_NO 0 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_CHANNEL 0 +// TIMER0 CC0 on PB04 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PIN 4 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_CHANNEL 1 +// TIMER0 CC1 on PB05 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PIN 5 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_CHANNEL 2 +// TIMER0 CC2 on PB06 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PIN 6 + +// [TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H diff --git a/hardware/board/config/brd4328a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h b/hardware/board/config/brd4328a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h deleted file mode 100644 index dcb06e3f9d..0000000000 --- a/hardware/board/config/brd4328a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h +++ /dev/null @@ -1,84 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple RGB PWM Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H -#define SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple RGB PWM LED Configuration -// PWM frequency [Hz] -// Sets the frequency of the PWM signal -// 0 = Don't care -// Default: 10000 -#define SL_SIMPLE_RGB_PWM_LED_INST0_FREQUENCY 10000 - -// PWM resolution <2-65536> -// Specifies the PWM (dimming) resolution. I.e. if you want a -// dimming resolution that takes the input values from 0 to 99, -// set this value to 100 -// Default: 256 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RESOLUTION 256 - -// Red LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Green LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW - -// Blue LED Polarity -// Active low -// Active high -// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_RGB_PWM_LED_INST0 -// $[TIMER_SL_SIMPLE_RGB_PWM_LED_INST0] -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL TIMER0 -#define SL_SIMPLE_RGB_PWM_LED_INST0_PERIPHERAL_NO 0 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_CHANNEL 0 -// TIMER0 CC0 on PB04 -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PORT gpioPortB -#define SL_SIMPLE_RGB_PWM_LED_INST0_RED_PIN 4 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_CHANNEL 1 -// TIMER0 CC1 on PB05 -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PORT gpioPortB -#define SL_SIMPLE_RGB_PWM_LED_INST0_GREEN_PIN 5 - -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_CHANNEL 2 -// TIMER0 CC2 on PB06 -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PORT gpioPortB -#define SL_SIMPLE_RGB_PWM_LED_INST0_BLUE_PIN 6 - -// [TIMER_SL_SIMPLE_RGB_PWM_LED_INST0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_RGB_PWM_LED_INST0_CONFIG_H diff --git a/hardware/board/config/brd4328a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h b/hardware/board/config/brd4328a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h new file mode 100644 index 0000000000..512cfe4a0a --- /dev/null +++ b/hardware/board/config/brd4328a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h @@ -0,0 +1,84 @@ +/***************************************************************************//** + * @file + * @brief Simple RGB PWM Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple RGB PWM LED Configuration +// PWM frequency [Hz] +// Sets the frequency of the PWM signal +// 0 = Don't care +// Default: 10000 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_FREQUENCY 10000 + +// PWM resolution <2-65536> +// Specifies the PWM (dimming) resolution. I.e. if you want a +// dimming resolution that takes the input values from 0 to 99, +// set this value to 100 +// Default: 256 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RESOLUTION 256 + +// Red LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Green LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW + +// Blue LED Polarity +// Active low +// Active high +// Default: SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_POLARITY SL_SIMPLE_RGB_PWM_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_RGB_PWM_LED_RGB_LED0 +// $[TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0] +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL TIMER0 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_PERIPHERAL_NO 0 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_CHANNEL 0 +// TIMER0 CC0 on PB04 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_RED_PIN 4 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_CHANNEL 1 +// TIMER0 CC1 on PB05 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_GREEN_PIN 5 + +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_CHANNEL 2 +// TIMER0 CC2 on PB06 +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PORT gpioPortB +#define SL_SIMPLE_RGB_PWM_LED_RGB_LED0_BLUE_PIN 6 + +// [TIMER_SL_SIMPLE_RGB_PWM_LED_RGB_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_RGB_PWM_LED_RGB_LED0_CONFIG_H diff --git a/hardware/board/config/component/brd2207a_config.slcc b/hardware/board/config/component/brd2207a_config.slcc index 0c9e904370..d837e31388 100644 --- a/hardware/board/config/component/brd2207a_config.slcc +++ b/hardware/board/config/component/brd2207a_config.slcc @@ -186,13 +186,13 @@ - override: component: simple_rgb_pwm_led file_id: simple_rgb_pwm_led_config - instance: inst0 - path: brd2207a/sl_simple_rgb_pwm_led_inst0_config.h + instance: rgb_led0 + path: brd2207a/sl_simple_rgb_pwm_led_rgb_led0_config.h - override: component: simple_rgb_pwm_led file_id: simple_rgb_pwm_led_config - instance: inst1 - path: brd2207a/sl_simple_rgb_pwm_led_inst1_config.h + instance: rgb_led1 + path: brd2207a/sl_simple_rgb_pwm_led_rgb_led1_config.h - override: component: spidrv file_id: spidrv_config diff --git a/hardware/board/config/component/brd2601a_config.slcc b/hardware/board/config/component/brd2601a_config.slcc index 69f49b7daf..cacc6a7071 100644 --- a/hardware/board/config/component/brd2601a_config.slcc +++ b/hardware/board/config/component/brd2601a_config.slcc @@ -258,8 +258,8 @@ - override: component: simple_rgb_pwm_led file_id: simple_rgb_pwm_led_config - instance: inst0 - path: brd2601a/sl_simple_rgb_pwm_led_inst0_config.h + instance: rgb_led0 + path: brd2601a/sl_simple_rgb_pwm_led_rgb_led0_config.h - override: component: spidrv file_id: spidrv_config diff --git a/hardware/board/config/component/brd2601b_config.slcc b/hardware/board/config/component/brd2601b_config.slcc index af28ba2a28..b57c22ad94 100644 --- a/hardware/board/config/component/brd2601b_config.slcc +++ b/hardware/board/config/component/brd2601b_config.slcc @@ -258,8 +258,8 @@ - override: component: simple_rgb_pwm_led file_id: simple_rgb_pwm_led_config - instance: inst0 - path: brd2601b/sl_simple_rgb_pwm_led_inst0_config.h + instance: rgb_led0 + path: brd2601b/sl_simple_rgb_pwm_led_rgb_led0_config.h - override: component: spidrv file_id: spidrv_config diff --git a/hardware/board/config/component/brd2603a_config.slcc b/hardware/board/config/component/brd2603a_config.slcc index c48d34a28a..ac19a94645 100644 --- a/hardware/board/config/component/brd2603a_config.slcc +++ b/hardware/board/config/component/brd2603a_config.slcc @@ -269,8 +269,8 @@ - override: component: simple_rgb_pwm_led file_id: simple_rgb_pwm_led_config - instance: inst0 - path: brd2603a/sl_simple_rgb_pwm_led_inst0_config.h + instance: rgb_led0 + path: brd2603a/sl_simple_rgb_pwm_led_rgb_led0_config.h - override: component: spidrv file_id: spidrv_config diff --git a/hardware/board/config/component/brd2703a_config.slcc b/hardware/board/config/component/brd2703a_config.slcc new file mode 100644 index 0000000000..c864200ebd --- /dev/null +++ b/hardware/board/config/component/brd2703a_config.slcc @@ -0,0 +1,243 @@ +!!omap +- id: brd2703a_config +- label: brd2703a config +- description: Configuration files for BRD2703A +- package: platform +- category: Platform|Board|Config +- quality: production +- ui_hints: + visibility: never +- root_path: hardware/board/config +- requires: + - name: brd2703a +- provides: + - name: brd2703a_config +- config_file: + - override: + component: board_control + file_id: board_control_config + path: brd2703a/sl_board_control_config.h + - override: + component: bootloader_euart_driver + file_id: btl_euart_driver_cfg + path: brd2703a/btl_euart_driver_cfg.h + - override: + component: bootloader_gpio_activation + file_id: btl_gpio_activation_cfg + path: brd2703a/btl_gpio_activation_cfg.h + - override: + component: bootloader_uart_driver + file_id: btl_uart_driver_cfg + path: brd2703a/btl_uart_driver_cfg.h + - override: + component: cpc_primary_driver_spi_usart + file_id: cpc_drv_spi_primary_config + instance: mikroe + path: brd2703a/sl_cpc_drv_primary_spi_usart_mikroe_config.h + - override: + component: cpc_primary_driver_uart_usart + file_id: cpc_drv_uart_primary_config + instance: vcom + path: brd2703a/sl_cpc_drv_primary_uart_usart_vcom_config.h + - override: + component: cpc_primary_driver_uart_usart + file_id: cpc_drv_uart_primary_config + instance: mikroe + path: brd2703a/sl_cpc_drv_primary_uart_usart_mikroe_config.h + - override: + component: cpc_secondary_driver_spi_eusart + file_id: cpc_drv_secondary_spi_eusart_config + instance: mikroe + path: brd2703a/sl_cpc_drv_secondary_spi_eusart_mikroe_config.h + - override: + component: cpc_secondary_driver_spi_usart + file_id: cpc_drv_secondary_spi_usart_config + instance: mikroe + path: brd2703a/sl_cpc_drv_secondary_spi_usart_mikroe_config.h + - override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_secondary_uart_eusart_config + instance: vcom + path: brd2703a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h + - override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_secondary_uart_eusart_config + instance: mikroe + path: brd2703a/sl_cpc_drv_secondary_uart_eusart_mikroe_config.h + - override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_secondary_uart_usart_config + instance: vcom + path: brd2703a/sl_cpc_drv_secondary_uart_usart_vcom_config.h + - override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_secondary_uart_usart_config + instance: mikroe + path: brd2703a/sl_cpc_drv_secondary_uart_usart_mikroe_config.h + - override: + component: device_init_lfxo + file_id: device_init_lfxo_config + path: brd2703a/sl_device_init_lfxo_config.h + - override: + component: i2cspm + file_id: i2cspm_config + instance: mikroe + path: brd2703a/sl_i2cspm_mikroe_config.h + - override: + component: i2cspm + file_id: i2cspm_config + instance: qwiic + path: brd2703a/sl_i2cspm_qwiic_config.h + - override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: vcom + path: brd2703a/sl_iostream_eusart_vcom_config.h + - override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: mikroe + path: brd2703a/sl_iostream_eusart_mikroe_config.h + - override: + component: iostream_usart + file_id: iostream_usart_config + instance: vcom + path: brd2703a/sl_iostream_usart_vcom_config.h + - override: + component: iostream_usart + file_id: iostream_usart_config + instance: mikroe + path: brd2703a/sl_iostream_usart_mikroe_config.h + - override: + component: iot_flash + file_id: iot_flash_cfg + instance: msc + path: brd2703a/iot_flash_cfg_msc.h + - override: + component: iot_flash + file_id: iot_flash_cfg + instance: mikroe + path: brd2703a/iot_flash_cfg_mikroe.h + - override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: mikroe + path: brd2703a/iot_i2c_cfg_mikroe.h + - override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: qwiic + path: brd2703a/iot_i2c_cfg_qwiic.h + - override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led0 + path: brd2703a/iot_pwm_cfg_led0.h + - override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led1 + path: brd2703a/iot_pwm_cfg_led1.h + - override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: mikroe + path: brd2703a/iot_pwm_cfg_mikroe.h + - override: + component: iot_spi + file_id: iot_spi_cfg + instance: mikroe + path: brd2703a/iot_spi_cfg_mikroe.h + - override: + component: iot_uart + file_id: iot_uart_cfg + instance: vcom + path: brd2703a/iot_uart_cfg_vcom.h + - override: + component: iot_uart + file_id: iot_uart_cfg + instance: mikroe + path: brd2703a/iot_uart_cfg_mikroe.h + - override: + component: iot_uart + file_id: iot_uart_cfg + instance: loopback + path: brd2703a/iot_uart_cfg_loopback.h + - override: + component: pwm + file_id: pwm_config + instance: led0 + path: brd2703a/sl_pwm_init_led0_config.h + - override: + component: pwm + file_id: pwm_config + instance: led1 + path: brd2703a/sl_pwm_init_led1_config.h + - override: + component: pwm + file_id: pwm_config + instance: mikroe + path: brd2703a/sl_pwm_init_mikroe_config.h + - override: + component: rail_util_pa + file_id: rail_util_pa_config + path: brd2703a/sl_rail_util_pa_config.h + - override: + component: rail_util_pti + file_id: rail_util_pti_config + path: brd2703a/sl_rail_util_pti_config.h + - override: + component: simple_button + file_id: simple_button_config + instance: btn0 + path: brd2703a/sl_simple_button_btn0_config.h + - override: + component: simple_button + file_id: simple_button_config + instance: btn1 + path: brd2703a/sl_simple_button_btn1_config.h + - override: + component: simple_led + file_id: simple_led_config + instance: led0 + path: brd2703a/sl_simple_led_led0_config.h + - override: + component: simple_led + file_id: simple_led_config + instance: led1 + path: brd2703a/sl_simple_led_led1_config.h + - override: + component: spidrv + file_id: spidrv_config + instance: mikroe + path: brd2703a/sl_spidrv_mikroe_config.h + - override: + component: spidrv_eusart + file_id: spidrv_eusart_config + instance: mikroe + path: brd2703a/sl_spidrv_eusart_mikroe_config.h + - override: + component: spidrv_usart + file_id: spidrv_usart_config + instance: mikroe + path: brd2703a/sl_spidrv_usart_mikroe_config.h + - override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: vcom + path: brd2703a/sl_uartdrv_eusart_vcom_config.h + - override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: mikroe + path: brd2703a/sl_uartdrv_eusart_mikroe_config.h + - override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: vcom + path: brd2703a/sl_uartdrv_usart_vcom_config.h + - override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: mikroe + path: brd2703a/sl_uartdrv_usart_mikroe_config.h diff --git a/hardware/board/config/component/brd4109a_config.slcc b/hardware/board/config/component/brd4109a_config.slcc deleted file mode 100644 index a851f747ed..0000000000 --- a/hardware/board/config/component/brd4109a_config.slcc +++ /dev/null @@ -1,823 +0,0 @@ -!!omap -- id: brd4109a_config -- label: brd4109a config -- description: Configuration files for BRD4109A -- package: platform -- category: Platform|Board|Config -- quality: production -- ui_hints: - visibility: never -- root_path: hardware/board/config -- requires: - - name: brd4109a -- provides: - - name: brd4109a_config -- config_file: - - condition: - - brd4001a - override: - component: board_control - file_id: board_control_config - path: brd4109a_brd4001a/sl_board_control_config.h - - condition: - - brd4002a - override: - component: board_control - file_id: board_control_config - path: brd4109a_brd4002a/sl_board_control_config.h - - condition: - - brd4001a - override: - component: bootloader_euart_driver - file_id: btl_euart_driver_cfg - path: brd4109a_brd4001a/btl_euart_driver_cfg.h - - condition: - - brd4001a - override: - component: bootloader_ezsp_gpio_activation - file_id: ezsp_gpio_activation_cfg - path: brd4109a_brd4001a/btl_ezsp_gpio_activation_cfg.h - - condition: - - brd4001a - override: - component: bootloader_gpio_activation - file_id: btl_gpio_activation_cfg - path: brd4109a_brd4001a/btl_gpio_activation_cfg.h - - condition: - - brd4001a - override: - component: bootloader_spi_controller_eusart_driver - file_id: btl_spi_controller_eusart_driver_cfg - path: brd4109a_brd4001a/btl_spi_controller_eusart_driver_cfg.h - - condition: - - brd4001a - override: - component: bootloader_spi_controller_usart_driver - file_id: btl_spi_controller_usart_driver_cfg - path: brd4109a_brd4001a/btl_spi_controller_usart_driver_cfg.h - - condition: - - brd4001a - override: - component: bootloader_spi_peripheral_eusart_driver - file_id: btl_spi_peripheral_eusart_driver_cfg - path: brd4109a_brd4001a/btl_spi_peripheral_eusart_driver_cfg.h - - condition: - - brd4001a - override: - component: bootloader_spi_peripheral_usart_driver - file_id: btl_spi_peripheral_usart_driver_cfg - path: brd4109a_brd4001a/btl_spi_peripheral_usart_driver_cfg.h - - condition: - - brd4001a - override: - component: bootloader_uart_driver - file_id: btl_uart_driver_cfg - path: brd4109a_brd4001a/btl_uart_driver_cfg.h - - condition: - - brd4001a - override: - component: cpc_primary_driver_spi_usart - file_id: cpc_drv_spi_primary_config - instance: exp - path: brd4109a_brd4001a/sl_cpc_drv_primary_spi_usart_exp_config.h - - condition: - - brd4001a - override: - component: cpc_primary_driver_uart_usart - file_id: cpc_drv_uart_primary_config - instance: vcom - path: brd4109a_brd4001a/sl_cpc_drv_primary_uart_usart_vcom_config.h - - condition: - - brd4001a - override: - component: cpc_primary_driver_uart_usart - file_id: cpc_drv_uart_primary_config - instance: exp - path: brd4109a_brd4001a/sl_cpc_drv_primary_uart_usart_exp_config.h - - condition: - - brd4001a - override: - component: cpc_secondary_driver_spi_eusart - file_id: cpc_drv_secondary_spi_eusart_config - instance: exp - path: brd4109a_brd4001a/sl_cpc_drv_secondary_spi_eusart_exp_config.h - - condition: - - brd4001a - override: - component: cpc_secondary_driver_spi_usart - file_id: cpc_drv_secondary_spi_usart_config - instance: exp - path: brd4109a_brd4001a/sl_cpc_drv_secondary_spi_usart_exp_config.h - - condition: - - brd4001a - override: - component: cpc_secondary_driver_uart_eusart - file_id: cpc_drv_secondary_uart_eusart_config - instance: vcom - path: brd4109a_brd4001a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h - - condition: - - brd4001a - override: - component: cpc_secondary_driver_uart_eusart - file_id: cpc_drv_secondary_uart_eusart_config - instance: exp - path: brd4109a_brd4001a/sl_cpc_drv_secondary_uart_eusart_exp_config.h - - condition: - - brd4001a - override: - component: cpc_secondary_driver_uart_usart - file_id: cpc_drv_secondary_uart_usart_config - instance: vcom - path: brd4109a_brd4001a/sl_cpc_drv_secondary_uart_usart_vcom_config.h - - condition: - - brd4001a - override: - component: cpc_secondary_driver_uart_usart - file_id: cpc_drv_secondary_uart_usart_config - instance: exp - path: brd4109a_brd4001a/sl_cpc_drv_secondary_uart_usart_exp_config.h - - condition: - - brd4001a - override: - component: device_init_hfxo - file_id: device_init_hfxo_config - path: brd4109a_brd4001a/sl_device_init_hfxo_config.h - - condition: - - brd4001a - override: - component: device_init_lfxo - file_id: device_init_lfxo_config - path: brd4109a_brd4001a/sl_device_init_lfxo_config.h - - condition: - - brd4001a - override: - component: i2cspm - file_id: i2cspm_config - instance: sensor - path: brd4109a_brd4001a/sl_i2cspm_sensor_config.h - - condition: - - brd4001a - override: - component: iostream_eusart - file_id: iostream_eusart_config - instance: vcom - path: brd4109a_brd4001a/sl_iostream_eusart_vcom_config.h - - condition: - - brd4001a - override: - component: iostream_eusart - file_id: iostream_eusart_config - instance: exp - path: brd4109a_brd4001a/sl_iostream_eusart_exp_config.h - - condition: - - brd4001a - override: - component: iostream_usart - file_id: iostream_usart_config - instance: vcom - path: brd4109a_brd4001a/sl_iostream_usart_vcom_config.h - - condition: - - brd4001a - override: - component: iostream_usart - file_id: iostream_usart_config - instance: exp - path: brd4109a_brd4001a/sl_iostream_usart_exp_config.h - - condition: - - brd4001a - override: - component: iot_flash - file_id: iot_flash_cfg - instance: msc - path: brd4109a_brd4001a/iot_flash_cfg_msc.h - - condition: - - brd4001a - override: - component: iot_flash - file_id: iot_flash_cfg - instance: exp - path: brd4109a_brd4001a/iot_flash_cfg_exp.h - - condition: - - brd4001a - override: - component: iot_flash - file_id: iot_flash_cfg - instance: spiflash - path: brd4109a_brd4001a/iot_flash_cfg_spiflash.h - - condition: - - brd4001a - override: - component: iot_i2c - file_id: iot_i2c_cfg - instance: sensor - path: brd4109a_brd4001a/iot_i2c_cfg_sensor.h - - condition: - - brd4001a - override: - component: iot_i2c - file_id: iot_i2c_cfg - instance: exp - path: brd4109a_brd4001a/iot_i2c_cfg_exp.h - - condition: - - brd4001a - override: - component: iot_i2c - file_id: iot_i2c_cfg - instance: test - path: brd4109a_brd4001a/iot_i2c_cfg_test.h - - condition: - - brd4001a - override: - component: iot_pwm - file_id: iot_pwm_cfg - instance: led0 - path: brd4109a_brd4001a/iot_pwm_cfg_led0.h - - condition: - - brd4001a - override: - component: iot_pwm - file_id: iot_pwm_cfg - instance: led1 - path: brd4109a_brd4001a/iot_pwm_cfg_led1.h - - condition: - - brd4001a - override: - component: iot_pwm - file_id: iot_pwm_cfg - instance: exp - path: brd4109a_brd4001a/iot_pwm_cfg_exp.h - - condition: - - brd4001a - override: - component: iot_spi - file_id: iot_spi_cfg - instance: exp - path: brd4109a_brd4001a/iot_spi_cfg_exp.h - - condition: - - brd4001a - override: - component: iot_spi - file_id: iot_spi_cfg - instance: loopback - path: brd4109a_brd4001a/iot_spi_cfg_loopback.h - - condition: - - brd4001a - override: - component: iot_uart - file_id: iot_uart_cfg - instance: vcom - path: brd4109a_brd4001a/iot_uart_cfg_vcom.h - - condition: - - brd4001a - override: - component: iot_uart - file_id: iot_uart_cfg - instance: exp - path: brd4109a_brd4001a/iot_uart_cfg_exp.h - - condition: - - brd4001a - override: - component: iot_uart - file_id: iot_uart_cfg - instance: loopback - path: brd4109a_brd4001a/iot_uart_cfg_loopback.h - - condition: - - brd4001a - override: - component: legacy_ncp_spi - file_id: legacy_ncp_spi_config - path: brd4109a_brd4001a/legacy_ncp_spi_config.h - - condition: - - brd4001a - override: - component: memlcd_eusart - file_id: sl_memlcd_eusart_config - path: brd4109a_brd4001a/sl_memlcd_eusart_config.h - - condition: - - brd4001a - override: - component: memlcd_usart - file_id: sl_memlcd_usart_config - path: brd4109a_brd4001a/sl_memlcd_usart_config.h - - condition: - - brd4001a - override: - component: mx25_flash_shutdown_eusart - file_id: mx25_flash_shutdown_eusart_config - path: brd4109a_brd4001a/sl_mx25_flash_shutdown_eusart_config.h - - condition: - - brd4001a - override: - component: mx25_flash_shutdown_usart - file_id: mx25_flash_shutdown_usart_config - path: brd4109a_brd4001a/sl_mx25_flash_shutdown_usart_config.h - - condition: - - brd4001a - override: - component: ot_ncp_spidrv - file_id: sl_ncp_spidrv_usart_config - path: brd4109a_brd4001a/sl_ncp_spidrv_usart_config.h - - condition: - - brd4001a - override: - component: pwm - file_id: pwm_config - instance: led0 - path: brd4109a_brd4001a/sl_pwm_init_led0_config.h - - condition: - - brd4001a - override: - component: pwm - file_id: pwm_config - instance: led1 - path: brd4109a_brd4001a/sl_pwm_init_led1_config.h - - condition: - - brd4001a - override: - component: rail_util_pa - file_id: rail_util_pa_config - path: brd4109a_brd4001a/sl_rail_util_pa_config.h - - condition: - - brd4001a - override: - component: rail_util_pti - file_id: rail_util_pti_config - path: brd4109a_brd4001a/sl_rail_util_pti_config.h - - condition: - - brd4001a - override: - component: simple_button - file_id: simple_button_config - instance: btn0 - path: brd4109a_brd4001a/sl_simple_button_btn0_config.h - - condition: - - brd4001a - override: - component: simple_button - file_id: simple_button_config - instance: btn1 - path: brd4109a_brd4001a/sl_simple_button_btn1_config.h - - condition: - - brd4001a - override: - component: simple_led - file_id: simple_led_config - instance: led0 - path: brd4109a_brd4001a/sl_simple_led_led0_config.h - - condition: - - brd4001a - override: - component: simple_led - file_id: simple_led_config - instance: led1 - path: brd4109a_brd4001a/sl_simple_led_led1_config.h - - condition: - - brd4001a - override: - component: spidrv - file_id: spidrv_config - instance: exp - path: brd4109a_brd4001a/sl_spidrv_exp_config.h - - condition: - - brd4001a - override: - component: spidrv_eusart - file_id: spidrv_eusart_config - instance: exp - path: brd4109a_brd4001a/sl_spidrv_eusart_exp_config.h - - condition: - - brd4001a - override: - component: spidrv_usart - file_id: spidrv_usart_config - instance: exp - path: brd4109a_brd4001a/sl_spidrv_usart_exp_config.h - - condition: - - brd4001a - override: - component: uartdrv_eusart - file_id: uartdrv_eusart_config - instance: vcom - path: brd4109a_brd4001a/sl_uartdrv_eusart_vcom_config.h - - condition: - - brd4001a - override: - component: uartdrv_eusart - file_id: uartdrv_eusart_config - instance: exp - path: brd4109a_brd4001a/sl_uartdrv_eusart_exp_config.h - - condition: - - brd4001a - override: - component: uartdrv_usart - file_id: uartdrv_usart_config - instance: vcom - path: brd4109a_brd4001a/sl_uartdrv_usart_vcom_config.h - - condition: - - brd4001a - override: - component: uartdrv_usart - file_id: uartdrv_usart_config - instance: exp - path: brd4109a_brd4001a/sl_uartdrv_usart_exp_config.h - - condition: - - brd4002a - override: - component: bootloader_euart_driver - file_id: btl_euart_driver_cfg - path: brd4109a_brd4002a/btl_euart_driver_cfg.h - - condition: - - brd4002a - override: - component: bootloader_ezsp_gpio_activation - file_id: ezsp_gpio_activation_cfg - path: brd4109a_brd4002a/btl_ezsp_gpio_activation_cfg.h - - condition: - - brd4002a - override: - component: bootloader_gpio_activation - file_id: btl_gpio_activation_cfg - path: brd4109a_brd4002a/btl_gpio_activation_cfg.h - - condition: - - brd4002a - override: - component: bootloader_spi_controller_eusart_driver - file_id: btl_spi_controller_eusart_driver_cfg - path: brd4109a_brd4002a/btl_spi_controller_eusart_driver_cfg.h - - condition: - - brd4002a - override: - component: bootloader_spi_controller_usart_driver - file_id: btl_spi_controller_usart_driver_cfg - path: brd4109a_brd4002a/btl_spi_controller_usart_driver_cfg.h - - condition: - - brd4002a - override: - component: bootloader_spi_peripheral_eusart_driver - file_id: btl_spi_peripheral_eusart_driver_cfg - path: brd4109a_brd4002a/btl_spi_peripheral_eusart_driver_cfg.h - - condition: - - brd4002a - override: - component: bootloader_spi_peripheral_usart_driver - file_id: btl_spi_peripheral_usart_driver_cfg - path: brd4109a_brd4002a/btl_spi_peripheral_usart_driver_cfg.h - - condition: - - brd4002a - override: - component: bootloader_uart_driver - file_id: btl_uart_driver_cfg - path: brd4109a_brd4002a/btl_uart_driver_cfg.h - - condition: - - brd4002a - override: - component: cpc_primary_driver_spi_usart - file_id: cpc_drv_spi_primary_config - instance: exp - path: brd4109a_brd4002a/sl_cpc_drv_primary_spi_usart_exp_config.h - - condition: - - brd4002a - override: - component: cpc_primary_driver_uart_usart - file_id: cpc_drv_uart_primary_config - instance: vcom - path: brd4109a_brd4002a/sl_cpc_drv_primary_uart_usart_vcom_config.h - - condition: - - brd4002a - override: - component: cpc_primary_driver_uart_usart - file_id: cpc_drv_uart_primary_config - instance: exp - path: brd4109a_brd4002a/sl_cpc_drv_primary_uart_usart_exp_config.h - - condition: - - brd4002a - override: - component: cpc_secondary_driver_spi_eusart - file_id: cpc_drv_secondary_spi_eusart_config - instance: exp - path: brd4109a_brd4002a/sl_cpc_drv_secondary_spi_eusart_exp_config.h - - condition: - - brd4002a - override: - component: cpc_secondary_driver_spi_usart - file_id: cpc_drv_secondary_spi_usart_config - instance: exp - path: brd4109a_brd4002a/sl_cpc_drv_secondary_spi_usart_exp_config.h - - condition: - - brd4002a - override: - component: cpc_secondary_driver_uart_eusart - file_id: cpc_drv_secondary_uart_eusart_config - instance: vcom - path: brd4109a_brd4002a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h - - condition: - - brd4002a - override: - component: cpc_secondary_driver_uart_eusart - file_id: cpc_drv_secondary_uart_eusart_config - instance: exp - path: brd4109a_brd4002a/sl_cpc_drv_secondary_uart_eusart_exp_config.h - - condition: - - brd4002a - override: - component: cpc_secondary_driver_uart_usart - file_id: cpc_drv_secondary_uart_usart_config - instance: vcom - path: brd4109a_brd4002a/sl_cpc_drv_secondary_uart_usart_vcom_config.h - - condition: - - brd4002a - override: - component: cpc_secondary_driver_uart_usart - file_id: cpc_drv_secondary_uart_usart_config - instance: exp - path: brd4109a_brd4002a/sl_cpc_drv_secondary_uart_usart_exp_config.h - - condition: - - brd4002a - override: - component: device_init_hfxo - file_id: device_init_hfxo_config - path: brd4109a_brd4002a/sl_device_init_hfxo_config.h - - condition: - - brd4002a - override: - component: device_init_lfxo - file_id: device_init_lfxo_config - path: brd4109a_brd4002a/sl_device_init_lfxo_config.h - - condition: - - brd4002a - override: - component: i2cspm - file_id: i2cspm_config - instance: sensor - path: brd4109a_brd4002a/sl_i2cspm_sensor_config.h - - condition: - - brd4002a - override: - component: iostream_eusart - file_id: iostream_eusart_config - instance: vcom - path: brd4109a_brd4002a/sl_iostream_eusart_vcom_config.h - - condition: - - brd4002a - override: - component: iostream_eusart - file_id: iostream_eusart_config - instance: exp - path: brd4109a_brd4002a/sl_iostream_eusart_exp_config.h - - condition: - - brd4002a - override: - component: iostream_usart - file_id: iostream_usart_config - instance: vcom - path: brd4109a_brd4002a/sl_iostream_usart_vcom_config.h - - condition: - - brd4002a - override: - component: iostream_usart - file_id: iostream_usart_config - instance: exp - path: brd4109a_brd4002a/sl_iostream_usart_exp_config.h - - condition: - - brd4002a - override: - component: iot_flash - file_id: iot_flash_cfg - instance: msc - path: brd4109a_brd4002a/iot_flash_cfg_msc.h - - condition: - - brd4002a - override: - component: iot_flash - file_id: iot_flash_cfg - instance: exp - path: brd4109a_brd4002a/iot_flash_cfg_exp.h - - condition: - - brd4002a - override: - component: iot_flash - file_id: iot_flash_cfg - instance: spiflash - path: brd4109a_brd4002a/iot_flash_cfg_spiflash.h - - condition: - - brd4002a - override: - component: iot_i2c - file_id: iot_i2c_cfg - instance: sensor - path: brd4109a_brd4002a/iot_i2c_cfg_sensor.h - - condition: - - brd4002a - override: - component: iot_i2c - file_id: iot_i2c_cfg - instance: exp - path: brd4109a_brd4002a/iot_i2c_cfg_exp.h - - condition: - - brd4002a - override: - component: iot_i2c - file_id: iot_i2c_cfg - instance: test - path: brd4109a_brd4002a/iot_i2c_cfg_test.h - - condition: - - brd4002a - override: - component: iot_pwm - file_id: iot_pwm_cfg - instance: led0 - path: brd4109a_brd4002a/iot_pwm_cfg_led0.h - - condition: - - brd4002a - override: - component: iot_pwm - file_id: iot_pwm_cfg - instance: led1 - path: brd4109a_brd4002a/iot_pwm_cfg_led1.h - - condition: - - brd4002a - override: - component: iot_pwm - file_id: iot_pwm_cfg - instance: exp - path: brd4109a_brd4002a/iot_pwm_cfg_exp.h - - condition: - - brd4002a - override: - component: iot_spi - file_id: iot_spi_cfg - instance: exp - path: brd4109a_brd4002a/iot_spi_cfg_exp.h - - condition: - - brd4002a - override: - component: iot_spi - file_id: iot_spi_cfg - instance: loopback - path: brd4109a_brd4002a/iot_spi_cfg_loopback.h - - condition: - - brd4002a - override: - component: iot_uart - file_id: iot_uart_cfg - instance: vcom - path: brd4109a_brd4002a/iot_uart_cfg_vcom.h - - condition: - - brd4002a - override: - component: iot_uart - file_id: iot_uart_cfg - instance: exp - path: brd4109a_brd4002a/iot_uart_cfg_exp.h - - condition: - - brd4002a - override: - component: iot_uart - file_id: iot_uart_cfg - instance: loopback - path: brd4109a_brd4002a/iot_uart_cfg_loopback.h - - condition: - - brd4002a - override: - component: joystick - file_id: joystick_config - path: brd4109a_brd4002a/sl_joystick_config.h - - condition: - - brd4002a - override: - component: legacy_ncp_spi - file_id: legacy_ncp_spi_config - path: brd4109a_brd4002a/legacy_ncp_spi_config.h - - condition: - - brd4002a - override: - component: memlcd_eusart - file_id: sl_memlcd_eusart_config - path: brd4109a_brd4002a/sl_memlcd_eusart_config.h - - condition: - - brd4002a - override: - component: memlcd_usart - file_id: sl_memlcd_usart_config - path: brd4109a_brd4002a/sl_memlcd_usart_config.h - - condition: - - brd4002a - override: - component: mx25_flash_shutdown_eusart - file_id: mx25_flash_shutdown_eusart_config - path: brd4109a_brd4002a/sl_mx25_flash_shutdown_eusart_config.h - - condition: - - brd4002a - override: - component: mx25_flash_shutdown_usart - file_id: mx25_flash_shutdown_usart_config - path: brd4109a_brd4002a/sl_mx25_flash_shutdown_usart_config.h - - condition: - - brd4002a - override: - component: ot_ncp_spidrv - file_id: sl_ncp_spidrv_usart_config - path: brd4109a_brd4002a/sl_ncp_spidrv_usart_config.h - - condition: - - brd4002a - override: - component: pwm - file_id: pwm_config - instance: led0 - path: brd4109a_brd4002a/sl_pwm_init_led0_config.h - - condition: - - brd4002a - override: - component: pwm - file_id: pwm_config - instance: led1 - path: brd4109a_brd4002a/sl_pwm_init_led1_config.h - - condition: - - brd4002a - override: - component: rail_util_pa - file_id: rail_util_pa_config - path: brd4109a_brd4002a/sl_rail_util_pa_config.h - - condition: - - brd4002a - override: - component: rail_util_pti - file_id: rail_util_pti_config - path: brd4109a_brd4002a/sl_rail_util_pti_config.h - - condition: - - brd4002a - override: - component: simple_button - file_id: simple_button_config - instance: btn0 - path: brd4109a_brd4002a/sl_simple_button_btn0_config.h - - condition: - - brd4002a - override: - component: simple_button - file_id: simple_button_config - instance: btn1 - path: brd4109a_brd4002a/sl_simple_button_btn1_config.h - - condition: - - brd4002a - override: - component: simple_led - file_id: simple_led_config - instance: led0 - path: brd4109a_brd4002a/sl_simple_led_led0_config.h - - condition: - - brd4002a - override: - component: simple_led - file_id: simple_led_config - instance: led1 - path: brd4109a_brd4002a/sl_simple_led_led1_config.h - - condition: - - brd4002a - override: - component: spidrv - file_id: spidrv_config - instance: exp - path: brd4109a_brd4002a/sl_spidrv_exp_config.h - - condition: - - brd4002a - override: - component: spidrv_eusart - file_id: spidrv_eusart_config - instance: exp - path: brd4109a_brd4002a/sl_spidrv_eusart_exp_config.h - - condition: - - brd4002a - override: - component: spidrv_usart - file_id: spidrv_usart_config - instance: exp - path: brd4109a_brd4002a/sl_spidrv_usart_exp_config.h - - condition: - - brd4002a - override: - component: uartdrv_eusart - file_id: uartdrv_eusart_config - instance: vcom - path: brd4109a_brd4002a/sl_uartdrv_eusart_vcom_config.h - - condition: - - brd4002a - override: - component: uartdrv_eusart - file_id: uartdrv_eusart_config - instance: exp - path: brd4109a_brd4002a/sl_uartdrv_eusart_exp_config.h - - condition: - - brd4002a - override: - component: uartdrv_usart - file_id: uartdrv_usart_config - instance: vcom - path: brd4109a_brd4002a/sl_uartdrv_usart_vcom_config.h - - condition: - - brd4002a - override: - component: uartdrv_usart - file_id: uartdrv_usart_config - instance: exp - path: brd4109a_brd4002a/sl_uartdrv_usart_exp_config.h diff --git a/hardware/board/config/component/brd4111a_config.slcc b/hardware/board/config/component/brd4111a_config.slcc deleted file mode 100644 index d2322a190a..0000000000 --- a/hardware/board/config/component/brd4111a_config.slcc +++ /dev/null @@ -1,479 +0,0 @@ -!!omap -- id: brd4111a_config -- label: brd4111a config -- description: Configuration files for BRD4111A -- package: platform -- category: Platform|Board|Config -- quality: production -- ui_hints: - visibility: never -- root_path: hardware/board/config -- requires: - - name: brd4111a -- provides: - - name: brd4111a_config -- config_file: - - condition: - - brd4001a - override: - component: board_control - file_id: board_control_config - path: brd4111a_brd4001a/sl_board_control_config.h - - condition: - - brd4002a - override: - component: board_control - file_id: board_control_config - path: brd4111a_brd4002a/sl_board_control_config.h - - condition: - - brd4001a - override: - component: bootloader_euart_driver - file_id: btl_euart_driver_cfg - path: brd4111a_brd4001a/btl_euart_driver_cfg.h - - condition: - - brd4001a - override: - component: bootloader_ezsp_gpio_activation - file_id: ezsp_gpio_activation_cfg - path: brd4111a_brd4001a/btl_ezsp_gpio_activation_cfg.h - - condition: - - brd4001a - override: - component: bootloader_gpio_activation - file_id: btl_gpio_activation_cfg - path: brd4111a_brd4001a/btl_gpio_activation_cfg.h - - condition: - - brd4001a - override: - component: bootloader_spi_controller_eusart_driver - file_id: btl_spi_controller_eusart_driver_cfg - path: brd4111a_brd4001a/btl_spi_controller_eusart_driver_cfg.h - - condition: - - brd4001a - override: - component: bootloader_spi_controller_usart_driver - file_id: btl_spi_controller_usart_driver_cfg - path: brd4111a_brd4001a/btl_spi_controller_usart_driver_cfg.h - - condition: - - brd4001a - override: - component: bootloader_uart_driver - file_id: btl_uart_driver_cfg - path: brd4111a_brd4001a/btl_uart_driver_cfg.h - - condition: - - brd4001a - override: - component: cpc_primary_driver_uart_usart - file_id: cpc_drv_uart_primary_config - instance: vcom - path: brd4111a_brd4001a/sl_cpc_drv_primary_uart_usart_vcom_config.h - - condition: - - brd4001a - override: - component: cpc_primary_driver_uart_usart - file_id: cpc_drv_uart_primary_config - instance: exp - path: brd4111a_brd4001a/sl_cpc_drv_primary_uart_usart_exp_config.h - - condition: - - brd4001a - override: - component: cpc_secondary_driver_uart_eusart - file_id: cpc_drv_secondary_uart_eusart_config - instance: vcom - path: brd4111a_brd4001a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h - - condition: - - brd4001a - override: - component: cpc_secondary_driver_uart_eusart - file_id: cpc_drv_secondary_uart_eusart_config - instance: exp - path: brd4111a_brd4001a/sl_cpc_drv_secondary_uart_eusart_exp_config.h - - condition: - - brd4001a - override: - component: cpc_secondary_driver_uart_usart - file_id: cpc_drv_secondary_uart_usart_config - instance: vcom - path: brd4111a_brd4001a/sl_cpc_drv_secondary_uart_usart_vcom_config.h - - condition: - - brd4001a - override: - component: cpc_secondary_driver_uart_usart - file_id: cpc_drv_secondary_uart_usart_config - instance: exp - path: brd4111a_brd4001a/sl_cpc_drv_secondary_uart_usart_exp_config.h - - condition: - - brd4001a - override: - component: device_init_hfxo - file_id: device_init_hfxo_config - path: brd4111a_brd4001a/sl_device_init_hfxo_config.h - - condition: - - brd4001a - override: - component: device_init_lfxo - file_id: device_init_lfxo_config - path: brd4111a_brd4001a/sl_device_init_lfxo_config.h - - condition: - - brd4001a - override: - component: iostream_eusart - file_id: iostream_eusart_config - instance: vcom - path: brd4111a_brd4001a/sl_iostream_eusart_vcom_config.h - - condition: - - brd4001a - override: - component: iostream_eusart - file_id: iostream_eusart_config - instance: exp - path: brd4111a_brd4001a/sl_iostream_eusart_exp_config.h - - condition: - - brd4001a - override: - component: iostream_usart - file_id: iostream_usart_config - instance: vcom - path: brd4111a_brd4001a/sl_iostream_usart_vcom_config.h - - condition: - - brd4001a - override: - component: iostream_usart - file_id: iostream_usart_config - instance: exp - path: brd4111a_brd4001a/sl_iostream_usart_exp_config.h - - condition: - - brd4001a - override: - component: iot_flash - file_id: iot_flash_cfg - instance: msc - path: brd4111a_brd4001a/iot_flash_cfg_msc.h - - condition: - - brd4001a - override: - component: iot_flash - file_id: iot_flash_cfg - instance: spiflash - path: brd4111a_brd4001a/iot_flash_cfg_spiflash.h - - condition: - - brd4001a - override: - component: iot_pwm - file_id: iot_pwm_cfg - instance: exp - path: brd4111a_brd4001a/iot_pwm_cfg_exp.h - - condition: - - brd4001a - override: - component: iot_uart - file_id: iot_uart_cfg - instance: vcom - path: brd4111a_brd4001a/iot_uart_cfg_vcom.h - - condition: - - brd4001a - override: - component: iot_uart - file_id: iot_uart_cfg - instance: exp - path: brd4111a_brd4001a/iot_uart_cfg_exp.h - - condition: - - brd4001a - override: - component: iot_uart - file_id: iot_uart_cfg - instance: loopback - path: brd4111a_brd4001a/iot_uart_cfg_loopback.h - - condition: - - brd4001a - override: - component: mx25_flash_shutdown_eusart - file_id: mx25_flash_shutdown_eusart_config - path: brd4111a_brd4001a/sl_mx25_flash_shutdown_eusart_config.h - - condition: - - brd4001a - override: - component: mx25_flash_shutdown_usart - file_id: mx25_flash_shutdown_usart_config - path: brd4111a_brd4001a/sl_mx25_flash_shutdown_usart_config.h - - condition: - - brd4001a - override: - component: rail_util_pa - file_id: rail_util_pa_config - path: brd4111a_brd4001a/sl_rail_util_pa_config.h - - condition: - - brd4001a - override: - component: rail_util_pti - file_id: rail_util_pti_config - path: brd4111a_brd4001a/sl_rail_util_pti_config.h - - condition: - - brd4001a - override: - component: simple_button - file_id: simple_button_config - instance: btn0 - path: brd4111a_brd4001a/sl_simple_button_btn0_config.h - - condition: - - brd4001a - override: - component: simple_button - file_id: simple_button_config - instance: btn1 - path: brd4111a_brd4001a/sl_simple_button_btn1_config.h - - condition: - - brd4001a - override: - component: uartdrv_eusart - file_id: uartdrv_eusart_config - instance: vcom - path: brd4111a_brd4001a/sl_uartdrv_eusart_vcom_config.h - - condition: - - brd4001a - override: - component: uartdrv_eusart - file_id: uartdrv_eusart_config - instance: exp - path: brd4111a_brd4001a/sl_uartdrv_eusart_exp_config.h - - condition: - - brd4001a - override: - component: uartdrv_usart - file_id: uartdrv_usart_config - instance: vcom - path: brd4111a_brd4001a/sl_uartdrv_usart_vcom_config.h - - condition: - - brd4001a - override: - component: uartdrv_usart - file_id: uartdrv_usart_config - instance: exp - path: brd4111a_brd4001a/sl_uartdrv_usart_exp_config.h - - condition: - - brd4002a - override: - component: bootloader_euart_driver - file_id: btl_euart_driver_cfg - path: brd4111a_brd4002a/btl_euart_driver_cfg.h - - condition: - - brd4002a - override: - component: bootloader_ezsp_gpio_activation - file_id: ezsp_gpio_activation_cfg - path: brd4111a_brd4002a/btl_ezsp_gpio_activation_cfg.h - - condition: - - brd4002a - override: - component: bootloader_gpio_activation - file_id: btl_gpio_activation_cfg - path: brd4111a_brd4002a/btl_gpio_activation_cfg.h - - condition: - - brd4002a - override: - component: bootloader_spi_controller_eusart_driver - file_id: btl_spi_controller_eusart_driver_cfg - path: brd4111a_brd4002a/btl_spi_controller_eusart_driver_cfg.h - - condition: - - brd4002a - override: - component: bootloader_spi_controller_usart_driver - file_id: btl_spi_controller_usart_driver_cfg - path: brd4111a_brd4002a/btl_spi_controller_usart_driver_cfg.h - - condition: - - brd4002a - override: - component: bootloader_uart_driver - file_id: btl_uart_driver_cfg - path: brd4111a_brd4002a/btl_uart_driver_cfg.h - - condition: - - brd4002a - override: - component: cpc_primary_driver_uart_usart - file_id: cpc_drv_uart_primary_config - instance: vcom - path: brd4111a_brd4002a/sl_cpc_drv_primary_uart_usart_vcom_config.h - - condition: - - brd4002a - override: - component: cpc_primary_driver_uart_usart - file_id: cpc_drv_uart_primary_config - instance: exp - path: brd4111a_brd4002a/sl_cpc_drv_primary_uart_usart_exp_config.h - - condition: - - brd4002a - override: - component: cpc_secondary_driver_uart_eusart - file_id: cpc_drv_secondary_uart_eusart_config - instance: vcom - path: brd4111a_brd4002a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h - - condition: - - brd4002a - override: - component: cpc_secondary_driver_uart_eusart - file_id: cpc_drv_secondary_uart_eusart_config - instance: exp - path: brd4111a_brd4002a/sl_cpc_drv_secondary_uart_eusart_exp_config.h - - condition: - - brd4002a - override: - component: cpc_secondary_driver_uart_usart - file_id: cpc_drv_secondary_uart_usart_config - instance: vcom - path: brd4111a_brd4002a/sl_cpc_drv_secondary_uart_usart_vcom_config.h - - condition: - - brd4002a - override: - component: cpc_secondary_driver_uart_usart - file_id: cpc_drv_secondary_uart_usart_config - instance: exp - path: brd4111a_brd4002a/sl_cpc_drv_secondary_uart_usart_exp_config.h - - condition: - - brd4002a - override: - component: device_init_hfxo - file_id: device_init_hfxo_config - path: brd4111a_brd4002a/sl_device_init_hfxo_config.h - - condition: - - brd4002a - override: - component: device_init_lfxo - file_id: device_init_lfxo_config - path: brd4111a_brd4002a/sl_device_init_lfxo_config.h - - condition: - - brd4002a - override: - component: iostream_eusart - file_id: iostream_eusart_config - instance: vcom - path: brd4111a_brd4002a/sl_iostream_eusart_vcom_config.h - - condition: - - brd4002a - override: - component: iostream_eusart - file_id: iostream_eusart_config - instance: exp - path: brd4111a_brd4002a/sl_iostream_eusart_exp_config.h - - condition: - - brd4002a - override: - component: iostream_usart - file_id: iostream_usart_config - instance: vcom - path: brd4111a_brd4002a/sl_iostream_usart_vcom_config.h - - condition: - - brd4002a - override: - component: iostream_usart - file_id: iostream_usart_config - instance: exp - path: brd4111a_brd4002a/sl_iostream_usart_exp_config.h - - condition: - - brd4002a - override: - component: iot_flash - file_id: iot_flash_cfg - instance: msc - path: brd4111a_brd4002a/iot_flash_cfg_msc.h - - condition: - - brd4002a - override: - component: iot_flash - file_id: iot_flash_cfg - instance: spiflash - path: brd4111a_brd4002a/iot_flash_cfg_spiflash.h - - condition: - - brd4002a - override: - component: iot_pwm - file_id: iot_pwm_cfg - instance: exp - path: brd4111a_brd4002a/iot_pwm_cfg_exp.h - - condition: - - brd4002a - override: - component: iot_uart - file_id: iot_uart_cfg - instance: vcom - path: brd4111a_brd4002a/iot_uart_cfg_vcom.h - - condition: - - brd4002a - override: - component: iot_uart - file_id: iot_uart_cfg - instance: exp - path: brd4111a_brd4002a/iot_uart_cfg_exp.h - - condition: - - brd4002a - override: - component: iot_uart - file_id: iot_uart_cfg - instance: loopback - path: brd4111a_brd4002a/iot_uart_cfg_loopback.h - - condition: - - brd4002a - override: - component: mx25_flash_shutdown_eusart - file_id: mx25_flash_shutdown_eusart_config - path: brd4111a_brd4002a/sl_mx25_flash_shutdown_eusart_config.h - - condition: - - brd4002a - override: - component: mx25_flash_shutdown_usart - file_id: mx25_flash_shutdown_usart_config - path: brd4111a_brd4002a/sl_mx25_flash_shutdown_usart_config.h - - condition: - - brd4002a - override: - component: rail_util_pa - file_id: rail_util_pa_config - path: brd4111a_brd4002a/sl_rail_util_pa_config.h - - condition: - - brd4002a - override: - component: rail_util_pti - file_id: rail_util_pti_config - path: brd4111a_brd4002a/sl_rail_util_pti_config.h - - condition: - - brd4002a - override: - component: simple_button - file_id: simple_button_config - instance: btn0 - path: brd4111a_brd4002a/sl_simple_button_btn0_config.h - - condition: - - brd4002a - override: - component: simple_button - file_id: simple_button_config - instance: btn1 - path: brd4111a_brd4002a/sl_simple_button_btn1_config.h - - condition: - - brd4002a - override: - component: uartdrv_eusart - file_id: uartdrv_eusart_config - instance: vcom - path: brd4111a_brd4002a/sl_uartdrv_eusart_vcom_config.h - - condition: - - brd4002a - override: - component: uartdrv_eusart - file_id: uartdrv_eusart_config - instance: exp - path: brd4111a_brd4002a/sl_uartdrv_eusart_exp_config.h - - condition: - - brd4002a - override: - component: uartdrv_usart - file_id: uartdrv_usart_config - instance: vcom - path: brd4111a_brd4002a/sl_uartdrv_usart_vcom_config.h - - condition: - - brd4002a - override: - component: uartdrv_usart - file_id: uartdrv_usart_config - instance: exp - path: brd4111a_brd4002a/sl_uartdrv_usart_exp_config.h diff --git a/hardware/board/config/component/brd4113a_config.slcc b/hardware/board/config/component/brd4113a_config.slcc deleted file mode 100644 index 7945e73712..0000000000 --- a/hardware/board/config/component/brd4113a_config.slcc +++ /dev/null @@ -1,569 +0,0 @@ -!!omap -- id: brd4113a_config -- label: brd4113a config -- description: Configuration files for BRD4113A -- package: platform -- category: Platform|Board|Config -- quality: production -- ui_hints: - visibility: never -- root_path: hardware/board/config -- requires: - - name: brd4113a -- provides: - - name: brd4113a_config -- config_file: - - condition: - - brd4001a - override: - component: board_control - file_id: board_control_config - path: brd4113a_brd4001a/sl_board_control_config.h - - condition: - - brd4002a - override: - component: board_control - file_id: board_control_config - path: brd4113a_brd4002a/sl_board_control_config.h - - condition: - - brd4001a - override: - component: bootloader_euart_driver - file_id: btl_euart_driver_cfg - path: brd4113a_brd4001a/btl_euart_driver_cfg.h - - condition: - - brd4001a - override: - component: bootloader_ezsp_gpio_activation - file_id: ezsp_gpio_activation_cfg - path: brd4113a_brd4001a/btl_ezsp_gpio_activation_cfg.h - - condition: - - brd4001a - override: - component: bootloader_gpio_activation - file_id: btl_gpio_activation_cfg - path: brd4113a_brd4001a/btl_gpio_activation_cfg.h - - condition: - - brd4001a - override: - component: bootloader_spi_controller_eusart_driver - file_id: btl_spi_controller_eusart_driver_cfg - path: brd4113a_brd4001a/btl_spi_controller_eusart_driver_cfg.h - - condition: - - brd4001a - override: - component: bootloader_spi_controller_usart_driver - file_id: btl_spi_controller_usart_driver_cfg - path: brd4113a_brd4001a/btl_spi_controller_usart_driver_cfg.h - - condition: - - brd4001a - override: - component: bootloader_uart_driver - file_id: btl_uart_driver_cfg - path: brd4113a_brd4001a/btl_uart_driver_cfg.h - - condition: - - brd4001a - override: - component: cpc_primary_driver_uart_usart - file_id: cpc_drv_uart_primary_config - instance: vcom - path: brd4113a_brd4001a/sl_cpc_drv_primary_uart_usart_vcom_config.h - - condition: - - brd4001a - override: - component: cpc_primary_driver_uart_usart - file_id: cpc_drv_uart_primary_config - instance: exp - path: brd4113a_brd4001a/sl_cpc_drv_primary_uart_usart_exp_config.h - - condition: - - brd4001a - override: - component: cpc_secondary_driver_uart_eusart - file_id: cpc_drv_secondary_uart_eusart_config - instance: vcom - path: brd4113a_brd4001a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h - - condition: - - brd4001a - override: - component: cpc_secondary_driver_uart_eusart - file_id: cpc_drv_secondary_uart_eusart_config - instance: exp - path: brd4113a_brd4001a/sl_cpc_drv_secondary_uart_eusart_exp_config.h - - condition: - - brd4001a - override: - component: cpc_secondary_driver_uart_usart - file_id: cpc_drv_secondary_uart_usart_config - instance: vcom - path: brd4113a_brd4001a/sl_cpc_drv_secondary_uart_usart_vcom_config.h - - condition: - - brd4001a - override: - component: cpc_secondary_driver_uart_usart - file_id: cpc_drv_secondary_uart_usart_config - instance: exp - path: brd4113a_brd4001a/sl_cpc_drv_secondary_uart_usart_exp_config.h - - condition: - - brd4001a - override: - component: device_init_hfxo - file_id: device_init_hfxo_config - path: brd4113a_brd4001a/sl_device_init_hfxo_config.h - - condition: - - brd4001a - override: - component: device_init_lfxo - file_id: device_init_lfxo_config - path: brd4113a_brd4001a/sl_device_init_lfxo_config.h - - condition: - - brd4001a - override: - component: iostream_eusart - file_id: iostream_eusart_config - instance: vcom - path: brd4113a_brd4001a/sl_iostream_eusart_vcom_config.h - - condition: - - brd4001a - override: - component: iostream_eusart - file_id: iostream_eusart_config - instance: exp - path: brd4113a_brd4001a/sl_iostream_eusart_exp_config.h - - condition: - - brd4001a - override: - component: iostream_usart - file_id: iostream_usart_config - instance: vcom - path: brd4113a_brd4001a/sl_iostream_usart_vcom_config.h - - condition: - - brd4001a - override: - component: iostream_usart - file_id: iostream_usart_config - instance: exp - path: brd4113a_brd4001a/sl_iostream_usart_exp_config.h - - condition: - - brd4001a - override: - component: iot_flash - file_id: iot_flash_cfg - instance: msc - path: brd4113a_brd4001a/iot_flash_cfg_msc.h - - condition: - - brd4001a - override: - component: iot_flash - file_id: iot_flash_cfg - instance: spiflash - path: brd4113a_brd4001a/iot_flash_cfg_spiflash.h - - condition: - - brd4001a - override: - component: iot_pwm - file_id: iot_pwm_cfg - instance: led0 - path: brd4113a_brd4001a/iot_pwm_cfg_led0.h - - condition: - - brd4001a - override: - component: iot_pwm - file_id: iot_pwm_cfg - instance: led1 - path: brd4113a_brd4001a/iot_pwm_cfg_led1.h - - condition: - - brd4001a - override: - component: iot_pwm - file_id: iot_pwm_cfg - instance: exp - path: brd4113a_brd4001a/iot_pwm_cfg_exp.h - - condition: - - brd4001a - override: - component: iot_uart - file_id: iot_uart_cfg - instance: vcom - path: brd4113a_brd4001a/iot_uart_cfg_vcom.h - - condition: - - brd4001a - override: - component: iot_uart - file_id: iot_uart_cfg - instance: exp - path: brd4113a_brd4001a/iot_uart_cfg_exp.h - - condition: - - brd4001a - override: - component: iot_uart - file_id: iot_uart_cfg - instance: loopback - path: brd4113a_brd4001a/iot_uart_cfg_loopback.h - - condition: - - brd4001a - override: - component: mx25_flash_shutdown_eusart - file_id: mx25_flash_shutdown_eusart_config - path: brd4113a_brd4001a/sl_mx25_flash_shutdown_eusart_config.h - - condition: - - brd4001a - override: - component: mx25_flash_shutdown_usart - file_id: mx25_flash_shutdown_usart_config - path: brd4113a_brd4001a/sl_mx25_flash_shutdown_usart_config.h - - condition: - - brd4001a - override: - component: pwm - file_id: pwm_config - instance: led0 - path: brd4113a_brd4001a/sl_pwm_init_led0_config.h - - condition: - - brd4001a - override: - component: pwm - file_id: pwm_config - instance: led1 - path: brd4113a_brd4001a/sl_pwm_init_led1_config.h - - condition: - - brd4001a - override: - component: rail_util_pa - file_id: rail_util_pa_config - path: brd4113a_brd4001a/sl_rail_util_pa_config.h - - condition: - - brd4001a - override: - component: rail_util_pti - file_id: rail_util_pti_config - path: brd4113a_brd4001a/sl_rail_util_pti_config.h - - condition: - - brd4001a - override: - component: simple_button - file_id: simple_button_config - instance: btn0 - path: brd4113a_brd4001a/sl_simple_button_btn0_config.h - - condition: - - brd4001a - override: - component: simple_button - file_id: simple_button_config - instance: btn1 - path: brd4113a_brd4001a/sl_simple_button_btn1_config.h - - condition: - - brd4001a - override: - component: simple_led - file_id: simple_led_config - instance: led0 - path: brd4113a_brd4001a/sl_simple_led_led0_config.h - - condition: - - brd4001a - override: - component: simple_led - file_id: simple_led_config - instance: led1 - path: brd4113a_brd4001a/sl_simple_led_led1_config.h - - condition: - - brd4001a - override: - component: uartdrv_eusart - file_id: uartdrv_eusart_config - instance: vcom - path: brd4113a_brd4001a/sl_uartdrv_eusart_vcom_config.h - - condition: - - brd4001a - override: - component: uartdrv_eusart - file_id: uartdrv_eusart_config - instance: exp - path: brd4113a_brd4001a/sl_uartdrv_eusart_exp_config.h - - condition: - - brd4001a - override: - component: uartdrv_usart - file_id: uartdrv_usart_config - instance: vcom - path: brd4113a_brd4001a/sl_uartdrv_usart_vcom_config.h - - condition: - - brd4001a - override: - component: uartdrv_usart - file_id: uartdrv_usart_config - instance: exp - path: brd4113a_brd4001a/sl_uartdrv_usart_exp_config.h - - condition: - - brd4002a - override: - component: bootloader_euart_driver - file_id: btl_euart_driver_cfg - path: brd4113a_brd4002a/btl_euart_driver_cfg.h - - condition: - - brd4002a - override: - component: bootloader_ezsp_gpio_activation - file_id: ezsp_gpio_activation_cfg - path: brd4113a_brd4002a/btl_ezsp_gpio_activation_cfg.h - - condition: - - brd4002a - override: - component: bootloader_gpio_activation - file_id: btl_gpio_activation_cfg - path: brd4113a_brd4002a/btl_gpio_activation_cfg.h - - condition: - - brd4002a - override: - component: bootloader_spi_controller_eusart_driver - file_id: btl_spi_controller_eusart_driver_cfg - path: brd4113a_brd4002a/btl_spi_controller_eusart_driver_cfg.h - - condition: - - brd4002a - override: - component: bootloader_spi_controller_usart_driver - file_id: btl_spi_controller_usart_driver_cfg - path: brd4113a_brd4002a/btl_spi_controller_usart_driver_cfg.h - - condition: - - brd4002a - override: - component: bootloader_uart_driver - file_id: btl_uart_driver_cfg - path: brd4113a_brd4002a/btl_uart_driver_cfg.h - - condition: - - brd4002a - override: - component: cpc_primary_driver_uart_usart - file_id: cpc_drv_uart_primary_config - instance: vcom - path: brd4113a_brd4002a/sl_cpc_drv_primary_uart_usart_vcom_config.h - - condition: - - brd4002a - override: - component: cpc_primary_driver_uart_usart - file_id: cpc_drv_uart_primary_config - instance: exp - path: brd4113a_brd4002a/sl_cpc_drv_primary_uart_usart_exp_config.h - - condition: - - brd4002a - override: - component: cpc_secondary_driver_uart_eusart - file_id: cpc_drv_secondary_uart_eusart_config - instance: vcom - path: brd4113a_brd4002a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h - - condition: - - brd4002a - override: - component: cpc_secondary_driver_uart_eusart - file_id: cpc_drv_secondary_uart_eusart_config - instance: exp - path: brd4113a_brd4002a/sl_cpc_drv_secondary_uart_eusart_exp_config.h - - condition: - - brd4002a - override: - component: cpc_secondary_driver_uart_usart - file_id: cpc_drv_secondary_uart_usart_config - instance: vcom - path: brd4113a_brd4002a/sl_cpc_drv_secondary_uart_usart_vcom_config.h - - condition: - - brd4002a - override: - component: cpc_secondary_driver_uart_usart - file_id: cpc_drv_secondary_uart_usart_config - instance: exp - path: brd4113a_brd4002a/sl_cpc_drv_secondary_uart_usart_exp_config.h - - condition: - - brd4002a - override: - component: device_init_hfxo - file_id: device_init_hfxo_config - path: brd4113a_brd4002a/sl_device_init_hfxo_config.h - - condition: - - brd4002a - override: - component: device_init_lfxo - file_id: device_init_lfxo_config - path: brd4113a_brd4002a/sl_device_init_lfxo_config.h - - condition: - - brd4002a - override: - component: iostream_eusart - file_id: iostream_eusart_config - instance: vcom - path: brd4113a_brd4002a/sl_iostream_eusart_vcom_config.h - - condition: - - brd4002a - override: - component: iostream_eusart - file_id: iostream_eusart_config - instance: exp - path: brd4113a_brd4002a/sl_iostream_eusart_exp_config.h - - condition: - - brd4002a - override: - component: iostream_usart - file_id: iostream_usart_config - instance: vcom - path: brd4113a_brd4002a/sl_iostream_usart_vcom_config.h - - condition: - - brd4002a - override: - component: iostream_usart - file_id: iostream_usart_config - instance: exp - path: brd4113a_brd4002a/sl_iostream_usart_exp_config.h - - condition: - - brd4002a - override: - component: iot_flash - file_id: iot_flash_cfg - instance: msc - path: brd4113a_brd4002a/iot_flash_cfg_msc.h - - condition: - - brd4002a - override: - component: iot_flash - file_id: iot_flash_cfg - instance: spiflash - path: brd4113a_brd4002a/iot_flash_cfg_spiflash.h - - condition: - - brd4002a - override: - component: iot_pwm - file_id: iot_pwm_cfg - instance: led0 - path: brd4113a_brd4002a/iot_pwm_cfg_led0.h - - condition: - - brd4002a - override: - component: iot_pwm - file_id: iot_pwm_cfg - instance: led1 - path: brd4113a_brd4002a/iot_pwm_cfg_led1.h - - condition: - - brd4002a - override: - component: iot_pwm - file_id: iot_pwm_cfg - instance: exp - path: brd4113a_brd4002a/iot_pwm_cfg_exp.h - - condition: - - brd4002a - override: - component: iot_uart - file_id: iot_uart_cfg - instance: vcom - path: brd4113a_brd4002a/iot_uart_cfg_vcom.h - - condition: - - brd4002a - override: - component: iot_uart - file_id: iot_uart_cfg - instance: exp - path: brd4113a_brd4002a/iot_uart_cfg_exp.h - - condition: - - brd4002a - override: - component: iot_uart - file_id: iot_uart_cfg - instance: loopback - path: brd4113a_brd4002a/iot_uart_cfg_loopback.h - - condition: - - brd4002a - override: - component: joystick - file_id: joystick_config - path: brd4113a_brd4002a/sl_joystick_config.h - - condition: - - brd4002a - override: - component: mx25_flash_shutdown_eusart - file_id: mx25_flash_shutdown_eusart_config - path: brd4113a_brd4002a/sl_mx25_flash_shutdown_eusart_config.h - - condition: - - brd4002a - override: - component: mx25_flash_shutdown_usart - file_id: mx25_flash_shutdown_usart_config - path: brd4113a_brd4002a/sl_mx25_flash_shutdown_usart_config.h - - condition: - - brd4002a - override: - component: pwm - file_id: pwm_config - instance: led0 - path: brd4113a_brd4002a/sl_pwm_init_led0_config.h - - condition: - - brd4002a - override: - component: pwm - file_id: pwm_config - instance: led1 - path: brd4113a_brd4002a/sl_pwm_init_led1_config.h - - condition: - - brd4002a - override: - component: rail_util_pa - file_id: rail_util_pa_config - path: brd4113a_brd4002a/sl_rail_util_pa_config.h - - condition: - - brd4002a - override: - component: rail_util_pti - file_id: rail_util_pti_config - path: brd4113a_brd4002a/sl_rail_util_pti_config.h - - condition: - - brd4002a - override: - component: simple_button - file_id: simple_button_config - instance: btn0 - path: brd4113a_brd4002a/sl_simple_button_btn0_config.h - - condition: - - brd4002a - override: - component: simple_button - file_id: simple_button_config - instance: btn1 - path: brd4113a_brd4002a/sl_simple_button_btn1_config.h - - condition: - - brd4002a - override: - component: simple_led - file_id: simple_led_config - instance: led0 - path: brd4113a_brd4002a/sl_simple_led_led0_config.h - - condition: - - brd4002a - override: - component: simple_led - file_id: simple_led_config - instance: led1 - path: brd4113a_brd4002a/sl_simple_led_led1_config.h - - condition: - - brd4002a - override: - component: uartdrv_eusart - file_id: uartdrv_eusart_config - instance: vcom - path: brd4113a_brd4002a/sl_uartdrv_eusart_vcom_config.h - - condition: - - brd4002a - override: - component: uartdrv_eusart - file_id: uartdrv_eusart_config - instance: exp - path: brd4113a_brd4002a/sl_uartdrv_eusart_exp_config.h - - condition: - - brd4002a - override: - component: uartdrv_usart - file_id: uartdrv_usart_config - instance: vcom - path: brd4113a_brd4002a/sl_uartdrv_usart_vcom_config.h - - condition: - - brd4002a - override: - component: uartdrv_usart - file_id: uartdrv_usart_config - instance: exp - path: brd4113a_brd4002a/sl_uartdrv_usart_exp_config.h diff --git a/hardware/board/config/component/brd4166a_config.slcc b/hardware/board/config/component/brd4166a_config.slcc index 1dd1293eef..a7552140bd 100644 --- a/hardware/board/config/component/brd4166a_config.slcc +++ b/hardware/board/config/component/brd4166a_config.slcc @@ -178,6 +178,11 @@ file_id: iot_pwm_cfg instance: led1 path: brd4166a/iot_pwm_cfg_led1.h + - override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: exp + path: brd4166a/iot_pwm_cfg_exp.h - override: component: iot_spi file_id: iot_spi_cfg @@ -260,8 +265,8 @@ - override: component: simple_rgb_pwm_led file_id: simple_rgb_pwm_led_config - instance: inst0 - path: brd4166a/sl_simple_rgb_pwm_led_inst0_config.h + instance: rgb_led0 + path: brd4166a/sl_simple_rgb_pwm_led_rgb_led0_config.h - override: component: spidrv file_id: spidrv_config diff --git a/hardware/board/config/component/brd4166c_config.slcc b/hardware/board/config/component/brd4166c_config.slcc new file mode 100644 index 0000000000..caeb34874e --- /dev/null +++ b/hardware/board/config/component/brd4166c_config.slcc @@ -0,0 +1,252 @@ +!!omap +- id: brd4166c_config +- label: brd4166c config +- description: Configuration files for BRD4166C +- package: platform +- category: Platform|Board|Config +- quality: production +- ui_hints: + visibility: never +- root_path: hardware/board/config +- requires: + - name: brd4166c +- provides: + - name: brd4166c_config +- config_file: + - override: + component: board_control + file_id: board_control_config + path: brd4166c/sl_board_control_config.h + - override: + component: bootloader_ezsp_gpio_activation + file_id: ezsp_gpio_activation_cfg + path: brd4166c/btl_ezsp_gpio_activation_cfg.h + - override: + component: bootloader_gpio_activation + file_id: btl_gpio_activation_cfg + path: brd4166c/btl_gpio_activation_cfg.h + - override: + component: bootloader_spi_controller_usart_driver + file_id: btl_spi_controller_usart_driver_cfg + path: brd4166c/btl_spi_controller_usart_driver_cfg.h + - override: + component: bootloader_spi_peripheral_usart_driver + file_id: btl_spi_peripheral_usart_driver_cfg + path: brd4166c/btl_spi_peripheral_usart_driver_cfg.h + - override: + component: bootloader_uart_driver + file_id: btl_uart_driver_cfg + path: brd4166c/btl_uart_driver_cfg.h + - override: + component: cpc_primary_driver_spi_usart + file_id: cpc_drv_spi_primary_config + instance: exp + path: brd4166c/sl_cpc_drv_primary_spi_usart_exp_config.h + - override: + component: cpc_primary_driver_uart_usart + file_id: cpc_drv_uart_primary_config + instance: vcom + path: brd4166c/sl_cpc_drv_primary_uart_usart_vcom_config.h + - override: + component: cpc_primary_driver_uart_usart + file_id: cpc_drv_uart_primary_config + instance: exp + path: brd4166c/sl_cpc_drv_primary_uart_usart_exp_config.h + - override: + component: cpc_secondary_driver_spi_usart + file_id: cpc_drv_secondary_spi_usart_config + instance: exp + path: brd4166c/sl_cpc_drv_secondary_spi_usart_exp_config.h + - override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_secondary_uart_usart_config + instance: vcom + path: brd4166c/sl_cpc_drv_secondary_uart_usart_vcom_config.h + - override: + component: cpc_secondary_driver_uart_usart + file_id: cpc_drv_secondary_uart_usart_config + instance: exp + path: brd4166c/sl_cpc_drv_secondary_uart_usart_exp_config.h + - override: + component: device_init_hfxo + file_id: device_init_hfxo_config + path: brd4166c/sl_device_init_hfxo_config.h + - override: + component: device_init_lfxo + file_id: device_init_lfxo_config + path: brd4166c/sl_device_init_lfxo_config.h + - override: + component: i2cspm + file_id: i2cspm_config + instance: sensor_env + path: brd4166c/sl_i2cspm_sensor_env_config.h + - override: + component: i2cspm + file_id: i2cspm_config + instance: sensor + path: brd4166c/sl_i2cspm_sensor_config.h + - override: + component: iostream_leuart + file_id: iostream_leuart_config + instance: vcom + path: brd4166c/sl_iostream_leuart_vcom_config.h + - override: + component: iostream_leuart + file_id: iostream_leuart_config + instance: exp + path: brd4166c/sl_iostream_leuart_exp_config.h + - override: + component: iostream_usart + file_id: iostream_usart_config + instance: vcom + path: brd4166c/sl_iostream_usart_vcom_config.h + - override: + component: iostream_usart + file_id: iostream_usart_config + instance: exp + path: brd4166c/sl_iostream_usart_exp_config.h + - override: + component: iot_flash + file_id: iot_flash_cfg + instance: msc + path: brd4166c/iot_flash_cfg_msc.h + - override: + component: iot_flash + file_id: iot_flash_cfg + instance: exp + path: brd4166c/iot_flash_cfg_exp.h + - override: + component: iot_flash + file_id: iot_flash_cfg + instance: spiflash + path: brd4166c/iot_flash_cfg_spiflash.h + - override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: sensor_env + path: brd4166c/iot_i2c_cfg_sensor_env.h + - override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: sensor + path: brd4166c/iot_i2c_cfg_sensor.h + - override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: exp + path: brd4166c/iot_i2c_cfg_exp.h + - override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: test + path: brd4166c/iot_i2c_cfg_test.h + - override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led0 + path: brd4166c/iot_pwm_cfg_led0.h + - override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: exp + path: brd4166c/iot_pwm_cfg_exp.h + - override: + component: iot_spi + file_id: iot_spi_cfg + instance: exp + path: brd4166c/iot_spi_cfg_exp.h + - override: + component: iot_spi + file_id: iot_spi_cfg + instance: loopback + path: brd4166c/iot_spi_cfg_loopback.h + - override: + component: iot_uart + file_id: iot_uart_cfg + instance: vcom + path: brd4166c/iot_uart_cfg_vcom.h + - override: + component: iot_uart + file_id: iot_uart_cfg + instance: exp + path: brd4166c/iot_uart_cfg_exp.h + - override: + component: iot_uart + file_id: iot_uart_cfg + instance: loopback + path: brd4166c/iot_uart_cfg_loopback.h + - override: + component: legacy_ncp_spi + file_id: legacy_ncp_spi_config + path: brd4166c/legacy_ncp_spi_config.h + - override: + component: mx25_flash_shutdown_usart + file_id: mx25_flash_shutdown_usart_config + path: brd4166c/sl_mx25_flash_shutdown_usart_config.h + - override: + component: ot_ncp_spidrv + file_id: sl_ncp_spidrv_usart_config + path: brd4166c/sl_ncp_spidrv_usart_config.h + - override: + component: pwm + file_id: pwm_config + instance: led0 + path: brd4166c/sl_pwm_init_led0_config.h + - override: + component: rail_util_pa + file_id: rail_util_pa_config + path: brd4166c/sl_rail_util_pa_config.h + - override: + component: rail_util_pti + file_id: rail_util_pti_config + path: brd4166c/sl_rail_util_pti_config.h + - override: + component: simple_button + file_id: simple_button_config + instance: btn0 + path: brd4166c/sl_simple_button_btn0_config.h + - override: + component: simple_button + file_id: simple_button_config + instance: btn1 + path: brd4166c/sl_simple_button_btn1_config.h + - override: + component: simple_led + file_id: simple_led_config + instance: led0 + path: brd4166c/sl_simple_led_led0_config.h + - override: + component: simple_led + file_id: simple_led_config + instance: led1 + path: brd4166c/sl_simple_led_led1_config.h + - override: + component: spidrv + file_id: spidrv_config + instance: exp + path: brd4166c/sl_spidrv_exp_config.h + - override: + component: spidrv_usart + file_id: spidrv_usart_config + instance: exp + path: brd4166c/sl_spidrv_usart_exp_config.h + - override: + component: uartdrv_leuart + file_id: uartdrv_leuart_config + instance: vcom + path: brd4166c/sl_uartdrv_leuart_vcom_config.h + - override: + component: uartdrv_leuart + file_id: uartdrv_leuart_config + instance: exp + path: brd4166c/sl_uartdrv_leuart_exp_config.h + - override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: vcom + path: brd4166c/sl_uartdrv_usart_vcom_config.h + - override: + component: uartdrv_usart + file_id: uartdrv_usart_config + instance: exp + path: brd4166c/sl_uartdrv_usart_exp_config.h diff --git a/hardware/board/config/component/brd4200a_config.slcc b/hardware/board/config/component/brd4200a_config.slcc index 31a75eab83..757890c669 100644 --- a/hardware/board/config/component/brd4200a_config.slcc +++ b/hardware/board/config/component/brd4200a_config.slcc @@ -323,8 +323,8 @@ override: component: simple_rgb_pwm_led file_id: simple_rgb_pwm_led_config - instance: inst0 - path: brd4200a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h + instance: rgb_led0 + path: brd4200a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h - condition: - brd4001a override: @@ -665,8 +665,8 @@ override: component: simple_rgb_pwm_led file_id: simple_rgb_pwm_led_config - instance: inst0 - path: brd4200a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h + instance: rgb_led0 + path: brd4200a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h - condition: - brd4002a override: diff --git a/hardware/board/config/component/brd4202a_config.slcc b/hardware/board/config/component/brd4202a_config.slcc index be9e90528a..ad25abba7e 100644 --- a/hardware/board/config/component/brd4202a_config.slcc +++ b/hardware/board/config/component/brd4202a_config.slcc @@ -323,8 +323,8 @@ override: component: simple_rgb_pwm_led file_id: simple_rgb_pwm_led_config - instance: inst0 - path: brd4202a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h + instance: rgb_led0 + path: brd4202a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h - condition: - brd4001a override: @@ -665,8 +665,8 @@ override: component: simple_rgb_pwm_led file_id: simple_rgb_pwm_led_config - instance: inst0 - path: brd4202a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h + instance: rgb_led0 + path: brd4202a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h - condition: - brd4002a override: diff --git a/hardware/board/config/component/brd4203a_config.slcc b/hardware/board/config/component/brd4203a_config.slcc index 047c0d1596..db7bd4518c 100644 --- a/hardware/board/config/component/brd4203a_config.slcc +++ b/hardware/board/config/component/brd4203a_config.slcc @@ -354,8 +354,8 @@ override: component: simple_rgb_pwm_led file_id: simple_rgb_pwm_led_config - instance: inst0 - path: brd4203a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h + instance: rgb_led0 + path: brd4203a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h - condition: - brd4001a override: @@ -727,8 +727,8 @@ override: component: simple_rgb_pwm_led file_id: simple_rgb_pwm_led_config - instance: inst0 - path: brd4203a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h + instance: rgb_led0 + path: brd4203a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h - condition: - brd4002a override: diff --git a/hardware/board/config/component/brd4205a_config.slcc b/hardware/board/config/component/brd4205a_config.slcc index b21194017e..edce953e4d 100644 --- a/hardware/board/config/component/brd4205a_config.slcc +++ b/hardware/board/config/component/brd4205a_config.slcc @@ -393,8 +393,8 @@ override: component: simple_rgb_pwm_led file_id: simple_rgb_pwm_led_config - instance: inst0 - path: brd4205a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h + instance: rgb_led0 + path: brd4205a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h - condition: - brd4001a override: @@ -812,8 +812,8 @@ override: component: simple_rgb_pwm_led file_id: simple_rgb_pwm_led_config - instance: inst0 - path: brd4205a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h + instance: rgb_led0 + path: brd4205a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h - condition: - brd4002a override: diff --git a/hardware/board/config/component/brd4205b_config.slcc b/hardware/board/config/component/brd4205b_config.slcc index 4bc4e2b343..adb154a50c 100644 --- a/hardware/board/config/component/brd4205b_config.slcc +++ b/hardware/board/config/component/brd4205b_config.slcc @@ -399,8 +399,8 @@ override: component: simple_rgb_pwm_led file_id: simple_rgb_pwm_led_config - instance: inst0 - path: brd4205b_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h + instance: rgb_led0 + path: brd4205b_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h - condition: - brd4001a override: @@ -824,8 +824,8 @@ override: component: simple_rgb_pwm_led file_id: simple_rgb_pwm_led_config - instance: inst0 - path: brd4205b_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h + instance: rgb_led0 + path: brd4205b_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h - condition: - brd4002a override: diff --git a/hardware/board/config/component/brd4207a_config.slcc b/hardware/board/config/component/brd4207a_config.slcc index 26b40dcc51..cbfbae4671 100644 --- a/hardware/board/config/component/brd4207a_config.slcc +++ b/hardware/board/config/component/brd4207a_config.slcc @@ -323,8 +323,8 @@ override: component: simple_rgb_pwm_led file_id: simple_rgb_pwm_led_config - instance: inst0 - path: brd4207a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h + instance: rgb_led0 + path: brd4207a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h - condition: - brd4001a override: @@ -665,8 +665,8 @@ override: component: simple_rgb_pwm_led file_id: simple_rgb_pwm_led_config - instance: inst0 - path: brd4207a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h + instance: rgb_led0 + path: brd4207a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h - condition: - brd4002a override: diff --git a/hardware/board/config/component/brd4209a_config.slcc b/hardware/board/config/component/brd4209a_config.slcc index 2f29bf3256..5964ed1f7c 100644 --- a/hardware/board/config/component/brd4209a_config.slcc +++ b/hardware/board/config/component/brd4209a_config.slcc @@ -354,8 +354,8 @@ override: component: simple_rgb_pwm_led file_id: simple_rgb_pwm_led_config - instance: inst0 - path: brd4209a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h + instance: rgb_led0 + path: brd4209a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h - condition: - brd4001a override: @@ -727,8 +727,8 @@ override: component: simple_rgb_pwm_led file_id: simple_rgb_pwm_led_config - instance: inst0 - path: brd4209a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h + instance: rgb_led0 + path: brd4209a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h - condition: - brd4002a override: diff --git a/hardware/board/config/component/brd4272a_config.slcc b/hardware/board/config/component/brd4272a_config.slcc index 1e2fc6567e..2c88db5f47 100644 --- a/hardware/board/config/component/brd4272a_config.slcc +++ b/hardware/board/config/component/brd4272a_config.slcc @@ -31,12 +31,6 @@ component: bootloader_euart_driver file_id: btl_euart_driver_cfg path: brd4272a_brd4001a/btl_euart_driver_cfg.h - - condition: - - brd4001a - override: - component: bootloader_ezsp_gpio_activation - file_id: ezsp_gpio_activation_cfg - path: brd4272a_brd4001a/btl_ezsp_gpio_activation_cfg.h - condition: - brd4001a override: @@ -88,13 +82,6 @@ component: device_init_lfxo file_id: device_init_lfxo_config path: brd4272a_brd4001a/sl_device_init_lfxo_config.h - - condition: - - brd4001a - override: - component: i2cspm - file_id: i2cspm_config - instance: sensor - path: brd4272a_brd4001a/sl_i2cspm_sensor_config.h - condition: - brd4001a override: @@ -245,18 +232,18 @@ file_id: uartdrv_eusart_config instance: exp path: brd4272a_brd4001a/sl_uartdrv_eusart_exp_config.h + - condition: + - brd4001a + override: + component: usb_device_driver_dwc_otg_fs + file_id: usbd_driver_config + path: brd4272a_brd4001a/sl_usbd_driver_config.h - condition: - brd4002a override: component: bootloader_euart_driver file_id: btl_euart_driver_cfg path: brd4272a_brd4002a/btl_euart_driver_cfg.h - - condition: - - brd4002a - override: - component: bootloader_ezsp_gpio_activation - file_id: ezsp_gpio_activation_cfg - path: brd4272a_brd4002a/btl_ezsp_gpio_activation_cfg.h - condition: - brd4002a override: @@ -308,13 +295,6 @@ component: device_init_lfxo file_id: device_init_lfxo_config path: brd4272a_brd4002a/sl_device_init_lfxo_config.h - - condition: - - brd4002a - override: - component: i2cspm - file_id: i2cspm_config - instance: sensor - path: brd4272a_brd4002a/sl_i2cspm_sensor_config.h - condition: - brd4002a override: @@ -465,3 +445,9 @@ file_id: uartdrv_eusart_config instance: exp path: brd4272a_brd4002a/sl_uartdrv_eusart_exp_config.h + - condition: + - brd4002a + override: + component: usb_device_driver_dwc_otg_fs + file_id: usbd_driver_config + path: brd4272a_brd4002a/sl_usbd_driver_config.h diff --git a/hardware/board/config/component/brd4274a_config.slcc b/hardware/board/config/component/brd4274a_config.slcc new file mode 100644 index 0000000000..517cccf646 --- /dev/null +++ b/hardware/board/config/component/brd4274a_config.slcc @@ -0,0 +1,451 @@ +!!omap +- id: brd4274a_config +- label: brd4274a config +- description: Configuration files for BRD4274A +- package: platform +- category: Platform|Board|Config +- quality: production +- ui_hints: + visibility: never +- root_path: hardware/board/config +- requires: + - name: brd4274a +- provides: + - name: brd4274a_config +- config_file: + - condition: + - brd4001a + override: + component: board_control + file_id: board_control_config + path: brd4274a_brd4001a/sl_board_control_config.h + - condition: + - brd4002a + override: + component: board_control + file_id: board_control_config + path: brd4274a_brd4002a/sl_board_control_config.h + - condition: + - brd4001a + override: + component: bootloader_euart_driver + file_id: btl_euart_driver_cfg + path: brd4274a_brd4001a/btl_euart_driver_cfg.h + - condition: + - brd4001a + override: + component: bootloader_gpio_activation + file_id: btl_gpio_activation_cfg + path: brd4274a_brd4001a/btl_gpio_activation_cfg.h + - condition: + - brd4001a + override: + component: bootloader_spi_controller_eusart_driver + file_id: btl_spi_controller_eusart_driver_cfg + path: brd4274a_brd4001a/btl_spi_controller_eusart_driver_cfg.h + - condition: + - brd4001a + override: + component: bootloader_spi_peripheral_eusart_driver + file_id: btl_spi_peripheral_eusart_driver_cfg + path: brd4274a_brd4001a/btl_spi_peripheral_eusart_driver_cfg.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_spi_eusart + file_id: cpc_drv_secondary_spi_eusart_config + instance: exp + path: brd4274a_brd4001a/sl_cpc_drv_secondary_spi_eusart_exp_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_secondary_uart_eusart_config + instance: vcom + path: brd4274a_brd4001a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h + - condition: + - brd4001a + override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_secondary_uart_eusart_config + instance: exp + path: brd4274a_brd4001a/sl_cpc_drv_secondary_uart_eusart_exp_config.h + - condition: + - brd4001a + override: + component: device_init_hfxo + file_id: device_init_hfxo_config + path: brd4274a_brd4001a/sl_device_init_hfxo_config.h + - condition: + - brd4001a + override: + component: device_init_lfxo + file_id: device_init_lfxo_config + path: brd4274a_brd4001a/sl_device_init_lfxo_config.h + - condition: + - brd4001a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: vcom + path: brd4274a_brd4001a/sl_iostream_eusart_vcom_config.h + - condition: + - brd4001a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: exp + path: brd4274a_brd4001a/sl_iostream_eusart_exp_config.h + - condition: + - brd4001a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: msc + path: brd4274a_brd4001a/iot_flash_cfg_msc.h + - condition: + - brd4001a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: sensor + path: brd4274a_brd4001a/iot_i2c_cfg_sensor.h + - condition: + - brd4001a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: exp + path: brd4274a_brd4001a/iot_i2c_cfg_exp.h + - condition: + - brd4001a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: test + path: brd4274a_brd4001a/iot_i2c_cfg_test.h + - condition: + - brd4001a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led0 + path: brd4274a_brd4001a/iot_pwm_cfg_led0.h + - condition: + - brd4001a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led1 + path: brd4274a_brd4001a/iot_pwm_cfg_led1.h + - condition: + - brd4001a + override: + component: memlcd_eusart + file_id: sl_memlcd_eusart_config + path: brd4274a_brd4001a/sl_memlcd_eusart_config.h + - condition: + - brd4001a + override: + component: mx25_flash_shutdown_eusart + file_id: mx25_flash_shutdown_eusart_config + path: brd4274a_brd4001a/sl_mx25_flash_shutdown_eusart_config.h + - condition: + - brd4001a + override: + component: pwm + file_id: pwm_config + instance: led0 + path: brd4274a_brd4001a/sl_pwm_init_led0_config.h + - condition: + - brd4001a + override: + component: pwm + file_id: pwm_config + instance: led1 + path: brd4274a_brd4001a/sl_pwm_init_led1_config.h + - condition: + - brd4001a + override: + component: rail_util_eff + file_id: rail_util_eff_config + path: brd4274a_brd4001a/sl_rail_util_eff_config.h + - condition: + - brd4001a + override: + component: rail_util_pa + file_id: rail_util_pa_config + path: brd4274a_brd4001a/sl_rail_util_pa_config.h + - condition: + - brd4001a + override: + component: rail_util_pti + file_id: rail_util_pti_config + path: brd4274a_brd4001a/sl_rail_util_pti_config.h + - condition: + - brd4001a + override: + component: simple_button + file_id: simple_button_config + instance: btn0 + path: brd4274a_brd4001a/sl_simple_button_btn0_config.h + - condition: + - brd4001a + override: + component: simple_button + file_id: simple_button_config + instance: btn1 + path: brd4274a_brd4001a/sl_simple_button_btn1_config.h + - condition: + - brd4001a + override: + component: simple_led + file_id: simple_led_config + instance: led0 + path: brd4274a_brd4001a/sl_simple_led_led0_config.h + - condition: + - brd4001a + override: + component: simple_led + file_id: simple_led_config + instance: led1 + path: brd4274a_brd4001a/sl_simple_led_led1_config.h + - condition: + - brd4001a + override: + component: spidrv_eusart + file_id: spidrv_eusart_config + instance: exp + path: brd4274a_brd4001a/sl_spidrv_eusart_exp_config.h + - condition: + - brd4001a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: vcom + path: brd4274a_brd4001a/sl_uartdrv_eusart_vcom_config.h + - condition: + - brd4001a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: exp + path: brd4274a_brd4001a/sl_uartdrv_eusart_exp_config.h + - condition: + - brd4001a + override: + component: usb_device_driver_dwc_otg_fs + file_id: usbd_driver_config + path: brd4274a_brd4001a/sl_usbd_driver_config.h + - condition: + - brd4002a + override: + component: bootloader_euart_driver + file_id: btl_euart_driver_cfg + path: brd4274a_brd4002a/btl_euart_driver_cfg.h + - condition: + - brd4002a + override: + component: bootloader_gpio_activation + file_id: btl_gpio_activation_cfg + path: brd4274a_brd4002a/btl_gpio_activation_cfg.h + - condition: + - brd4002a + override: + component: bootloader_spi_controller_eusart_driver + file_id: btl_spi_controller_eusart_driver_cfg + path: brd4274a_brd4002a/btl_spi_controller_eusart_driver_cfg.h + - condition: + - brd4002a + override: + component: bootloader_spi_peripheral_eusart_driver + file_id: btl_spi_peripheral_eusart_driver_cfg + path: brd4274a_brd4002a/btl_spi_peripheral_eusart_driver_cfg.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_spi_eusart + file_id: cpc_drv_secondary_spi_eusart_config + instance: exp + path: brd4274a_brd4002a/sl_cpc_drv_secondary_spi_eusart_exp_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_secondary_uart_eusart_config + instance: vcom + path: brd4274a_brd4002a/sl_cpc_drv_secondary_uart_eusart_vcom_config.h + - condition: + - brd4002a + override: + component: cpc_secondary_driver_uart_eusart + file_id: cpc_drv_secondary_uart_eusart_config + instance: exp + path: brd4274a_brd4002a/sl_cpc_drv_secondary_uart_eusart_exp_config.h + - condition: + - brd4002a + override: + component: device_init_hfxo + file_id: device_init_hfxo_config + path: brd4274a_brd4002a/sl_device_init_hfxo_config.h + - condition: + - brd4002a + override: + component: device_init_lfxo + file_id: device_init_lfxo_config + path: brd4274a_brd4002a/sl_device_init_lfxo_config.h + - condition: + - brd4002a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: vcom + path: brd4274a_brd4002a/sl_iostream_eusart_vcom_config.h + - condition: + - brd4002a + override: + component: iostream_eusart + file_id: iostream_eusart_config + instance: exp + path: brd4274a_brd4002a/sl_iostream_eusart_exp_config.h + - condition: + - brd4002a + override: + component: iot_flash + file_id: iot_flash_cfg + instance: msc + path: brd4274a_brd4002a/iot_flash_cfg_msc.h + - condition: + - brd4002a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: sensor + path: brd4274a_brd4002a/iot_i2c_cfg_sensor.h + - condition: + - brd4002a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: exp + path: brd4274a_brd4002a/iot_i2c_cfg_exp.h + - condition: + - brd4002a + override: + component: iot_i2c + file_id: iot_i2c_cfg + instance: test + path: brd4274a_brd4002a/iot_i2c_cfg_test.h + - condition: + - brd4002a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led0 + path: brd4274a_brd4002a/iot_pwm_cfg_led0.h + - condition: + - brd4002a + override: + component: iot_pwm + file_id: iot_pwm_cfg + instance: led1 + path: brd4274a_brd4002a/iot_pwm_cfg_led1.h + - condition: + - brd4002a + override: + component: memlcd_eusart + file_id: sl_memlcd_eusart_config + path: brd4274a_brd4002a/sl_memlcd_eusart_config.h + - condition: + - brd4002a + override: + component: mx25_flash_shutdown_eusart + file_id: mx25_flash_shutdown_eusart_config + path: brd4274a_brd4002a/sl_mx25_flash_shutdown_eusart_config.h + - condition: + - brd4002a + override: + component: pwm + file_id: pwm_config + instance: led0 + path: brd4274a_brd4002a/sl_pwm_init_led0_config.h + - condition: + - brd4002a + override: + component: pwm + file_id: pwm_config + instance: led1 + path: brd4274a_brd4002a/sl_pwm_init_led1_config.h + - condition: + - brd4002a + override: + component: rail_util_eff + file_id: rail_util_eff_config + path: brd4274a_brd4002a/sl_rail_util_eff_config.h + - condition: + - brd4002a + override: + component: rail_util_pa + file_id: rail_util_pa_config + path: brd4274a_brd4002a/sl_rail_util_pa_config.h + - condition: + - brd4002a + override: + component: rail_util_pti + file_id: rail_util_pti_config + path: brd4274a_brd4002a/sl_rail_util_pti_config.h + - condition: + - brd4002a + override: + component: simple_button + file_id: simple_button_config + instance: btn0 + path: brd4274a_brd4002a/sl_simple_button_btn0_config.h + - condition: + - brd4002a + override: + component: simple_button + file_id: simple_button_config + instance: btn1 + path: brd4274a_brd4002a/sl_simple_button_btn1_config.h + - condition: + - brd4002a + override: + component: simple_led + file_id: simple_led_config + instance: led0 + path: brd4274a_brd4002a/sl_simple_led_led0_config.h + - condition: + - brd4002a + override: + component: simple_led + file_id: simple_led_config + instance: led1 + path: brd4274a_brd4002a/sl_simple_led_led1_config.h + - condition: + - brd4002a + override: + component: spidrv_eusart + file_id: spidrv_eusart_config + instance: exp + path: brd4274a_brd4002a/sl_spidrv_eusart_exp_config.h + - condition: + - brd4002a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: vcom + path: brd4274a_brd4002a/sl_uartdrv_eusart_vcom_config.h + - condition: + - brd4002a + override: + component: uartdrv_eusart + file_id: uartdrv_eusart_config + instance: exp + path: brd4274a_brd4002a/sl_uartdrv_eusart_exp_config.h + - condition: + - brd4002a + override: + component: usb_device_driver_dwc_otg_fs + file_id: usbd_driver_config + path: brd4274a_brd4002a/sl_usbd_driver_config.h diff --git a/hardware/board/config/component/brd4328a_config.slcc b/hardware/board/config/component/brd4328a_config.slcc index 5352cd8e8d..95be42b793 100644 --- a/hardware/board/config/component/brd4328a_config.slcc +++ b/hardware/board/config/component/brd4328a_config.slcc @@ -358,8 +358,8 @@ override: component: simple_rgb_pwm_led file_id: simple_rgb_pwm_led_config - instance: inst0 - path: brd4328a_brd4001a/sl_simple_rgb_pwm_led_inst0_config.h + instance: rgb_led0 + path: brd4328a_brd4001a/sl_simple_rgb_pwm_led_rgb_led0_config.h - condition: - brd4001a override: @@ -742,8 +742,8 @@ override: component: simple_rgb_pwm_led file_id: simple_rgb_pwm_led_config - instance: inst0 - path: brd4328a_brd4002a/sl_simple_rgb_pwm_led_inst0_config.h + instance: rgb_led0 + path: brd4328a_brd4002a/sl_simple_rgb_pwm_led_rgb_led0_config.h - condition: - brd4002a override: diff --git a/hardware/board/inc/brd4166a_support.h b/hardware/board/inc/brd4166a_support.h index 2508147730..b8734c9374 100644 --- a/hardware/board/inc/brd4166a_support.h +++ b/hardware/board/inc/brd4166a_support.h @@ -28,9 +28,16 @@ * ******************************************************************************/ +#ifndef BRD4166A_SUPPORT_H +#define BRD4166A_SUPPORT_H + #include "sl_status.h" #include "sl_enum.h" +#ifdef __cplusplus +extern "C" { +#endif + /**************************************************************************//** * @defgroup brd4166a_support Thunderboard Sense 2 Support * @brief Board support functions for Thunderboard Sense 2 (BRD4166A) @@ -72,4 +79,9 @@ SL_ENUM_GENERIC(sl_thunderboard_i2c_bus_select_t, int) { ******************************************************************************/ sl_status_t sl_thunderboard_require_i2c(sl_thunderboard_i2c_bus_select_t select); +#ifdef __cplusplus +} +#endif /** @} */ + +#endif // BRD4166A_SUPPORT_H diff --git a/hardware/board/inc/sl_board_control.h b/hardware/board/inc/sl_board_control.h index bba3cfdd16..4b2974fd8e 100644 --- a/hardware/board/inc/sl_board_control.h +++ b/hardware/board/inc/sl_board_control.h @@ -33,6 +33,10 @@ #include "sl_status.h" #include "sl_enum.h" +#ifdef __cplusplus +extern "C" { +#endif + /***************************************************************************//** * @addtogroup board_control Board Control * @brief Functions to control Silicon Labs board features @@ -208,4 +212,8 @@ sl_status_t sl_board_disable_oscillator(sl_board_oscillator_t oscillator); /** @} */ +#ifdef __cplusplus +} +#endif + #endif // SL_BOARD_CONTROL_H diff --git a/hardware/board/inc/sl_board_init.h b/hardware/board/inc/sl_board_init.h index 26d7e5a4f8..8bd5f4badd 100644 --- a/hardware/board/inc/sl_board_init.h +++ b/hardware/board/inc/sl_board_init.h @@ -30,6 +30,10 @@ #ifndef SL_BOARD_INIT_H #define SL_BOARD_INIT_H +#ifdef __cplusplus +extern "C" { +#endif + /***************************************************************************//** * @addtogroup board_init Board Init * @brief Initialization of Silicon Labs board features @@ -54,4 +58,8 @@ void sl_board_init(void); void sl_board_preinit(void); /** @} */ +#ifdef __cplusplus +} +#endif + #endif // SL_BOARD_INIT_H diff --git a/hardware/driver/bmp280/bosch/BMP280_driver/bmp280.h b/hardware/driver/bmp280/bosch/BMP280_driver/bmp280.h index dcfb530ac2..37e96d4599 100644 --- a/hardware/driver/bmp280/bosch/BMP280_driver/bmp280.h +++ b/hardware/driver/bmp280/bosch/BMP280_driver/bmp280.h @@ -59,6 +59,10 @@ #ifndef BMP280_H #define BMP280_H +#ifdef __cplusplus +extern "C" { +#endif + /*! * @brief The following definition uses for define the data types * @@ -1446,4 +1450,10 @@ u32 bmp280_compensate_pressure_int64(s32 v_uncomp_pressure_s32); */ BMP280_RETURN_FUNCTION_TYPE bmp280_compute_wait_time(u8 *v_delaytime_u8r); + + +#ifdef __cplusplus +} +#endif + #endif diff --git a/hardware/driver/si72xx/inc/sl_si72xx.h b/hardware/driver/si72xx/inc/sl_si72xx.h index d39e871e99..c9b3b725e4 100644 --- a/hardware/driver/si72xx/inc/sl_si72xx.h +++ b/hardware/driver/si72xx/inc/sl_si72xx.h @@ -35,6 +35,10 @@ #include #include +#ifdef __cplusplus +extern "C" { +#endif + /***************************************************************************//** * @addtogroup si72xx Si72xx - Magnetic Hall Effect Sensor * @{ @@ -451,4 +455,8 @@ uint32_t sl_si72xx_read_variant_and_sleep(I2C_TypeDef *i2c, /** @} (end group si72xx) */ +#ifdef __cplusplus +} +#endif + #endif /* SL_SI72xx_H */ diff --git a/hardware/driver/veml6035/inc/sl_veml6035.h b/hardware/driver/veml6035/inc/sl_veml6035.h index ab797b90f1..babec11e94 100644 --- a/hardware/driver/veml6035/inc/sl_veml6035.h +++ b/hardware/driver/veml6035/inc/sl_veml6035.h @@ -35,6 +35,10 @@ #include "sl_status.h" #include "sl_enum.h" +#ifdef __cplusplus +extern "C" { +#endif + /**************************************************************************//** * @addtogroup veml6035 VEML6035 - Ambient Light Sensor * @brief Driver for the Vishay VEML6025 ambient light sensor @@ -339,4 +343,9 @@ sl_status_t sl_veml6035_read_interrupt_status(sl_i2cspm_t *i2cspm, bool *threshold_high); /** @} (end addtogroup veml6035) */ + +#ifdef __cplusplus +} +#endif + #endif //SL_VEML6035_H diff --git a/hardware/board/config/brd4113a_brd4001a/iot_flash_cfg_msc.h b/hardware/module/config/MGM210L022JIF/iot_flash_cfg_msc.h similarity index 100% rename from hardware/board/config/brd4113a_brd4001a/iot_flash_cfg_msc.h rename to hardware/module/config/MGM210L022JIF/iot_flash_cfg_msc.h diff --git a/hardware/module/config/MGM210L022JIF/sl_device_init_hfxo_config.h b/hardware/module/config/MGM210L022JIF/sl_device_init_hfxo_config.h index d9cad7f67d..d207700f04 100644 --- a/hardware/module/config/MGM210L022JIF/sl_device_init_hfxo_config.h +++ b/hardware/module/config/MGM210L022JIF/sl_device_init_hfxo_config.h @@ -1,3 +1,33 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + #ifndef SL_DEVICE_INIT_HFXO_CONFIG_H #define SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/board/config/brd4113a_brd4002a/iot_flash_cfg_msc.h b/hardware/module/config/MGM210L022JNF/iot_flash_cfg_msc.h similarity index 100% rename from hardware/board/config/brd4113a_brd4002a/iot_flash_cfg_msc.h rename to hardware/module/config/MGM210L022JNF/iot_flash_cfg_msc.h diff --git a/hardware/module/config/MGM210L022JNF/sl_device_init_hfxo_config.h b/hardware/module/config/MGM210L022JNF/sl_device_init_hfxo_config.h index d9cad7f67d..d207700f04 100644 --- a/hardware/module/config/MGM210L022JNF/sl_device_init_hfxo_config.h +++ b/hardware/module/config/MGM210L022JNF/sl_device_init_hfxo_config.h @@ -1,3 +1,33 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + #ifndef SL_DEVICE_INIT_HFXO_CONFIG_H #define SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/module/config/MGM210LA22JIF/iot_flash_cfg_msc.h b/hardware/module/config/MGM210LA22JIF/iot_flash_cfg_msc.h new file mode 100644 index 0000000000..88b1602d58 --- /dev/null +++ b/hardware/module/config/MGM210LA22JIF/iot_flash_cfg_msc.h @@ -0,0 +1,118 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_MSC_H_ +#define _IOT_FLASH_CFG_MSC_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_NUM 0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_TYPE 0 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_MSC_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_MSC_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_MSC_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_MSC_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_MSC_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_MSC_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_MSC_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_MSC_SPI +// $[USART_IOT_FLASH_CFG_MSC_SPI] + +// [USART_IOT_FLASH_CFG_MSC_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_MSC_H_ */ diff --git a/hardware/module/config/MGM210LA22JIF/sl_device_init_hfxo_config.h b/hardware/module/config/MGM210LA22JIF/sl_device_init_hfxo_config.h index d9cad7f67d..d207700f04 100644 --- a/hardware/module/config/MGM210LA22JIF/sl_device_init_hfxo_config.h +++ b/hardware/module/config/MGM210LA22JIF/sl_device_init_hfxo_config.h @@ -1,3 +1,33 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + #ifndef SL_DEVICE_INIT_HFXO_CONFIG_H #define SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/module/config/MGM210LA22JNF/iot_flash_cfg_msc.h b/hardware/module/config/MGM210LA22JNF/iot_flash_cfg_msc.h new file mode 100644 index 0000000000..88b1602d58 --- /dev/null +++ b/hardware/module/config/MGM210LA22JNF/iot_flash_cfg_msc.h @@ -0,0 +1,118 @@ +/***************************************************************************//** + * @file iot_flash_cfg_inst.h + * @brief Common I/O flash instance configurations. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#ifndef _IOT_FLASH_CFG_MSC_H_ +#define _IOT_FLASH_CFG_MSC_H_ + +/******************************************************************************* + * Flash Default Configs + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Flash General Options + +// Instance number +// Instance number used when iot_flash_open() is called. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_NUM 0 + +// Instance type +// <0=> Internal Flash (MSC) +// <1=> External Flash (SPI) +// Specify whether this instance is for internal flash (MSC) +// or an external SPI flash. If external, then you need to setup +// SPI configs below. +// Default: 0 +#define IOT_FLASH_CFG_MSC_INST_TYPE 0 + +// + +// SPI Configuration + +// Default SPI bitrate +// Default: 1000000 +#define IOT_FLASH_CFG_MSC_SPI_BITRATE 1000000 + +// Default SPI frame length <4-16> +// Default: 8 +#define IOT_FLASH_CFG_MSC_SPI_FRAME_LENGTH 8 + +// Default SPI master/slave mode +// Master +// Slave +#define IOT_FLASH_CFG_MSC_SPI_TYPE spidrvMaster + +// Default SPI bit order +// LSB transmitted first +// MSB transmitted first +#define IOT_FLASH_CFG_MSC_SPI_BIT_ORDER spidrvBitOrderMsbFirst + +// Default SPI clock mode +// SPI mode 0: CLKPOL=0, CLKPHA=0 +// SPI mode 1: CLKPOL=0, CLKPHA=1 +// SPI mode 2: CLKPOL=1, CLKPHA=0 +// SPI mode 3: CLKPOL=1, CLKPHA=1 +#define IOT_FLASH_CFG_MSC_SPI_CLOCK_MODE spidrvClockMode0 + +// Default SPI CS control scheme +// CS controlled by the SPI driver +// CS controlled by the application +#define IOT_FLASH_CFG_MSC_SPI_CS_CONTROL spidrvCsControlApplication + +// Default SPI transfer scheme +// Transfer starts immediately +// Transfer starts when the bus is idle +#define IOT_FLASH_CFG_MSC_SPI_SLAVE_START_MODE spidrvSlaveStartImmediate + +// + +// <<< end of configuration section >>> + +/******************************************************************************* + * EXTERNAL FLASH: H/W PERIPHERAL CONFIG + ******************************************************************************/ + +// <<< sl:start pin_tool >>> +// IOT_FLASH_CFG_MSC_SPI +// $[USART_IOT_FLASH_CFG_MSC_SPI] + +// [USART_IOT_FLASH_CFG_MSC_SPI]$ +// <<< sl:end pin_tool >>> + +/******************************************************************************* + * SAFE GUARD + ******************************************************************************/ + +#endif /* _IOT_FLASH_CFG_MSC_H_ */ diff --git a/hardware/module/config/MGM210LA22JNF/sl_device_init_hfxo_config.h b/hardware/module/config/MGM210LA22JNF/sl_device_init_hfxo_config.h index d9cad7f67d..d207700f04 100644 --- a/hardware/module/config/MGM210LA22JNF/sl_device_init_hfxo_config.h +++ b/hardware/module/config/MGM210LA22JNF/sl_device_init_hfxo_config.h @@ -1,3 +1,33 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + #ifndef SL_DEVICE_INIT_HFXO_CONFIG_H #define SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/hardware/module/config/component/MGM210L022JIF_config.slcc b/hardware/module/config/component/MGM210L022JIF_config.slcc index 1cda6a62ae..dff45436df 100644 --- a/hardware/module/config/component/MGM210L022JIF_config.slcc +++ b/hardware/module/config/component/MGM210L022JIF_config.slcc @@ -21,3 +21,8 @@ component: device_init_hfxo file_id: device_init_hfxo_config path: MGM210L022JIF/sl_device_init_hfxo_config.h + - override: + component: iot_flash + file_id: iot_flash_cfg + instance: msc + path: MGM210L022JIF/iot_flash_cfg_msc.h diff --git a/hardware/module/config/component/MGM210L022JNF_config.slcc b/hardware/module/config/component/MGM210L022JNF_config.slcc index 5da96eb6f1..f10f5bff59 100644 --- a/hardware/module/config/component/MGM210L022JNF_config.slcc +++ b/hardware/module/config/component/MGM210L022JNF_config.slcc @@ -21,3 +21,8 @@ component: device_init_hfxo file_id: device_init_hfxo_config path: MGM210L022JNF/sl_device_init_hfxo_config.h + - override: + component: iot_flash + file_id: iot_flash_cfg + instance: msc + path: MGM210L022JNF/iot_flash_cfg_msc.h diff --git a/hardware/module/config/component/MGM210LA22JIF_config.slcc b/hardware/module/config/component/MGM210LA22JIF_config.slcc index 832ba3c9c5..448f288be7 100644 --- a/hardware/module/config/component/MGM210LA22JIF_config.slcc +++ b/hardware/module/config/component/MGM210LA22JIF_config.slcc @@ -21,3 +21,8 @@ component: device_init_hfxo file_id: device_init_hfxo_config path: MGM210LA22JIF/sl_device_init_hfxo_config.h + - override: + component: iot_flash + file_id: iot_flash_cfg + instance: msc + path: MGM210LA22JIF/iot_flash_cfg_msc.h diff --git a/hardware/module/config/component/MGM210LA22JNF_config.slcc b/hardware/module/config/component/MGM210LA22JNF_config.slcc index 12d94946b2..7a3d0ed322 100644 --- a/hardware/module/config/component/MGM210LA22JNF_config.slcc +++ b/hardware/module/config/component/MGM210LA22JNF_config.slcc @@ -21,3 +21,8 @@ component: device_init_hfxo file_id: device_init_hfxo_config path: MGM210LA22JNF/sl_device_init_hfxo_config.h + - override: + component: iot_flash + file_id: iot_flash_cfg + instance: msc + path: MGM210LA22JNF/iot_flash_cfg_msc.h diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm210la22jif.h b/platform/Device/SiliconLabs/BGM21/Include/bgm210la22jif.h index 57021e645f..299bb231f2 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm210la22jif.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm210la22jif.h @@ -539,217 +539,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm210la22jnf.h b/platform/Device/SiliconLabs/BGM21/Include/bgm210la22jnf.h index d7792f9c1b..c85ac94abd 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm210la22jnf.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm210la22jnf.h @@ -539,217 +539,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm210p022jia.h b/platform/Device/SiliconLabs/BGM21/Include/bgm210p022jia.h index 3edc98c192..f53868d5fd 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm210p022jia.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm210p022jia.h @@ -551,217 +551,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm210p032jia.h b/platform/Device/SiliconLabs/BGM21/Include/bgm210p032jia.h index 1108ebb889..ac45d47984 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm210p032jia.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm210p032jia.h @@ -553,217 +553,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm210pa22jia.h b/platform/Device/SiliconLabs/BGM21/Include/bgm210pa22jia.h index b516e574b1..28d2bcb55f 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm210pa22jia.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm210pa22jia.h @@ -551,217 +551,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm210pa32jia.h b/platform/Device/SiliconLabs/BGM21/Include/bgm210pa32jia.h index ac32c95611..21d58d0573 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm210pa32jia.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm210pa32jia.h @@ -553,217 +553,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm210pb22jia.h b/platform/Device/SiliconLabs/BGM21/Include/bgm210pb22jia.h index 5eda41f9da..8b4327dd8b 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm210pb22jia.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm210pb22jia.h @@ -551,217 +551,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm210pb32jia.h b/platform/Device/SiliconLabs/BGM21/Include/bgm210pb32jia.h index 1882696fd7..3196b16d75 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm210pb32jia.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm210pb32jia.h @@ -553,217 +553,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_dma_descriptor.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_dma_descriptor.h index 1890850529..fdbb0e2b23 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_dma_descriptor.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_dma_descriptor.h @@ -27,6 +27,8 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef BGM21_DMA_DESCRIPTOR_H +#define BGM21_DMA_DESCRIPTOR_H #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ @@ -53,3 +55,5 @@ typedef struct { } DMA_DESCRIPTOR_TypeDef; /**< @} */ /** @} End of group Parts */ + +#endif /* BGM21_DMA_DESCRIPTOR_H */ diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldmaxbar_defines.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldmaxbar_defines.h index e874851076..74840a26eb 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_ldmaxbar_defines.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef BGM21_LDMAXBAR_DEFINES_H +#define BGM21_LDMAXBAR_DEFINES_H + /* Module source selection indices */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ @@ -140,3 +143,5 @@ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 << 0) /** Shifted Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 << 0) /** Shifted Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF << 0) /** Shifted Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ + +#endif /* BGM21_LDMAXBAR_DEFINES_H */ diff --git a/platform/Device/SiliconLabs/BGM21/Include/bgm21_prs_signals.h b/platform/Device/SiliconLabs/BGM21/Include/bgm21_prs_signals.h index af0f9cd4a6..3063baaad9 100644 --- a/platform/Device/SiliconLabs/BGM21/Include/bgm21_prs_signals.h +++ b/platform/Device/SiliconLabs/BGM21/Include/bgm21_prs_signals.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef BGM21_PRS_SIGNALS_H +#define BGM21_PRS_SIGNALS_H + /** Synchronous signal sources enumeration: */ #define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) #define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) @@ -768,3 +771,5 @@ #define PRS_SE_STATE0GATED (PRS_ASYNC_SE_STATE0GATED) #define PRS_SE_STATE1GATED (PRS_ASYNC_SE_STATE1GATED) #define PRS_SE_STATE2GATED (PRS_ASYNC_SE_STATE2GATED) + +#endif /* BGM21_PRS_SIGNALS_H */ diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm220pc22hna.h b/platform/Device/SiliconLabs/BGM22/Include/bgm220pc22hna.h index fc05c99001..9408b43f1f 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm220pc22hna.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm220pc22hna.h @@ -581,222 +581,222 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm220pc22wga.h b/platform/Device/SiliconLabs/BGM22/Include/bgm220pc22wga.h index c8447312fa..530d6cb9d9 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm220pc22wga.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm220pc22wga.h @@ -586,222 +586,222 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm220sc12wga.h b/platform/Device/SiliconLabs/BGM22/Include/bgm220sc12wga.h index 6d464fee11..d112f570f7 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm220sc12wga.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm220sc12wga.h @@ -584,222 +584,222 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm220sc22hna.h b/platform/Device/SiliconLabs/BGM22/Include/bgm220sc22hna.h index 74af64139f..3895ee66cb 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm220sc22hna.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm220sc22hna.h @@ -586,222 +586,222 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm220sc22wga.h b/platform/Device/SiliconLabs/BGM22/Include/bgm220sc22wga.h index 179f2fda02..854a2ace53 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm220sc22wga.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm220sc22wga.h @@ -586,222 +586,222 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_dma_descriptor.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_dma_descriptor.h index 4d98bcf741..a5fb887cae 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_dma_descriptor.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_dma_descriptor.h @@ -27,6 +27,8 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef BGM22_DMA_DESCRIPTOR_H +#define BGM22_DMA_DESCRIPTOR_H #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ @@ -53,3 +55,5 @@ typedef struct { } DMA_DESCRIPTOR_TypeDef; /**< @} */ /** @} End of group Parts */ + +#endif /* BGM22_DMA_DESCRIPTOR_H */ diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldmaxbar_defines.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldmaxbar_defines.h index ca94ca99c2..91b18a12ab 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_ldmaxbar_defines.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef BGM22_LDMAXBAR_DEFINES_H +#define BGM22_LDMAXBAR_DEFINES_H + /* Module source selection indices */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ @@ -148,3 +151,5 @@ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 << 0) /** Shifted Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 << 0) /** Shifted Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF << 0) /** Shifted Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ + +#endif /* BGM22_LDMAXBAR_DEFINES_H */ diff --git a/platform/Device/SiliconLabs/BGM22/Include/bgm22_prs_signals.h b/platform/Device/SiliconLabs/BGM22/Include/bgm22_prs_signals.h index 322c554bac..94c052fb46 100644 --- a/platform/Device/SiliconLabs/BGM22/Include/bgm22_prs_signals.h +++ b/platform/Device/SiliconLabs/BGM22/Include/bgm22_prs_signals.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef BGM22_PRS_SIGNALS_H +#define BGM22_PRS_SIGNALS_H + /** Synchronous signal sources enumeration: */ #define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) #define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) @@ -843,3 +846,5 @@ #define PRS_LFRCO_CALMEAS (PRS_ASYNC_LFRCO_CALMEAS) #define PRS_LFRCO_SDM (PRS_ASYNC_LFRCO_SDM) #define PRS_LFRCO_TCMEAS (PRS_ASYNC_LFRCO_TCMEAS) + +#endif /* BGM22_PRS_SIGNALS_H */ diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm240pa22vna.h b/platform/Device/SiliconLabs/BGM24/Include/bgm240pa22vna.h index dd778b6a5b..d81e3e5348 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm240pa22vna.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm240pa22vna.h @@ -623,257 +623,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm240pa32vna.h b/platform/Device/SiliconLabs/BGM24/Include/bgm240pa32vna.h index 253a6951d3..7347acf3d9 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm240pa32vna.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm240pa32vna.h @@ -621,257 +621,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm240pa32vnn.h b/platform/Device/SiliconLabs/BGM24/Include/bgm240pa32vnn.h index f0fa83283e..f7c0d3bd3b 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm240pa32vnn.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm240pa32vnn.h @@ -621,257 +621,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm240pb22vna.h b/platform/Device/SiliconLabs/BGM24/Include/bgm240pb22vna.h index ab5b0693a6..e665c1ec22 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm240pb22vna.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm240pb22vna.h @@ -624,257 +624,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm240pb32vna.h b/platform/Device/SiliconLabs/BGM24/Include/bgm240pb32vna.h index b1e803f2a1..1c36553c2e 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm240pb32vna.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm240pb32vna.h @@ -622,257 +622,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm240pb32vnn.h b/platform/Device/SiliconLabs/BGM24/Include/bgm240pb32vnn.h index 1f08ade247..eccf999c37 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm240pb32vnn.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm240pb32vnn.h @@ -622,257 +622,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm240sa22vna.h b/platform/Device/SiliconLabs/BGM24/Include/bgm240sa22vna.h index 543cacd3f0..ef5732a331 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm240sa22vna.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm240sa22vna.h @@ -637,257 +637,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm240sb22vna.h b/platform/Device/SiliconLabs/BGM24/Include/bgm240sb22vna.h index 0ddc933111..2a2db7e47e 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm240sb22vna.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm240sb22vna.h @@ -638,257 +638,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm241sb22vna.h b/platform/Device/SiliconLabs/BGM24/Include/bgm241sb22vna.h index e1016ce46c..a9f16713b3 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm241sb22vna.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm241sb22vna.h @@ -638,257 +638,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm241sd22vna.h b/platform/Device/SiliconLabs/BGM24/Include/bgm241sd22vna.h new file mode 100644 index 0000000000..5cd794c2ef --- /dev/null +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm241sd22vna.h @@ -0,0 +1,1539 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for BGM241SD22VNA + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM241SD22VNA_H +#define BGM241SD22VNA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup BGM241SD22VNA BGM241SD22VNA + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** BGM24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + MVP_IRQn = 15, /*!< 15 EFR32 MVP Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup BGM241SD22VNA_Core BGM241SD22VNA Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group BGM241SD22VNA_Core */ + +/**************************************************************************//** +* @defgroup BGM241SD22VNA_Part BGM241SD22VNA Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(BGM241SD22VNA) +#define BGM241SD22VNA 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "BGM241SD22VNA" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_BLUE_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_BG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_MODULE 1 /** Silicon Labs multi-chip module */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for BGM241SD22VNA */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define IADC0_VREFP_PORT GPIO_PB_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 2U /**< Pin of VREFP.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define MVP_PRESENT /** MVP is available in this part */ +#define MVP_COUNT 1 /** 1 MVPs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_bgm24.h" /* System Header File */ + +/** @} End of group BGM241SD22VNA_Part */ + +/**************************************************************************//** + * @defgroup BGM241SD22VNA_Peripheral_TypeDefs BGM241SD22VNA Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "bgm24_scratchpad.h" +#include "bgm24_emu.h" +#include "bgm24_cmu.h" +#include "bgm24_hfrco.h" +#include "bgm24_fsrco.h" +#include "bgm24_dpll.h" +#include "bgm24_lfxo.h" +#include "bgm24_lfrco.h" +#include "bgm24_ulfrco.h" +#include "bgm24_msc.h" +#include "bgm24_icache.h" +#include "bgm24_prs.h" +#include "bgm24_gpio.h" +#include "bgm24_ldma.h" +#include "bgm24_ldmaxbar.h" +#include "bgm24_timer.h" +#include "bgm24_usart.h" +#include "bgm24_burtc.h" +#include "bgm24_i2c.h" +#include "bgm24_syscfg.h" +#include "bgm24_buram.h" +#include "bgm24_gpcrc.h" +#include "bgm24_dcdc.h" +#include "bgm24_mailbox.h" +#include "bgm24_eusart.h" +#include "bgm24_sysrtc.h" +#include "bgm24_keyscan.h" +#include "bgm24_mpahbram.h" +#include "bgm24_aes.h" +#include "bgm24_smu.h" +#include "bgm24_letimer.h" +#include "bgm24_iadc.h" +#include "bgm24_acmp.h" +#include "bgm24_amuxcp.h" +#include "bgm24_vdac.h" +#include "bgm24_pcnt.h" +#include "bgm24_hfxo.h" +#include "bgm24_wdog.h" +#include "bgm24_semailbox.h" +#include "bgm24_mvp.h" +#include "bgm24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "bgm24_prs_signals.h" +#include "bgm24_dma_descriptor.h" +#include "bgm24_ldmaxbar_defines.h" + +/** @} End of group BGM241SD22VNA_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup BGM241SD22VNA_Peripheral_Base BGM241SD22VNA Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define MVP_S_BASE (0x4D000000UL) /* MVP_S base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ +#define MVP_NS_BASE (0x5D000000UL) /* MVP_NS base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MVP_S) && (SL_TRUSTZONE_PERIPHERAL_MVP_S != 0))) +#define MVP_BASE (MVP_S_BASE) /* MVP base address */ +#else +#define MVP_BASE (MVP_NS_BASE) /* MVP base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MVP_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group BGM241SD22VNA_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup BGM241SD22VNA_Peripheral_Declaration BGM241SD22VNA Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define MVP_S ((MVP_TypeDef *) MVP_S_BASE) /**< MVP_S base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define MVP_NS ((MVP_TypeDef *) MVP_NS_BASE) /**< MVP_NS base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define MVP ((MVP_TypeDef *) MVP_BASE) /**< MVP base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group BGM241SD22VNA_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup BGM241SD22VNA_Peripheral_Parameters BGM241SD22VNA Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group BGM241SD22VNA_Peripheral_Parameters */ + +/** @} End of group BGM241SD22VNA */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_dma_descriptor.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_dma_descriptor.h index 4b297bb1e1..aa34fbff7b 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_dma_descriptor.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_dma_descriptor.h @@ -27,6 +27,8 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef BGM24_DMA_DESCRIPTOR_H +#define BGM24_DMA_DESCRIPTOR_H #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ @@ -53,3 +55,5 @@ typedef struct { } DMA_DESCRIPTOR_TypeDef; /**< @} */ /** @} End of group Parts */ + +#endif /* BGM24_DMA_DESCRIPTOR_H */ diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldmaxbar_defines.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldmaxbar_defines.h index b96634ace7..9eff70e41c 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_ldmaxbar_defines.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef BGM24_LDMAXBAR_DEFINES_H +#define BGM24_LDMAXBAR_DEFINES_H + /* Module source selection indices */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ @@ -150,3 +153,5 @@ #define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ << 0) /** Shifted Mode VDAC0CH1_REQ for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ << 0) /** Shifted Mode VDAC1CH0_REQ for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ << 0) /** Shifted Mode VDAC1CH1_REQ for LDMAXBAR_CH_REQSEL**/ + +#endif /* BGM24_LDMAXBAR_DEFINES_H */ diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_mvp.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_mvp.h new file mode 100644 index 0000000000..cb765355b6 --- /dev/null +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_mvp.h @@ -0,0 +1,1386 @@ +/**************************************************************************//** + * @file + * @brief BGM24 MVP register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef BGM24_MVP_H +#define BGM24_MVP_H +#define MVP_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup BGM24_MVP MVP + * @{ + * @brief BGM24 MVP Register Declaration. + *****************************************************************************/ + +/** MVP PERF Register Group Declaration. */ +typedef struct { + __IM uint32_t CNT; /**< Run Counter */ +} MVP_PERF_TypeDef; + +/** MVP ARRAYST Register Group Declaration. */ +typedef struct { + __IOM uint32_t INDEXSTATE; /**< Index State */ +} MVP_ARRAYST_TypeDef; + +/** MVP LOOPST Register Group Declaration. */ +typedef struct { + __IOM uint32_t STATE; /**< Loop State */ +} MVP_LOOPST_TypeDef; + +/** MVP ALU Register Group Declaration. */ +typedef struct { + __IOM uint32_t REGSTATE; /**< ALU Rn Register */ +} MVP_ALU_TypeDef; + +/** MVP ARRAY Register Group Declaration. */ +typedef struct { + __IOM uint32_t ADDRCFG; /**< Array Base Address */ + __IOM uint32_t DIM0CFG; /**< Dimension 0 Configuration */ + __IOM uint32_t DIM1CFG; /**< Dimension 1 Configuration */ + __IOM uint32_t DIM2CFG; /**< Dimension 2 Configuration */ +} MVP_ARRAY_TypeDef; + +/** MVP LOOP Register Group Declaration. */ +typedef struct { + __IOM uint32_t CFG; /**< Loop Configuration */ + __IOM uint32_t RST; /**< Loop Reset */ +} MVP_LOOP_TypeDef; + +/** MVP INSTR Register Group Declaration. */ +typedef struct { + __IOM uint32_t CFG0; /**< Instruction Configuration Word 0 */ + __IOM uint32_t CFG1; /**< Instruction Configuration Word 1 */ + __IOM uint32_t CFG2; /**< Instruction Configuration Word 2 */ +} MVP_INSTR_TypeDef; + +/** MVP Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t SWRST; /**< Software Reset */ + __IOM uint32_t CFG; /**< Configuration */ + __IM uint32_t STATUS; /**< Status */ + MVP_PERF_TypeDef PERF[2U]; /**< */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enables */ + __IM uint32_t FAULTSTATUS; /**< Fault Status */ + __IM uint32_t FAULTADDR; /**< Fault Address */ + __IOM uint32_t PROGRAMSTATE; /**< Program State */ + MVP_ARRAYST_TypeDef ARRAYST[5U]; /**< */ + MVP_LOOPST_TypeDef LOOPST[8U]; /**< */ + MVP_ALU_TypeDef ALU[8U]; /**< */ + MVP_ARRAY_TypeDef ARRAY[5U]; /**< */ + MVP_LOOP_TypeDef LOOP[8U]; /**< */ + MVP_INSTR_TypeDef INSTR[8U]; /**< */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED0[34U]; /**< Reserved for future use */ + __IOM uint32_t DEBUGEN; /**< Debug Enable Register */ + __IOM uint32_t DEBUGSTEPCNT; /**< Debug Step Register */ + uint32_t RESERVED1[894U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t SWRST_SET; /**< Software Reset */ + __IOM uint32_t CFG_SET; /**< Configuration */ + __IM uint32_t STATUS_SET; /**< Status */ + MVP_PERF_TypeDef PERF_SET[2U]; /**< */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enables */ + __IM uint32_t FAULTSTATUS_SET; /**< Fault Status */ + __IM uint32_t FAULTADDR_SET; /**< Fault Address */ + __IOM uint32_t PROGRAMSTATE_SET; /**< Program State */ + MVP_ARRAYST_TypeDef ARRAYST_SET[5U]; /**< */ + MVP_LOOPST_TypeDef LOOPST_SET[8U]; /**< */ + MVP_ALU_TypeDef ALU_SET[8U]; /**< */ + MVP_ARRAY_TypeDef ARRAY_SET[5U]; /**< */ + MVP_LOOP_TypeDef LOOP_SET[8U]; /**< */ + MVP_INSTR_TypeDef INSTR_SET[8U]; /**< */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED2[34U]; /**< Reserved for future use */ + __IOM uint32_t DEBUGEN_SET; /**< Debug Enable Register */ + __IOM uint32_t DEBUGSTEPCNT_SET; /**< Debug Step Register */ + uint32_t RESERVED3[894U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t SWRST_CLR; /**< Software Reset */ + __IOM uint32_t CFG_CLR; /**< Configuration */ + __IM uint32_t STATUS_CLR; /**< Status */ + MVP_PERF_TypeDef PERF_CLR[2U]; /**< */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ + __IM uint32_t FAULTSTATUS_CLR; /**< Fault Status */ + __IM uint32_t FAULTADDR_CLR; /**< Fault Address */ + __IOM uint32_t PROGRAMSTATE_CLR; /**< Program State */ + MVP_ARRAYST_TypeDef ARRAYST_CLR[5U]; /**< */ + MVP_LOOPST_TypeDef LOOPST_CLR[8U]; /**< */ + MVP_ALU_TypeDef ALU_CLR[8U]; /**< */ + MVP_ARRAY_TypeDef ARRAY_CLR[5U]; /**< */ + MVP_LOOP_TypeDef LOOP_CLR[8U]; /**< */ + MVP_INSTR_TypeDef INSTR_CLR[8U]; /**< */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED4[34U]; /**< Reserved for future use */ + __IOM uint32_t DEBUGEN_CLR; /**< Debug Enable Register */ + __IOM uint32_t DEBUGSTEPCNT_CLR; /**< Debug Step Register */ + uint32_t RESERVED5[894U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t SWRST_TGL; /**< Software Reset */ + __IOM uint32_t CFG_TGL; /**< Configuration */ + __IM uint32_t STATUS_TGL; /**< Status */ + MVP_PERF_TypeDef PERF_TGL[2U]; /**< */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ + __IM uint32_t FAULTSTATUS_TGL; /**< Fault Status */ + __IM uint32_t FAULTADDR_TGL; /**< Fault Address */ + __IOM uint32_t PROGRAMSTATE_TGL; /**< Program State */ + MVP_ARRAYST_TypeDef ARRAYST_TGL[5U]; /**< */ + MVP_LOOPST_TypeDef LOOPST_TGL[8U]; /**< */ + MVP_ALU_TypeDef ALU_TGL[8U]; /**< */ + MVP_ARRAY_TypeDef ARRAY_TGL[5U]; /**< */ + MVP_LOOP_TypeDef LOOP_TGL[8U]; /**< */ + MVP_INSTR_TypeDef INSTR_TGL[8U]; /**< */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + uint32_t RESERVED6[34U]; /**< Reserved for future use */ + __IOM uint32_t DEBUGEN_TGL; /**< Debug Enable Register */ + __IOM uint32_t DEBUGSTEPCNT_TGL; /**< Debug Step Register */ +} MVP_TypeDef; +/** @} End of group BGM24_MVP */ + +/**************************************************************************//** + * @addtogroup BGM24_MVP + * @{ + * @defgroup BGM24_MVP_BitFields MVP Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for MVP IPVERSION */ +#define _MVP_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for MVP_IPVERSION */ +#define _MVP_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for MVP_IPVERSION */ +#define _MVP_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MVP_IPVERSION */ +#define _MVP_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_IPVERSION */ +#define _MVP_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for MVP_IPVERSION */ +#define MVP_IPVERSION_IPVERSION_DEFAULT (_MVP_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_IPVERSION */ + +/* Bit fields for MVP EN */ +#define _MVP_EN_RESETVALUE 0x00000000UL /**< Default value for MVP_EN */ +#define _MVP_EN_MASK 0x00000003UL /**< Mask for MVP_EN */ +#define MVP_EN_EN (0x1UL << 0) /**< Enable */ +#define _MVP_EN_EN_SHIFT 0 /**< Shift value for MVP_EN */ +#define _MVP_EN_EN_MASK 0x1UL /**< Bit mask for MVP_EN */ +#define _MVP_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_EN */ +#define MVP_EN_EN_DEFAULT (_MVP_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_EN */ +#define MVP_EN_DISABLING (0x1UL << 1) /**< Disablement Busy Status */ +#define _MVP_EN_DISABLING_SHIFT 1 /**< Shift value for MVP_DISABLING */ +#define _MVP_EN_DISABLING_MASK 0x2UL /**< Bit mask for MVP_DISABLING */ +#define _MVP_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_EN */ +#define MVP_EN_DISABLING_DEFAULT (_MVP_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_EN */ + +/* Bit fields for MVP SWRST */ +#define _MVP_SWRST_RESETVALUE 0x00000000UL /**< Default value for MVP_SWRST */ +#define _MVP_SWRST_MASK 0x00000003UL /**< Mask for MVP_SWRST */ +#define MVP_SWRST_SWRST (0x1UL << 0) /**< Software Reset Command */ +#define _MVP_SWRST_SWRST_SHIFT 0 /**< Shift value for MVP_SWRST */ +#define _MVP_SWRST_SWRST_MASK 0x1UL /**< Bit mask for MVP_SWRST */ +#define _MVP_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_SWRST */ +#define MVP_SWRST_SWRST_DEFAULT (_MVP_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_SWRST */ +#define MVP_SWRST_RESETTING (0x1UL << 1) /**< Software Reset Busy Status */ +#define _MVP_SWRST_RESETTING_SHIFT 1 /**< Shift value for MVP_RESETTING */ +#define _MVP_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for MVP_RESETTING */ +#define _MVP_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_SWRST */ +#define MVP_SWRST_RESETTING_DEFAULT (_MVP_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_SWRST */ + +/* Bit fields for MVP CFG */ +#define _MVP_CFG_RESETVALUE 0x00000000UL /**< Default value for MVP_CFG */ +#define _MVP_CFG_MASK 0x00FF000FUL /**< Mask for MVP_CFG */ +#define MVP_CFG_PERFCNTEN (0x1UL << 0) /**< Performance Counter Enable */ +#define _MVP_CFG_PERFCNTEN_SHIFT 0 /**< Shift value for MVP_PERFCNTEN */ +#define _MVP_CFG_PERFCNTEN_MASK 0x1UL /**< Bit mask for MVP_PERFCNTEN */ +#define _MVP_CFG_PERFCNTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define MVP_CFG_PERFCNTEN_DEFAULT (_MVP_CFG_PERFCNTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_CFG */ +#define MVP_CFG_OUTCOMPRESSDIS (0x1UL << 1) /**< ALU Output Stream Compression Disable */ +#define _MVP_CFG_OUTCOMPRESSDIS_SHIFT 1 /**< Shift value for MVP_OUTCOMPRESSDIS */ +#define _MVP_CFG_OUTCOMPRESSDIS_MASK 0x2UL /**< Bit mask for MVP_OUTCOMPRESSDIS */ +#define _MVP_CFG_OUTCOMPRESSDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define MVP_CFG_OUTCOMPRESSDIS_DEFAULT (_MVP_CFG_OUTCOMPRESSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_CFG */ +#define MVP_CFG_INCACHEDIS (0x1UL << 2) /**< ALU Input Word Cache Disable */ +#define _MVP_CFG_INCACHEDIS_SHIFT 2 /**< Shift value for MVP_INCACHEDIS */ +#define _MVP_CFG_INCACHEDIS_MASK 0x4UL /**< Bit mask for MVP_INCACHEDIS */ +#define _MVP_CFG_INCACHEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define MVP_CFG_INCACHEDIS_DEFAULT (_MVP_CFG_INCACHEDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_CFG */ +#define MVP_CFG_LOOPERRHALTDIS (0x1UL << 3) /**< Loop Error Halt Disable */ +#define _MVP_CFG_LOOPERRHALTDIS_SHIFT 3 /**< Shift value for MVP_LOOPERRHALTDIS */ +#define _MVP_CFG_LOOPERRHALTDIS_MASK 0x8UL /**< Bit mask for MVP_LOOPERRHALTDIS */ +#define _MVP_CFG_LOOPERRHALTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define MVP_CFG_LOOPERRHALTDIS_DEFAULT (_MVP_CFG_LOOPERRHALTDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_SHIFT 16 /**< Shift value for MVP_PERF0CNTSEL */ +#define _MVP_CFG_PERF0CNTSEL_MASK 0xF0000UL /**< Bit mask for MVP_PERF0CNTSEL */ +#define _MVP_CFG_PERF0CNTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_RUN 0x00000000UL /**< Mode RUN for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_CMD 0x00000001UL /**< Mode CMD for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_STALL 0x00000002UL /**< Mode STALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_NOOP 0x00000003UL /**< Mode NOOP for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_ALUACTIVE 0x00000004UL /**< Mode ALUACTIVE for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_PIPESTALL 0x00000005UL /**< Mode PIPESTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_IOFENCESTALL 0x00000006UL /**< Mode IOFENCESTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD0STALL 0x00000007UL /**< Mode LOAD0STALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD1STALL 0x00000008UL /**< Mode LOAD1STALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_STORESTALL 0x00000009UL /**< Mode STORESTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_BUSSTALL 0x0000000AUL /**< Mode BUSSTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD0AHBSTALL 0x0000000BUL /**< Mode LOAD0AHBSTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD1AHBSTALL 0x0000000CUL /**< Mode LOAD1AHBSTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD0FENCESTALL 0x0000000DUL /**< Mode LOAD0FENCESTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD1FENCESTALL 0x0000000EUL /**< Mode LOAD1FENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_DEFAULT (_MVP_CFG_PERF0CNTSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_RUN (_MVP_CFG_PERF0CNTSEL_RUN << 16) /**< Shifted mode RUN for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_CMD (_MVP_CFG_PERF0CNTSEL_CMD << 16) /**< Shifted mode CMD for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_STALL (_MVP_CFG_PERF0CNTSEL_STALL << 16) /**< Shifted mode STALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_NOOP (_MVP_CFG_PERF0CNTSEL_NOOP << 16) /**< Shifted mode NOOP for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_ALUACTIVE (_MVP_CFG_PERF0CNTSEL_ALUACTIVE << 16) /**< Shifted mode ALUACTIVE for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_PIPESTALL (_MVP_CFG_PERF0CNTSEL_PIPESTALL << 16) /**< Shifted mode PIPESTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_IOFENCESTALL (_MVP_CFG_PERF0CNTSEL_IOFENCESTALL << 16) /**< Shifted mode IOFENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD0STALL (_MVP_CFG_PERF0CNTSEL_LOAD0STALL << 16) /**< Shifted mode LOAD0STALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD1STALL (_MVP_CFG_PERF0CNTSEL_LOAD1STALL << 16) /**< Shifted mode LOAD1STALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_STORESTALL (_MVP_CFG_PERF0CNTSEL_STORESTALL << 16) /**< Shifted mode STORESTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_BUSSTALL (_MVP_CFG_PERF0CNTSEL_BUSSTALL << 16) /**< Shifted mode BUSSTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD0AHBSTALL (_MVP_CFG_PERF0CNTSEL_LOAD0AHBSTALL << 16) /**< Shifted mode LOAD0AHBSTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD1AHBSTALL (_MVP_CFG_PERF0CNTSEL_LOAD1AHBSTALL << 16) /**< Shifted mode LOAD1AHBSTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD0FENCESTALL (_MVP_CFG_PERF0CNTSEL_LOAD0FENCESTALL << 16) /**< Shifted mode LOAD0FENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD1FENCESTALL (_MVP_CFG_PERF0CNTSEL_LOAD1FENCESTALL << 16) /**< Shifted mode LOAD1FENCESTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_SHIFT 20 /**< Shift value for MVP_PERF1CNTSEL */ +#define _MVP_CFG_PERF1CNTSEL_MASK 0xF00000UL /**< Bit mask for MVP_PERF1CNTSEL */ +#define _MVP_CFG_PERF1CNTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_RUN 0x00000000UL /**< Mode RUN for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_CMD 0x00000001UL /**< Mode CMD for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_STALL 0x00000002UL /**< Mode STALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_NOOP 0x00000003UL /**< Mode NOOP for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_ALUACTIVE 0x00000004UL /**< Mode ALUACTIVE for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_PIPESTALL 0x00000005UL /**< Mode PIPESTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_IOFENCESTALL 0x00000006UL /**< Mode IOFENCESTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD0STALL 0x00000007UL /**< Mode LOAD0STALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD1STALL 0x00000008UL /**< Mode LOAD1STALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_STORESTALL 0x00000009UL /**< Mode STORESTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_BUSSTALL 0x0000000AUL /**< Mode BUSSTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD0AHBSTALL 0x0000000BUL /**< Mode LOAD0AHBSTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD1AHBSTALL 0x0000000CUL /**< Mode LOAD1AHBSTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD0FENCESTALL 0x0000000DUL /**< Mode LOAD0FENCESTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD1FENCESTALL 0x0000000EUL /**< Mode LOAD1FENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_DEFAULT (_MVP_CFG_PERF1CNTSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_RUN (_MVP_CFG_PERF1CNTSEL_RUN << 20) /**< Shifted mode RUN for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_CMD (_MVP_CFG_PERF1CNTSEL_CMD << 20) /**< Shifted mode CMD for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_STALL (_MVP_CFG_PERF1CNTSEL_STALL << 20) /**< Shifted mode STALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_NOOP (_MVP_CFG_PERF1CNTSEL_NOOP << 20) /**< Shifted mode NOOP for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_ALUACTIVE (_MVP_CFG_PERF1CNTSEL_ALUACTIVE << 20) /**< Shifted mode ALUACTIVE for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_PIPESTALL (_MVP_CFG_PERF1CNTSEL_PIPESTALL << 20) /**< Shifted mode PIPESTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_IOFENCESTALL (_MVP_CFG_PERF1CNTSEL_IOFENCESTALL << 20) /**< Shifted mode IOFENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD0STALL (_MVP_CFG_PERF1CNTSEL_LOAD0STALL << 20) /**< Shifted mode LOAD0STALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD1STALL (_MVP_CFG_PERF1CNTSEL_LOAD1STALL << 20) /**< Shifted mode LOAD1STALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_STORESTALL (_MVP_CFG_PERF1CNTSEL_STORESTALL << 20) /**< Shifted mode STORESTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_BUSSTALL (_MVP_CFG_PERF1CNTSEL_BUSSTALL << 20) /**< Shifted mode BUSSTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD0AHBSTALL (_MVP_CFG_PERF1CNTSEL_LOAD0AHBSTALL << 20) /**< Shifted mode LOAD0AHBSTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD1AHBSTALL (_MVP_CFG_PERF1CNTSEL_LOAD1AHBSTALL << 20) /**< Shifted mode LOAD1AHBSTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD0FENCESTALL (_MVP_CFG_PERF1CNTSEL_LOAD0FENCESTALL << 20) /**< Shifted mode LOAD0FENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD1FENCESTALL (_MVP_CFG_PERF1CNTSEL_LOAD1FENCESTALL << 20) /**< Shifted mode LOAD1FENCESTALL for MVP_CFG */ + +/* Bit fields for MVP STATUS */ +#define _MVP_STATUS_RESETVALUE 0x00000004UL /**< Default value for MVP_STATUS */ +#define _MVP_STATUS_MASK 0x00000007UL /**< Mask for MVP_STATUS */ +#define MVP_STATUS_RUNNING (0x1UL << 0) /**< Running Status */ +#define _MVP_STATUS_RUNNING_SHIFT 0 /**< Shift value for MVP_RUNNING */ +#define _MVP_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for MVP_RUNNING */ +#define _MVP_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_STATUS */ +#define MVP_STATUS_RUNNING_DEFAULT (_MVP_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_STATUS */ +#define MVP_STATUS_PAUSED (0x1UL << 1) /**< Paused Status */ +#define _MVP_STATUS_PAUSED_SHIFT 1 /**< Shift value for MVP_PAUSED */ +#define _MVP_STATUS_PAUSED_MASK 0x2UL /**< Bit mask for MVP_PAUSED */ +#define _MVP_STATUS_PAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_STATUS */ +#define MVP_STATUS_PAUSED_DEFAULT (_MVP_STATUS_PAUSED_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_STATUS */ +#define MVP_STATUS_IDLE (0x1UL << 2) /**< Idle Status */ +#define _MVP_STATUS_IDLE_SHIFT 2 /**< Shift value for MVP_IDLE */ +#define _MVP_STATUS_IDLE_MASK 0x4UL /**< Bit mask for MVP_IDLE */ +#define _MVP_STATUS_IDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MVP_STATUS */ +#define MVP_STATUS_IDLE_DEFAULT (_MVP_STATUS_IDLE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_STATUS */ + +/* Bit fields for MVP PERFCNT */ +#define _MVP_PERFCNT_RESETVALUE 0x00000000UL /**< Default value for MVP_PERFCNT */ +#define _MVP_PERFCNT_MASK 0x00FFFFFFUL /**< Mask for MVP_PERFCNT */ +#define _MVP_PERFCNT_COUNT_SHIFT 0 /**< Shift value for MVP_COUNT */ +#define _MVP_PERFCNT_COUNT_MASK 0xFFFFFFUL /**< Bit mask for MVP_COUNT */ +#define _MVP_PERFCNT_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_PERFCNT */ +#define MVP_PERFCNT_COUNT_DEFAULT (_MVP_PERFCNT_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_PERFCNT */ + +/* Bit fields for MVP IF */ +#define _MVP_IF_RESETVALUE 0x00000000UL /**< Default value for MVP_IF */ +#define _MVP_IF_MASK 0x1F0FFDFFUL /**< Mask for MVP_IF */ +#define MVP_IF_PROGDONE (0x1UL << 0) /**< Program Done Interrupt Flags */ +#define _MVP_IF_PROGDONE_SHIFT 0 /**< Shift value for MVP_PROGDONE */ +#define _MVP_IF_PROGDONE_MASK 0x1UL /**< Bit mask for MVP_PROGDONE */ +#define _MVP_IF_PROGDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_PROGDONE_DEFAULT (_MVP_IF_PROGDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP0DONE (0x1UL << 1) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP0DONE_SHIFT 1 /**< Shift value for MVP_LOOP0DONE */ +#define _MVP_IF_LOOP0DONE_MASK 0x2UL /**< Bit mask for MVP_LOOP0DONE */ +#define _MVP_IF_LOOP0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP0DONE_DEFAULT (_MVP_IF_LOOP0DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP1DONE (0x1UL << 2) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP1DONE_SHIFT 2 /**< Shift value for MVP_LOOP1DONE */ +#define _MVP_IF_LOOP1DONE_MASK 0x4UL /**< Bit mask for MVP_LOOP1DONE */ +#define _MVP_IF_LOOP1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP1DONE_DEFAULT (_MVP_IF_LOOP1DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP2DONE (0x1UL << 3) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP2DONE_SHIFT 3 /**< Shift value for MVP_LOOP2DONE */ +#define _MVP_IF_LOOP2DONE_MASK 0x8UL /**< Bit mask for MVP_LOOP2DONE */ +#define _MVP_IF_LOOP2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP2DONE_DEFAULT (_MVP_IF_LOOP2DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP3DONE (0x1UL << 4) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP3DONE_SHIFT 4 /**< Shift value for MVP_LOOP3DONE */ +#define _MVP_IF_LOOP3DONE_MASK 0x10UL /**< Bit mask for MVP_LOOP3DONE */ +#define _MVP_IF_LOOP3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP3DONE_DEFAULT (_MVP_IF_LOOP3DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP4DONE (0x1UL << 5) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP4DONE_SHIFT 5 /**< Shift value for MVP_LOOP4DONE */ +#define _MVP_IF_LOOP4DONE_MASK 0x20UL /**< Bit mask for MVP_LOOP4DONE */ +#define _MVP_IF_LOOP4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP4DONE_DEFAULT (_MVP_IF_LOOP4DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP5DONE (0x1UL << 6) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP5DONE_SHIFT 6 /**< Shift value for MVP_LOOP5DONE */ +#define _MVP_IF_LOOP5DONE_MASK 0x40UL /**< Bit mask for MVP_LOOP5DONE */ +#define _MVP_IF_LOOP5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP5DONE_DEFAULT (_MVP_IF_LOOP5DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP6DONE (0x1UL << 7) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP6DONE_SHIFT 7 /**< Shift value for MVP_LOOP6DONE */ +#define _MVP_IF_LOOP6DONE_MASK 0x80UL /**< Bit mask for MVP_LOOP6DONE */ +#define _MVP_IF_LOOP6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP6DONE_DEFAULT (_MVP_IF_LOOP6DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP7DONE (0x1UL << 8) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP7DONE_SHIFT 8 /**< Shift value for MVP_LOOP7DONE */ +#define _MVP_IF_LOOP7DONE_MASK 0x100UL /**< Bit mask for MVP_LOOP7DONE */ +#define _MVP_IF_LOOP7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP7DONE_DEFAULT (_MVP_IF_LOOP7DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUNAN (0x1UL << 10) /**< Not-a-Number Interrupt Flag */ +#define _MVP_IF_ALUNAN_SHIFT 10 /**< Shift value for MVP_ALUNAN */ +#define _MVP_IF_ALUNAN_MASK 0x400UL /**< Bit mask for MVP_ALUNAN */ +#define _MVP_IF_ALUNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUNAN_DEFAULT (_MVP_IF_ALUNAN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_R0POSREAL (0x1UL << 11) /**< R0 non-zero Interrupt Flag */ +#define _MVP_IF_R0POSREAL_SHIFT 11 /**< Shift value for MVP_R0POSREAL */ +#define _MVP_IF_R0POSREAL_MASK 0x800UL /**< Bit mask for MVP_R0POSREAL */ +#define _MVP_IF_R0POSREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_R0POSREAL_DEFAULT (_MVP_IF_R0POSREAL_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUOF (0x1UL << 12) /**< ALU Overflow on result */ +#define _MVP_IF_ALUOF_SHIFT 12 /**< Shift value for MVP_ALUOF */ +#define _MVP_IF_ALUOF_MASK 0x1000UL /**< Bit mask for MVP_ALUOF */ +#define _MVP_IF_ALUOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUOF_DEFAULT (_MVP_IF_ALUOF_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUUF (0x1UL << 13) /**< ALU Underflow on result */ +#define _MVP_IF_ALUUF_SHIFT 13 /**< Shift value for MVP_ALUUF */ +#define _MVP_IF_ALUUF_MASK 0x2000UL /**< Bit mask for MVP_ALUUF */ +#define _MVP_IF_ALUUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUUF_DEFAULT (_MVP_IF_ALUUF_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTOF (0x1UL << 14) /**< Overflow during array store */ +#define _MVP_IF_STORECONVERTOF_SHIFT 14 /**< Shift value for MVP_STORECONVERTOF */ +#define _MVP_IF_STORECONVERTOF_MASK 0x4000UL /**< Bit mask for MVP_STORECONVERTOF */ +#define _MVP_IF_STORECONVERTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTOF_DEFAULT (_MVP_IF_STORECONVERTOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTUF (0x1UL << 15) /**< Underflow during array store conversion */ +#define _MVP_IF_STORECONVERTUF_SHIFT 15 /**< Shift value for MVP_STORECONVERTUF */ +#define _MVP_IF_STORECONVERTUF_MASK 0x8000UL /**< Bit mask for MVP_STORECONVERTUF */ +#define _MVP_IF_STORECONVERTUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTUF_DEFAULT (_MVP_IF_STORECONVERTUF_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTINF (0x1UL << 16) /**< Infinity encountered during array store conversion*/ +#define _MVP_IF_STORECONVERTINF_SHIFT 16 /**< Shift value for MVP_STORECONVERTINF */ +#define _MVP_IF_STORECONVERTINF_MASK 0x10000UL /**< Bit mask for MVP_STORECONVERTINF */ +#define _MVP_IF_STORECONVERTINF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTINF_DEFAULT (_MVP_IF_STORECONVERTINF_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTNAN (0x1UL << 17) /**< NaN encountered during array store conversion*/ +#define _MVP_IF_STORECONVERTNAN_SHIFT 17 /**< Shift value for MVP_STORECONVERTNAN */ +#define _MVP_IF_STORECONVERTNAN_MASK 0x20000UL /**< Bit mask for MVP_STORECONVERTNAN */ +#define _MVP_IF_STORECONVERTNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTNAN_DEFAULT (_MVP_IF_STORECONVERTNAN_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_PERFCNT0 (0x1UL << 18) /**< Run Count Overflow Interrupt Flag */ +#define _MVP_IF_PERFCNT0_SHIFT 18 /**< Shift value for MVP_PERFCNT0 */ +#define _MVP_IF_PERFCNT0_MASK 0x40000UL /**< Bit mask for MVP_PERFCNT0 */ +#define _MVP_IF_PERFCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_PERFCNT0_DEFAULT (_MVP_IF_PERFCNT0_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_PERFCNT1 (0x1UL << 19) /**< Stall Count Overflow Interrupt Flag */ +#define _MVP_IF_PERFCNT1_SHIFT 19 /**< Shift value for MVP_PERFCNT1 */ +#define _MVP_IF_PERFCNT1_MASK 0x80000UL /**< Bit mask for MVP_PERFCNT1 */ +#define _MVP_IF_PERFCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_PERFCNT1_DEFAULT (_MVP_IF_PERFCNT1_DEFAULT << 19) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOPFAULT (0x1UL << 24) /**< Loop Fault Interrupt Flag */ +#define _MVP_IF_LOOPFAULT_SHIFT 24 /**< Shift value for MVP_LOOPFAULT */ +#define _MVP_IF_LOOPFAULT_MASK 0x1000000UL /**< Bit mask for MVP_LOOPFAULT */ +#define _MVP_IF_LOOPFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOPFAULT_DEFAULT (_MVP_IF_LOOPFAULT_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_BUSERRFAULT (0x1UL << 25) /**< Bus Error Fault Interrupt Flag */ +#define _MVP_IF_BUSERRFAULT_SHIFT 25 /**< Shift value for MVP_BUSERRFAULT */ +#define _MVP_IF_BUSERRFAULT_MASK 0x2000000UL /**< Bit mask for MVP_BUSERRFAULT */ +#define _MVP_IF_BUSERRFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_BUSERRFAULT_DEFAULT (_MVP_IF_BUSERRFAULT_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_BUSALIGNFAULT (0x1UL << 26) /**< Bus Alignment Fault Interrupt Flag */ +#define _MVP_IF_BUSALIGNFAULT_SHIFT 26 /**< Shift value for MVP_BUSALIGNFAULT */ +#define _MVP_IF_BUSALIGNFAULT_MASK 0x4000000UL /**< Bit mask for MVP_BUSALIGNFAULT */ +#define _MVP_IF_BUSALIGNFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_BUSALIGNFAULT_DEFAULT (_MVP_IF_BUSALIGNFAULT_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUFAULT (0x1UL << 27) /**< ALU Fault Interrupt Flag */ +#define _MVP_IF_ALUFAULT_SHIFT 27 /**< Shift value for MVP_ALUFAULT */ +#define _MVP_IF_ALUFAULT_MASK 0x8000000UL /**< Bit mask for MVP_ALUFAULT */ +#define _MVP_IF_ALUFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUFAULT_DEFAULT (_MVP_IF_ALUFAULT_DEFAULT << 27) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_ARRAYFAULT (0x1UL << 28) /**< Array Fault Interrupt Flag */ +#define _MVP_IF_ARRAYFAULT_SHIFT 28 /**< Shift value for MVP_ARRAYFAULT */ +#define _MVP_IF_ARRAYFAULT_MASK 0x10000000UL /**< Bit mask for MVP_ARRAYFAULT */ +#define _MVP_IF_ARRAYFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_ARRAYFAULT_DEFAULT (_MVP_IF_ARRAYFAULT_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_IF */ + +/* Bit fields for MVP IEN */ +#define _MVP_IEN_RESETVALUE 0x00000000UL /**< Default value for MVP_IEN */ +#define _MVP_IEN_MASK 0x1F0FFDFFUL /**< Mask for MVP_IEN */ +#define MVP_IEN_PROGDONE (0x1UL << 0) /**< Program Done Interrupt Enable */ +#define _MVP_IEN_PROGDONE_SHIFT 0 /**< Shift value for MVP_PROGDONE */ +#define _MVP_IEN_PROGDONE_MASK 0x1UL /**< Bit mask for MVP_PROGDONE */ +#define _MVP_IEN_PROGDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_PROGDONE_DEFAULT (_MVP_IEN_PROGDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP0DONE (0x1UL << 1) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP0DONE_SHIFT 1 /**< Shift value for MVP_LOOP0DONE */ +#define _MVP_IEN_LOOP0DONE_MASK 0x2UL /**< Bit mask for MVP_LOOP0DONE */ +#define _MVP_IEN_LOOP0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP0DONE_DEFAULT (_MVP_IEN_LOOP0DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP1DONE (0x1UL << 2) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP1DONE_SHIFT 2 /**< Shift value for MVP_LOOP1DONE */ +#define _MVP_IEN_LOOP1DONE_MASK 0x4UL /**< Bit mask for MVP_LOOP1DONE */ +#define _MVP_IEN_LOOP1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP1DONE_DEFAULT (_MVP_IEN_LOOP1DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP2DONE (0x1UL << 3) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP2DONE_SHIFT 3 /**< Shift value for MVP_LOOP2DONE */ +#define _MVP_IEN_LOOP2DONE_MASK 0x8UL /**< Bit mask for MVP_LOOP2DONE */ +#define _MVP_IEN_LOOP2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP2DONE_DEFAULT (_MVP_IEN_LOOP2DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP3DONE (0x1UL << 4) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP3DONE_SHIFT 4 /**< Shift value for MVP_LOOP3DONE */ +#define _MVP_IEN_LOOP3DONE_MASK 0x10UL /**< Bit mask for MVP_LOOP3DONE */ +#define _MVP_IEN_LOOP3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP3DONE_DEFAULT (_MVP_IEN_LOOP3DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP4DONE (0x1UL << 5) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP4DONE_SHIFT 5 /**< Shift value for MVP_LOOP4DONE */ +#define _MVP_IEN_LOOP4DONE_MASK 0x20UL /**< Bit mask for MVP_LOOP4DONE */ +#define _MVP_IEN_LOOP4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP4DONE_DEFAULT (_MVP_IEN_LOOP4DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP5DONE (0x1UL << 6) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP5DONE_SHIFT 6 /**< Shift value for MVP_LOOP5DONE */ +#define _MVP_IEN_LOOP5DONE_MASK 0x40UL /**< Bit mask for MVP_LOOP5DONE */ +#define _MVP_IEN_LOOP5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP5DONE_DEFAULT (_MVP_IEN_LOOP5DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP6DONE (0x1UL << 7) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP6DONE_SHIFT 7 /**< Shift value for MVP_LOOP6DONE */ +#define _MVP_IEN_LOOP6DONE_MASK 0x80UL /**< Bit mask for MVP_LOOP6DONE */ +#define _MVP_IEN_LOOP6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP6DONE_DEFAULT (_MVP_IEN_LOOP6DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP7DONE (0x1UL << 8) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP7DONE_SHIFT 8 /**< Shift value for MVP_LOOP7DONE */ +#define _MVP_IEN_LOOP7DONE_MASK 0x100UL /**< Bit mask for MVP_LOOP7DONE */ +#define _MVP_IEN_LOOP7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP7DONE_DEFAULT (_MVP_IEN_LOOP7DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUNAN (0x1UL << 10) /**< Not-a-Number Interrupt Enable */ +#define _MVP_IEN_ALUNAN_SHIFT 10 /**< Shift value for MVP_ALUNAN */ +#define _MVP_IEN_ALUNAN_MASK 0x400UL /**< Bit mask for MVP_ALUNAN */ +#define _MVP_IEN_ALUNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUNAN_DEFAULT (_MVP_IEN_ALUNAN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_R0POSREAL (0x1UL << 11) /**< R0 Non-Zero Interrupt Enable */ +#define _MVP_IEN_R0POSREAL_SHIFT 11 /**< Shift value for MVP_R0POSREAL */ +#define _MVP_IEN_R0POSREAL_MASK 0x800UL /**< Bit mask for MVP_R0POSREAL */ +#define _MVP_IEN_R0POSREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_R0POSREAL_DEFAULT (_MVP_IEN_R0POSREAL_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUOF (0x1UL << 12) /**< ALU Overflow Interrupt Enable */ +#define _MVP_IEN_ALUOF_SHIFT 12 /**< Shift value for MVP_ALUOF */ +#define _MVP_IEN_ALUOF_MASK 0x1000UL /**< Bit mask for MVP_ALUOF */ +#define _MVP_IEN_ALUOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUOF_DEFAULT (_MVP_IEN_ALUOF_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUUF (0x1UL << 13) /**< ALU Underflow Interrupt Enable */ +#define _MVP_IEN_ALUUF_SHIFT 13 /**< Shift value for MVP_ALUUF */ +#define _MVP_IEN_ALUUF_MASK 0x2000UL /**< Bit mask for MVP_ALUUF */ +#define _MVP_IEN_ALUUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUUF_DEFAULT (_MVP_IEN_ALUUF_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTOF (0x1UL << 14) /**< Store conversion Overflow Interrupt Enable */ +#define _MVP_IEN_STORECONVERTOF_SHIFT 14 /**< Shift value for MVP_STORECONVERTOF */ +#define _MVP_IEN_STORECONVERTOF_MASK 0x4000UL /**< Bit mask for MVP_STORECONVERTOF */ +#define _MVP_IEN_STORECONVERTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTOF_DEFAULT (_MVP_IEN_STORECONVERTOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTUF (0x1UL << 15) /**< Store Conversion Underflow Interrupt Enable */ +#define _MVP_IEN_STORECONVERTUF_SHIFT 15 /**< Shift value for MVP_STORECONVERTUF */ +#define _MVP_IEN_STORECONVERTUF_MASK 0x8000UL /**< Bit mask for MVP_STORECONVERTUF */ +#define _MVP_IEN_STORECONVERTUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTUF_DEFAULT (_MVP_IEN_STORECONVERTUF_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTINF (0x1UL << 16) /**< Store Conversion Infinity Interrupt Enable */ +#define _MVP_IEN_STORECONVERTINF_SHIFT 16 /**< Shift value for MVP_STORECONVERTINF */ +#define _MVP_IEN_STORECONVERTINF_MASK 0x10000UL /**< Bit mask for MVP_STORECONVERTINF */ +#define _MVP_IEN_STORECONVERTINF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTINF_DEFAULT (_MVP_IEN_STORECONVERTINF_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTNAN (0x1UL << 17) /**< Store Conversion NaN Interrupt Enable */ +#define _MVP_IEN_STORECONVERTNAN_SHIFT 17 /**< Shift value for MVP_STORECONVERTNAN */ +#define _MVP_IEN_STORECONVERTNAN_MASK 0x20000UL /**< Bit mask for MVP_STORECONVERTNAN */ +#define _MVP_IEN_STORECONVERTNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTNAN_DEFAULT (_MVP_IEN_STORECONVERTNAN_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_PERFCNT0 (0x1UL << 18) /**< Perf Counter 0 Overflow Interrupt Enable */ +#define _MVP_IEN_PERFCNT0_SHIFT 18 /**< Shift value for MVP_PERFCNT0 */ +#define _MVP_IEN_PERFCNT0_MASK 0x40000UL /**< Bit mask for MVP_PERFCNT0 */ +#define _MVP_IEN_PERFCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_PERFCNT0_DEFAULT (_MVP_IEN_PERFCNT0_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_PERFCNT1 (0x1UL << 19) /**< Perf Counter 1 Overflow Interrupt Enable */ +#define _MVP_IEN_PERFCNT1_SHIFT 19 /**< Shift value for MVP_PERFCNT1 */ +#define _MVP_IEN_PERFCNT1_MASK 0x80000UL /**< Bit mask for MVP_PERFCNT1 */ +#define _MVP_IEN_PERFCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_PERFCNT1_DEFAULT (_MVP_IEN_PERFCNT1_DEFAULT << 19) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOPFAULT (0x1UL << 24) /**< Loop Fault Interrupt Enable */ +#define _MVP_IEN_LOOPFAULT_SHIFT 24 /**< Shift value for MVP_LOOPFAULT */ +#define _MVP_IEN_LOOPFAULT_MASK 0x1000000UL /**< Bit mask for MVP_LOOPFAULT */ +#define _MVP_IEN_LOOPFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOPFAULT_DEFAULT (_MVP_IEN_LOOPFAULT_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_BUSERRFAULT (0x1UL << 25) /**< Bus Error Fault Interrupt Enable */ +#define _MVP_IEN_BUSERRFAULT_SHIFT 25 /**< Shift value for MVP_BUSERRFAULT */ +#define _MVP_IEN_BUSERRFAULT_MASK 0x2000000UL /**< Bit mask for MVP_BUSERRFAULT */ +#define _MVP_IEN_BUSERRFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_BUSERRFAULT_DEFAULT (_MVP_IEN_BUSERRFAULT_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_BUSALIGNFAULT (0x1UL << 26) /**< Bus Alignment Fault Interrupt Enable */ +#define _MVP_IEN_BUSALIGNFAULT_SHIFT 26 /**< Shift value for MVP_BUSALIGNFAULT */ +#define _MVP_IEN_BUSALIGNFAULT_MASK 0x4000000UL /**< Bit mask for MVP_BUSALIGNFAULT */ +#define _MVP_IEN_BUSALIGNFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_BUSALIGNFAULT_DEFAULT (_MVP_IEN_BUSALIGNFAULT_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUFAULT (0x1UL << 27) /**< ALU Input Fault Interrupt Enable */ +#define _MVP_IEN_ALUFAULT_SHIFT 27 /**< Shift value for MVP_ALUFAULT */ +#define _MVP_IEN_ALUFAULT_MASK 0x8000000UL /**< Bit mask for MVP_ALUFAULT */ +#define _MVP_IEN_ALUFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUFAULT_DEFAULT (_MVP_IEN_ALUFAULT_DEFAULT << 27) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ARRAYFAULT (0x1UL << 28) /**< Array Fault Interrupt Enable */ +#define _MVP_IEN_ARRAYFAULT_SHIFT 28 /**< Shift value for MVP_ARRAYFAULT */ +#define _MVP_IEN_ARRAYFAULT_MASK 0x10000000UL /**< Bit mask for MVP_ARRAYFAULT */ +#define _MVP_IEN_ARRAYFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ARRAYFAULT_DEFAULT (_MVP_IEN_ARRAYFAULT_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_IEN */ + +/* Bit fields for MVP FAULTSTATUS */ +#define _MVP_FAULTSTATUS_RESETVALUE 0x00000000UL /**< Default value for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_MASK 0x000F3707UL /**< Mask for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTPC_SHIFT 0 /**< Shift value for MVP_FAULTPC */ +#define _MVP_FAULTSTATUS_FAULTPC_MASK 0x7UL /**< Bit mask for MVP_FAULTPC */ +#define _MVP_FAULTSTATUS_FAULTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTPC_DEFAULT (_MVP_FAULTSTATUS_FAULTPC_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTARRAY_SHIFT 8 /**< Shift value for MVP_FAULTARRAY */ +#define _MVP_FAULTSTATUS_FAULTARRAY_MASK 0x700UL /**< Bit mask for MVP_FAULTARRAY */ +#define _MVP_FAULTSTATUS_FAULTARRAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTARRAY_DEFAULT (_MVP_FAULTSTATUS_FAULTARRAY_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_SHIFT 12 /**< Shift value for MVP_FAULTBUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_MASK 0x3000UL /**< Bit mask for MVP_FAULTBUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_NONE 0x00000000UL /**< Mode NONE for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_LOAD0STREAM 0x00000001UL /**< Mode LOAD0STREAM for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_LOAD1STREAM 0x00000002UL /**< Mode LOAD1STREAM for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_STORESTREAM 0x00000003UL /**< Mode STORESTREAM for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTBUS_DEFAULT (_MVP_FAULTSTATUS_FAULTBUS_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTBUS_NONE (_MVP_FAULTSTATUS_FAULTBUS_NONE << 12) /**< Shifted mode NONE for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTBUS_LOAD0STREAM (_MVP_FAULTSTATUS_FAULTBUS_LOAD0STREAM << 12) /**< Shifted mode LOAD0STREAM for MVP_FAULTSTATUS*/ +#define MVP_FAULTSTATUS_FAULTBUS_LOAD1STREAM (_MVP_FAULTSTATUS_FAULTBUS_LOAD1STREAM << 12) /**< Shifted mode LOAD1STREAM for MVP_FAULTSTATUS*/ +#define MVP_FAULTSTATUS_FAULTBUS_STORESTREAM (_MVP_FAULTSTATUS_FAULTBUS_STORESTREAM << 12) /**< Shifted mode STORESTREAM for MVP_FAULTSTATUS*/ +#define _MVP_FAULTSTATUS_FAULTLOOP_SHIFT 16 /**< Shift value for MVP_FAULTLOOP */ +#define _MVP_FAULTSTATUS_FAULTLOOP_MASK 0xF0000UL /**< Bit mask for MVP_FAULTLOOP */ +#define _MVP_FAULTSTATUS_FAULTLOOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTLOOP_DEFAULT (_MVP_FAULTSTATUS_FAULTLOOP_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */ + +/* Bit fields for MVP FAULTADDR */ +#define _MVP_FAULTADDR_RESETVALUE 0x00000000UL /**< Default value for MVP_FAULTADDR */ +#define _MVP_FAULTADDR_MASK 0xFFFFFFFFUL /**< Mask for MVP_FAULTADDR */ +#define _MVP_FAULTADDR_FAULTADDR_SHIFT 0 /**< Shift value for MVP_FAULTADDR */ +#define _MVP_FAULTADDR_FAULTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_FAULTADDR */ +#define _MVP_FAULTADDR_FAULTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTADDR */ +#define MVP_FAULTADDR_FAULTADDR_DEFAULT (_MVP_FAULTADDR_FAULTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_FAULTADDR */ + +/* Bit fields for MVP PROGRAMSTATE */ +#define _MVP_PROGRAMSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_PROGRAMSTATE */ +#define _MVP_PROGRAMSTATE_MASK 0x00000007UL /**< Mask for MVP_PROGRAMSTATE */ +#define _MVP_PROGRAMSTATE_PC_SHIFT 0 /**< Shift value for MVP_PC */ +#define _MVP_PROGRAMSTATE_PC_MASK 0x7UL /**< Bit mask for MVP_PC */ +#define _MVP_PROGRAMSTATE_PC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_PROGRAMSTATE */ +#define MVP_PROGRAMSTATE_PC_DEFAULT (_MVP_PROGRAMSTATE_PC_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_PROGRAMSTATE */ + +/* Bit fields for MVP ARRAYINDEXSTATE */ +#define _MVP_ARRAYINDEXSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYINDEXSTATE */ +#define _MVP_ARRAYINDEXSTATE_MASK 0x3FFFFFFFUL /**< Mask for MVP_ARRAYINDEXSTATE */ +#define _MVP_ARRAYINDEXSTATE_DIM0INDEX_SHIFT 0 /**< Shift value for MVP_DIM0INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM0INDEX_MASK 0x3FFUL /**< Bit mask for MVP_DIM0INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM0INDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYINDEXSTATE */ +#define MVP_ARRAYINDEXSTATE_DIM0INDEX_DEFAULT (_MVP_ARRAYINDEXSTATE_DIM0INDEX_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYINDEXSTATE*/ +#define _MVP_ARRAYINDEXSTATE_DIM1INDEX_SHIFT 10 /**< Shift value for MVP_DIM1INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM1INDEX_MASK 0xFFC00UL /**< Bit mask for MVP_DIM1INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM1INDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYINDEXSTATE */ +#define MVP_ARRAYINDEXSTATE_DIM1INDEX_DEFAULT (_MVP_ARRAYINDEXSTATE_DIM1INDEX_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_ARRAYINDEXSTATE*/ +#define _MVP_ARRAYINDEXSTATE_DIM2INDEX_SHIFT 20 /**< Shift value for MVP_DIM2INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM2INDEX_MASK 0x3FF00000UL /**< Bit mask for MVP_DIM2INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM2INDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYINDEXSTATE */ +#define MVP_ARRAYINDEXSTATE_DIM2INDEX_DEFAULT (_MVP_ARRAYINDEXSTATE_DIM2INDEX_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_ARRAYINDEXSTATE*/ + +/* Bit fields for MVP LOOPSTATE */ +#define _MVP_LOOPSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_LOOPSTATE */ +#define _MVP_LOOPSTATE_MASK 0x000713FFUL /**< Mask for MVP_LOOPSTATE */ +#define _MVP_LOOPSTATE_CNT_SHIFT 0 /**< Shift value for MVP_CNT */ +#define _MVP_LOOPSTATE_CNT_MASK 0x3FFUL /**< Bit mask for MVP_CNT */ +#define _MVP_LOOPSTATE_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPSTATE */ +#define MVP_LOOPSTATE_CNT_DEFAULT (_MVP_LOOPSTATE_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_LOOPSTATE */ +#define MVP_LOOPSTATE_ACTIVE (0x1UL << 12) /**< Loop Active */ +#define _MVP_LOOPSTATE_ACTIVE_SHIFT 12 /**< Shift value for MVP_ACTIVE */ +#define _MVP_LOOPSTATE_ACTIVE_MASK 0x1000UL /**< Bit mask for MVP_ACTIVE */ +#define _MVP_LOOPSTATE_ACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPSTATE */ +#define MVP_LOOPSTATE_ACTIVE_DEFAULT (_MVP_LOOPSTATE_ACTIVE_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_LOOPSTATE */ +#define _MVP_LOOPSTATE_PCBEGIN_SHIFT 16 /**< Shift value for MVP_PCBEGIN */ +#define _MVP_LOOPSTATE_PCBEGIN_MASK 0x70000UL /**< Bit mask for MVP_PCBEGIN */ +#define _MVP_LOOPSTATE_PCBEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPSTATE */ +#define MVP_LOOPSTATE_PCBEGIN_DEFAULT (_MVP_LOOPSTATE_PCBEGIN_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_LOOPSTATE */ + +/* Bit fields for MVP ALUREGSTATE */ +#define _MVP_ALUREGSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_ALUREGSTATE */ +#define _MVP_ALUREGSTATE_MASK 0xFFFFFFFFUL /**< Mask for MVP_ALUREGSTATE */ +#define _MVP_ALUREGSTATE_FREAL_SHIFT 0 /**< Shift value for MVP_FREAL */ +#define _MVP_ALUREGSTATE_FREAL_MASK 0xFFFFUL /**< Bit mask for MVP_FREAL */ +#define _MVP_ALUREGSTATE_FREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ALUREGSTATE */ +#define MVP_ALUREGSTATE_FREAL_DEFAULT (_MVP_ALUREGSTATE_FREAL_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ALUREGSTATE */ +#define _MVP_ALUREGSTATE_FIMAG_SHIFT 16 /**< Shift value for MVP_FIMAG */ +#define _MVP_ALUREGSTATE_FIMAG_MASK 0xFFFF0000UL /**< Bit mask for MVP_FIMAG */ +#define _MVP_ALUREGSTATE_FIMAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ALUREGSTATE */ +#define MVP_ALUREGSTATE_FIMAG_DEFAULT (_MVP_ALUREGSTATE_FIMAG_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ALUREGSTATE */ + +/* Bit fields for MVP ARRAYADDRCFG */ +#define _MVP_ARRAYADDRCFG_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYADDRCFG */ +#define _MVP_ARRAYADDRCFG_MASK 0xFFFFFFFFUL /**< Mask for MVP_ARRAYADDRCFG */ +#define _MVP_ARRAYADDRCFG_BASE_SHIFT 0 /**< Shift value for MVP_BASE */ +#define _MVP_ARRAYADDRCFG_BASE_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_BASE */ +#define _MVP_ARRAYADDRCFG_BASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYADDRCFG */ +#define MVP_ARRAYADDRCFG_BASE_DEFAULT (_MVP_ARRAYADDRCFG_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYADDRCFG */ + +/* Bit fields for MVP ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_RESETVALUE 0x00002000UL /**< Default value for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_MASK 0x0FFF73FFUL /**< Mask for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_SIZE_SHIFT 0 /**< Shift value for MVP_SIZE */ +#define _MVP_ARRAYDIM0CFG_SIZE_MASK 0x3FFUL /**< Bit mask for MVP_SIZE */ +#define _MVP_ARRAYDIM0CFG_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_SIZE_DEFAULT (_MVP_ARRAYDIM0CFG_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT 12 /**< Shift value for MVP_BASETYPE */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_MASK 0x3000UL /**< Bit mask for MVP_BASETYPE */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_DEFAULT 0x00000002UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_UINT8 0x00000000UL /**< Mode UINT8 for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_INT8 0x00000001UL /**< Mode INT8 for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_BINARY16 0x00000002UL /**< Mode BINARY16 for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_RESERVED 0x00000003UL /**< Mode RESERVED for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_BASETYPE_DEFAULT (_MVP_ARRAYDIM0CFG_BASETYPE_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_BASETYPE_UINT8 (_MVP_ARRAYDIM0CFG_BASETYPE_UINT8 << 12) /**< Shifted mode UINT8 for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_BASETYPE_INT8 (_MVP_ARRAYDIM0CFG_BASETYPE_INT8 << 12) /**< Shifted mode INT8 for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_BASETYPE_BINARY16 (_MVP_ARRAYDIM0CFG_BASETYPE_BINARY16 << 12) /**< Shifted mode BINARY16 for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_COMPLEX (0x1UL << 14) /**< Complex Data Type */ +#define _MVP_ARRAYDIM0CFG_COMPLEX_SHIFT 14 /**< Shift value for MVP_COMPLEX */ +#define _MVP_ARRAYDIM0CFG_COMPLEX_MASK 0x4000UL /**< Bit mask for MVP_COMPLEX */ +#define _MVP_ARRAYDIM0CFG_COMPLEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_COMPLEX_SCALAR 0x00000000UL /**< Mode SCALAR for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_COMPLEX_COMPLEX 0x00000001UL /**< Mode COMPLEX for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_COMPLEX_DEFAULT (_MVP_ARRAYDIM0CFG_COMPLEX_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_COMPLEX_SCALAR (_MVP_ARRAYDIM0CFG_COMPLEX_SCALAR << 14) /**< Shifted mode SCALAR for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_COMPLEX_COMPLEX (_MVP_ARRAYDIM0CFG_COMPLEX_COMPLEX << 14) /**< Shifted mode COMPLEX for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_STRIDE_SHIFT 16 /**< Shift value for MVP_STRIDE */ +#define _MVP_ARRAYDIM0CFG_STRIDE_MASK 0xFFF0000UL /**< Bit mask for MVP_STRIDE */ +#define _MVP_ARRAYDIM0CFG_STRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_STRIDE_DEFAULT (_MVP_ARRAYDIM0CFG_STRIDE_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */ + +/* Bit fields for MVP ARRAYDIM1CFG */ +#define _MVP_ARRAYDIM1CFG_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYDIM1CFG */ +#define _MVP_ARRAYDIM1CFG_MASK 0x0FFF03FFUL /**< Mask for MVP_ARRAYDIM1CFG */ +#define _MVP_ARRAYDIM1CFG_SIZE_SHIFT 0 /**< Shift value for MVP_SIZE */ +#define _MVP_ARRAYDIM1CFG_SIZE_MASK 0x3FFUL /**< Bit mask for MVP_SIZE */ +#define _MVP_ARRAYDIM1CFG_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM1CFG */ +#define MVP_ARRAYDIM1CFG_SIZE_DEFAULT (_MVP_ARRAYDIM1CFG_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYDIM1CFG */ +#define _MVP_ARRAYDIM1CFG_STRIDE_SHIFT 16 /**< Shift value for MVP_STRIDE */ +#define _MVP_ARRAYDIM1CFG_STRIDE_MASK 0xFFF0000UL /**< Bit mask for MVP_STRIDE */ +#define _MVP_ARRAYDIM1CFG_STRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM1CFG */ +#define MVP_ARRAYDIM1CFG_STRIDE_DEFAULT (_MVP_ARRAYDIM1CFG_STRIDE_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ARRAYDIM1CFG */ + +/* Bit fields for MVP ARRAYDIM2CFG */ +#define _MVP_ARRAYDIM2CFG_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYDIM2CFG */ +#define _MVP_ARRAYDIM2CFG_MASK 0x0FFF03FFUL /**< Mask for MVP_ARRAYDIM2CFG */ +#define _MVP_ARRAYDIM2CFG_SIZE_SHIFT 0 /**< Shift value for MVP_SIZE */ +#define _MVP_ARRAYDIM2CFG_SIZE_MASK 0x3FFUL /**< Bit mask for MVP_SIZE */ +#define _MVP_ARRAYDIM2CFG_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM2CFG */ +#define MVP_ARRAYDIM2CFG_SIZE_DEFAULT (_MVP_ARRAYDIM2CFG_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYDIM2CFG */ +#define _MVP_ARRAYDIM2CFG_STRIDE_SHIFT 16 /**< Shift value for MVP_STRIDE */ +#define _MVP_ARRAYDIM2CFG_STRIDE_MASK 0xFFF0000UL /**< Bit mask for MVP_STRIDE */ +#define _MVP_ARRAYDIM2CFG_STRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM2CFG */ +#define MVP_ARRAYDIM2CFG_STRIDE_DEFAULT (_MVP_ARRAYDIM2CFG_STRIDE_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ARRAYDIM2CFG */ + +/* Bit fields for MVP LOOPCFG */ +#define _MVP_LOOPCFG_RESETVALUE 0x00000000UL /**< Default value for MVP_LOOPCFG */ +#define _MVP_LOOPCFG_MASK 0x777773FFUL /**< Mask for MVP_LOOPCFG */ +#define _MVP_LOOPCFG_NUMITERS_SHIFT 0 /**< Shift value for MVP_NUMITERS */ +#define _MVP_LOOPCFG_NUMITERS_MASK 0x3FFUL /**< Bit mask for MVP_NUMITERS */ +#define _MVP_LOOPCFG_NUMITERS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_NUMITERS_DEFAULT (_MVP_LOOPCFG_NUMITERS_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM0 (0x1UL << 12) /**< Increment Dimension 0 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT 12 /**< Shift value for MVP_ARRAY0INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM0_MASK 0x1000UL /**< Bit mask for MVP_ARRAY0INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY0INCRDIM0_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM1 (0x1UL << 13) /**< Increment Dimension 1 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM1_SHIFT 13 /**< Shift value for MVP_ARRAY0INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM1_MASK 0x2000UL /**< Bit mask for MVP_ARRAY0INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY0INCRDIM1_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM2 (0x1UL << 14) /**< Increment Dimension 2 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM2_SHIFT 14 /**< Shift value for MVP_ARRAY0INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM2_MASK 0x4000UL /**< Bit mask for MVP_ARRAY0INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY0INCRDIM2_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM0 (0x1UL << 16) /**< Increment Dimension 0 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM0_SHIFT 16 /**< Shift value for MVP_ARRAY1INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM0_MASK 0x10000UL /**< Bit mask for MVP_ARRAY1INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY1INCRDIM0_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM1 (0x1UL << 17) /**< Increment Dimension 1 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM1_SHIFT 17 /**< Shift value for MVP_ARRAY1INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM1_MASK 0x20000UL /**< Bit mask for MVP_ARRAY1INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY1INCRDIM1_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM2 (0x1UL << 18) /**< Increment Dimension 2 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM2_SHIFT 18 /**< Shift value for MVP_ARRAY1INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM2_MASK 0x40000UL /**< Bit mask for MVP_ARRAY1INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY1INCRDIM2_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM0 (0x1UL << 20) /**< Increment Dimension 0 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM0_SHIFT 20 /**< Shift value for MVP_ARRAY2INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM0_MASK 0x100000UL /**< Bit mask for MVP_ARRAY2INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY2INCRDIM0_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM1 (0x1UL << 21) /**< Increment Dimension 1 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM1_SHIFT 21 /**< Shift value for MVP_ARRAY2INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM1_MASK 0x200000UL /**< Bit mask for MVP_ARRAY2INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY2INCRDIM1_DEFAULT << 21) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM2 (0x1UL << 22) /**< Increment Dimension 2 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM2_SHIFT 22 /**< Shift value for MVP_ARRAY2INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM2_MASK 0x400000UL /**< Bit mask for MVP_ARRAY2INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY2INCRDIM2_DEFAULT << 22) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM0 (0x1UL << 24) /**< Increment Dimension 0 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM0_SHIFT 24 /**< Shift value for MVP_ARRAY3INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM0_MASK 0x1000000UL /**< Bit mask for MVP_ARRAY3INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY3INCRDIM0_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM1 (0x1UL << 25) /**< Increment Dimension 1 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM1_SHIFT 25 /**< Shift value for MVP_ARRAY3INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM1_MASK 0x2000000UL /**< Bit mask for MVP_ARRAY3INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY3INCRDIM1_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM2 (0x1UL << 26) /**< Increment Dimension 2 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM2_SHIFT 26 /**< Shift value for MVP_ARRAY3INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM2_MASK 0x4000000UL /**< Bit mask for MVP_ARRAY3INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY3INCRDIM2_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM0 (0x1UL << 28) /**< Increment Dimension 0 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM0_SHIFT 28 /**< Shift value for MVP_ARRAY4INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM0_MASK 0x10000000UL /**< Bit mask for MVP_ARRAY4INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY4INCRDIM0_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM1 (0x1UL << 29) /**< Increment Dimension 1 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM1_SHIFT 29 /**< Shift value for MVP_ARRAY4INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM1_MASK 0x20000000UL /**< Bit mask for MVP_ARRAY4INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY4INCRDIM1_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM2 (0x1UL << 30) /**< Increment Dimension 2 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM2_SHIFT 30 /**< Shift value for MVP_ARRAY4INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM2_MASK 0x40000000UL /**< Bit mask for MVP_ARRAY4INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY4INCRDIM2_DEFAULT << 30) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ + +/* Bit fields for MVP LOOPRST */ +#define _MVP_LOOPRST_RESETVALUE 0x00000000UL /**< Default value for MVP_LOOPRST */ +#define _MVP_LOOPRST_MASK 0x77777000UL /**< Mask for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM0 (0x1UL << 12) /**< Reset Dimension 0 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM0_SHIFT 12 /**< Shift value for MVP_ARRAY0RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM0_MASK 0x1000UL /**< Bit mask for MVP_ARRAY0RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY0RESETDIM0_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM1 (0x1UL << 13) /**< Reset Dimension 1 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM1_SHIFT 13 /**< Shift value for MVP_ARRAY0RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM1_MASK 0x2000UL /**< Bit mask for MVP_ARRAY0RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY0RESETDIM1_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM2 (0x1UL << 14) /**< Reset Dimension 2 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM2_SHIFT 14 /**< Shift value for MVP_ARRAY0RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM2_MASK 0x4000UL /**< Bit mask for MVP_ARRAY0RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY0RESETDIM2_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM0 (0x1UL << 16) /**< Reset Dimension 0 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM0_SHIFT 16 /**< Shift value for MVP_ARRAY1RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM0_MASK 0x10000UL /**< Bit mask for MVP_ARRAY1RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY1RESETDIM0_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM1 (0x1UL << 17) /**< Reset Dimension 1 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM1_SHIFT 17 /**< Shift value for MVP_ARRAY1RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM1_MASK 0x20000UL /**< Bit mask for MVP_ARRAY1RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY1RESETDIM1_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM2 (0x1UL << 18) /**< Reset Dimension 2 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM2_SHIFT 18 /**< Shift value for MVP_ARRAY1RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM2_MASK 0x40000UL /**< Bit mask for MVP_ARRAY1RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY1RESETDIM2_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM0 (0x1UL << 20) /**< Reset Dimension 0 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM0_SHIFT 20 /**< Shift value for MVP_ARRAY2RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM0_MASK 0x100000UL /**< Bit mask for MVP_ARRAY2RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY2RESETDIM0_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM1 (0x1UL << 21) /**< Reset Dimension 1 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM1_SHIFT 21 /**< Shift value for MVP_ARRAY2RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM1_MASK 0x200000UL /**< Bit mask for MVP_ARRAY2RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY2RESETDIM1_DEFAULT << 21) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM2 (0x1UL << 22) /**< Reset Dimension 2 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM2_SHIFT 22 /**< Shift value for MVP_ARRAY2RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM2_MASK 0x400000UL /**< Bit mask for MVP_ARRAY2RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY2RESETDIM2_DEFAULT << 22) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM0 (0x1UL << 24) /**< Reset Dimension 0 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM0_SHIFT 24 /**< Shift value for MVP_ARRAY3RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM0_MASK 0x1000000UL /**< Bit mask for MVP_ARRAY3RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY3RESETDIM0_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM1 (0x1UL << 25) /**< Reset Dimension 1 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM1_SHIFT 25 /**< Shift value for MVP_ARRAY3RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM1_MASK 0x2000000UL /**< Bit mask for MVP_ARRAY3RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY3RESETDIM1_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM2 (0x1UL << 26) /**< Reset Dimension 2 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM2_SHIFT 26 /**< Shift value for MVP_ARRAY3RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM2_MASK 0x4000000UL /**< Bit mask for MVP_ARRAY3RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY3RESETDIM2_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM0 (0x1UL << 28) /**< Reset Dimension 0 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM0_SHIFT 28 /**< Shift value for MVP_ARRAY4RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM0_MASK 0x10000000UL /**< Bit mask for MVP_ARRAY4RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY4RESETDIM0_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM1 (0x1UL << 29) /**< Reset Dimension 1 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM1_SHIFT 29 /**< Shift value for MVP_ARRAY4RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM1_MASK 0x20000000UL /**< Bit mask for MVP_ARRAY4RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY4RESETDIM1_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM2 (0x1UL << 30) /**< Reset Dimension 2 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM2_SHIFT 30 /**< Shift value for MVP_ARRAY4RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM2_MASK 0x40000000UL /**< Bit mask for MVP_ARRAY4RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY4RESETDIM2_DEFAULT << 30) /**< Shifted mode DEFAULT for MVP_LOOPRST */ + +/* Bit fields for MVP INSTRCFG0 */ +#define _MVP_INSTRCFG0_RESETVALUE 0x00000000UL /**< Default value for MVP_INSTRCFG0 */ +#define _MVP_INSTRCFG0_MASK 0x70F7F7F7UL /**< Mask for MVP_INSTRCFG0 */ +#define _MVP_INSTRCFG0_ALUIN0REGID_SHIFT 0 /**< Shift value for MVP_ALUIN0REGID */ +#define _MVP_INSTRCFG0_ALUIN0REGID_MASK 0x7UL /**< Bit mask for MVP_ALUIN0REGID */ +#define _MVP_INSTRCFG0_ALUIN0REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0REGID_DEFAULT (_MVP_INSTRCFG0_ALUIN0REGID_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0REALZERO (0x1UL << 4) /**< Real Zero */ +#define _MVP_INSTRCFG0_ALUIN0REALZERO_SHIFT 4 /**< Shift value for MVP_ALUIN0REALZERO */ +#define _MVP_INSTRCFG0_ALUIN0REALZERO_MASK 0x10UL /**< Bit mask for MVP_ALUIN0REALZERO */ +#define _MVP_INSTRCFG0_ALUIN0REALZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0REALZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN0REALZERO_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0REALNEGATE (0x1UL << 5) /**< Real Negate */ +#define _MVP_INSTRCFG0_ALUIN0REALNEGATE_SHIFT 5 /**< Shift value for MVP_ALUIN0REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN0REALNEGATE_MASK 0x20UL /**< Bit mask for MVP_ALUIN0REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN0REALNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0REALNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN0REALNEGATE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0IMAGZERO (0x1UL << 6) /**< Imaginary Not Zero */ +#define _MVP_INSTRCFG0_ALUIN0IMAGZERO_SHIFT 6 /**< Shift value for MVP_ALUIN0IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN0IMAGZERO_MASK 0x40UL /**< Bit mask for MVP_ALUIN0IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN0IMAGZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0IMAGZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN0IMAGZERO_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0IMAGNEGATE (0x1UL << 7) /**< Imaginary Negate */ +#define _MVP_INSTRCFG0_ALUIN0IMAGNEGATE_SHIFT 7 /**< Shift value for MVP_ALUIN0IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN0IMAGNEGATE_MASK 0x80UL /**< Bit mask for MVP_ALUIN0IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN0IMAGNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0IMAGNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN0IMAGNEGATE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define _MVP_INSTRCFG0_ALUIN1REGID_SHIFT 8 /**< Shift value for MVP_ALUIN1REGID */ +#define _MVP_INSTRCFG0_ALUIN1REGID_MASK 0x700UL /**< Bit mask for MVP_ALUIN1REGID */ +#define _MVP_INSTRCFG0_ALUIN1REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1REGID_DEFAULT (_MVP_INSTRCFG0_ALUIN1REGID_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1REALZERO (0x1UL << 12) /**< Real Zero */ +#define _MVP_INSTRCFG0_ALUIN1REALZERO_SHIFT 12 /**< Shift value for MVP_ALUIN1REALZERO */ +#define _MVP_INSTRCFG0_ALUIN1REALZERO_MASK 0x1000UL /**< Bit mask for MVP_ALUIN1REALZERO */ +#define _MVP_INSTRCFG0_ALUIN1REALZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1REALZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN1REALZERO_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1REALNEGATE (0x1UL << 13) /**< Real Negate */ +#define _MVP_INSTRCFG0_ALUIN1REALNEGATE_SHIFT 13 /**< Shift value for MVP_ALUIN1REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN1REALNEGATE_MASK 0x2000UL /**< Bit mask for MVP_ALUIN1REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN1REALNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1REALNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN1REALNEGATE_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1IMAGZERO (0x1UL << 14) /**< Imaginary Not Zero */ +#define _MVP_INSTRCFG0_ALUIN1IMAGZERO_SHIFT 14 /**< Shift value for MVP_ALUIN1IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN1IMAGZERO_MASK 0x4000UL /**< Bit mask for MVP_ALUIN1IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN1IMAGZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1IMAGZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN1IMAGZERO_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1IMAGNEGATE (0x1UL << 15) /**< Imaginary Negate */ +#define _MVP_INSTRCFG0_ALUIN1IMAGNEGATE_SHIFT 15 /**< Shift value for MVP_ALUIN1IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN1IMAGNEGATE_MASK 0x8000UL /**< Bit mask for MVP_ALUIN1IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN1IMAGNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1IMAGNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN1IMAGNEGATE_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define _MVP_INSTRCFG0_ALUIN2REGID_SHIFT 16 /**< Shift value for MVP_ALUIN2REGID */ +#define _MVP_INSTRCFG0_ALUIN2REGID_MASK 0x70000UL /**< Bit mask for MVP_ALUIN2REGID */ +#define _MVP_INSTRCFG0_ALUIN2REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2REGID_DEFAULT (_MVP_INSTRCFG0_ALUIN2REGID_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2REALZERO (0x1UL << 20) /**< Real Zero */ +#define _MVP_INSTRCFG0_ALUIN2REALZERO_SHIFT 20 /**< Shift value for MVP_ALUIN2REALZERO */ +#define _MVP_INSTRCFG0_ALUIN2REALZERO_MASK 0x100000UL /**< Bit mask for MVP_ALUIN2REALZERO */ +#define _MVP_INSTRCFG0_ALUIN2REALZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2REALZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN2REALZERO_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2REALNEGATE (0x1UL << 21) /**< Real Negate */ +#define _MVP_INSTRCFG0_ALUIN2REALNEGATE_SHIFT 21 /**< Shift value for MVP_ALUIN2REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN2REALNEGATE_MASK 0x200000UL /**< Bit mask for MVP_ALUIN2REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN2REALNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2REALNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN2REALNEGATE_DEFAULT << 21) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2IMAGZERO (0x1UL << 22) /**< Imaginary Not Zero */ +#define _MVP_INSTRCFG0_ALUIN2IMAGZERO_SHIFT 22 /**< Shift value for MVP_ALUIN2IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN2IMAGZERO_MASK 0x400000UL /**< Bit mask for MVP_ALUIN2IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN2IMAGZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2IMAGZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN2IMAGZERO_DEFAULT << 22) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2IMAGNEGATE (0x1UL << 23) /**< Imaginary Negate */ +#define _MVP_INSTRCFG0_ALUIN2IMAGNEGATE_SHIFT 23 /**< Shift value for MVP_ALUIN2IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN2IMAGNEGATE_MASK 0x800000UL /**< Bit mask for MVP_ALUIN2IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN2IMAGNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2IMAGNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN2IMAGNEGATE_DEFAULT << 23) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define _MVP_INSTRCFG0_ALUOUTREGID_SHIFT 28 /**< Shift value for MVP_ALUOUTREGID */ +#define _MVP_INSTRCFG0_ALUOUTREGID_MASK 0x70000000UL /**< Bit mask for MVP_ALUOUTREGID */ +#define _MVP_INSTRCFG0_ALUOUTREGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUOUTREGID_DEFAULT (_MVP_INSTRCFG0_ALUOUTREGID_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ + +/* Bit fields for MVP INSTRCFG1 */ +#define _MVP_INSTRCFG1_RESETVALUE 0x00000000UL /**< Default value for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_MASK 0x3FFFFFFFUL /**< Mask for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_ISTREAM0REGID_SHIFT 0 /**< Shift value for MVP_ISTREAM0REGID */ +#define _MVP_INSTRCFG1_ISTREAM0REGID_MASK 0x7UL /**< Bit mask for MVP_ISTREAM0REGID */ +#define _MVP_INSTRCFG1_ISTREAM0REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0REGID_DEFAULT (_MVP_INSTRCFG1_ISTREAM0REGID_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0LOAD (0x1UL << 3) /**< Load register */ +#define _MVP_INSTRCFG1_ISTREAM0LOAD_SHIFT 3 /**< Shift value for MVP_ISTREAM0LOAD */ +#define _MVP_INSTRCFG1_ISTREAM0LOAD_MASK 0x8UL /**< Bit mask for MVP_ISTREAM0LOAD */ +#define _MVP_INSTRCFG1_ISTREAM0LOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0LOAD_DEFAULT (_MVP_INSTRCFG1_ISTREAM0LOAD_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYID_SHIFT 4 /**< Shift value for MVP_ISTREAM0ARRAYID */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYID_MASK 0x70UL /**< Bit mask for MVP_ISTREAM0ARRAYID */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYID_DEFAULT (_MVP_INSTRCFG1_ISTREAM0ARRAYID_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0 (0x1UL << 7) /**< Increment Array Dimension 0 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_SHIFT 7 /**< Shift value for MVP_ISTREAM0ARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_MASK 0x80UL /**< Bit mask for MVP_ISTREAM0ARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_DEFAULT (_MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1 (0x1UL << 8) /**< Increment Array Dimension 1 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_SHIFT 8 /**< Shift value for MVP_ISTREAM0ARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_MASK 0x100UL /**< Bit mask for MVP_ISTREAM0ARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_DEFAULT (_MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2 (0x1UL << 9) /**< Increment Array Dimension 2 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_SHIFT 9 /**< Shift value for MVP_ISTREAM0ARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_MASK 0x200UL /**< Bit mask for MVP_ISTREAM0ARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_DEFAULT (_MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_DEFAULT << 9) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_ISTREAM1REGID_SHIFT 10 /**< Shift value for MVP_ISTREAM1REGID */ +#define _MVP_INSTRCFG1_ISTREAM1REGID_MASK 0x1C00UL /**< Bit mask for MVP_ISTREAM1REGID */ +#define _MVP_INSTRCFG1_ISTREAM1REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1REGID_DEFAULT (_MVP_INSTRCFG1_ISTREAM1REGID_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1LOAD (0x1UL << 13) /**< Load register */ +#define _MVP_INSTRCFG1_ISTREAM1LOAD_SHIFT 13 /**< Shift value for MVP_ISTREAM1LOAD */ +#define _MVP_INSTRCFG1_ISTREAM1LOAD_MASK 0x2000UL /**< Bit mask for MVP_ISTREAM1LOAD */ +#define _MVP_INSTRCFG1_ISTREAM1LOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1LOAD_DEFAULT (_MVP_INSTRCFG1_ISTREAM1LOAD_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYID_SHIFT 14 /**< Shift value for MVP_ISTREAM1ARRAYID */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYID_MASK 0x1C000UL /**< Bit mask for MVP_ISTREAM1ARRAYID */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYID_DEFAULT (_MVP_INSTRCFG1_ISTREAM1ARRAYID_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0 (0x1UL << 17) /**< Increment Array Dimension 0 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_SHIFT 17 /**< Shift value for MVP_ISTREAM1ARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_MASK 0x20000UL /**< Bit mask for MVP_ISTREAM1ARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_DEFAULT (_MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1 (0x1UL << 18) /**< Increment Array Dimension 1 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_SHIFT 18 /**< Shift value for MVP_ISTREAM1ARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_MASK 0x40000UL /**< Bit mask for MVP_ISTREAM1ARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_DEFAULT (_MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2 (0x1UL << 19) /**< Increment Array Dimension 2 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_SHIFT 19 /**< Shift value for MVP_ISTREAM1ARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_MASK 0x80000UL /**< Bit mask for MVP_ISTREAM1ARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_DEFAULT (_MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_DEFAULT << 19) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_OSTREAMREGID_SHIFT 20 /**< Shift value for MVP_OSTREAMREGID */ +#define _MVP_INSTRCFG1_OSTREAMREGID_MASK 0x700000UL /**< Bit mask for MVP_OSTREAMREGID */ +#define _MVP_INSTRCFG1_OSTREAMREGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMREGID_DEFAULT (_MVP_INSTRCFG1_OSTREAMREGID_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMSTORE (0x1UL << 23) /**< Store to Register */ +#define _MVP_INSTRCFG1_OSTREAMSTORE_SHIFT 23 /**< Shift value for MVP_OSTREAMSTORE */ +#define _MVP_INSTRCFG1_OSTREAMSTORE_MASK 0x800000UL /**< Bit mask for MVP_OSTREAMSTORE */ +#define _MVP_INSTRCFG1_OSTREAMSTORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMSTORE_DEFAULT (_MVP_INSTRCFG1_OSTREAMSTORE_DEFAULT << 23) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYID_SHIFT 24 /**< Shift value for MVP_OSTREAMARRAYID */ +#define _MVP_INSTRCFG1_OSTREAMARRAYID_MASK 0x7000000UL /**< Bit mask for MVP_OSTREAMARRAYID */ +#define _MVP_INSTRCFG1_OSTREAMARRAYID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYID_DEFAULT (_MVP_INSTRCFG1_OSTREAMARRAYID_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0 (0x1UL << 27) /**< Increment Array Dimension 0 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_SHIFT 27 /**< Shift value for MVP_OSTREAMARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_MASK 0x8000000UL /**< Bit mask for MVP_OSTREAMARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_DEFAULT (_MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_DEFAULT << 27) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1 (0x1UL << 28) /**< Increment Array Dimension 1 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_SHIFT 28 /**< Shift value for MVP_OSTREAMARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_MASK 0x10000000UL /**< Bit mask for MVP_OSTREAMARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_DEFAULT (_MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2 (0x1UL << 29) /**< Increment Array Dimension 2 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_SHIFT 29 /**< Shift value for MVP_OSTREAMARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_MASK 0x20000000UL /**< Bit mask for MVP_OSTREAMARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_DEFAULT (_MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ + +/* Bit fields for MVP INSTRCFG2 */ +#define _MVP_INSTRCFG2_RESETVALUE 0x00000000UL /**< Default value for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_MASK 0x9FF0FFFFUL /**< Mask for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP0BEGIN (0x1UL << 0) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP0BEGIN_SHIFT 0 /**< Shift value for MVP_LOOP0BEGIN */ +#define _MVP_INSTRCFG2_LOOP0BEGIN_MASK 0x1UL /**< Bit mask for MVP_LOOP0BEGIN */ +#define _MVP_INSTRCFG2_LOOP0BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP0BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP0BEGIN_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP0END (0x1UL << 1) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP0END_SHIFT 1 /**< Shift value for MVP_LOOP0END */ +#define _MVP_INSTRCFG2_LOOP0END_MASK 0x2UL /**< Bit mask for MVP_LOOP0END */ +#define _MVP_INSTRCFG2_LOOP0END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP0END_DEFAULT (_MVP_INSTRCFG2_LOOP0END_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP1BEGIN (0x1UL << 2) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP1BEGIN_SHIFT 2 /**< Shift value for MVP_LOOP1BEGIN */ +#define _MVP_INSTRCFG2_LOOP1BEGIN_MASK 0x4UL /**< Bit mask for MVP_LOOP1BEGIN */ +#define _MVP_INSTRCFG2_LOOP1BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP1BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP1BEGIN_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP1END (0x1UL << 3) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP1END_SHIFT 3 /**< Shift value for MVP_LOOP1END */ +#define _MVP_INSTRCFG2_LOOP1END_MASK 0x8UL /**< Bit mask for MVP_LOOP1END */ +#define _MVP_INSTRCFG2_LOOP1END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP1END_DEFAULT (_MVP_INSTRCFG2_LOOP1END_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP2BEGIN (0x1UL << 4) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP2BEGIN_SHIFT 4 /**< Shift value for MVP_LOOP2BEGIN */ +#define _MVP_INSTRCFG2_LOOP2BEGIN_MASK 0x10UL /**< Bit mask for MVP_LOOP2BEGIN */ +#define _MVP_INSTRCFG2_LOOP2BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP2BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP2BEGIN_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP2END (0x1UL << 5) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP2END_SHIFT 5 /**< Shift value for MVP_LOOP2END */ +#define _MVP_INSTRCFG2_LOOP2END_MASK 0x20UL /**< Bit mask for MVP_LOOP2END */ +#define _MVP_INSTRCFG2_LOOP2END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP2END_DEFAULT (_MVP_INSTRCFG2_LOOP2END_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP3BEGIN (0x1UL << 6) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP3BEGIN_SHIFT 6 /**< Shift value for MVP_LOOP3BEGIN */ +#define _MVP_INSTRCFG2_LOOP3BEGIN_MASK 0x40UL /**< Bit mask for MVP_LOOP3BEGIN */ +#define _MVP_INSTRCFG2_LOOP3BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP3BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP3BEGIN_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP3END (0x1UL << 7) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP3END_SHIFT 7 /**< Shift value for MVP_LOOP3END */ +#define _MVP_INSTRCFG2_LOOP3END_MASK 0x80UL /**< Bit mask for MVP_LOOP3END */ +#define _MVP_INSTRCFG2_LOOP3END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP3END_DEFAULT (_MVP_INSTRCFG2_LOOP3END_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP4BEGIN (0x1UL << 8) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP4BEGIN_SHIFT 8 /**< Shift value for MVP_LOOP4BEGIN */ +#define _MVP_INSTRCFG2_LOOP4BEGIN_MASK 0x100UL /**< Bit mask for MVP_LOOP4BEGIN */ +#define _MVP_INSTRCFG2_LOOP4BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP4BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP4BEGIN_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP4END (0x1UL << 9) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP4END_SHIFT 9 /**< Shift value for MVP_LOOP4END */ +#define _MVP_INSTRCFG2_LOOP4END_MASK 0x200UL /**< Bit mask for MVP_LOOP4END */ +#define _MVP_INSTRCFG2_LOOP4END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP4END_DEFAULT (_MVP_INSTRCFG2_LOOP4END_DEFAULT << 9) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP5BEGIN (0x1UL << 10) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP5BEGIN_SHIFT 10 /**< Shift value for MVP_LOOP5BEGIN */ +#define _MVP_INSTRCFG2_LOOP5BEGIN_MASK 0x400UL /**< Bit mask for MVP_LOOP5BEGIN */ +#define _MVP_INSTRCFG2_LOOP5BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP5BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP5BEGIN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP5END (0x1UL << 11) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP5END_SHIFT 11 /**< Shift value for MVP_LOOP5END */ +#define _MVP_INSTRCFG2_LOOP5END_MASK 0x800UL /**< Bit mask for MVP_LOOP5END */ +#define _MVP_INSTRCFG2_LOOP5END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP5END_DEFAULT (_MVP_INSTRCFG2_LOOP5END_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP6BEGIN (0x1UL << 12) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP6BEGIN_SHIFT 12 /**< Shift value for MVP_LOOP6BEGIN */ +#define _MVP_INSTRCFG2_LOOP6BEGIN_MASK 0x1000UL /**< Bit mask for MVP_LOOP6BEGIN */ +#define _MVP_INSTRCFG2_LOOP6BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP6BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP6BEGIN_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP6END (0x1UL << 13) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP6END_SHIFT 13 /**< Shift value for MVP_LOOP6END */ +#define _MVP_INSTRCFG2_LOOP6END_MASK 0x2000UL /**< Bit mask for MVP_LOOP6END */ +#define _MVP_INSTRCFG2_LOOP6END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP6END_DEFAULT (_MVP_INSTRCFG2_LOOP6END_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP7BEGIN (0x1UL << 14) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP7BEGIN_SHIFT 14 /**< Shift value for MVP_LOOP7BEGIN */ +#define _MVP_INSTRCFG2_LOOP7BEGIN_MASK 0x4000UL /**< Bit mask for MVP_LOOP7BEGIN */ +#define _MVP_INSTRCFG2_LOOP7BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP7BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP7BEGIN_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP7END (0x1UL << 15) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP7END_SHIFT 15 /**< Shift value for MVP_LOOP7END */ +#define _MVP_INSTRCFG2_LOOP7END_MASK 0x8000UL /**< Bit mask for MVP_LOOP7END */ +#define _MVP_INSTRCFG2_LOOP7END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP7END_DEFAULT (_MVP_INSTRCFG2_LOOP7END_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_SHIFT 20 /**< Shift value for MVP_ALUOP */ +#define _MVP_INSTRCFG2_ALUOP_MASK 0x1FF00000UL /**< Bit mask for MVP_ALUOP */ +#define _MVP_INSTRCFG2_ALUOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_NOOP 0x00000000UL /**< Mode NOOP for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_CLEAR 0x00000001UL /**< Mode CLEAR for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_COPY 0x00000041UL /**< Mode COPY for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_SWAP 0x00000042UL /**< Mode SWAP for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_DBL 0x00000043UL /**< Mode DBL for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_FANA 0x00000044UL /**< Mode FANA for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_FANB 0x00000045UL /**< Mode FANB for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_RELU2 0x00000046UL /**< Mode RELU2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_NRELU2 0x00000047UL /**< Mode NRELU2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_INC2 0x00000048UL /**< Mode INC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_DEC2 0x00000049UL /**< Mode DEC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ADDR 0x0000004AUL /**< Mode ADDR for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MAX 0x0000004BUL /**< Mode MAX for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MIN 0x0000004CUL /**< Mode MIN for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_RSQR2B 0x00000124UL /**< Mode RSQR2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ADDC 0x0000014EUL /**< Mode ADDC for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MAX2A 0x00000153UL /**< Mode MAX2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MIN2A 0x00000154UL /**< Mode MIN2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_XREALC2 0x0000015EUL /**< Mode XREALC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_XIMAGC2 0x0000015FUL /**< Mode XIMAGC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ADDR2B 0x00000161UL /**< Mode ADDR2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MAX2B 0x00000162UL /**< Mode MAX2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MIN2B 0x00000163UL /**< Mode MIN2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MULC 0x0000018DUL /**< Mode MULC for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MULR2A 0x00000197UL /**< Mode MULR2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MULR2B 0x00000198UL /**< Mode MULR2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ADDR4 0x0000019AUL /**< Mode ADDR4 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MAX4 0x0000019BUL /**< Mode MAX4 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MIN4 0x0000019CUL /**< Mode MIN4 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_SQRMAGC2 0x0000019DUL /**< Mode SQRMAGC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_PRELU2B 0x000001A0UL /**< Mode PRELU2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MACC 0x000001CDUL /**< Mode MACC for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_AACC 0x000001CEUL /**< Mode AACC for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ELU2A 0x000001CFUL /**< Mode ELU2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ELU2B 0x000001D0UL /**< Mode ELU2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_IFR2A 0x000001D1UL /**< Mode IFR2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_IFR2B 0x000001D2UL /**< Mode IFR2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MAXAC2 0x000001D3UL /**< Mode MAXAC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MINAC2 0x000001D4UL /**< Mode MINAC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_CLIP2A 0x000001D5UL /**< Mode CLIP2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_CLIP2B 0x000001D6UL /**< Mode CLIP2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MACR2A 0x000001D7UL /**< Mode MACR2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MACR2B 0x000001D8UL /**< Mode MACR2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_IFC 0x000001D9UL /**< Mode IFC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_DEFAULT (_MVP_INSTRCFG2_ALUOP_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_NOOP (_MVP_INSTRCFG2_ALUOP_NOOP << 20) /**< Shifted mode NOOP for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_CLEAR (_MVP_INSTRCFG2_ALUOP_CLEAR << 20) /**< Shifted mode CLEAR for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_COPY (_MVP_INSTRCFG2_ALUOP_COPY << 20) /**< Shifted mode COPY for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_SWAP (_MVP_INSTRCFG2_ALUOP_SWAP << 20) /**< Shifted mode SWAP for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_DBL (_MVP_INSTRCFG2_ALUOP_DBL << 20) /**< Shifted mode DBL for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_FANA (_MVP_INSTRCFG2_ALUOP_FANA << 20) /**< Shifted mode FANA for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_FANB (_MVP_INSTRCFG2_ALUOP_FANB << 20) /**< Shifted mode FANB for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_RELU2 (_MVP_INSTRCFG2_ALUOP_RELU2 << 20) /**< Shifted mode RELU2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_NRELU2 (_MVP_INSTRCFG2_ALUOP_NRELU2 << 20) /**< Shifted mode NRELU2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_INC2 (_MVP_INSTRCFG2_ALUOP_INC2 << 20) /**< Shifted mode INC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_DEC2 (_MVP_INSTRCFG2_ALUOP_DEC2 << 20) /**< Shifted mode DEC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ADDR (_MVP_INSTRCFG2_ALUOP_ADDR << 20) /**< Shifted mode ADDR for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MAX (_MVP_INSTRCFG2_ALUOP_MAX << 20) /**< Shifted mode MAX for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MIN (_MVP_INSTRCFG2_ALUOP_MIN << 20) /**< Shifted mode MIN for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_RSQR2B (_MVP_INSTRCFG2_ALUOP_RSQR2B << 20) /**< Shifted mode RSQR2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ADDC (_MVP_INSTRCFG2_ALUOP_ADDC << 20) /**< Shifted mode ADDC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MAX2A (_MVP_INSTRCFG2_ALUOP_MAX2A << 20) /**< Shifted mode MAX2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MIN2A (_MVP_INSTRCFG2_ALUOP_MIN2A << 20) /**< Shifted mode MIN2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_XREALC2 (_MVP_INSTRCFG2_ALUOP_XREALC2 << 20) /**< Shifted mode XREALC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_XIMAGC2 (_MVP_INSTRCFG2_ALUOP_XIMAGC2 << 20) /**< Shifted mode XIMAGC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ADDR2B (_MVP_INSTRCFG2_ALUOP_ADDR2B << 20) /**< Shifted mode ADDR2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MAX2B (_MVP_INSTRCFG2_ALUOP_MAX2B << 20) /**< Shifted mode MAX2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MIN2B (_MVP_INSTRCFG2_ALUOP_MIN2B << 20) /**< Shifted mode MIN2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MULC (_MVP_INSTRCFG2_ALUOP_MULC << 20) /**< Shifted mode MULC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MULR2A (_MVP_INSTRCFG2_ALUOP_MULR2A << 20) /**< Shifted mode MULR2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MULR2B (_MVP_INSTRCFG2_ALUOP_MULR2B << 20) /**< Shifted mode MULR2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ADDR4 (_MVP_INSTRCFG2_ALUOP_ADDR4 << 20) /**< Shifted mode ADDR4 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MAX4 (_MVP_INSTRCFG2_ALUOP_MAX4 << 20) /**< Shifted mode MAX4 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MIN4 (_MVP_INSTRCFG2_ALUOP_MIN4 << 20) /**< Shifted mode MIN4 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_SQRMAGC2 (_MVP_INSTRCFG2_ALUOP_SQRMAGC2 << 20) /**< Shifted mode SQRMAGC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_PRELU2B (_MVP_INSTRCFG2_ALUOP_PRELU2B << 20) /**< Shifted mode PRELU2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MACC (_MVP_INSTRCFG2_ALUOP_MACC << 20) /**< Shifted mode MACC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_AACC (_MVP_INSTRCFG2_ALUOP_AACC << 20) /**< Shifted mode AACC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ELU2A (_MVP_INSTRCFG2_ALUOP_ELU2A << 20) /**< Shifted mode ELU2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ELU2B (_MVP_INSTRCFG2_ALUOP_ELU2B << 20) /**< Shifted mode ELU2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_IFR2A (_MVP_INSTRCFG2_ALUOP_IFR2A << 20) /**< Shifted mode IFR2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_IFR2B (_MVP_INSTRCFG2_ALUOP_IFR2B << 20) /**< Shifted mode IFR2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MAXAC2 (_MVP_INSTRCFG2_ALUOP_MAXAC2 << 20) /**< Shifted mode MAXAC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MINAC2 (_MVP_INSTRCFG2_ALUOP_MINAC2 << 20) /**< Shifted mode MINAC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_CLIP2A (_MVP_INSTRCFG2_ALUOP_CLIP2A << 20) /**< Shifted mode CLIP2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_CLIP2B (_MVP_INSTRCFG2_ALUOP_CLIP2B << 20) /**< Shifted mode CLIP2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MACR2A (_MVP_INSTRCFG2_ALUOP_MACR2A << 20) /**< Shifted mode MACR2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MACR2B (_MVP_INSTRCFG2_ALUOP_MACR2B << 20) /**< Shifted mode MACR2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_IFC (_MVP_INSTRCFG2_ALUOP_IFC << 20) /**< Shifted mode IFC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ENDPROG (0x1UL << 31) /**< End of Program */ +#define _MVP_INSTRCFG2_ENDPROG_SHIFT 31 /**< Shift value for MVP_ENDPROG */ +#define _MVP_INSTRCFG2_ENDPROG_MASK 0x80000000UL /**< Bit mask for MVP_ENDPROG */ +#define _MVP_INSTRCFG2_ENDPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ENDPROG_DEFAULT (_MVP_INSTRCFG2_ENDPROG_DEFAULT << 31) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ + +/* Bit fields for MVP CMD */ +#define _MVP_CMD_RESETVALUE 0x00000000UL /**< Default value for MVP_CMD */ +#define _MVP_CMD_MASK 0x0000000FUL /**< Mask for MVP_CMD */ +#define MVP_CMD_START (0x1UL << 0) /**< Start Command */ +#define _MVP_CMD_START_SHIFT 0 /**< Shift value for MVP_START */ +#define _MVP_CMD_START_MASK 0x1UL /**< Bit mask for MVP_START */ +#define _MVP_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */ +#define MVP_CMD_START_DEFAULT (_MVP_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_CMD */ +#define MVP_CMD_HALT (0x1UL << 1) /**< Halt Command */ +#define _MVP_CMD_HALT_SHIFT 1 /**< Shift value for MVP_HALT */ +#define _MVP_CMD_HALT_MASK 0x2UL /**< Bit mask for MVP_HALT */ +#define _MVP_CMD_HALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */ +#define MVP_CMD_HALT_DEFAULT (_MVP_CMD_HALT_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_CMD */ +#define MVP_CMD_STEP (0x1UL << 2) /**< Step Command */ +#define _MVP_CMD_STEP_SHIFT 2 /**< Shift value for MVP_STEP */ +#define _MVP_CMD_STEP_MASK 0x4UL /**< Bit mask for MVP_STEP */ +#define _MVP_CMD_STEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */ +#define MVP_CMD_STEP_DEFAULT (_MVP_CMD_STEP_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_CMD */ +#define MVP_CMD_INIT (0x1UL << 3) /**< Initialization Command/Qualifier */ +#define _MVP_CMD_INIT_SHIFT 3 /**< Shift value for MVP_INIT */ +#define _MVP_CMD_INIT_MASK 0x8UL /**< Bit mask for MVP_INIT */ +#define _MVP_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */ +#define MVP_CMD_INIT_DEFAULT (_MVP_CMD_INIT_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_CMD */ + +/* Bit fields for MVP DEBUGEN */ +#define _MVP_DEBUGEN_RESETVALUE 0x00000000UL /**< Default value for MVP_DEBUGEN */ +#define _MVP_DEBUGEN_MASK 0x7003FDFEUL /**< Mask for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP0DONE (0x1UL << 1) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP0DONE_SHIFT 1 /**< Shift value for MVP_BKPTLOOP0DONE */ +#define _MVP_DEBUGEN_BKPTLOOP0DONE_MASK 0x2UL /**< Bit mask for MVP_BKPTLOOP0DONE */ +#define _MVP_DEBUGEN_BKPTLOOP0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP0DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP0DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP1DONE (0x1UL << 2) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP1DONE_SHIFT 2 /**< Shift value for MVP_BKPTLOOP1DONE */ +#define _MVP_DEBUGEN_BKPTLOOP1DONE_MASK 0x4UL /**< Bit mask for MVP_BKPTLOOP1DONE */ +#define _MVP_DEBUGEN_BKPTLOOP1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP1DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP1DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP2DONE (0x1UL << 3) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP2DONE_SHIFT 3 /**< Shift value for MVP_BKPTLOOP2DONE */ +#define _MVP_DEBUGEN_BKPTLOOP2DONE_MASK 0x8UL /**< Bit mask for MVP_BKPTLOOP2DONE */ +#define _MVP_DEBUGEN_BKPTLOOP2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP2DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP2DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP3DONE (0x1UL << 4) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP3DONE_SHIFT 4 /**< Shift value for MVP_BKPTLOOP3DONE */ +#define _MVP_DEBUGEN_BKPTLOOP3DONE_MASK 0x10UL /**< Bit mask for MVP_BKPTLOOP3DONE */ +#define _MVP_DEBUGEN_BKPTLOOP3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP3DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP3DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP4DONE (0x1UL << 5) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP4DONE_SHIFT 5 /**< Shift value for MVP_BKPTLOOP4DONE */ +#define _MVP_DEBUGEN_BKPTLOOP4DONE_MASK 0x20UL /**< Bit mask for MVP_BKPTLOOP4DONE */ +#define _MVP_DEBUGEN_BKPTLOOP4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP4DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP4DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP5DONE (0x1UL << 6) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP5DONE_SHIFT 6 /**< Shift value for MVP_BKPTLOOP5DONE */ +#define _MVP_DEBUGEN_BKPTLOOP5DONE_MASK 0x40UL /**< Bit mask for MVP_BKPTLOOP5DONE */ +#define _MVP_DEBUGEN_BKPTLOOP5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP5DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP5DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP6DONE (0x1UL << 7) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP6DONE_SHIFT 7 /**< Shift value for MVP_BKPTLOOP6DONE */ +#define _MVP_DEBUGEN_BKPTLOOP6DONE_MASK 0x80UL /**< Bit mask for MVP_BKPTLOOP6DONE */ +#define _MVP_DEBUGEN_BKPTLOOP6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP6DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP6DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP7DONE (0x1UL << 8) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP7DONE_SHIFT 8 /**< Shift value for MVP_BKPTLOOP7DONE */ +#define _MVP_DEBUGEN_BKPTLOOP7DONE_MASK 0x100UL /**< Bit mask for MVP_BKPTLOOP7DONE */ +#define _MVP_DEBUGEN_BKPTLOOP7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP7DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP7DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUNAN (0x1UL << 10) /**< Enable Breakpoint on ALUNAN */ +#define _MVP_DEBUGEN_BKPTALUNAN_SHIFT 10 /**< Shift value for MVP_BKPTALUNAN */ +#define _MVP_DEBUGEN_BKPTALUNAN_MASK 0x400UL /**< Bit mask for MVP_BKPTALUNAN */ +#define _MVP_DEBUGEN_BKPTALUNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUNAN_DEFAULT (_MVP_DEBUGEN_BKPTALUNAN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTR0POSREAL (0x1UL << 11) /**< Enable Breakpoint on R0POSREAL */ +#define _MVP_DEBUGEN_BKPTR0POSREAL_SHIFT 11 /**< Shift value for MVP_BKPTR0POSREAL */ +#define _MVP_DEBUGEN_BKPTR0POSREAL_MASK 0x800UL /**< Bit mask for MVP_BKPTR0POSREAL */ +#define _MVP_DEBUGEN_BKPTR0POSREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTR0POSREAL_DEFAULT (_MVP_DEBUGEN_BKPTR0POSREAL_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUOF (0x1UL << 12) /**< Enable Breakpoint on ALUOF */ +#define _MVP_DEBUGEN_BKPTALUOF_SHIFT 12 /**< Shift value for MVP_BKPTALUOF */ +#define _MVP_DEBUGEN_BKPTALUOF_MASK 0x1000UL /**< Bit mask for MVP_BKPTALUOF */ +#define _MVP_DEBUGEN_BKPTALUOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUOF_DEFAULT (_MVP_DEBUGEN_BKPTALUOF_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUUF (0x1UL << 13) /**< Enable Breakpoint on ALUUF */ +#define _MVP_DEBUGEN_BKPTALUUF_SHIFT 13 /**< Shift value for MVP_BKPTALUUF */ +#define _MVP_DEBUGEN_BKPTALUUF_MASK 0x2000UL /**< Bit mask for MVP_BKPTALUUF */ +#define _MVP_DEBUGEN_BKPTALUUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUUF_DEFAULT (_MVP_DEBUGEN_BKPTALUUF_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTOF (0x1UL << 14) /**< Enable Breakpoint on STORECONVERTOF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTOF_SHIFT 14 /**< Shift value for MVP_BKPTSTORECONVERTOF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTOF_MASK 0x4000UL /**< Bit mask for MVP_BKPTSTORECONVERTOF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTOF_DEFAULT (_MVP_DEBUGEN_BKPTSTORECONVERTOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTUF (0x1UL << 15) /**< Enable Breakpoint on STORECONVERTUF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTUF_SHIFT 15 /**< Shift value for MVP_BKPTSTORECONVERTUF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTUF_MASK 0x8000UL /**< Bit mask for MVP_BKPTSTORECONVERTUF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTUF_DEFAULT (_MVP_DEBUGEN_BKPTSTORECONVERTUF_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTINF (0x1UL << 16) /**< Enable Breakpoint on STORECONVERTINF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTINF_SHIFT 16 /**< Shift value for MVP_BKPTSTORECONVERTINF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTINF_MASK 0x10000UL /**< Bit mask for MVP_BKPTSTORECONVERTINF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTINF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTINF_DEFAULT (_MVP_DEBUGEN_BKPTSTORECONVERTINF_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTNAN (0x1UL << 17) /**< Enable Breakpoint on STORECONVERTNAN */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTNAN_SHIFT 17 /**< Shift value for MVP_BKPTSTORECONVERTNAN */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTNAN_MASK 0x20000UL /**< Bit mask for MVP_BKPTSTORECONVERTNAN */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTNAN_DEFAULT (_MVP_DEBUGEN_BKPTSTORECONVERTNAN_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGSTEPCNTEN (0x1UL << 28) /**< Debug Step Count Enable */ +#define _MVP_DEBUGEN_DEBUGSTEPCNTEN_SHIFT 28 /**< Shift value for MVP_DEBUGSTEPCNTEN */ +#define _MVP_DEBUGEN_DEBUGSTEPCNTEN_MASK 0x10000000UL /**< Bit mask for MVP_DEBUGSTEPCNTEN */ +#define _MVP_DEBUGEN_DEBUGSTEPCNTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGSTEPCNTEN_DEFAULT (_MVP_DEBUGEN_DEBUGSTEPCNTEN_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGBKPTALLEN (0x1UL << 29) /**< Trigger Breakpoint when ALL conditions match*/ +#define _MVP_DEBUGEN_DEBUGBKPTALLEN_SHIFT 29 /**< Shift value for MVP_DEBUGBKPTALLEN */ +#define _MVP_DEBUGEN_DEBUGBKPTALLEN_MASK 0x20000000UL /**< Bit mask for MVP_DEBUGBKPTALLEN */ +#define _MVP_DEBUGEN_DEBUGBKPTALLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGBKPTALLEN_DEFAULT (_MVP_DEBUGEN_DEBUGBKPTALLEN_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGBKPTANYEN (0x1UL << 30) /**< Enable Breakpoint when ANY conditions match */ +#define _MVP_DEBUGEN_DEBUGBKPTANYEN_SHIFT 30 /**< Shift value for MVP_DEBUGBKPTANYEN */ +#define _MVP_DEBUGEN_DEBUGBKPTANYEN_MASK 0x40000000UL /**< Bit mask for MVP_DEBUGBKPTANYEN */ +#define _MVP_DEBUGEN_DEBUGBKPTANYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGBKPTANYEN_DEFAULT (_MVP_DEBUGEN_DEBUGBKPTANYEN_DEFAULT << 30) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ + +/* Bit fields for MVP DEBUGSTEPCNT */ +#define _MVP_DEBUGSTEPCNT_RESETVALUE 0x00000000UL /**< Default value for MVP_DEBUGSTEPCNT */ +#define _MVP_DEBUGSTEPCNT_MASK 0x00FFFFFFUL /**< Mask for MVP_DEBUGSTEPCNT */ +#define _MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_SHIFT 0 /**< Shift value for MVP_DEBUGSTEPCNT */ +#define _MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_MASK 0xFFFFFFUL /**< Bit mask for MVP_DEBUGSTEPCNT */ +#define _MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGSTEPCNT */ +#define MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_DEFAULT (_MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_DEBUGSTEPCNT */ + +/** @} End of group BGM24_MVP_BitFields */ +/** @} End of group BGM24_MVP */ +/** @} End of group Parts */ + +#endif /* BGM24_MVP_H */ diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_prs_signals.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_prs_signals.h index 5e86a87ddb..6054e20e0d 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_prs_signals.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_prs_signals.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef BGM24_PRS_SIGNALS_H +#define BGM24_PRS_SIGNALS_H + /** Synchronous signal sources enumeration: */ #define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) #define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) @@ -969,3 +972,5 @@ #define PRS_LFRCO_CALMEAS (PRS_ASYNC_LFRCO_CALMEAS) #define PRS_LFRCO_SDM (PRS_ASYNC_LFRCO_SDM) #define PRS_LFRCO_TCMEAS (PRS_ASYNC_LFRCO_TCMEAS) + +#endif /* BGM24_PRS_SIGNALS_H */ diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_smu.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_smu.h index 8bfa7d12ba..885adccc1a 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_smu.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_smu.h @@ -555,6 +555,11 @@ typedef struct { #define _SMU_PPUPATD1_SEMAILBOX_MASK 0x80000UL /**< Bit mask for SMU_SEMAILBOX */ #define _SMU_PPUPATD1_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_SEMAILBOX_DEFAULT (_SMU_PPUPATD1_SEMAILBOX_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_MVP (0x1UL << 20) /**< MVP Privileged Access */ +#define _SMU_PPUPATD1_MVP_SHIFT 20 /**< Shift value for SMU_MVP */ +#define _SMU_PPUPATD1_MVP_MASK 0x100000UL /**< Bit mask for SMU_MVP */ +#define _SMU_PPUPATD1_MVP_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_MVP_DEFAULT (_SMU_PPUPATD1_MVP_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ #define SMU_PPUPATD1_AHBRADIO (0x1UL << 21) /**< AHBRADIO Privileged Access */ #define _SMU_PPUPATD1_AHBRADIO_SHIFT 21 /**< Shift value for SMU_AHBRADIO */ #define _SMU_PPUPATD1_AHBRADIO_MASK 0x200000UL /**< Bit mask for SMU_AHBRADIO */ @@ -823,6 +828,11 @@ typedef struct { #define _SMU_PPUSATD1_SEMAILBOX_MASK 0x80000UL /**< Bit mask for SMU_SEMAILBOX */ #define _SMU_PPUSATD1_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ #define SMU_PPUSATD1_SEMAILBOX_DEFAULT (_SMU_PPUSATD1_SEMAILBOX_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_MVP (0x1UL << 20) /**< MVP Secure Access */ +#define _SMU_PPUSATD1_MVP_SHIFT 20 /**< Shift value for SMU_MVP */ +#define _SMU_PPUSATD1_MVP_MASK 0x100000UL /**< Bit mask for SMU_MVP */ +#define _SMU_PPUSATD1_MVP_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_MVP_DEFAULT (_SMU_PPUSATD1_MVP_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ #define SMU_PPUSATD1_AHBRADIO (0x1UL << 21) /**< AHBRADIO Secure Access */ #define _SMU_PPUSATD1_AHBRADIO_SHIFT 21 /**< Shift value for SMU_AHBRADIO */ #define _SMU_PPUSATD1_AHBRADIO_MASK 0x200000UL /**< Bit mask for SMU_AHBRADIO */ @@ -855,6 +865,21 @@ typedef struct { #define _SMU_BMPUPATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ #define _SMU_BMPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ #define SMU_BMPUPATD0_LDMA_DEFAULT (_SMU_BMPUPATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_MVPAHBDATA0 (0x1UL << 3) /**< MVPAHBDATA0 privileged mode */ +#define _SMU_BMPUPATD0_MVPAHBDATA0_SHIFT 3 /**< Shift value for SMU_MVPAHBDATA0 */ +#define _SMU_BMPUPATD0_MVPAHBDATA0_MASK 0x8UL /**< Bit mask for SMU_MVPAHBDATA0 */ +#define _SMU_BMPUPATD0_MVPAHBDATA0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_MVPAHBDATA0_DEFAULT (_SMU_BMPUPATD0_MVPAHBDATA0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_MVPAHBDATA1 (0x1UL << 4) /**< MVPAHBDATA1 privileged mode */ +#define _SMU_BMPUPATD0_MVPAHBDATA1_SHIFT 4 /**< Shift value for SMU_MVPAHBDATA1 */ +#define _SMU_BMPUPATD0_MVPAHBDATA1_MASK 0x10UL /**< Bit mask for SMU_MVPAHBDATA1 */ +#define _SMU_BMPUPATD0_MVPAHBDATA1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_MVPAHBDATA1_DEFAULT (_SMU_BMPUPATD0_MVPAHBDATA1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_MVPAHBDATA2 (0x1UL << 5) /**< MVPAHBDATA2 privileged mode */ +#define _SMU_BMPUPATD0_MVPAHBDATA2_SHIFT 5 /**< Shift value for SMU_MVPAHBDATA2 */ +#define _SMU_BMPUPATD0_MVPAHBDATA2_MASK 0x20UL /**< Bit mask for SMU_MVPAHBDATA2 */ +#define _SMU_BMPUPATD0_MVPAHBDATA2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_MVPAHBDATA2_DEFAULT (_SMU_BMPUPATD0_MVPAHBDATA2_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ #define SMU_BMPUPATD0_RFECA0 (0x1UL << 6) /**< RFECA0 privileged mode */ #define _SMU_BMPUPATD0_RFECA0_SHIFT 6 /**< Shift value for SMU_RFECA0 */ #define _SMU_BMPUPATD0_RFECA0_MASK 0x40UL /**< Bit mask for SMU_RFECA0 */ @@ -889,6 +914,21 @@ typedef struct { #define _SMU_BMPUSATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ #define _SMU_BMPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ #define SMU_BMPUSATD0_LDMA_DEFAULT (_SMU_BMPUSATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_MVPAHBDATA0 (0x1UL << 3) /**< MVPAHBDATA0 secure mode */ +#define _SMU_BMPUSATD0_MVPAHBDATA0_SHIFT 3 /**< Shift value for SMU_MVPAHBDATA0 */ +#define _SMU_BMPUSATD0_MVPAHBDATA0_MASK 0x8UL /**< Bit mask for SMU_MVPAHBDATA0 */ +#define _SMU_BMPUSATD0_MVPAHBDATA0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_MVPAHBDATA0_DEFAULT (_SMU_BMPUSATD0_MVPAHBDATA0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_MVPAHBDATA1 (0x1UL << 4) /**< MVPAHBDATA1 secure mode */ +#define _SMU_BMPUSATD0_MVPAHBDATA1_SHIFT 4 /**< Shift value for SMU_MVPAHBDATA1 */ +#define _SMU_BMPUSATD0_MVPAHBDATA1_MASK 0x10UL /**< Bit mask for SMU_MVPAHBDATA1 */ +#define _SMU_BMPUSATD0_MVPAHBDATA1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_MVPAHBDATA1_DEFAULT (_SMU_BMPUSATD0_MVPAHBDATA1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_MVPAHBDATA2 (0x1UL << 5) /**< MVPAHBDATA2 secure mode */ +#define _SMU_BMPUSATD0_MVPAHBDATA2_SHIFT 5 /**< Shift value for SMU_MVPAHBDATA2 */ +#define _SMU_BMPUSATD0_MVPAHBDATA2_MASK 0x20UL /**< Bit mask for SMU_MVPAHBDATA2 */ +#define _SMU_BMPUSATD0_MVPAHBDATA2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_MVPAHBDATA2_DEFAULT (_SMU_BMPUSATD0_MVPAHBDATA2_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ #define SMU_BMPUSATD0_RFECA0 (0x1UL << 6) /**< RFECA0 secure mode */ #define _SMU_BMPUSATD0_RFECA0_SHIFT 6 /**< Shift value for SMU_RFECA0 */ #define _SMU_BMPUSATD0_RFECA0_MASK 0x40UL /**< Bit mask for SMU_RFECA0 */ diff --git a/platform/Device/SiliconLabs/BGM24/Include/bgm24_syscfg.h b/platform/Device/SiliconLabs/BGM24/Include/bgm24_syscfg.h index cc698d109b..e8c7ce8c99 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/bgm24_syscfg.h +++ b/platform/Device/SiliconLabs/BGM24/Include/bgm24_syscfg.h @@ -185,488 +185,500 @@ typedef struct { *****************************************************************************/ /* Bit fields for SYSCFG IPVERSION */ -#define _SYSCFG_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for SYSCFG_IPVERSION */ -#define _SYSCFG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_IPVERSION */ -#define _SYSCFG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SYSCFG_IPVERSION */ -#define _SYSCFG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_IPVERSION */ -#define _SYSCFG_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for SYSCFG_IPVERSION */ -#define SYSCFG_IPVERSION_IPVERSION_DEFAULT (_SYSCFG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for SYSCFG_IPVERSION */ +#define SYSCFG_IPVERSION_IPVERSION_DEFAULT (_SYSCFG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IPVERSION */ /* Bit fields for SYSCFG IF */ -#define _SYSCFG_IF_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IF */ -#define _SYSCFG_IF_MASK 0x33033F0FUL /**< Mask for SYSCFG_IF */ -#define SYSCFG_IF_SW0 (0x1UL << 0) /**< Software Interrupt Flag */ -#define _SYSCFG_IF_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ -#define _SYSCFG_IF_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ -#define _SYSCFG_IF_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SW0_DEFAULT (_SYSCFG_IF_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SW1 (0x1UL << 1) /**< Software Interrupt Flag */ -#define _SYSCFG_IF_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ -#define _SYSCFG_IF_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ -#define _SYSCFG_IF_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SW1_DEFAULT (_SYSCFG_IF_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SW2 (0x1UL << 2) /**< Software Interrupt Flag */ -#define _SYSCFG_IF_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ -#define _SYSCFG_IF_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ -#define _SYSCFG_IF_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SW2_DEFAULT (_SYSCFG_IF_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SW3 (0x1UL << 3) /**< Software Interrupt Flag */ -#define _SYSCFG_IF_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ -#define _SYSCFG_IF_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ -#define _SYSCFG_IF_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SW3_DEFAULT (_SYSCFG_IF_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FPIOC (0x1UL << 8) /**< FPU Invalid Operation interrupt flag */ -#define _SYSCFG_IF_FPIOC_SHIFT 8 /**< Shift value for SYSCFG_FPIOC */ -#define _SYSCFG_IF_FPIOC_MASK 0x100UL /**< Bit mask for SYSCFG_FPIOC */ -#define _SYSCFG_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FPIOC_DEFAULT (_SYSCFG_IF_FPIOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FPDZC (0x1UL << 9) /**< FPU Divide by zero interrupt flag */ -#define _SYSCFG_IF_FPDZC_SHIFT 9 /**< Shift value for SYSCFG_FPDZC */ -#define _SYSCFG_IF_FPDZC_MASK 0x200UL /**< Bit mask for SYSCFG_FPDZC */ -#define _SYSCFG_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FPDZC_DEFAULT (_SYSCFG_IF_FPDZC_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FPUFC (0x1UL << 10) /**< FPU Underflow interrupt flag */ -#define _SYSCFG_IF_FPUFC_SHIFT 10 /**< Shift value for SYSCFG_FPUFC */ -#define _SYSCFG_IF_FPUFC_MASK 0x400UL /**< Bit mask for SYSCFG_FPUFC */ -#define _SYSCFG_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FPUFC_DEFAULT (_SYSCFG_IF_FPUFC_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FPOFC (0x1UL << 11) /**< FPU Overflow interrupt flag */ -#define _SYSCFG_IF_FPOFC_SHIFT 11 /**< Shift value for SYSCFG_FPOFC */ -#define _SYSCFG_IF_FPOFC_MASK 0x800UL /**< Bit mask for SYSCFG_FPOFC */ -#define _SYSCFG_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FPOFC_DEFAULT (_SYSCFG_IF_FPOFC_DEFAULT << 11) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FPIDC (0x1UL << 12) /**< FPU Input denormal interrupt flag */ -#define _SYSCFG_IF_FPIDC_SHIFT 12 /**< Shift value for SYSCFG_FPIDC */ -#define _SYSCFG_IF_FPIDC_MASK 0x1000UL /**< Bit mask for SYSCFG_FPIDC */ -#define _SYSCFG_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FPIDC_DEFAULT (_SYSCFG_IF_FPIDC_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FPIXC (0x1UL << 13) /**< FPU Inexact interrupt flag */ -#define _SYSCFG_IF_FPIXC_SHIFT 13 /**< Shift value for SYSCFG_FPIXC */ -#define _SYSCFG_IF_FPIXC_MASK 0x2000UL /**< Bit mask for SYSCFG_FPIXC */ -#define _SYSCFG_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FPIXC_DEFAULT (_SYSCFG_IF_FPIXC_DEFAULT << 13) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_HOST2SRWBUSERR (0x1UL << 16) /**< HOST2SRWBUSERRIF Interrupt Flag */ -#define _SYSCFG_IF_HOST2SRWBUSERR_SHIFT 16 /**< Shift value for SYSCFG_HOST2SRWBUSERR */ -#define _SYSCFG_IF_HOST2SRWBUSERR_MASK 0x10000UL /**< Bit mask for SYSCFG_HOST2SRWBUSERR */ -#define _SYSCFG_IF_HOST2SRWBUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_HOST2SRWBUSERR_DEFAULT (_SYSCFG_IF_HOST2SRWBUSERR_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SRW2HOSTBUSERR (0x1UL << 17) /**< SRW2HOSTBUSERRIF Interrupt Flag */ -#define _SYSCFG_IF_SRW2HOSTBUSERR_SHIFT 17 /**< Shift value for SYSCFG_SRW2HOSTBUSERR */ -#define _SYSCFG_IF_SRW2HOSTBUSERR_MASK 0x20000UL /**< Bit mask for SYSCFG_SRW2HOSTBUSERR */ -#define _SYSCFG_IF_SRW2HOSTBUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SRW2HOSTBUSERR_DEFAULT (_SYSCFG_IF_SRW2HOSTBUSERR_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM Error 1-bit Interrupt Flag */ -#define _SYSCFG_IF_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ -#define _SYSCFG_IF_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ -#define _SYSCFG_IF_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SEQRAMERR1B_DEFAULT (_SYSCFG_IF_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM Error 2-bit Interrupt Flag */ -#define _SYSCFG_IF_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ -#define _SYSCFG_IF_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ -#define _SYSCFG_IF_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SEQRAMERR2B_DEFAULT (_SYSCFG_IF_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM Error 1-bit Interrupt Flag */ -#define _SYSCFG_IF_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */ -#define _SYSCFG_IF_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */ -#define _SYSCFG_IF_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FRCRAMERR1B_DEFAULT (_SYSCFG_IF_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM Error 2-bit Interrupt Flag */ -#define _SYSCFG_IF_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */ -#define _SYSCFG_IF_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */ -#define _SYSCFG_IF_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FRCRAMERR2B_DEFAULT (_SYSCFG_IF_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define _SYSCFG_IF_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IF */ +#define _SYSCFG_IF_MASK 0x33033F0FUL /**< Mask for SYSCFG_IF */ +#define SYSCFG_IF_SW0 (0x1UL << 0) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ +#define _SYSCFG_IF_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ +#define _SYSCFG_IF_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW0_DEFAULT (_SYSCFG_IF_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW1 (0x1UL << 1) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ +#define _SYSCFG_IF_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ +#define _SYSCFG_IF_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW1_DEFAULT (_SYSCFG_IF_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW2 (0x1UL << 2) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ +#define _SYSCFG_IF_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ +#define _SYSCFG_IF_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW2_DEFAULT (_SYSCFG_IF_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW3 (0x1UL << 3) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ +#define _SYSCFG_IF_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ +#define _SYSCFG_IF_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW3_DEFAULT (_SYSCFG_IF_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIOC (0x1UL << 8) /**< FPU Invalid Operation interrupt flag */ +#define _SYSCFG_IF_FPIOC_SHIFT 8 /**< Shift value for SYSCFG_FPIOC */ +#define _SYSCFG_IF_FPIOC_MASK 0x100UL /**< Bit mask for SYSCFG_FPIOC */ +#define _SYSCFG_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIOC_DEFAULT (_SYSCFG_IF_FPIOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPDZC (0x1UL << 9) /**< FPU Divide by zero interrupt flag */ +#define _SYSCFG_IF_FPDZC_SHIFT 9 /**< Shift value for SYSCFG_FPDZC */ +#define _SYSCFG_IF_FPDZC_MASK 0x200UL /**< Bit mask for SYSCFG_FPDZC */ +#define _SYSCFG_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPDZC_DEFAULT (_SYSCFG_IF_FPDZC_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPUFC (0x1UL << 10) /**< FPU Underflow interrupt flag */ +#define _SYSCFG_IF_FPUFC_SHIFT 10 /**< Shift value for SYSCFG_FPUFC */ +#define _SYSCFG_IF_FPUFC_MASK 0x400UL /**< Bit mask for SYSCFG_FPUFC */ +#define _SYSCFG_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPUFC_DEFAULT (_SYSCFG_IF_FPUFC_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPOFC (0x1UL << 11) /**< FPU Overflow interrupt flag */ +#define _SYSCFG_IF_FPOFC_SHIFT 11 /**< Shift value for SYSCFG_FPOFC */ +#define _SYSCFG_IF_FPOFC_MASK 0x800UL /**< Bit mask for SYSCFG_FPOFC */ +#define _SYSCFG_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPOFC_DEFAULT (_SYSCFG_IF_FPOFC_DEFAULT << 11) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIDC (0x1UL << 12) /**< FPU Input denormal interrupt flag */ +#define _SYSCFG_IF_FPIDC_SHIFT 12 /**< Shift value for SYSCFG_FPIDC */ +#define _SYSCFG_IF_FPIDC_MASK 0x1000UL /**< Bit mask for SYSCFG_FPIDC */ +#define _SYSCFG_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIDC_DEFAULT (_SYSCFG_IF_FPIDC_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIXC (0x1UL << 13) /**< FPU Inexact interrupt flag */ +#define _SYSCFG_IF_FPIXC_SHIFT 13 /**< Shift value for SYSCFG_FPIXC */ +#define _SYSCFG_IF_FPIXC_MASK 0x2000UL /**< Bit mask for SYSCFG_FPIXC */ +#define _SYSCFG_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIXC_DEFAULT (_SYSCFG_IF_FPIXC_DEFAULT << 13) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_HOST2SRWBUSERR (0x1UL << 16) /**< HOST2SRWBUSERRIF Interrupt Flag */ +#define _SYSCFG_IF_HOST2SRWBUSERR_SHIFT 16 /**< Shift value for SYSCFG_HOST2SRWBUSERR */ +#define _SYSCFG_IF_HOST2SRWBUSERR_MASK 0x10000UL /**< Bit mask for SYSCFG_HOST2SRWBUSERR */ +#define _SYSCFG_IF_HOST2SRWBUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_HOST2SRWBUSERR_DEFAULT (_SYSCFG_IF_HOST2SRWBUSERR_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SRW2HOSTBUSERR (0x1UL << 17) /**< SRW2HOSTBUSERRIF Interrupt Flag */ +#define _SYSCFG_IF_SRW2HOSTBUSERR_SHIFT 17 /**< Shift value for SYSCFG_SRW2HOSTBUSERR */ +#define _SYSCFG_IF_SRW2HOSTBUSERR_MASK 0x20000UL /**< Bit mask for SYSCFG_SRW2HOSTBUSERR */ +#define _SYSCFG_IF_SRW2HOSTBUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SRW2HOSTBUSERR_DEFAULT (_SYSCFG_IF_SRW2HOSTBUSERR_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM Error 1-bit Interrupt Flag */ +#define _SYSCFG_IF_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IF_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IF_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR1B_DEFAULT (_SYSCFG_IF_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM Error 2-bit Interrupt Flag */ +#define _SYSCFG_IF_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IF_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IF_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR2B_DEFAULT (_SYSCFG_IF_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM Error 1-bit Interrupt Flag */ +#define _SYSCFG_IF_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IF_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IF_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR1B_DEFAULT (_SYSCFG_IF_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM Error 2-bit Interrupt Flag */ +#define _SYSCFG_IF_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IF_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IF_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR2B_DEFAULT (_SYSCFG_IF_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IF */ /* Bit fields for SYSCFG IEN */ -#define _SYSCFG_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IEN */ -#define _SYSCFG_IEN_MASK 0x33033F0FUL /**< Mask for SYSCFG_IEN */ -#define SYSCFG_IEN_SW0 (0x1UL << 0) /**< Software Interrupt Enable */ -#define _SYSCFG_IEN_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ -#define _SYSCFG_IEN_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ -#define _SYSCFG_IEN_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SW0_DEFAULT (_SYSCFG_IEN_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SW1 (0x1UL << 1) /**< Software Interrupt Enable */ -#define _SYSCFG_IEN_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ -#define _SYSCFG_IEN_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ -#define _SYSCFG_IEN_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SW1_DEFAULT (_SYSCFG_IEN_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SW2 (0x1UL << 2) /**< Software Interrupt Enable */ -#define _SYSCFG_IEN_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ -#define _SYSCFG_IEN_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ -#define _SYSCFG_IEN_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SW2_DEFAULT (_SYSCFG_IEN_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SW3 (0x1UL << 3) /**< Software Interrupt Enable */ -#define _SYSCFG_IEN_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ -#define _SYSCFG_IEN_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ -#define _SYSCFG_IEN_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SW3_DEFAULT (_SYSCFG_IEN_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FPIOC (0x1UL << 8) /**< FPU Invalid Operation Interrupt Enable */ -#define _SYSCFG_IEN_FPIOC_SHIFT 8 /**< Shift value for SYSCFG_FPIOC */ -#define _SYSCFG_IEN_FPIOC_MASK 0x100UL /**< Bit mask for SYSCFG_FPIOC */ -#define _SYSCFG_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FPIOC_DEFAULT (_SYSCFG_IEN_FPIOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FPDZC (0x1UL << 9) /**< FPU Divide by zero Interrupt Enable */ -#define _SYSCFG_IEN_FPDZC_SHIFT 9 /**< Shift value for SYSCFG_FPDZC */ -#define _SYSCFG_IEN_FPDZC_MASK 0x200UL /**< Bit mask for SYSCFG_FPDZC */ -#define _SYSCFG_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FPDZC_DEFAULT (_SYSCFG_IEN_FPDZC_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FPUFC (0x1UL << 10) /**< FPU Underflow Interrupt Enable */ -#define _SYSCFG_IEN_FPUFC_SHIFT 10 /**< Shift value for SYSCFG_FPUFC */ -#define _SYSCFG_IEN_FPUFC_MASK 0x400UL /**< Bit mask for SYSCFG_FPUFC */ -#define _SYSCFG_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FPUFC_DEFAULT (_SYSCFG_IEN_FPUFC_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FPOFC (0x1UL << 11) /**< FPU Overflow Interrupt Enable */ -#define _SYSCFG_IEN_FPOFC_SHIFT 11 /**< Shift value for SYSCFG_FPOFC */ -#define _SYSCFG_IEN_FPOFC_MASK 0x800UL /**< Bit mask for SYSCFG_FPOFC */ -#define _SYSCFG_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FPOFC_DEFAULT (_SYSCFG_IEN_FPOFC_DEFAULT << 11) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FPIDC (0x1UL << 12) /**< FPU Input denormal Interrupt Enable */ -#define _SYSCFG_IEN_FPIDC_SHIFT 12 /**< Shift value for SYSCFG_FPIDC */ -#define _SYSCFG_IEN_FPIDC_MASK 0x1000UL /**< Bit mask for SYSCFG_FPIDC */ -#define _SYSCFG_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FPIDC_DEFAULT (_SYSCFG_IEN_FPIDC_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FPIXC (0x1UL << 13) /**< FPU Inexact Interrupt Enable */ -#define _SYSCFG_IEN_FPIXC_SHIFT 13 /**< Shift value for SYSCFG_FPIXC */ -#define _SYSCFG_IEN_FPIXC_MASK 0x2000UL /**< Bit mask for SYSCFG_FPIXC */ -#define _SYSCFG_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FPIXC_DEFAULT (_SYSCFG_IEN_FPIXC_DEFAULT << 13) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_HOST2SRWBUSERR (0x1UL << 16) /**< HOST2SRWBUSERRIEN Interrupt Enable */ -#define _SYSCFG_IEN_HOST2SRWBUSERR_SHIFT 16 /**< Shift value for SYSCFG_HOST2SRWBUSERR */ -#define _SYSCFG_IEN_HOST2SRWBUSERR_MASK 0x10000UL /**< Bit mask for SYSCFG_HOST2SRWBUSERR */ -#define _SYSCFG_IEN_HOST2SRWBUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_HOST2SRWBUSERR_DEFAULT (_SYSCFG_IEN_HOST2SRWBUSERR_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SRW2HOSTBUSERR (0x1UL << 17) /**< SRW2HOSTBUSERRIEN Interrupt Enable */ -#define _SYSCFG_IEN_SRW2HOSTBUSERR_SHIFT 17 /**< Shift value for SYSCFG_SRW2HOSTBUSERR */ -#define _SYSCFG_IEN_SRW2HOSTBUSERR_MASK 0x20000UL /**< Bit mask for SYSCFG_SRW2HOSTBUSERR */ -#define _SYSCFG_IEN_SRW2HOSTBUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SRW2HOSTBUSERR_DEFAULT (_SYSCFG_IEN_SRW2HOSTBUSERR_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM Error 1-bit Interrupt Enable */ -#define _SYSCFG_IEN_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ -#define _SYSCFG_IEN_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ -#define _SYSCFG_IEN_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SEQRAMERR1B_DEFAULT (_SYSCFG_IEN_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM Error 2-bit Interrupt Enable */ -#define _SYSCFG_IEN_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ -#define _SYSCFG_IEN_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ -#define _SYSCFG_IEN_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SEQRAMERR2B_DEFAULT (_SYSCFG_IEN_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM Error 1-bit Interrupt Enable */ -#define _SYSCFG_IEN_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */ -#define _SYSCFG_IEN_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */ -#define _SYSCFG_IEN_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FRCRAMERR1B_DEFAULT (_SYSCFG_IEN_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM Error 2-bit Interrupt Enable */ -#define _SYSCFG_IEN_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */ -#define _SYSCFG_IEN_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */ -#define _SYSCFG_IEN_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FRCRAMERR2B_DEFAULT (_SYSCFG_IEN_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define _SYSCFG_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IEN */ +#define _SYSCFG_IEN_MASK 0x33033F0FUL /**< Mask for SYSCFG_IEN */ +#define SYSCFG_IEN_SW0 (0x1UL << 0) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ +#define _SYSCFG_IEN_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ +#define _SYSCFG_IEN_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW0_DEFAULT (_SYSCFG_IEN_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW1 (0x1UL << 1) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ +#define _SYSCFG_IEN_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ +#define _SYSCFG_IEN_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW1_DEFAULT (_SYSCFG_IEN_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW2 (0x1UL << 2) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ +#define _SYSCFG_IEN_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ +#define _SYSCFG_IEN_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW2_DEFAULT (_SYSCFG_IEN_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW3 (0x1UL << 3) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ +#define _SYSCFG_IEN_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ +#define _SYSCFG_IEN_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW3_DEFAULT (_SYSCFG_IEN_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIOC (0x1UL << 8) /**< FPU Invalid Operation Interrupt Enable */ +#define _SYSCFG_IEN_FPIOC_SHIFT 8 /**< Shift value for SYSCFG_FPIOC */ +#define _SYSCFG_IEN_FPIOC_MASK 0x100UL /**< Bit mask for SYSCFG_FPIOC */ +#define _SYSCFG_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIOC_DEFAULT (_SYSCFG_IEN_FPIOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPDZC (0x1UL << 9) /**< FPU Divide by zero Interrupt Enable */ +#define _SYSCFG_IEN_FPDZC_SHIFT 9 /**< Shift value for SYSCFG_FPDZC */ +#define _SYSCFG_IEN_FPDZC_MASK 0x200UL /**< Bit mask for SYSCFG_FPDZC */ +#define _SYSCFG_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPDZC_DEFAULT (_SYSCFG_IEN_FPDZC_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPUFC (0x1UL << 10) /**< FPU Underflow Interrupt Enable */ +#define _SYSCFG_IEN_FPUFC_SHIFT 10 /**< Shift value for SYSCFG_FPUFC */ +#define _SYSCFG_IEN_FPUFC_MASK 0x400UL /**< Bit mask for SYSCFG_FPUFC */ +#define _SYSCFG_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPUFC_DEFAULT (_SYSCFG_IEN_FPUFC_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPOFC (0x1UL << 11) /**< FPU Overflow Interrupt Enable */ +#define _SYSCFG_IEN_FPOFC_SHIFT 11 /**< Shift value for SYSCFG_FPOFC */ +#define _SYSCFG_IEN_FPOFC_MASK 0x800UL /**< Bit mask for SYSCFG_FPOFC */ +#define _SYSCFG_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPOFC_DEFAULT (_SYSCFG_IEN_FPOFC_DEFAULT << 11) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIDC (0x1UL << 12) /**< FPU Input denormal Interrupt Enable */ +#define _SYSCFG_IEN_FPIDC_SHIFT 12 /**< Shift value for SYSCFG_FPIDC */ +#define _SYSCFG_IEN_FPIDC_MASK 0x1000UL /**< Bit mask for SYSCFG_FPIDC */ +#define _SYSCFG_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIDC_DEFAULT (_SYSCFG_IEN_FPIDC_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIXC (0x1UL << 13) /**< FPU Inexact Interrupt Enable */ +#define _SYSCFG_IEN_FPIXC_SHIFT 13 /**< Shift value for SYSCFG_FPIXC */ +#define _SYSCFG_IEN_FPIXC_MASK 0x2000UL /**< Bit mask for SYSCFG_FPIXC */ +#define _SYSCFG_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIXC_DEFAULT (_SYSCFG_IEN_FPIXC_DEFAULT << 13) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_HOST2SRWBUSERR (0x1UL << 16) /**< HOST2SRWBUSERRIEN Interrupt Enable */ +#define _SYSCFG_IEN_HOST2SRWBUSERR_SHIFT 16 /**< Shift value for SYSCFG_HOST2SRWBUSERR */ +#define _SYSCFG_IEN_HOST2SRWBUSERR_MASK 0x10000UL /**< Bit mask for SYSCFG_HOST2SRWBUSERR */ +#define _SYSCFG_IEN_HOST2SRWBUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_HOST2SRWBUSERR_DEFAULT (_SYSCFG_IEN_HOST2SRWBUSERR_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SRW2HOSTBUSERR (0x1UL << 17) /**< SRW2HOSTBUSERRIEN Interrupt Enable */ +#define _SYSCFG_IEN_SRW2HOSTBUSERR_SHIFT 17 /**< Shift value for SYSCFG_SRW2HOSTBUSERR */ +#define _SYSCFG_IEN_SRW2HOSTBUSERR_MASK 0x20000UL /**< Bit mask for SYSCFG_SRW2HOSTBUSERR */ +#define _SYSCFG_IEN_SRW2HOSTBUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SRW2HOSTBUSERR_DEFAULT (_SYSCFG_IEN_SRW2HOSTBUSERR_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM Error 1-bit Interrupt Enable */ +#define _SYSCFG_IEN_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IEN_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IEN_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR1B_DEFAULT (_SYSCFG_IEN_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM Error 2-bit Interrupt Enable */ +#define _SYSCFG_IEN_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IEN_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IEN_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR2B_DEFAULT (_SYSCFG_IEN_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM Error 1-bit Interrupt Enable */ +#define _SYSCFG_IEN_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IEN_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IEN_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR1B_DEFAULT (_SYSCFG_IEN_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM Error 2-bit Interrupt Enable */ +#define _SYSCFG_IEN_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IEN_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IEN_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR2B_DEFAULT (_SYSCFG_IEN_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IEN */ /* Bit fields for SYSCFG CHIPREVHW */ -#define _SYSCFG_CHIPREVHW_RESETVALUE 0x00000C01UL /**< Default value for SYSCFG_CHIPREVHW */ -#define _SYSCFG_CHIPREVHW_MASK 0xFF0FFFFFUL /**< Mask for SYSCFG_CHIPREVHW */ -#define _SYSCFG_CHIPREVHW_MAJOR_SHIFT 0 /**< Shift value for SYSCFG_MAJOR */ -#define _SYSCFG_CHIPREVHW_MAJOR_MASK 0x3FUL /**< Bit mask for SYSCFG_MAJOR */ -#define _SYSCFG_CHIPREVHW_MAJOR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ -#define SYSCFG_CHIPREVHW_MAJOR_DEFAULT (_SYSCFG_CHIPREVHW_MAJOR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ -#define _SYSCFG_CHIPREVHW_FAMILY_SHIFT 6 /**< Shift value for SYSCFG_FAMILY */ -#define _SYSCFG_CHIPREVHW_FAMILY_MASK 0xFC0UL /**< Bit mask for SYSCFG_FAMILY */ -#define _SYSCFG_CHIPREVHW_FAMILY_DEFAULT 0x00000030UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ -#define SYSCFG_CHIPREVHW_FAMILY_DEFAULT (_SYSCFG_CHIPREVHW_FAMILY_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ -#define _SYSCFG_CHIPREVHW_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ -#define _SYSCFG_CHIPREVHW_MINOR_MASK 0xFF000UL /**< Bit mask for SYSCFG_MINOR */ -#define _SYSCFG_CHIPREVHW_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ -#define SYSCFG_CHIPREVHW_MINOR_DEFAULT (_SYSCFG_CHIPREVHW_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_RESETVALUE 0x00000C01UL /**< Default value for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_MASK 0xFF0FFFFFUL /**< Mask for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_MAJOR_SHIFT 0 /**< Shift value for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREVHW_MAJOR_MASK 0x3FUL /**< Bit mask for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREVHW_MAJOR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ +#define SYSCFG_CHIPREVHW_MAJOR_DEFAULT (_SYSCFG_CHIPREVHW_MAJOR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_FAMILY_SHIFT 6 /**< Shift value for SYSCFG_FAMILY */ +#define _SYSCFG_CHIPREVHW_FAMILY_MASK 0xFC0UL /**< Bit mask for SYSCFG_FAMILY */ +#define _SYSCFG_CHIPREVHW_FAMILY_DEFAULT 0x00000030UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ +#define SYSCFG_CHIPREVHW_FAMILY_DEFAULT (_SYSCFG_CHIPREVHW_FAMILY_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREVHW_MINOR_MASK 0xFF000UL /**< Bit mask for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREVHW_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ +#define SYSCFG_CHIPREVHW_MINOR_DEFAULT (_SYSCFG_CHIPREVHW_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ /* Bit fields for SYSCFG CHIPREV */ -#define _SYSCFG_CHIPREV_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CHIPREV */ -#define _SYSCFG_CHIPREV_MASK 0x000FFFFFUL /**< Mask for SYSCFG_CHIPREV */ -#define _SYSCFG_CHIPREV_MAJOR_SHIFT 0 /**< Shift value for SYSCFG_MAJOR */ -#define _SYSCFG_CHIPREV_MAJOR_MASK 0x3FUL /**< Bit mask for SYSCFG_MAJOR */ -#define _SYSCFG_CHIPREV_MAJOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ -#define SYSCFG_CHIPREV_MAJOR_DEFAULT (_SYSCFG_CHIPREV_MAJOR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ -#define _SYSCFG_CHIPREV_FAMILY_SHIFT 6 /**< Shift value for SYSCFG_FAMILY */ -#define _SYSCFG_CHIPREV_FAMILY_MASK 0xFC0UL /**< Bit mask for SYSCFG_FAMILY */ -#define _SYSCFG_CHIPREV_FAMILY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ -#define SYSCFG_CHIPREV_FAMILY_DEFAULT (_SYSCFG_CHIPREV_FAMILY_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ -#define _SYSCFG_CHIPREV_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ -#define _SYSCFG_CHIPREV_MINOR_MASK 0xFF000UL /**< Bit mask for SYSCFG_MINOR */ -#define _SYSCFG_CHIPREV_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ -#define SYSCFG_CHIPREV_MINOR_DEFAULT (_SYSCFG_CHIPREV_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_MASK 0x000FFFFFUL /**< Mask for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_MAJOR_SHIFT 0 /**< Shift value for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREV_MAJOR_MASK 0x3FUL /**< Bit mask for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREV_MAJOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_MAJOR_DEFAULT (_SYSCFG_CHIPREV_MAJOR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_FAMILY_SHIFT 6 /**< Shift value for SYSCFG_FAMILY */ +#define _SYSCFG_CHIPREV_FAMILY_MASK 0xFC0UL /**< Bit mask for SYSCFG_FAMILY */ +#define _SYSCFG_CHIPREV_FAMILY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_FAMILY_DEFAULT (_SYSCFG_CHIPREV_FAMILY_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREV_MINOR_MASK 0xFF000UL /**< Bit mask for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREV_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_MINOR_DEFAULT (_SYSCFG_CHIPREV_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ /* Bit fields for SYSCFG CFGSYSTIC */ -#define _SYSCFG_CFGSYSTIC_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CFGSYSTIC */ -#define _SYSCFG_CFGSYSTIC_MASK 0x00000001UL /**< Mask for SYSCFG_CFGSYSTIC */ -#define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN (0x1UL << 0) /**< SysTick External Clock Enable */ -#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_SHIFT 0 /**< Shift value for SYSCFG_SYSTICEXTCLKEN */ -#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK 0x1UL /**< Bit mask for SYSCFG_SYSTICEXTCLKEN */ -#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGSYSTIC */ -#define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT (_SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGSYSTIC */ +#define _SYSCFG_CFGSYSTIC_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CFGSYSTIC */ +#define _SYSCFG_CFGSYSTIC_MASK 0x00000001UL /**< Mask for SYSCFG_CFGSYSTIC */ +#define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN (0x1UL << 0) /**< SysTick External Clock Enable */ +#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_SHIFT 0 /**< Shift value for SYSCFG_SYSTICEXTCLKEN */ +#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK 0x1UL /**< Bit mask for SYSCFG_SYSTICEXTCLKEN */ +#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGSYSTIC */ +#define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT (_SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGSYSTIC */ /* Bit fields for SYSCFG CTRL */ -#define _SYSCFG_CTRL_RESETVALUE 0x00000023UL /**< Default value for SYSCFG_CTRL */ -#define _SYSCFG_CTRL_MASK 0x00000023UL /**< Mask for SYSCFG_CTRL */ -#define SYSCFG_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enabl */ -#define _SYSCFG_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for SYSCFG_ADDRFAULTEN */ -#define _SYSCFG_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for SYSCFG_ADDRFAULTEN */ -#define _SYSCFG_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ -#define SYSCFG_CTRL_ADDRFAULTEN_DEFAULT (_SYSCFG_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ -#define SYSCFG_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Disabled Clkbus Bus Fault Enable */ -#define _SYSCFG_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for SYSCFG_CLKDISFAULTEN */ -#define _SYSCFG_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for SYSCFG_CLKDISFAULTEN */ -#define _SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ -#define SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT (_SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ -#define SYSCFG_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two bit ECC error bus fault response ena */ -#define _SYSCFG_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for SYSCFG_RAMECCERRFAULTEN */ -#define _SYSCFG_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for SYSCFG_RAMECCERRFAULTEN */ -#define _SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ -#define SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT (_SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ +#define _SYSCFG_CTRL_RESETVALUE 0x00000023UL /**< Default value for SYSCFG_CTRL */ +#define _SYSCFG_CTRL_MASK 0x00000023UL /**< Mask for SYSCFG_CTRL */ +#define SYSCFG_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enabl */ +#define _SYSCFG_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for SYSCFG_ADDRFAULTEN */ +#define _SYSCFG_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for SYSCFG_ADDRFAULTEN */ +#define _SYSCFG_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_ADDRFAULTEN_DEFAULT (_SYSCFG_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Disabled Clkbus Bus Fault Enable */ +#define _SYSCFG_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for SYSCFG_CLKDISFAULTEN */ +#define _SYSCFG_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for SYSCFG_CLKDISFAULTEN */ +#define _SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT (_SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two bit ECC error bus fault response ena */ +#define _SYSCFG_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for SYSCFG_RAMECCERRFAULTEN */ +#define _SYSCFG_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for SYSCFG_RAMECCERRFAULTEN */ +#define _SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT (_SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ /* Bit fields for SYSCFG DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_MASK 0x00007FFFUL /**< Mask for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_MASK 0x7FFFUL /**< Bit mask for SYSCFG_RAMRETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15 0x00004000UL /**< Mode BLK15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO15 0x00006000UL /**< Mode BLK14TO15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO15 0x00007000UL /**< Mode BLK13TO15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO15 0x00007800UL /**< Mode BLK12TO15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO15 0x00007C00UL /**< Mode BLK11TO15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO15 0x00007E00UL /**< Mode BLK10TO15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO15 0x00007F00UL /**< Mode BLK9TO15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO15 0x00007F80UL /**< Mode BLK8TO15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO15 0x00007FC0UL /**< Mode BLK7TO15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO15 0x00007FE0UL /**< Mode BLK6TO15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO15 0x00007FF0UL /**< Mode BLK5TO15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO15 0x00007FF8UL /**< Mode BLK4TO15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO15 0x00007FFCUL /**< Mode BLK3TO15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO15 0x00007FFEUL /**< Mode BLK2TO15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO15 0x00007FFFUL /**< Mode BLK1TO15 for SYSCFG_DMEM0RETNCTRL */ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_DMEM0RETNCTRL */ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15 << 0) /**< Shifted mode BLK15 for SYSCFG_DMEM0RETNCTRL */ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO15 << 0) /**< Shifted mode BLK14TO15 for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO15 << 0) /**< Shifted mode BLK13TO15 for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO15 << 0) /**< Shifted mode BLK12TO15 for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO15 << 0) /**< Shifted mode BLK11TO15 for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO15 << 0) /**< Shifted mode BLK10TO15 for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO15 << 0) /**< Shifted mode BLK9TO15 for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO15 << 0) /**< Shifted mode BLK8TO15 for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO15 << 0) /**< Shifted mode BLK7TO15 for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO15 << 0) /**< Shifted mode BLK6TO15 for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO15 << 0) /**< Shifted mode BLK5TO15 for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO15 << 0) /**< Shifted mode BLK4TO15 for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO15 << 0) /**< Shifted mode BLK3TO15 for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO15 << 0) /**< Shifted mode BLK2TO15 for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO15 << 0) /**< Shifted mode BLK1TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define _SYSCFG_DMEM0RETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_MASK 0x00007FFFUL /**< Mask for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_MASK 0x7FFFUL /**< Bit mask for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15 0x00004000UL /**< Mode BLK15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO15 0x00006000UL /**< Mode BLK14TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO15 0x00007000UL /**< Mode BLK13TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO15 0x00007800UL /**< Mode BLK12TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO15 0x00007C00UL /**< Mode BLK11TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO15 0x00007E00UL /**< Mode BLK10TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO15 0x00007F00UL /**< Mode BLK9TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO15 0x00007F80UL /**< Mode BLK8TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO15 0x00007FC0UL /**< Mode BLK7TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO15 0x00007FE0UL /**< Mode BLK6TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO15 0x00007FF0UL /**< Mode BLK5TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO15 0x00007FF8UL /**< Mode BLK4TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO15 0x00007FFCUL /**< Mode BLK3TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO15 0x00007FFEUL /**< Mode BLK2TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO15 0x00007FFFUL /**< Mode BLK1TO15 for SYSCFG_DMEM0RETNCTRL */ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_DMEM0RETNCTRL */ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15 << 0) /**< Shifted mode BLK15 for SYSCFG_DMEM0RETNCTRL */ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO15 << 0) /**< Shifted mode BLK14TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO15 << 0) /**< Shifted mode BLK13TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO15 << 0) /**< Shifted mode BLK12TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO15 << 0) /**< Shifted mode BLK11TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO15 << 0) /**< Shifted mode BLK10TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO15 << 0) /**< Shifted mode BLK9TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO15 << 0) /**< Shifted mode BLK8TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO15 << 0) /**< Shifted mode BLK7TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO15 << 0) /**< Shifted mode BLK6TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO15 << 0) /**< Shifted mode BLK5TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO15 << 0) /**< Shifted mode BLK4TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO15 << 0) /**< Shifted mode BLK3TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO15 << 0) /**< Shifted mode BLK2TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO15 << 0) /**< Shifted mode BLK1TO15 for SYSCFG_DMEM0RETNCTRL*/ /* Bit fields for SYSCFG RAMBIASCONF */ -#define _SYSCFG_RAMBIASCONF_RESETVALUE 0x00000002UL /**< Default value for SYSCFG_RAMBIASCONF */ -#define _SYSCFG_RAMBIASCONF_MASK 0x0000000FUL /**< Mask for SYSCFG_RAMBIASCONF */ -#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMBIASCTRL */ -#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_MASK 0xFUL /**< Bit mask for SYSCFG_RAMBIASCTRL */ -#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT 0x00000002UL /**< Mode DEFAULT for SYSCFG_RAMBIASCONF */ -#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_No 0x00000000UL /**< Mode No for SYSCFG_RAMBIASCONF */ -#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 0x00000001UL /**< Mode VSB100 for SYSCFG_RAMBIASCONF */ -#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 0x00000002UL /**< Mode VSB200 for SYSCFG_RAMBIASCONF */ -#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 0x00000004UL /**< Mode VSB300 for SYSCFG_RAMBIASCONF */ -#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 0x00000008UL /**< Mode VSB400 for SYSCFG_RAMBIASCONF */ -#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RAMBIASCONF */ -#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_No (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_No << 0) /**< Shifted mode No for SYSCFG_RAMBIASCONF */ -#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 << 0) /**< Shifted mode VSB100 for SYSCFG_RAMBIASCONF */ -#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 << 0) /**< Shifted mode VSB200 for SYSCFG_RAMBIASCONF */ -#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 << 0) /**< Shifted mode VSB300 for SYSCFG_RAMBIASCONF */ -#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 << 0) /**< Shifted mode VSB400 for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RESETVALUE 0x00000002UL /**< Default value for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_MASK 0x0000000FUL /**< Mask for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMBIASCTRL */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_MASK 0xFUL /**< Bit mask for SYSCFG_RAMBIASCTRL */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT 0x00000002UL /**< Mode DEFAULT for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_No 0x00000000UL /**< Mode No for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 0x00000001UL /**< Mode VSB100 for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 0x00000002UL /**< Mode VSB200 for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 0x00000004UL /**< Mode VSB300 for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 0x00000008UL /**< Mode VSB400 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_No (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_No << 0) /**< Shifted mode No for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 << 0) /**< Shifted mode VSB100 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 << 0) /**< Shifted mode VSB200 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 << 0) /**< Shifted mode VSB300 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 << 0) /**< Shifted mode VSB400 for SYSCFG_RAMBIASCONF */ /* Bit fields for SYSCFG RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_MASK 0x00000103UL /**< Mask for SYSCFG_RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_MASK 0x3UL /**< Bit mask for SYSCFG_SEQRAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 0x00000001UL /**< Mode BLK0 for SYSCFG_RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 0x00000002UL /**< Mode BLK1 for SYSCFG_RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF 0x00000003UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */ -#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ -#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ -#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 << 0) /**< Shifted mode BLK0 for SYSCFG_RADIORAMRETNCTRL*/ -#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 << 0) /**< Shifted mode BLK1 for SYSCFG_RADIORAMRETNCTRL*/ -#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/ -#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL (0x1UL << 8) /**< FRCRAM Retention Control */ -#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */ -#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ -#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON << 8) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ -#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF << 8) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/ +#define _SYSCFG_RADIORAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_MASK 0x00000103UL /**< Mask for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_MASK 0x3UL /**< Bit mask for SYSCFG_SEQRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 0x00000001UL /**< Mode BLK0 for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 0x00000002UL /**< Mode BLK1 for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF 0x00000003UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 << 0) /**< Shifted mode BLK0 for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 << 0) /**< Shifted mode BLK1 for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL (0x1UL << 8) /**< FRCRAM Retention Control */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON << 8) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF << 8) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/ /* Bit fields for SYSCFG RADIOECCCTRL */ -#define _SYSCFG_RADIOECCCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIOECCCTRL */ -#define _SYSCFG_RADIOECCCTRL_MASK 0x00000303UL /**< Mask for SYSCFG_RADIOECCCTRL */ -#define SYSCFG_RADIOECCCTRL_SEQRAMECCEN (0x1UL << 0) /**< SEQRAM ECC Enable */ -#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCEN */ -#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_MASK 0x1UL /**< Bit mask for SYSCFG_SEQRAMECCEN */ -#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ -#define SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ -#define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN (0x1UL << 1) /**< SEQRAM ECC Error Writeback Enable */ -#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_SHIFT 1 /**< Shift value for SYSCFG_SEQRAMECCEWEN */ -#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_MASK 0x2UL /**< Bit mask for SYSCFG_SEQRAMECCEWEN */ -#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ -#define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ -#define SYSCFG_RADIOECCCTRL_FRCRAMECCEN (0x1UL << 8) /**< FRCRAM ECC Enable */ -#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMECCEN */ -#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMECCEN */ -#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ -#define SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ -#define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN (0x1UL << 9) /**< FRCRAM ECC Error Writeback Enable */ -#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_SHIFT 9 /**< Shift value for SYSCFG_FRCRAMECCEWEN */ -#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_MASK 0x200UL /**< Bit mask for SYSCFG_FRCRAMECCEWEN */ -#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ -#define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ +#define _SYSCFG_RADIOECCCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIOECCCTRL */ +#define _SYSCFG_RADIOECCCTRL_MASK 0x00000303UL /**< Mask for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEN (0x1UL << 0) /**< SEQRAM ECC Enable */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_MASK 0x1UL /**< Bit mask for SYSCFG_SEQRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN (0x1UL << 1) /**< SEQRAM ECC Error Writeback Enable */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_SHIFT 1 /**< Shift value for SYSCFG_SEQRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_MASK 0x2UL /**< Bit mask for SYSCFG_SEQRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEN (0x1UL << 8) /**< FRCRAM ECC Enable */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN (0x1UL << 9) /**< FRCRAM ECC Error Writeback Enable */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_SHIFT 9 /**< Shift value for SYSCFG_FRCRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_MASK 0x200UL /**< Bit mask for SYSCFG_FRCRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ /* Bit fields for SYSCFG SEQRAMECCADDR */ -#define _SYSCFG_SEQRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_SEQRAMECCADDR */ -#define _SYSCFG_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_SEQRAMECCADDR */ -#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCADDR */ -#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SEQRAMECCADDR */ -#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_SEQRAMECCADDR */ -#define SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT (_SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_SEQRAMECCADDR*/ +#define _SYSCFG_SEQRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_SEQRAMECCADDR */ +#define SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT (_SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_SEQRAMECCADDR*/ /* Bit fields for SYSCFG FRCRAMECCADDR */ -#define _SYSCFG_FRCRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_FRCRAMECCADDR */ -#define _SYSCFG_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_FRCRAMECCADDR */ -#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_FRCRAMECCADDR */ -#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_FRCRAMECCADDR */ -#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_FRCRAMECCADDR */ -#define SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT (_SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_FRCRAMECCADDR*/ +#define _SYSCFG_FRCRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_FRCRAMECCADDR */ +#define SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT (_SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_FRCRAMECCADDR*/ /* Bit fields for SYSCFG ICACHERAMRETNCTRL */ -#define _SYSCFG_ICACHERAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ICACHERAMRETNCTRL */ -#define _SYSCFG_ICACHERAMRETNCTRL_MASK 0x00000001UL /**< Mask for SYSCFG_ICACHERAMRETNCTRL */ -#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL (0x1UL << 0) /**< ICACHERAM Retention control */ -#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */ -#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_MASK 0x1UL /**< Bit mask for SYSCFG_RAMRETNCTRL */ -#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ICACHERAMRETNCTRL */ -#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_ICACHERAMRETNCTRL */ -#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_ICACHERAMRETNCTRL */ -#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ICACHERAMRETNCTRL*/ -#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_ICACHERAMRETNCTRL*/ -#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_ICACHERAMRETNCTRL*/ +#define _SYSCFG_ICACHERAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_MASK 0x00000001UL /**< Mask for SYSCFG_ICACHERAMRETNCTRL */ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL (0x1UL << 0) /**< ICACHERAM Retention control */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_MASK 0x1UL /**< Bit mask for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_ICACHERAMRETNCTRL */ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ICACHERAMRETNCTRL*/ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_ICACHERAMRETNCTRL*/ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_ICACHERAMRETNCTRL*/ /* Bit fields for SYSCFG DMEM0PORTMAPSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_RESETVALUE 0x00007905UL /**< Default value for SYSCFG_DMEM0PORTMAPSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_MASK 0x0000FFFFUL /**< Mask for SYSCFG_DMEM0PORTMAPSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_SHIFT 0 /**< Shift value for SYSCFG_LDMAPORTSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_MASK 0x3UL /**< Bit mask for SYSCFG_LDMAPORTSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ -#define SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ -#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_SHIFT 2 /**< Shift value for SYSCFG_SRWAESPORTSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_MASK 0xCUL /**< Bit mask for SYSCFG_SRWAESPORTSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ -#define SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ -#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_SHIFT 4 /**< Shift value for SYSCFG_AHBSRWPORTSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_MASK 0x30UL /**< Bit mask for SYSCFG_AHBSRWPORTSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ -#define SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ -#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_SHIFT 6 /**< Shift value for SYSCFG_SRWECA0PORTSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_MASK 0xC0UL /**< Bit mask for SYSCFG_SRWECA0PORTSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ -#define SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ -#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_SHIFT 8 /**< Shift value for SYSCFG_SRWECA1PORTSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_MASK 0x300UL /**< Bit mask for SYSCFG_SRWECA1PORTSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ -#define SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_RESETVALUE 0x00007905UL /**< Default value for SYSCFG_DMEM0PORTMAPSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MASK 0x0000FFFFUL /**< Mask for SYSCFG_DMEM0PORTMAPSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_SHIFT 0 /**< Shift value for SYSCFG_LDMAPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_MASK 0x3UL /**< Bit mask for SYSCFG_LDMAPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_SHIFT 2 /**< Shift value for SYSCFG_SRWAESPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_MASK 0xCUL /**< Bit mask for SYSCFG_SRWAESPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_SHIFT 4 /**< Shift value for SYSCFG_AHBSRWPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_MASK 0x30UL /**< Bit mask for SYSCFG_AHBSRWPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_SHIFT 6 /**< Shift value for SYSCFG_SRWECA0PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_MASK 0xC0UL /**< Bit mask for SYSCFG_SRWECA0PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_SHIFT 8 /**< Shift value for SYSCFG_SRWECA1PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_MASK 0x300UL /**< Bit mask for SYSCFG_SRWECA1PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_SHIFT 10 /**< Shift value for SYSCFG_MVPAHBDATA0PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_MASK 0xC00UL /**< Bit mask for SYSCFG_MVPAHBDATA0PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_SHIFT 12 /**< Shift value for SYSCFG_MVPAHBDATA1PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_MASK 0x3000UL /**< Bit mask for SYSCFG_MVPAHBDATA1PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_SHIFT 14 /**< Shift value for SYSCFG_MVPAHBDATA2PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_MASK 0xC000UL /**< Bit mask for SYSCFG_MVPAHBDATA2PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_DEFAULT << 14) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ /* Bit fields for SYSCFG ROOTDATA0 */ -#define _SYSCFG_ROOTDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA0 */ -#define _SYSCFG_ROOTDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA0 */ -#define _SYSCFG_ROOTDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ -#define _SYSCFG_ROOTDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ -#define _SYSCFG_ROOTDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA0 */ -#define SYSCFG_ROOTDATA0_DATA_DEFAULT (_SYSCFG_ROOTDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA0 */ +#define _SYSCFG_ROOTDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA0 */ +#define _SYSCFG_ROOTDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA0 */ +#define _SYSCFG_ROOTDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA0 */ +#define SYSCFG_ROOTDATA0_DATA_DEFAULT (_SYSCFG_ROOTDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA0 */ /* Bit fields for SYSCFG ROOTDATA1 */ -#define _SYSCFG_ROOTDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA1 */ -#define _SYSCFG_ROOTDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA1 */ -#define _SYSCFG_ROOTDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ -#define _SYSCFG_ROOTDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ -#define _SYSCFG_ROOTDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA1 */ -#define SYSCFG_ROOTDATA1_DATA_DEFAULT (_SYSCFG_ROOTDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA1 */ +#define _SYSCFG_ROOTDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA1 */ +#define _SYSCFG_ROOTDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA1 */ +#define _SYSCFG_ROOTDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA1 */ +#define SYSCFG_ROOTDATA1_DATA_DEFAULT (_SYSCFG_ROOTDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA1 */ /* Bit fields for SYSCFG ROOTLOCKSTATUS */ -#define _SYSCFG_ROOTLOCKSTATUS_RESETVALUE 0x007F0107UL /**< Default value for SYSCFG_ROOTLOCKSTATUS */ -#define _SYSCFG_ROOTLOCKSTATUS_MASK 0x807F0107UL /**< Mask for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_BUSLOCK (0x1UL << 0) /**< Bus Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_SHIFT 0 /**< Shift value for SYSCFG_BUSLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_MASK 0x1UL /**< Bit mask for SYSCFG_BUSLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_REGLOCK (0x1UL << 1) /**< Register Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_SHIFT 1 /**< Shift value for SYSCFG_REGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_MASK 0x2UL /**< Bit mask for SYSCFG_REGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_MFRLOCK (0x1UL << 2) /**< Manufacture Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_SHIFT 2 /**< Shift value for SYSCFG_MFRLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_MASK 0x4UL /**< Bit mask for SYSCFG_MFRLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK (0x1UL << 8) /**< Root Debug Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_SHIFT 8 /**< Shift value for SYSCFG_ROOTDBGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_MASK 0x100UL /**< Bit mask for SYSCFG_ROOTDBGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK (0x1UL << 16) /**< User Debug Access Port Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_SHIFT 16 /**< Shift value for SYSCFG_USERDBGAPLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_MASK 0x10000UL /**< Bit mask for SYSCFG_USERDBGAPLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK (0x1UL << 17) /**< User Invasive Debug Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_SHIFT 17 /**< Shift value for SYSCFG_USERDBGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_MASK 0x20000UL /**< Bit mask for SYSCFG_USERDBGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK (0x1UL << 18) /**< User Non-invasive Debug Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_SHIFT 18 /**< Shift value for SYSCFG_USERNIDLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_MASK 0x40000UL /**< Bit mask for SYSCFG_USERNIDLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK (0x1UL << 19) /**< User Secure Invasive Debug Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_SHIFT 19 /**< Shift value for SYSCFG_USERSPIDLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_MASK 0x80000UL /**< Bit mask for SYSCFG_USERSPIDLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK (0x1UL << 20) /**< User Secure Non-invasive Debug Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_SHIFT 20 /**< Shift value for SYSCFG_USERSPNIDLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_MASK 0x100000UL /**< Bit mask for SYSCFG_USERSPNIDLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK (0x1UL << 21) /**< Radio Invasive Debug Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_SHIFT 21 /**< Shift value for SYSCFG_RADIOIDBGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_MASK 0x200000UL /**< Bit mask for SYSCFG_RADIOIDBGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK (0x1UL << 22) /**< Radio Non-invasive Debug Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_SHIFT 22 /**< Shift value for SYSCFG_RADIONIDBGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_MASK 0x400000UL /**< Bit mask for SYSCFG_RADIONIDBGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED (0x1UL << 31) /**< E-Fuse Unlocked */ -#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_SHIFT 31 /**< Shift value for SYSCFG_EFUSEUNLOCKED */ -#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_MASK 0x80000000UL /**< Bit mask for SYSCFG_EFUSEUNLOCKED */ -#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT << 31) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define _SYSCFG_ROOTLOCKSTATUS_RESETVALUE 0x007F0107UL /**< Default value for SYSCFG_ROOTLOCKSTATUS */ +#define _SYSCFG_ROOTLOCKSTATUS_MASK 0x807F0107UL /**< Mask for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_BUSLOCK (0x1UL << 0) /**< Bus Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_SHIFT 0 /**< Shift value for SYSCFG_BUSLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_MASK 0x1UL /**< Bit mask for SYSCFG_BUSLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_REGLOCK (0x1UL << 1) /**< Register Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_SHIFT 1 /**< Shift value for SYSCFG_REGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_MASK 0x2UL /**< Bit mask for SYSCFG_REGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_MFRLOCK (0x1UL << 2) /**< Manufacture Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_SHIFT 2 /**< Shift value for SYSCFG_MFRLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_MASK 0x4UL /**< Bit mask for SYSCFG_MFRLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK (0x1UL << 8) /**< Root Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_SHIFT 8 /**< Shift value for SYSCFG_ROOTDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_MASK 0x100UL /**< Bit mask for SYSCFG_ROOTDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK (0x1UL << 16) /**< User Debug Access Port Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_SHIFT 16 /**< Shift value for SYSCFG_USERDBGAPLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_MASK 0x10000UL /**< Bit mask for SYSCFG_USERDBGAPLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK (0x1UL << 17) /**< User Invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_SHIFT 17 /**< Shift value for SYSCFG_USERDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_MASK 0x20000UL /**< Bit mask for SYSCFG_USERDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK (0x1UL << 18) /**< User Non-invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_SHIFT 18 /**< Shift value for SYSCFG_USERNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_MASK 0x40000UL /**< Bit mask for SYSCFG_USERNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK (0x1UL << 19) /**< User Secure Invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_SHIFT 19 /**< Shift value for SYSCFG_USERSPIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_MASK 0x80000UL /**< Bit mask for SYSCFG_USERSPIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK (0x1UL << 20) /**< User Secure Non-invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_SHIFT 20 /**< Shift value for SYSCFG_USERSPNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_MASK 0x100000UL /**< Bit mask for SYSCFG_USERSPNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK (0x1UL << 21) /**< Radio Invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_SHIFT 21 /**< Shift value for SYSCFG_RADIOIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_MASK 0x200000UL /**< Bit mask for SYSCFG_RADIOIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK (0x1UL << 22) /**< Radio Non-invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_SHIFT 22 /**< Shift value for SYSCFG_RADIONIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_MASK 0x400000UL /**< Bit mask for SYSCFG_RADIONIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED (0x1UL << 31) /**< E-Fuse Unlocked */ +#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_SHIFT 31 /**< Shift value for SYSCFG_EFUSEUNLOCKED */ +#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_MASK 0x80000000UL /**< Bit mask for SYSCFG_EFUSEUNLOCKED */ +#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT << 31) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ /* Bit fields for SYSCFG ROOTSESWVERSION */ -#define _SYSCFG_ROOTSESWVERSION_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTSESWVERSION */ -#define _SYSCFG_ROOTSESWVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTSESWVERSION */ -#define _SYSCFG_ROOTSESWVERSION_SWVERSION_SHIFT 0 /**< Shift value for SYSCFG_SWVERSION */ -#define _SYSCFG_ROOTSESWVERSION_SWVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SWVERSION */ -#define _SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTSESWVERSION */ -#define SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT (_SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTSESWVERSION*/ +#define _SYSCFG_ROOTSESWVERSION_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTSESWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTSESWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_SWVERSION_SHIFT 0 /**< Shift value for SYSCFG_SWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_SWVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTSESWVERSION */ +#define SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT (_SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTSESWVERSION*/ /** @} End of group BGM24_SYSCFG_BitFields */ /** @} End of group BGM24_SYSCFG */ diff --git a/platform/Device/SiliconLabs/BGM24/Include/em_device.h b/platform/Device/SiliconLabs/BGM24/Include/em_device.h index b8b3bc83a0..70877a8d34 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/em_device.h +++ b/platform/Device/SiliconLabs/BGM24/Include/em_device.h @@ -68,6 +68,9 @@ #elif defined(BGM241SB22VNA) #include "bgm241sb22vna.h" +#elif defined(BGM241SD22VNA) +#include "bgm241sd22vna.h" + #else #error "em_device.h: PART NUMBER undefined" #endif diff --git a/platform/Device/SiliconLabs/BGM24/Include/system_bgm24.h b/platform/Device/SiliconLabs/BGM24/Include/system_bgm24.h index 8402e40841..f7f1cb4692 100644 --- a/platform/Device/SiliconLabs/BGM24/Include/system_bgm24.h +++ b/platform/Device/SiliconLabs/BGM24/Include/system_bgm24.h @@ -115,6 +115,7 @@ void EUSART0_RX_IRQHandler(void); /**< EUSART0_RX IRQ Handler */ void EUSART0_TX_IRQHandler(void); /**< EUSART0_TX IRQ Handler */ void EUSART1_RX_IRQHandler(void); /**< EUSART1_RX IRQ Handler */ void EUSART1_TX_IRQHandler(void); /**< EUSART1_TX IRQ Handler */ +void MVP_IRQHandler(void); /**< MVP IRQ Handler */ void ICACHE0_IRQHandler(void); /**< ICACHE0 IRQ Handler */ void BURTC_IRQHandler(void); /**< BURTC IRQ Handler */ void LETIMER0_IRQHandler(void); /**< LETIMER0 IRQ Handler */ diff --git a/platform/Device/SiliconLabs/BGM24/Source/startup_bgm24.c b/platform/Device/SiliconLabs/BGM24/Source/startup_bgm24.c index 466c333a29..6fa072224c 100644 --- a/platform/Device/SiliconLabs/BGM24/Source/startup_bgm24.c +++ b/platform/Device/SiliconLabs/BGM24/Source/startup_bgm24.c @@ -138,6 +138,7 @@ void EUSART0_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler")) void EUSART0_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void EUSART1_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void EUSART1_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void MVP_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void ICACHE0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void BURTC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); void LETIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); @@ -261,7 +262,7 @@ const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS] __VECTOR_TABLE_ATTRIBUTE = { { EUSART0_TX_IRQHandler }, /* -4 = EUSART0_TX */ { EUSART1_RX_IRQHandler }, /* -3 = EUSART1_RX */ { EUSART1_TX_IRQHandler }, /* -2 = EUSART1_TX */ - { Default_Handler }, /* Reserved */ + { MVP_IRQHandler }, /* -1 = MVP */ { ICACHE0_IRQHandler }, /* 00 = ICACHE0 */ { BURTC_IRQHandler }, /* 01 = BURTC */ { LETIMER0_IRQHandler }, /* 02 = LETIMER0 */ diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dma_descriptor.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dma_descriptor.h index 12974ef155..aaba7b7967 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_dma_descriptor.h @@ -27,6 +27,8 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFM32PG22_DMA_DESCRIPTOR_H +#define EFM32PG22_DMA_DESCRIPTOR_H #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ @@ -53,3 +55,5 @@ typedef struct { } DMA_DESCRIPTOR_TypeDef; /**< @} */ /** @} End of group Parts */ + +#endif /* EFM32PG22_DMA_DESCRIPTOR_H */ diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldmaxbar_defines.h index f899ae6eb5..2e666ed977 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_ldmaxbar_defines.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFM32PG22_LDMAXBAR_DEFINES_H +#define EFM32PG22_LDMAXBAR_DEFINES_H + /* Module source selection indices */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ @@ -148,3 +151,5 @@ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 << 0) /** Shifted Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 << 0) /** Shifted Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF << 0) /** Shifted Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ + +#endif /* EFM32PG22_LDMAXBAR_DEFINES_H */ diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_prs_signals.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_prs_signals.h index 166276a49a..66fbcf3af6 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_prs_signals.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22_prs_signals.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFM32PG22_PRS_SIGNALS_H +#define EFM32PG22_PRS_SIGNALS_H + /** Synchronous signal sources enumeration: */ #define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) #define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) @@ -535,3 +538,5 @@ #define PRS_LFRCO_CALMEAS (PRS_ASYNC_LFRCO_CALMEAS) #define PRS_LFRCO_SDM (PRS_ASYNC_LFRCO_SDM) #define PRS_LFRCO_TCMEAS (PRS_ASYNC_LFRCO_TCMEAS) + +#endif /* EFM32PG22_PRS_SIGNALS_H */ diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f128im32.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f128im32.h index 67c7e8d828..b7a8dab422 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f128im32.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f128im32.h @@ -546,212 +546,212 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f128im40.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f128im40.h index d494e6055d..82912cc4f3 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f128im40.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f128im40.h @@ -560,212 +560,212 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f256im32.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f256im32.h index ab63081c6d..90da36d58f 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f256im32.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f256im32.h @@ -546,212 +546,212 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f256im40.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f256im40.h index f740d596a4..41600ca1bd 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f256im40.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f256im40.h @@ -560,212 +560,212 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f32im32.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f32im32.h index 6be79587ee..f2a297b47e 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f32im32.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f32im32.h @@ -546,212 +546,212 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f32im40.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f32im40.h index 31c9fd223e..6e66780a80 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f32im40.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f32im40.h @@ -560,212 +560,212 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f512im32.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f512im32.h index 09f3c8f8e5..6d62fb82e0 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f512im32.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f512im32.h @@ -546,212 +546,212 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f512im40.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f512im40.h index 0e7f339e3d..22b433d808 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f512im40.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f512im40.h @@ -560,212 +560,212 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f64im32.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f64im32.h index 7855c2c810..36a36f4980 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f64im32.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f64im32.h @@ -546,212 +546,212 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ diff --git a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f64im40.h b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f64im40.h index 541548f30d..5ca4c48c1d 100644 --- a/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f64im40.h +++ b/platform/Device/SiliconLabs/EFM32PG22/Include/efm32pg22c200f64im40.h @@ -560,212 +560,212 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dma_descriptor.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dma_descriptor.h index a3a1bcf37e..b0f8d82991 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_dma_descriptor.h @@ -27,6 +27,8 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFM32PG23_DMA_DESCRIPTOR_H +#define EFM32PG23_DMA_DESCRIPTOR_H #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ @@ -53,3 +55,5 @@ typedef struct { } DMA_DESCRIPTOR_TypeDef; /**< @} */ /** @} End of group Parts */ + +#endif /* EFM32PG23_DMA_DESCRIPTOR_H */ diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldmaxbar_defines.h index a6899f0fd6..52e68d6fe7 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_ldmaxbar_defines.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFM32PG23_LDMAXBAR_DEFINES_H +#define EFM32PG23_LDMAXBAR_DEFINES_H + /* Module source selection indices */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ @@ -158,3 +161,5 @@ #define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL << 0) /** Shifted Mode EUSART2TXFL for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO (_LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO << 0) /** Shifted Mode LESENSEFIFO for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_LCD (_LDMAXBAR_CH_REQSEL_SIGSEL_LCD << 0) /** Shifted Mode LCD for LDMAXBAR_CH_REQSEL**/ + +#endif /* EFM32PG23_LDMAXBAR_DEFINES_H */ diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_prs_signals.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_prs_signals.h index 0d6f96aa14..d5781f8aae 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_prs_signals.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23_prs_signals.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFM32PG23_PRS_SIGNALS_H +#define EFM32PG23_PRS_SIGNALS_H + /** Synchronous signal sources enumeration: */ #define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) #define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) @@ -667,3 +670,5 @@ #define PRS_EUSART2L_TXC (PRS_ASYNC_EUSART2L_TXC) #define PRS_EUSART2L_RXFL (PRS_ASYNC_EUSART2L_RXFL) #define PRS_EUSART2L_TXFL (PRS_ASYNC_EUSART2L_TXFL) + +#endif /* EFM32PG23_PRS_SIGNALS_H */ diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f128im40.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f128im40.h index e49ad5b95b..b3aaee1cea 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f128im40.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f128im40.h @@ -636,267 +636,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f256im40.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f256im40.h index f93b6f6916..3b1f607a90 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f256im40.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f256im40.h @@ -636,267 +636,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f512im40.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f512im40.h index 290fde536e..700b34e3cf 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f512im40.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f512im40.h @@ -636,267 +636,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f64im40.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f64im40.h index 710335f35b..b5da6269cb 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f64im40.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b200f64im40.h @@ -636,267 +636,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f128im48.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f128im48.h index aed49d54ac..7ca5dfb878 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f128im48.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f128im48.h @@ -651,267 +651,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f256im48.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f256im48.h index 25445c0fec..2a1a3b6169 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f256im48.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f256im48.h @@ -651,267 +651,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f512im48.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f512im48.h index 8efb185c52..1beb747444 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f512im48.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f512im48.h @@ -651,267 +651,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f64im48.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f64im48.h index 3c618658f8..c77cdc0820 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f64im48.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b210f64im48.h @@ -651,267 +651,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f128im48.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f128im48.h index bded32c4eb..098b6b47a9 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f128im48.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f128im48.h @@ -647,267 +647,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f256im48.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f256im48.h index c94a9baa9b..ab56f60481 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f256im48.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f256im48.h @@ -647,267 +647,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f512im48.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f512im48.h index 9d96c22167..36c1ad9a4d 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f512im48.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f512im48.h @@ -647,267 +647,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f64im48.h b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f64im48.h index 5bd9e5e503..de064c80c5 100644 --- a/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f64im48.h +++ b/platform/Device/SiliconLabs/EFM32PG23/Include/efm32pg23b310f64im48.h @@ -647,267 +647,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_dma_descriptor.h index b69f144cb0..e5bc1ed4cf 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_dma_descriptor.h @@ -27,6 +27,8 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32BG21_DMA_DESCRIPTOR_H +#define EFR32BG21_DMA_DESCRIPTOR_H #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ @@ -53,3 +55,5 @@ typedef struct { } DMA_DESCRIPTOR_TypeDef; /**< @} */ /** @} End of group Parts */ + +#endif /* EFR32BG21_DMA_DESCRIPTOR_H */ diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldmaxbar_defines.h index 7fcf1c7c8f..e375796c5b 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_ldmaxbar_defines.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32BG21_LDMAXBAR_DEFINES_H +#define EFR32BG21_LDMAXBAR_DEFINES_H + /* Module source selection indices */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ @@ -140,3 +143,5 @@ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 << 0) /** Shifted Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 << 0) /** Shifted Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF << 0) /** Shifted Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ + +#endif /* EFR32BG21_LDMAXBAR_DEFINES_H */ diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_prs_signals.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_prs_signals.h index 7e85acde95..68b59436f7 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21_prs_signals.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32BG21_PRS_SIGNALS_H +#define EFR32BG21_PRS_SIGNALS_H + /** Synchronous signal sources enumeration: */ #define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) #define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) @@ -768,3 +771,5 @@ #define PRS_SE_STATE0GATED (PRS_ASYNC_SE_STATE0GATED) #define PRS_SE_STATE1GATED (PRS_ASYNC_SE_STATE1GATED) #define PRS_SE_STATE2GATED (PRS_ASYNC_SE_STATE2GATED) + +#endif /* EFR32BG21_PRS_SIGNALS_H */ diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f1024im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f1024im32.h index ed45c958a7..1969423e89 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f1024im32.h @@ -552,217 +552,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f512im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f512im32.h index 9bfe652fec..816850d810 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f512im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f512im32.h @@ -552,217 +552,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f768im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f768im32.h index 7e5cc86f65..d906df0fb2 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f768im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a010f768im32.h @@ -552,217 +552,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f1024im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f1024im32.h index 03f50f36b6..01ca3ff553 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f1024im32.h @@ -554,217 +554,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f512im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f512im32.h index da020def2c..6ed818b560 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f512im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f512im32.h @@ -554,217 +554,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f768im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f768im32.h index 8a35bc846a..28eed1e2c1 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f768im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21a020f768im32.h @@ -554,217 +554,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f1024im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f1024im32.h index 77865a5c84..bddeb2ba67 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f1024im32.h @@ -552,217 +552,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f512im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f512im32.h index d5010c67c4..5a21e86d13 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f512im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f512im32.h @@ -554,217 +554,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f768im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f768im32.h index 4aac6925f5..651f0b6a55 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f768im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b010f768im32.h @@ -552,217 +552,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f1024im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f1024im32.h index dbc84061ad..963efa7938 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f1024im32.h @@ -554,217 +554,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f512im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f512im32.h index fed74c3e7f..fb74562f87 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f512im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f512im32.h @@ -554,217 +554,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f768im32.h b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f768im32.h index 8c2536a526..925fa6e758 100644 --- a/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f768im32.h +++ b/platform/Device/SiliconLabs/EFR32BG21/Include/efr32bg21b020f768im32.h @@ -554,217 +554,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dma_descriptor.h index cbd9a40151..f1cde9c33f 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dma_descriptor.h @@ -27,6 +27,8 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32BG22_DMA_DESCRIPTOR_H +#define EFR32BG22_DMA_DESCRIPTOR_H #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ @@ -53,3 +55,5 @@ typedef struct { } DMA_DESCRIPTOR_TypeDef; /**< @} */ /** @} End of group Parts */ + +#endif /* EFR32BG22_DMA_DESCRIPTOR_H */ diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar_defines.h index 59398facf6..b02a11ab49 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar_defines.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32BG22_LDMAXBAR_DEFINES_H +#define EFR32BG22_LDMAXBAR_DEFINES_H + /* Module source selection indices */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ @@ -148,3 +151,5 @@ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 << 0) /** Shifted Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 << 0) /** Shifted Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF << 0) /** Shifted Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ + +#endif /* EFR32BG22_LDMAXBAR_DEFINES_H */ diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs_signals.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs_signals.h index 335952b045..47b5a42886 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs_signals.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32BG22_PRS_SIGNALS_H +#define EFR32BG22_PRS_SIGNALS_H + /** Synchronous signal sources enumeration: */ #define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) #define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) @@ -843,3 +846,5 @@ #define PRS_LFRCO_CALMEAS (PRS_ASYNC_LFRCO_CALMEAS) #define PRS_LFRCO_SDM (PRS_ASYNC_LFRCO_SDM) #define PRS_LFRCO_TCMEAS (PRS_ASYNC_LFRCO_TCMEAS) + +#endif /* EFR32BG22_PRS_SIGNALS_H */ diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm32.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm32.h index 731a3b21f8..8c98d9ec91 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm32.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm32.h @@ -572,222 +572,222 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm40.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm40.h index abad5a00b4..b2851791a9 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm40.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm40.h @@ -586,222 +586,222 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm32.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm32.h index 54e3eaf4c9..a42c7a72ff 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm32.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm32.h @@ -574,222 +574,222 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm40.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm40.h index 66cb169818..04fa5c850b 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm40.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm40.h @@ -588,222 +588,222 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gn32.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gn32.h index 1fc14e32e3..10971cfe89 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gn32.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gn32.h @@ -574,222 +574,222 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm32.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm32.h index 9a707a965d..e13159c81e 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm32.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm32.h @@ -574,222 +574,222 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm40.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm40.h index 0e6f5cccd8..66682455e2 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm40.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm40.h @@ -588,222 +588,222 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gn32.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gn32.h index bbe7bdef75..a95a0647bb 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gn32.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gn32.h @@ -574,222 +574,222 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im32.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im32.h index b8c30b0e23..0e31a42366 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im32.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im32.h @@ -574,222 +574,222 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im40.h b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im40.h index 1f71d97b66..b2daa98fe2 100644 --- a/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im40.h +++ b/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im40.h @@ -588,222 +588,222 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dma_descriptor.h index bbee0ee8d9..3b5c5cb6ef 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_dma_descriptor.h @@ -27,6 +27,8 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32BG24_DMA_DESCRIPTOR_H +#define EFR32BG24_DMA_DESCRIPTOR_H #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ @@ -53,3 +55,5 @@ typedef struct { } DMA_DESCRIPTOR_TypeDef; /**< @} */ /** @} End of group Parts */ + +#endif /* EFR32BG24_DMA_DESCRIPTOR_H */ diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldmaxbar_defines.h index 3242bdd015..45a55d6df2 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_ldmaxbar_defines.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32BG24_LDMAXBAR_DEFINES_H +#define EFR32BG24_LDMAXBAR_DEFINES_H + /* Module source selection indices */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ @@ -150,3 +153,5 @@ #define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ << 0) /** Shifted Mode VDAC0CH1_REQ for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ << 0) /** Shifted Mode VDAC1CH0_REQ for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ << 0) /** Shifted Mode VDAC1CH1_REQ for LDMAXBAR_CH_REQSEL**/ + +#endif /* EFR32BG24_LDMAXBAR_DEFINES_H */ diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_prs_signals.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_prs_signals.h index ed61957462..9ad32e7486 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24_prs_signals.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32BG24_PRS_SIGNALS_H +#define EFR32BG24_PRS_SIGNALS_H + /** Synchronous signal sources enumeration: */ #define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) #define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) @@ -969,3 +972,5 @@ #define PRS_LFRCO_CALMEAS (PRS_ASYNC_LFRCO_CALMEAS) #define PRS_LFRCO_SDM (PRS_ASYNC_LFRCO_SDM) #define PRS_LFRCO_TCMEAS (PRS_ASYNC_LFRCO_TCMEAS) + +#endif /* EFR32BG24_PRS_SIGNALS_H */ diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024im40.h index c40f83d005..6d112dd87a 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024im40.h @@ -632,257 +632,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024im48.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024im48.h index f2485d5ef0..ae9725f69a 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1024im48.h @@ -634,257 +634,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1536im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1536im40.h index 4ae3da84b8..446209d237 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1536im40.h @@ -632,257 +632,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1536im48.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1536im48.h index fd614aed6c..7274a56e52 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a010f1536im48.h @@ -634,257 +634,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1024im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1024im40.h index f59852db6b..76d5651b4a 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1024im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1024im40.h @@ -630,257 +630,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1024im48.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1024im48.h index ff36173a7e..b2e7bfdc02 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1024im48.h @@ -632,257 +632,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1536im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1536im40.h index 4b4063b137..080fef102e 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a020f1536im40.h @@ -630,257 +630,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a610f1536im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a610f1536im40.h index bb11d59a93..0aa1aeb49e 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a610f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a610f1536im40.h @@ -632,257 +632,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a620f1536im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a620f1536im40.h index 7aa5e105ac..bab156c8e3 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a620f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24a620f1536im40.h @@ -630,257 +630,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1536im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1536im40.h index e75361d2c6..a5d50c4d0c 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1536im40.h @@ -633,257 +633,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1536im48.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1536im48.h index 14e57ccbea..054e2429a6 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b010f1536im48.h @@ -635,257 +635,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b020f1536im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b020f1536im40.h index 31c8b87179..95ecb1a474 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b020f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b020f1536im40.h @@ -631,257 +631,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b110f1536im48.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b110f1536im48.h index 3bbdd33bcc..5c2fcda078 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b110f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b110f1536im48.h @@ -631,257 +631,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b210f1024im48.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b210f1024im48.h index 19cec26436..8a11582a31 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b210f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b210f1024im48.h @@ -641,262 +641,262 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) || SL_TRUSTZONE_PERIPHERAL_MVP_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MVP_S) && (SL_TRUSTZONE_PERIPHERAL_MVP_S != 0))) #define MVP_BASE (MVP_S_BASE) /* MVP base address */ #else #define MVP_BASE (MVP_NS_BASE) /* MVP base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b210f1536im48.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b210f1536im48.h new file mode 100644 index 0000000000..ab7aab5080 --- /dev/null +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b210f1536im48.h @@ -0,0 +1,1536 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32BG24B210F1536IM48 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG24B210F1536IM48_H +#define EFR32BG24B210F1536IM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32BG24B210F1536IM48 EFR32BG24B210F1536IM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32BG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + MVP_IRQn = 15, /*!< 15 EFR32 MVP Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32BG24B210F1536IM48_Core EFR32BG24B210F1536IM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32BG24B210F1536IM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32BG24B210F1536IM48_Part EFR32BG24B210F1536IM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32BG24B210F1536IM48) +#define EFR32BG24B210F1536IM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32BG24B210F1536IM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_BLUE_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_BG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32BG24B210F1536IM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH0_MAIN_OUTPUT_PIN 0U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC0_VDAC_CH1_MAIN_OUTPUT_PIN 1U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH0_MAIN_OUTPUT_PIN 2U /**< Pin of VDAC_CH0_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PORT GPIO_PB_INDEX /**< Port of VDAC_CH1_MAIN_OUTPUT.*/ +#define VDAC1_VDAC_CH1_MAIN_OUTPUT_PIN 3U /**< Pin of VDAC_CH1_MAIN_OUTPUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define MVP_PRESENT /** MVP is available in this part */ +#define MVP_COUNT 1 /** 1 MVPs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32bg24.h" /* System Header File */ + +/** @} End of group EFR32BG24B210F1536IM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32BG24B210F1536IM48_Peripheral_TypeDefs EFR32BG24B210F1536IM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32bg24_scratchpad.h" +#include "efr32bg24_emu.h" +#include "efr32bg24_cmu.h" +#include "efr32bg24_hfrco.h" +#include "efr32bg24_fsrco.h" +#include "efr32bg24_dpll.h" +#include "efr32bg24_lfxo.h" +#include "efr32bg24_lfrco.h" +#include "efr32bg24_ulfrco.h" +#include "efr32bg24_msc.h" +#include "efr32bg24_icache.h" +#include "efr32bg24_prs.h" +#include "efr32bg24_gpio.h" +#include "efr32bg24_ldma.h" +#include "efr32bg24_ldmaxbar.h" +#include "efr32bg24_timer.h" +#include "efr32bg24_usart.h" +#include "efr32bg24_burtc.h" +#include "efr32bg24_i2c.h" +#include "efr32bg24_syscfg.h" +#include "efr32bg24_buram.h" +#include "efr32bg24_gpcrc.h" +#include "efr32bg24_dcdc.h" +#include "efr32bg24_mailbox.h" +#include "efr32bg24_eusart.h" +#include "efr32bg24_sysrtc.h" +#include "efr32bg24_keyscan.h" +#include "efr32bg24_mpahbram.h" +#include "efr32bg24_aes.h" +#include "efr32bg24_smu.h" +#include "efr32bg24_letimer.h" +#include "efr32bg24_iadc.h" +#include "efr32bg24_acmp.h" +#include "efr32bg24_amuxcp.h" +#include "efr32bg24_vdac.h" +#include "efr32bg24_pcnt.h" +#include "efr32bg24_hfxo.h" +#include "efr32bg24_wdog.h" +#include "efr32bg24_semailbox.h" +#include "efr32bg24_mvp.h" +#include "efr32bg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32bg24_prs_signals.h" +#include "efr32bg24_dma_descriptor.h" +#include "efr32bg24_ldmaxbar_defines.h" + +/** @} End of group EFR32BG24B210F1536IM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32BG24B210F1536IM48_Peripheral_Base EFR32BG24B210F1536IM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define MVP_S_BASE (0x4D000000UL) /* MVP_S base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ +#define MVP_NS_BASE (0x5D000000UL) /* MVP_NS base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MVP_S) && (SL_TRUSTZONE_PERIPHERAL_MVP_S != 0))) +#define MVP_BASE (MVP_S_BASE) /* MVP base address */ +#else +#define MVP_BASE (MVP_NS_BASE) /* MVP base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MVP_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32BG24B210F1536IM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32BG24B210F1536IM48_Peripheral_Declaration EFR32BG24B210F1536IM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define MVP_S ((MVP_TypeDef *) MVP_S_BASE) /**< MVP_S base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define MVP_NS ((MVP_TypeDef *) MVP_NS_BASE) /**< MVP_NS base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define MVP ((MVP_TypeDef *) MVP_BASE) /**< MVP base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32BG24B210F1536IM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32BG24B210F1536IM48_Peripheral_Parameters EFR32BG24B210F1536IM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32BG24B210F1536IM48_Peripheral_Parameters */ + +/** @} End of group EFR32BG24B210F1536IM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b220f1024im48.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b220f1024im48.h index c4d18365b7..bfebc27aa7 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b220f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b220f1024im48.h @@ -639,262 +639,262 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) || SL_TRUSTZONE_PERIPHERAL_MVP_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MVP_S) && (SL_TRUSTZONE_PERIPHERAL_MVP_S != 0))) #define MVP_BASE (MVP_S_BASE) /* MVP base address */ #else #define MVP_BASE (MVP_NS_BASE) /* MVP base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b610f1536im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b610f1536im40.h index 008d0d8621..0eca14ab33 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b610f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b610f1536im40.h @@ -633,257 +633,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b620f1536im40.h b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b620f1536im40.h index 1685af927a..6db5d2aee9 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b620f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/efr32bg24b620f1536im40.h @@ -631,257 +631,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG24/Include/em_device.h b/platform/Device/SiliconLabs/EFR32BG24/Include/em_device.h index 12e17c7219..608a69e5c8 100644 --- a/platform/Device/SiliconLabs/EFR32BG24/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32BG24/Include/em_device.h @@ -83,6 +83,9 @@ #elif defined(EFR32BG24B210F1024IM48) #include "efr32bg24b210f1024im48.h" +#elif defined(EFR32BG24B210F1536IM48) +#include "efr32bg24b210f1536im48.h" + #elif defined(EFR32BG24B220F1024IM48) #include "efr32bg24b220f1024im48.h" diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dcdc.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dcdc.h index 388da14178..21795ca1d2 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dcdc.h @@ -333,31 +333,27 @@ typedef struct { #define _DCDC_BSTEM01CTRL_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ #define _DCDC_BSTEM01CTRL_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ #define _DCDC_BSTEM01CTRL_IPKVAL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for DCDC_BSTEM01CTRL */ -#define _DCDC_BSTEM01CTRL_IPKVAL_Load36mA 0x00000003UL /**< Mode Load36mA for DCDC_BSTEM01CTRL */ -#define _DCDC_BSTEM01CTRL_IPKVAL_Load40mA 0x00000004UL /**< Mode Load40mA for DCDC_BSTEM01CTRL */ -#define _DCDC_BSTEM01CTRL_IPKVAL_Load44mA 0x00000005UL /**< Mode Load44mA for DCDC_BSTEM01CTRL */ -#define _DCDC_BSTEM01CTRL_IPKVAL_Load48mA 0x00000006UL /**< Mode Load48mA for DCDC_BSTEM01CTRL */ -#define _DCDC_BSTEM01CTRL_IPKVAL_Load52mA 0x00000007UL /**< Mode Load52mA for DCDC_BSTEM01CTRL */ -#define _DCDC_BSTEM01CTRL_IPKVAL_Load56mA 0x00000008UL /**< Mode Load56mA for DCDC_BSTEM01CTRL */ -#define _DCDC_BSTEM01CTRL_IPKVAL_Load60mA 0x00000009UL /**< Mode Load60mA for DCDC_BSTEM01CTRL */ -#define _DCDC_BSTEM01CTRL_IPKVAL_Load64mA 0x0000000AUL /**< Mode Load64mA for DCDC_BSTEM01CTRL */ -#define _DCDC_BSTEM01CTRL_IPKVAL_Load68mA 0x0000000BUL /**< Mode Load68mA for DCDC_BSTEM01CTRL */ -#define _DCDC_BSTEM01CTRL_IPKVAL_Load72mA 0x0000000CUL /**< Mode Load72mA for DCDC_BSTEM01CTRL */ -#define _DCDC_BSTEM01CTRL_IPKVAL_Load76mA 0x0000000DUL /**< Mode Load76mA for DCDC_BSTEM01CTRL */ -#define _DCDC_BSTEM01CTRL_IPKVAL_Load80mA 0x0000000EUL /**< Mode Load80mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load10mA 0x00000003UL /**< Mode Load10mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load11mA 0x00000004UL /**< Mode Load11mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load13mA 0x00000005UL /**< Mode Load13mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load15mA 0x00000006UL /**< Mode Load15mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load16mA 0x00000007UL /**< Mode Load16mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load18mA 0x00000008UL /**< Mode Load18mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load20mA 0x00000009UL /**< Mode Load20mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load21mA 0x0000000AUL /**< Mode Load21mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load23mA 0x0000000BUL /**< Mode Load23mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load25mA 0x0000000CUL /**< Mode Load25mA for DCDC_BSTEM01CTRL */ #define DCDC_BSTEM01CTRL_IPKVAL_DEFAULT (_DCDC_BSTEM01CTRL_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_BSTEM01CTRL */ -#define DCDC_BSTEM01CTRL_IPKVAL_Load36mA (_DCDC_BSTEM01CTRL_IPKVAL_Load36mA << 0) /**< Shifted mode Load36mA for DCDC_BSTEM01CTRL */ -#define DCDC_BSTEM01CTRL_IPKVAL_Load40mA (_DCDC_BSTEM01CTRL_IPKVAL_Load40mA << 0) /**< Shifted mode Load40mA for DCDC_BSTEM01CTRL */ -#define DCDC_BSTEM01CTRL_IPKVAL_Load44mA (_DCDC_BSTEM01CTRL_IPKVAL_Load44mA << 0) /**< Shifted mode Load44mA for DCDC_BSTEM01CTRL */ -#define DCDC_BSTEM01CTRL_IPKVAL_Load48mA (_DCDC_BSTEM01CTRL_IPKVAL_Load48mA << 0) /**< Shifted mode Load48mA for DCDC_BSTEM01CTRL */ -#define DCDC_BSTEM01CTRL_IPKVAL_Load52mA (_DCDC_BSTEM01CTRL_IPKVAL_Load52mA << 0) /**< Shifted mode Load52mA for DCDC_BSTEM01CTRL */ -#define DCDC_BSTEM01CTRL_IPKVAL_Load56mA (_DCDC_BSTEM01CTRL_IPKVAL_Load56mA << 0) /**< Shifted mode Load56mA for DCDC_BSTEM01CTRL */ -#define DCDC_BSTEM01CTRL_IPKVAL_Load60mA (_DCDC_BSTEM01CTRL_IPKVAL_Load60mA << 0) /**< Shifted mode Load60mA for DCDC_BSTEM01CTRL */ -#define DCDC_BSTEM01CTRL_IPKVAL_Load64mA (_DCDC_BSTEM01CTRL_IPKVAL_Load64mA << 0) /**< Shifted mode Load64mA for DCDC_BSTEM01CTRL */ -#define DCDC_BSTEM01CTRL_IPKVAL_Load68mA (_DCDC_BSTEM01CTRL_IPKVAL_Load68mA << 0) /**< Shifted mode Load68mA for DCDC_BSTEM01CTRL */ -#define DCDC_BSTEM01CTRL_IPKVAL_Load72mA (_DCDC_BSTEM01CTRL_IPKVAL_Load72mA << 0) /**< Shifted mode Load72mA for DCDC_BSTEM01CTRL */ -#define DCDC_BSTEM01CTRL_IPKVAL_Load76mA (_DCDC_BSTEM01CTRL_IPKVAL_Load76mA << 0) /**< Shifted mode Load76mA for DCDC_BSTEM01CTRL */ -#define DCDC_BSTEM01CTRL_IPKVAL_Load80mA (_DCDC_BSTEM01CTRL_IPKVAL_Load80mA << 0) /**< Shifted mode Load80mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load10mA (_DCDC_BSTEM01CTRL_IPKVAL_Load10mA << 0) /**< Shifted mode Load10mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load11mA (_DCDC_BSTEM01CTRL_IPKVAL_Load11mA << 0) /**< Shifted mode Load11mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load13mA (_DCDC_BSTEM01CTRL_IPKVAL_Load13mA << 0) /**< Shifted mode Load13mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load15mA (_DCDC_BSTEM01CTRL_IPKVAL_Load15mA << 0) /**< Shifted mode Load15mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load16mA (_DCDC_BSTEM01CTRL_IPKVAL_Load16mA << 0) /**< Shifted mode Load16mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load18mA (_DCDC_BSTEM01CTRL_IPKVAL_Load18mA << 0) /**< Shifted mode Load18mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load20mA (_DCDC_BSTEM01CTRL_IPKVAL_Load20mA << 0) /**< Shifted mode Load20mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load21mA (_DCDC_BSTEM01CTRL_IPKVAL_Load21mA << 0) /**< Shifted mode Load21mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load23mA (_DCDC_BSTEM01CTRL_IPKVAL_Load23mA << 0) /**< Shifted mode Load23mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load25mA (_DCDC_BSTEM01CTRL_IPKVAL_Load25mA << 0) /**< Shifted mode Load25mA for DCDC_BSTEM01CTRL */ #define _DCDC_BSTEM01CTRL_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ #define _DCDC_BSTEM01CTRL_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ #define _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_BSTEM01CTRL */ diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dma_descriptor.h index 0851a1ac01..9052e8ffed 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_dma_descriptor.h @@ -27,6 +27,8 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32BG27_DMA_DESCRIPTOR_H +#define EFR32BG27_DMA_DESCRIPTOR_H #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ @@ -53,3 +55,5 @@ typedef struct { } DMA_DESCRIPTOR_TypeDef; /**< @} */ /** @} End of group Parts */ + +#endif /* EFR32BG27_DMA_DESCRIPTOR_H */ diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_emu.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_emu.h index 6e80bf92e7..98f24d9174 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_emu.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_emu.h @@ -69,7 +69,7 @@ typedef struct { __IOM uint32_t DGIF; /**< Interrupt Flags Debug */ __IOM uint32_t DGIEN; /**< Interrupt Enables Debug */ uint32_t RESERVED7[5U]; /**< Reserved for future use */ - __IOM uint32_t BOOSTCTRL; /**< EMU boost mode controller reigsiters */ + __IOM uint32_t BOOSTCTRL; /**< EMU boost mode controller register */ uint32_t RESERVED8[1U]; /**< Reserved for future use */ uint32_t RESERVED9[15U]; /**< Reserved for future use */ __IOM uint32_t EFPIF; /**< EFP Interrupt Register */ @@ -103,7 +103,7 @@ typedef struct { __IOM uint32_t DGIF_SET; /**< Interrupt Flags Debug */ __IOM uint32_t DGIEN_SET; /**< Interrupt Enables Debug */ uint32_t RESERVED20[5U]; /**< Reserved for future use */ - __IOM uint32_t BOOSTCTRL_SET; /**< EMU boost mode controller reigsiters */ + __IOM uint32_t BOOSTCTRL_SET; /**< EMU boost mode controller register */ uint32_t RESERVED21[1U]; /**< Reserved for future use */ uint32_t RESERVED22[15U]; /**< Reserved for future use */ __IOM uint32_t EFPIF_SET; /**< EFP Interrupt Register */ @@ -137,7 +137,7 @@ typedef struct { __IOM uint32_t DGIF_CLR; /**< Interrupt Flags Debug */ __IOM uint32_t DGIEN_CLR; /**< Interrupt Enables Debug */ uint32_t RESERVED33[5U]; /**< Reserved for future use */ - __IOM uint32_t BOOSTCTRL_CLR; /**< EMU boost mode controller reigsiters */ + __IOM uint32_t BOOSTCTRL_CLR; /**< EMU boost mode controller register */ uint32_t RESERVED34[1U]; /**< Reserved for future use */ uint32_t RESERVED35[15U]; /**< Reserved for future use */ __IOM uint32_t EFPIF_CLR; /**< EFP Interrupt Register */ @@ -171,7 +171,7 @@ typedef struct { __IOM uint32_t DGIF_TGL; /**< Interrupt Flags Debug */ __IOM uint32_t DGIEN_TGL; /**< Interrupt Enables Debug */ uint32_t RESERVED46[5U]; /**< Reserved for future use */ - __IOM uint32_t BOOSTCTRL_TGL; /**< EMU boost mode controller reigsiters */ + __IOM uint32_t BOOSTCTRL_TGL; /**< EMU boost mode controller register */ uint32_t RESERVED47[1U]; /**< Reserved for future use */ uint32_t RESERVED48[15U]; /**< Reserved for future use */ __IOM uint32_t EFPIF_TGL; /**< EFP Interrupt Register */ @@ -710,7 +710,7 @@ typedef struct { #define _EMU_RSTCAUSE_DCI_MASK 0x10000UL /**< Bit mask for EMU_DCI */ #define _EMU_RSTCAUSE_DCI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ #define EMU_RSTCAUSE_DCI_DEFAULT (_EMU_RSTCAUSE_DCI_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_BOOSTON (0x1UL << 18) /**< BOOSTON PIN reset */ +#define EMU_RSTCAUSE_BOOSTON (0x1UL << 18) /**< BOOST_EN pin reset */ #define _EMU_RSTCAUSE_BOOSTON_SHIFT 18 /**< Shift value for EMU_BOOSTON */ #define _EMU_RSTCAUSE_BOOSTON_MASK 0x40000UL /**< Bit mask for EMU_BOOSTON */ #define _EMU_RSTCAUSE_BOOSTON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ @@ -772,7 +772,7 @@ typedef struct { /* Bit fields for EMU BOOSTCTRL */ #define _EMU_BOOSTCTRL_RESETVALUE 0x00000001UL /**< Default value for EMU_BOOSTCTRL */ #define _EMU_BOOSTCTRL_MASK 0x00000001UL /**< Mask for EMU_BOOSTCTRL */ -#define EMU_BOOSTCTRL_BOOSTENCTRL (0x1UL << 0) /**< BOOST_EN_CTRL BIT */ +#define EMU_BOOSTCTRL_BOOSTENCTRL (0x1UL << 0) /**< BOOST_EN Control */ #define _EMU_BOOSTCTRL_BOOSTENCTRL_SHIFT 0 /**< Shift value for EMU_BOOSTENCTRL */ #define _EMU_BOOSTCTRL_BOOSTENCTRL_MASK 0x1UL /**< Bit mask for EMU_BOOSTENCTRL */ #define _EMU_BOOSTCTRL_BOOSTENCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BOOSTCTRL */ diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpio.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpio.h index 806b70745b..4b43eaa54f 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpio.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpio.h @@ -651,151 +651,151 @@ typedef struct { #define _GPIO_EXTIPINSELL_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET0 << 0) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET1 << 0) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET2 << 0) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET3 << 0) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 << 0) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 << 0) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 << 0) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 << 0) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET0 << 4) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET1 << 4) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET2 << 4) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET3 << 4) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 << 4) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 << 4) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 << 4) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 << 4) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET0 << 8) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET1 << 8) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET2 << 8) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET3 << 8) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 << 8) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 << 8) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 << 8) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 << 8) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET0 << 12) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET1 << 12) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET2 << 12) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET3 << 12) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 << 12) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 << 12) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 << 12) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 << 12) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET0 << 16) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET1 << 16) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET2 << 16) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET3 << 16) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 << 16) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 << 16) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 << 16) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 << 16) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET0 << 20) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET1 << 20) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET2 << 20) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET3 << 20) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 << 20) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 << 20) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 << 20) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 << 20) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET0 << 24) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET1 << 24) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET2 << 24) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET3 << 24) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 << 24) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 << 24) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 << 24) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 << 24) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET0 << 28) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET1 << 28) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET2 << 28) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET3 << 28) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 << 28) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 << 28) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 << 28) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 << 28) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ /* Bit fields for GPIO EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_MASK 0x00003333UL /**< Mask for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET8 0x00000000UL /**< Mode OFFSET8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET9 0x00000001UL /**< Mode OFFSET9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET10 0x00000002UL /**< Mode OFFSET10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET11 0x00000003UL /**< Mode OFFSET11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET8 (_GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET8 << 0) /**< Shifted mode OFFSET8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET9 (_GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET9 << 0) /**< Shifted mode OFFSET9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET10 (_GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET10 << 0) /**< Shifted mode OFFSET10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET11 (_GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET11 << 0) /**< Shifted mode OFFSET11 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET8 0x00000000UL /**< Mode OFFSET8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET9 0x00000001UL /**< Mode OFFSET9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET10 0x00000002UL /**< Mode OFFSET10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET11 0x00000003UL /**< Mode OFFSET11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET8 (_GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET8 << 4) /**< Shifted mode OFFSET8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET9 (_GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET9 << 4) /**< Shifted mode OFFSET9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET10 (_GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET10 << 4) /**< Shifted mode OFFSET10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET11 (_GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET11 << 4) /**< Shifted mode OFFSET11 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET8 0x00000000UL /**< Mode OFFSET8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET9 0x00000001UL /**< Mode OFFSET9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET10 0x00000002UL /**< Mode OFFSET10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET11 0x00000003UL /**< Mode OFFSET11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET8 (_GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET8 << 8) /**< Shifted mode OFFSET8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET9 (_GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET9 << 8) /**< Shifted mode OFFSET9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET10 (_GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET10 << 8) /**< Shifted mode OFFSET10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET11 (_GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET11 << 8) /**< Shifted mode OFFSET11 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET8 0x00000000UL /**< Mode OFFSET8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET9 0x00000001UL /**< Mode OFFSET9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET10 0x00000002UL /**< Mode OFFSET10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET11 0x00000003UL /**< Mode OFFSET11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET8 (_GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET8 << 12) /**< Shifted mode OFFSET8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET9 (_GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET9 << 12) /**< Shifted mode OFFSET9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET10 (_GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET10 << 12) /**< Shifted mode OFFSET10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET11 (_GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET11 << 12) /**< Shifted mode OFFSET11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_MASK 0x00003333UL /**< Mask for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 << 0) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 << 0) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 << 0) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 << 0) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 << 4) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 << 4) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 << 4) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 << 4) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 << 8) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 << 8) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 << 8) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 << 8) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 << 12) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 << 12) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 << 12) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 << 12) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ /* Bit fields for GPIO EXTIRISE */ #define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */ diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldmaxbar_defines.h index 01442a6ce4..47abb18b74 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_ldmaxbar_defines.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32BG27_LDMAXBAR_DEFINES_H +#define EFR32BG27_LDMAXBAR_DEFINES_H + /* Module source selection indices */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ @@ -148,3 +151,5 @@ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF << 0) /** Shifted Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL << 0) /** Shifted Mode EUSART0RXFL for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL << 0) /** Shifted Mode EUSART0TXFL for LDMAXBAR_CH_REQSEL**/ + +#endif /* EFR32BG27_LDMAXBAR_DEFINES_H */ diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_prs_signals.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_prs_signals.h index ff0442f034..a4f3690078 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_prs_signals.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32BG27_PRS_SIGNALS_H +#define EFR32BG27_PRS_SIGNALS_H + /** Synchronous signal sources enumeration: */ #define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) #define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) @@ -875,3 +878,5 @@ #define PRS_LFRCO_CALMEAS (PRS_ASYNC_LFRCO_CALMEAS) #define PRS_LFRCO_SDM (PRS_ASYNC_LFRCO_SDM) #define PRS_LFRCO_TCMEAS (PRS_ASYNC_LFRCO_TCMEAS) + +#endif /* EFR32BG27_PRS_SIGNALS_H */ diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im32.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im32.h index f81cd5703d..35d9fc609e 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im32.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im32.h @@ -209,14 +209,14 @@ typedef enum IRQn{ #define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ #define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ #define USERDATA_BITS (0xBUL) /** USERDATA used bits */ -#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ -#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ -#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE085FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ -#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ -#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08600UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ #define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ -#define MSC_FLASH_DEVINFO_MEM_END (0x0FE089FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ #define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ #define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ #define DMEM_RAM0_RAM_MEM_SIZE (0x00010000UL) /** DMEM_RAM0_RAM_MEM available address space */ #define DMEM_RAM0_RAM_MEM_END (0x2000FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ @@ -632,227 +632,227 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S != 0))) #define SEPUF_APBCFG_BASE (SEPUF_S_APBCFG_BASE) /* SEPUF_APBCFG base address */ #else #define SEPUF_APBCFG_BASE (SEPUF_NS_APBCFG_BASE) /* SEPUF_APBCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) && (SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S != 0))) #define ETAMPDET_BASE (ETAMPDET_S_BASE) /* ETAMPDET base address */ #else #define ETAMPDET_BASE (ETAMPDET_NS_BASE) /* ETAMPDET base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im40.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im40.h index 01567bd0c5..41505f0a3d 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im40.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im40.h @@ -209,14 +209,14 @@ typedef enum IRQn{ #define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ #define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ #define USERDATA_BITS (0xBUL) /** USERDATA used bits */ -#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ -#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ -#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE085FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ -#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ -#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08600UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ #define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ -#define MSC_FLASH_DEVINFO_MEM_END (0x0FE089FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ #define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ #define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ #define DMEM_RAM0_RAM_MEM_SIZE (0x00010000UL) /** DMEM_RAM0_RAM_MEM available address space */ #define DMEM_RAM0_RAM_MEM_END (0x2000FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ @@ -648,227 +648,227 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S != 0))) #define SEPUF_APBCFG_BASE (SEPUF_S_APBCFG_BASE) /* SEPUF_APBCFG base address */ #else #define SEPUF_APBCFG_BASE (SEPUF_NS_APBCFG_BASE) /* SEPUF_APBCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) && (SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S != 0))) #define ETAMPDET_BASE (ETAMPDET_S_BASE) /* ETAMPDET base address */ #else #define ETAMPDET_BASE (ETAMPDET_NS_BASE) /* ETAMPDET base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im32.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im32.h index 0eb7398961..dc669873eb 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im32.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im32.h @@ -209,14 +209,14 @@ typedef enum IRQn{ #define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ #define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ #define USERDATA_BITS (0xBUL) /** USERDATA used bits */ -#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ -#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ -#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE085FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ -#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ -#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08600UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ #define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ -#define MSC_FLASH_DEVINFO_MEM_END (0x0FE089FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ #define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ #define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ #define DMEM_RAM0_RAM_MEM_SIZE (0x00010000UL) /** DMEM_RAM0_RAM_MEM available address space */ #define DMEM_RAM0_RAM_MEM_END (0x2000FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ @@ -627,227 +627,227 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S != 0))) #define SEPUF_APBCFG_BASE (SEPUF_S_APBCFG_BASE) /* SEPUF_APBCFG base address */ #else #define SEPUF_APBCFG_BASE (SEPUF_NS_APBCFG_BASE) /* SEPUF_APBCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) && (SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S != 0))) #define ETAMPDET_BASE (ETAMPDET_S_BASE) /* ETAMPDET base address */ #else #define ETAMPDET_BASE (ETAMPDET_NS_BASE) /* ETAMPDET base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im40.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im40.h index 176f11b687..eb93bfc7a0 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im40.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im40.h @@ -209,14 +209,14 @@ typedef enum IRQn{ #define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ #define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ #define USERDATA_BITS (0xBUL) /** USERDATA used bits */ -#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ -#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ -#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE085FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ -#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ -#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08600UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ #define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ -#define MSC_FLASH_DEVINFO_MEM_END (0x0FE089FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ #define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ #define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ #define DMEM_RAM0_RAM_MEM_SIZE (0x00010000UL) /** DMEM_RAM0_RAM_MEM available address space */ #define DMEM_RAM0_RAM_MEM_END (0x2000FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ @@ -647,227 +647,227 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S != 0))) #define SEPUF_APBCFG_BASE (SEPUF_S_APBCFG_BASE) /* SEPUF_APBCFG base address */ #else #define SEPUF_APBCFG_BASE (SEPUF_NS_APBCFG_BASE) /* SEPUF_APBCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) && (SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S != 0))) #define ETAMPDET_BASE (ETAMPDET_S_BASE) /* ETAMPDET base address */ #else #define ETAMPDET_BASE (ETAMPDET_NS_BASE) /* ETAMPDET base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c320f768gj39.h b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c320f768gj39.h index 94d3c63a1d..87eb0fac7f 100644 --- a/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c320f768gj39.h +++ b/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c320f768gj39.h @@ -209,14 +209,14 @@ typedef enum IRQn{ #define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ #define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ #define USERDATA_BITS (0xBUL) /** USERDATA used bits */ -#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ -#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ -#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE085FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ -#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ -#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08600UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ #define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ -#define MSC_FLASH_DEVINFO_MEM_END (0x0FE089FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ #define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ #define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ #define DMEM_RAM0_RAM_MEM_SIZE (0x00010000UL) /** DMEM_RAM0_RAM_MEM available address space */ #define DMEM_RAM0_RAM_MEM_END (0x2000FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ @@ -633,227 +633,227 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S != 0))) #define SEPUF_APBCFG_BASE (SEPUF_S_APBCFG_BASE) /* SEPUF_APBCFG base address */ #else #define SEPUF_APBCFG_BASE (SEPUF_NS_APBCFG_BASE) /* SEPUF_APBCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) && (SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S != 0))) #define ETAMPDET_BASE (ETAMPDET_S_BASE) /* ETAMPDET base address */ #else #define ETAMPDET_BASE (ETAMPDET_NS_BASE) /* ETAMPDET base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dma_descriptor.h index 1291d2c480..bf4e75dba2 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_dma_descriptor.h @@ -27,6 +27,8 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32FG22_DMA_DESCRIPTOR_H +#define EFR32FG22_DMA_DESCRIPTOR_H #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ @@ -53,3 +55,5 @@ typedef struct { } DMA_DESCRIPTOR_TypeDef; /**< @} */ /** @} End of group Parts */ + +#endif /* EFR32FG22_DMA_DESCRIPTOR_H */ diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldmaxbar_defines.h index 19988b4775..349c06a6b9 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_ldmaxbar_defines.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32FG22_LDMAXBAR_DEFINES_H +#define EFR32FG22_LDMAXBAR_DEFINES_H + /* Module source selection indices */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ @@ -148,3 +151,5 @@ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 << 0) /** Shifted Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 << 0) /** Shifted Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF << 0) /** Shifted Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ + +#endif /* EFR32FG22_LDMAXBAR_DEFINES_H */ diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_prs_signals.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_prs_signals.h index 6fddcc150b..5b694117da 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22_prs_signals.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32FG22_PRS_SIGNALS_H +#define EFR32FG22_PRS_SIGNALS_H + /** Synchronous signal sources enumeration: */ #define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) #define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) @@ -843,3 +846,5 @@ #define PRS_LFRCO_CALMEAS (PRS_ASYNC_LFRCO_CALMEAS) #define PRS_LFRCO_SDM (PRS_ASYNC_LFRCO_SDM) #define PRS_LFRCO_TCMEAS (PRS_ASYNC_LFRCO_TCMEAS) + +#endif /* EFR32FG22_PRS_SIGNALS_H */ diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f256gm32.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f256gm32.h index 40005232f5..e817b31d80 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f256gm32.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f256gm32.h @@ -574,222 +574,222 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f256gm40.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f256gm40.h index ec3b3901f1..5f0e6a619d 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f256gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f256gm40.h @@ -588,222 +588,222 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f512gm32.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f512gm32.h index d3913cb6cf..fb503635d3 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f512gm32.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f512gm32.h @@ -574,222 +574,222 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f512gm40.h b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f512gm40.h index e8c36ad744..7f26c0b0d5 100644 --- a/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f512gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG22/Include/efr32fg22c121f512gm40.h @@ -588,222 +588,222 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dma_descriptor.h index 8efe2d6aaf..37bfa33648 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_dma_descriptor.h @@ -27,6 +27,8 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32FG23_DMA_DESCRIPTOR_H +#define EFR32FG23_DMA_DESCRIPTOR_H #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ @@ -53,3 +55,5 @@ typedef struct { } DMA_DESCRIPTOR_TypeDef; /**< @} */ /** @} End of group Parts */ + +#endif /* EFR32FG23_DMA_DESCRIPTOR_H */ diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldmaxbar_defines.h index 2229840c2b..cbd3f48f4f 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_ldmaxbar_defines.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32FG23_LDMAXBAR_DEFINES_H +#define EFR32FG23_LDMAXBAR_DEFINES_H + /* Module source selection indices */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ @@ -158,3 +161,5 @@ #define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL << 0) /** Shifted Mode EUSART2TXFL for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO (_LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO << 0) /** Shifted Mode LESENSEFIFO for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_LCD (_LDMAXBAR_CH_REQSEL_SIGSEL_LCD << 0) /** Shifted Mode LCD for LDMAXBAR_CH_REQSEL**/ + +#endif /* EFR32FG23_LDMAXBAR_DEFINES_H */ diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_prs_signals.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_prs_signals.h index 3e7be6e67c..cb1c8c1765 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_prs_signals.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32FG23_PRS_SIGNALS_H +#define EFR32FG23_PRS_SIGNALS_H + /** Synchronous signal sources enumeration: */ #define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) #define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) @@ -971,3 +974,5 @@ #define PRS_EUSART2L_TXC (PRS_ASYNC_EUSART2L_TXC) #define PRS_EUSART2L_RXFL (PRS_ASYNC_EUSART2L_RXFL) #define PRS_EUSART2L_TXFL (PRS_ASYNC_EUSART2L_TXFL) + +#endif /* EFR32FG23_PRS_SIGNALS_H */ diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f128gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f128gm40.h index fab17d391d..d160f35dc6 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f128gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f128gm40.h @@ -626,267 +626,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm40.h index cc7ae29d3d..c59b55af39 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm40.h @@ -626,267 +626,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm48.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm48.h index 3fe62f2e78..6e49081879 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm48.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm48.h @@ -697,277 +697,277 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm40.h index 1a3eb2901f..5c42364631 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm40.h @@ -626,267 +626,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm48.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm48.h index 603606f518..f75509993d 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm48.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm48.h @@ -697,277 +697,277 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a011f512gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a011f512gm40.h index 46bf4d6e7f..89e9b3aa0c 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a011f512gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a011f512gm40.h @@ -623,267 +623,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f128gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f128gm40.h index 623ea42a3b..b35389d370 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f128gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f128gm40.h @@ -626,267 +626,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm40.h index 3a26d8a0be..fae225a32f 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm40.h @@ -626,267 +626,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm48.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm48.h index dbfe1fecdc..4babfd85b1 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm48.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm48.h @@ -697,277 +697,277 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm40.h index 8f35db3c1a..26587ea65e 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm40.h @@ -626,267 +626,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm48.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm48.h index 7074f294e3..1c5c0c5066 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm48.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm48.h @@ -697,277 +697,277 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a021f512gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a021f512gm40.h index ef105f1862..bb491980fe 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a021f512gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a021f512gm40.h @@ -623,267 +623,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f128gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f128gm40.h index 0fde683723..7a4f5306f5 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f128gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f128gm40.h @@ -627,267 +627,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512gm48.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512gm48.h index 74259c474d..f3baea044a 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512gm48.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512gm48.h @@ -698,277 +698,277 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im40.h index f4bad2b6fc..cee622b4be 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im40.h @@ -627,267 +627,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im48.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im48.h index c42c7ac336..357c351ade 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im48.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im48.h @@ -698,277 +698,277 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f128gm40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f128gm40.h index 3dfa9703be..62af081890 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f128gm40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f128gm40.h @@ -627,267 +627,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im40.h index 194e73e80c..a87a6ccf35 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im40.h @@ -627,267 +627,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im48.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im48.h index a354ae2630..c5ecc0c8d6 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im48.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im48.h @@ -698,277 +698,277 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im40.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im40.h index e189a4ce9a..4caac287e3 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im40.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im40.h @@ -624,267 +624,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im48.h b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im48.h new file mode 100644 index 0000000000..8fa4b53983 --- /dev/null +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im48.h @@ -0,0 +1,1579 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32FG23B021F512IM48 + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32FG23B021F512IM48_H +#define EFR32FG23B021F512IM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32FG23B021F512IM48 EFR32FG23B021F512IM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32FG23 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + EUSART2_RX_IRQn = 15, /*!< 15 EFR32 EUSART2_RX Interrupt */ + EUSART2_TX_IRQn = 16, /*!< 16 EFR32 EUSART2_TX Interrupt */ + ICACHE0_IRQn = 17, /*!< 17 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 18, /*!< 18 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 19, /*!< 19 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 20, /*!< 20 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 21, /*!< 21 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 22, /*!< 22 EFR32 LDMA Interrupt */ + LFXO_IRQn = 23, /*!< 23 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 24, /*!< 24 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 25, /*!< 25 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 26, /*!< 26 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 27, /*!< 27 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 28, /*!< 28 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 29, /*!< 29 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 30, /*!< 30 EFR32 EMUDG Interrupt */ + AGC_IRQn = 31, /*!< 31 EFR32 AGC Interrupt */ + BUFC_IRQn = 32, /*!< 32 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 33, /*!< 33 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 34, /*!< 34 EFR32 FRC Interrupt */ + MODEM_IRQn = 35, /*!< 35 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 36, /*!< 36 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 37, /*!< 37 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 38, /*!< 38 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 39, /*!< 39 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 40, /*!< 40 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 41, /*!< 41 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 42, /*!< 42 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 43, /*!< 43 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 44, /*!< 44 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 45, /*!< 45 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 46, /*!< 46 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 47, /*!< 47 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 48, /*!< 48 EFR32 CMU Interrupt */ + AES_IRQn = 49, /*!< 49 EFR32 AES Interrupt */ + IADC_IRQn = 50, /*!< 50 EFR32 IADC Interrupt */ + MSC_IRQn = 51, /*!< 51 EFR32 MSC Interrupt */ + DPLL0_IRQn = 52, /*!< 52 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 53, /*!< 53 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 54, /*!< 54 EFR32 DCDC Interrupt */ + VDAC_IRQn = 55, /*!< 55 EFR32 VDAC Interrupt */ + PCNT0_IRQn = 56, /*!< 56 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 57, /*!< 57 EFR32 SW0 Interrupt */ + SW1_IRQn = 58, /*!< 58 EFR32 SW1 Interrupt */ + SW2_IRQn = 59, /*!< 59 EFR32 SW2 Interrupt */ + SW3_IRQn = 60, /*!< 60 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 61, /*!< 61 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 62, /*!< 62 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 63, /*!< 63 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 64, /*!< 64 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 65, /*!< 65 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 66, /*!< 66 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 67, /*!< 67 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 68, /*!< 68 EFR32 SEMBTX Interrupt */ + LESENSE_IRQn = 69, /*!< 69 EFR32 LESENSE Interrupt */ + SYSRTC_APP_IRQn = 70, /*!< 70 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 71, /*!< 71 EFR32 SYSRTC_SEQ Interrupt */ + LCD_IRQn = 72, /*!< 72 EFR32 LCD Interrupt */ + KEYSCAN_IRQn = 73, /*!< 73 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 74, /*!< 74 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 75, /*!< 75 EFR32 RFECA1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32FG23B021F512IM48_Core EFR32FG23B021F512IM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32FG23B021F512IM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32FG23B021F512IM48_Part EFR32FG23B021F512IM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32FG23B021F512IM48) +#define EFR32FG23B021F512IM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32FG23B021F512IM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_FLEX_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_FG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_3 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 3 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 210 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_210 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /** Radio type */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio SUBGHZ HP PA output power */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT /** Radio SUBGHZ HP PA is present */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00080000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0807FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x14UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00080000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0807FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x14UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00010000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2000FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x11UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00010000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2000FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x11UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32FG23B021F512IM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00010000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 11U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x07FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PA_PIN10 1U /**< GPIO pin PA10 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 4U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x000FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 9U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x01FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 8U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_EN_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_EN_PRIMARY_PIN 9U /**< Pin of THMSW_EN_PRIMARY.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LCD_COM0_PORT GPIO_PD_INDEX /**< Port of COM0.*/ +#define LCD_COM0_PIN 2U /**< Pin of COM0.*/ +#define LCD_COM1_PORT GPIO_PD_INDEX /**< Port of COM1.*/ +#define LCD_COM1_PIN 3U /**< Pin of COM1.*/ +#define LCD_COM2_PORT GPIO_PD_INDEX /**< Port of COM2.*/ +#define LCD_COM2_PIN 4U /**< Pin of COM2.*/ +#define LCD_COM3_PORT GPIO_PD_INDEX /**< Port of COM3.*/ +#define LCD_COM3_PIN 5U /**< Pin of COM3.*/ +#define LCD_LCD_CP_PORT GPIO_PA_INDEX /**< Port of LCD_CP.*/ +#define LCD_LCD_CP_PIN 6U /**< Pin of LCD_CP.*/ +#define LCD_SEG0_PORT GPIO_PC_INDEX /**< Port of SEG0.*/ +#define LCD_SEG0_PIN 0U /**< Pin of SEG0.*/ +#define LCD_SEG1_PORT GPIO_PC_INDEX /**< Port of SEG1.*/ +#define LCD_SEG1_PIN 1U /**< Pin of SEG1.*/ +#define LCD_SEG10_PORT GPIO_PA_INDEX /**< Port of SEG10.*/ +#define LCD_SEG10_PIN 4U /**< Pin of SEG10.*/ +#define LCD_SEG11_PORT GPIO_PA_INDEX /**< Port of SEG11.*/ +#define LCD_SEG11_PIN 5U /**< Pin of SEG11.*/ +#define LCD_SEG12_PORT GPIO_PA_INDEX /**< Port of SEG12.*/ +#define LCD_SEG12_PIN 7U /**< Pin of SEG12.*/ +#define LCD_SEG13_PORT GPIO_PA_INDEX /**< Port of SEG13.*/ +#define LCD_SEG13_PIN 8U /**< Pin of SEG13.*/ +#define LCD_SEG14_PORT GPIO_PB_INDEX /**< Port of SEG14.*/ +#define LCD_SEG14_PIN 0U /**< Pin of SEG14.*/ +#define LCD_SEG15_PORT GPIO_PB_INDEX /**< Port of SEG15.*/ +#define LCD_SEG15_PIN 1U /**< Pin of SEG15.*/ +#define LCD_SEG16_PORT GPIO_PB_INDEX /**< Port of SEG16.*/ +#define LCD_SEG16_PIN 2U /**< Pin of SEG16.*/ +#define LCD_SEG17_PORT GPIO_PB_INDEX /**< Port of SEG17.*/ +#define LCD_SEG17_PIN 3U /**< Pin of SEG17.*/ +#define LCD_SEG18_PORT GPIO_PC_INDEX /**< Port of SEG18.*/ +#define LCD_SEG18_PIN 8U /**< Pin of SEG18.*/ +#define LCD_SEG19_PORT GPIO_PC_INDEX /**< Port of SEG19.*/ +#define LCD_SEG19_PIN 8U /**< Pin of SEG19.*/ +#define LCD_SEG19_PRIMARY_PORT GPIO_PC_INDEX /**< Port of SEG19_PRIMARY.*/ +#define LCD_SEG19_PRIMARY_PIN 9U /**< Pin of SEG19_PRIMARY.*/ +#define LCD_SEG2_PORT GPIO_PC_INDEX /**< Port of SEG2.*/ +#define LCD_SEG2_PIN 2U /**< Pin of SEG2.*/ +#define LCD_SEG3_PORT GPIO_PC_INDEX /**< Port of SEG3.*/ +#define LCD_SEG3_PIN 3U /**< Pin of SEG3.*/ +#define LCD_SEG4_PORT GPIO_PC_INDEX /**< Port of SEG4.*/ +#define LCD_SEG4_PIN 4U /**< Pin of SEG4.*/ +#define LCD_SEG5_PORT GPIO_PC_INDEX /**< Port of SEG5.*/ +#define LCD_SEG5_PIN 5U /**< Pin of SEG5.*/ +#define LCD_SEG6_PORT GPIO_PC_INDEX /**< Port of SEG6.*/ +#define LCD_SEG6_PIN 6U /**< Pin of SEG6.*/ +#define LCD_SEG7_PORT GPIO_PC_INDEX /**< Port of SEG7.*/ +#define LCD_SEG7_PIN 7U /**< Pin of SEG7.*/ +#define LCD_SEG8_PORT GPIO_PA_INDEX /**< Port of SEG8.*/ +#define LCD_SEG8_PIN 0U /**< Pin of SEG8.*/ +#define LCD_SEG9_PORT GPIO_PA_INDEX /**< Port of SEG9.*/ +#define LCD_SEG9_PIN 1U /**< Pin of SEG9.*/ +#define LESENSE_EN_0_PORT GPIO_PA_INDEX /**< Port of EN_0.*/ +#define LESENSE_EN_0_PIN 3U /**< Pin of EN_0.*/ +#define LESENSE_EN_1_PORT GPIO_PA_INDEX /**< Port of EN_1.*/ +#define LESENSE_EN_1_PIN 4U /**< Pin of EN_1.*/ +#define LESENSE_EN_2_PORT GPIO_PA_INDEX /**< Port of EN_2.*/ +#define LESENSE_EN_2_PIN 5U /**< Pin of EN_2.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ +#define VDAC0_CH0_MAIN_OUT_PIN 0U /**< Pin of CH0_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PIN 1U /**< Pin of CH1_MAIN_OUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define AMUXCP_PRESENT /** AMUXCP is available in this part */ +#define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 3 /** 3 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LCD_PRESENT /** LCD is available in this part */ +#define LCD_COUNT 1 /** 1 LCDs available */ +#define LCDRF_PRESENT /** LCDRF is available in this part */ +#define LCDRF_COUNT 1 /** 1 LCDRFs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LESENSE_PRESENT /** LESENSE is available in this part */ +#define LESENSE_COUNT 1 /** 1 LESENSEs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PFMXPPRF_PRESENT /** PFMXPPRF is available in this part */ +#define PFMXPPRF_COUNT 1 /** 1 PFMXPPRFs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 1 /** 1 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32fg23.h" /* System Header File */ + +/** @} End of group EFR32FG23B021F512IM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32FG23B021F512IM48_Peripheral_TypeDefs EFR32FG23B021F512IM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32fg23_scratchpad.h" +#include "efr32fg23_emu.h" +#include "efr32fg23_cmu.h" +#include "efr32fg23_hfrco.h" +#include "efr32fg23_fsrco.h" +#include "efr32fg23_dpll.h" +#include "efr32fg23_lfxo.h" +#include "efr32fg23_lfrco.h" +#include "efr32fg23_ulfrco.h" +#include "efr32fg23_msc.h" +#include "efr32fg23_icache.h" +#include "efr32fg23_prs.h" +#include "efr32fg23_gpio.h" +#include "efr32fg23_ldma.h" +#include "efr32fg23_ldmaxbar.h" +#include "efr32fg23_timer.h" +#include "efr32fg23_usart.h" +#include "efr32fg23_burtc.h" +#include "efr32fg23_i2c.h" +#include "efr32fg23_syscfg.h" +#include "efr32fg23_buram.h" +#include "efr32fg23_gpcrc.h" +#include "efr32fg23_dcdc.h" +#include "efr32fg23_mailbox.h" +#include "efr32fg23_eusart.h" +#include "efr32fg23_sysrtc.h" +#include "efr32fg23_lcd.h" +#include "efr32fg23_keyscan.h" +#include "efr32fg23_mpahbram.h" +#include "efr32fg23_lcdrf.h" +#include "efr32fg23_pfmxpprf.h" +#include "efr32fg23_aes.h" +#include "efr32fg23_smu.h" +#include "efr32fg23_letimer.h" +#include "efr32fg23_iadc.h" +#include "efr32fg23_acmp.h" +#include "efr32fg23_amuxcp.h" +#include "efr32fg23_vdac.h" +#include "efr32fg23_pcnt.h" +#include "efr32fg23_lesense.h" +#include "efr32fg23_hfxo.h" +#include "efr32fg23_wdog.h" +#include "efr32fg23_semailbox.h" +#include "efr32fg23_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32fg23_prs_signals.h" +#include "efr32fg23_dma_descriptor.h" +#include "efr32fg23_ldmaxbar_defines.h" + +/** @} End of group EFR32FG23B021F512IM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32FG23B021F512IM48_Peripheral_Base EFR32FG23B021F512IM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define EUSART2_S_BASE (0x400A4000UL) /* EUSART2_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define LCD_S_BASE (0x400AC000UL) /* LCD_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define LCDRF_S_BASE (0x400C0000UL) /* LCDRF_S base address */ +#define PFMXPPRF_S_BASE (0x400C4000UL) /* PFMXPPRF_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define AMUXCP0_S_BASE (0x49020000UL) /* AMUXCP0_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define LESENSE_S_BASE (0x49038000UL) /* LESENSE_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define EUSART2_NS_BASE (0x500A4000UL) /* EUSART2_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define LCD_NS_BASE (0x500AC000UL) /* LCD_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define LCDRF_NS_BASE (0x500C0000UL) /* LCDRF_NS base address */ +#define PFMXPPRF_NS_BASE (0x500C4000UL) /* PFMXPPRF_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define AMUXCP0_NS_BASE (0x59020000UL) /* AMUXCP0_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define LESENSE_NS_BASE (0x59038000UL) /* LESENSE_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) +#define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ +#else +#define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) +#define LCD_BASE (LCD_S_BASE) /* LCD base address */ +#else +#define LCD_BASE (LCD_NS_BASE) /* LCD base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) +#define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ +#else +#define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) +#define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ +#else +#define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) +#define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ +#else +#define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) +#define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ +#else +#define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32FG23B021F512IM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32FG23B021F512IM48_Peripheral_Declaration EFR32FG23B021F512IM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define EUSART2_S ((EUSART_TypeDef *) EUSART2_S_BASE) /**< EUSART2_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define LCD_S ((LCD_TypeDef *) LCD_S_BASE) /**< LCD_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define LCDRF_S ((LCDRF_TypeDef *) LCDRF_S_BASE) /**< LCDRF_S base pointer */ +#define PFMXPPRF_S ((PFMXPPRF_TypeDef *) PFMXPPRF_S_BASE) /**< PFMXPPRF_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define LESENSE_S ((LESENSE_TypeDef *) LESENSE_S_BASE) /**< LESENSE_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define EUSART2_NS ((EUSART_TypeDef *) EUSART2_NS_BASE) /**< EUSART2_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define LCD_NS ((LCD_TypeDef *) LCD_NS_BASE) /**< LCD_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define LCDRF_NS ((LCDRF_TypeDef *) LCDRF_NS_BASE) /**< LCDRF_NS base pointer */ +#define PFMXPPRF_NS ((PFMXPPRF_TypeDef *) PFMXPPRF_NS_BASE) /**< PFMXPPRF_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define LESENSE_NS ((LESENSE_TypeDef *) LESENSE_NS_BASE) /**< LESENSE_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define EUSART2 ((EUSART_TypeDef *) EUSART2_BASE) /**< EUSART2 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define LCDRF ((LCDRF_TypeDef *) LCDRF_BASE) /**< LCDRF base pointer */ +#define PFMXPPRF ((PFMXPPRF_TypeDef *) PFMXPPRF_BASE) /**< PFMXPPRF base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32FG23B021F512IM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32FG23B021F512IM48_Peripheral_Parameters EFR32FG23B021F512IM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x2000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x2000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x2000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x2000UL /**> Bank7 size */ +#define DMEM_NUM_BANKS 0x4UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x2UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x1UL /**> Boolean indicating if NUM_PORTS=2 */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x14UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x14UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0x50UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x80000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x80000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x5UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0xCUL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_COMALLOC_WIDTH 0x4UL /**> New Param */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x6UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x4UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xBUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x3UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x7UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x7UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SEGALLOC_WIDTH 0x14UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x38UL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define EUSART2_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART2_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define LCD_COM_NUM 0x4UL /**> None */ +#define LCD_NO_ANIM_LOCS 0x1UL /**> None */ +#define LCD_NO_BANKED_SEG 0x1UL /**> */ +#define LCD_NO_DSC 0x0UL /**> None */ +#define LCD_NO_EXTOSC 0x0UL /**> None */ +#define LCD_NO_UPPER_SEGMENTS 0x1UL /**> */ +#define LCD_OCTAPLEX 0x0UL /**> None */ +#define LCD_SEGASCOM_NUM 0x4UL /**> None */ +#define LCD_SEG_NUM 0x14UL /**> None */ +#define LCD_SEL_WIDTH 0x3UL /**> None */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define PFMXPPRF_COUNT_WIDTH 0x9UL /**> Width of counters for pulse-pairing */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x7UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x39UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x19UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x19UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define LESENSE_CHANNEL_NUM 0x10UL /**> None */ +#define LESENSE_RIPCNT_WIDTH 0x10UL /**> None */ +#define LESENSE_STATE_NUM 0x20UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32FG23B021F512IM48_Peripheral_Parameters */ + +/** @} End of group EFR32FG23B021F512IM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/platform/Device/SiliconLabs/EFR32FG23/Include/em_device.h b/platform/Device/SiliconLabs/EFR32FG23/Include/em_device.h index ac4df678f3..0f54aa7700 100644 --- a/platform/Device/SiliconLabs/EFR32FG23/Include/em_device.h +++ b/platform/Device/SiliconLabs/EFR32FG23/Include/em_device.h @@ -101,6 +101,9 @@ #elif defined(EFR32FG23B021F512IM40) #include "efr32fg23b021f512im40.h" +#elif defined(EFR32FG23B021F512IM48) +#include "efr32fg23b021f512im48.h" + #else #error "em_device.h: PART NUMBER undefined" #endif diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_devinfo.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_devinfo.h index 041b6d2deb..5db80cb9cf 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_devinfo.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_devinfo.h @@ -113,7 +113,7 @@ typedef struct { *****************************************************************************/ /* Bit fields for DEVINFO INFO */ -#define _DEVINFO_INFO_RESETVALUE 0x0F000000UL /**< Default value for DEVINFO_INFO */ +#define _DEVINFO_INFO_RESETVALUE 0x11000000UL /**< Default value for DEVINFO_INFO */ #define _DEVINFO_INFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_INFO */ #define _DEVINFO_INFO_CRC_SHIFT 0 /**< Shift value for DEVINFO_CRC */ #define _DEVINFO_INFO_CRC_MASK 0xFFFFUL /**< Bit mask for DEVINFO_CRC */ @@ -125,7 +125,7 @@ typedef struct { #define DEVINFO_INFO_PRODREV_DEFAULT (_DEVINFO_INFO_PRODREV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_INFO */ #define _DEVINFO_INFO_DEVINFOREV_SHIFT 24 /**< Shift value for DEVINFO_DEVINFOREV */ #define _DEVINFO_INFO_DEVINFOREV_MASK 0xFF000000UL /**< Bit mask for DEVINFO_DEVINFOREV */ -#define _DEVINFO_INFO_DEVINFOREV_DEFAULT 0x0000000FUL /**< Mode DEFAULT for DEVINFO_INFO */ +#define _DEVINFO_INFO_DEVINFOREV_DEFAULT 0x00000011UL /**< Mode DEFAULT for DEVINFO_INFO */ #define DEVINFO_INFO_DEVINFOREV_DEFAULT (_DEVINFO_INFO_DEVINFOREV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_INFO */ /* Bit fields for DEVINFO PART */ diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dma_descriptor.h index 228caf8f5b..52e92a043a 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_dma_descriptor.h @@ -27,6 +27,8 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32FG25_DMA_DESCRIPTOR_H +#define EFR32FG25_DMA_DESCRIPTOR_H #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ @@ -53,3 +55,5 @@ typedef struct { } DMA_DESCRIPTOR_TypeDef; /**< @} */ /** @} End of group Parts */ + +#endif /* EFR32FG25_DMA_DESCRIPTOR_H */ diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldmaxbar_defines.h index 98ed4717c1..5e5ef63701 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_ldmaxbar_defines.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32FG25_LDMAXBAR_DEFINES_H +#define EFR32FG25_LDMAXBAR_DEFINES_H + /* Module source selection indices */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ @@ -184,3 +187,5 @@ #define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL << 0) /** Shifted Mode EUSART4RXFL for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL << 0) /** Shifted Mode EUSART4TXFL for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO (_LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO << 0) /** Shifted Mode LESENSEFIFO for LDMAXBAR_CH_REQSEL**/ + +#endif /* EFR32FG25_LDMAXBAR_DEFINES_H */ diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_prs_signals.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_prs_signals.h index a27c0b61d5..1a804429db 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_prs_signals.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32FG25_PRS_SIGNALS_H +#define EFR32FG25_PRS_SIGNALS_H + /** Synchronous signal sources enumeration: */ #define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) #define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) @@ -1220,3 +1223,5 @@ #define PRS_SMCTRL_SOFTM9 (PRS_ASYNC_SMCTRL_SOFTM9) #define PRS_SMCTRL_SOFTM10 (PRS_ASYNC_SMCTRL_SOFTM10) #define PRS_SMCTRL_SOFTM11 (PRS_ASYNC_SMCTRL_SOFTM11) + +#endif /* EFR32FG25_PRS_SIGNALS_H */ diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a111f1152im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a111f1152im56.h index a196ec0e51..7a4efa7e53 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a111f1152im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a111f1152im56.h @@ -207,7 +207,7 @@ typedef enum IRQn{ #define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ #define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ #define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /** Radio type */ -#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 14 /** Radio SUBGHZ HP PA output power */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 16 /** Radio SUBGHZ HP PA output power */ #define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT /** Radio SUBGHZ HP PA is present */ /** Memory Base addresses and limits */ @@ -740,317 +740,317 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER5_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER5_S != 0))) #define TIMER5_BASE (TIMER5_S_BASE) /* TIMER5 base address */ #else #define TIMER5_BASE (TIMER5_NS_BASE) /* TIMER5 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER5_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER6_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER6_S != 0))) #define TIMER6_BASE (TIMER6_S_BASE) /* TIMER6 base address */ #else #define TIMER6_BASE (TIMER6_NS_BASE) /* TIMER6 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER6_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER7_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER7_S != 0))) #define TIMER7_BASE (TIMER7_S_BASE) /* TIMER7 base address */ #else #define TIMER7_BASE (TIMER7_NS_BASE) /* TIMER7 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER7_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART3_S != 0))) #define EUSART3_BASE (EUSART3_S_BASE) /* EUSART3 base address */ #else #define EUSART3_BASE (EUSART3_NS_BASE) /* EUSART3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART4_S != 0))) #define EUSART4_BASE (EUSART4_S_BASE) /* EUSART4 base address */ #else #define EUSART4_BASE (EUSART4_NS_BASE) /* EUSART4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S != 0))) #define RFFPLL0_BASE (RFFPLL0_S_BASE) /* RFFPLL0 base address */ #else #define RFFPLL0_BASE (RFFPLL0_NS_BASE) /* RFFPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) && (SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S != 0))) #define ETAMPDET_BASE (ETAMPDET_S_BASE) /* ETAMPDET base address */ #else #define ETAMPDET_BASE (ETAMPDET_NS_BASE) /* ETAMPDET base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S)) || SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S) && (SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S != 0))) #define USBAHB_AHBS_BASE (USBAHB_S_AHBS_BASE) /* USBAHB_AHBS base address */ #else #define USBAHB_AHBS_BASE (USBAHB_NS_AHBS_BASE) /* USBAHB_AHBS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S)) || SL_TRUSTZONE_PERIPHERAL_USB_APBS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S) && (SL_TRUSTZONE_PERIPHERAL_USB_APBS_S != 0))) #define USB_APBS_BASE (USB_S_APBS_BASE) /* USB_APBS base address */ #else #define USB_APBS_BASE (USB_NS_APBS_BASE) /* USB_APBS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USB_APBS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_USBPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_USBPLL0_S != 0))) #define USBPLL0_BASE (USBPLL0_S_BASE) /* USBPLL0 base address */ #else #define USBPLL0_BASE (USBPLL0_NS_BASE) /* USBPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USBPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S)) || SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S) && (SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S != 0))) #define MPAHBRAM_BASE (MPAHBRAM_S_BASE) /* MPAHBRAM base address */ #else #define MPAHBRAM_BASE (MPAHBRAM_NS_BASE) /* MPAHBRAM base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a121f1152im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a121f1152im56.h index 57fea890fb..0b861c3c5c 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a121f1152im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a121f1152im56.h @@ -207,7 +207,7 @@ typedef enum IRQn{ #define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ #define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ #define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /** Radio type */ -#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 14 /** Radio SUBGHZ HP PA output power */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 16 /** Radio SUBGHZ HP PA output power */ #define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT /** Radio SUBGHZ HP PA is present */ /** Memory Base addresses and limits */ @@ -740,317 +740,317 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER5_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER5_S != 0))) #define TIMER5_BASE (TIMER5_S_BASE) /* TIMER5 base address */ #else #define TIMER5_BASE (TIMER5_NS_BASE) /* TIMER5 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER5_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER6_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER6_S != 0))) #define TIMER6_BASE (TIMER6_S_BASE) /* TIMER6 base address */ #else #define TIMER6_BASE (TIMER6_NS_BASE) /* TIMER6 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER6_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER7_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER7_S != 0))) #define TIMER7_BASE (TIMER7_S_BASE) /* TIMER7 base address */ #else #define TIMER7_BASE (TIMER7_NS_BASE) /* TIMER7 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER7_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART3_S != 0))) #define EUSART3_BASE (EUSART3_S_BASE) /* EUSART3 base address */ #else #define EUSART3_BASE (EUSART3_NS_BASE) /* EUSART3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART4_S != 0))) #define EUSART4_BASE (EUSART4_S_BASE) /* EUSART4 base address */ #else #define EUSART4_BASE (EUSART4_NS_BASE) /* EUSART4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S != 0))) #define RFFPLL0_BASE (RFFPLL0_S_BASE) /* RFFPLL0 base address */ #else #define RFFPLL0_BASE (RFFPLL0_NS_BASE) /* RFFPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) && (SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S != 0))) #define ETAMPDET_BASE (ETAMPDET_S_BASE) /* ETAMPDET base address */ #else #define ETAMPDET_BASE (ETAMPDET_NS_BASE) /* ETAMPDET base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S)) || SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S) && (SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S != 0))) #define USBAHB_AHBS_BASE (USBAHB_S_AHBS_BASE) /* USBAHB_AHBS base address */ #else #define USBAHB_AHBS_BASE (USBAHB_NS_AHBS_BASE) /* USBAHB_AHBS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S)) || SL_TRUSTZONE_PERIPHERAL_USB_APBS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S) && (SL_TRUSTZONE_PERIPHERAL_USB_APBS_S != 0))) #define USB_APBS_BASE (USB_S_APBS_BASE) /* USB_APBS base address */ #else #define USB_APBS_BASE (USB_NS_APBS_BASE) /* USB_APBS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USB_APBS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_USBPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_USBPLL0_S != 0))) #define USBPLL0_BASE (USBPLL0_S_BASE) /* USBPLL0 base address */ #else #define USBPLL0_BASE (USBPLL0_NS_BASE) /* USBPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USBPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S)) || SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S) && (SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S != 0))) #define MPAHBRAM_BASE (MPAHBRAM_S_BASE) /* MPAHBRAM base address */ #else #define MPAHBRAM_BASE (MPAHBRAM_NS_BASE) /* MPAHBRAM base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a211f1920im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a211f1920im56.h index 2d480d47d9..eabb9836b2 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a211f1920im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a211f1920im56.h @@ -207,7 +207,7 @@ typedef enum IRQn{ #define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ #define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ #define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /** Radio type */ -#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 14 /** Radio SUBGHZ HP PA output power */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 16 /** Radio SUBGHZ HP PA output power */ #define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT /** Radio SUBGHZ HP PA is present */ /** Memory Base addresses and limits */ @@ -740,317 +740,317 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER5_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER5_S != 0))) #define TIMER5_BASE (TIMER5_S_BASE) /* TIMER5 base address */ #else #define TIMER5_BASE (TIMER5_NS_BASE) /* TIMER5 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER5_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER6_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER6_S != 0))) #define TIMER6_BASE (TIMER6_S_BASE) /* TIMER6 base address */ #else #define TIMER6_BASE (TIMER6_NS_BASE) /* TIMER6 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER6_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER7_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER7_S != 0))) #define TIMER7_BASE (TIMER7_S_BASE) /* TIMER7 base address */ #else #define TIMER7_BASE (TIMER7_NS_BASE) /* TIMER7 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER7_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART3_S != 0))) #define EUSART3_BASE (EUSART3_S_BASE) /* EUSART3 base address */ #else #define EUSART3_BASE (EUSART3_NS_BASE) /* EUSART3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART4_S != 0))) #define EUSART4_BASE (EUSART4_S_BASE) /* EUSART4 base address */ #else #define EUSART4_BASE (EUSART4_NS_BASE) /* EUSART4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S != 0))) #define RFFPLL0_BASE (RFFPLL0_S_BASE) /* RFFPLL0 base address */ #else #define RFFPLL0_BASE (RFFPLL0_NS_BASE) /* RFFPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) && (SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S != 0))) #define ETAMPDET_BASE (ETAMPDET_S_BASE) /* ETAMPDET base address */ #else #define ETAMPDET_BASE (ETAMPDET_NS_BASE) /* ETAMPDET base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S)) || SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S) && (SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S != 0))) #define USBAHB_AHBS_BASE (USBAHB_S_AHBS_BASE) /* USBAHB_AHBS base address */ #else #define USBAHB_AHBS_BASE (USBAHB_NS_AHBS_BASE) /* USBAHB_AHBS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S)) || SL_TRUSTZONE_PERIPHERAL_USB_APBS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S) && (SL_TRUSTZONE_PERIPHERAL_USB_APBS_S != 0))) #define USB_APBS_BASE (USB_S_APBS_BASE) /* USB_APBS base address */ #else #define USB_APBS_BASE (USB_NS_APBS_BASE) /* USB_APBS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USB_APBS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_USBPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_USBPLL0_S != 0))) #define USBPLL0_BASE (USBPLL0_S_BASE) /* USBPLL0 base address */ #else #define USBPLL0_BASE (USBPLL0_NS_BASE) /* USBPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USBPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S)) || SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S) && (SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S != 0))) #define MPAHBRAM_BASE (MPAHBRAM_S_BASE) /* MPAHBRAM base address */ #else #define MPAHBRAM_BASE (MPAHBRAM_NS_BASE) /* MPAHBRAM base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a221f1920im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a221f1920im56.h index 231db3063a..960cb14fa3 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a221f1920im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25a221f1920im56.h @@ -207,7 +207,7 @@ typedef enum IRQn{ #define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ #define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ #define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /** Radio type */ -#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 14 /** Radio SUBGHZ HP PA output power */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 16 /** Radio SUBGHZ HP PA output power */ #define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT /** Radio SUBGHZ HP PA is present */ /** Memory Base addresses and limits */ @@ -740,317 +740,317 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER5_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER5_S != 0))) #define TIMER5_BASE (TIMER5_S_BASE) /* TIMER5 base address */ #else #define TIMER5_BASE (TIMER5_NS_BASE) /* TIMER5 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER5_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER6_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER6_S != 0))) #define TIMER6_BASE (TIMER6_S_BASE) /* TIMER6 base address */ #else #define TIMER6_BASE (TIMER6_NS_BASE) /* TIMER6 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER6_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER7_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER7_S != 0))) #define TIMER7_BASE (TIMER7_S_BASE) /* TIMER7 base address */ #else #define TIMER7_BASE (TIMER7_NS_BASE) /* TIMER7 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER7_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART3_S != 0))) #define EUSART3_BASE (EUSART3_S_BASE) /* EUSART3 base address */ #else #define EUSART3_BASE (EUSART3_NS_BASE) /* EUSART3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART4_S != 0))) #define EUSART4_BASE (EUSART4_S_BASE) /* EUSART4 base address */ #else #define EUSART4_BASE (EUSART4_NS_BASE) /* EUSART4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S != 0))) #define RFFPLL0_BASE (RFFPLL0_S_BASE) /* RFFPLL0 base address */ #else #define RFFPLL0_BASE (RFFPLL0_NS_BASE) /* RFFPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) && (SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S != 0))) #define ETAMPDET_BASE (ETAMPDET_S_BASE) /* ETAMPDET base address */ #else #define ETAMPDET_BASE (ETAMPDET_NS_BASE) /* ETAMPDET base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S)) || SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S) && (SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S != 0))) #define USBAHB_AHBS_BASE (USBAHB_S_AHBS_BASE) /* USBAHB_AHBS base address */ #else #define USBAHB_AHBS_BASE (USBAHB_NS_AHBS_BASE) /* USBAHB_AHBS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S)) || SL_TRUSTZONE_PERIPHERAL_USB_APBS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S) && (SL_TRUSTZONE_PERIPHERAL_USB_APBS_S != 0))) #define USB_APBS_BASE (USB_S_APBS_BASE) /* USB_APBS base address */ #else #define USB_APBS_BASE (USB_NS_APBS_BASE) /* USB_APBS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USB_APBS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_USBPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_USBPLL0_S != 0))) #define USBPLL0_BASE (USBPLL0_S_BASE) /* USBPLL0 base address */ #else #define USBPLL0_BASE (USBPLL0_NS_BASE) /* USBPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USBPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S)) || SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S) && (SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S != 0))) #define MPAHBRAM_BASE (MPAHBRAM_S_BASE) /* MPAHBRAM base address */ #else #define MPAHBRAM_BASE (MPAHBRAM_NS_BASE) /* MPAHBRAM base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b111f1152im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b111f1152im56.h index 8863c79a3c..42b119f8f6 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b111f1152im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b111f1152im56.h @@ -208,7 +208,7 @@ typedef enum IRQn{ #define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ #define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ #define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /** Radio type */ -#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 14 /** Radio SUBGHZ HP PA output power */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 16 /** Radio SUBGHZ HP PA output power */ #define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT /** Radio SUBGHZ HP PA is present */ /** Memory Base addresses and limits */ @@ -741,317 +741,317 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER5_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER5_S != 0))) #define TIMER5_BASE (TIMER5_S_BASE) /* TIMER5 base address */ #else #define TIMER5_BASE (TIMER5_NS_BASE) /* TIMER5 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER5_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER6_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER6_S != 0))) #define TIMER6_BASE (TIMER6_S_BASE) /* TIMER6 base address */ #else #define TIMER6_BASE (TIMER6_NS_BASE) /* TIMER6 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER6_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER7_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER7_S != 0))) #define TIMER7_BASE (TIMER7_S_BASE) /* TIMER7 base address */ #else #define TIMER7_BASE (TIMER7_NS_BASE) /* TIMER7 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER7_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART3_S != 0))) #define EUSART3_BASE (EUSART3_S_BASE) /* EUSART3 base address */ #else #define EUSART3_BASE (EUSART3_NS_BASE) /* EUSART3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART4_S != 0))) #define EUSART4_BASE (EUSART4_S_BASE) /* EUSART4 base address */ #else #define EUSART4_BASE (EUSART4_NS_BASE) /* EUSART4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S != 0))) #define RFFPLL0_BASE (RFFPLL0_S_BASE) /* RFFPLL0 base address */ #else #define RFFPLL0_BASE (RFFPLL0_NS_BASE) /* RFFPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) && (SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S != 0))) #define ETAMPDET_BASE (ETAMPDET_S_BASE) /* ETAMPDET base address */ #else #define ETAMPDET_BASE (ETAMPDET_NS_BASE) /* ETAMPDET base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S)) || SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S) && (SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S != 0))) #define USBAHB_AHBS_BASE (USBAHB_S_AHBS_BASE) /* USBAHB_AHBS base address */ #else #define USBAHB_AHBS_BASE (USBAHB_NS_AHBS_BASE) /* USBAHB_AHBS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S)) || SL_TRUSTZONE_PERIPHERAL_USB_APBS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S) && (SL_TRUSTZONE_PERIPHERAL_USB_APBS_S != 0))) #define USB_APBS_BASE (USB_S_APBS_BASE) /* USB_APBS base address */ #else #define USB_APBS_BASE (USB_NS_APBS_BASE) /* USB_APBS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USB_APBS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_USBPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_USBPLL0_S != 0))) #define USBPLL0_BASE (USBPLL0_S_BASE) /* USBPLL0 base address */ #else #define USBPLL0_BASE (USBPLL0_NS_BASE) /* USBPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USBPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S)) || SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S) && (SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S != 0))) #define MPAHBRAM_BASE (MPAHBRAM_S_BASE) /* MPAHBRAM base address */ #else #define MPAHBRAM_BASE (MPAHBRAM_NS_BASE) /* MPAHBRAM base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b121f1152im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b121f1152im56.h index c19403c714..b00bfc8239 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b121f1152im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b121f1152im56.h @@ -208,7 +208,7 @@ typedef enum IRQn{ #define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ #define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ #define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /** Radio type */ -#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 14 /** Radio SUBGHZ HP PA output power */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 16 /** Radio SUBGHZ HP PA output power */ #define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT /** Radio SUBGHZ HP PA is present */ /** Memory Base addresses and limits */ @@ -741,317 +741,317 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER5_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER5_S != 0))) #define TIMER5_BASE (TIMER5_S_BASE) /* TIMER5 base address */ #else #define TIMER5_BASE (TIMER5_NS_BASE) /* TIMER5 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER5_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER6_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER6_S != 0))) #define TIMER6_BASE (TIMER6_S_BASE) /* TIMER6 base address */ #else #define TIMER6_BASE (TIMER6_NS_BASE) /* TIMER6 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER6_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER7_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER7_S != 0))) #define TIMER7_BASE (TIMER7_S_BASE) /* TIMER7 base address */ #else #define TIMER7_BASE (TIMER7_NS_BASE) /* TIMER7 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER7_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART3_S != 0))) #define EUSART3_BASE (EUSART3_S_BASE) /* EUSART3 base address */ #else #define EUSART3_BASE (EUSART3_NS_BASE) /* EUSART3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART4_S != 0))) #define EUSART4_BASE (EUSART4_S_BASE) /* EUSART4 base address */ #else #define EUSART4_BASE (EUSART4_NS_BASE) /* EUSART4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S != 0))) #define RFFPLL0_BASE (RFFPLL0_S_BASE) /* RFFPLL0 base address */ #else #define RFFPLL0_BASE (RFFPLL0_NS_BASE) /* RFFPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) && (SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S != 0))) #define ETAMPDET_BASE (ETAMPDET_S_BASE) /* ETAMPDET base address */ #else #define ETAMPDET_BASE (ETAMPDET_NS_BASE) /* ETAMPDET base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S)) || SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S) && (SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S != 0))) #define USBAHB_AHBS_BASE (USBAHB_S_AHBS_BASE) /* USBAHB_AHBS base address */ #else #define USBAHB_AHBS_BASE (USBAHB_NS_AHBS_BASE) /* USBAHB_AHBS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S)) || SL_TRUSTZONE_PERIPHERAL_USB_APBS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S) && (SL_TRUSTZONE_PERIPHERAL_USB_APBS_S != 0))) #define USB_APBS_BASE (USB_S_APBS_BASE) /* USB_APBS base address */ #else #define USB_APBS_BASE (USB_NS_APBS_BASE) /* USB_APBS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USB_APBS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_USBPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_USBPLL0_S != 0))) #define USBPLL0_BASE (USBPLL0_S_BASE) /* USBPLL0 base address */ #else #define USBPLL0_BASE (USBPLL0_NS_BASE) /* USBPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USBPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S)) || SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S) && (SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S != 0))) #define MPAHBRAM_BASE (MPAHBRAM_S_BASE) /* MPAHBRAM base address */ #else #define MPAHBRAM_BASE (MPAHBRAM_NS_BASE) /* MPAHBRAM base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b211f1920im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b211f1920im56.h index e9dfd9bdae..ef02bad28e 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b211f1920im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b211f1920im56.h @@ -208,7 +208,7 @@ typedef enum IRQn{ #define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ #define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ #define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /** Radio type */ -#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 14 /** Radio SUBGHZ HP PA output power */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 16 /** Radio SUBGHZ HP PA output power */ #define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT /** Radio SUBGHZ HP PA is present */ /** Memory Base addresses and limits */ @@ -741,317 +741,317 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER5_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER5_S != 0))) #define TIMER5_BASE (TIMER5_S_BASE) /* TIMER5 base address */ #else #define TIMER5_BASE (TIMER5_NS_BASE) /* TIMER5 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER5_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER6_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER6_S != 0))) #define TIMER6_BASE (TIMER6_S_BASE) /* TIMER6 base address */ #else #define TIMER6_BASE (TIMER6_NS_BASE) /* TIMER6 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER6_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER7_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER7_S != 0))) #define TIMER7_BASE (TIMER7_S_BASE) /* TIMER7 base address */ #else #define TIMER7_BASE (TIMER7_NS_BASE) /* TIMER7 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER7_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART3_S != 0))) #define EUSART3_BASE (EUSART3_S_BASE) /* EUSART3 base address */ #else #define EUSART3_BASE (EUSART3_NS_BASE) /* EUSART3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART4_S != 0))) #define EUSART4_BASE (EUSART4_S_BASE) /* EUSART4 base address */ #else #define EUSART4_BASE (EUSART4_NS_BASE) /* EUSART4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S != 0))) #define RFFPLL0_BASE (RFFPLL0_S_BASE) /* RFFPLL0 base address */ #else #define RFFPLL0_BASE (RFFPLL0_NS_BASE) /* RFFPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) && (SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S != 0))) #define ETAMPDET_BASE (ETAMPDET_S_BASE) /* ETAMPDET base address */ #else #define ETAMPDET_BASE (ETAMPDET_NS_BASE) /* ETAMPDET base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S)) || SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S) && (SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S != 0))) #define USBAHB_AHBS_BASE (USBAHB_S_AHBS_BASE) /* USBAHB_AHBS base address */ #else #define USBAHB_AHBS_BASE (USBAHB_NS_AHBS_BASE) /* USBAHB_AHBS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S)) || SL_TRUSTZONE_PERIPHERAL_USB_APBS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S) && (SL_TRUSTZONE_PERIPHERAL_USB_APBS_S != 0))) #define USB_APBS_BASE (USB_S_APBS_BASE) /* USB_APBS base address */ #else #define USB_APBS_BASE (USB_NS_APBS_BASE) /* USB_APBS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USB_APBS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_USBPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_USBPLL0_S != 0))) #define USBPLL0_BASE (USBPLL0_S_BASE) /* USBPLL0 base address */ #else #define USBPLL0_BASE (USBPLL0_NS_BASE) /* USBPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USBPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S)) || SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S) && (SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S != 0))) #define MPAHBRAM_BASE (MPAHBRAM_S_BASE) /* MPAHBRAM base address */ #else #define MPAHBRAM_BASE (MPAHBRAM_NS_BASE) /* MPAHBRAM base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b212f1920im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b212f1920im56.h index 3a76e65a7c..419cdb47f3 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b212f1920im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b212f1920im56.h @@ -208,7 +208,7 @@ typedef enum IRQn{ #define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ #define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ #define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /** Radio type */ -#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 14 /** Radio SUBGHZ HP PA output power */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 16 /** Radio SUBGHZ HP PA output power */ #define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT /** Radio SUBGHZ HP PA is present */ /** Memory Base addresses and limits */ @@ -744,317 +744,317 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER5_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER5_S != 0))) #define TIMER5_BASE (TIMER5_S_BASE) /* TIMER5 base address */ #else #define TIMER5_BASE (TIMER5_NS_BASE) /* TIMER5 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER5_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER6_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER6_S != 0))) #define TIMER6_BASE (TIMER6_S_BASE) /* TIMER6 base address */ #else #define TIMER6_BASE (TIMER6_NS_BASE) /* TIMER6 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER6_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER7_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER7_S != 0))) #define TIMER7_BASE (TIMER7_S_BASE) /* TIMER7 base address */ #else #define TIMER7_BASE (TIMER7_NS_BASE) /* TIMER7 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER7_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART3_S != 0))) #define EUSART3_BASE (EUSART3_S_BASE) /* EUSART3 base address */ #else #define EUSART3_BASE (EUSART3_NS_BASE) /* EUSART3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART4_S != 0))) #define EUSART4_BASE (EUSART4_S_BASE) /* EUSART4 base address */ #else #define EUSART4_BASE (EUSART4_NS_BASE) /* EUSART4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S != 0))) #define RFFPLL0_BASE (RFFPLL0_S_BASE) /* RFFPLL0 base address */ #else #define RFFPLL0_BASE (RFFPLL0_NS_BASE) /* RFFPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) && (SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S != 0))) #define ETAMPDET_BASE (ETAMPDET_S_BASE) /* ETAMPDET base address */ #else #define ETAMPDET_BASE (ETAMPDET_NS_BASE) /* ETAMPDET base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S)) || SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S) && (SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S != 0))) #define USBAHB_AHBS_BASE (USBAHB_S_AHBS_BASE) /* USBAHB_AHBS base address */ #else #define USBAHB_AHBS_BASE (USBAHB_NS_AHBS_BASE) /* USBAHB_AHBS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S)) || SL_TRUSTZONE_PERIPHERAL_USB_APBS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S) && (SL_TRUSTZONE_PERIPHERAL_USB_APBS_S != 0))) #define USB_APBS_BASE (USB_S_APBS_BASE) /* USB_APBS base address */ #else #define USB_APBS_BASE (USB_NS_APBS_BASE) /* USB_APBS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USB_APBS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_USBPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_USBPLL0_S != 0))) #define USBPLL0_BASE (USBPLL0_S_BASE) /* USBPLL0 base address */ #else #define USBPLL0_BASE (USBPLL0_NS_BASE) /* USBPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USBPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S)) || SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S) && (SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S != 0))) #define MPAHBRAM_BASE (MPAHBRAM_S_BASE) /* MPAHBRAM base address */ #else #define MPAHBRAM_BASE (MPAHBRAM_NS_BASE) /* MPAHBRAM base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b221f1920im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b221f1920im56.h index 193a3a0114..1ec159930e 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b221f1920im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b221f1920im56.h @@ -208,7 +208,7 @@ typedef enum IRQn{ #define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ #define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ #define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /** Radio type */ -#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 14 /** Radio SUBGHZ HP PA output power */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 16 /** Radio SUBGHZ HP PA output power */ #define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT /** Radio SUBGHZ HP PA is present */ /** Memory Base addresses and limits */ @@ -741,317 +741,317 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER5_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER5_S != 0))) #define TIMER5_BASE (TIMER5_S_BASE) /* TIMER5 base address */ #else #define TIMER5_BASE (TIMER5_NS_BASE) /* TIMER5 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER5_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER6_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER6_S != 0))) #define TIMER6_BASE (TIMER6_S_BASE) /* TIMER6 base address */ #else #define TIMER6_BASE (TIMER6_NS_BASE) /* TIMER6 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER6_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER7_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER7_S != 0))) #define TIMER7_BASE (TIMER7_S_BASE) /* TIMER7 base address */ #else #define TIMER7_BASE (TIMER7_NS_BASE) /* TIMER7 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER7_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART3_S != 0))) #define EUSART3_BASE (EUSART3_S_BASE) /* EUSART3 base address */ #else #define EUSART3_BASE (EUSART3_NS_BASE) /* EUSART3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART4_S != 0))) #define EUSART4_BASE (EUSART4_S_BASE) /* EUSART4 base address */ #else #define EUSART4_BASE (EUSART4_NS_BASE) /* EUSART4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S != 0))) #define RFFPLL0_BASE (RFFPLL0_S_BASE) /* RFFPLL0 base address */ #else #define RFFPLL0_BASE (RFFPLL0_NS_BASE) /* RFFPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) && (SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S != 0))) #define ETAMPDET_BASE (ETAMPDET_S_BASE) /* ETAMPDET base address */ #else #define ETAMPDET_BASE (ETAMPDET_NS_BASE) /* ETAMPDET base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S)) || SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S) && (SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S != 0))) #define USBAHB_AHBS_BASE (USBAHB_S_AHBS_BASE) /* USBAHB_AHBS base address */ #else #define USBAHB_AHBS_BASE (USBAHB_NS_AHBS_BASE) /* USBAHB_AHBS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S)) || SL_TRUSTZONE_PERIPHERAL_USB_APBS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S) && (SL_TRUSTZONE_PERIPHERAL_USB_APBS_S != 0))) #define USB_APBS_BASE (USB_S_APBS_BASE) /* USB_APBS base address */ #else #define USB_APBS_BASE (USB_NS_APBS_BASE) /* USB_APBS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USB_APBS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_USBPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_USBPLL0_S != 0))) #define USBPLL0_BASE (USBPLL0_S_BASE) /* USBPLL0 base address */ #else #define USBPLL0_BASE (USBPLL0_NS_BASE) /* USBPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USBPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S)) || SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S) && (SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S != 0))) #define MPAHBRAM_BASE (MPAHBRAM_S_BASE) /* MPAHBRAM base address */ #else #define MPAHBRAM_BASE (MPAHBRAM_NS_BASE) /* MPAHBRAM base address */ diff --git a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b222f1920im56.h b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b222f1920im56.h index 70dce5e673..1134815540 100644 --- a/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b222f1920im56.h +++ b/platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25b222f1920im56.h @@ -208,7 +208,7 @@ typedef enum IRQn{ #define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ #define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ #define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /** Radio type */ -#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 14 /** Radio SUBGHZ HP PA output power */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 16 /** Radio SUBGHZ HP PA output power */ #define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT /** Radio SUBGHZ HP PA is present */ /** Memory Base addresses and limits */ @@ -744,317 +744,317 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER5_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER5_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER5_S != 0))) #define TIMER5_BASE (TIMER5_S_BASE) /* TIMER5 base address */ #else #define TIMER5_BASE (TIMER5_NS_BASE) /* TIMER5 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER5_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER6_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER6_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER6_S != 0))) #define TIMER6_BASE (TIMER6_S_BASE) /* TIMER6 base address */ #else #define TIMER6_BASE (TIMER6_NS_BASE) /* TIMER6 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER6_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER7_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER7_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER7_S != 0))) #define TIMER7_BASE (TIMER7_S_BASE) /* TIMER7 base address */ #else #define TIMER7_BASE (TIMER7_NS_BASE) /* TIMER7 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER7_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART3_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART3_S != 0))) #define EUSART3_BASE (EUSART3_S_BASE) /* EUSART3 base address */ #else #define EUSART3_BASE (EUSART3_NS_BASE) /* EUSART3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART4_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART4_S != 0))) #define EUSART4_BASE (EUSART4_S_BASE) /* EUSART4 base address */ #else #define EUSART4_BASE (EUSART4_NS_BASE) /* EUSART4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S != 0))) #define RFFPLL0_BASE (RFFPLL0_S_BASE) /* RFFPLL0 base address */ #else #define RFFPLL0_BASE (RFFPLL0_NS_BASE) /* RFFPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RFFPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) && (SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S != 0))) #define ETAMPDET_BASE (ETAMPDET_S_BASE) /* ETAMPDET base address */ #else #define ETAMPDET_BASE (ETAMPDET_NS_BASE) /* ETAMPDET base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S)) || SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S) && (SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S != 0))) #define USBAHB_AHBS_BASE (USBAHB_S_AHBS_BASE) /* USBAHB_AHBS base address */ #else #define USBAHB_AHBS_BASE (USBAHB_NS_AHBS_BASE) /* USBAHB_AHBS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USBAHB_AHBS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S)) || SL_TRUSTZONE_PERIPHERAL_USB_APBS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USB_APBS_S) && (SL_TRUSTZONE_PERIPHERAL_USB_APBS_S != 0))) #define USB_APBS_BASE (USB_S_APBS_BASE) /* USB_APBS base address */ #else #define USB_APBS_BASE (USB_NS_APBS_BASE) /* USB_APBS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USB_APBS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_USBPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USBPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_USBPLL0_S != 0))) #define USBPLL0_BASE (USBPLL0_S_BASE) /* USBPLL0 base address */ #else #define USBPLL0_BASE (USBPLL0_NS_BASE) /* USBPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USBPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S)) || SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S) && (SL_TRUSTZONE_PERIPHERAL_MPAHBRAM_S != 0))) #define MPAHBRAM_BASE (MPAHBRAM_S_BASE) /* MPAHBRAM base address */ #else #define MPAHBRAM_BASE (MPAHBRAM_NS_BASE) /* MPAHBRAM base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_dma_descriptor.h index 7e9f82411f..0d53c91474 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_dma_descriptor.h @@ -27,6 +27,8 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32MG21_DMA_DESCRIPTOR_H +#define EFR32MG21_DMA_DESCRIPTOR_H #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ @@ -53,3 +55,5 @@ typedef struct { } DMA_DESCRIPTOR_TypeDef; /**< @} */ /** @} End of group Parts */ + +#endif /* EFR32MG21_DMA_DESCRIPTOR_H */ diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldmaxbar_defines.h index 284402429e..f979cf5520 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_ldmaxbar_defines.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32MG21_LDMAXBAR_DEFINES_H +#define EFR32MG21_LDMAXBAR_DEFINES_H + /* Module source selection indices */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ @@ -140,3 +143,5 @@ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 << 0) /** Shifted Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 << 0) /** Shifted Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF << 0) /** Shifted Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ + +#endif /* EFR32MG21_LDMAXBAR_DEFINES_H */ diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_prs_signals.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_prs_signals.h index cdb342eafc..833a5ac7e4 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_prs_signals.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32MG21_PRS_SIGNALS_H +#define EFR32MG21_PRS_SIGNALS_H + /** Synchronous signal sources enumeration: */ #define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) #define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) @@ -768,3 +771,5 @@ #define PRS_SE_STATE0GATED (PRS_ASYNC_SE_STATE0GATED) #define PRS_SE_STATE1GATED (PRS_ASYNC_SE_STATE1GATED) #define PRS_SE_STATE2GATED (PRS_ASYNC_SE_STATE2GATED) + +#endif /* EFR32MG21_PRS_SIGNALS_H */ diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f1024im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f1024im32.h index 85dd7d7a44..74c5c52bee 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f1024im32.h @@ -552,217 +552,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f512im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f512im32.h index 96a8ae5d8c..b0b04b1cc9 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f512im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f512im32.h @@ -552,217 +552,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f768im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f768im32.h index 9c121e98bc..3ebb9d609c 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f768im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f768im32.h @@ -552,217 +552,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f1024im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f1024im32.h index f1881e5a8c..9399399954 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f1024im32.h @@ -554,217 +554,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f512im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f512im32.h index 851c31614e..cc8d69fc92 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f512im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f512im32.h @@ -554,217 +554,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f768im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f768im32.h index bd781c51ea..5d14746892 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f768im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f768im32.h @@ -554,217 +554,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f1024im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f1024im32.h index c7f5ee5d7b..3d63fcde28 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f1024im32.h @@ -552,217 +552,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f512im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f512im32.h index fd9943f39f..03d2b96133 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f512im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f512im32.h @@ -552,217 +552,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f768im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f768im32.h index 03adcbb91a..b9603a81ee 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f768im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f768im32.h @@ -552,217 +552,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f1024im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f1024im32.h index 4ce4a25379..d1941e5b11 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f1024im32.h @@ -554,217 +554,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f512im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f512im32.h index 21a26d3e98..d196aa3c3f 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f512im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f512im32.h @@ -554,217 +554,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f768im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f768im32.h index dcddcc34c8..c1359d6a38 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f768im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f768im32.h @@ -554,217 +554,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG21/Include/rm21z000f1024im32.h b/platform/Device/SiliconLabs/EFR32MG21/Include/rm21z000f1024im32.h index 76652440c1..125125ea0f 100644 --- a/platform/Device/SiliconLabs/EFR32MG21/Include/rm21z000f1024im32.h +++ b/platform/Device/SiliconLabs/EFR32MG21/Include/rm21z000f1024im32.h @@ -550,217 +550,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dma_descriptor.h index 1d1930a81d..4a3383a837 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_dma_descriptor.h @@ -27,6 +27,8 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32MG22_DMA_DESCRIPTOR_H +#define EFR32MG22_DMA_DESCRIPTOR_H #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ @@ -53,3 +55,5 @@ typedef struct { } DMA_DESCRIPTOR_TypeDef; /**< @} */ /** @} End of group Parts */ + +#endif /* EFR32MG22_DMA_DESCRIPTOR_H */ diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldmaxbar_defines.h index cd8b21e06c..876242e46b 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_ldmaxbar_defines.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32MG22_LDMAXBAR_DEFINES_H +#define EFR32MG22_LDMAXBAR_DEFINES_H + /* Module source selection indices */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ @@ -148,3 +151,5 @@ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 << 0) /** Shifted Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 << 0) /** Shifted Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF << 0) /** Shifted Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ + +#endif /* EFR32MG22_LDMAXBAR_DEFINES_H */ diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_prs_signals.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_prs_signals.h index adda526196..f220e200db 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22_prs_signals.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32MG22_PRS_SIGNALS_H +#define EFR32MG22_PRS_SIGNALS_H + /** Synchronous signal sources enumeration: */ #define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) #define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) @@ -843,3 +846,5 @@ #define PRS_LFRCO_CALMEAS (PRS_ASYNC_LFRCO_CALMEAS) #define PRS_LFRCO_SDM (PRS_ASYNC_LFRCO_SDM) #define PRS_LFRCO_TCMEAS (PRS_ASYNC_LFRCO_TCMEAS) + +#endif /* EFR32MG22_PRS_SIGNALS_H */ diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22a224f512im40.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22a224f512im40.h index b54a3cba38..7b6b37de94 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22a224f512im40.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22a224f512im40.h @@ -588,222 +588,222 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512gn32.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512gn32.h index d0b7efb755..5f1da9e318 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512gn32.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512gn32.h @@ -574,222 +574,222 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512im32.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512im32.h index 8dc5fa0b60..0b33202b09 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512im32.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512im32.h @@ -574,222 +574,222 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512im40.h b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512im40.h index 14e9d22b94..3e2a02446a 100644 --- a/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512im40.h +++ b/platform/Device/SiliconLabs/EFR32MG22/Include/efr32mg22c224f512im40.h @@ -588,222 +588,222 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dma_descriptor.h index d5aeb7a405..a663a752f9 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dma_descriptor.h @@ -27,6 +27,8 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32MG24_DMA_DESCRIPTOR_H +#define EFR32MG24_DMA_DESCRIPTOR_H #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ @@ -53,3 +55,5 @@ typedef struct { } DMA_DESCRIPTOR_TypeDef; /**< @} */ /** @} End of group Parts */ + +#endif /* EFR32MG24_DMA_DESCRIPTOR_H */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar_defines.h index ac0960e7e9..e94c3c6316 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar_defines.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32MG24_LDMAXBAR_DEFINES_H +#define EFR32MG24_LDMAXBAR_DEFINES_H + /* Module source selection indices */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ @@ -150,3 +153,5 @@ #define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ << 0) /** Shifted Mode VDAC0CH1_REQ for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ << 0) /** Shifted Mode VDAC1CH0_REQ for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ << 0) /** Shifted Mode VDAC1CH1_REQ for LDMAXBAR_CH_REQSEL**/ + +#endif /* EFR32MG24_LDMAXBAR_DEFINES_H */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs_signals.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs_signals.h index b8dcbe6066..eb7514a2d3 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs_signals.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32MG24_PRS_SIGNALS_H +#define EFR32MG24_PRS_SIGNALS_H + /** Synchronous signal sources enumeration: */ #define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) #define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) @@ -969,3 +972,5 @@ #define PRS_LFRCO_CALMEAS (PRS_ASYNC_LFRCO_CALMEAS) #define PRS_LFRCO_SDM (PRS_ASYNC_LFRCO_SDM) #define PRS_LFRCO_TCMEAS (PRS_ASYNC_LFRCO_TCMEAS) + +#endif /* EFR32MG24_PRS_SIGNALS_H */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im40.h index 146589b9f0..8b95a9979a 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im40.h @@ -632,257 +632,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im48.h index 54cdafd215..f8cc76b8a9 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im48.h @@ -634,257 +634,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm40.h index cb7ad67795..2184d25e5b 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm40.h @@ -632,257 +632,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm48.h index 8dea3b3805..e8336bdb3e 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm48.h @@ -634,257 +634,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im40.h index 6faa214904..2fb1416ed5 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im40.h @@ -632,257 +632,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im48.h index 8f61feab55..1701d1f920 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im48.h @@ -634,257 +634,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im40.h index c1a3cf745d..6f6f38a359 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im40.h @@ -630,257 +630,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im48.h index e87b6ae6dd..8f16453524 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im48.h @@ -632,257 +632,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm40.h index 5900eb0500..4cdc6cfbed 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm40.h @@ -630,257 +630,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm48.h index d7f9c3d248..7ba9deb533 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm48.h @@ -632,257 +632,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im40.h index 86357bbb7b..f6da52e338 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im40.h @@ -630,257 +630,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im48.h index 5e6944d25b..e205cbdd54 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im48.h @@ -632,257 +632,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a021f1024im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a021f1024im40.h index 461cca3045..bcb9c9c829 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a021f1024im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a021f1024im40.h @@ -627,257 +627,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1024im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1024im48.h index b893aadc1a..2a553973de 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1024im48.h @@ -630,257 +630,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1536gm48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1536gm48.h index 5cb271ceba..6e1f1ac480 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1536gm48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1536gm48.h @@ -630,257 +630,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a111f1536gm48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a111f1536gm48.h index a72495cbcf..0f41bf5cb7 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a111f1536gm48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a111f1536gm48.h @@ -629,257 +629,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a120f1536gm48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a120f1536gm48.h index ec39f88d0f..efac0eb5d7 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a120f1536gm48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a120f1536gm48.h @@ -628,257 +628,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a121f1536gm48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a121f1536gm48.h index 42f0fa0fc8..8bd5addce4 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a121f1536gm48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a121f1536gm48.h @@ -627,257 +627,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im40.h index 5499a9fe57..66aecc1dad 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im40.h @@ -632,257 +632,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im48.h index e6cff4c025..51e94379b6 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im48.h @@ -634,257 +634,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im40.h index cc93414fbb..a75caf3b16 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im40.h @@ -630,257 +630,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im48.h index dea8b8a58b..bc3cddf0e5 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im48.h @@ -632,257 +632,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a610f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a610f1536im40.h index de6494f1ad..f68d2acc32 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a610f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a610f1536im40.h @@ -632,257 +632,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a620f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a620f1536im40.h index 3551342e23..52d1b54ae6 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a620f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a620f1536im40.h @@ -630,257 +630,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1024im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1024im48.h index d907c34a89..3a7648e8a4 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1024im48.h @@ -635,257 +635,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im40.h index d9b724e068..0da09970c5 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im40.h @@ -633,257 +633,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im48.h index a446b9ed67..e68141fc3a 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im48.h @@ -635,257 +635,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1024im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1024im48.h index 977b592e98..c57cc0f2bb 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1024im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1024im48.h @@ -633,257 +633,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im40.h index 6bbcf034a1..9ecf62e0a2 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im40.h @@ -631,257 +631,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im48.h index 0b78f79f9e..b1263f757f 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im48.h @@ -633,257 +633,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536gm48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536gm48.h index 61ef69872d..3aa2017ae2 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536gm48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536gm48.h @@ -631,257 +631,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536im48.h index 96c78686d0..212ac1cad7 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536im48.h @@ -631,257 +631,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b120f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b120f1536im48.h index caeed530ad..5d95af4252 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b120f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b120f1536im48.h @@ -629,257 +629,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im48.h index 92813cd34d..d45f5c67dd 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im48.h @@ -641,262 +641,262 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) || SL_TRUSTZONE_PERIPHERAL_MVP_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MVP_S) && (SL_TRUSTZONE_PERIPHERAL_MVP_S != 0))) #define MVP_BASE (MVP_S_BASE) /* MVP base address */ #else #define MVP_BASE (MVP_NS_BASE) /* MVP base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b220f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b220f1536im48.h index 0a2fd6c454..9f1c672c9b 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b220f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b220f1536im48.h @@ -639,262 +639,262 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) || SL_TRUSTZONE_PERIPHERAL_MVP_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MVP_S) && (SL_TRUSTZONE_PERIPHERAL_MVP_S != 0))) #define MVP_BASE (MVP_S_BASE) /* MVP base address */ #else #define MVP_BASE (MVP_NS_BASE) /* MVP base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b310f1536im48.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b310f1536im48.h index aff1e294b5..bca4e8059e 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b310f1536im48.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b310f1536im48.h @@ -637,262 +637,262 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) || SL_TRUSTZONE_PERIPHERAL_MVP_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MVP_S) && (SL_TRUSTZONE_PERIPHERAL_MVP_S != 0))) #define MVP_BASE (MVP_S_BASE) /* MVP base address */ #else #define MVP_BASE (MVP_NS_BASE) /* MVP base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b610f1536im40.h b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b610f1536im40.h index 1f9f60caa3..946b7eea57 100644 --- a/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b610f1536im40.h +++ b/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b610f1536im40.h @@ -633,257 +633,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dcdc.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dcdc.h index 00f02df825..57b6e73e2f 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dcdc.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dcdc.h @@ -333,31 +333,27 @@ typedef struct { #define _DCDC_BSTEM01CTRL_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ #define _DCDC_BSTEM01CTRL_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ #define _DCDC_BSTEM01CTRL_IPKVAL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for DCDC_BSTEM01CTRL */ -#define _DCDC_BSTEM01CTRL_IPKVAL_Load36mA 0x00000003UL /**< Mode Load36mA for DCDC_BSTEM01CTRL */ -#define _DCDC_BSTEM01CTRL_IPKVAL_Load40mA 0x00000004UL /**< Mode Load40mA for DCDC_BSTEM01CTRL */ -#define _DCDC_BSTEM01CTRL_IPKVAL_Load44mA 0x00000005UL /**< Mode Load44mA for DCDC_BSTEM01CTRL */ -#define _DCDC_BSTEM01CTRL_IPKVAL_Load48mA 0x00000006UL /**< Mode Load48mA for DCDC_BSTEM01CTRL */ -#define _DCDC_BSTEM01CTRL_IPKVAL_Load52mA 0x00000007UL /**< Mode Load52mA for DCDC_BSTEM01CTRL */ -#define _DCDC_BSTEM01CTRL_IPKVAL_Load56mA 0x00000008UL /**< Mode Load56mA for DCDC_BSTEM01CTRL */ -#define _DCDC_BSTEM01CTRL_IPKVAL_Load60mA 0x00000009UL /**< Mode Load60mA for DCDC_BSTEM01CTRL */ -#define _DCDC_BSTEM01CTRL_IPKVAL_Load64mA 0x0000000AUL /**< Mode Load64mA for DCDC_BSTEM01CTRL */ -#define _DCDC_BSTEM01CTRL_IPKVAL_Load68mA 0x0000000BUL /**< Mode Load68mA for DCDC_BSTEM01CTRL */ -#define _DCDC_BSTEM01CTRL_IPKVAL_Load72mA 0x0000000CUL /**< Mode Load72mA for DCDC_BSTEM01CTRL */ -#define _DCDC_BSTEM01CTRL_IPKVAL_Load76mA 0x0000000DUL /**< Mode Load76mA for DCDC_BSTEM01CTRL */ -#define _DCDC_BSTEM01CTRL_IPKVAL_Load80mA 0x0000000EUL /**< Mode Load80mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load10mA 0x00000003UL /**< Mode Load10mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load11mA 0x00000004UL /**< Mode Load11mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load13mA 0x00000005UL /**< Mode Load13mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load15mA 0x00000006UL /**< Mode Load15mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load16mA 0x00000007UL /**< Mode Load16mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load18mA 0x00000008UL /**< Mode Load18mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load20mA 0x00000009UL /**< Mode Load20mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load21mA 0x0000000AUL /**< Mode Load21mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load23mA 0x0000000BUL /**< Mode Load23mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load25mA 0x0000000CUL /**< Mode Load25mA for DCDC_BSTEM01CTRL */ #define DCDC_BSTEM01CTRL_IPKVAL_DEFAULT (_DCDC_BSTEM01CTRL_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_BSTEM01CTRL */ -#define DCDC_BSTEM01CTRL_IPKVAL_Load36mA (_DCDC_BSTEM01CTRL_IPKVAL_Load36mA << 0) /**< Shifted mode Load36mA for DCDC_BSTEM01CTRL */ -#define DCDC_BSTEM01CTRL_IPKVAL_Load40mA (_DCDC_BSTEM01CTRL_IPKVAL_Load40mA << 0) /**< Shifted mode Load40mA for DCDC_BSTEM01CTRL */ -#define DCDC_BSTEM01CTRL_IPKVAL_Load44mA (_DCDC_BSTEM01CTRL_IPKVAL_Load44mA << 0) /**< Shifted mode Load44mA for DCDC_BSTEM01CTRL */ -#define DCDC_BSTEM01CTRL_IPKVAL_Load48mA (_DCDC_BSTEM01CTRL_IPKVAL_Load48mA << 0) /**< Shifted mode Load48mA for DCDC_BSTEM01CTRL */ -#define DCDC_BSTEM01CTRL_IPKVAL_Load52mA (_DCDC_BSTEM01CTRL_IPKVAL_Load52mA << 0) /**< Shifted mode Load52mA for DCDC_BSTEM01CTRL */ -#define DCDC_BSTEM01CTRL_IPKVAL_Load56mA (_DCDC_BSTEM01CTRL_IPKVAL_Load56mA << 0) /**< Shifted mode Load56mA for DCDC_BSTEM01CTRL */ -#define DCDC_BSTEM01CTRL_IPKVAL_Load60mA (_DCDC_BSTEM01CTRL_IPKVAL_Load60mA << 0) /**< Shifted mode Load60mA for DCDC_BSTEM01CTRL */ -#define DCDC_BSTEM01CTRL_IPKVAL_Load64mA (_DCDC_BSTEM01CTRL_IPKVAL_Load64mA << 0) /**< Shifted mode Load64mA for DCDC_BSTEM01CTRL */ -#define DCDC_BSTEM01CTRL_IPKVAL_Load68mA (_DCDC_BSTEM01CTRL_IPKVAL_Load68mA << 0) /**< Shifted mode Load68mA for DCDC_BSTEM01CTRL */ -#define DCDC_BSTEM01CTRL_IPKVAL_Load72mA (_DCDC_BSTEM01CTRL_IPKVAL_Load72mA << 0) /**< Shifted mode Load72mA for DCDC_BSTEM01CTRL */ -#define DCDC_BSTEM01CTRL_IPKVAL_Load76mA (_DCDC_BSTEM01CTRL_IPKVAL_Load76mA << 0) /**< Shifted mode Load76mA for DCDC_BSTEM01CTRL */ -#define DCDC_BSTEM01CTRL_IPKVAL_Load80mA (_DCDC_BSTEM01CTRL_IPKVAL_Load80mA << 0) /**< Shifted mode Load80mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load10mA (_DCDC_BSTEM01CTRL_IPKVAL_Load10mA << 0) /**< Shifted mode Load10mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load11mA (_DCDC_BSTEM01CTRL_IPKVAL_Load11mA << 0) /**< Shifted mode Load11mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load13mA (_DCDC_BSTEM01CTRL_IPKVAL_Load13mA << 0) /**< Shifted mode Load13mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load15mA (_DCDC_BSTEM01CTRL_IPKVAL_Load15mA << 0) /**< Shifted mode Load15mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load16mA (_DCDC_BSTEM01CTRL_IPKVAL_Load16mA << 0) /**< Shifted mode Load16mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load18mA (_DCDC_BSTEM01CTRL_IPKVAL_Load18mA << 0) /**< Shifted mode Load18mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load20mA (_DCDC_BSTEM01CTRL_IPKVAL_Load20mA << 0) /**< Shifted mode Load20mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load21mA (_DCDC_BSTEM01CTRL_IPKVAL_Load21mA << 0) /**< Shifted mode Load21mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load23mA (_DCDC_BSTEM01CTRL_IPKVAL_Load23mA << 0) /**< Shifted mode Load23mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load25mA (_DCDC_BSTEM01CTRL_IPKVAL_Load25mA << 0) /**< Shifted mode Load25mA for DCDC_BSTEM01CTRL */ #define _DCDC_BSTEM01CTRL_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ #define _DCDC_BSTEM01CTRL_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ #define _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_BSTEM01CTRL */ diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dma_descriptor.h index 84d7e529ba..e02103bcf6 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_dma_descriptor.h @@ -27,6 +27,8 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32MG27_DMA_DESCRIPTOR_H +#define EFR32MG27_DMA_DESCRIPTOR_H #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ @@ -53,3 +55,5 @@ typedef struct { } DMA_DESCRIPTOR_TypeDef; /**< @} */ /** @} End of group Parts */ + +#endif /* EFR32MG27_DMA_DESCRIPTOR_H */ diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_emu.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_emu.h index 6e70ac88c8..7803d90dd3 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_emu.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_emu.h @@ -69,7 +69,7 @@ typedef struct { __IOM uint32_t DGIF; /**< Interrupt Flags Debug */ __IOM uint32_t DGIEN; /**< Interrupt Enables Debug */ uint32_t RESERVED7[5U]; /**< Reserved for future use */ - __IOM uint32_t BOOSTCTRL; /**< EMU boost mode controller reigsiters */ + __IOM uint32_t BOOSTCTRL; /**< EMU boost mode controller register */ uint32_t RESERVED8[1U]; /**< Reserved for future use */ uint32_t RESERVED9[15U]; /**< Reserved for future use */ __IOM uint32_t EFPIF; /**< EFP Interrupt Register */ @@ -103,7 +103,7 @@ typedef struct { __IOM uint32_t DGIF_SET; /**< Interrupt Flags Debug */ __IOM uint32_t DGIEN_SET; /**< Interrupt Enables Debug */ uint32_t RESERVED20[5U]; /**< Reserved for future use */ - __IOM uint32_t BOOSTCTRL_SET; /**< EMU boost mode controller reigsiters */ + __IOM uint32_t BOOSTCTRL_SET; /**< EMU boost mode controller register */ uint32_t RESERVED21[1U]; /**< Reserved for future use */ uint32_t RESERVED22[15U]; /**< Reserved for future use */ __IOM uint32_t EFPIF_SET; /**< EFP Interrupt Register */ @@ -137,7 +137,7 @@ typedef struct { __IOM uint32_t DGIF_CLR; /**< Interrupt Flags Debug */ __IOM uint32_t DGIEN_CLR; /**< Interrupt Enables Debug */ uint32_t RESERVED33[5U]; /**< Reserved for future use */ - __IOM uint32_t BOOSTCTRL_CLR; /**< EMU boost mode controller reigsiters */ + __IOM uint32_t BOOSTCTRL_CLR; /**< EMU boost mode controller register */ uint32_t RESERVED34[1U]; /**< Reserved for future use */ uint32_t RESERVED35[15U]; /**< Reserved for future use */ __IOM uint32_t EFPIF_CLR; /**< EFP Interrupt Register */ @@ -171,7 +171,7 @@ typedef struct { __IOM uint32_t DGIF_TGL; /**< Interrupt Flags Debug */ __IOM uint32_t DGIEN_TGL; /**< Interrupt Enables Debug */ uint32_t RESERVED46[5U]; /**< Reserved for future use */ - __IOM uint32_t BOOSTCTRL_TGL; /**< EMU boost mode controller reigsiters */ + __IOM uint32_t BOOSTCTRL_TGL; /**< EMU boost mode controller register */ uint32_t RESERVED47[1U]; /**< Reserved for future use */ uint32_t RESERVED48[15U]; /**< Reserved for future use */ __IOM uint32_t EFPIF_TGL; /**< EFP Interrupt Register */ @@ -710,7 +710,7 @@ typedef struct { #define _EMU_RSTCAUSE_DCI_MASK 0x10000UL /**< Bit mask for EMU_DCI */ #define _EMU_RSTCAUSE_DCI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ #define EMU_RSTCAUSE_DCI_DEFAULT (_EMU_RSTCAUSE_DCI_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_BOOSTON (0x1UL << 18) /**< BOOSTON PIN reset */ +#define EMU_RSTCAUSE_BOOSTON (0x1UL << 18) /**< BOOST_EN pin reset */ #define _EMU_RSTCAUSE_BOOSTON_SHIFT 18 /**< Shift value for EMU_BOOSTON */ #define _EMU_RSTCAUSE_BOOSTON_MASK 0x40000UL /**< Bit mask for EMU_BOOSTON */ #define _EMU_RSTCAUSE_BOOSTON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ @@ -772,7 +772,7 @@ typedef struct { /* Bit fields for EMU BOOSTCTRL */ #define _EMU_BOOSTCTRL_RESETVALUE 0x00000001UL /**< Default value for EMU_BOOSTCTRL */ #define _EMU_BOOSTCTRL_MASK 0x00000001UL /**< Mask for EMU_BOOSTCTRL */ -#define EMU_BOOSTCTRL_BOOSTENCTRL (0x1UL << 0) /**< BOOST_EN_CTRL BIT */ +#define EMU_BOOSTCTRL_BOOSTENCTRL (0x1UL << 0) /**< BOOST_EN Control */ #define _EMU_BOOSTCTRL_BOOSTENCTRL_SHIFT 0 /**< Shift value for EMU_BOOSTENCTRL */ #define _EMU_BOOSTCTRL_BOOSTENCTRL_MASK 0x1UL /**< Bit mask for EMU_BOOSTENCTRL */ #define _EMU_BOOSTCTRL_BOOSTENCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BOOSTCTRL */ diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpio.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpio.h index ad20186c7e..3c11c1e03a 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpio.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_gpio.h @@ -651,151 +651,151 @@ typedef struct { #define _GPIO_EXTIPINSELL_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET0 << 0) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET1 << 0) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET2 << 0) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET3 << 0) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 << 0) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 << 0) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 << 0) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 << 0) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET0 << 4) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET1 << 4) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET2 << 4) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET3 << 4) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 << 4) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 << 4) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 << 4) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 << 4) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET0 << 8) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET1 << 8) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET2 << 8) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET3 << 8) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 << 8) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 << 8) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 << 8) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 << 8) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET0 << 12) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET1 << 12) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET2 << 12) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET3 << 12) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 << 12) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 << 12) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 << 12) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 << 12) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET0 << 16) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET1 << 16) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET2 << 16) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET3 << 16) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 << 16) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 << 16) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 << 16) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 << 16) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET0 << 20) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET1 << 20) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET2 << 20) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET3 << 20) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 << 20) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 << 20) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 << 20) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 << 20) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET0 << 24) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET1 << 24) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET2 << 24) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET3 << 24) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 << 24) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 << 24) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 << 24) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 << 24) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ #define _GPIO_EXTIPINSELL_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */ #define _GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ #define GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET0 << 28) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET1 << 28) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET2 << 28) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET3 << 28) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 << 28) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 << 28) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 << 28) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 << 28) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ /* Bit fields for GPIO EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_MASK 0x00003333UL /**< Mask for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET8 0x00000000UL /**< Mode OFFSET8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET9 0x00000001UL /**< Mode OFFSET9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET10 0x00000002UL /**< Mode OFFSET10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET11 0x00000003UL /**< Mode OFFSET11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET8 (_GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET8 << 0) /**< Shifted mode OFFSET8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET9 (_GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET9 << 0) /**< Shifted mode OFFSET9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET10 (_GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET10 << 0) /**< Shifted mode OFFSET10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET11 (_GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET11 << 0) /**< Shifted mode OFFSET11 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET8 0x00000000UL /**< Mode OFFSET8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET9 0x00000001UL /**< Mode OFFSET9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET10 0x00000002UL /**< Mode OFFSET10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET11 0x00000003UL /**< Mode OFFSET11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET8 (_GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET8 << 4) /**< Shifted mode OFFSET8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET9 (_GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET9 << 4) /**< Shifted mode OFFSET9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET10 (_GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET10 << 4) /**< Shifted mode OFFSET10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET11 (_GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET11 << 4) /**< Shifted mode OFFSET11 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET8 0x00000000UL /**< Mode OFFSET8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET9 0x00000001UL /**< Mode OFFSET9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET10 0x00000002UL /**< Mode OFFSET10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET11 0x00000003UL /**< Mode OFFSET11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET8 (_GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET8 << 8) /**< Shifted mode OFFSET8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET9 (_GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET9 << 8) /**< Shifted mode OFFSET9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET10 (_GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET10 << 8) /**< Shifted mode OFFSET10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET11 (_GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET11 << 8) /**< Shifted mode OFFSET11 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET8 0x00000000UL /**< Mode OFFSET8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET9 0x00000001UL /**< Mode OFFSET9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET10 0x00000002UL /**< Mode OFFSET10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET11 0x00000003UL /**< Mode OFFSET11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET8 (_GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET8 << 12) /**< Shifted mode OFFSET8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET9 (_GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET9 << 12) /**< Shifted mode OFFSET9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET10 (_GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET10 << 12) /**< Shifted mode OFFSET10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET11 (_GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET11 << 12) /**< Shifted mode OFFSET11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_MASK 0x00003333UL /**< Mask for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 << 0) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 << 0) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 << 0) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 << 0) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 << 4) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 << 4) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 << 4) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 << 4) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 << 8) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 << 8) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 << 8) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 << 8) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 << 12) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 << 12) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 << 12) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 << 12) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ /* Bit fields for GPIO EXTIRISE */ #define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */ diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldmaxbar_defines.h index af81104bed..9144ece6a5 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_ldmaxbar_defines.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32MG27_LDMAXBAR_DEFINES_H +#define EFR32MG27_LDMAXBAR_DEFINES_H + /* Module source selection indices */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ @@ -148,3 +151,5 @@ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF << 0) /** Shifted Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL << 0) /** Shifted Mode EUSART0RXFL for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL << 0) /** Shifted Mode EUSART0TXFL for LDMAXBAR_CH_REQSEL**/ + +#endif /* EFR32MG27_LDMAXBAR_DEFINES_H */ diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_prs_signals.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_prs_signals.h index 386a9823d5..9f6561332e 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27_prs_signals.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32MG27_PRS_SIGNALS_H +#define EFR32MG27_PRS_SIGNALS_H + /** Synchronous signal sources enumeration: */ #define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) #define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) @@ -875,3 +878,5 @@ #define PRS_LFRCO_CALMEAS (PRS_ASYNC_LFRCO_CALMEAS) #define PRS_LFRCO_SDM (PRS_ASYNC_LFRCO_SDM) #define PRS_LFRCO_TCMEAS (PRS_ASYNC_LFRCO_TCMEAS) + +#endif /* EFR32MG27_PRS_SIGNALS_H */ diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c140f768im32.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c140f768im32.h index d59e1f75b6..50fb98e276 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c140f768im32.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c140f768im32.h @@ -209,14 +209,14 @@ typedef enum IRQn{ #define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ #define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ #define USERDATA_BITS (0xBUL) /** USERDATA used bits */ -#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ -#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ -#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE085FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ -#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ -#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08600UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ #define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ -#define MSC_FLASH_DEVINFO_MEM_END (0x0FE089FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ #define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ #define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ #define DMEM_RAM0_RAM_MEM_SIZE (0x00010000UL) /** DMEM_RAM0_RAM_MEM available address space */ #define DMEM_RAM0_RAM_MEM_END (0x2000FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ @@ -632,227 +632,227 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S != 0))) #define SEPUF_APBCFG_BASE (SEPUF_S_APBCFG_BASE) /* SEPUF_APBCFG base address */ #else #define SEPUF_APBCFG_BASE (SEPUF_NS_APBCFG_BASE) /* SEPUF_APBCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) && (SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S != 0))) #define ETAMPDET_BASE (ETAMPDET_S_BASE) /* ETAMPDET base address */ #else #define ETAMPDET_BASE (ETAMPDET_NS_BASE) /* ETAMPDET base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c140f768im40.h b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c140f768im40.h index 29f58f0bfb..fb023b39d4 100644 --- a/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c140f768im40.h +++ b/platform/Device/SiliconLabs/EFR32MG27/Include/efr32mg27c140f768im40.h @@ -209,14 +209,14 @@ typedef enum IRQn{ #define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ #define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ #define USERDATA_BITS (0xBUL) /** USERDATA used bits */ -#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ -#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ -#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE085FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ -#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ -#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08600UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ #define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ -#define MSC_FLASH_DEVINFO_MEM_END (0x0FE089FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ #define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ #define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ #define DMEM_RAM0_RAM_MEM_SIZE (0x00010000UL) /** DMEM_RAM0_RAM_MEM available address space */ #define DMEM_RAM0_RAM_MEM_END (0x2000FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ @@ -648,227 +648,227 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S != 0))) #define SEPUF_APBCFG_BASE (SEPUF_S_APBCFG_BASE) /* SEPUF_APBCFG base address */ #else #define SEPUF_APBCFG_BASE (SEPUF_NS_APBCFG_BASE) /* SEPUF_APBCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEPUF_APBCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) && (SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S != 0))) #define ETAMPDET_BASE (ETAMPDET_S_BASE) /* ETAMPDET base address */ #else #define ETAMPDET_BASE (ETAMPDET_NS_BASE) /* ETAMPDET base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_dma_descriptor.h index 7528cceb48..ce60696622 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_dma_descriptor.h @@ -27,6 +27,8 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32MR21_DMA_DESCRIPTOR_H +#define EFR32MR21_DMA_DESCRIPTOR_H #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ @@ -53,3 +55,5 @@ typedef struct { } DMA_DESCRIPTOR_TypeDef; /**< @} */ /** @} End of group Parts */ + +#endif /* EFR32MR21_DMA_DESCRIPTOR_H */ diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldmaxbar_defines.h index bd613f80e9..6e70c55af2 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_ldmaxbar_defines.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32MR21_LDMAXBAR_DEFINES_H +#define EFR32MR21_LDMAXBAR_DEFINES_H + /* Module source selection indices */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ @@ -122,3 +125,5 @@ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 << 0) /** Shifted Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 << 0) /** Shifted Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF << 0) /** Shifted Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ + +#endif /* EFR32MR21_LDMAXBAR_DEFINES_H */ diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_prs_signals.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_prs_signals.h index c35795f463..4a294f4a13 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21_prs_signals.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32MR21_PRS_SIGNALS_H +#define EFR32MR21_PRS_SIGNALS_H + /** Synchronous signal sources enumeration: */ #define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) #define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) @@ -731,3 +734,5 @@ #define PRS_SE_STATE0GATED (PRS_ASYNC_SE_STATE0GATED) #define PRS_SE_STATE1GATED (PRS_ASYNC_SE_STATE1GATED) #define PRS_SE_STATE2GATED (PRS_ASYNC_SE_STATE2GATED) + +#endif /* EFR32MR21_PRS_SIGNALS_H */ diff --git a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21a020f512im32.h b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21a020f512im32.h index ed302ed72f..89cae30b68 100644 --- a/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21a020f512im32.h +++ b/platform/Device/SiliconLabs/EFR32MR21/Include/efr32mr21a020f512im32.h @@ -528,192 +528,192 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dma_descriptor.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dma_descriptor.h index 1ddce61ff9..94e1d1983a 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dma_descriptor.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dma_descriptor.h @@ -27,6 +27,8 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32ZG23_DMA_DESCRIPTOR_H +#define EFR32ZG23_DMA_DESCRIPTOR_H #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ @@ -53,3 +55,5 @@ typedef struct { } DMA_DESCRIPTOR_TypeDef; /**< @} */ /** @} End of group Parts */ + +#endif /* EFR32ZG23_DMA_DESCRIPTOR_H */ diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldmaxbar_defines.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldmaxbar_defines.h index fb68ab500a..2c07350f9c 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldmaxbar_defines.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32ZG23_LDMAXBAR_DEFINES_H +#define EFR32ZG23_LDMAXBAR_DEFINES_H + /* Module source selection indices */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ @@ -158,3 +161,5 @@ #define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL << 0) /** Shifted Mode EUSART2TXFL for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO (_LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO << 0) /** Shifted Mode LESENSEFIFO for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_LCD (_LDMAXBAR_CH_REQSEL_SIGSEL_LCD << 0) /** Shifted Mode LCD for LDMAXBAR_CH_REQSEL**/ + +#endif /* EFR32ZG23_LDMAXBAR_DEFINES_H */ diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_prs_signals.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_prs_signals.h index 7a8e7331c4..769106027d 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_prs_signals.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_prs_signals.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef EFR32ZG23_PRS_SIGNALS_H +#define EFR32ZG23_PRS_SIGNALS_H + /** Synchronous signal sources enumeration: */ #define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) #define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) @@ -971,3 +974,5 @@ #define PRS_EUSART2L_TXC (PRS_ASYNC_EUSART2L_TXC) #define PRS_EUSART2L_RXFL (PRS_ASYNC_EUSART2L_RXFL) #define PRS_EUSART2L_TXFL (PRS_ASYNC_EUSART2L_TXFL) + +#endif /* EFR32ZG23_PRS_SIGNALS_H */ diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm40.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm40.h index 137d43c7d2..34d03efb62 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm40.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm40.h @@ -626,267 +626,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm48.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm48.h index e17869be5e..5c494db442 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm48.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm48.h @@ -697,277 +697,277 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm40.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm40.h index 1013817c20..4d5bfdd8f4 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm40.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm40.h @@ -626,267 +626,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm48.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm48.h index a2d76f0dd0..e7c8c4767e 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm48.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm48.h @@ -697,277 +697,277 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im40.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im40.h index 1265757e33..7c1c484af6 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im40.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im40.h @@ -627,267 +627,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im48.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im48.h index 124566da0e..590adbc4f2 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im48.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im48.h @@ -698,277 +698,277 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b011f512im40.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b011f512im40.h index 92942a3666..d283079886 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b011f512im40.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b011f512im40.h @@ -624,267 +624,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im40.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im40.h index 67b4d4f48f..7829d8464d 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im40.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im40.h @@ -627,267 +627,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im48.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im48.h index 4fad13c27d..28d68de62e 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im48.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im48.h @@ -698,277 +698,277 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b021f512im40.h b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b021f512im40.h index ded1c8141c..a23ba02277 100644 --- a/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b021f512im40.h +++ b/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b021f512im40.h @@ -624,267 +624,267 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm230sa27hgn.h b/platform/Device/SiliconLabs/FGM23/Include/fgm230sa27hgn.h index 1eb1a5d28c..99cec1eaf8 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm230sa27hgn.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm230sa27hgn.h @@ -701,277 +701,277 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm230sb27hgn.h b/platform/Device/SiliconLabs/FGM23/Include/fgm230sb27hgn.h index 795da0ff40..99ee0fb64d 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm230sb27hgn.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm230sb27hgn.h @@ -702,277 +702,277 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_dma_descriptor.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_dma_descriptor.h index 18b7665239..0262d26161 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_dma_descriptor.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_dma_descriptor.h @@ -27,6 +27,8 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef FGM23_DMA_DESCRIPTOR_H +#define FGM23_DMA_DESCRIPTOR_H #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ @@ -53,3 +55,5 @@ typedef struct { } DMA_DESCRIPTOR_TypeDef; /**< @} */ /** @} End of group Parts */ + +#endif /* FGM23_DMA_DESCRIPTOR_H */ diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldmaxbar_defines.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldmaxbar_defines.h index c7d90c2e23..11b56cd85f 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_ldmaxbar_defines.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef FGM23_LDMAXBAR_DEFINES_H +#define FGM23_LDMAXBAR_DEFINES_H + /* Module source selection indices */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ @@ -158,3 +161,5 @@ #define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL << 0) /** Shifted Mode EUSART2TXFL for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO (_LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO << 0) /** Shifted Mode LESENSEFIFO for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_LCD (_LDMAXBAR_CH_REQSEL_SIGSEL_LCD << 0) /** Shifted Mode LCD for LDMAXBAR_CH_REQSEL**/ + +#endif /* FGM23_LDMAXBAR_DEFINES_H */ diff --git a/platform/Device/SiliconLabs/FGM23/Include/fgm23_prs_signals.h b/platform/Device/SiliconLabs/FGM23/Include/fgm23_prs_signals.h index 111921b6ec..b9973d8a12 100644 --- a/platform/Device/SiliconLabs/FGM23/Include/fgm23_prs_signals.h +++ b/platform/Device/SiliconLabs/FGM23/Include/fgm23_prs_signals.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef FGM23_PRS_SIGNALS_H +#define FGM23_PRS_SIGNALS_H + /** Synchronous signal sources enumeration: */ #define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) #define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) @@ -971,3 +974,5 @@ #define PRS_EUSART2L_TXC (PRS_ASYNC_EUSART2L_TXC) #define PRS_EUSART2L_RXFL (PRS_ASYNC_EUSART2L_RXFL) #define PRS_EUSART2L_TXFL (PRS_ASYNC_EUSART2L_TXFL) + +#endif /* FGM23_PRS_SIGNALS_H */ diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210l022jif.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210l022jif.h index b844319a87..df6dcad45f 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210l022jif.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210l022jif.h @@ -539,217 +539,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210l022jnf.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210l022jnf.h index 1dc5371f13..3c261dd779 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210l022jnf.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210l022jnf.h @@ -539,217 +539,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210la22jif.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210la22jif.h index ababa897c5..bbb9fed211 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210la22jif.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210la22jif.h @@ -539,217 +539,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210la22jnf.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210la22jnf.h index bfd837fae1..6d98ab913f 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210la22jnf.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210la22jnf.h @@ -539,217 +539,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210p022jia.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210p022jia.h index 6372c1e8fc..7fb3ffbf72 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210p022jia.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210p022jia.h @@ -551,217 +551,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210p032jia.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210p032jia.h index 58328d4370..c05b1409c3 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210p032jia.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210p032jia.h @@ -553,217 +553,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210pa22jia.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210pa22jia.h index dd734af7f8..1cbebf040c 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210pa22jia.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210pa22jia.h @@ -551,217 +551,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210pa32jia.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210pa32jia.h index 178055f7a5..1e65635e85 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210pa32jia.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210pa32jia.h @@ -553,217 +553,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210pb22jia.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210pb22jia.h index 990a391854..23fcb9c861 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210pb22jia.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210pb22jia.h @@ -551,217 +551,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm210pb32jia.h b/platform/Device/SiliconLabs/MGM21/Include/mgm210pb32jia.h index 894397d32b..08cd93ff43 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm210pb32jia.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm210pb32jia.h @@ -553,217 +553,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm211la02jnf.h b/platform/Device/SiliconLabs/MGM21/Include/mgm211la02jnf.h index b5ac3845e9..0923858a86 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm211la02jnf.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm211la02jnf.h @@ -539,217 +539,217 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || SL_TRUSTZONE_PERIPHERAL_USART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ #else #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || SL_TRUSTZONE_PERIPHERAL_LVGD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ #else #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || SL_TRUSTZONE_PERIPHERAL_BUFC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ #else #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_dma_descriptor.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_dma_descriptor.h index b5ae3484fb..2422ed4cc4 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_dma_descriptor.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_dma_descriptor.h @@ -27,6 +27,8 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef MGM21_DMA_DESCRIPTOR_H +#define MGM21_DMA_DESCRIPTOR_H #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ @@ -53,3 +55,5 @@ typedef struct { } DMA_DESCRIPTOR_TypeDef; /**< @} */ /** @} End of group Parts */ + +#endif /* MGM21_DMA_DESCRIPTOR_H */ diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldmaxbar_defines.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldmaxbar_defines.h index 6db13848a9..9f75109bd8 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_ldmaxbar_defines.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef MGM21_LDMAXBAR_DEFINES_H +#define MGM21_LDMAXBAR_DEFINES_H + /* Module source selection indices */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ @@ -140,3 +143,5 @@ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 << 0) /** Shifted Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 << 0) /** Shifted Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF << 0) /** Shifted Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ + +#endif /* MGM21_LDMAXBAR_DEFINES_H */ diff --git a/platform/Device/SiliconLabs/MGM21/Include/mgm21_prs_signals.h b/platform/Device/SiliconLabs/MGM21/Include/mgm21_prs_signals.h index 6d7e77c578..439e069ad8 100644 --- a/platform/Device/SiliconLabs/MGM21/Include/mgm21_prs_signals.h +++ b/platform/Device/SiliconLabs/MGM21/Include/mgm21_prs_signals.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef MGM21_PRS_SIGNALS_H +#define MGM21_PRS_SIGNALS_H + /** Synchronous signal sources enumeration: */ #define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) #define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) @@ -768,3 +771,5 @@ #define PRS_SE_STATE0GATED (PRS_ASYNC_SE_STATE0GATED) #define PRS_SE_STATE1GATED (PRS_ASYNC_SE_STATE1GATED) #define PRS_SE_STATE2GATED (PRS_ASYNC_SE_STATE2GATED) + +#endif /* MGM21_PRS_SIGNALS_H */ diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm220pc22hna.h b/platform/Device/SiliconLabs/MGM22/Include/mgm220pc22hna.h index 5ecf22e4bf..fd6d6e867b 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm220pc22hna.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm220pc22hna.h @@ -581,222 +581,222 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || SL_TRUSTZONE_PERIPHERAL_USART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ #else #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || SL_TRUSTZONE_PERIPHERAL_PDM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) #define PDM_BASE (PDM_S_BASE) /* PDM base address */ #else #define PDM_BASE (PDM_NS_BASE) /* PDM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PDM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || SL_TRUSTZONE_PERIPHERAL_RTCC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ #else #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) #define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ #else #define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) #define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ #else #define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #else #define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #else #define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || SL_TRUSTZONE_PERIPHERAL_PRORTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ #else #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_dma_descriptor.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_dma_descriptor.h index 83e67ec721..99edb47fd6 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_dma_descriptor.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_dma_descriptor.h @@ -27,6 +27,8 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef MGM22_DMA_DESCRIPTOR_H +#define MGM22_DMA_DESCRIPTOR_H #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ @@ -53,3 +55,5 @@ typedef struct { } DMA_DESCRIPTOR_TypeDef; /**< @} */ /** @} End of group Parts */ + +#endif /* MGM22_DMA_DESCRIPTOR_H */ diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldmaxbar_defines.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldmaxbar_defines.h index aae77b083a..784ad799f8 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_ldmaxbar_defines.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef MGM22_LDMAXBAR_DEFINES_H +#define MGM22_LDMAXBAR_DEFINES_H + /* Module source selection indices */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ @@ -148,3 +151,5 @@ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 << 0) /** Shifted Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 << 0) /** Shifted Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF << 0) /** Shifted Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ + +#endif /* MGM22_LDMAXBAR_DEFINES_H */ diff --git a/platform/Device/SiliconLabs/MGM22/Include/mgm22_prs_signals.h b/platform/Device/SiliconLabs/MGM22/Include/mgm22_prs_signals.h index 0547b6d5c4..9fdeca5a40 100644 --- a/platform/Device/SiliconLabs/MGM22/Include/mgm22_prs_signals.h +++ b/platform/Device/SiliconLabs/MGM22/Include/mgm22_prs_signals.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef MGM22_PRS_SIGNALS_H +#define MGM22_PRS_SIGNALS_H + /** Synchronous signal sources enumeration: */ #define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) #define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) @@ -843,3 +846,5 @@ #define PRS_LFRCO_CALMEAS (PRS_ASYNC_LFRCO_CALMEAS) #define PRS_LFRCO_SDM (PRS_ASYNC_LFRCO_SDM) #define PRS_LFRCO_TCMEAS (PRS_ASYNC_LFRCO_TCMEAS) + +#endif /* MGM22_PRS_SIGNALS_H */ diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240l022rnf.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240l022rnf.h index 9017496a94..de149f5508 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240l022rnf.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240l022rnf.h @@ -586,257 +586,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240l022vnf.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240l022vnf.h index e805c39192..d232424c08 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240l022vnf.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240l022vnf.h @@ -586,257 +586,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240pa22vna.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240pa22vna.h index ef2d131bd1..d20c85d36f 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240pa22vna.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240pa22vna.h @@ -623,257 +623,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240pa32vna.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240pa32vna.h index 63d56403c9..49c20f8818 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240pa32vna.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240pa32vna.h @@ -621,257 +621,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240pa32vnn.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240pa32vnn.h index 8bd21d6e43..205a67161f 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240pa32vnn.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240pa32vnn.h @@ -621,257 +621,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240pb22vna.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240pb22vna.h index cbb0879992..c0beaae872 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240pb22vna.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240pb22vna.h @@ -624,257 +624,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240pb32vna.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240pb32vna.h index 4560a2461e..8169bb5206 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240pb32vna.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240pb32vna.h @@ -622,257 +622,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240pb32vnn.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240pb32vnn.h index aba6873a62..2c87b5b312 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240pb32vnn.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240pb32vnn.h @@ -622,257 +622,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240sa22vna.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240sa22vna.h index feb9fc007d..ac81d585bc 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240sa22vna.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240sa22vna.h @@ -637,257 +637,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240sb22vna.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240sb22vna.h index 33099719d9..b0538cec47 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240sb22vna.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240sb22vna.h @@ -638,257 +638,257 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm240sd22vna.h b/platform/Device/SiliconLabs/MGM24/Include/mgm240sd22vna.h index e183f2986e..a1695dafdc 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm240sd22vna.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm240sd22vna.h @@ -644,262 +644,262 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ #else #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) || SL_TRUSTZONE_PERIPHERAL_MVP_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MVP_S) && (SL_TRUSTZONE_PERIPHERAL_MVP_S != 0))) #define MVP_BASE (MVP_S_BASE) /* MVP base address */ #else #define MVP_BASE (MVP_NS_BASE) /* MVP base address */ diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_dma_descriptor.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_dma_descriptor.h index bd7ccb2cc7..e693c00a73 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_dma_descriptor.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_dma_descriptor.h @@ -27,6 +27,8 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef MGM24_DMA_DESCRIPTOR_H +#define MGM24_DMA_DESCRIPTOR_H #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ @@ -53,3 +55,5 @@ typedef struct { } DMA_DESCRIPTOR_TypeDef; /**< @} */ /** @} End of group Parts */ + +#endif /* MGM24_DMA_DESCRIPTOR_H */ diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldmaxbar_defines.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldmaxbar_defines.h index 5deddf9b73..bd2e97184a 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_ldmaxbar_defines.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef MGM24_LDMAXBAR_DEFINES_H +#define MGM24_LDMAXBAR_DEFINES_H + /* Module source selection indices */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ @@ -150,3 +153,5 @@ #define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ << 0) /** Shifted Mode VDAC0CH1_REQ for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ << 0) /** Shifted Mode VDAC1CH0_REQ for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ << 0) /** Shifted Mode VDAC1CH1_REQ for LDMAXBAR_CH_REQSEL**/ + +#endif /* MGM24_LDMAXBAR_DEFINES_H */ diff --git a/platform/Device/SiliconLabs/MGM24/Include/mgm24_prs_signals.h b/platform/Device/SiliconLabs/MGM24/Include/mgm24_prs_signals.h index 861fb322d0..ab56436fa8 100644 --- a/platform/Device/SiliconLabs/MGM24/Include/mgm24_prs_signals.h +++ b/platform/Device/SiliconLabs/MGM24/Include/mgm24_prs_signals.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef MGM24_PRS_SIGNALS_H +#define MGM24_PRS_SIGNALS_H + /** Synchronous signal sources enumeration: */ #define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) #define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) @@ -969,3 +972,5 @@ #define PRS_LFRCO_CALMEAS (PRS_ASYNC_LFRCO_CALMEAS) #define PRS_LFRCO_SDM (PRS_ASYNC_LFRCO_SDM) #define PRS_LFRCO_TCMEAS (PRS_ASYNC_LFRCO_TCMEAS) + +#endif /* MGM24_PRS_SIGNALS_H */ diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm230sa27hgn.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm230sa27hgn.h index 5149ca081c..039af37b83 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm230sa27hgn.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm230sa27hgn.h @@ -701,277 +701,277 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm230sa27hnn.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm230sa27hnn.h index 09dd4e8633..a80bad872b 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm230sa27hnn.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm230sa27hnn.h @@ -701,277 +701,277 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm230sb27hgn.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm230sb27hgn.h index daa86ff93f..ca4bd43c3b 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm230sb27hgn.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm230sb27hgn.h @@ -702,277 +702,277 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm230sb27hnn.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm230sb27hnn.h index 29cbdf7d70..0c4794d00a 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm230sb27hnn.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm230sb27hnn.h @@ -702,277 +702,277 @@ typedef enum IRQn{ #endif -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ #else #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || SL_TRUSTZONE_PERIPHERAL_EMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) #define EMU_BASE (EMU_S_BASE) /* EMU base address */ #else #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || SL_TRUSTZONE_PERIPHERAL_CMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) #define CMU_BASE (CMU_S_BASE) /* CMU base address */ #else #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ #else #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || SL_TRUSTZONE_PERIPHERAL_FSRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ #else #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || SL_TRUSTZONE_PERIPHERAL_DPLL0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ #else #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || SL_TRUSTZONE_PERIPHERAL_LFXO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ #else #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_LFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ #else #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ #else #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || SL_TRUSTZONE_PERIPHERAL_MSC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) #define MSC_BASE (MSC_S_BASE) /* MSC base address */ #else #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ #else #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || SL_TRUSTZONE_PERIPHERAL_PRS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) #define PRS_BASE (PRS_S_BASE) /* PRS base address */ #else #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || SL_TRUSTZONE_PERIPHERAL_GPIO_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ #else #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || SL_TRUSTZONE_PERIPHERAL_LDMA_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ #else #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ #else #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ #else #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ #else #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ #else #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER3_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ #else #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || SL_TRUSTZONE_PERIPHERAL_TIMER4_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ #else #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || SL_TRUSTZONE_PERIPHERAL_USART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ #else #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || SL_TRUSTZONE_PERIPHERAL_BURTC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ #else #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || SL_TRUSTZONE_PERIPHERAL_I2C1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ #else #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #else #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ #else #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || SL_TRUSTZONE_PERIPHERAL_BURAM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ #else #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || SL_TRUSTZONE_PERIPHERAL_GPCRC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ #else #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || SL_TRUSTZONE_PERIPHERAL_DCDC_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ #else #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ #else #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ #else #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART2_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) #define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ #else #define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART2_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ #else #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || SL_TRUSTZONE_PERIPHERAL_LCD_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) #define LCD_BASE (LCD_S_BASE) /* LCD base address */ #else #define LCD_BASE (LCD_NS_BASE) /* LCD base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCD_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ #else #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || SL_TRUSTZONE_PERIPHERAL_DMEM_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ #else #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || SL_TRUSTZONE_PERIPHERAL_LCDRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) #define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ #else #define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LCDRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) #define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ #else #define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ #else #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #else #define SMU_BASE (SMU_S_BASE) /* SMU base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ #else #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ #else #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || SL_TRUSTZONE_PERIPHERAL_IADC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ #else #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ #else #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || SL_TRUSTZONE_PERIPHERAL_ACMP1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ #else #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ #else #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || SL_TRUSTZONE_PERIPHERAL_VDAC0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ #else #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || SL_TRUSTZONE_PERIPHERAL_PCNT0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ #else #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || SL_TRUSTZONE_PERIPHERAL_LESENSE_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) #define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ #else #define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_LESENSE_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ #else #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || SL_TRUSTZONE_PERIPHERAL_HFXO0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ #else #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || SL_TRUSTZONE_PERIPHERAL_I2C0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ #else #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ #else #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || SL_TRUSTZONE_PERIPHERAL_WDOG1_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ #else #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || SL_TRUSTZONE_PERIPHERAL_EUSART0_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ #else #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ #else #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dma_descriptor.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dma_descriptor.h index 50e8c736cc..d1b322f5c6 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dma_descriptor.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_dma_descriptor.h @@ -27,6 +27,8 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef ZGM23_DMA_DESCRIPTOR_H +#define ZGM23_DMA_DESCRIPTOR_H #if defined(__ICCARM__) #pragma system_include /* Treat file as system include file. */ @@ -53,3 +55,5 @@ typedef struct { } DMA_DESCRIPTOR_TypeDef; /**< @} */ /** @} End of group Parts */ + +#endif /* ZGM23_DMA_DESCRIPTOR_H */ diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldmaxbar_defines.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldmaxbar_defines.h index 8763355840..1e7992ac02 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldmaxbar_defines.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_ldmaxbar_defines.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef ZGM23_LDMAXBAR_DEFINES_H +#define ZGM23_LDMAXBAR_DEFINES_H + /* Module source selection indices */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ #define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ @@ -158,3 +161,5 @@ #define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL << 0) /** Shifted Mode EUSART2TXFL for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO (_LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO << 0) /** Shifted Mode LESENSEFIFO for LDMAXBAR_CH_REQSEL**/ #define LDMAXBAR_CH_REQSEL_SIGSEL_LCD (_LDMAXBAR_CH_REQSEL_SIGSEL_LCD << 0) /** Shifted Mode LCD for LDMAXBAR_CH_REQSEL**/ + +#endif /* ZGM23_LDMAXBAR_DEFINES_H */ diff --git a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_prs_signals.h b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_prs_signals.h index d9511a7035..6e52e745c6 100644 --- a/platform/Device/SiliconLabs/ZGM23/Include/zgm23_prs_signals.h +++ b/platform/Device/SiliconLabs/ZGM23/Include/zgm23_prs_signals.h @@ -27,6 +27,9 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef ZGM23_PRS_SIGNALS_H +#define ZGM23_PRS_SIGNALS_H + /** Synchronous signal sources enumeration: */ #define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) #define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) @@ -971,3 +974,5 @@ #define PRS_EUSART2L_TXC (PRS_ASYNC_EUSART2L_TXC) #define PRS_EUSART2L_RXFL (PRS_ASYNC_EUSART2L_RXFL) #define PRS_EUSART2L_TXFL (PRS_ASYNC_EUSART2L_TXFL) + +#endif /* ZGM23_PRS_SIGNALS_H */ diff --git a/platform/Device/component/bgm111a256v2.slcc b/platform/Device/component/bgm111a256v2.slcc index e7375f060f..b0c3a5e76c 100644 --- a/platform/Device/component/bgm111a256v2.slcc +++ b/platform/Device/component/bgm111a256v2.slcc @@ -69,6 +69,7 @@ - name: device - name: device_series_1 - name: device_sdid_80 + - name: device_generic_family_efr32xg11 - name: device_family_bgm1 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm111e256v2.slcc b/platform/Device/component/bgm111e256v2.slcc index f2108c534e..5e94bdc520 100644 --- a/platform/Device/component/bgm111e256v2.slcc +++ b/platform/Device/component/bgm111e256v2.slcc @@ -69,6 +69,7 @@ - name: device - name: device_series_1 - name: device_sdid_80 + - name: device_generic_family_efr32xg11 - name: device_family_bgm1 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm113a256v2.slcc b/platform/Device/component/bgm113a256v2.slcc index d97f6865fc..02611ea666 100644 --- a/platform/Device/component/bgm113a256v2.slcc +++ b/platform/Device/component/bgm113a256v2.slcc @@ -69,6 +69,7 @@ - name: device - name: device_series_1 - name: device_sdid_80 + - name: device_generic_family_efr32xg11 - name: device_family_bgm1 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm11s12f256ga.slcc b/platform/Device/component/bgm11s12f256ga.slcc index 77249635ea..2cf8e8a3e9 100644 --- a/platform/Device/component/bgm11s12f256ga.slcc +++ b/platform/Device/component/bgm11s12f256ga.slcc @@ -69,6 +69,7 @@ - name: device - name: device_series_1 - name: device_sdid_80 + - name: device_generic_family_efr32xg11 - name: device_family_bgm1 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm11s22f256ga.slcc b/platform/Device/component/bgm11s22f256ga.slcc index 305462e304..42e51891b7 100644 --- a/platform/Device/component/bgm11s22f256ga.slcc +++ b/platform/Device/component/bgm11s22f256ga.slcc @@ -69,6 +69,7 @@ - name: device - name: device_series_1 - name: device_sdid_80 + - name: device_generic_family_efr32xg11 - name: device_family_bgm1 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm121a256v2.slcc b/platform/Device/component/bgm121a256v2.slcc index 6a3e008625..b076566f26 100644 --- a/platform/Device/component/bgm121a256v2.slcc +++ b/platform/Device/component/bgm121a256v2.slcc @@ -69,6 +69,7 @@ - name: device - name: device_series_1 - name: device_sdid_80 + - name: device_generic_family_efr32xg11 - name: device_family_bgm1 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm121n256v2.slcc b/platform/Device/component/bgm121n256v2.slcc index a28763cc65..052f0f0f47 100644 --- a/platform/Device/component/bgm121n256v2.slcc +++ b/platform/Device/component/bgm121n256v2.slcc @@ -69,6 +69,7 @@ - name: device - name: device_series_1 - name: device_sdid_80 + - name: device_generic_family_efr32xg11 - name: device_family_bgm1 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm123a256v2.slcc b/platform/Device/component/bgm123a256v2.slcc index c63218bdaf..b3ae388270 100644 --- a/platform/Device/component/bgm123a256v2.slcc +++ b/platform/Device/component/bgm123a256v2.slcc @@ -69,6 +69,7 @@ - name: device - name: device_series_1 - name: device_sdid_80 + - name: device_generic_family_efr32xg11 - name: device_family_bgm1 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm123n256v2.slcc b/platform/Device/component/bgm123n256v2.slcc index 28c55ac552..a7c8078bc1 100644 --- a/platform/Device/component/bgm123n256v2.slcc +++ b/platform/Device/component/bgm123n256v2.slcc @@ -69,6 +69,7 @@ - name: device - name: device_series_1 - name: device_sdid_80 + - name: device_generic_family_efr32xg11 - name: device_family_bgm1 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm13p22f512ga.slcc b/platform/Device/component/bgm13p22f512ga.slcc index 0a3299a521..104945594b 100644 --- a/platform/Device/component/bgm13p22f512ga.slcc +++ b/platform/Device/component/bgm13p22f512ga.slcc @@ -81,6 +81,7 @@ - name: device - name: device_series_1 - name: device_sdid_89 + - name: device_generic_family_efr32xg13 - name: device_family_bgm13 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm13p22f512ge.slcc b/platform/Device/component/bgm13p22f512ge.slcc index 16dd182231..20425fbebe 100644 --- a/platform/Device/component/bgm13p22f512ge.slcc +++ b/platform/Device/component/bgm13p22f512ge.slcc @@ -81,6 +81,7 @@ - name: device - name: device_series_1 - name: device_sdid_89 + - name: device_generic_family_efr32xg13 - name: device_family_bgm13 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm13p32f512ga.slcc b/platform/Device/component/bgm13p32f512ga.slcc index 7c36f4091b..a0f244871f 100644 --- a/platform/Device/component/bgm13p32f512ga.slcc +++ b/platform/Device/component/bgm13p32f512ga.slcc @@ -81,6 +81,7 @@ - name: device - name: device_series_1 - name: device_sdid_89 + - name: device_generic_family_efr32xg13 - name: device_family_bgm13 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm13p32f512ge.slcc b/platform/Device/component/bgm13p32f512ge.slcc index 62a084db23..5ebc5f421f 100644 --- a/platform/Device/component/bgm13p32f512ge.slcc +++ b/platform/Device/component/bgm13p32f512ge.slcc @@ -81,6 +81,7 @@ - name: device - name: device_series_1 - name: device_sdid_89 + - name: device_generic_family_efr32xg13 - name: device_family_bgm13 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm13s22f512ga.slcc b/platform/Device/component/bgm13s22f512ga.slcc index 242fc15ce1..f3a8d86ae8 100644 --- a/platform/Device/component/bgm13s22f512ga.slcc +++ b/platform/Device/component/bgm13s22f512ga.slcc @@ -81,6 +81,7 @@ - name: device - name: device_series_1 - name: device_sdid_89 + - name: device_generic_family_efr32xg13 - name: device_family_bgm13 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm13s22f512gn.slcc b/platform/Device/component/bgm13s22f512gn.slcc index 491f29b83f..a4f8685c51 100644 --- a/platform/Device/component/bgm13s22f512gn.slcc +++ b/platform/Device/component/bgm13s22f512gn.slcc @@ -81,6 +81,7 @@ - name: device - name: device_series_1 - name: device_sdid_89 + - name: device_generic_family_efr32xg13 - name: device_family_bgm13 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm13s32f512ga.slcc b/platform/Device/component/bgm13s32f512ga.slcc index f208c0b7bf..3ccdcd1feb 100644 --- a/platform/Device/component/bgm13s32f512ga.slcc +++ b/platform/Device/component/bgm13s32f512ga.slcc @@ -81,6 +81,7 @@ - name: device - name: device_series_1 - name: device_sdid_89 + - name: device_generic_family_efr32xg13 - name: device_family_bgm13 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm13s32f512gn.slcc b/platform/Device/component/bgm13s32f512gn.slcc index e966a074d4..fc80387ecd 100644 --- a/platform/Device/component/bgm13s32f512gn.slcc +++ b/platform/Device/component/bgm13s32f512gn.slcc @@ -81,6 +81,7 @@ - name: device - name: device_series_1 - name: device_sdid_89 + - name: device_generic_family_efr32xg13 - name: device_family_bgm13 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm210la22jif.slcc b/platform/Device/component/bgm210la22jif.slcc index 18482212d3..1edf17258e 100644 --- a/platform/Device/component/bgm210la22jif.slcc +++ b/platform/Device/component/bgm210la22jif.slcc @@ -66,6 +66,7 @@ - name: device - name: device_series_2 - name: device_sdid_200 + - name: device_generic_family_efr32xg21 - name: device_family_bgm21 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm210la22jnf.slcc b/platform/Device/component/bgm210la22jnf.slcc index ef9cfe7051..4245864e29 100644 --- a/platform/Device/component/bgm210la22jnf.slcc +++ b/platform/Device/component/bgm210la22jnf.slcc @@ -66,6 +66,7 @@ - name: device - name: device_series_2 - name: device_sdid_200 + - name: device_generic_family_efr32xg21 - name: device_family_bgm21 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm210p022jia.slcc b/platform/Device/component/bgm210p022jia.slcc index 7fa2049649..42e139e5b9 100644 --- a/platform/Device/component/bgm210p022jia.slcc +++ b/platform/Device/component/bgm210p022jia.slcc @@ -66,6 +66,7 @@ - name: device - name: device_series_2 - name: device_sdid_200 + - name: device_generic_family_efr32xg21 - name: device_family_bgm21 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm210p032jia.slcc b/platform/Device/component/bgm210p032jia.slcc index dd382584b1..1417acfa71 100644 --- a/platform/Device/component/bgm210p032jia.slcc +++ b/platform/Device/component/bgm210p032jia.slcc @@ -66,6 +66,7 @@ - name: device - name: device_series_2 - name: device_sdid_200 + - name: device_generic_family_efr32xg21 - name: device_family_bgm21 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm210pa22jia.slcc b/platform/Device/component/bgm210pa22jia.slcc index 23163f1409..cc04fac927 100644 --- a/platform/Device/component/bgm210pa22jia.slcc +++ b/platform/Device/component/bgm210pa22jia.slcc @@ -66,6 +66,7 @@ - name: device - name: device_series_2 - name: device_sdid_200 + - name: device_generic_family_efr32xg21 - name: device_family_bgm21 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm210pa32jia.slcc b/platform/Device/component/bgm210pa32jia.slcc index 6ce4d32de3..5947154874 100644 --- a/platform/Device/component/bgm210pa32jia.slcc +++ b/platform/Device/component/bgm210pa32jia.slcc @@ -66,6 +66,7 @@ - name: device - name: device_series_2 - name: device_sdid_200 + - name: device_generic_family_efr32xg21 - name: device_family_bgm21 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm210pb22jia.slcc b/platform/Device/component/bgm210pb22jia.slcc index d17aa4e750..97a3d64a74 100644 --- a/platform/Device/component/bgm210pb22jia.slcc +++ b/platform/Device/component/bgm210pb22jia.slcc @@ -66,6 +66,7 @@ - name: device - name: device_series_2 - name: device_sdid_200 + - name: device_generic_family_efr32xg21 - name: device_family_bgm21 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm210pb32jia.slcc b/platform/Device/component/bgm210pb32jia.slcc index c9beaa646a..aee84945b9 100644 --- a/platform/Device/component/bgm210pb32jia.slcc +++ b/platform/Device/component/bgm210pb32jia.slcc @@ -66,6 +66,7 @@ - name: device - name: device_series_2 - name: device_sdid_200 + - name: device_generic_family_efr32xg21 - name: device_family_bgm21 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm220pc22hna.slcc b/platform/Device/component/bgm220pc22hna.slcc index 37a5acefc4..15cb140003 100644 --- a/platform/Device/component/bgm220pc22hna.slcc +++ b/platform/Device/component/bgm220pc22hna.slcc @@ -66,6 +66,7 @@ - name: device - name: device_series_2 - name: device_sdid_205 + - name: device_generic_family_efr32xg22 - name: device_family_bgm22 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm220pc22wga.slcc b/platform/Device/component/bgm220pc22wga.slcc index 12fccbbcb1..6b14c0347e 100644 --- a/platform/Device/component/bgm220pc22wga.slcc +++ b/platform/Device/component/bgm220pc22wga.slcc @@ -66,6 +66,7 @@ - name: device - name: device_series_2 - name: device_sdid_205 + - name: device_generic_family_efr32xg22 - name: device_family_bgm22 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm220sc12wga.slcc b/platform/Device/component/bgm220sc12wga.slcc index 7c15e78d7e..6ef96ad629 100644 --- a/platform/Device/component/bgm220sc12wga.slcc +++ b/platform/Device/component/bgm220sc12wga.slcc @@ -66,6 +66,7 @@ - name: device - name: device_series_2 - name: device_sdid_205 + - name: device_generic_family_efr32xg22 - name: device_family_bgm22 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm220sc22hna.slcc b/platform/Device/component/bgm220sc22hna.slcc index 57cb3dcff0..fb928d05d5 100644 --- a/platform/Device/component/bgm220sc22hna.slcc +++ b/platform/Device/component/bgm220sc22hna.slcc @@ -66,6 +66,7 @@ - name: device - name: device_series_2 - name: device_sdid_205 + - name: device_generic_family_efr32xg22 - name: device_family_bgm22 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm220sc22wga.slcc b/platform/Device/component/bgm220sc22wga.slcc index 3978b7ed6d..7a0589d27c 100644 --- a/platform/Device/component/bgm220sc22wga.slcc +++ b/platform/Device/component/bgm220sc22wga.slcc @@ -66,6 +66,7 @@ - name: device - name: device_series_2 - name: device_sdid_205 + - name: device_generic_family_efr32xg22 - name: device_family_bgm22 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm240pa22vna.slcc b/platform/Device/component/bgm240pa22vna.slcc index de723abda2..954fa51ffa 100644 --- a/platform/Device/component/bgm240pa22vna.slcc +++ b/platform/Device/component/bgm240pa22vna.slcc @@ -49,6 +49,7 @@ - path: bgm24_mailbox.h - path: bgm24_mpahbram.h - path: bgm24_msc.h + - path: bgm24_mvp.h - path: bgm24_pcnt.h - path: bgm24_prs.h - path: bgm24_prs_signals.h @@ -72,6 +73,7 @@ - name: device - name: device_series_2 - name: device_sdid_215 + - name: device_generic_family_efr32xg24 - name: device_family_bgm24 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm240pa32vna.slcc b/platform/Device/component/bgm240pa32vna.slcc index 1a6f3570c0..575a330880 100644 --- a/platform/Device/component/bgm240pa32vna.slcc +++ b/platform/Device/component/bgm240pa32vna.slcc @@ -49,6 +49,7 @@ - path: bgm24_mailbox.h - path: bgm24_mpahbram.h - path: bgm24_msc.h + - path: bgm24_mvp.h - path: bgm24_pcnt.h - path: bgm24_prs.h - path: bgm24_prs_signals.h @@ -72,6 +73,7 @@ - name: device - name: device_series_2 - name: device_sdid_215 + - name: device_generic_family_efr32xg24 - name: device_family_bgm24 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm240pa32vnn.slcc b/platform/Device/component/bgm240pa32vnn.slcc index 33b348bf44..2401063eb1 100644 --- a/platform/Device/component/bgm240pa32vnn.slcc +++ b/platform/Device/component/bgm240pa32vnn.slcc @@ -49,6 +49,7 @@ - path: bgm24_mailbox.h - path: bgm24_mpahbram.h - path: bgm24_msc.h + - path: bgm24_mvp.h - path: bgm24_pcnt.h - path: bgm24_prs.h - path: bgm24_prs_signals.h @@ -72,6 +73,7 @@ - name: device - name: device_series_2 - name: device_sdid_215 + - name: device_generic_family_efr32xg24 - name: device_family_bgm24 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm240pb22vna.slcc b/platform/Device/component/bgm240pb22vna.slcc index e69de4c6fc..a847b99d31 100644 --- a/platform/Device/component/bgm240pb22vna.slcc +++ b/platform/Device/component/bgm240pb22vna.slcc @@ -49,6 +49,7 @@ - path: bgm24_mailbox.h - path: bgm24_mpahbram.h - path: bgm24_msc.h + - path: bgm24_mvp.h - path: bgm24_pcnt.h - path: bgm24_prs.h - path: bgm24_prs_signals.h @@ -72,6 +73,7 @@ - name: device - name: device_series_2 - name: device_sdid_215 + - name: device_generic_family_efr32xg24 - name: device_family_bgm24 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm240pb32vna.slcc b/platform/Device/component/bgm240pb32vna.slcc index 708880d2a3..e82a78d316 100644 --- a/platform/Device/component/bgm240pb32vna.slcc +++ b/platform/Device/component/bgm240pb32vna.slcc @@ -49,6 +49,7 @@ - path: bgm24_mailbox.h - path: bgm24_mpahbram.h - path: bgm24_msc.h + - path: bgm24_mvp.h - path: bgm24_pcnt.h - path: bgm24_prs.h - path: bgm24_prs_signals.h @@ -72,6 +73,7 @@ - name: device - name: device_series_2 - name: device_sdid_215 + - name: device_generic_family_efr32xg24 - name: device_family_bgm24 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm240pb32vnn.slcc b/platform/Device/component/bgm240pb32vnn.slcc index 21551b2d34..3550f2b8a1 100644 --- a/platform/Device/component/bgm240pb32vnn.slcc +++ b/platform/Device/component/bgm240pb32vnn.slcc @@ -49,6 +49,7 @@ - path: bgm24_mailbox.h - path: bgm24_mpahbram.h - path: bgm24_msc.h + - path: bgm24_mvp.h - path: bgm24_pcnt.h - path: bgm24_prs.h - path: bgm24_prs_signals.h @@ -72,6 +73,7 @@ - name: device - name: device_series_2 - name: device_sdid_215 + - name: device_generic_family_efr32xg24 - name: device_family_bgm24 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm240sa22vna.slcc b/platform/Device/component/bgm240sa22vna.slcc index 3dbc7494e7..c93fc371a9 100644 --- a/platform/Device/component/bgm240sa22vna.slcc +++ b/platform/Device/component/bgm240sa22vna.slcc @@ -49,6 +49,7 @@ - path: bgm24_mailbox.h - path: bgm24_mpahbram.h - path: bgm24_msc.h + - path: bgm24_mvp.h - path: bgm24_pcnt.h - path: bgm24_prs.h - path: bgm24_prs_signals.h @@ -72,6 +73,7 @@ - name: device - name: device_series_2 - name: device_sdid_215 + - name: device_generic_family_efr32xg24 - name: device_family_bgm24 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm240sb22vna.slcc b/platform/Device/component/bgm240sb22vna.slcc index cdfa9af41f..390605d4df 100644 --- a/platform/Device/component/bgm240sb22vna.slcc +++ b/platform/Device/component/bgm240sb22vna.slcc @@ -49,6 +49,7 @@ - path: bgm24_mailbox.h - path: bgm24_mpahbram.h - path: bgm24_msc.h + - path: bgm24_mvp.h - path: bgm24_pcnt.h - path: bgm24_prs.h - path: bgm24_prs_signals.h @@ -72,6 +73,7 @@ - name: device - name: device_series_2 - name: device_sdid_215 + - name: device_generic_family_efr32xg24 - name: device_family_bgm24 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm241sb22vna.slcc b/platform/Device/component/bgm241sb22vna.slcc index 861c2948ec..2db19812de 100644 --- a/platform/Device/component/bgm241sb22vna.slcc +++ b/platform/Device/component/bgm241sb22vna.slcc @@ -49,6 +49,7 @@ - path: bgm24_mailbox.h - path: bgm24_mpahbram.h - path: bgm24_msc.h + - path: bgm24_mvp.h - path: bgm24_pcnt.h - path: bgm24_prs.h - path: bgm24_prs_signals.h @@ -72,6 +73,7 @@ - name: device - name: device_series_2 - name: device_sdid_215 + - name: device_generic_family_efr32xg24 - name: device_family_bgm24 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/bgm241sd22vna.slcc b/platform/Device/component/bgm241sd22vna.slcc new file mode 100644 index 0000000000..a4e136bf56 --- /dev/null +++ b/platform/Device/component/bgm241sd22vna.slcc @@ -0,0 +1,238 @@ +!!omap +- id: BGM241SD22VNA +- package: platform +- description: Silicon Labs CMSIS-Device part headers for BGM241SD22VNA. +- category: Platform|Device|BGM24 +- quality: production +- define: + - name: BGM241SD22VNA + unless: + - device_content_override +- source: + - path: platform/Device/SiliconLabs/BGM24/Source/system_bgm24.c + unless: + - device_content_override + - path: platform/Device/SiliconLabs/BGM24/Source/startup_bgm24.c + unless: + - device_content_override +- include: + - file_list: + - path: bgm241sd22vna.h + - path: bgm24_acmp.h + - path: bgm24_aes.h + - path: bgm24_amuxcp.h + - path: bgm24_buram.h + - path: bgm24_burtc.h + - path: bgm24_cmu.h + - path: bgm24_dcdc.h + - path: bgm24_devinfo.h + - path: bgm24_dma_descriptor.h + - path: bgm24_dpll.h + - path: bgm24_emu.h + - path: bgm24_eusart.h + - path: bgm24_fsrco.h + - path: bgm24_gpcrc.h + - path: bgm24_gpio.h + - path: bgm24_gpio_port.h + - path: bgm24_hfrco.h + - path: bgm24_hfxo.h + - path: bgm24_i2c.h + - path: bgm24_iadc.h + - path: bgm24_icache.h + - path: bgm24_keyscan.h + - path: bgm24_ldma.h + - path: bgm24_ldmaxbar.h + - path: bgm24_ldmaxbar_defines.h + - path: bgm24_letimer.h + - path: bgm24_lfrco.h + - path: bgm24_lfxo.h + - path: bgm24_mailbox.h + - path: bgm24_mpahbram.h + - path: bgm24_msc.h + - path: bgm24_mvp.h + - path: bgm24_pcnt.h + - path: bgm24_prs.h + - path: bgm24_prs_signals.h + - path: bgm24_scratchpad.h + - path: bgm24_semailbox.h + - path: bgm24_smu.h + - path: bgm24_syscfg.h + - path: bgm24_sysrtc.h + - path: bgm24_timer.h + - path: bgm24_ulfrco.h + - path: bgm24_usart.h + - path: bgm24_vdac.h + - path: bgm24_wdog.h + - path: em_device.h + - path: system_bgm24.h + path: platform/Device/SiliconLabs/BGM24/Include/ + unless: + - device_content_override +- provides: + - name: bgm241sd22vna + - name: device + - name: device_series_2 + - name: device_sdid_215 + - name: device_generic_family_efr32xg24 + - name: device_family_bgm24 + - name: device_cortexm + - name: device_arm + - name: cortexm33 + - name: armv8m.main + - name: device_is_module + - name: hardware_board_has_hfxo + - name: device_security_vault + - name: device_dcdc_buck + - name: device_pa_10dbm + - name: device_has_acmp + - name: device_has_acmp0 + - name: device_has_acmp1 + - name: device_has_amuxcp + - name: device_has_amuxcp0 + - name: device_has_buram + - name: device_has_burtc + - name: device_has_cmu + - name: device_has_dcdc + - name: device_has_devinfo + - name: device_has_dmem + - name: device_has_dpll + - name: device_has_dpll0 + - name: device_has_emu + - name: device_has_euart + - name: device_has_eusart + - name: device_has_eusart0 + - name: device_has_eusart1 + - name: device_has_fsrco + - name: device_has_gpcrc + - name: device_has_gpio + - name: device_has_hfrco + - name: device_has_hfrco0 + - name: device_has_hfrcoem2 + - name: device_has_hfrcoem23 + - name: device_has_hfxo + - name: device_has_hfxo0 + - name: device_has_hostmailbox + - name: device_has_i2c + - name: device_has_i2c0 + - name: device_has_i2c1 + - name: device_has_iadc + - name: device_has_iadc0 + - name: device_has_icache + - name: device_has_icache0 + - name: device_has_keyscan + - name: device_has_ldma + - name: device_has_ldmaxbar + - name: device_has_letimer + - name: device_has_letimer0 + - name: device_has_lfrco + - name: device_has_lfxo + - name: device_has_msc + - name: device_has_mvp + - name: device_has_pcnt + - name: device_has_pcnt0 + - name: device_has_prs + - name: device_has_radioaes + - name: device_has_scratchpad + - name: device_has_semailbox + - name: device_has_smu + - name: device_has_syscfg + - name: device_has_sysrtc + - name: device_has_sysrtc0 + - name: device_has_timer + - name: device_has_timer0 + - name: device_has_timer1 + - name: device_has_timer2 + - name: device_has_timer3 + - name: device_has_timer4 + - name: device_has_uart + - name: device_has_ulfrco + - name: device_has_usart + - name: device_has_usart0 + - name: device_has_vdac + - name: device_has_vdac0 + - name: device_has_vdac1 + - name: device_has_wdog + - name: device_has_wdog0 + - name: device_has_wdog1 + - name: device_has_dwt + - name: device_has_emu_temp_sensor + - name: device_has_fpu + - name: device_has_mpu + - name: device_has_radio + - name: device_has_radio_2g4hz + - name: device_supports_rail + - name: device_no_rail_api + - name: device_supports_bluetooth + - name: device_supports_bluetooth_iq_sampling + - name: device_supports_bluetooth_antenna_switching + - name: device_supports_bluetooth_coded_phy + - name: device_supports_bluetooth_cte + - name: device_supports_connect + - name: device_compute_mvp +- recommends: + - id: trustzone_unaware +- requires: + - name: cmsis_core + - name: BGM241SD22VNA_config +- template_contribution: + - name: device_opn + value: BGM241SD22VNA + - name: device_arch + value: armv8m.main + - name: device_cpu + value: cortexm33 + - name: device_series + value: 2 + - name: device_family + value: bgm24 + - name: device_flash_addr + value: 134217728 + - name: device_flash_size + value: 1572864 + - name: device_flash_page_size + value: 8192 + - name: device_ram_addr + value: 536870912 + - name: device_ram_size + value: 262144 + - name: device_fpu + value: true + - name: device_mpu + value: true + - name: default_stack_size + value: 4096 + - name: default_heap_size + value: 2048 +- tag: + - device:opn:bgm241sd22vna +- toolchain_settings: + - option: device_opn + value: bgm241sd22vna + - option: architecture + value: armv8-mml + - option: cpu + value: cortex-m33 + - option: fpu + value: fpv5-sp + - option: cmse + unless: + - trustzone_nonsecure + value: enabled +- config_file: + - condition: + - custom_radio_config + directory: rail + path: platform/Device/config/215/device.yaml +- metadata: + device: + memory: + - name: Main Flash + page_size: 8192 + size: 1572864 + start: 134217728 + type: non-volatile + - name: RAM + size: 262144 + start: 536870912 + type: volatile + opn: bgm241sd22vna diff --git a/platform/Device/component/efr32bg24b210f1536im48.slcc b/platform/Device/component/efr32bg24b210f1536im48.slcc new file mode 100644 index 0000000000..63d41a8f4c --- /dev/null +++ b/platform/Device/component/efr32bg24b210f1536im48.slcc @@ -0,0 +1,235 @@ +!!omap +- id: EFR32BG24B210F1536IM48 +- package: platform +- description: Silicon Labs CMSIS-Device part headers for EFR32BG24B210F1536IM48. +- category: Platform|Device|EFR32BG24 +- quality: production +- define: + - name: EFR32BG24B210F1536IM48 + unless: + - device_content_override +- source: + - path: platform/Device/SiliconLabs/EFR32BG24/Source/system_efr32bg24.c + unless: + - device_content_override + - path: platform/Device/SiliconLabs/EFR32BG24/Source/startup_efr32bg24.c + unless: + - device_content_override +- include: + - file_list: + - path: efr32bg24b210f1536im48.h + - path: efr32bg24_acmp.h + - path: efr32bg24_aes.h + - path: efr32bg24_amuxcp.h + - path: efr32bg24_buram.h + - path: efr32bg24_burtc.h + - path: efr32bg24_cmu.h + - path: efr32bg24_dcdc.h + - path: efr32bg24_devinfo.h + - path: efr32bg24_dma_descriptor.h + - path: efr32bg24_dpll.h + - path: efr32bg24_emu.h + - path: efr32bg24_eusart.h + - path: efr32bg24_fsrco.h + - path: efr32bg24_gpcrc.h + - path: efr32bg24_gpio.h + - path: efr32bg24_gpio_port.h + - path: efr32bg24_hfrco.h + - path: efr32bg24_hfxo.h + - path: efr32bg24_i2c.h + - path: efr32bg24_iadc.h + - path: efr32bg24_icache.h + - path: efr32bg24_keyscan.h + - path: efr32bg24_ldma.h + - path: efr32bg24_ldmaxbar.h + - path: efr32bg24_ldmaxbar_defines.h + - path: efr32bg24_letimer.h + - path: efr32bg24_lfrco.h + - path: efr32bg24_lfxo.h + - path: efr32bg24_mailbox.h + - path: efr32bg24_mpahbram.h + - path: efr32bg24_msc.h + - path: efr32bg24_mvp.h + - path: efr32bg24_pcnt.h + - path: efr32bg24_prs.h + - path: efr32bg24_prs_signals.h + - path: efr32bg24_scratchpad.h + - path: efr32bg24_semailbox.h + - path: efr32bg24_smu.h + - path: efr32bg24_syscfg.h + - path: efr32bg24_sysrtc.h + - path: efr32bg24_timer.h + - path: efr32bg24_ulfrco.h + - path: efr32bg24_usart.h + - path: efr32bg24_vdac.h + - path: efr32bg24_wdog.h + - path: em_device.h + - path: system_efr32bg24.h + path: platform/Device/SiliconLabs/EFR32BG24/Include/ + unless: + - device_content_override +- provides: + - name: efr32bg24b210f1536im48 + - name: device + - name: device_series_2 + - name: device_sdid_215 + - name: device_generic_family_efr32xg24 + - name: device_family_efr32bg24 + - name: device_cortexm + - name: device_arm + - name: cortexm33 + - name: armv8m.main + - name: device_security_vault + - name: device_dcdc_buck + - name: device_pa_10dbm + - name: device_has_acmp + - name: device_has_acmp0 + - name: device_has_acmp1 + - name: device_has_amuxcp + - name: device_has_amuxcp0 + - name: device_has_buram + - name: device_has_burtc + - name: device_has_cmu + - name: device_has_dcdc + - name: device_has_devinfo + - name: device_has_dmem + - name: device_has_dpll + - name: device_has_dpll0 + - name: device_has_emu + - name: device_has_euart + - name: device_has_eusart + - name: device_has_eusart0 + - name: device_has_eusart1 + - name: device_has_fsrco + - name: device_has_gpcrc + - name: device_has_gpio + - name: device_has_hfrco + - name: device_has_hfrco0 + - name: device_has_hfrcoem2 + - name: device_has_hfrcoem23 + - name: device_has_hfxo + - name: device_has_hfxo0 + - name: device_has_hostmailbox + - name: device_has_i2c + - name: device_has_i2c0 + - name: device_has_i2c1 + - name: device_has_iadc + - name: device_has_iadc0 + - name: device_has_icache + - name: device_has_icache0 + - name: device_has_keyscan + - name: device_has_ldma + - name: device_has_ldmaxbar + - name: device_has_letimer + - name: device_has_letimer0 + - name: device_has_lfrco + - name: device_has_lfxo + - name: device_has_msc + - name: device_has_mvp + - name: device_has_pcnt + - name: device_has_pcnt0 + - name: device_has_prs + - name: device_has_radioaes + - name: device_has_scratchpad + - name: device_has_semailbox + - name: device_has_smu + - name: device_has_syscfg + - name: device_has_sysrtc + - name: device_has_sysrtc0 + - name: device_has_timer + - name: device_has_timer0 + - name: device_has_timer1 + - name: device_has_timer2 + - name: device_has_timer3 + - name: device_has_timer4 + - name: device_has_uart + - name: device_has_ulfrco + - name: device_has_usart + - name: device_has_usart0 + - name: device_has_vdac + - name: device_has_vdac0 + - name: device_has_vdac1 + - name: device_has_wdog + - name: device_has_wdog0 + - name: device_has_wdog1 + - name: device_has_dwt + - name: device_has_emu_temp_sensor + - name: device_has_fpu + - name: device_has_mpu + - name: device_has_radio + - name: device_has_radio_2g4hz + - name: device_supports_rail + - name: device_supports_rail_stack + - name: device_supports_bluetooth + - name: device_supports_bluetooth_iq_sampling + - name: device_supports_bluetooth_antenna_switching + - name: device_supports_bluetooth_coded_phy + - name: device_supports_bluetooth_cte + - name: device_supports_connect + - name: device_compute_mvp +- recommends: + - id: trustzone_unaware +- requires: + - name: cmsis_core +- template_contribution: + - name: device_opn + value: EFR32BG24B210F1536IM48 + - name: device_arch + value: armv8m.main + - name: device_cpu + value: cortexm33 + - name: device_series + value: 2 + - name: device_family + value: efr32bg24 + - name: device_flash_addr + value: 134217728 + - name: device_flash_size + value: 1572864 + - name: device_flash_page_size + value: 8192 + - name: device_ram_addr + value: 536870912 + - name: device_ram_size + value: 262144 + - name: device_fpu + value: true + - name: device_mpu + value: true + - name: default_stack_size + value: 4096 + - name: default_heap_size + value: 2048 +- tag: + - device:opn:efr32bg24b210f1536im48 +- toolchain_settings: + - option: device_opn + value: efr32bg24b210f1536im48 + - option: architecture + value: armv8-mml + - option: cpu + value: cortex-m33 + - option: fpu + value: fpv5-sp + - option: cmse + unless: + - trustzone_nonsecure + value: enabled +- config_file: + - condition: + - custom_radio_config + directory: rail + path: platform/Device/config/215/device.yaml +- metadata: + device: + memory: + - name: Main Flash + page_size: 8192 + size: 1572864 + start: 134217728 + type: non-volatile + - name: RAM + size: 262144 + start: 536870912 + type: volatile + opn: efr32bg24b210f1536im48 diff --git a/platform/Device/component/efr32fg23b021f512im48.slcc b/platform/Device/component/efr32fg23b021f512im48.slcc new file mode 100644 index 0000000000..74ee85f33c --- /dev/null +++ b/platform/Device/component/efr32fg23b021f512im48.slcc @@ -0,0 +1,236 @@ +!!omap +- id: EFR32FG23B021F512IM48 +- package: platform +- description: Silicon Labs CMSIS-Device part headers for EFR32FG23B021F512IM48. +- category: Platform|Device|EFR32FG23 +- quality: production +- define: + - name: EFR32FG23B021F512IM48 + unless: + - device_content_override +- source: + - path: platform/Device/SiliconLabs/EFR32FG23/Source/system_efr32fg23.c + unless: + - device_content_override + - path: platform/Device/SiliconLabs/EFR32FG23/Source/startup_efr32fg23.c + unless: + - device_content_override +- include: + - file_list: + - path: efr32fg23b021f512im48.h + - path: efr32fg23_acmp.h + - path: efr32fg23_aes.h + - path: efr32fg23_amuxcp.h + - path: efr32fg23_buram.h + - path: efr32fg23_burtc.h + - path: efr32fg23_cmu.h + - path: efr32fg23_dcdc.h + - path: efr32fg23_devinfo.h + - path: efr32fg23_dma_descriptor.h + - path: efr32fg23_dpll.h + - path: efr32fg23_emu.h + - path: efr32fg23_eusart.h + - path: efr32fg23_fsrco.h + - path: efr32fg23_gpcrc.h + - path: efr32fg23_gpio.h + - path: efr32fg23_gpio_port.h + - path: efr32fg23_hfrco.h + - path: efr32fg23_hfxo.h + - path: efr32fg23_i2c.h + - path: efr32fg23_iadc.h + - path: efr32fg23_icache.h + - path: efr32fg23_keyscan.h + - path: efr32fg23_lcd.h + - path: efr32fg23_lcdrf.h + - path: efr32fg23_ldma.h + - path: efr32fg23_ldmaxbar.h + - path: efr32fg23_ldmaxbar_defines.h + - path: efr32fg23_lesense.h + - path: efr32fg23_letimer.h + - path: efr32fg23_lfrco.h + - path: efr32fg23_lfxo.h + - path: efr32fg23_mailbox.h + - path: efr32fg23_mpahbram.h + - path: efr32fg23_msc.h + - path: efr32fg23_pcnt.h + - path: efr32fg23_pfmxpprf.h + - path: efr32fg23_prs.h + - path: efr32fg23_prs_signals.h + - path: efr32fg23_scratchpad.h + - path: efr32fg23_semailbox.h + - path: efr32fg23_smu.h + - path: efr32fg23_syscfg.h + - path: efr32fg23_sysrtc.h + - path: efr32fg23_timer.h + - path: efr32fg23_ulfrco.h + - path: efr32fg23_usart.h + - path: efr32fg23_vdac.h + - path: efr32fg23_wdog.h + - path: em_device.h + - path: system_efr32fg23.h + path: platform/Device/SiliconLabs/EFR32FG23/Include/ + unless: + - device_content_override +- provides: + - name: efr32fg23b021f512im48 + - name: device + - name: device_series_2 + - name: device_sdid_210 + - name: device_generic_family_efr32xg23 + - name: device_family_efr32fg23 + - name: device_cortexm + - name: device_arm + - name: cortexm33 + - name: armv8m.main + - name: device_security_vault + - name: device_dcdc_buck + - name: device_pa_20dbm + - name: device_has_acmp + - name: device_has_acmp0 + - name: device_has_acmp1 + - name: device_has_amuxcp + - name: device_has_amuxcp0 + - name: device_has_buram + - name: device_has_burtc + - name: device_has_cmu + - name: device_has_dcdc + - name: device_has_devinfo + - name: device_has_dmem + - name: device_has_dpll + - name: device_has_dpll0 + - name: device_has_emu + - name: device_has_euart + - name: device_has_eusart + - name: device_has_eusart0 + - name: device_has_eusart1 + - name: device_has_eusart2 + - name: device_has_fsrco + - name: device_has_gpcrc + - name: device_has_gpio + - name: device_has_hfrco + - name: device_has_hfrco0 + - name: device_has_hfrcoem2 + - name: device_has_hfrcoem23 + - name: device_has_hfxo + - name: device_has_hfxo0 + - name: device_has_hostmailbox + - name: device_has_i2c + - name: device_has_i2c0 + - name: device_has_i2c1 + - name: device_has_iadc + - name: device_has_iadc0 + - name: device_has_icache + - name: device_has_icache0 + - name: device_has_keyscan + - name: device_has_lcd + - name: device_has_lcdrf + - name: device_has_ldma + - name: device_has_ldmaxbar + - name: device_has_lesense + - name: device_has_letimer + - name: device_has_letimer0 + - name: device_has_lfrco + - name: device_has_lfxo + - name: device_has_msc + - name: device_has_pcnt + - name: device_has_pcnt0 + - name: device_has_pfmxpprf + - name: device_has_prs + - name: device_has_radioaes + - name: device_has_scratchpad + - name: device_has_semailbox + - name: device_has_smu + - name: device_has_syscfg + - name: device_has_sysrtc + - name: device_has_sysrtc0 + - name: device_has_timer + - name: device_has_timer0 + - name: device_has_timer1 + - name: device_has_timer2 + - name: device_has_timer3 + - name: device_has_timer4 + - name: device_has_uart + - name: device_has_ulfrco + - name: device_has_usart + - name: device_has_usart0 + - name: device_has_vdac + - name: device_has_vdac0 + - name: device_has_wdog + - name: device_has_wdog0 + - name: device_has_wdog1 + - name: device_has_dwt + - name: device_has_emu_temp_sensor + - name: device_has_fpu + - name: device_has_mpu + - name: device_has_radio + - name: device_has_radio_subghz + - name: device_supports_rail + - name: device_supports_rail_stack + - name: device_supports_connect + - name: device_compute_basic +- recommends: + - id: trustzone_unaware +- requires: + - name: cmsis_core +- template_contribution: + - name: device_opn + value: EFR32FG23B021F512IM48 + - name: device_arch + value: armv8m.main + - name: device_cpu + value: cortexm33 + - name: device_series + value: 2 + - name: device_family + value: efr32fg23 + - name: device_flash_addr + value: 134217728 + - name: device_flash_size + value: 524288 + - name: device_flash_page_size + value: 8192 + - name: device_ram_addr + value: 536870912 + - name: device_ram_size + value: 65536 + - name: device_fpu + value: true + - name: device_mpu + value: true + - name: default_stack_size + value: 4096 + - name: default_heap_size + value: 2048 +- tag: + - device:opn:efr32fg23b021f512im48 +- toolchain_settings: + - option: device_opn + value: efr32fg23b021f512im48 + - option: architecture + value: armv8-mml + - option: cpu + value: cortex-m33 + - option: fpu + value: fpv5-sp + - option: cmse + unless: + - trustzone_nonsecure + value: enabled +- config_file: + - condition: + - custom_radio_config + directory: rail + path: platform/Device/config/210/device.yaml +- metadata: + device: + memory: + - name: Main Flash + page_size: 8192 + size: 524288 + start: 134217728 + type: non-volatile + - name: RAM + size: 65536 + start: 536870912 + type: volatile + opn: efr32fg23b021f512im48 diff --git a/platform/Device/component/efr32fg25a111f1152im56.slcc b/platform/Device/component/efr32fg25a111f1152im56.slcc index cb7a1305da..fdf0023924 100644 --- a/platform/Device/component/efr32fg25a111f1152im56.slcc +++ b/platform/Device/component/efr32fg25a111f1152im56.slcc @@ -86,7 +86,7 @@ - name: armv8m.main - name: device_security_se - name: device_dcdc_buck - - name: device_pa_14dbm + - name: device_pa_16dbm - name: device_has_acmp - name: device_has_acmp0 - name: device_has_acmp1 diff --git a/platform/Device/component/efr32fg25a121f1152im56.slcc b/platform/Device/component/efr32fg25a121f1152im56.slcc index bcd42a4bf8..585ce09411 100644 --- a/platform/Device/component/efr32fg25a121f1152im56.slcc +++ b/platform/Device/component/efr32fg25a121f1152im56.slcc @@ -86,7 +86,7 @@ - name: armv8m.main - name: device_security_se - name: device_dcdc_buck - - name: device_pa_14dbm + - name: device_pa_16dbm - name: device_has_acmp - name: device_has_acmp0 - name: device_has_acmp1 diff --git a/platform/Device/component/efr32fg25a211f1920im56.slcc b/platform/Device/component/efr32fg25a211f1920im56.slcc index a15df6af6d..6cf13717e0 100644 --- a/platform/Device/component/efr32fg25a211f1920im56.slcc +++ b/platform/Device/component/efr32fg25a211f1920im56.slcc @@ -86,7 +86,7 @@ - name: armv8m.main - name: device_security_se - name: device_dcdc_buck - - name: device_pa_14dbm + - name: device_pa_16dbm - name: device_has_acmp - name: device_has_acmp0 - name: device_has_acmp1 diff --git a/platform/Device/component/efr32fg25a221f1920im56.slcc b/platform/Device/component/efr32fg25a221f1920im56.slcc index ee82a43d6a..11fa50f816 100644 --- a/platform/Device/component/efr32fg25a221f1920im56.slcc +++ b/platform/Device/component/efr32fg25a221f1920im56.slcc @@ -86,7 +86,7 @@ - name: armv8m.main - name: device_security_se - name: device_dcdc_buck - - name: device_pa_14dbm + - name: device_pa_16dbm - name: device_has_acmp - name: device_has_acmp0 - name: device_has_acmp1 diff --git a/platform/Device/component/efr32fg25b111f1152im56.slcc b/platform/Device/component/efr32fg25b111f1152im56.slcc index 06f3ab5d4c..7dd2dc668a 100644 --- a/platform/Device/component/efr32fg25b111f1152im56.slcc +++ b/platform/Device/component/efr32fg25b111f1152im56.slcc @@ -86,7 +86,7 @@ - name: armv8m.main - name: device_security_vault - name: device_dcdc_buck - - name: device_pa_14dbm + - name: device_pa_16dbm - name: device_has_acmp - name: device_has_acmp0 - name: device_has_acmp1 diff --git a/platform/Device/component/efr32fg25b121f1152im56.slcc b/platform/Device/component/efr32fg25b121f1152im56.slcc index eebf760710..561bb37af6 100644 --- a/platform/Device/component/efr32fg25b121f1152im56.slcc +++ b/platform/Device/component/efr32fg25b121f1152im56.slcc @@ -86,7 +86,7 @@ - name: armv8m.main - name: device_security_vault - name: device_dcdc_buck - - name: device_pa_14dbm + - name: device_pa_16dbm - name: device_has_acmp - name: device_has_acmp0 - name: device_has_acmp1 diff --git a/platform/Device/component/efr32fg25b211f1920im56.slcc b/platform/Device/component/efr32fg25b211f1920im56.slcc index ca78678b8f..8f60d69057 100644 --- a/platform/Device/component/efr32fg25b211f1920im56.slcc +++ b/platform/Device/component/efr32fg25b211f1920im56.slcc @@ -86,7 +86,7 @@ - name: armv8m.main - name: device_security_vault - name: device_dcdc_buck - - name: device_pa_14dbm + - name: device_pa_16dbm - name: device_has_acmp - name: device_has_acmp0 - name: device_has_acmp1 diff --git a/platform/Device/component/efr32fg25b212f1920im56.slcc b/platform/Device/component/efr32fg25b212f1920im56.slcc index 9e837c9f09..f7077d465a 100644 --- a/platform/Device/component/efr32fg25b212f1920im56.slcc +++ b/platform/Device/component/efr32fg25b212f1920im56.slcc @@ -86,7 +86,7 @@ - name: armv8m.main - name: device_security_vault - name: device_dcdc_buck - - name: device_pa_14dbm + - name: device_pa_16dbm - name: device_has_acmp - name: device_has_acmp0 - name: device_has_acmp1 diff --git a/platform/Device/component/efr32fg25b221f1920im56.slcc b/platform/Device/component/efr32fg25b221f1920im56.slcc index 454df568f5..ad3977185a 100644 --- a/platform/Device/component/efr32fg25b221f1920im56.slcc +++ b/platform/Device/component/efr32fg25b221f1920im56.slcc @@ -86,7 +86,7 @@ - name: armv8m.main - name: device_security_vault - name: device_dcdc_buck - - name: device_pa_14dbm + - name: device_pa_16dbm - name: device_has_acmp - name: device_has_acmp0 - name: device_has_acmp1 diff --git a/platform/Device/component/efr32fg25b222f1920im56.slcc b/platform/Device/component/efr32fg25b222f1920im56.slcc index 87fdf4ed0c..6f8a1698d2 100644 --- a/platform/Device/component/efr32fg25b222f1920im56.slcc +++ b/platform/Device/component/efr32fg25b222f1920im56.slcc @@ -86,7 +86,7 @@ - name: armv8m.main - name: device_security_vault - name: device_dcdc_buck - - name: device_pa_14dbm + - name: device_pa_16dbm - name: device_has_acmp - name: device_has_acmp0 - name: device_has_acmp1 diff --git a/platform/Device/component/fgm230sa27hgn.slcc b/platform/Device/component/fgm230sa27hgn.slcc index 6617b10f38..55b4e37185 100644 --- a/platform/Device/component/fgm230sa27hgn.slcc +++ b/platform/Device/component/fgm230sa27hgn.slcc @@ -76,6 +76,7 @@ - name: device - name: device_series_2 - name: device_sdid_210 + - name: device_generic_family_efr32xg23 - name: device_family_fgm23 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/fgm230sb27hgn.slcc b/platform/Device/component/fgm230sb27hgn.slcc index ff0cca0c9d..b01d931995 100644 --- a/platform/Device/component/fgm230sb27hgn.slcc +++ b/platform/Device/component/fgm230sb27hgn.slcc @@ -76,6 +76,7 @@ - name: device - name: device_series_2 - name: device_sdid_210 + - name: device_generic_family_efr32xg23 - name: device_family_fgm23 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm111a256v2.slcc b/platform/Device/component/mgm111a256v2.slcc index d6f67d8542..12cd459eb0 100644 --- a/platform/Device/component/mgm111a256v2.slcc +++ b/platform/Device/component/mgm111a256v2.slcc @@ -69,6 +69,7 @@ - name: device - name: device_series_1 - name: device_sdid_80 + - name: device_generic_family_efr32xg11 - name: device_family_mgm1 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm111e256v2.slcc b/platform/Device/component/mgm111e256v2.slcc index cbae843afd..7d7c38fd37 100644 --- a/platform/Device/component/mgm111e256v2.slcc +++ b/platform/Device/component/mgm111e256v2.slcc @@ -69,6 +69,7 @@ - name: device - name: device_series_1 - name: device_sdid_80 + - name: device_generic_family_efr32xg11 - name: device_family_mgm1 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm12p02f1024ga.slcc b/platform/Device/component/mgm12p02f1024ga.slcc index aa7b2747d9..fd9e9482c6 100644 --- a/platform/Device/component/mgm12p02f1024ga.slcc +++ b/platform/Device/component/mgm12p02f1024ga.slcc @@ -79,6 +79,7 @@ - name: device - name: device_series_1 - name: device_sdid_84 + - name: device_generic_family_efr32xg12 - name: device_family_mgm12 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm12p02f1024ge.slcc b/platform/Device/component/mgm12p02f1024ge.slcc index eeb86039a4..bdfecada15 100644 --- a/platform/Device/component/mgm12p02f1024ge.slcc +++ b/platform/Device/component/mgm12p02f1024ge.slcc @@ -79,6 +79,7 @@ - name: device - name: device_series_1 - name: device_sdid_84 + - name: device_generic_family_efr32xg12 - name: device_family_mgm12 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm12p22f1024ga.slcc b/platform/Device/component/mgm12p22f1024ga.slcc index 5fe7356aca..86744c49a7 100644 --- a/platform/Device/component/mgm12p22f1024ga.slcc +++ b/platform/Device/component/mgm12p22f1024ga.slcc @@ -79,6 +79,7 @@ - name: device - name: device_series_1 - name: device_sdid_84 + - name: device_generic_family_efr32xg12 - name: device_family_mgm12 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm12p22f1024ge.slcc b/platform/Device/component/mgm12p22f1024ge.slcc index d2e25c0ce0..64d73867a1 100644 --- a/platform/Device/component/mgm12p22f1024ge.slcc +++ b/platform/Device/component/mgm12p22f1024ge.slcc @@ -79,6 +79,7 @@ - name: device - name: device_series_1 - name: device_sdid_84 + - name: device_generic_family_efr32xg12 - name: device_family_mgm12 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm12p32f1024ga.slcc b/platform/Device/component/mgm12p32f1024ga.slcc index 11956a6698..8ef1eec28d 100644 --- a/platform/Device/component/mgm12p32f1024ga.slcc +++ b/platform/Device/component/mgm12p32f1024ga.slcc @@ -79,6 +79,7 @@ - name: device - name: device_series_1 - name: device_sdid_84 + - name: device_generic_family_efr32xg12 - name: device_family_mgm12 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm12p32f1024ge.slcc b/platform/Device/component/mgm12p32f1024ge.slcc index d2c845910d..cb8ecedf69 100644 --- a/platform/Device/component/mgm12p32f1024ge.slcc +++ b/platform/Device/component/mgm12p32f1024ge.slcc @@ -79,6 +79,7 @@ - name: device - name: device_series_1 - name: device_sdid_84 + - name: device_generic_family_efr32xg12 - name: device_family_mgm12 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm13p02f512ga.slcc b/platform/Device/component/mgm13p02f512ga.slcc index f2d168b439..e6210fc6de 100644 --- a/platform/Device/component/mgm13p02f512ga.slcc +++ b/platform/Device/component/mgm13p02f512ga.slcc @@ -81,6 +81,7 @@ - name: device - name: device_series_1 - name: device_sdid_89 + - name: device_generic_family_efr32xg13 - name: device_family_mgm13 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm13p02f512ge.slcc b/platform/Device/component/mgm13p02f512ge.slcc index 4b8d923cca..54a21a311f 100644 --- a/platform/Device/component/mgm13p02f512ge.slcc +++ b/platform/Device/component/mgm13p02f512ge.slcc @@ -81,6 +81,7 @@ - name: device - name: device_series_1 - name: device_sdid_89 + - name: device_generic_family_efr32xg13 - name: device_family_mgm13 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm13p12f512ga.slcc b/platform/Device/component/mgm13p12f512ga.slcc index aec6f78c18..98eab55273 100644 --- a/platform/Device/component/mgm13p12f512ga.slcc +++ b/platform/Device/component/mgm13p12f512ga.slcc @@ -81,6 +81,7 @@ - name: device - name: device_series_1 - name: device_sdid_89 + - name: device_generic_family_efr32xg13 - name: device_family_mgm13 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm13p12f512ge.slcc b/platform/Device/component/mgm13p12f512ge.slcc index debbb21a0d..4a2ee9d1bb 100644 --- a/platform/Device/component/mgm13p12f512ge.slcc +++ b/platform/Device/component/mgm13p12f512ge.slcc @@ -81,6 +81,7 @@ - name: device - name: device_series_1 - name: device_sdid_89 + - name: device_generic_family_efr32xg13 - name: device_family_mgm13 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm13s02f512ga.slcc b/platform/Device/component/mgm13s02f512ga.slcc index 8d92c85dc2..0bb5cd7264 100644 --- a/platform/Device/component/mgm13s02f512ga.slcc +++ b/platform/Device/component/mgm13s02f512ga.slcc @@ -81,6 +81,7 @@ - name: device - name: device_series_1 - name: device_sdid_89 + - name: device_generic_family_efr32xg13 - name: device_family_mgm13 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm13s02f512gn.slcc b/platform/Device/component/mgm13s02f512gn.slcc index 4e5fa30f06..a9c57e7aa5 100644 --- a/platform/Device/component/mgm13s02f512gn.slcc +++ b/platform/Device/component/mgm13s02f512gn.slcc @@ -81,6 +81,7 @@ - name: device - name: device_series_1 - name: device_sdid_89 + - name: device_generic_family_efr32xg13 - name: device_family_mgm13 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm13s12f512ga.slcc b/platform/Device/component/mgm13s12f512ga.slcc index 244566b883..19cb2ff040 100644 --- a/platform/Device/component/mgm13s12f512ga.slcc +++ b/platform/Device/component/mgm13s12f512ga.slcc @@ -81,6 +81,7 @@ - name: device - name: device_series_1 - name: device_sdid_89 + - name: device_generic_family_efr32xg13 - name: device_family_mgm13 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm13s12f512gn.slcc b/platform/Device/component/mgm13s12f512gn.slcc index 280beb409d..f46a1a1be7 100644 --- a/platform/Device/component/mgm13s12f512gn.slcc +++ b/platform/Device/component/mgm13s12f512gn.slcc @@ -81,6 +81,7 @@ - name: device - name: device_series_1 - name: device_sdid_89 + - name: device_generic_family_efr32xg13 - name: device_family_mgm13 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm210l022jif.slcc b/platform/Device/component/mgm210l022jif.slcc index caff6e7baf..2ebbb47dd2 100644 --- a/platform/Device/component/mgm210l022jif.slcc +++ b/platform/Device/component/mgm210l022jif.slcc @@ -66,6 +66,7 @@ - name: device - name: device_series_2 - name: device_sdid_200 + - name: device_generic_family_efr32xg21 - name: device_family_mgm21 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm210l022jnf.slcc b/platform/Device/component/mgm210l022jnf.slcc index 22b28a4e08..5932c6479c 100644 --- a/platform/Device/component/mgm210l022jnf.slcc +++ b/platform/Device/component/mgm210l022jnf.slcc @@ -66,6 +66,7 @@ - name: device - name: device_series_2 - name: device_sdid_200 + - name: device_generic_family_efr32xg21 - name: device_family_mgm21 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm210la22jif.slcc b/platform/Device/component/mgm210la22jif.slcc index 7e8e765a7b..ea72933456 100644 --- a/platform/Device/component/mgm210la22jif.slcc +++ b/platform/Device/component/mgm210la22jif.slcc @@ -66,6 +66,7 @@ - name: device - name: device_series_2 - name: device_sdid_200 + - name: device_generic_family_efr32xg21 - name: device_family_mgm21 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm210la22jnf.slcc b/platform/Device/component/mgm210la22jnf.slcc index 393b2793c4..2b5ef8738e 100644 --- a/platform/Device/component/mgm210la22jnf.slcc +++ b/platform/Device/component/mgm210la22jnf.slcc @@ -66,6 +66,7 @@ - name: device - name: device_series_2 - name: device_sdid_200 + - name: device_generic_family_efr32xg21 - name: device_family_mgm21 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm210p022jia.slcc b/platform/Device/component/mgm210p022jia.slcc index a1322f7950..ca177d55d9 100644 --- a/platform/Device/component/mgm210p022jia.slcc +++ b/platform/Device/component/mgm210p022jia.slcc @@ -66,6 +66,7 @@ - name: device - name: device_series_2 - name: device_sdid_200 + - name: device_generic_family_efr32xg21 - name: device_family_mgm21 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm210p032jia.slcc b/platform/Device/component/mgm210p032jia.slcc index b1cfaad870..5a788ccfdf 100644 --- a/platform/Device/component/mgm210p032jia.slcc +++ b/platform/Device/component/mgm210p032jia.slcc @@ -66,6 +66,7 @@ - name: device - name: device_series_2 - name: device_sdid_200 + - name: device_generic_family_efr32xg21 - name: device_family_mgm21 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm210pa22jia.slcc b/platform/Device/component/mgm210pa22jia.slcc index 4e9a78bcd0..d428e04675 100644 --- a/platform/Device/component/mgm210pa22jia.slcc +++ b/platform/Device/component/mgm210pa22jia.slcc @@ -66,6 +66,7 @@ - name: device - name: device_series_2 - name: device_sdid_200 + - name: device_generic_family_efr32xg21 - name: device_family_mgm21 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm210pa32jia.slcc b/platform/Device/component/mgm210pa32jia.slcc index 142572aba1..ed250f8c3b 100644 --- a/platform/Device/component/mgm210pa32jia.slcc +++ b/platform/Device/component/mgm210pa32jia.slcc @@ -66,6 +66,7 @@ - name: device - name: device_series_2 - name: device_sdid_200 + - name: device_generic_family_efr32xg21 - name: device_family_mgm21 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm210pb22jia.slcc b/platform/Device/component/mgm210pb22jia.slcc index 956432e13f..7755a32cf4 100644 --- a/platform/Device/component/mgm210pb22jia.slcc +++ b/platform/Device/component/mgm210pb22jia.slcc @@ -66,6 +66,7 @@ - name: device - name: device_series_2 - name: device_sdid_200 + - name: device_generic_family_efr32xg21 - name: device_family_mgm21 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm210pb32jia.slcc b/platform/Device/component/mgm210pb32jia.slcc index 5fb73a0772..005c24ab8a 100644 --- a/platform/Device/component/mgm210pb32jia.slcc +++ b/platform/Device/component/mgm210pb32jia.slcc @@ -66,6 +66,7 @@ - name: device - name: device_series_2 - name: device_sdid_200 + - name: device_generic_family_efr32xg21 - name: device_family_mgm21 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm211la02jnf.slcc b/platform/Device/component/mgm211la02jnf.slcc index 5496376699..76cb9a01d5 100644 --- a/platform/Device/component/mgm211la02jnf.slcc +++ b/platform/Device/component/mgm211la02jnf.slcc @@ -66,6 +66,7 @@ - name: device - name: device_series_2 - name: device_sdid_200 + - name: device_generic_family_efr32xg21 - name: device_family_mgm21 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm220pc22hna.slcc b/platform/Device/component/mgm220pc22hna.slcc index 09477f6739..717883cd96 100644 --- a/platform/Device/component/mgm220pc22hna.slcc +++ b/platform/Device/component/mgm220pc22hna.slcc @@ -66,6 +66,7 @@ - name: device - name: device_series_2 - name: device_sdid_205 + - name: device_generic_family_efr32xg22 - name: device_family_mgm22 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm240l022rnf.slcc b/platform/Device/component/mgm240l022rnf.slcc index ae3f03dc3a..07e13a6044 100644 --- a/platform/Device/component/mgm240l022rnf.slcc +++ b/platform/Device/component/mgm240l022rnf.slcc @@ -73,6 +73,7 @@ - name: device - name: device_series_2 - name: device_sdid_215 + - name: device_generic_family_efr32xg24 - name: device_family_mgm24 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm240l022vnf.slcc b/platform/Device/component/mgm240l022vnf.slcc index b51753f0c3..05ad04423f 100644 --- a/platform/Device/component/mgm240l022vnf.slcc +++ b/platform/Device/component/mgm240l022vnf.slcc @@ -73,6 +73,7 @@ - name: device - name: device_series_2 - name: device_sdid_215 + - name: device_generic_family_efr32xg24 - name: device_family_mgm24 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm240pa22vna.slcc b/platform/Device/component/mgm240pa22vna.slcc index 7833af7af3..5146ae3e43 100644 --- a/platform/Device/component/mgm240pa22vna.slcc +++ b/platform/Device/component/mgm240pa22vna.slcc @@ -73,6 +73,7 @@ - name: device - name: device_series_2 - name: device_sdid_215 + - name: device_generic_family_efr32xg24 - name: device_family_mgm24 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm240pa32vna.slcc b/platform/Device/component/mgm240pa32vna.slcc index 71765a25c1..9f4646650e 100644 --- a/platform/Device/component/mgm240pa32vna.slcc +++ b/platform/Device/component/mgm240pa32vna.slcc @@ -73,6 +73,7 @@ - name: device - name: device_series_2 - name: device_sdid_215 + - name: device_generic_family_efr32xg24 - name: device_family_mgm24 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm240pa32vnn.slcc b/platform/Device/component/mgm240pa32vnn.slcc index 3c7330ad8f..5ac2465dc2 100644 --- a/platform/Device/component/mgm240pa32vnn.slcc +++ b/platform/Device/component/mgm240pa32vnn.slcc @@ -73,6 +73,7 @@ - name: device - name: device_series_2 - name: device_sdid_215 + - name: device_generic_family_efr32xg24 - name: device_family_mgm24 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm240pb22vna.slcc b/platform/Device/component/mgm240pb22vna.slcc index b3058c07c5..a20b8ef652 100644 --- a/platform/Device/component/mgm240pb22vna.slcc +++ b/platform/Device/component/mgm240pb22vna.slcc @@ -73,6 +73,7 @@ - name: device - name: device_series_2 - name: device_sdid_215 + - name: device_generic_family_efr32xg24 - name: device_family_mgm24 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm240pb32vna.slcc b/platform/Device/component/mgm240pb32vna.slcc index 46f59e094c..173091eae2 100644 --- a/platform/Device/component/mgm240pb32vna.slcc +++ b/platform/Device/component/mgm240pb32vna.slcc @@ -73,6 +73,7 @@ - name: device - name: device_series_2 - name: device_sdid_215 + - name: device_generic_family_efr32xg24 - name: device_family_mgm24 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm240pb32vnn.slcc b/platform/Device/component/mgm240pb32vnn.slcc index 9424348a4b..f4026b799b 100644 --- a/platform/Device/component/mgm240pb32vnn.slcc +++ b/platform/Device/component/mgm240pb32vnn.slcc @@ -73,6 +73,7 @@ - name: device - name: device_series_2 - name: device_sdid_215 + - name: device_generic_family_efr32xg24 - name: device_family_mgm24 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm240sa22vna.slcc b/platform/Device/component/mgm240sa22vna.slcc index 6cd3d328c7..c2d7f85f0e 100644 --- a/platform/Device/component/mgm240sa22vna.slcc +++ b/platform/Device/component/mgm240sa22vna.slcc @@ -73,6 +73,7 @@ - name: device - name: device_series_2 - name: device_sdid_215 + - name: device_generic_family_efr32xg24 - name: device_family_mgm24 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm240sb22vna.slcc b/platform/Device/component/mgm240sb22vna.slcc index 54bdb08b5f..d025d578c4 100644 --- a/platform/Device/component/mgm240sb22vna.slcc +++ b/platform/Device/component/mgm240sb22vna.slcc @@ -73,6 +73,7 @@ - name: device - name: device_series_2 - name: device_sdid_215 + - name: device_generic_family_efr32xg24 - name: device_family_mgm24 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/mgm240sd22vna.slcc b/platform/Device/component/mgm240sd22vna.slcc index 0bfd8e2862..2b77edf082 100644 --- a/platform/Device/component/mgm240sd22vna.slcc +++ b/platform/Device/component/mgm240sd22vna.slcc @@ -73,6 +73,7 @@ - name: device - name: device_series_2 - name: device_sdid_215 + - name: device_generic_family_efr32xg24 - name: device_family_mgm24 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/wgm160p022kga2.slcc b/platform/Device/component/wgm160p022kga2.slcc index 19d1e1170c..9f80acd9d0 100644 --- a/platform/Device/component/wgm160p022kga2.slcc +++ b/platform/Device/component/wgm160p022kga2.slcc @@ -93,6 +93,7 @@ - name: device - name: device_series_1 - name: device_sdid_100 + - name: device_generic_family_efr32xg11 - name: device_family_wgm160 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/wgm160p022kga3.slcc b/platform/Device/component/wgm160p022kga3.slcc index 449f7b769f..38810012f2 100644 --- a/platform/Device/component/wgm160p022kga3.slcc +++ b/platform/Device/component/wgm160p022kga3.slcc @@ -93,6 +93,7 @@ - name: device - name: device_series_1 - name: device_sdid_100 + - name: device_generic_family_efr32xg11 - name: device_family_wgm160 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/wgm160p022kgn2.slcc b/platform/Device/component/wgm160p022kgn2.slcc index 1a0d42583b..7141c94bdd 100644 --- a/platform/Device/component/wgm160p022kgn2.slcc +++ b/platform/Device/component/wgm160p022kgn2.slcc @@ -93,6 +93,7 @@ - name: device - name: device_series_1 - name: device_sdid_100 + - name: device_generic_family_efr32xg11 - name: device_family_wgm160 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/wgm160p022kgn3.slcc b/platform/Device/component/wgm160p022kgn3.slcc index c64f0fea5d..dd1ca2e66c 100644 --- a/platform/Device/component/wgm160p022kgn3.slcc +++ b/platform/Device/component/wgm160p022kgn3.slcc @@ -93,6 +93,7 @@ - name: device - name: device_series_1 - name: device_sdid_100 + - name: device_generic_family_efr32xg11 - name: device_family_wgm160 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/wgm160px22kga2.slcc b/platform/Device/component/wgm160px22kga2.slcc index 9d5307d0cb..5fe7290e44 100644 --- a/platform/Device/component/wgm160px22kga2.slcc +++ b/platform/Device/component/wgm160px22kga2.slcc @@ -93,6 +93,7 @@ - name: device - name: device_series_1 - name: device_sdid_100 + - name: device_generic_family_efr32xg11 - name: device_family_wgm160 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/wgm160px22kga3.slcc b/platform/Device/component/wgm160px22kga3.slcc index ff2b1beb6c..6cc0c1447d 100644 --- a/platform/Device/component/wgm160px22kga3.slcc +++ b/platform/Device/component/wgm160px22kga3.slcc @@ -93,6 +93,7 @@ - name: device - name: device_series_1 - name: device_sdid_100 + - name: device_generic_family_efr32xg11 - name: device_family_wgm160 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/wgm160px22kgn2.slcc b/platform/Device/component/wgm160px22kgn2.slcc index a91ccef83b..d5f1ac9d67 100644 --- a/platform/Device/component/wgm160px22kgn2.slcc +++ b/platform/Device/component/wgm160px22kgn2.slcc @@ -93,6 +93,7 @@ - name: device - name: device_series_1 - name: device_sdid_100 + - name: device_generic_family_efr32xg11 - name: device_family_wgm160 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/wgm160px22kgn3.slcc b/platform/Device/component/wgm160px22kgn3.slcc index 264a981e64..dbeaa3ceba 100644 --- a/platform/Device/component/wgm160px22kgn3.slcc +++ b/platform/Device/component/wgm160px22kgn3.slcc @@ -93,6 +93,7 @@ - name: device - name: device_series_1 - name: device_sdid_100 + - name: device_generic_family_efr32xg11 - name: device_family_wgm160 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/zgm130s037hgn.slcc b/platform/Device/component/zgm130s037hgn.slcc index f5000ce29c..8d43f57db6 100644 --- a/platform/Device/component/zgm130s037hgn.slcc +++ b/platform/Device/component/zgm130s037hgn.slcc @@ -81,6 +81,7 @@ - name: device - name: device_series_1 - name: device_sdid_89 + - name: device_generic_family_efr32xg13 - name: device_family_zgm13 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/zgm130s037hgn1.slcc b/platform/Device/component/zgm130s037hgn1.slcc index ee61c09df6..032b423958 100644 --- a/platform/Device/component/zgm130s037hgn1.slcc +++ b/platform/Device/component/zgm130s037hgn1.slcc @@ -81,6 +81,7 @@ - name: device - name: device_series_1 - name: device_sdid_89 + - name: device_generic_family_efr32xg13 - name: device_family_zgm13 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/zgm230sa27hgn.slcc b/platform/Device/component/zgm230sa27hgn.slcc index 570ad19ffd..749e09de4f 100644 --- a/platform/Device/component/zgm230sa27hgn.slcc +++ b/platform/Device/component/zgm230sa27hgn.slcc @@ -76,6 +76,7 @@ - name: device - name: device_series_2 - name: device_sdid_210 + - name: device_generic_family_efr32xg23 - name: device_family_zgm23 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/zgm230sa27hnn.slcc b/platform/Device/component/zgm230sa27hnn.slcc index 5977749d40..d147f3ebd0 100644 --- a/platform/Device/component/zgm230sa27hnn.slcc +++ b/platform/Device/component/zgm230sa27hnn.slcc @@ -76,6 +76,7 @@ - name: device - name: device_series_2 - name: device_sdid_210 + - name: device_generic_family_efr32xg23 - name: device_family_zgm23 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/zgm230sb27hgn.slcc b/platform/Device/component/zgm230sb27hgn.slcc index 661929c9ed..51bff3e45f 100644 --- a/platform/Device/component/zgm230sb27hgn.slcc +++ b/platform/Device/component/zgm230sb27hgn.slcc @@ -76,6 +76,7 @@ - name: device - name: device_series_2 - name: device_sdid_210 + - name: device_generic_family_efr32xg23 - name: device_family_zgm23 - name: device_cortexm - name: device_arm diff --git a/platform/Device/component/zgm230sb27hnn.slcc b/platform/Device/component/zgm230sb27hnn.slcc index b743caa1c8..d948cfeeb5 100644 --- a/platform/Device/component/zgm230sb27hnn.slcc +++ b/platform/Device/component/zgm230sb27hnn.slcc @@ -76,6 +76,7 @@ - name: device - name: device_series_2 - name: device_sdid_210 + - name: device_generic_family_efr32xg23 - name: device_family_zgm23 - name: device_cortexm - name: device_arm diff --git a/platform/bootloader/api/btl_interface.h b/platform/bootloader/api/btl_interface.h index b07868a553..d1ed46caf6 100644 --- a/platform/bootloader/api/btl_interface.h +++ b/platform/bootloader/api/btl_interface.h @@ -84,7 +84,9 @@ typedef struct { #define BOOTLOADER_VERSION_MINOR_MASK (0x00FF0000U) /// Bootloader interface APIs are trust zone aware -#if defined(_SILICON_LABS_32B_SERIES_2) && !defined(BOOTLOADER_APPLOADER) +#if defined(BOOTLOADER_SECURE) +#define BOOTLOADER_INTERFACE_TRUSTZONE_AWARE +#elif defined(_SILICON_LABS_32B_SERIES_2) && !defined(BOOTLOADER_APPLOADER) // The bootloader with AppLoader as the communication interface will not // re-configure the SMU since it is using the NS peripherals by default. #define BOOTLOADER_INTERFACE_TRUSTZONE_AWARE @@ -324,7 +326,11 @@ typedef struct Bootloader_inOutVec { // No bootloader area: Place the bootloader in main flash #define BTL_FIRST_STAGE_BASE FLASH_BASE #if defined(BOOTLOADER_APPLOADER) +#if defined(BOOTLOADER_SECURE) +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00014000UL) +#else #define BTL_APPLICATION_BASE (FLASH_BASE + 0x00012000UL) +#endif // BOOTLOADER_SECURE #elif defined(BOOTLOADER_SECURE) && defined(BOOTLOADER_SUPPORT_COMMUNICATION) #define BTL_APPLICATION_BASE (FLASH_BASE + 0x00006000UL) #else @@ -336,7 +342,11 @@ typedef struct Bootloader_inOutVec { // No bootloader area: Place the bootloader in main flash #define BTL_FIRST_STAGE_BASE FLASH_BASE #if defined(BOOTLOADER_APPLOADER) +#if defined(BOOTLOADER_SECURE) +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00014000UL) +#else #define BTL_APPLICATION_BASE (FLASH_BASE + 0x00012000UL) +#endif // BOOTLOADER_SECURE #else #define BTL_APPLICATION_BASE (FLASH_BASE + 0x00006000UL) #endif // BOOTLOADER_APPLOADER @@ -346,7 +356,13 @@ typedef struct Bootloader_inOutVec { // No bootloader area: Place the bootloader in main flash #define BTL_FIRST_STAGE_BASE FLASH_BASE #if defined(BOOTLOADER_APPLOADER) +#if defined(BOOTLOADER_SECURE) +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00014000UL) +#else #define BTL_APPLICATION_BASE (FLASH_BASE + 0x00012000UL) +#endif // BOOTLOADER_SECURE +#elif defined(BOOTLOADER_CUSTOM_SIZE) +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00004000UL) #else #define BTL_APPLICATION_BASE (FLASH_BASE + 0x00006000UL) #endif // BOOTLOADER_APPLOADER @@ -357,7 +373,11 @@ typedef struct Bootloader_inOutVec { // No bootloader area: Place the bootloader in main flash #define BTL_FIRST_STAGE_BASE FLASH_BASE #if defined(BOOTLOADER_APPLOADER) +#if defined(BOOTLOADER_SECURE) +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00014000UL) +#else #define BTL_APPLICATION_BASE (FLASH_BASE + 0x00012000UL) +#endif // BOOTLOADER_SECURE #else #define BTL_APPLICATION_BASE (FLASH_BASE + 0x00006000UL) #endif // BOOTLOADER_APPLOADER @@ -368,7 +388,11 @@ typedef struct Bootloader_inOutVec { // No bootloader area: Place the bootloader in main flash #define BTL_FIRST_STAGE_BASE FLASH_BASE #if defined(BOOTLOADER_APPLOADER) +#if defined(BOOTLOADER_SECURE) +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00014000UL) +#else #define BTL_APPLICATION_BASE (FLASH_BASE + 0x00012000UL) +#endif // BOOTLOADER_SECURE #else #define BTL_APPLICATION_BASE (FLASH_BASE + 0x00006000UL) #endif // BOOTLOADER_APPLOADER @@ -379,7 +403,11 @@ typedef struct Bootloader_inOutVec { // No bootloader area: Place the bootloader in main flash #define BTL_FIRST_STAGE_BASE FLASH_BASE #if defined(BOOTLOADER_APPLOADER) +#if defined(BOOTLOADER_SECURE) +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00014000UL) +#else #define BTL_APPLICATION_BASE (FLASH_BASE + 0x00012000UL) +#endif // BOOTLOADER_SECURE #else #define BTL_APPLICATION_BASE (FLASH_BASE + 0x00006000UL) #endif // BOOTLOADER_APPLOADER diff --git a/platform/bootloader/api/btl_interface_storage.h b/platform/bootloader/api/btl_interface_storage.h index a8568f7d92..df0af492b1 100644 --- a/platform/bootloader/api/btl_interface_storage.h +++ b/platform/bootloader/api/btl_interface_storage.h @@ -177,7 +177,7 @@ typedef struct BootloaderStorageFunctions { /// Current version of the BootloaderStorageInformation_t struct #define BOOTLOADER_STORAGE_INFO_VERSION (0x30000U) /// Current version of the BootloaderStorageImplementationInformation_t struct -#define BOOTLOADER_STORAGE_IMPL_INFO_VERSION (0x0201U) +#define BOOTLOADER_STORAGE_IMPL_INFO_VERSION (0x0210U) /// Major version of the BootloaderStorageImplementationInformation_t struct #define BOOTLOADER_STORAGE_IMPL_INFO_VERSION_MAJOR (0x0200U) /// Major version mask for @ref BOOTLOADER_STORAGE_IMPL_INFO_VERSION @@ -194,55 +194,55 @@ typedef struct BootloaderStorageFunctions { #define BOOTLOADER_STORAGE_IMPL_CAPABILITY_BLOCKING_ERASE (1 << 3) /// ISSI IS25LQ040B SPI Flash -#define BOOTLOADER_STORAGE_ISSI_IS25LQ040B (1 << 0) +#define BOOTLOADER_STORAGE_ISSI_IS25LQ040B (1U << 0) /// ISSI IS25LQ020B SPI Flash -#define BOOTLOADER_STORAGE_ISSI_IS25LQ020B (1 << 1) +#define BOOTLOADER_STORAGE_ISSI_IS25LQ020B (1U << 1) /// ISSI IS25LQ010B SPI Flash -#define BOOTLOADER_STORAGE_ISSI_IS25LQ010B (1 << 2) +#define BOOTLOADER_STORAGE_ISSI_IS25LQ010B (1U << 2) /// ISSI IS25LQ512B SPI Flash -#define BOOTLOADER_STORAGE_ISSI_IS25LQ512B (1 << 3) +#define BOOTLOADER_STORAGE_ISSI_IS25LQ512B (1U << 3) /// ISSI IS25LQ025B SPI Flash -#define BOOTLOADER_STORAGE_ISSI_IS25LQ025B (1 << 4) +#define BOOTLOADER_STORAGE_ISSI_IS25LQ025B (1U << 4) /// Numonyx M25P16 SPI Flash -#define BOOTLOADER_STORAGE_NUMONYX_M25P16 (1 << 5) +#define BOOTLOADER_STORAGE_NUMONYX_M25P16 (1U << 5) /// Numonyx M25P80 SPI Flash -#define BOOTLOADER_STORAGE_NUMONYX_M25P80 (1 << 6) +#define BOOTLOADER_STORAGE_NUMONYX_M25P80 (1U << 6) /// Numonyx M25P40 SPI Flash -#define BOOTLOADER_STORAGE_NUMONYX_M25P40 (1 << 7) +#define BOOTLOADER_STORAGE_NUMONYX_M25P40 (1U << 7) /// Numonyx M25P20 SPI Flash -#define BOOTLOADER_STORAGE_NUMONYX_M25P20 (1 << 8) +#define BOOTLOADER_STORAGE_NUMONYX_M25P20 (1U << 8) /// Adesto AT25SF041 SPI Flash -#define BOOTLOADER_STORAGE_ADESTO_AT25SF041 (1 << 9) +#define BOOTLOADER_STORAGE_ADESTO_AT25SF041 (1U << 9) /// Atmel AT25DF081A SPI Flash -#define BOOTLOADER_STORAGE_ATMEL_AT25DF081A (1 << 10) +#define BOOTLOADER_STORAGE_ATMEL_AT25DF081A (1U << 10) /// Atmel AT25DF041A SPI Flash -#define BOOTLOADER_STORAGE_ATMEL_AT25DF041A (1 << 11) +#define BOOTLOADER_STORAGE_ATMEL_AT25DF041A (1U << 11) /// Macronix MX25R6435F SPI Flash -#define BOOTLOADER_STORAGE_MACRONIX_MX25R6435F (1 << 12) +#define BOOTLOADER_STORAGE_MACRONIX_MX25R6435F (1U << 12) /// Macronix MX25R6435F SPI Flash -#define BOOTLOADER_STORAGE_MACRONIX_MX25R3235F (1 << 13) +#define BOOTLOADER_STORAGE_MACRONIX_MX25R3235F (1U << 13) /// Macronix MX25U1635E SPI Flash -#define BOOTLOADER_STORAGE_MACRONIX_MX25U1635E (1 << 14) +#define BOOTLOADER_STORAGE_MACRONIX_MX25U1635E (1U << 14) /// Macronix MX25L1606E SPI Flash -#define BOOTLOADER_STORAGE_MACRONIX_MX25L1606E (1 << 15) +#define BOOTLOADER_STORAGE_MACRONIX_MX25L1606E (1U << 15) /// Macronix MX25R8035F SPI Flash -#define BOOTLOADER_STORAGE_MACRONIX_MX25R8035F (1 << 16) +#define BOOTLOADER_STORAGE_MACRONIX_MX25R8035F (1U << 16) /// Macronix MX25L8006E SPI Flash -#define BOOTLOADER_STORAGE_MACRONIX_MX25L8006E (1 << 17) +#define BOOTLOADER_STORAGE_MACRONIX_MX25L8006E (1U << 17) /// Macronix MX25L4006E SPI Flash -#define BOOTLOADER_STORAGE_MACRONIX_MX25L4006E (1 << 18) +#define BOOTLOADER_STORAGE_MACRONIX_MX25L4006E (1U << 18) /// Macronix MX25L2006E SPI Flash -#define BOOTLOADER_STORAGE_MACRONIX_MX25L2006E (1 << 19) +#define BOOTLOADER_STORAGE_MACRONIX_MX25L2006E (1U << 19) /// Winbond W25Q80BV SPI Flash -#define BOOTLOADER_STORAGE_WINBOND_W25Q80BV (1 << 20) +#define BOOTLOADER_STORAGE_WINBOND_W25Q80BV (1U << 20) /// Winbond W25X20BV SPI Flash -#define BOOTLOADER_STORAGE_WINBOND_W25X20BV (1 << 21) +#define BOOTLOADER_STORAGE_WINBOND_W25X20BV (1U << 21) /// Spansion S25L208K SPI Flash -#define BOOTLOADER_STORAGE_SPANSION_S25FL208K (1 << 22) +#define BOOTLOADER_STORAGE_SPANSION_S25FL208K (1U << 22) /// Internal storage -#define BOOTLOADER_STORAGE_INTERNAL_STORAGE (1 << 30) +#define BOOTLOADER_STORAGE_INTERNAL_STORAGE (1U << 30) /// JEDEC Supported SPI Flash -#define BOOTLOADER_STORAGE_JEDEC (1 << 31) +#define BOOTLOADER_STORAGE_JEDEC (1U << 31) // ----------------------------------------------------------------------------- // Functions @@ -287,7 +287,9 @@ int32_t bootloader_readStorage(uint32_t slotId, * * @note * If DMA-based MSC write is enabled on the bootloader, writing data from - * flash to flash is not supported on Series-1 devices. + * flash to flash is not supported on Series-1 devices. DMA-based MSC write is + * enabled, both offset and buffer should be word aligned. In case the buffer + * is not aligned, the normal write procedure is used instead of DMA. * * @param[in] slotId ID of the slot * @param[in] offset Offset into the slot to start writing to diff --git a/platform/bootloader/application/config/usb-device/usbconfig.h b/platform/bootloader/application/config/usb-device/usbconfig.h deleted file mode 100644 index 4e5dabea8c..0000000000 --- a/platform/bootloader/application/config/usb-device/usbconfig.h +++ /dev/null @@ -1,51 +0,0 @@ -/***************************************************************************//** - * @file - * @brief USB protocol stack library, application supplied configuration options. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef __USBCONFIG_H -#define __USBCONFIG_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "application-configuration.h" - -#define USB_DEVICE // Compile stack for device mode. - -#define USB_CLKSRC_USHFRCO // USHFRCO as USB clock source. - -/**************************************************************************** -** ** -** Specify number of endpoints used (in addition to EP0). ** -** ** -*****************************************************************************/ -#define NUM_EP_USED 2 - -/**************************************************************************** -** ** -** USB Mass storage class device driver definitions. ** -** ** -*****************************************************************************/ -#define MSD_INTERFACE_NO (0) -#define MSD_BULK_OUT (0x01) // Endpoint for MSD data reception. -#define MSD_BULK_IN (0x81) // Endpoint for MSD data transmission. - -#ifdef __cplusplus -} -#endif - -#endif // __USBCONFIG_H diff --git a/platform/bootloader/application/config/usb-host/usbconfig.h b/platform/bootloader/application/config/usb-host/usbconfig.h deleted file mode 100644 index fcd6d1ce07..0000000000 --- a/platform/bootloader/application/config/usb-host/usbconfig.h +++ /dev/null @@ -1,54 +0,0 @@ -/***************************************************************************//** - * @file - * @brief USB protocol stack library, application supplied configuration options. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef USBCONFIG_H -#define USBCONFIG_H - -#ifdef __cplusplus -extern "C" { -#endif - -#define USB_HOST // Compile stack for host mode. - -#define USB_CLKSRC_HFRCODPLL // Use HFRCO and DPLL as USB clock - -// Use DPLL with 50 MHz HFXO as reference clock: -#define USB_DPLL_FREQUENCY 48000000UL -#define USB_DPLL_M 349U -#define USB_DPLL_N 335U -#define USB_DPLL_SRC USB_DPLL_SRC_HFXO - -/**************************************************************************** -** ** -** Specify number of host channels used (in addition to EP0). ** -** ** -*****************************************************************************/ -#define NUM_HC_USED 2 // Not counting default control ep which -// is assigned to host channels 0 and 1 - -// -// Some utility functions in the API needs printf. These -// functions have "print" in their name. This macro enables -// these functions. -// -#define USB_USE_PRINTF - -#ifdef __cplusplus -} -#endif - -#endif // USBCONFIG_H diff --git a/platform/bootloader/application/core/GCC/EFM32GG11B/efm32gg11b.ld b/platform/bootloader/application/core/GCC/EFM32GG11B/efm32gg11b.ld deleted file mode 100644 index 4f762069b9..0000000000 --- a/platform/bootloader/application/core/GCC/EFM32GG11B/efm32gg11b.ld +++ /dev/null @@ -1,229 +0,0 @@ -/***************************************************************************//** - * Linker script for Silicon Labs EFM32GG11B devices - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 2097152 - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 524288 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapBase - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - . = ALIGN (4); - PROVIDE (__ram_func_section_start = .); - *(.ram) - PROVIDE (__ram_func_section_end = .); - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY): - { - __HeapBase = .; - __end__ = .; - end = __end__; - _end = __end__; - KEEP(*(.heap*)) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - /* Check if FLASH usage exceeds FLASH size */ - ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !") -} diff --git a/platform/bootloader/application/core/GCC/EFM32GG11B/startup_efm32gg11b.c b/platform/bootloader/application/core/GCC/EFM32GG11B/startup_efm32gg11b.c deleted file mode 100644 index 6d8c554f0f..0000000000 --- a/platform/bootloader/application/core/GCC/EFM32GG11B/startup_efm32gg11b.c +++ /dev/null @@ -1,392 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CMSIS Compatible EFM32GG11B startup file in C. - * Should be used with GCC 'GNU Tools ARM Embedded' - ******************************************************************************* - * # License - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include "em_device.h" /* The correct device header file. */ - -/*---------------------------------------------------------------------------- - * Linker generated Symbols - *----------------------------------------------------------------------------*/ -extern uint32_t __etext; -extern uint32_t __data_start__; -extern uint32_t __data_end__; -extern uint32_t __copy_table_start__; -extern uint32_t __copy_table_end__; -extern uint32_t __zero_table_start__; -extern uint32_t __zero_table_end__; -extern uint32_t __bss_start__; -extern uint32_t __bss_end__; -extern uint32_t __StackTop; - -/*---------------------------------------------------------------------------- - * External References - *----------------------------------------------------------------------------*/ -#ifndef __START -extern void _start(void) __attribute__((noreturn)); /* Pre Main (C library entry point) */ -#else -extern int __START(void) __attribute__((noreturn)); /* main entry point */ -#endif - -#ifndef __NO_SYSTEM_INIT -extern void SystemInit(void); /* CMSIS System Initialization */ -#endif - -/*---------------------------------------------------------------------------- - * Internal References - *----------------------------------------------------------------------------*/ -void Default_Handler(void); /* Default empty handler */ -void Reset_Handler(void); /* Reset Handler */ - -/*---------------------------------------------------------------------------- - * User Initial Stack & Heap - *----------------------------------------------------------------------------*/ -#ifndef __STACK_SIZE -#define __STACK_SIZE 0x00001000 -#endif -static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack"))); - -#ifndef __HEAP_SIZE -#define __HEAP_SIZE 0x00001000 -#endif -#if __HEAP_SIZE > 0 -static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap"))); -#endif - -/*---------------------------------------------------------------------------- - * Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Cortex-M Processor Exceptions */ -void NMI_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void MemManage_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -/* Provide a dummy value for the sl_app_properties symbol. */ -void sl_app_properties(void); /* Prototype to please MISRA checkers. */ -void sl_app_properties(void) __attribute__ ((weak, alias("Default_Handler"))); - -/* Part Specific Interrupts */ - -void EMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void WDOG0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void LDMA_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO_EVEN_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART0_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART0_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void ACMP0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void ADC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void IDAC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void I2C0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void I2C1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO_ODD_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART1_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART1_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART2_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART2_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void UART0_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void UART0_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void LEUART0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void LEUART1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void LETIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void PCNT0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void PCNT1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void PCNT2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void RTCC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void CMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void MSC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void CRYPTO0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void CRYOTIMER_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void FPUEH_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART3_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART3_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART4_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART4_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void WTIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void WTIMER1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void WTIMER2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void WTIMER3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void I2C2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void VDAC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER4_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER5_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER6_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART5_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART5_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void CSEN_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void LESENSE_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void EBI_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void ACMP2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void ADC1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void LCD_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SDIO_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void ETH_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void CAN0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void CAN1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USB_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void RTC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void WDOG1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void LETIMER1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void TRNG0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void QSPI0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); - -/*---------------------------------------------------------------------------- - * Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const tVectorEntry __Vectors[]; -const tVectorEntry __Vectors[] __attribute__ ((section(".vectors"))) = { - /* Cortex-M Exception Handlers */ - { .topOfStack = &__StackTop }, /* Initial Stack Pointer */ - { Reset_Handler }, /* Reset Handler */ - { NMI_Handler }, /* NMI Handler */ - { HardFault_Handler }, /* Hard Fault Handler */ - { MemManage_Handler }, /* MPU Fault Handler */ - { BusFault_Handler }, /* Bus Fault Handler */ - { UsageFault_Handler }, /* Usage Fault Handler */ - { Default_Handler }, /* Reserved */ - { Default_Handler }, /* Reserved */ - { Default_Handler }, /* Reserved */ - { Default_Handler }, /* Reserved */ - { SVC_Handler }, /* SVCall Handler */ - { DebugMon_Handler }, /* Debug Monitor Handler */ - { sl_app_properties }, /* Application properties*/ - { PendSV_Handler }, /* PendSV Handler */ - { SysTick_Handler }, /* SysTick Handler */ - - /* External interrupts */ - - { EMU_IRQHandler }, /* 0 */ - { WDOG0_IRQHandler }, /* 1 */ - { LDMA_IRQHandler }, /* 2 */ - { GPIO_EVEN_IRQHandler }, /* 3 */ - { SMU_IRQHandler }, /* 4 */ - { TIMER0_IRQHandler }, /* 5 */ - { USART0_RX_IRQHandler }, /* 6 */ - { USART0_TX_IRQHandler }, /* 7 */ - { ACMP0_IRQHandler }, /* 8 */ - { ADC0_IRQHandler }, /* 9 */ - { IDAC0_IRQHandler }, /* 10 */ - { I2C0_IRQHandler }, /* 11 */ - { I2C1_IRQHandler }, /* 12 */ - { GPIO_ODD_IRQHandler }, /* 13 */ - { TIMER1_IRQHandler }, /* 14 */ - { TIMER2_IRQHandler }, /* 15 */ - { TIMER3_IRQHandler }, /* 16 */ - { USART1_RX_IRQHandler }, /* 17 */ - { USART1_TX_IRQHandler }, /* 18 */ - { USART2_RX_IRQHandler }, /* 19 */ - { USART2_TX_IRQHandler }, /* 20 */ - { UART0_RX_IRQHandler }, /* 21 */ - { UART0_TX_IRQHandler }, /* 22 */ - { UART1_RX_IRQHandler }, /* 23 */ - { UART1_TX_IRQHandler }, /* 24 */ - { LEUART0_IRQHandler }, /* 25 */ - { LEUART1_IRQHandler }, /* 26 */ - { LETIMER0_IRQHandler }, /* 27 */ - { PCNT0_IRQHandler }, /* 28 */ - { PCNT1_IRQHandler }, /* 29 */ - { PCNT2_IRQHandler }, /* 30 */ - { RTCC_IRQHandler }, /* 31 */ - { CMU_IRQHandler }, /* 32 */ - { MSC_IRQHandler }, /* 33 */ - { CRYPTO0_IRQHandler }, /* 34 */ - { CRYOTIMER_IRQHandler }, /* 35 */ - { FPUEH_IRQHandler }, /* 36 */ - { USART3_RX_IRQHandler }, /* 37 */ - { USART3_TX_IRQHandler }, /* 38 */ - { USART4_RX_IRQHandler }, /* 39 */ - { USART4_TX_IRQHandler }, /* 40 */ - { WTIMER0_IRQHandler }, /* 41 */ - { WTIMER1_IRQHandler }, /* 42 */ - { WTIMER2_IRQHandler }, /* 43 */ - { WTIMER3_IRQHandler }, /* 44 */ - { I2C2_IRQHandler }, /* 45 */ - { VDAC0_IRQHandler }, /* 46 */ - { TIMER4_IRQHandler }, /* 47 */ - { TIMER5_IRQHandler }, /* 48 */ - { TIMER6_IRQHandler }, /* 49 */ - { USART5_RX_IRQHandler }, /* 50 */ - { USART5_TX_IRQHandler }, /* 51 */ - { CSEN_IRQHandler }, /* 52 */ - { LESENSE_IRQHandler }, /* 53 */ - { EBI_IRQHandler }, /* 54 */ - { ACMP2_IRQHandler }, /* 55 */ - { ADC1_IRQHandler }, /* 56 */ - { LCD_IRQHandler }, /* 57 */ - { SDIO_IRQHandler }, /* 58 */ - { ETH_IRQHandler }, /* 59 */ - { CAN0_IRQHandler }, /* 60 */ - { CAN1_IRQHandler }, /* 61 */ - { USB_IRQHandler }, /* 62 */ - { RTC_IRQHandler }, /* 63 */ - { WDOG1_IRQHandler }, /* 64 */ - { LETIMER1_IRQHandler }, /* 65 */ - { TRNG0_IRQHandler }, /* 66 */ - { QSPI0_IRQHandler }, /* 67 */ -}; - -/*---------------------------------------------------------------------------- - * Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -void Reset_Handler(void) -{ - uint32_t *pSrc, *pDest; - uint32_t start, end; - uint32_t tableStart __attribute__((unused)); - uint32_t tableEnd __attribute__((unused)); - -#ifndef __NO_SYSTEM_INIT - SystemInit(); -#endif - -/* Firstly it copies data from read only memory to RAM. There are two schemes - * to copy. One can copy more than one sections. Another can only copy - * one section. The former scheme needs more instructions and read-only - * data to implement than the latter. - * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ - -#ifdef __STARTUP_COPY_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of triplets, each of which specify: - * offset 0: LMA of start of a section to copy from - * offset 4: VMA of start of a section to copy to - * offset 8: size of the section to copy. Must be multiply of 4 - * - * All addresses must be aligned to 4 bytes boundary. - */ - tableStart = (uint32_t) &__copy_table_start__; - tableEnd = (uint32_t) &__copy_table_end__; - - for (; tableStart < tableEnd; tableStart += 12U) { - pSrc = (uint32_t *) (*(uint32_t *) tableStart); - start = *(uint32_t *) (tableStart + 4U); - end = *(uint32_t *) (tableStart + 8U) + start; - pDest = (uint32_t *) start; - for (; start < end; start += 4U) { - *pDest++ = *pSrc++; - } - } -#else -/* Single section scheme. - * - * The ranges of copy from/to are specified by following symbols - * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to - * __data_end__: VMA of end of the section to copy to - * - * All addresses must be aligned to 4 bytes boundary. - */ - pSrc = &__etext; - pDest = &__data_start__; - start = (uint32_t) &__data_start__; - end = (uint32_t) &__data_end__; - - for (; start < end; start += 4U) { - *pDest++ = *pSrc++; - } -#endif /*__STARTUP_COPY_MULTIPLE */ - -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * There are two schemes too. One can clear multiple BSS sections. Another - * can only clear one section. The former is more size expensive than the - * latter. - * - * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. - * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. - */ -#ifdef __STARTUP_CLEAR_BSS_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __zero_table_start__ and __zero_table_end__, - * there are array of tuples specifying: - * offset 0: Start of a BSS section - * offset 4: Size of this BSS section. Must be multiply of 4 - */ - tableStart = (uint32_t) &__zero_table_start__; - tableEnd = (uint32_t) &__zero_table_end__; - - for (; tableStart < tableEnd; tableStart += 8U) { - start = *(uint32_t *) tableStart; - end = *(uint32_t *) (tableStart + 4U) + start; - pDest = (uint32_t *) start; - for (; start < end; start += 4U) { - *pDest++ = 0UL; - } - } -#elif defined (__STARTUP_CLEAR_BSS) -/* Single BSS section scheme. - * - * The BSS section is specified by following symbols - * __bss_start__: start of the BSS section. - * __bss_end__: end of the BSS section. - * - * Both addresses must be aligned to 4 bytes boundary. - */ - pDest = &__bss_start__; - start = (uint32_t) &__bss_start__; - end = (uint32_t) &__bss_end__; - - for (; start < end; start += 4U) { - *pDest++ = 0UL; - } -#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ - -#ifndef __START -#define __START _start -#endif - __START(); -} - -/*---------------------------------------------------------------------------- - * Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while (true) { - } -} diff --git a/platform/bootloader/application/core/GCC/EFM32GG12B/efm32gg12b.ld b/platform/bootloader/application/core/GCC/EFM32GG12B/efm32gg12b.ld deleted file mode 100644 index b7827855f4..0000000000 --- a/platform/bootloader/application/core/GCC/EFM32GG12B/efm32gg12b.ld +++ /dev/null @@ -1,229 +0,0 @@ -/***************************************************************************//** - * Linker script for Silicon Labs EFM32GG12B devices - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 1048576 - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 196608 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapBase - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - . = ALIGN (4); - PROVIDE (__ram_func_section_start = .); - *(.ram) - PROVIDE (__ram_func_section_end = .); - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY): - { - __HeapBase = .; - __end__ = .; - end = __end__; - _end = __end__; - KEEP(*(.heap*)) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - /* Check if FLASH usage exceeds FLASH size */ - ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !") -} diff --git a/platform/bootloader/application/core/GCC/EFM32GG12B/startup_efm32gg12b.c b/platform/bootloader/application/core/GCC/EFM32GG12B/startup_efm32gg12b.c deleted file mode 100644 index 79564f655a..0000000000 --- a/platform/bootloader/application/core/GCC/EFM32GG12B/startup_efm32gg12b.c +++ /dev/null @@ -1,376 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CMSIS Compatible EFM32GG12B startup file in C. - * Should be used with GCC 'GNU Tools ARM Embedded' - ******************************************************************************* - * # License - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. - * - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include "em_device.h" /* The correct device header file. */ - -/*---------------------------------------------------------------------------- - * Linker generated Symbols - *----------------------------------------------------------------------------*/ -extern uint32_t __etext; -extern uint32_t __data_start__; -extern uint32_t __data_end__; -extern uint32_t __copy_table_start__; -extern uint32_t __copy_table_end__; -extern uint32_t __zero_table_start__; -extern uint32_t __zero_table_end__; -extern uint32_t __bss_start__; -extern uint32_t __bss_end__; -extern uint32_t __StackTop; - -/*---------------------------------------------------------------------------- - * External References - *----------------------------------------------------------------------------*/ -#ifndef __START -extern void _start(void) __attribute__((noreturn)); /* Pre Main (C library entry point) */ -#else -extern int __START(void) __attribute__((noreturn)); /* main entry point */ -#endif - -#ifndef __NO_SYSTEM_INIT -extern void SystemInit(void); /* CMSIS System Initialization */ -#endif - -/*---------------------------------------------------------------------------- - * Internal References - *----------------------------------------------------------------------------*/ -void Default_Handler(void); /* Default empty handler */ -void Reset_Handler(void); /* Reset Handler */ - -/*---------------------------------------------------------------------------- - * User Initial Stack & Heap - *----------------------------------------------------------------------------*/ -#ifndef __STACK_SIZE -#define __STACK_SIZE 0x00001000 -#endif -static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack"))); - -#ifndef __HEAP_SIZE -#define __HEAP_SIZE 0x00001000 -#endif -#if __HEAP_SIZE > 0 -static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap"))); -#endif - -/*---------------------------------------------------------------------------- - * Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Cortex-M Processor Exceptions */ -void NMI_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void MemManage_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -/* Provide a dummy value for the sl_app_properties symbol. */ -void sl_app_properties(void); /* Prototype to please MISRA checkers. */ -void sl_app_properties(void) __attribute__ ((weak, alias("Default_Handler"))); - -/* Part Specific Interrupts */ - -void EMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void WDOG0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void LDMA_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO_EVEN_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART0_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART0_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void ACMP0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void ADC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void IDAC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void I2C0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void I2C1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO_ODD_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART1_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART1_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART2_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART2_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void UART0_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void UART0_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void LEUART0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void LEUART1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void LETIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void PCNT0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void PCNT1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void PCNT2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void RTCC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void CMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void MSC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void CRYPTO0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void CRYOTIMER_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void FPUEH_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART3_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART3_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART4_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART4_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void WTIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void WTIMER1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void VDAC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void CSEN_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void LESENSE_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void EBI_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void ACMP2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void ADC1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void LCD_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SDIO_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void CAN0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void CAN1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USB_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void RTC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void WDOG1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void LETIMER1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void TRNG0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void QSPI0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void PDM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); - -/*---------------------------------------------------------------------------- - * Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const tVectorEntry __Vectors[]; -const tVectorEntry __Vectors[] __attribute__ ((section(".vectors"))) = { - /* Cortex-M Exception Handlers */ - { .topOfStack = &__StackTop }, /* Initial Stack Pointer */ - { Reset_Handler }, /* Reset Handler */ - { NMI_Handler }, /* NMI Handler */ - { HardFault_Handler }, /* Hard Fault Handler */ - { MemManage_Handler }, /* MPU Fault Handler */ - { BusFault_Handler }, /* Bus Fault Handler */ - { UsageFault_Handler }, /* Usage Fault Handler */ - { Default_Handler }, /* Reserved */ - { Default_Handler }, /* Reserved */ - { Default_Handler }, /* Reserved */ - { Default_Handler }, /* Reserved */ - { SVC_Handler }, /* SVCall Handler */ - { DebugMon_Handler }, /* Debug Monitor Handler */ - { sl_app_properties }, /* Application properties*/ - { PendSV_Handler }, /* PendSV Handler */ - { SysTick_Handler }, /* SysTick Handler */ - - /* External interrupts */ - - { EMU_IRQHandler }, /* 0 */ - { WDOG0_IRQHandler }, /* 1 */ - { LDMA_IRQHandler }, /* 2 */ - { GPIO_EVEN_IRQHandler }, /* 3 */ - { SMU_IRQHandler }, /* 4 */ - { TIMER0_IRQHandler }, /* 5 */ - { USART0_RX_IRQHandler }, /* 6 */ - { USART0_TX_IRQHandler }, /* 7 */ - { ACMP0_IRQHandler }, /* 8 */ - { ADC0_IRQHandler }, /* 9 */ - { IDAC0_IRQHandler }, /* 10 */ - { I2C0_IRQHandler }, /* 11 */ - { I2C1_IRQHandler }, /* 12 */ - { GPIO_ODD_IRQHandler }, /* 13 */ - { TIMER1_IRQHandler }, /* 14 */ - { TIMER2_IRQHandler }, /* 15 */ - { TIMER3_IRQHandler }, /* 16 */ - { USART1_RX_IRQHandler }, /* 17 */ - { USART1_TX_IRQHandler }, /* 18 */ - { USART2_RX_IRQHandler }, /* 19 */ - { USART2_TX_IRQHandler }, /* 20 */ - { UART0_RX_IRQHandler }, /* 21 */ - { UART0_TX_IRQHandler }, /* 22 */ - { UART1_RX_IRQHandler }, /* 23 */ - { UART1_TX_IRQHandler }, /* 24 */ - { LEUART0_IRQHandler }, /* 25 */ - { LEUART1_IRQHandler }, /* 26 */ - { LETIMER0_IRQHandler }, /* 27 */ - { PCNT0_IRQHandler }, /* 28 */ - { PCNT1_IRQHandler }, /* 29 */ - { PCNT2_IRQHandler }, /* 30 */ - { RTCC_IRQHandler }, /* 31 */ - { CMU_IRQHandler }, /* 32 */ - { MSC_IRQHandler }, /* 33 */ - { CRYPTO0_IRQHandler }, /* 34 */ - { CRYOTIMER_IRQHandler }, /* 35 */ - { FPUEH_IRQHandler }, /* 36 */ - { USART3_RX_IRQHandler }, /* 37 */ - { USART3_TX_IRQHandler }, /* 38 */ - { USART4_RX_IRQHandler }, /* 39 */ - { USART4_TX_IRQHandler }, /* 40 */ - { WTIMER0_IRQHandler }, /* 41 */ - { WTIMER1_IRQHandler }, /* 42 */ - { VDAC0_IRQHandler }, /* 43 */ - { CSEN_IRQHandler }, /* 44 */ - { LESENSE_IRQHandler }, /* 45 */ - { EBI_IRQHandler }, /* 46 */ - { ACMP2_IRQHandler }, /* 47 */ - { ADC1_IRQHandler }, /* 48 */ - { LCD_IRQHandler }, /* 49 */ - { SDIO_IRQHandler }, /* 50 */ - { CAN0_IRQHandler }, /* 51 */ - { CAN1_IRQHandler }, /* 52 */ - { USB_IRQHandler }, /* 53 */ - { RTC_IRQHandler }, /* 54 */ - { WDOG1_IRQHandler }, /* 55 */ - { LETIMER1_IRQHandler }, /* 56 */ - { TRNG0_IRQHandler }, /* 57 */ - { QSPI0_IRQHandler }, /* 58 */ - { PDM_IRQHandler }, /* 59 */ -}; - -/*---------------------------------------------------------------------------- - * Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -void Reset_Handler(void) -{ - uint32_t *pSrc, *pDest; - uint32_t start, end; - uint32_t tableStart __attribute__((unused)); - uint32_t tableEnd __attribute__((unused)); - -#ifndef __NO_SYSTEM_INIT - SystemInit(); -#endif - -/* Firstly it copies data from read only memory to RAM. There are two schemes - * to copy. One can copy more than one sections. Another can only copy - * one section. The former scheme needs more instructions and read-only - * data to implement than the latter. - * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ - -#ifdef __STARTUP_COPY_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of triplets, each of which specify: - * offset 0: LMA of start of a section to copy from - * offset 4: VMA of start of a section to copy to - * offset 8: size of the section to copy. Must be multiply of 4 - * - * All addresses must be aligned to 4 bytes boundary. - */ - tableStart = (uint32_t) &__copy_table_start__; - tableEnd = (uint32_t) &__copy_table_end__; - - for (; tableStart < tableEnd; tableStart += 12U) { - pSrc = (uint32_t *) (*(uint32_t *) tableStart); - start = *(uint32_t *) (tableStart + 4U); - end = *(uint32_t *) (tableStart + 8U) + start; - pDest = (uint32_t *) start; - for (; start < end; start += 4U) { - *pDest++ = *pSrc++; - } - } -#else -/* Single section scheme. - * - * The ranges of copy from/to are specified by following symbols - * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to - * __data_end__: VMA of end of the section to copy to - * - * All addresses must be aligned to 4 bytes boundary. - */ - pSrc = &__etext; - pDest = &__data_start__; - start = (uint32_t) &__data_start__; - end = (uint32_t) &__data_end__; - - for (; start < end; start += 4U) { - *pDest++ = *pSrc++; - } -#endif /*__STARTUP_COPY_MULTIPLE */ - -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * There are two schemes too. One can clear multiple BSS sections. Another - * can only clear one section. The former is more size expensive than the - * latter. - * - * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. - * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. - */ -#ifdef __STARTUP_CLEAR_BSS_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __zero_table_start__ and __zero_table_end__, - * there are array of tuples specifying: - * offset 0: Start of a BSS section - * offset 4: Size of this BSS section. Must be multiply of 4 - */ - tableStart = (uint32_t) &__zero_table_start__; - tableEnd = (uint32_t) &__zero_table_end__; - - for (; tableStart < tableEnd; tableStart += 8U) { - start = *(uint32_t *) tableStart; - end = *(uint32_t *) (tableStart + 4U) + start; - pDest = (uint32_t *) start; - for (; start < end; start += 4U) { - *pDest++ = 0UL; - } - } -#elif defined (__STARTUP_CLEAR_BSS) -/* Single BSS section scheme. - * - * The BSS section is specified by following symbols - * __bss_start__: start of the BSS section. - * __bss_end__: end of the BSS section. - * - * Both addresses must be aligned to 4 bytes boundary. - */ - pDest = &__bss_start__; - start = (uint32_t) &__bss_start__; - end = (uint32_t) &__bss_end__; - - for (; start < end; start += 4U) { - *pDest++ = 0UL; - } -#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ - -#ifndef __START -#define __START _start -#endif - __START(); -} - -/*---------------------------------------------------------------------------- - * Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while (true) { - } -} diff --git a/platform/bootloader/application/core/IAR/EFM32GG11B/efm32gg11b.icf b/platform/bootloader/application/core/IAR/EFM32GG11B/efm32gg11b.icf deleted file mode 100644 index eb1135489d..0000000000 --- a/platform/bootloader/application/core/IAR/EFM32GG11B/efm32gg11b.icf +++ /dev/null @@ -1,40 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/* Version 5.2.1 */ - -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; - -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = (0x00000000+0x00200000-1); -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = (0x20000000+0x00080000-1); - -/*-Sizes-*/ -if ( !isdefinedsymbol( __ICFEDIT_size_cstack__ ) ) -{ define symbol __ICFEDIT_size_cstack__ = 0x1000; } - -if ( !isdefinedsymbol( __ICFEDIT_size_heap__ ) ) -{ define symbol __ICFEDIT_size_heap__ = 0x1000; } - -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -keep { section .intvec }; -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, - block HEAP }; diff --git a/platform/bootloader/application/core/IAR/EFM32GG11B/startup_efm32gg11b.c b/platform/bootloader/application/core/IAR/EFM32GG11B/startup_efm32gg11b.c deleted file mode 100644 index 355afeaa84..0000000000 --- a/platform/bootloader/application/core/IAR/EFM32GG11B/startup_efm32gg11b.c +++ /dev/null @@ -1,608 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CMSIS Compatible EFM32GG11B startup file in C for IAR EWARM - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include -#include "em_device.h" /* The correct device header file. */ - -#pragma language=extended -#pragma segment="CSTACK" - -/* IAR start function */ -extern void __iar_program_start(void); -/* CMSIS init function */ -extern void SystemInit(void); - -/* Auto defined by linker */ -extern unsigned char CSTACK$$Limit; - -__weak void Reset_Handler(void) -{ - SystemInit(); - __iar_program_start(); -} - -/* Provide a dummy value for the sl_app_properties symbol. */ -void sl_app_properties(void); /* Prototype to please MISRA checkers. */ -__weak void sl_app_properties(void) -{ -} - -__weak void NMI_Handler(void) -{ - while (true) { - } -} - -__weak void HardFault_Handler(void) -{ - while (true) { - } -} - -__weak void MemManage_Handler(void) -{ - while (true) { - } -} - -__weak void BusFault_Handler(void) -{ - while (true) { - } -} - -__weak void UsageFault_Handler(void) -{ - while (true) { - } -} - -__weak void SVC_Handler(void) -{ - while (true) { - } -} - -__weak void DebugMon_Handler(void) -{ - while (true) { - } -} - -__weak void PendSV_Handler(void) -{ - while (true) { - } -} - -__weak void SysTick_Handler(void) -{ - while (true) { - } -} - -__weak void EMU_IRQHandler(void) -{ - while (true) { - } -} - -__weak void WDOG0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void LDMA_IRQHandler(void) -{ - while (true) { - } -} - -__weak void GPIO_EVEN_IRQHandler(void) -{ - while (true) { - } -} - -__weak void SMU_IRQHandler(void) -{ - while (true) { - } -} - -__weak void TIMER0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void USART0_RX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void USART0_TX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void ACMP0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void ADC0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void IDAC0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void I2C0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void I2C1_IRQHandler(void) -{ - while (true) { - } -} - -__weak void GPIO_ODD_IRQHandler(void) -{ - while (true) { - } -} - -__weak void TIMER1_IRQHandler(void) -{ - while (true) { - } -} - -__weak void TIMER2_IRQHandler(void) -{ - while (true) { - } -} - -__weak void TIMER3_IRQHandler(void) -{ - while (true) { - } -} - -__weak void USART1_RX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void USART1_TX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void USART2_RX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void USART2_TX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void UART0_RX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void UART0_TX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void UART1_RX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void UART1_TX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void LEUART0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void LEUART1_IRQHandler(void) -{ - while (true) { - } -} - -__weak void LETIMER0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void PCNT0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void PCNT1_IRQHandler(void) -{ - while (true) { - } -} - -__weak void PCNT2_IRQHandler(void) -{ - while (true) { - } -} - -__weak void RTCC_IRQHandler(void) -{ - while (true) { - } -} - -__weak void CMU_IRQHandler(void) -{ - while (true) { - } -} - -__weak void MSC_IRQHandler(void) -{ - while (true) { - } -} - -__weak void CRYPTO0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void CRYOTIMER_IRQHandler(void) -{ - while (true) { - } -} - -__weak void FPUEH_IRQHandler(void) -{ - while (true) { - } -} - -__weak void USART3_RX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void USART3_TX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void USART4_RX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void USART4_TX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void WTIMER0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void WTIMER1_IRQHandler(void) -{ - while (true) { - } -} - -__weak void WTIMER2_IRQHandler(void) -{ - while (true) { - } -} - -__weak void WTIMER3_IRQHandler(void) -{ - while (true) { - } -} - -__weak void I2C2_IRQHandler(void) -{ - while (true) { - } -} - -__weak void VDAC0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void TIMER4_IRQHandler(void) -{ - while (true) { - } -} - -__weak void TIMER5_IRQHandler(void) -{ - while (true) { - } -} - -__weak void TIMER6_IRQHandler(void) -{ - while (true) { - } -} - -__weak void USART5_RX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void USART5_TX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void CSEN_IRQHandler(void) -{ - while (true) { - } -} - -__weak void LESENSE_IRQHandler(void) -{ - while (true) { - } -} - -__weak void EBI_IRQHandler(void) -{ - while (true) { - } -} - -__weak void ACMP2_IRQHandler(void) -{ - while (true) { - } -} - -__weak void ADC1_IRQHandler(void) -{ - while (true) { - } -} - -__weak void LCD_IRQHandler(void) -{ - while (true) { - } -} - -__weak void SDIO_IRQHandler(void) -{ - while (true) { - } -} - -__weak void ETH_IRQHandler(void) -{ - while (true) { - } -} - -__weak void CAN0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void CAN1_IRQHandler(void) -{ - while (true) { - } -} - -__weak void USB_IRQHandler(void) -{ - while (true) { - } -} - -__weak void RTC_IRQHandler(void) -{ - while (true) { - } -} - -__weak void WDOG1_IRQHandler(void) -{ - while (true) { - } -} - -__weak void LETIMER1_IRQHandler(void) -{ - while (true) { - } -} - -__weak void TRNG0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void QSPI0_IRQHandler(void) -{ - while (true) { - } -} - -#pragma data_alignment=256 -#pragma location = ".intvec" -const tVectorEntry __vector_table[] = { - { .topOfStack = &CSTACK$$Limit }, /* With IAR, the CSTACK is defined via */ - /* project options settings */ - - { Reset_Handler }, - { NMI_Handler }, - { HardFault_Handler }, - { MemManage_Handler }, - { BusFault_Handler }, - { UsageFault_Handler }, - { 0 }, - { 0 }, - { 0 }, - { 0 }, - { SVC_Handler }, - { DebugMon_Handler }, - { sl_app_properties }, - { PendSV_Handler }, - { SysTick_Handler }, - { EMU_IRQHandler }, /* 0 */ - { WDOG0_IRQHandler }, /* 1 */ - { LDMA_IRQHandler }, /* 2 */ - { GPIO_EVEN_IRQHandler }, /* 3 */ - { SMU_IRQHandler }, /* 4 */ - { TIMER0_IRQHandler }, /* 5 */ - { USART0_RX_IRQHandler }, /* 6 */ - { USART0_TX_IRQHandler }, /* 7 */ - { ACMP0_IRQHandler }, /* 8 */ - { ADC0_IRQHandler }, /* 9 */ - { IDAC0_IRQHandler }, /* 10 */ - { I2C0_IRQHandler }, /* 11 */ - { I2C1_IRQHandler }, /* 12 */ - { GPIO_ODD_IRQHandler }, /* 13 */ - { TIMER1_IRQHandler }, /* 14 */ - { TIMER2_IRQHandler }, /* 15 */ - { TIMER3_IRQHandler }, /* 16 */ - { USART1_RX_IRQHandler }, /* 17 */ - { USART1_TX_IRQHandler }, /* 18 */ - { USART2_RX_IRQHandler }, /* 19 */ - { USART2_TX_IRQHandler }, /* 20 */ - { UART0_RX_IRQHandler }, /* 21 */ - { UART0_TX_IRQHandler }, /* 22 */ - { UART1_RX_IRQHandler }, /* 23 */ - { UART1_TX_IRQHandler }, /* 24 */ - { LEUART0_IRQHandler }, /* 25 */ - { LEUART1_IRQHandler }, /* 26 */ - { LETIMER0_IRQHandler }, /* 27 */ - { PCNT0_IRQHandler }, /* 28 */ - { PCNT1_IRQHandler }, /* 29 */ - { PCNT2_IRQHandler }, /* 30 */ - { RTCC_IRQHandler }, /* 31 */ - { CMU_IRQHandler }, /* 32 */ - { MSC_IRQHandler }, /* 33 */ - { CRYPTO0_IRQHandler }, /* 34 */ - { CRYOTIMER_IRQHandler }, /* 35 */ - { FPUEH_IRQHandler }, /* 36 */ - { USART3_RX_IRQHandler }, /* 37 */ - { USART3_TX_IRQHandler }, /* 38 */ - { USART4_RX_IRQHandler }, /* 39 */ - { USART4_TX_IRQHandler }, /* 40 */ - { WTIMER0_IRQHandler }, /* 41 */ - { WTIMER1_IRQHandler }, /* 42 */ - { WTIMER2_IRQHandler }, /* 43 */ - { WTIMER3_IRQHandler }, /* 44 */ - { I2C2_IRQHandler }, /* 45 */ - { VDAC0_IRQHandler }, /* 46 */ - { TIMER4_IRQHandler }, /* 47 */ - { TIMER5_IRQHandler }, /* 48 */ - { TIMER6_IRQHandler }, /* 49 */ - { USART5_RX_IRQHandler }, /* 50 */ - { USART5_TX_IRQHandler }, /* 51 */ - { CSEN_IRQHandler }, /* 52 */ - { LESENSE_IRQHandler }, /* 53 */ - { EBI_IRQHandler }, /* 54 */ - { ACMP2_IRQHandler }, /* 55 */ - { ADC1_IRQHandler }, /* 56 */ - { LCD_IRQHandler }, /* 57 */ - { SDIO_IRQHandler }, /* 58 */ - { ETH_IRQHandler }, /* 59 */ - { CAN0_IRQHandler }, /* 60 */ - { CAN1_IRQHandler }, /* 61 */ - { USB_IRQHandler }, /* 62 */ - { RTC_IRQHandler }, /* 63 */ - { WDOG1_IRQHandler }, /* 64 */ - { LETIMER1_IRQHandler }, /* 65 */ - { TRNG0_IRQHandler }, /* 66 */ - { QSPI0_IRQHandler }, /* 67 */ -}; diff --git a/platform/bootloader/application/core/IAR/EFM32GG12B/efm32gg12b.icf b/platform/bootloader/application/core/IAR/EFM32GG12B/efm32gg12b.icf deleted file mode 100644 index 6442f779a7..0000000000 --- a/platform/bootloader/application/core/IAR/EFM32GG12B/efm32gg12b.icf +++ /dev/null @@ -1,40 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/* Version 5.2.1 */ - -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; - -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = (0x00000000+0x000800000-1); -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = (0x20000000+0x00030000-1); - -/*-Sizes-*/ -if ( !isdefinedsymbol( __ICFEDIT_size_cstack__ ) ) -{ define symbol __ICFEDIT_size_cstack__ = 0x1000; } - -if ( !isdefinedsymbol( __ICFEDIT_size_heap__ ) ) -{ define symbol __ICFEDIT_size_heap__ = 0x1000; } - -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -keep { section .intvec }; -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, - block HEAP }; diff --git a/platform/bootloader/application/core/IAR/EFM32GG12B/startup_efm32gg12b.c b/platform/bootloader/application/core/IAR/EFM32GG12B/startup_efm32gg12b.c deleted file mode 100644 index cb9f682077..0000000000 --- a/platform/bootloader/application/core/IAR/EFM32GG12B/startup_efm32gg12b.c +++ /dev/null @@ -1,552 +0,0 @@ -/***************************************************************************//** - * @file - * @brief CMSIS Compatible EFM32GG12B startup file in C for IAR EWARM - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include -#include "em_device.h" /* The correct device header file. */ - -#pragma language=extended -#pragma segment="CSTACK" - -/* IAR start function */ -extern void __iar_program_start(void); -/* CMSIS init function */ -extern void SystemInit(void); - -/* Auto defined by linker */ -extern unsigned char CSTACK$$Limit; - -__weak void Reset_Handler(void) -{ - SystemInit(); - __iar_program_start(); -} - -/* Provide a dummy value for the sl_app_properties symbol. */ -void sl_app_properties(void); /* Prototype to please MISRA checkers. */ -__weak void sl_app_properties(void) -{ -} - -__weak void NMI_Handler(void) -{ - while (true) { - } -} - -__weak void HardFault_Handler(void) -{ - while (true) { - } -} - -__weak void MemManage_Handler(void) -{ - while (true) { - } -} - -__weak void BusFault_Handler(void) -{ - while (true) { - } -} - -__weak void UsageFault_Handler(void) -{ - while (true) { - } -} - -__weak void SVC_Handler(void) -{ - while (true) { - } -} - -__weak void DebugMon_Handler(void) -{ - while (true) { - } -} - -__weak void PendSV_Handler(void) -{ - while (true) { - } -} - -__weak void SysTick_Handler(void) -{ - while (true) { - } -} - -__weak void EMU_IRQHandler(void) -{ - while (true) { - } -} - -__weak void WDOG0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void LDMA_IRQHandler(void) -{ - while (true) { - } -} - -__weak void GPIO_EVEN_IRQHandler(void) -{ - while (true) { - } -} - -__weak void SMU_IRQHandler(void) -{ - while (true) { - } -} - -__weak void TIMER0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void USART0_RX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void USART0_TX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void ACMP0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void ADC0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void IDAC0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void I2C0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void I2C1_IRQHandler(void) -{ - while (true) { - } -} - -__weak void GPIO_ODD_IRQHandler(void) -{ - while (true) { - } -} - -__weak void TIMER1_IRQHandler(void) -{ - while (true) { - } -} - -__weak void TIMER2_IRQHandler(void) -{ - while (true) { - } -} - -__weak void TIMER3_IRQHandler(void) -{ - while (true) { - } -} - -__weak void USART1_RX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void USART1_TX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void USART2_RX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void USART2_TX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void UART0_RX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void UART0_TX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void UART1_RX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void UART1_TX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void LEUART0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void LEUART1_IRQHandler(void) -{ - while (true) { - } -} - -__weak void LETIMER0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void PCNT0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void PCNT1_IRQHandler(void) -{ - while (true) { - } -} - -__weak void PCNT2_IRQHandler(void) -{ - while (true) { - } -} - -__weak void RTCC_IRQHandler(void) -{ - while (true) { - } -} - -__weak void CMU_IRQHandler(void) -{ - while (true) { - } -} - -__weak void MSC_IRQHandler(void) -{ - while (true) { - } -} - -__weak void CRYPTO0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void CRYOTIMER_IRQHandler(void) -{ - while (true) { - } -} - -__weak void FPUEH_IRQHandler(void) -{ - while (true) { - } -} - -__weak void USART3_RX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void USART3_TX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void USART4_RX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void USART4_TX_IRQHandler(void) -{ - while (true) { - } -} - -__weak void WTIMER0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void WTIMER1_IRQHandler(void) -{ - while (true) { - } -} - -__weak void VDAC0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void CSEN_IRQHandler(void) -{ - while (true) { - } -} - -__weak void LESENSE_IRQHandler(void) -{ - while (true) { - } -} - -__weak void EBI_IRQHandler(void) -{ - while (true) { - } -} - -__weak void ACMP2_IRQHandler(void) -{ - while (true) { - } -} - -__weak void ADC1_IRQHandler(void) -{ - while (true) { - } -} - -__weak void LCD_IRQHandler(void) -{ - while (true) { - } -} - -__weak void SDIO_IRQHandler(void) -{ - while (true) { - } -} - -__weak void CAN0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void CAN1_IRQHandler(void) -{ - while (true) { - } -} - -__weak void USB_IRQHandler(void) -{ - while (true) { - } -} - -__weak void RTC_IRQHandler(void) -{ - while (true) { - } -} - -__weak void WDOG1_IRQHandler(void) -{ - while (true) { - } -} - -__weak void LETIMER1_IRQHandler(void) -{ - while (true) { - } -} - -__weak void TRNG0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void QSPI0_IRQHandler(void) -{ - while (true) { - } -} - -__weak void PDM_IRQHandler(void) -{ - while (true) { - } -} - -#pragma data_alignment=256 -#pragma location = ".intvec" -const tVectorEntry __vector_table[] = { - { .topOfStack = &CSTACK$$Limit }, /* With IAR, the CSTACK is defined via */ - /* project options settings */ - - { Reset_Handler }, - { NMI_Handler }, - { HardFault_Handler }, - { MemManage_Handler }, - { BusFault_Handler }, - { UsageFault_Handler }, - { 0 }, - { 0 }, - { 0 }, - { 0 }, - { SVC_Handler }, - { DebugMon_Handler }, - { sl_app_properties }, - { PendSV_Handler }, - { SysTick_Handler }, - { EMU_IRQHandler }, /* 0 */ - { WDOG0_IRQHandler }, /* 1 */ - { LDMA_IRQHandler }, /* 2 */ - { GPIO_EVEN_IRQHandler }, /* 3 */ - { SMU_IRQHandler }, /* 4 */ - { TIMER0_IRQHandler }, /* 5 */ - { USART0_RX_IRQHandler }, /* 6 */ - { USART0_TX_IRQHandler }, /* 7 */ - { ACMP0_IRQHandler }, /* 8 */ - { ADC0_IRQHandler }, /* 9 */ - { IDAC0_IRQHandler }, /* 10 */ - { I2C0_IRQHandler }, /* 11 */ - { I2C1_IRQHandler }, /* 12 */ - { GPIO_ODD_IRQHandler }, /* 13 */ - { TIMER1_IRQHandler }, /* 14 */ - { TIMER2_IRQHandler }, /* 15 */ - { TIMER3_IRQHandler }, /* 16 */ - { USART1_RX_IRQHandler }, /* 17 */ - { USART1_TX_IRQHandler }, /* 18 */ - { USART2_RX_IRQHandler }, /* 19 */ - { USART2_TX_IRQHandler }, /* 20 */ - { UART0_RX_IRQHandler }, /* 21 */ - { UART0_TX_IRQHandler }, /* 22 */ - { UART1_RX_IRQHandler }, /* 23 */ - { UART1_TX_IRQHandler }, /* 24 */ - { LEUART0_IRQHandler }, /* 25 */ - { LEUART1_IRQHandler }, /* 26 */ - { LETIMER0_IRQHandler }, /* 27 */ - { PCNT0_IRQHandler }, /* 28 */ - { PCNT1_IRQHandler }, /* 29 */ - { PCNT2_IRQHandler }, /* 30 */ - { RTCC_IRQHandler }, /* 31 */ - { CMU_IRQHandler }, /* 32 */ - { MSC_IRQHandler }, /* 33 */ - { CRYPTO0_IRQHandler }, /* 34 */ - { CRYOTIMER_IRQHandler }, /* 35 */ - { FPUEH_IRQHandler }, /* 36 */ - { USART3_RX_IRQHandler }, /* 37 */ - { USART3_TX_IRQHandler }, /* 38 */ - { USART4_RX_IRQHandler }, /* 39 */ - { USART4_TX_IRQHandler }, /* 40 */ - { WTIMER0_IRQHandler }, /* 41 */ - { WTIMER1_IRQHandler }, /* 42 */ - { VDAC0_IRQHandler }, /* 43 */ - { CSEN_IRQHandler }, /* 44 */ - { LESENSE_IRQHandler }, /* 45 */ - { EBI_IRQHandler }, /* 46 */ - { ACMP2_IRQHandler }, /* 47 */ - { ADC1_IRQHandler }, /* 48 */ - { LCD_IRQHandler }, /* 49 */ - { SDIO_IRQHandler }, /* 50 */ - { CAN0_IRQHandler }, /* 51 */ - { CAN1_IRQHandler }, /* 52 */ - { USB_IRQHandler }, /* 53 */ - { RTC_IRQHandler }, /* 54 */ - { WDOG1_IRQHandler }, /* 55 */ - { LETIMER1_IRQHandler }, /* 56 */ - { TRNG0_IRQHandler }, /* 57 */ - { QSPI0_IRQHandler }, /* 58 */ - { PDM_IRQHandler }, /* 59 */ -}; diff --git a/platform/bootloader/application/meta-inf/appbuilder.properties b/platform/bootloader/application/meta-inf/appbuilder.properties deleted file mode 100644 index f8bdb0fcd2..0000000000 --- a/platform/bootloader/application/meta-inf/appbuilder.properties +++ /dev/null @@ -1,32 +0,0 @@ -frameworkId=application -name=Configurable Application -stackId=bootloader-sdk -prefix=EMBER_AF -versionCategory=general - -architecture=efm32~series[1] - -boards=brd2204a,brd2207a - -devtools=iar,gcc -buildFileTemplates(efm32+iar)=meta-inf/template/efx32/efx32.eww,meta-inf/template/efx32/efx32.ewd,meta-inf/template/efx32/efx32.ewp,meta-inf/template/efx32/postbuild.sh -buildFileTemplates(efm32+gcc)=meta-inf/template/efx32/postbuild.sh -metaDataFiles(efm32)=meta-inf/template/efx32/base.slsproj,meta-inf/template/efx32/addition.slsproj - -requiredSetups=additionalFiles,macros,template -requiredFeatureLevel=app_bootloader:0 - -# Plugins info file, to declare virtual plugins and load the normal ones. -pluginInfo=../plugin/plugins.info - -sampleApps=../sample-apps/apps.info - -setup.template.initFile=template.properties - -# Generator arguments -generator.sourceroot=project -generator.prependdevicename=true - -# Required feature level -requiredIsdVersion=3.2.102 -requiredFeatureLevel=app_framework:136 diff --git a/platform/bootloader/application/meta-inf/hwConfig.properties b/platform/bootloader/application/meta-inf/hwConfig.properties deleted file mode 100644 index fec1171f91..0000000000 --- a/platform/bootloader/application/meta-inf/hwConfig.properties +++ /dev/null @@ -1,27 +0,0 @@ -# This false/true property will determine whether or not the hwConfig setup is -# enabled by default. By default, it is true. -#this.defaultActive = true - -# This false/true property will determine if AppBuilder tries to overwrite the -# .hwconf file that is added to the project by AppBuilder on every generation. -# By default, it is true. -#mergeHwconfFiles = true - -# This false/true property will determine if AppBuilder tries to run part -# migration merging whenever the device is changed in AppBuilder. For some -# reason it is also used to separate the old BLE usage of Hardware Config -# from the current HAL Config usage, so it has to be true. -cloneLastHwconfFile = false - -# This false/true property will determine if AppBuilder opens up the HW -# Configurator editor on every generation. By default, it is false. -useEditor = false - -# This list will specify the framework-contributed .hwconf files to a project. -# There is an ordered list of .hwconf files that get contributed to a project. -# SDK-contributed files (see ../../hwconf.xml) -# Framework-contributed files (from this file) -# Sample app-contributed files (from sample apps) -# When AppBuilder generates, it will make a list of all of the compatible -# .hwconf files applied from the SDK, then the framework, then the sample app. - diff --git a/platform/bootloader/application/meta-inf/layout.properties b/platform/bootloader/application/meta-inf/layout.properties deleted file mode 100644 index 4ecd16463c..0000000000 --- a/platform/bootloader/application/meta-inf/layout.properties +++ /dev/null @@ -1,15 +0,0 @@ -tabs=general, plugins, other - -general.name=General -general.icon=EMBER -general.0=application -general.1=setup.information - -plugins.name=Plugins -plugins.icon=PLUGIN -plugins.0=plugins - -other.name=Other -other.icon=OTHER -other.0=setup.macros -other.1=setup.additionalFiles \ No newline at end of file diff --git a/platform/bootloader/application/meta-inf/macros.properties b/platform/bootloader/application/meta-inf/macros.properties deleted file mode 100644 index 42dcd8296d..0000000000 --- a/platform/bootloader/application/meta-inf/macros.properties +++ /dev/null @@ -1,2 +0,0 @@ -architecture(efr32,efm32) { -} diff --git a/platform/bootloader/application/meta-inf/template.properties b/platform/bootloader/application/meta-inf/template.properties deleted file mode 100644 index a3c2b8cabe..0000000000 --- a/platform/bootloader/application/meta-inf/template.properties +++ /dev/null @@ -1,3 +0,0 @@ -#Including multiple template files - -includeTemplateFiles:template_linker.properties diff --git a/platform/bootloader/application/meta-inf/template/efx32/addition.slsproj b/platform/bootloader/application/meta-inf/template/efx32/addition.slsproj deleted file mode 100644 index efdfaf5710..0000000000 --- a/platform/bootloader/application/meta-inf/template/efx32/addition.slsproj +++ /dev/null @@ -1,33 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - sh "${ProjDirPath}/$--deviceName--$_postbuild.sh" ${BuildArtifactFileBaseName} ${StudioSdkPath} - - - - - - - - - - - - diff --git a/platform/bootloader/application/meta-inf/template/efx32/base.slsproj b/platform/bootloader/application/meta-inf/template/efx32/base.slsproj deleted file mode 100644 index 35dc73d5b7..0000000000 --- a/platform/bootloader/application/meta-inf/template/efx32/base.slsproj +++ /dev/null @@ -1,152 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/platform/bootloader/application/meta-inf/template/efx32/efx32.ewd b/platform/bootloader/application/meta-inf/template/efx32/efx32.ewd deleted file mode 100644 index f70bca377b..0000000000 --- a/platform/bootloader/application/meta-inf/template/efx32/efx32.ewd +++ /dev/null @@ -1,1403 +0,0 @@ - - - - 2 - - Debug - - ARM - - 1 - - C-SPY - 2 - - 21 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARMSIM_ID - 2 - - 1 - 1 - 1 - - - - - - - - ANGEL_ID - 2 - - 0 - 1 - 1 - - - - - - - - - - - - GDBSERVER_ID - 2 - - 0 - 1 - 1 - - - - - - - - - - - IARROM_ID - 2 - - 0 - 1 - 1 - - - - - - - - - - JLINK_ID - 2 - - 10 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LMIFTDI_ID - 2 - - 2 - 1 - 1 - - - - - - - - - - MACRAIGOR_ID - 2 - - 3 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - RDI_ID - 2 - - 1 - 1 - 1 - - - - - - - - - - - - - - - - - STLINK_ID - 2 - - 1 - 1 - 1 - - - - - - - THIRDPARTY_ID - 2 - - 0 - 1 - 1 - - - - - - - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB5_Plugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin - 0 - - - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin - 1 - - - $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin - 0 - - - $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin - 1 - - - $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin - 1 - - - $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin - 1 - - - - - Release - - ARM - - 0 - - C-SPY - 2 - - 21 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARMSIM_ID - 2 - - 1 - 1 - 0 - - - - - - - - ANGEL_ID - 2 - - 0 - 1 - 0 - - - - - - - - - - - - GDBSERVER_ID - 2 - - 0 - 1 - 0 - - - - - - - - - - - IARROM_ID - 2 - - 0 - 1 - 0 - - - - - - - - - - JLINK_ID - 2 - - 10 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LMIFTDI_ID - 2 - - 2 - 1 - 0 - - - - - - - - - - MACRAIGOR_ID - 2 - - 3 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - RDI_ID - 2 - - 1 - 1 - 0 - - - - - - - - - - - - - - - - - STLINK_ID - 2 - - 1 - 1 - 0 - - - - - - - THIRDPARTY_ID - 2 - - 0 - 1 - 0 - - - - - - - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB5_Plugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin - 0 - - - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin - 1 - - - $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin - 0 - - - $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin - 1 - - - $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin - 1 - - - $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin - 1 - - - - - - diff --git a/platform/bootloader/application/meta-inf/template/efx32/efx32.ewp b/platform/bootloader/application/meta-inf/template/efx32/efx32.ewp deleted file mode 100644 index 15350e5a18..0000000000 --- a/platform/bootloader/application/meta-inf/template/efx32/efx32.ewp +++ /dev/null @@ -1,1898 +0,0 @@ - - - - 2 - - Release - - ARM - - 0 - - General - 3 - - 22 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 29 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 7 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - - Debug - - ARM - - 1 - - General - 3 - - 22 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 29 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - -$--includeLibFilesEwp--$ -$--includeFilesEwp--$ - - Device - - $PROJ_DIR$\$--frameworkDirFromProjBs--$\..\$--deviceDir--$\SiliconLabs\$--chipFamily;U--$\Source\system_$--chipFamily;L--$.c - - - diff --git a/platform/bootloader/application/meta-inf/template/efx32/efx32.eww b/platform/bootloader/application/meta-inf/template/efx32/efx32.eww deleted file mode 100644 index cb3162a656..0000000000 --- a/platform/bootloader/application/meta-inf/template/efx32/efx32.eww +++ /dev/null @@ -1,8 +0,0 @@ - - - - - $WS_DIR$\$--deviceName--$_efx32.ewp - - - diff --git a/platform/bootloader/application/meta-inf/template/efx32/postbuild.sh b/platform/bootloader/application/meta-inf/template/efx32/postbuild.sh deleted file mode 100644 index 66f50ec18e..0000000000 --- a/platform/bootloader/application/meta-inf/template/efx32/postbuild.sh +++ /dev/null @@ -1,29 +0,0 @@ -#!/bin/sh - -# This file was generated by Simplicity Studio from the following template: -# platform/bootloader/meta-inf/template/efr32/efr32-postbuild.sh -# Please do not edit it directly. - -# Post Build processing for bootloader - -# use PATH_SCMD env var to override default path for Simplicity Commander -if [ -z "${PATH_SCMD}" ]; then - COMMANDER="$--commanderPath--$" - case `uname` in CYGWIN*) COMMANDER="`cygpath ${COMMANDER}`";; esac -else - COMMANDER="${PATH_SCMD}/commander" -fi - -if [ ! -f "${COMMANDER}" ]; then - echo "Error: Simplicity Commander not found at '${COMMANDER}'" - echo "Use PATH_SCMD env var to override default path for Simplicity Commander." - exit -fi - -FILENAME=$1 - -echo " " -echo "Create gbl upgrade image" -"${COMMANDER}" gbl create "${FILENAME}.gbl" --app "${FILENAME}.s37" - - diff --git a/platform/bootloader/application/meta-inf/template_linker.properties b/platform/bootloader/application/meta-inf/template_linker.properties deleted file mode 100644 index 6d8759b299..0000000000 --- a/platform/bootloader/application/meta-inf/template_linker.properties +++ /dev/null @@ -1,18 +0,0 @@ -# This file contains default key/value customized templates. - -# -# Linker files for different devices -# - - -architecture(efm32~family[GI]~series[1]~device_configuration[1]) { - linkerIcfFile=$--stackDir--$/$--frameworkDirFromStackFs--$/core/IAR/EFM32GG11B/efm32gg11b.icf - linkerLdFile=$--stackDir--$/$--frameworkDirFromStackFs--$/core/GCC/EFM32GG11B/efm32gg11b.ld -} - -architecture(efm32~family[GI]~series[1]~device_configuration[2]) { - linkerIcfFile=$--stackDir--$/$--frameworkDirFromStackFs--$/core/IAR/EFM32GG12B/efm32gg12b.icf - linkerLdFile=$--stackDir--$/$--frameworkDirFromStackFs--$/core/GCC/EFM32GG12B/efm32gg12b.ld -} - - diff --git a/platform/bootloader/application/plugin/msd-usb-device-loader/app_usbd_main.c b/platform/bootloader/application/plugin/msd-usb-device-loader/app_usbd_main.c deleted file mode 100644 index df9176225c..0000000000 --- a/platform/bootloader/application/plugin/msd-usb-device-loader/app_usbd_main.c +++ /dev/null @@ -1,138 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Gecko Bootloader USB Mass Storage Device example. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#include -#include -#include "em_assert.h" -#include "em_chip.h" -#include "em_emu.h" -#include "em_cmu.h" -#include "em_core.h" -#include "em_gpio.h" -#include "retargetserial.h" - -#include "em_usb.h" -#include "msdd.h" -#include "msddmedia.h" -#include "gbl_fat12_disk.h" -#include "descriptors.h" - -#include "btl_interface.h" -#include "application_properties.h" - - -/// Unique ID (e.g. UUID or GUID) for the product this application is built for (uint8_t[16]) -#define APP_PROPERTIES_ID { 0 } - -const ApplicationProperties_t sl_app_properties = { - /// @brief Magic value indicating that this is an ApplicationProperties_t struct. - /// Must equal @ref APPLICATION_PROPERTIES_MAGIC - .magic = APPLICATION_PROPERTIES_MAGIC, - /// Version number of this struct - .structVersion = APPLICATION_PROPERTIES_VERSION, - /// Type of signature this application is signed with - .signatureType = APPLICATION_SIGNATURE_NONE, - /// Location of the signature. Typically a pointer to the end of the application - .signatureLocation = 0, - /// Information about the application - .app = { - /// Bitfield representing type of application, e.g. @ref APPLICATION_TYPE_BLUETOOTH_APP - .type = APPLICATION_TYPE_MCU, - /// Version number for this application - .version = APP_PROPERTIES_VERSION, - /// Capabilities of this application - .capabilities = 0, - /// Unique ID (e.g. UUID or GUID) for the product this application is built for - .productId = APP_PROPERTIES_ID, - }, -}; - - -static const USBD_Callbacks_TypeDef callbacks = -{ - .usbReset = NULL, - .usbStateChange = MSDD_StateChangeEvent, - .setupCmd = MSDD_SetupCmd, - .isSelfPowered = NULL, - .sofInt = NULL -}; - -static const USBD_Init_TypeDef usbInitStruct = -{ - .deviceDescriptor = &USBDESC_deviceDesc, - .configDescriptor = USBDESC_configDesc, - .stringDescriptors = USBDESC_strings, - .numberOfStrings = sizeof(USBDESC_strings) / sizeof(void*), - .callbacks = &callbacks, - .bufferingMultiplier = USBDESC_bufferingMultiplier, - .reserved = 0 -}; - -/***************************************************************************//** - * @brief main - the entrypoint after reset. - ******************************************************************************/ -int main(void) -{ - bool msddState; - BootloaderInformation_t info; - CMU_HFXOInit_TypeDef hfxoInit = CMU_HFXOINIT_DEFAULT; - - // Chip errata - CHIP_Init(); - - // If first word of user data page is non-zero, enable Energy Profiler trace - //BSP_TraceProfilerSetup(); - - CMU_HFXOInit(&hfxoInit); - CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO); - CMU_OscillatorEnable(cmuOsc_LFXO, true, false); - CMU_ClockEnable(cmuClock_GPIO, true); - - RETARGET_SerialInit(); - RETARGET_SerialCrLf(1); - printf("\n\n***USBD Loader Demo***\n"); - - bootloader_getInfo(&info); - if (info.type == NO_BOOTLOADER) { - printf("\nNo bootloader is present (first stage or main stage invalid)\n"); - EFM_ASSERT(false); - } - - printf("\nCurrent APP version: %" PRIu32 "\n", sl_app_properties.app.version); - printf("\nCurrent Bootloader version: %lx \n", info.version); - - // Initialize Boot Loader - if (bootloader_init() & BOOTLOADER_ERROR_INIT_BASE) { - EFM_ASSERT(false); - } - - // Initialize the Mass Storage Media. - if (!MSDDMEDIA_Init()) { - EFM_ASSERT(false); - } - - // Initialize the Mass Storage Device. - MSDD_Init(BSP_GPIO_LED0_PORT, BSP_GPIO_LED0_PIN); - - // Initialize and start USB device stack. - USBD_Init(&usbInitStruct); - - printf("\nUSBD MSD ready\n\n"); - while (1) { - msddState = MSDD_Handler(); - gblfat12disk_reProgramCheck(msddState); - } -} diff --git a/platform/bootloader/application/plugin/msd-usb-device-loader/descriptors.c b/platform/bootloader/application/plugin/msd-usb-device-loader/descriptors.c deleted file mode 100644 index 12d17412d2..0000000000 --- a/platform/bootloader/application/plugin/msd-usb-device-loader/descriptors.c +++ /dev/null @@ -1,116 +0,0 @@ -/***************************************************************************//** - * @file - * @brief USB descriptors for MSD device example project. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#include "descriptors.h" - -SL_ALIGN(4) -const USB_DeviceDescriptor_TypeDef USBDESC_deviceDesc SL_ATTRIBUTE_ALIGN(4) = -{ - .bLength = USB_DEVICE_DESCSIZE, - .bDescriptorType = USB_DEVICE_DESCRIPTOR, - .bcdUSB = 0x0200, - .bDeviceClass = 0, - .bDeviceSubClass = 0, - .bDeviceProtocol = 0, - .bMaxPacketSize0 = USB_FS_CTRL_EP_MAXSIZE, - .idVendor = 0x10C4, - .idProduct = 0x0001, - .bcdDevice = 0x0000, - .iManufacturer = 1, - .iProduct = 2, - .iSerialNumber = 3, - .bNumConfigurations = 1 -}; - -SL_ALIGN(4) -const uint8_t USBDESC_configDesc[] SL_ATTRIBUTE_ALIGN(4) = -{ - /*** Configuration descriptor ***/ - USB_CONFIG_DESCSIZE, /* bLength */ - USB_CONFIG_DESCRIPTOR, /* bDescriptorType */ - - USB_CONFIG_DESCSIZE /* wTotalLength (LSB) */ - + USB_INTERFACE_DESCSIZE - + (USB_ENDPOINT_DESCSIZE * NUM_EP_USED), - - (USB_CONFIG_DESCSIZE /* wTotalLength (MSB) */ - + USB_INTERFACE_DESCSIZE - + (USB_ENDPOINT_DESCSIZE * NUM_EP_USED)) >> 8, - - 1, /* bNumInterfaces */ - 1, /* bConfigurationValue */ - 0, /* iConfiguration */ - -#if defined(BUSPOWERED) - CONFIG_DESC_BM_RESERVED_D7, /* bmAttrib: Bus powered */ -#else - CONFIG_DESC_BM_RESERVED_D7 /* bmAttrib: Self powered */ - | CONFIG_DESC_BM_SELFPOWERED, -#endif - - CONFIG_DESC_MAXPOWER_mA(50), /* bMaxPower: 50 mA */ - - /*** Interface descriptor ***/ - USB_INTERFACE_DESCSIZE, /* bLength */ - USB_INTERFACE_DESCRIPTOR,/* bDescriptorType */ - 0, /* bInterfaceNumber */ - 0, /* bAlternateSetting */ - NUM_EP_USED, /* bNumEndpoints */ - USB_CLASS_MSD, /* bInterfaceClass */ - USB_CLASS_MSD_SCSI_CMDSET, /* bInterfaceSubClass */ - USB_CLASS_MSD_BOT_TRANSPORT,/* bInterfaceProtocol*/ - 0, /* iInterface */ - - /*** Endpoint descriptors ***/ - USB_ENDPOINT_DESCSIZE, /* bLength */ - USB_ENDPOINT_DESCRIPTOR,/* bDescriptorType */ - MSD_BULK_OUT, /* bEndpointAddress (OUT)*/ - USB_EPTYPE_BULK, /* bmAttributes */ - USB_FS_BULK_EP_MAXSIZE, /* wMaxPacketSize (LSB) */ - 0, /* wMaxPacketSize (MSB) */ - 0, /* bInterval */ - - USB_ENDPOINT_DESCSIZE, /* bLength */ - USB_ENDPOINT_DESCRIPTOR,/* bDescriptorType */ - MSD_BULK_IN, /* bEndpointAddress (IN) */ - USB_EPTYPE_BULK, /* bmAttributes */ - USB_FS_BULK_EP_MAXSIZE, /* wMaxPacketSize (LSB) */ - 0, /* wMaxPacketSize (MSB) */ - 0, /* bInterval */ -}; - -STATIC_CONST_STRING_DESC_LANGID(langID, 0x04, 0x09); -STATIC_CONST_STRING_DESC(iManufacturer, 'S', 'i', 'l', 'i', 'c', 'o', 'n', ' ', 'L', \ - 'a', 'b', 'o', 'r', 'a', 't', 'o', 'r', 'i', \ - 'e', 's', ' ', 'I', 'n', 'c', '.'); -STATIC_CONST_STRING_DESC(iProduct, 'E', 'F', 'M', '3', '2', ' ', 'U', 'S', 'B', \ - ' ', 'M', 'a', 's', 's', ' ', 'S', 't', 'o', \ - 'r', 'a', 'g', 'e', ' ', 'D', 'e', 'v', 'i', \ - 'c', 'e'); -STATIC_CONST_STRING_DESC(iSerialNumber, '0', '0', '0', '0', '1', '2', \ - '3', '4', '5', '6', '7', '8'); - -const void * const USBDESC_strings[] = -{ - &langID, - &iManufacturer, - &iProduct, - &iSerialNumber -}; - -/* Endpoint buffer sizes */ -/* 1 = single buffer, 2 = double buffering, 3 = tripple buffering ... */ -const uint8_t USBDESC_bufferingMultiplier[NUM_EP_USED + 1] = { 1, 2, 2 }; diff --git a/platform/bootloader/application/plugin/msd-usb-device-loader/descriptors.h b/platform/bootloader/application/plugin/msd-usb-device-loader/descriptors.h deleted file mode 100644 index f3b50676db..0000000000 --- a/platform/bootloader/application/plugin/msd-usb-device-loader/descriptors.h +++ /dev/null @@ -1,35 +0,0 @@ -/***************************************************************************//** - * @file - * @brief USB descriptor prototypes for MSD device example project. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef __SILICON_LABS_DESCRIPTORS_H__ -#define __SILICON_LABS_DESCRIPTORS_H__ - -#include "em_usb.h" - -#ifdef __cplusplus -extern "C" { -#endif - -extern const USB_DeviceDescriptor_TypeDef USBDESC_deviceDesc; -extern const uint8_t USBDESC_configDesc[]; -extern const void * const USBDESC_strings[4]; -extern const uint8_t USBDESC_bufferingMultiplier[]; - -#ifdef __cplusplus -} -#endif - -#endif // __SILICON_LABS_DESCRIPTORS_H__ diff --git a/platform/bootloader/application/plugin/msd-usb-device-loader/gbl_fat12_disk.c b/platform/bootloader/application/plugin/msd-usb-device-loader/gbl_fat12_disk.c deleted file mode 100644 index 1211d59524..0000000000 --- a/platform/bootloader/application/plugin/msd-usb-device-loader/gbl_fat12_disk.c +++ /dev/null @@ -1,503 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Gecko Bootloader FAT12 disk API - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#include -#include "em_usb.h" -#include "gbl_fat12_disk.h" -#include "msddmedia.h" -#include "btl_interface.h" -#include "application_properties.h" - -// ----------------------------------------------------------------------------- -// Defines -//#define MAX_FILESIZE FLASH_SIZE - -// FAT 12 header: Boot block + FAT Table + Root directory -// NB: needs to be bigger than a page size of flash -#define DISK_HEADER_SPACE 7168 - -#define DIR_ENTRY_FILESIZE_OFFS 0x1C -#define DIR_ENTRY_STARTCLUST_OFFS 0x1A - -#define BOOT_BLOCK_FATNR 1 -#define BOOT_BLOCK_FATSIZE 6 -#define DIR_ENTRY_SIZE 32 -#define BOOT_BLOCK_BLOCKSIZE 512 -#define BOOT_BLOCK_ROOTNR 112 - -#define FATINDEX_2_LBA(x) (14 + (x)) // Assuming 1 sector per cluster - -#define FILE_EXT_UPP "GBL" -#define FILE_EXT_LOW "gbl" - -extern const ApplicationProperties_t sl_app_properties; - -// ----------------------------------------------------------------------------- -// Local variables -static uint8_t fatTable[6 * 512]; // FAT 12 table size - -static uint16_t mostRecentLBA; // Most recent LBA received - -// INDEX: [7 ... 0][15 ... 8][23 ... 16]... -static uint8_t lbaReceived[MAX_FILESIZE / (BOOT_BLOCK_BLOCKSIZE * 8)]; - -static const uint8_t minimalMBR[] __attribute__ ((aligned(4))) = -{ - 0xeb, 0x3c, 0x90, 0x6d, 0x6b, 0x64, 0x6f, 0x73, - 0x66, 0x73, 0x00, 0x00, 0x02, 0x01, 0x01, 0x00, - 0x01, 0x70, 0x00, 0x00, 0x08, 0xf8, 0x06, 0x00, - 0x20, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x29, 0xe8, - 0x96, 0x3d, 0x18, 0x20, 0x20, 0x20, 0x20, 0x20, - 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x46, 0x41, - 0x54, 0x31, 0x32, 0x20, 0x20, 0x20, 0xff, 0xff -}; - -// ----------------------------------------------------------------------------- -// Local Function Prototypes -static uint8_t getLBABit(uint16_t index); -static uint32_t getEntryPtr(void); -static uint32_t getFirstEntryRootDir(void); -static uint16_t getFirstClusterNr(uint8_t *entry); -static uint32_t getFileSize(uint8_t *entry); -static void saveFATtable(void); -static uint16_t nextCluster(uint16_t cluster); -static bool fileTransferComplete(void); -static int32_t eraseStorageSlot(uint32_t slotID); -static void reProgramBLApp(void); - -// ----------------------------------------------------------------------------- -// Local function definitions - -/**************************************************************************//** - * @brief - * Get bit from a byte array at the given index - * - * @param[in] bitMap - * Byte array - *. - * @param[in] index - * Index of the bit to be read - * - * @return - * 1 if the bit is set, otherwise 0 - *****************************************************************************/ -static uint8_t getLBABit(uint16_t index) -{ - if (lbaReceived[index / 8] & (0x1 << (index % 8))) { - return 1; - } - return 0; -} - -/**************************************************************************//** - * @brief - * Find the address to the first entry with the given file extension - *. - * @return - * Address to the entry - *****************************************************************************/ -static uint32_t getEntryPtr(void) -{ - uint8_t entries[DIR_ENTRY_SIZE]; - uint8_t *entryPtr; - uint16_t nrEntries; - - entryPtr = (uint8_t*)getFirstEntryRootDir(); - - // Check if a root directory flush is pending. - // Root directory is found between lba 7 and lba 13. - if (flashStatus.pendingWrite && (mostRecentLBA >= 7 && mostRecentLBA <= 13)) { - MSDDMEDIA_Flush(); - } - - for (nrEntries = 0; nrEntries < BOOT_BLOCK_ROOTNR; nrEntries++) { - bootloader_readRawStorage((uint32_t)entryPtr, entries, DIR_ENTRY_SIZE); - - if (entries[0] != 0xE5 && entries[0] != 0x2E - && (strncmp((char *)&entries[8], FILE_EXT_UPP, 3) == 0)) { - break; - } - - // No file found. - if (nrEntries == BOOT_BLOCK_ROOTNR - 1) { - return 0; - } - - entryPtr += DIR_ENTRY_SIZE; - } - - return (uint32_t)entryPtr; -} - -/**************************************************************************//** - * @brief - * Find the address to the first entry in the root directory - * - * @return - * Address to the first entry - *****************************************************************************/ -static uint32_t getFirstEntryRootDir(void) -{ - uint8_t *entryPtr; - - entryPtr = MSDDMEDIA_getDiskStorage() \ - + BOOT_BLOCK_BLOCKSIZE * (BOOT_BLOCK_FATSIZE * BOOT_BLOCK_FATNR + 1); - return (uint32_t)entryPtr; -} - -/**************************************************************************//** - * @brief - * Get first cluster number for the given entry in the root directory - * - * @return - * Total number of clusters - *****************************************************************************/ -static uint16_t getFirstClusterNr(uint8_t *entry) -{ - uint16_t cluster; - bootloader_readRawStorage((uint32_t)&entry[DIR_ENTRY_STARTCLUST_OFFS], (uint8_t *)&cluster, 2); - - return cluster; -} - -/**************************************************************************//** - * @brief - * Get file size for the given entry in the root directory - * - * @return - * File size - *****************************************************************************/ -static uint32_t getFileSize(uint8_t *entry) -{ - uint32_t fileSize; - bootloader_readRawStorage((uint32_t)&entry[DIR_ENTRY_FILESIZE_OFFS], (uint8_t *)&fileSize, 4); - - return fileSize; -} - -/**************************************************************************//** - * @brief - * Copy the FAT12 table from the disk located in flash to a buffer in RAM - *****************************************************************************/ -static void saveFATtable(void) -{ - uint8_t *fatAddr; - - fatAddr = MSDDMEDIA_getDiskStorage() + BOOT_BLOCK_BLOCKSIZE; - - // Check if FAT flush is pending. - // Root directory is found between lba 1 and lba 6 - if (flashStatus.pendingWrite && (mostRecentLBA >= 1 && mostRecentLBA <= 6)) { - MSDDMEDIA_Flush(); - } - - bootloader_readRawStorage((uint32_t)fatAddr, fatTable, BOOT_BLOCK_FATSIZE * BOOT_BLOCK_BLOCKSIZE); -} - -/**************************************************************************//** - * @brief - * Find next cluster in cluster chain. - * - * @param[in] cluster - * Current cluster. - * - * @return - * Next cluster in cluster chain, zero if error - *****************************************************************************/ -static uint16_t nextCluster(uint16_t cluster) -{ - int i, nextCluster; - - i = (3 * cluster) / 2; - if ( cluster & 1 ) { - nextCluster = (fatTable[i] & 0xF0) >> 4; - nextCluster |= fatTable[1 + i] << 4; - } else { - nextCluster = fatTable[i]; - nextCluster |= (fatTable[1 + i] & 0xF) << 8; - } - - return (uint16_t)nextCluster; -} - -/**************************************************************************//** - * @brief - * Check if a file transfer to the disk has been completed. - * - * @return - * True if file transfer has been completed, otherwise false. - *****************************************************************************/ -static bool fileTransferComplete(void) -{ - bool endOfFile; - uint8_t *lastEntry; - uint16_t cluster; - uint32_t fileSize; - int burst; - - endOfFile = false; - - lastEntry = (uint8_t*)getEntryPtr(); - - // Check if a valid file with the given file extension has been found. - if (lastEntry != 0) { - fileSize = getFileSize(lastEntry); - cluster = getFirstClusterNr(lastEntry); - - saveFATtable(); // Update the FAT table - - // This while loop is used for traversing the cluster chain - while (fileSize) { - // Check if the data area with the given cluster number has been received. - if (!getLBABit(FATINDEX_2_LBA(cluster - 2))) { - break; - } - - burst = (BOOT_BLOCK_BLOCKSIZE <= fileSize) ? BOOT_BLOCK_BLOCKSIZE : fileSize; - fileSize -= burst; - cluster = nextCluster(cluster); - - // Check for EOF mark in the cluster chain - if ((cluster >= 0xFF8 && cluster <= 0xFFF) && fileSize == 0) { - endOfFile = true; - } - } - } - - return endOfFile; -} - -/***************************************************************************//** - * @brief - * Erase the bootloader storage slot - ******************************************************************************/ -static int32_t eraseStorageSlot(uint32_t slotID) -{ - int32_t retVal; - uint32_t eraseOffset; - BootloaderStorageInformation_t infoStorage; - bootloader_getStorageInfo(&infoStorage); - uint32_t flashPageSize = infoStorage.info->pageSize; - - BootloaderStorageSlot_t storageSlot; - retVal = bootloader_getStorageSlotInfo(slotID, &storageSlot); - if (retVal != BOOTLOADER_OK) { - return retVal; - } - uint32_t storageSpaceAddr = storageSlot.address; - uint8_t storageBuf[1]; - - while (storageSpaceAddr < (storageSlot.address + storageSlot.length)) { - bootloader_readRawStorage(storageSpaceAddr, storageBuf, 1); - if (storageBuf[0] == 0xFF) { - storageSpaceAddr += 1; - } else { - eraseOffset = (storageSpaceAddr & ~(flashPageSize - 1)); - storageSpaceAddr = eraseOffset + flashPageSize; - retVal = bootloader_eraseRawStorage(eraseOffset, flashPageSize); - if (retVal != BOOTLOADER_OK) { - return retVal; - } - } - } - return BOOTLOADER_OK; -} - -/**************************************************************************//** - * @brief - * Reprogram app. and upgrade bootloader using GBL from the storage memory. - *****************************************************************************/ -static void reProgramBLApp(void) -{ - uint8_t *rootDirBlock, *rootDirLastBlock, *pSrc, *pDest, *pFlash; - uint32_t fileSize, appVersionNewImg, imgInfoVersion; - int burst; - uint16_t cluster; - - BootloaderInformation_t info; - ApplicationData_t appinfo; - - // Write pending data to flash before starting the read operation. - if (flashStatus.pendingWrite) { - MSDDMEDIA_Flush(); - } - - rootDirBlock = (uint8_t*)getFirstEntryRootDir(); - rootDirLastBlock = rootDirBlock + (DIR_ENTRY_SIZE * BOOT_BLOCK_ROOTNR); - - rootDirBlock = (uint8_t*)getEntryPtr(); - cluster = getFirstClusterNr(rootDirBlock); - fileSize = getFileSize(rootDirBlock); - fileSize = (fileSize + 3) & ~3; // Making file size divisible of the Word length (4 bytes) - - pDest = MSDDMEDIA_getFlashBuffer(); - pFlash = MSDDMEDIA_getDiskStorage(); - - saveFATtable(); - while (fileSize) { - burst = (BOOT_BLOCK_BLOCKSIZE <= fileSize) ? BOOT_BLOCK_BLOCKSIZE : fileSize; - - // The first two cluster's are non-existent, the first cluster on the disk is cluster no. 2 - pSrc = (cluster - 2) * BOOT_BLOCK_BLOCKSIZE + rootDirLastBlock; - bootloader_readRawStorage((uint32_t)pSrc, pDest, burst); - pDest += burst; - - if (pDest == MSDDMEDIA_getFlashBuffer() + flashPageSize) { - bootloader_eraseRawStorage((uint32_t)pFlash, flashPageSize); - bootloader_writeRawStorage((uint32_t)pFlash, MSDDMEDIA_getFlashBuffer(), flashPageSize); - pDest = MSDDMEDIA_getFlashBuffer(); - pFlash += flashPageSize; - } - - fileSize -= burst; - cluster = nextCluster(cluster); - } - - if (pDest != MSDDMEDIA_getFlashBuffer()) { - bootloader_eraseRawStorage((uint32_t)pFlash, flashPageSize); - bootloader_writeRawStorage((uint32_t)pFlash, MSDDMEDIA_getFlashBuffer(), pDest - MSDDMEDIA_getFlashBuffer()); - } - - // Verify the Bootloader image - if (bootloader_verifyImage(SLOT_ID, NULL) == BOOTLOADER_OK) { - if (bootloader_setImageToBootload(SLOT_ID) == BOOTLOADER_OK) { - bootloader_getInfo(&info); - bootloader_getImageInfo(SLOT_ID, &appinfo, &imgInfoVersion); - appVersionNewImg = appinfo.version; - - if (appVersionNewImg > sl_app_properties.app.version) { - printf("\nA valid GBL with a newer application version found, rebooting\n"); - bootloader_rebootAndInstall(); - } else { - printf("\nThe GBL file contains an application upgrade image with same/older version\n"); - } - } - } else { - printf("The upgrade image is invalid\n"); - } - - // Clean the bootloader storage space - printf("Erasing the bootloader storage space...\n"); - if (eraseStorageSlot(SLOT_ID) == BOOTLOADER_OK) { - printf("Erasing the bootloader storage space completed\n"); - } - - USBTIMER_DelayMs(1000); // Wait 1s before system reset - NVIC_SystemReset(); -} - -// ----------------------------------------------------------------------------- -// Global function definitions - -/**************************************************************************//** - * @brief - * Set bit in a byte array at the given index - *. - * @param[in] index - * Index of the bit to be set - *****************************************************************************/ -void gblfat12disk_setLBABit(uint16_t index) -{ - lbaReceived[index / 8] |= 0x1 << (index % 8); -} - -/**************************************************************************//** - * @brief - * Set most recent LBA received - * - * @param[in] blockNr - * Block number - *****************************************************************************/ -void gblfat12disk_setMostRecentLBA(uint16_t blockNr) -{ - mostRecentLBA = blockNr; -} - -/**************************************************************************//** - * @brief - * Check if a file has been completely transferred and - * if there is no pending activity in the MSD, perform a reprogram - * - * @param[in] msddState - * State of Mass Storage class Device - *****************************************************************************/ -void gblfat12disk_reProgramCheck(bool msddIdle) -{ - static bool endOfFile = false; - - if (!msddIdle) { - endOfFile = fileTransferComplete(); - } - - if (endOfFile && msddIdle) { - printf("File transfer completed\n"); - endOfFile = false; - USBTIMER_DelayMs(100); // Wait 100 ms before disconnecting USB - USBD_Stop(); - printf("USB disconnected\n"); - printf("Start reprogramming the bootloader storage space\n"); - reProgramBLApp(); - } -} - -/**************************************************************************//** - * @brief - * Preparing FAT 12 image on the disk - * - * @param[in] diskStorage - * Pointer to the disk storage - * - * @param[in] flashPageBuf - * Flash page buffer storage - *****************************************************************************/ -void gblfat12disk_prepareFAT12Img(uint8_t *diskStorage, - uint32_t numBlocks, - uint8_t *flashPageBuf) -{ - // Erase the two first flash pages - uint32_t diskStorageOffset = 0UL; - while (diskStorageOffset < DISK_HEADER_SPACE) { - bootloader_eraseRawStorage((uint32_t)diskStorage + diskStorageOffset, flashPageSize); - diskStorageOffset += flashPageSize; - } - - // Prepare FAT12 image - memset(flashPageBuf, 0xFF, flashPageSize); - // Copy the first part of the boot block. - memcpy(flashPageBuf, (uint8_t*)minimalMBR, 19); - // Total number of blocks in the entire disk. - flashPageBuf[19] = numBlocks & 0x000000FF; - flashPageBuf[20] = (numBlocks & 0x0000FF00) >> 8; - // Copy the second part of the boot block. - memcpy(&flashPageBuf[21], (uint8_t*)&minimalMBR[21], sizeof(minimalMBR) - 21); - flashPageBuf[508] = 0xFF; - flashPageBuf[509] = 0xFF; - flashPageBuf[510] = 0x55; - flashPageBuf[511] = 0xAA; - // Flash the boot block table. - bootloader_writeRawStorage((uint32_t)diskStorage, flashPageBuf, BOOT_BLOCK_BLOCKSIZE); - - flashPageBuf[0] = 0xF8; - flashPageBuf[1] = 0xFF; - flashPageBuf[2] = 0xFF; - flashPageBuf[3] = 0x00; - bootloader_writeRawStorage((uint32_t)diskStorage + 0x0200, flashPageBuf, 4); - memset(flashPageBuf, 0, flashPageSize); - bootloader_writeRawStorage((uint32_t)diskStorage + 0x0204, flashPageBuf, 0x9FC); - bootloader_writeRawStorage((uint32_t)diskStorage + 0x0C00, flashPageBuf, 0x1000); -} diff --git a/platform/bootloader/application/plugin/msd-usb-device-loader/gbl_fat12_disk.h b/platform/bootloader/application/plugin/msd-usb-device-loader/gbl_fat12_disk.h deleted file mode 100644 index 9446634781..0000000000 --- a/platform/bootloader/application/plugin/msd-usb-device-loader/gbl_fat12_disk.h +++ /dev/null @@ -1,33 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Gecko Bootloader FAT12 disk API - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef FAT12FS_H -#define FAT12FS_H - -#define SLOT_ID 0 // Bootloader default storage space ID - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ -void gblfat12disk_setLBABit(uint16_t index); -void gblfat12disk_setMostRecentLBA(uint16_t blockNr); -void gblfat12disk_reProgramCheck(bool msddIdle); -void gblfat12disk_prepareFAT12Img(uint8_t *diskStorage, - uint32_t numBlocks, - uint8_t *flashPageBuf); - -#endif // FAT12FS_H diff --git a/platform/bootloader/application/plugin/msd-usb-device-loader/msddmedia.c b/platform/bootloader/application/plugin/msd-usb-device-loader/msddmedia.c deleted file mode 100644 index 103e4c1701..0000000000 --- a/platform/bootloader/application/plugin/msd-usb-device-loader/msddmedia.c +++ /dev/null @@ -1,263 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Media interface for Mass Storage class Device (MSD). - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#include -#include -#include -#include "application_properties.h" - -#include "em_usb.h" - -#include "msdd.h" -#include "msddmedia.h" - -#include "em_msc.h" -#include "em_core.h" -#include "gbl_fat12_disk.h" - -#include "btl_interface.h" - -// ----------------------------------------------------------------------------- -// Defines -#define FLASH_PAGESIZE 8192 // To ensure large enough size for all kits -#define BLOCK_SIZE 512 // Size of a sector - -// ----------------------------------------------------------------------------- -// Local variables -static uint32_t numSectors; -static uint8_t *diskStorage; -static uint8_t flashPageBuf[((FLASH_PAGESIZE) +3) & ~3]; - -// ----------------------------------------------------------------------------- -// Global variables -uint32_t flashPageSize; -flashStat flashStatus; - -// ----------------------------------------------------------------------------- -// Local function definitions - -/***************************************************************************//** - * @brief - * Erase and rewrite a flash page. - ******************************************************************************/ -static int32_t FlushFlash(void) -{ - int32_t ret; - - // Erase flash page - ret = bootloader_eraseRawStorage((uint32_t)flashStatus.pPageBase, flashPageSize); - - if (ret & BOOTLOADER_ERROR_STORAGE_BASE) { - return ret; - } - - // Program flash page - ret = bootloader_writeRawStorage((uint32_t)flashStatus.pPageBase, flashPageBuf, flashPageSize); - return ret; -} - -// ----------------------------------------------------------------------------- -// Global function definitions - -/***************************************************************************//** - * @brief - * Get pointer to the flash buffer storage - * - * @return - * Pointer to the flash buffer storage - ******************************************************************************/ -uint8_t* MSDDMEDIA_getFlashBuffer(void) -{ - return flashPageBuf; -} - -/***************************************************************************//** - * @brief - * Get pointer to the disk storage - * - * @return - * Pointer to the disk storage - ******************************************************************************/ -uint8_t* MSDDMEDIA_getDiskStorage(void) -{ - return diskStorage; -} - -/***************************************************************************//** - * @brief - * Check if a media access is legal, prepare for later data transmissions. - * - * @param[in] pCmd - * Points to a MSDD_CmdStatus_TypeDef structure which holds info about the - * current transfer. - * - * @param[in] lba - * Media "Logical Block Address". - * - * @param[in] sectors - * Number of 512 byte sectors to transfer. - * - * @return - * True if legal access, false otherwise. - ******************************************************************************/ -bool MSDDMEDIA_CheckAccess(MSDD_CmdStatus_TypeDef *pCmd, - uint32_t lba, uint32_t sectors) -{ - if ((lba + sectors) > numSectors) { - return false; - } - - pCmd->lba = lba; - pCmd->pData = &diskStorage[lba * BLOCK_SIZE]; - if (pCmd->direction && !flashStatus.pendingWrite) { - pCmd->xferType = XFER_MEMORYMAPPED; - } else { - pCmd->xferType = XFER_INDIRECT; - pCmd->maxBurst = MEDIA_BUFSIZ; - } - - pCmd->xferLen = sectors * BLOCK_SIZE; - - return true; -} - -/***************************************************************************//** - * @brief - * Flush pending media writes. - ******************************************************************************/ -void MSDDMEDIA_Flush(void) -{ - if (flashStatus.pendingWrite) { - flashStatus.pendingWrite = false; - FlushFlash(); - } -} - -/***************************************************************************//** - * @brief - * Get number of 512 byte sectors on the media. - * - * @return - * Number of sectors on media. - ******************************************************************************/ -uint32_t MSDDMEDIA_GetSectorCount(void) -{ - return numSectors; -} - -/***************************************************************************//** - * @brief - * Initialize the storage media interface and prepare FAT12 image - ******************************************************************************/ -bool MSDDMEDIA_Init(void) -{ - BootloaderStorageInformation_t infoStorage; - BootloaderStorageSlot_t storageSlot; - bootloader_getStorageInfo(&infoStorage); - if (bootloader_getStorageSlotInfo(SLOT_ID, &storageSlot) & BOOTLOADER_ERROR_STORAGE_BASE) { - EFM_ASSERT(false); - } - - flashPageSize = infoStorage.info->pageSize; - diskStorage = (uint8_t*)storageSlot.address; - numSectors = storageSlot.length / BLOCK_SIZE; - flashStatus.pendingWrite = false; - gblfat12disk_setMostRecentLBA(0); - - MSC_Init(); - gblfat12disk_prepareFAT12Img(diskStorage, numSectors, flashPageBuf); - return true; -} - -/***************************************************************************//** - * @brief - * Read from indirectly accessed media. - * - * @param[in] pCmd - * Points to a MSDD_CmdStatus_TypeDef structure which holds info about the - * current transfer. - * - * @param[in] data - * Pointer to data buffer. - * - * @param[in] sectors - * Number of 512 byte sectors to read from media. - ******************************************************************************/ -void MSDDMEDIA_Read(MSDD_CmdStatus_TypeDef *pCmd, uint8_t *data, uint32_t sectors) -{ - // Write pending data to flash before starting the read operation. - MSDDMEDIA_Flush(); - bootloader_readRawStorage((uint32_t)pCmd->pData, data, sectors * BLOCK_SIZE); - pCmd->pData += sectors * BLOCK_SIZE; -} - -/***************************************************************************//** - * @brief - * Write to indirectly accessed media. - * - * @param[in] pCmd - * Points to a MSDD_CmdStatus_TypeDef structure which holds info about the - * current transfer. - * - * @param[in] data - * Pointer to data buffer. - * - * @param[in] sectors - * Number of 512 byte sectors to write to media. - ******************************************************************************/ -void MSDDMEDIA_Write(MSDD_CmdStatus_TypeDef *pCmd, uint8_t *data, uint32_t sectors) -{ - unsigned int i; - uint32_t offset; - - i = 0; - while (i < sectors) { - gblfat12disk_setMostRecentLBA(pCmd->lba + i); - - // Marking the reception of the data blocks for later checking - gblfat12disk_setLBABit(pCmd->lba + i); - - if (!flashStatus.pendingWrite) { - // Copy an entire flash page to the page buffer - flashStatus.pendingWrite = true; - flashStatus.pPageBase = (uint8_t*)((uint32_t)pCmd->pData & ~(flashPageSize - 1)); - offset = pCmd->pData - flashStatus.pPageBase; - bootloader_readRawStorage((uint32_t)flashStatus.pPageBase, flashPageBuf, flashPageSize); - - // Write the received data in the page buffer - memcpy(flashPageBuf + offset, data, BLOCK_SIZE); - data += BLOCK_SIZE; - pCmd->pData += BLOCK_SIZE; - } else { - // Check if current sector is located in the page buffer. - offset = pCmd->pData - flashStatus.pPageBase; - if (offset >= flashPageSize) { - /* - * Current sector not located in page buffer, flush pending data - * before continuing. - */ - MSDDMEDIA_Flush(); - i--; - } else { - // Write the received data in the page buffer - memcpy(flashPageBuf + offset, data, BLOCK_SIZE); - data += BLOCK_SIZE; - pCmd->pData += BLOCK_SIZE; - } - } - i++; - } -} diff --git a/platform/bootloader/application/plugin/msd-usb-device-loader/msddmedia.h b/platform/bootloader/application/plugin/msd-usb-device-loader/msddmedia.h deleted file mode 100644 index 7d802a000f..0000000000 --- a/platform/bootloader/application/plugin/msd-usb-device-loader/msddmedia.h +++ /dev/null @@ -1,45 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Media interface for Mass Storage class Device (MSD). - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef MSDDMEDIA_H -#define MSDDMEDIA_H - -#include "msdd.h" - -extern uint32_t flashPageSize; - -typedef struct flashStat { - uint8_t *pPageBase; - bool pendingWrite; -} flashStat; - -extern flashStat flashStatus; - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ -bool MSDDMEDIA_CheckAccess(MSDD_CmdStatus_TypeDef *pCmd, uint32_t lba, uint32_t sectors); -void MSDDMEDIA_Flush(void); -uint32_t MSDDMEDIA_GetSectorCount(void); -bool MSDDMEDIA_Init(void); -void MSDDMEDIA_Read(MSDD_CmdStatus_TypeDef *pCmd, uint8_t *data, uint32_t sectors); -void MSDDMEDIA_Write(MSDD_CmdStatus_TypeDef *pCmd, uint8_t *data, uint32_t sectors); - -uint8_t* MSDDMEDIA_getFlashBuffer(void); -uint8_t* MSDDMEDIA_getDiskStorage(void); - -#endif // MSDDMEDIA_H diff --git a/platform/bootloader/application/plugin/msd-usb-device-loader/plugin.properties b/platform/bootloader/application/plugin/msd-usb-device-loader/plugin.properties deleted file mode 100644 index 3c5b805379..0000000000 --- a/platform/bootloader/application/plugin/msd-usb-device-loader/plugin.properties +++ /dev/null @@ -1,35 +0,0 @@ -name=USB Device Loader -category=Application -architecture=efm32~series[1] -description=USB device loader - -# Files that are released in source - -# Common files -sourceFiles=msddmedia.c, descriptors.c, gbl_fat12_disk.c, app_usbd_main.c - -setup(additionalFiles) { - PATH(ABSOLUTE):$BOOTLOADER/application/plugin/msd-usb-device-loader - PATH(ABSOLUTE):$BOOTLOADER/api/ - PATH(ABSOLUTE):$BOOTLOADER/config/ -} - -setup(macros) { - -DRETARGET_VCOM - -DAPP_PROPERTIES_VERSION=1 - -DSL_SUPRESS_GECKO_USB_DEPRECATION_WARNINGS=1 -} - -options = max_Filesize, busPowered - -max_Filesize.name = Max Filesize -max_Filesize.description = Define max filesize. Must be a multiple of 4. -max_Filesize.type = NUMBER -max_Filesize.default = 458752 -max_Filesize.define = MAX_FILESIZE - -busPowered.name = Build buspowered device -busPowered.description = Set true if the device is buspowered. -busPowered.type = BOOLEAN -busPowered.default = false -busPowered.define = BUSPOWERED diff --git a/platform/bootloader/application/plugin/msd-usb-host-loader/app_usbh_main.c b/platform/bootloader/application/plugin/msd-usb-host-loader/app_usbh_main.c deleted file mode 100644 index 845be62a94..0000000000 --- a/platform/bootloader/application/plugin/msd-usb-host-loader/app_usbh_main.c +++ /dev/null @@ -1,412 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Gecko Bootloader USB host MSD loader example. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#include -#include -#include - -#include "em_device.h" -#include "em_chip.h" -#include "em_cmu.h" -#include "em_core.h" -#include "bsp.h" -#include "bsp_trace.h" -#include "retargetserial.h" -#include "em_usb.h" -#include "msdh.h" -#include "ff.h" -#include "btl_interface.h" - -// ----------------------------------------------------------------------------- -// Defines -#define USBBUFSIZE 1024 -#define FLASH_PAGESIZE FLASH_PAGE_SIZE - -#define FILE_EXT_UPP "GBL" -#define FILE_EXT_LOW "gbl" - -#define SLOT_ID 0 // Bootloader default storage space ID -#define PATH_LENGTH 260 - -// ----------------------------------------------------------------------------- -// Local Global Variables - -// Bootloader storage space address -static uint8_t *diskStorage; - -// File system -static FATFS Fatfs; -static FIL fh; - -// USB related data -STATIC_UBUF(tmpBuf, USBBUFSIZE); - -// Read data buffer -static char flashPageBuf[((FLASH_PAGESIZE) +3) & ~3]; -static UINT bufRead; - -/* - * The path array length is important when running checkValidGbl(path). - * checkValidGbl is recursive and will traverse the directory tree. - * The length of "path" need to be equal the maximum "path + filename" - * length existing on the disk. - * Max path length on MSDOS FAT12/16 is 260, on FAT32 there is no limit. - * The files with path name longer than 260 will not be found. - * Keep in mind that the FatFs library uses 8.3 name notation. - * - * When using checkValidGbl on large directory trees the default stacksize - * might be too small due to checkValidGbl recursive operation. - */ -static char path[PATH_LENGTH]; -static BootloaderInformation_t info; - -//extern const ApplicationProperties_t sl_app_properties; - -/// Unique ID (e.g. UUID or GUID) for the product this application is built for (uint8_t[16]) -#define APP_PROPERTIES_ID { 0 } - -const ApplicationProperties_t sl_app_properties = { - /// @brief Magic value indicating that this is an ApplicationProperties_t struct. - /// Must equal @ref APPLICATION_PROPERTIES_MAGIC - .magic = APPLICATION_PROPERTIES_MAGIC, - /// Version number of this struct - .structVersion = APPLICATION_PROPERTIES_VERSION, - /// Type of signature this application is signed with - .signatureType = APPLICATION_SIGNATURE_NONE, - /// Location of the signature. Typically a pointer to the end of the application - .signatureLocation = 0, - /// Information about the application - .app = { - /// Bitfield representing type of application, e.g. @ref APPLICATION_TYPE_BLUETOOTH_APP - .type = APPLICATION_TYPE_MCU, - /// Version number for this application - .version = APP_PROPERTIES_VERSION, - /// Capabilities of this application - .capabilities = 0, - /// Unique ID (e.g. UUID or GUID) for the product this application is built for - .productId = APP_PROPERTIES_ID, - }, -}; - - - -// ----------------------------------------------------------------------------- -// Local Function Prototypes -static int32_t flushFlash(uint32_t addr); -static bool reprogramGBLStorage(char* path, char* fileName); -static bool checkValidGbl(char* path); -static void reProgramBLApp(void); -static int32_t eraseStorageSlot(uint32_t slotID); - -/***************************************************************************//** - * @brief - * This function is required by the FAT file system in order to provide - * timestamps for created files. Since we do not have a reliable clock we - * hardcode a value here. - * - * Refer to reptile/fatfs/doc/en/fattime.html for the format of this DWORD. - * - * @return - * A DWORD containing the current time and date as a packed datastructure. - ******************************************************************************/ -DWORD get_fattime(void) -{ - return (28 << 25) | (2 << 21) | (1 << 16); -} - -/***************************************************************************//** - * @brief - * Erase and rewrite a flash page. - * - * @param[in] addr - * Address of the flash memory to be rewritten - * - * @return - * Bootloader error code - ******************************************************************************/ -static int32_t flushFlash(uint32_t addr) -{ - int32_t ret; - - // Erase flash page - ret = bootloader_eraseRawStorage(addr, FLASH_PAGESIZE); - - if (ret & BOOTLOADER_ERROR_STORAGE_BASE) { - return ret; - } - - // Program flash page - ret = bootloader_writeRawStorage(addr, (uint8_t*)flashPageBuf, FLASH_PAGESIZE); - return ret; -} - -/***************************************************************************//** - * @brief - * Process a file and reprogram the bootloader storage area - * - * @param[in] path - * Path of the file to be processed - * - * @param[in] fileName - * Name of the file to be processed - * - * @return - * True if the reprogrammed image is valid, otherwise false - ******************************************************************************/ -static bool reprogramGBLStorage(char* path, char* fileName) -{ - int32_t ret; - uint8_t* flashAddr = diskStorage; - FRESULT res; - char fileDir[PATH_LENGTH]; - - strcpy(fileDir, path); - strcat(fileDir, "/"); - strcat(fileDir, fileName); - - res = f_open(&fh, fileDir, FA_READ); - if (res == FR_OK) { - while (1) { - res = f_read(&fh, flashPageBuf, FLASH_PAGESIZE, &bufRead); - if ((res == FR_OK) && (bufRead > 0)) { - ret = flushFlash((uint32_t)flashAddr); - if (ret != BOOTLOADER_OK) { - printf("Writing to the flash failed %ld\n", ret); - break; - } - flashAddr += bufRead; - } else { - break; - } - } - } else { - printf("Failed to open %s\n", fileDir); - } - f_close(&fh); - - if (bootloader_verifyImage(SLOT_ID, NULL) == BOOTLOADER_OK) { - return true; - } - return false; -} - -/***************************************************************************//** - * @brief - * Scan files recursively from the disk - * - * @param[in] path - * Path to traverse - * - * @return - * True if a valid GBL file is found, otherwise false - ******************************************************************************/ -static bool checkValidGbl(char* path) -{ - DIR dir; - FRESULT res; - FILINFO fno; - int pathLen, fnLen; - char *fn; - bool returnVal; - - returnVal = false; - res = f_opendir(&dir, path); - if (res == FR_OK) { - pathLen = strlen(path); - while (1) { - res = f_readdir(&dir, &fno); - if (res != FR_OK || fno.fname[0] == 0) { - break; - } - if (fno.fname[0] == '.') { - continue; - } - fn = fno.fname; - fnLen = strlen(fn); - - if ((fno.fattrib & AM_DIR) - && (pathLen + fnLen + 1) <= PATH_LENGTH) { - sprintf(&path[pathLen], "/%s", fn); - returnVal = checkValidGbl(path); - if (returnVal) { - break; - } - path[pathLen] = 0; - } else { - if (strncmp((char *)&fn[fnLen - 3], FILE_EXT_UPP, 3) == 0 - && (pathLen + fnLen + 1) <= PATH_LENGTH) { - returnVal = reprogramGBLStorage(path, fn); - if (returnVal) { - return true; - } - } - } - } - } else { - printf("f_opendir failure %d\n", res); - } - return returnVal; -} - -/***************************************************************************//** - * @brief - * Find a valid GBL file and reprogram the flash. - ******************************************************************************/ -static void reProgramBLApp(void) -{ - FRESULT res; - bool gblFound; - uint32_t appVersionNewImg, imgInfoVersion; - ApplicationData_t appinfo; - - // Initialize filesystem - res = f_mount(0, &Fatfs); - if (res != FR_OK) { - printf("FAT-mount failed: %d\n", res); - return; - } else { - printf("FAT-mount successful\n"); - } - - gblFound = checkValidGbl(path); - if (gblFound) { - if (bootloader_setImageToBootload(SLOT_ID) == BOOTLOADER_OK) { - bootloader_getImageInfo(SLOT_ID, &appinfo, &imgInfoVersion); - appVersionNewImg = appinfo.version; - - if (appVersionNewImg > sl_app_properties.app.version) { - printf("\nA valid GBL with a newer application version found, reprogramming the flash\n"); - f_mount(0, NULL); - USBTIMER_DelayMs(500); // Wait 500 ms before system reset - bootloader_rebootAndInstall(); - } else { - printf("\nThe GBL file contains an application upgrade image with same/older version\n"); - } - } - } else { - printf("No valid GBL file found\n"); - } - // Clean the bootloader storage space - printf("Erasing the bootloader storage space...\n"); - if (eraseStorageSlot(SLOT_ID) == BOOTLOADER_OK) { - printf("Erasing the bootloader storage space completed\n"); - } - // UNMOUNT drive - printf("USB un-mounting...\n"); - if (f_mount(0, NULL) == FR_OK) { - printf("USB un-mounted\n"); - } -} - -/***************************************************************************//** - * @brief - * Erase the bootloader storage slot - ******************************************************************************/ -static int32_t eraseStorageSlot(uint32_t slotID) -{ - int32_t retVal; - uint32_t eraseOffset; - BootloaderStorageInformation_t infoStorage; - bootloader_getStorageInfo(&infoStorage); - uint32_t flashPageSize = infoStorage.info->pageSize; - BootloaderStorageSlot_t storageSlot; - retVal = bootloader_getStorageSlotInfo(slotID, &storageSlot); - if (retVal != BOOTLOADER_OK) { - return retVal; - } - uint32_t storageSpaceAddr = storageSlot.address; - uint8_t storageBuf[1]; - while (storageSpaceAddr < (storageSlot.address + storageSlot.length)) { - bootloader_readRawStorage(storageSpaceAddr, storageBuf, 1); - if (storageBuf[0] == 0xFF) { - storageSpaceAddr += 1; - } else { - eraseOffset = (storageSpaceAddr & ~(flashPageSize - 1)); - storageSpaceAddr = eraseOffset + flashPageSize; - retVal = bootloader_eraseRawStorage(eraseOffset, flashPageSize); - if (retVal != BOOTLOADER_OK) { - return retVal; - } - } - } - return BOOTLOADER_OK; -} - -/***************************************************************************//** - * @brief main - ******************************************************************************/ -int main(void) -{ - int connectionResult; - USBH_Init_TypeDef is = USBH_INIT_DEFAULT; - BootloaderStorageSlot_t storageSlot; - CMU_HFXOInit_TypeDef hfxoInit = CMU_HFXOINIT_DEFAULT; - - // Chip errata - CHIP_Init(); - BSP_Init(BSP_INIT_DEFAULT); - - // If first word of user data page is non-zero, enable Energy Profiler trace - BSP_TraceProfilerSetup(); - CMU_HFXOInit(&hfxoInit); - CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO); - - RETARGET_SerialInit(); - RETARGET_SerialCrLf(1); - printf("\n\n***USBH Loader Demo***\n"); - - // Initialize USB HOST stack - USBH_Init(&is); - bootloader_getInfo(&info); - printf("\nCurrent Bootloader Version: %lx \n", info.version); - if (info.type == NO_BOOTLOADER) { - printf("\nNo bootloader is present (first stage or main stage invalid)\n"); - EFM_ASSERT(false); - } - - // Initialize Boot Loader - if (bootloader_init() & BOOTLOADER_ERROR_INIT_BASE) { - EFM_ASSERT(false); - } - - if (bootloader_getStorageSlotInfo(SLOT_ID, &storageSlot) & BOOTLOADER_ERROR_STORAGE_BASE) { - EFM_ASSERT(false); - } - printf("\nCurrent APP version: %" PRIu32 "\n", sl_app_properties.app.version); - diskStorage = (uint8_t*)storageSlot.address; - while (1) { - // Wait for device connection - printf("\nWaiting for USB MSD device plug-in...\n"); - connectionResult = USBH_WaitForDeviceConnectionB(tmpBuf, 0); - - if (connectionResult == USB_STATUS_OK) { - printf("A device was attached"); - - if (MSDH_Init(tmpBuf, sizeof(tmpBuf))) { - reProgramBLApp(); - } else { - printf("\nMSD initialization error, please remove device\n"); - } - } else if (connectionResult == USB_STATUS_DEVICE_MALFUNCTION) { - printf("\nA malfunctioning device was attached, please remove device\n"); - } else if (connectionResult == USB_STATUS_PORT_OVERCURRENT) { - printf("\nVBUS overcurrent condition, please remove device\n"); - } - - while (USBH_DeviceConnected()) ; - printf("\nDevice removal detected"); - } -} diff --git a/platform/bootloader/application/plugin/msd-usb-host-loader/plugin.properties b/platform/bootloader/application/plugin/msd-usb-host-loader/plugin.properties deleted file mode 100644 index 8a5f037a43..0000000000 --- a/platform/bootloader/application/plugin/msd-usb-host-loader/plugin.properties +++ /dev/null @@ -1,20 +0,0 @@ -name=USB Host Loader -category=Application -architecture=efm32~family[GI]~series[1]~device_configuration[1], efm32~family[GI]~series[1]~device_configuration[2] -description=USB host loader - -# Files that are released in source - -# Common files -sourceFiles= app_usbh_main.c - -setup(additionalFiles) { - PATH(ABSOLUTE):$BOOTLOADER/api/ - PATH(ABSOLUTE):$BOOTLOADER/config/ -} - -setup(macros) { - -DRETARGET_VCOM - -DAPP_PROPERTIES_VERSION=1 - -DSL_SUPRESS_GECKO_USB_DEPRECATION_WARNINGS=1 -} diff --git a/platform/bootloader/application/plugin/plugins.info b/platform/bootloader/application/plugin/plugins.info deleted file mode 100644 index 2d1e2da9ef..0000000000 --- a/platform/bootloader/application/plugin/plugins.info +++ /dev/null @@ -1,181 +0,0 @@ -pluginDirectory=./ - -plugin(core) { - name=Application Core - category=Core - architecture=efm32~series[1] - description=Core library for bootloader applications - - root=$DEVICE/SiliconLabs/ - - # Files that are released in source - (efm32~family[GI]~series[1]~device_configuration[2]+gcc):EFM32GG12B/Source/startup_efm32gg12b.c - (efm32~family[GI]~series[1]~device_configuration[1]+gcc):EFM32GG11B/Source/startup_efm32gg11b.c - - (efm32~family[GI]~series[1]~device_configuration[2]+iar):EFM32GG12B/Source/startup_efm32gg12b.c - (efm32~family[GI]~series[1]~device_configuration[1]+iar):EFM32GG11B/Source/startup_efm32gg11b.c -} - -plugin(bootloader-interface) { - name=Bootloader - category=Core - architecture=efm32~series[1] - description=Bootloader api - - root=$BOOTLOADER/api - - #common files - btl_interface.c - btl_interface_storage.c -} - -plugin(emlib) { - name=EMLIB - category=Utils - architecture=efr32~series[1],efr32~series[2],efm32~series[1] - description=EMLIB Peripheral Library - - root=$EMLIB/src - - # Files that are released in source - em_cmu.c - em_emu.c - em_gpio.c - em_core.c - em_msc.c - em_rmu.c - em_system.c - em_timer.c - em_usart.c - em_ebi.c - - setup(additionalFiles) { - PATH(ABSOLUTE):$EMLIB/inc - } -} - -plugin(sl_assert) { - name=SL_ASSERT - category=Utils - architecture=efr32~series[1],efr32~series[2],efm32~series[1] - description= Plugin that provides assert functions - - root=$COMMON/src - - # Files that are released in source - sl_assert.c - - setup(additionalFiles) { - PATH(ABSOLUTE):$COMMON/inc - } -} - -plugin(usbd-driver){ - name=USB Device Driver - category=Drivers - architecture=efm32~family[GI]~series[1]~device_configuration[1], efm32~family[GI]~series[1]~device_configuration[2] - description=USB Device driver - - root=$KIT/common/drivers - - msdd.c - retargetio.c - retargetserial.c - - setup(additionalFiles) { - PATH(ABSOLUTE):$KIT/common/drivers - PATH(ABSOLUTE):$KIT/common/bsp - PATH(ABSOLUTE):$BOOTLOADER/application/config/usb-device/ - PATH(ABSOLUTE):$CMSIS/Core/Include/ - } - - headerFiles(efm32~family[GI]~series[1]~device_configuration[1])=../../SLSTK3701A_EFM32GG11/config/retargetserialconfig.h - headerFiles(efm32~family[GI]~series[1]~device_configuration[1])=../../SLSTK3701A_EFM32GG11/config/bspconfig.h - - headerFiles(efm32~family[GI]~series[1]~device_configuration[2])=../../SLTB009A_EFM32GG12/config/retargetserialconfig.h - headerFiles(efm32~family[GI]~series[1]~device_configuration[2])=../../SLTB009A_EFM32GG12/config/bspconfig.h - -} - -plugin(usbh-driver){ - - name=USB Host Driver - category=Drivers - architecture=efm32~family[GI]~series[1]~device_configuration[1], efm32~family[GI]~series[1]~device_configuration[2] - description=USB Host driver - - - root=$KIT/common/drivers - - - #common files - msdh.c - msdscsi.c - msdbot.c - retargetio.c - retargetserial.c - ../bsp/bsp_trace.c - ../bsp/bsp_bcc.c - ../bsp/bsp_stk.c - - - setup(additionalFiles) { - PATH(ABSOLUTE):$KIT/common/drivers - PATH(ABSOLUTE):$KIT/common/bsp - PATH(ABSOLUTE):$BOOTLOADER/application/config/usb-host/ - PATH(ABSOLUTE):$CMSIS/Core/Include/ -} - - headerFiles(efm32~family[GI]~series[1]~device_configuration[1])=../../../../hardware/kit/SLSTK3701A_EFM32GG11/config/retargetserialconfig.h - headerFiles(efm32~family[GI]~series[1]~device_configuration[1])=../../../../hardware/kit/SLSTK3701A_EFM32GG11/config/bspconfig.h - headerFiles(efm32~family[GI]~series[1]~device_configuration[1])=../../../../hardware/kit/SLSTK3701A_EFM32GG11/config/traceconfig.h - - headerFiles(efm32~family[GI]~series[1]~device_configuration[2])=../../../../hardware/kit/SLTB009A_EFM32GG12/config/retargetserialconfig.h - headerFiles(efm32~family[GI]~series[1]~device_configuration[2])=../../../../hardware/kit/SLTB009A_EFM32GG12/config/bspconfig.h - headerFiles(efm32~family[GI]~series[1]~device_configuration[2])=../../../../hardware/kit/SLTB009A_EFM32GG12/config/traceconfig.h - - -} - -plugin(gecko-usb) { - name=USB - category=Utils - architecture=efm32~family[GI]~series[1]~device_configuration[1], efm32~family[GI]~series[1]~device_configuration[2] - description=USB Pheripheral Library - - root=$USB_GECKO/src - - #Files released in source - em_usbd.c - em_usbdch9.c - em_usbdep.c - em_usbdint.c - em_usbhint.c - em_usbh.c - em_usbhal.c - em_usbhep.c - em_usbtimer.c - - - setup(additionalFiles) { - PATH(ABSOLUTE):$USB_GECKO/inc - } -} - -plugin(fatfs){ - name=FatFs - category=Utils - architecture=efm32~family[GI]~series[1]~device_configuration[1], efm32~family[GI]~series[1]~device_configuration[2] - description=Fat filesystem module - - root=$FATFS/src - - #Files released in source - msddiskio.c - ff.c - - setup(additionalFiles) { - $FATFS/inc - } - -} diff --git a/platform/bootloader/application/sample-apps/apps.info b/platform/bootloader/application/sample-apps/apps.info deleted file mode 100644 index dfd1dab90d..0000000000 --- a/platform/bootloader/application/sample-apps/apps.info +++ /dev/null @@ -1,21 +0,0 @@ -usb-device-loader-application { - name=USB Device Loader - dir=usb-device-loader-application/template/ - isc=usb-device-loader-application/template/usb-device-loader-application.isc - architecture=efm32~family[GI]~series[1]~device_configuration[1], efm32~family[GI]~series[1]~device_configuration[2] - - USB Device Loader Example -} - -usb-host-loader-application { - name=USB Host Loader - dir=usb-host-loader-application/template/ - isc=usb-host-loader-application/template/usb-host-loader-application.isc - architecture=efm32~family[GI]~series[1]~device_configuration[1], efm32~family[GI]~series[1]~device_configuration[2] - - USB Host Loader Example -} - - - - diff --git a/platform/bootloader/application/sample-apps/usb-device-loader-application/template/readme.md b/platform/bootloader/application/sample-apps/usb-device-loader-application/template/readme.md deleted file mode 100644 index e7cf36ba98..0000000000 --- a/platform/bootloader/application/sample-apps/usb-device-loader-application/template/readme.md +++ /dev/null @@ -1,5 +0,0 @@ -# USB Device Mass Storage Device GBL Loader Example - -Flash the device with the internal storage bootloader from Gecko bootloader examples to ensure that this example works. - -This example project uses the USB device protocol stack to implement a Mass Storage Device (MSD). Once the kit is connected to a PC via USB, it appears as an MSD with a FAT12-formatted disk. The MSD is used to store a GBL file used for bootloader upgrade. When a valid GBL file is dragged and dropped into the disk, the application waits for the file to be completely transferred. As soon as the transfer is completed, the flash memory allocated for the bootloader storage is reprogrammed with the GBL file. After the bootloader storage is reprogrammed, the bootloader upgrade procedure starts and a software reset is performed. diff --git a/platform/bootloader/application/sample-apps/usb-device-loader-application/template/usb-device-loader-application.isc b/platform/bootloader/application/sample-apps/usb-device-loader-application/template/usb-device-loader-application.isc deleted file mode 100644 index 76dad0344d..0000000000 --- a/platform/bootloader/application/sample-apps/usb-device-loader-application/template/usb-device-loader-application.isc +++ /dev/null @@ -1,43 +0,0 @@ -#ISD afv6 -# ISD version: 4.21.0.201709251649-886 - -# Application configuration -appId: application -frameworkRoot: platform/bootloader/application -architecture: EFM32GG11B820F2048GL192+BRD2204A+gcc -deviceName: bootloader application -generationDirectory: PATH(ISC_RELATIVE):. - -# Devices - -# Plugin configuration -appPlugin: msd-usb-device-loader=true -appPlugin: msd-usb-host-loader=false -appPlugin: emlib=true -appPlugin: usbd-driver=true -appPlugin: usbh-driver=false -appPlugin: gecko-usb=true -appPlugin: core=true -appPlugin: bootloader-interface=true -appPlugin: fatfs=false -appPlugin: sl_assert=true - - -# Setup configurations - -{setupId:information -\{key:description -USB Device Mass Storage Device GBL loader example. - -The device is required to be flashed with the Internal Storage Bootloader from Gecko Bootloader Examples in order for this example to work. - -This example project use the USB device protocol stack to implement a Mass Storage Class device (MSD). Once the kit is connected to a PC via USB, it appears as a MSD with a FAT12 formatted disk. The MSD is used to store a gbl file used for bootloader upgrade. When a valid gbl file is dragged and dropped into the disk, the application waits for the file to be completely transferred. As soon as the transfer is completed, the flash memory allocated for the bootloader storage is reprogrammed with the gbl file. After the bootloader storage is reprogrammed, the bootloader upgrade procedure starts and a software reset is performed. -\} -} -{setupId:macros -} -{setupId:template -} - -# Plugin options - diff --git a/platform/bootloader/application/sample-apps/usb-host-loader-application/template/readme.md b/platform/bootloader/application/sample-apps/usb-host-loader-application/template/readme.md deleted file mode 100644 index 4fcffd57a7..0000000000 --- a/platform/bootloader/application/sample-apps/usb-host-loader-application/template/readme.md +++ /dev/null @@ -1,5 +0,0 @@ -# USB Host Mass Storage Device GBL Loader Example - -Flash the device with the internal storage bootloader from Gecko bootloader examples to ensure that this example works. - -This example project uses the USB host and the MSD modules in the Drivers directory to implement support for Mass Storage Devices (MSD). Information about the MSD device will be output on the VCOM port. When an MSD device is connected and detected as valid, this application will start looking for a valid GBL file. Once the GBL file is found, the flash memory allocated for the bootloader storage is reprogrammed with the GBL file. Right after the bootloader storage is reprogrammed, the bootloader upgrade procedure starts and a software reset is performed. diff --git a/platform/bootloader/application/sample-apps/usb-host-loader-application/template/usb-host-loader-application.isc b/platform/bootloader/application/sample-apps/usb-host-loader-application/template/usb-host-loader-application.isc deleted file mode 100644 index 40e0136b3a..0000000000 --- a/platform/bootloader/application/sample-apps/usb-host-loader-application/template/usb-host-loader-application.isc +++ /dev/null @@ -1,42 +0,0 @@ -#ISD afv6 -# ISD version: 4.21.0.201709251649-886 - -# Application configuration -appId: application -frameworkRoot: platform/bootloader/application -architecture: EFM32GG11B820F2048GL192+BRD2204A+gcc -deviceName: bootloader application -generationDirectory: PATH(ISC_RELATIVE):. - -# Devices - -# Plugin configuration -appPlugin: msd-usb-device-loader=false -appPlugin: msd-usb-host-loader=true -appPlugin: emlib=true -appPlugin: usbd-driver=false -appPlugin: usbh-driver=true -appPlugin: gecko-usb=true -appPlugin: core=true -appPlugin: bootloader-interface=true -appPlugin: fatfs=true -appPlugin: sl_assert=true - -# Setup configurations - -{setupId:information -\{key:description -USB Host Mass Storage Device GBL loader example. - -The device is required to be flashed with the Internal Storage Bootloader from Gecko Bootloader Examples in order for this example to work. - -This example project uses the USB host and the MSD modules in the drivers directory to implement support for Mass Storage Device's (MSD). Info about the MSD device will be output on the VCOM port. When a MSD device is connected and detected as valid, this application will start looking for a valid gbl file. Once the gbl file is found, the flash memory allocated for the bootloader storage is reprogrammed with the gbl file. Right after the bootloader storage is reprogrammed, the bootloader upgrade procedure starts and a software reset is performed. - -\} -} -{setupId:macros -} -{setupId:template -} - -# Plugin options \ No newline at end of file diff --git a/platform/bootloader/bootloader_beta_templates.xml b/platform/bootloader/bootloader_beta_templates.xml index face946dec..d162835d1f 100644 --- a/platform/bootloader/bootloader_beta_templates.xml +++ b/platform/bootloader/bootloader_beta_templates.xml @@ -1,13 +1,44 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - + + + @@ -17,11 +48,12 @@ + - - - + + + @@ -31,11 +63,12 @@ + - - - + + + @@ -45,11 +78,12 @@ + - - - + + + @@ -59,11 +93,12 @@ + - - - + + + @@ -73,11 +108,12 @@ + - - - + + + diff --git a/platform/bootloader/bootloader_production_templates.xml b/platform/bootloader/bootloader_production_templates.xml index f50b429a2f..48409bbe03 100644 --- a/platform/bootloader/bootloader_production_templates.xml +++ b/platform/bootloader/bootloader_production_templates.xml @@ -3,11 +3,12 @@ + - - - + + + @@ -17,11 +18,12 @@ + - - - + + + @@ -31,11 +33,12 @@ + - - + + @@ -45,11 +48,12 @@ + - - - + + + @@ -59,11 +63,12 @@ + - - - + + + @@ -73,11 +78,12 @@ + - - + + @@ -87,11 +93,12 @@ + - - - + + + @@ -101,11 +108,12 @@ + - - - + + + @@ -115,11 +123,12 @@ + - - - + + + @@ -129,11 +138,12 @@ + - - - + + + @@ -143,11 +153,12 @@ + - - - + + + @@ -157,11 +168,12 @@ + - - + + @@ -171,11 +183,12 @@ + - - - + + + @@ -185,11 +198,12 @@ + - - - + + + @@ -199,11 +213,12 @@ + - - - + + + @@ -213,11 +228,12 @@ + - - - + + + @@ -227,11 +243,12 @@ + - - - + + + @@ -241,15 +258,46 @@ + - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/platform/bootloader/communication/apploader/btl_apploader.h b/platform/bootloader/communication/apploader/btl_apploader.h index 994effc7b5..df72e1ae42 100644 --- a/platform/bootloader/communication/apploader/btl_apploader.h +++ b/platform/bootloader/communication/apploader/btl_apploader.h @@ -68,9 +68,9 @@ int32_t bootloader_apploader_communication_start(void); * @return Error code indicating success or failure. ******************************************************************************/ int32_t bootloader_apploader_communication_main(ImageProperties_t *imageProps, - ParserContext_t *parserContext, - DecryptContext_t *decryptContext, - AuthContext_t *authContext, + void *parserContext, + void *decryptContext, + void *authContext, const BootloaderParserCallbacks_t *parseCb); /** @} addtogroup Communication */ diff --git a/platform/bootloader/communication/apploader/btl_apploader_common.c b/platform/bootloader/communication/apploader/btl_apploader_common.c index 8c3f1527cf..04e2a27ab2 100644 --- a/platform/bootloader/communication/apploader/btl_apploader_common.c +++ b/platform/bootloader/communication/apploader/btl_apploader_common.c @@ -35,9 +35,6 @@ #include "core/btl_reset.h" #endif -// Debug -#include "debug/btl_debug.h" - #include #include @@ -69,11 +66,14 @@ static volatile bool isConnected; static volatile bool hasDisconnected; static volatile bool started; + static ImageProperties_t *apploader_imageProps; -static ParserContext_t *apploader_parserContext; -static DecryptContext_t *apploader_decryptContext; -static AuthContext_t *apploader_authContext; +#if !defined (BOOTLOADER_NONSECURE) static const BootloaderParserCallbacks_t *apploader_parseCb; +static void *apploader_parserContext; +static void *apploader_decryptContext; +static void *apploader_authContext; +#endif // ----------------------------------------------------------------------------- // Static local functions @@ -100,13 +100,21 @@ void bootloader_apploader_disconnection_complete() if (apploader_imageProps->contents & BTL_IMAGE_CONTENT_SE) { if (bootload_checkSeUpgradeVersion(apploader_imageProps->seUpgradeVersion)) { // Install SE upgrade +#if defined(BOOTLOADER_NONSECURE) + bootload_commitSeUpgrade(); +#else bootload_commitSeUpgrade(BTL_UPGRADE_LOCATION); +#endif } } if (apploader_imageProps->contents & BTL_IMAGE_CONTENT_BOOTLOADER) { if (apploader_imageProps->bootloaderVersion > bootload_getBootloaderVersion()) { // Install bootloader upgrade +#if defined(BOOTLOADER_NONSECURE) + bootload_commitBootloaderUpgrade(apploader_imageProps->bootloaderUpgradeSize); +#else bootload_commitBootloaderUpgrade(BTL_UPGRADE_LOCATION, apploader_imageProps->bootloaderUpgradeSize); +#endif } } } @@ -120,17 +128,11 @@ uint32_t bootloader_apploader_get_bootloader_version() uint32_t bootloader_apploader_get_application_version() { uint32_t appVersion = 0; - BareBootTable_t *appStart = (BareBootTable_t *)BTL_APPLICATION_BASE; - ApplicationProperties_t *appProperties = (ApplicationProperties_t *)(appStart->signature); - - if (((size_t)appProperties > (size_t)mainBootloaderTable->startOfAppSpace) - && ((size_t)appProperties < (size_t)mainBootloaderTable->endOfAppSpace)) { - // App properties points into flash - if (bootload_checkApplicationPropertiesMagic(appProperties)) { - appVersion = appProperties->app.version; - } + if (bootload_getApplicationVersion(&appVersion)) { + return appVersion; } - return appVersion; + + return 0u; } int32_t bootloader_apploader_parse_gbl(uint8_t *data, size_t len) @@ -142,7 +144,7 @@ int32_t bootloader_apploader_parse_gbl(uint8_t *data, size_t len) len, apploader_imageProps); #else - ret = parser_parse(apploader_parserContext, + ret = parser_parse((ParserContext_t *)apploader_parserContext, apploader_imageProps, data, len, @@ -156,9 +158,9 @@ int32_t bootloader_apploader_parser_init() #if defined(BOOTLOADER_NONSECURE) return parser_init(PARSER_FLAG_PARSE_CUSTOM_TAGS); #else - return parser_init(apploader_parserContext, - apploader_decryptContext, - apploader_authContext, + return parser_init((ParserContext_t *)apploader_parserContext, + (DecryptContext_t *)apploader_decryptContext, + (AuthContext_t *)apploader_authContext, PARSER_FLAG_PARSE_CUSTOM_TAGS); #endif } @@ -182,7 +184,9 @@ int32_t bootloader_apploader_parser_finish() void bootloader_apploader_communication_init(void) { +#if !defined(BOOTLOADER_NONSECURE) sl_device_init_clocks(); +#endif // Configure Bluetooth static sl_apploader_config_t btConfig = { @@ -253,16 +257,19 @@ int32_t bootloader_apploader_communication_start(void) } int32_t bootloader_apploader_communication_main(ImageProperties_t *imageProps, - ParserContext_t *parserContext, - DecryptContext_t *decryptContext, - AuthContext_t *authContext, + void *parserContext, + void *decryptContext, + void *authContext, const BootloaderParserCallbacks_t *parseCb) { apploader_imageProps = imageProps; +#if !defined (BOOTLOADER_NONSECURE) apploader_parserContext = parserContext; apploader_decryptContext = decryptContext; apploader_authContext = authContext; apploader_parseCb = parseCb; +#endif + while (1) { if (isConnected) { sl_apploader_run(); diff --git a/platform/bootloader/communication/apploader/btl_apploader_ns.c b/platform/bootloader/communication/apploader/btl_apploader_ns.c new file mode 100644 index 0000000000..8a8f461769 --- /dev/null +++ b/platform/bootloader/communication/apploader/btl_apploader_ns.c @@ -0,0 +1,62 @@ +/***************************************************************************//** + * @file + * @brief Communication component implementing BLE Apploader OTA DFU protocol + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +// ----------------------------------------------------------------------------- +// Includes + +#include "btl_apploader.h" +#include "communication/btl_communication.h" + +// ----------------------------------------------------------------------------- +// Functions + +void communication_init(void) +{ + bootloader_apploader_communication_init(); +} + +int32_t communication_start(void) +{ + return bootloader_apploader_communication_start(); +} + +int32_t communication_main(void) +{ + int32_t ret = BOOTLOADER_OK; + + ImageProperties_t imageProps = { + .contents = 0U, + .imageCompleted = false, + .imageVerified = false, + .bootloaderVersion = 0, +#if defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) + .seUpgradeVersion = 0 +#endif + }; + + ret = bootloader_apploader_communication_main(&imageProps, + NULL, + NULL, + NULL, + NULL); + return ret; +} + +void communication_shutdown(void) +{ + // Do nothing +} diff --git a/platform/bootloader/component/bootloader_apploader_nonsecure.slcc b/platform/bootloader/component/bootloader_apploader_nonsecure.slcc new file mode 100644 index 0000000000..c682f2749d --- /dev/null +++ b/platform/bootloader/component/bootloader_apploader_nonsecure.slcc @@ -0,0 +1,28 @@ +id: bootloader_apploader_nonsecure +label: "Bluetooth AppLoader OTA DFU (Non-Secure)" +package: bootloader +description: AppLoader provides Bluetooth OTA updates for applications. +category: Platform|Bootloader|TrustZone NonSecure|Communication +quality: beta +source: + - path: platform/bootloader/communication/apploader/btl_apploader_ns.c + - path: platform/bootloader/communication/apploader/btl_apploader_common.c +include: + - path: platform/bootloader/communication + file_list: + - path: apploader/btl_apploader.h + - path: apploader/btl_apploader_callback.h + - path: btl_communication.h +requires: + - name: status + - name: apploader_lib + - name: device_series_2 + - name: device_supports_bluetooth +define: + - name: BOOTLOADER_SUPPORT_COMMUNICATION + value: 1 + - name: BOOTLOADER_APPLOADER + value: 1 +provides: + - name: bootloader_apploader + - name: bootloader_apploader_nonsecure \ No newline at end of file diff --git a/platform/bootloader/component/bootloader_apploader_secure.slcc b/platform/bootloader/component/bootloader_apploader_secure.slcc new file mode 100644 index 0000000000..fc45f0e2c9 --- /dev/null +++ b/platform/bootloader/component/bootloader_apploader_secure.slcc @@ -0,0 +1,14 @@ +id: bootloader_apploader_secure +label: "Bluetooth AppLoader OTA DFU (Secure)" +package: bootloader +description: AppLoader provides Bluetooth OTA updates for applications. +category: Platform|Bootloader|TrustZone Secure|Communication +quality: beta +define: + - name: BOOTLOADER_SUPPORT_COMMUNICATION + value: 1 + - name: BOOTLOADER_APPLOADER + value: 1 +provides: + - name: bootloader_apploader + - name: bootloader_apploader_secure \ No newline at end of file diff --git a/platform/bootloader/component/bootloader_bgapi_uartdfu_nonsecure.slcc b/platform/bootloader/component/bootloader_bgapi_uartdfu_nonsecure.slcc index e1045a82e6..62da3e2c90 100644 --- a/platform/bootloader/component/bootloader_bgapi_uartdfu_nonsecure.slcc +++ b/platform/bootloader/component/bootloader_bgapi_uartdfu_nonsecure.slcc @@ -1,5 +1,5 @@ id: bootloader_bgapi_uartdfu_nonsecure -label: "BGAPI UART DFU" +label: "BGAPI UART DFU (Non-Secure)" package: bootloader description: UART DFU for Bluetooth applications using the BGAPI protocol. category: Platform|Bootloader|TrustZone NonSecure|Communication diff --git a/platform/bootloader/component/bootloader_core_nonsecure.slcc b/platform/bootloader/component/bootloader_core_nonsecure.slcc index e65da4a0f8..7cda5a06a4 100644 --- a/platform/bootloader/component/bootloader_core_nonsecure.slcc +++ b/platform/bootloader/component/bootloader_core_nonsecure.slcc @@ -1,5 +1,5 @@ id: bootloader_core_nonsecure -label: Bootloader Core +label: Bootloader Core (Non-Secure) package: bootloader description: NonSecure Core library for Gecko bootloader. category: Platform|Bootloader|TrustZone NonSecure|Core @@ -92,12 +92,36 @@ template_contribution: value: 0x8005000 condition: - device_sdid_230 # xG27 + + # Memory flash size - name: memory_flash_size value: 4096 + unless: + - bootloader_apploader + - name: memory_flash_size + value: 0xF000 + condition: + - bootloader_apploader + + # Memory RAM start - name: memory_ram_start value: 0x20006000 + unless: + - bootloader_apploader + - name: memory_ram_start + value: 0x20002000 + condition: + - bootloader_apploader + + # Memory RAM size - name: memory_ram_size value: 0x2000 + unless: + - bootloader_apploader + - name: memory_ram_size + value: 0x6000 + condition: + - bootloader_apploader toolchain_settings: - option: optimize diff --git a/platform/bootloader/component/bootloader_core_secure.slcc b/platform/bootloader/component/bootloader_core_secure.slcc index d8dfbee792..094f73023e 100644 --- a/platform/bootloader/component/bootloader_core_secure.slcc +++ b/platform/bootloader/component/bootloader_core_secure.slcc @@ -1,5 +1,5 @@ id: bootloader_core_secure -label: Bootloader Core +label: Bootloader Core (Secure) package: bootloader description: Secure Core library for Gecko bootloader. category: Platform|Bootloader|TrustZone Secure|Core @@ -28,15 +28,24 @@ define: value: 1 - name: BOOTLOADER_SECOND_STAGE value: 1 - - name: NS_FLASH_OFFSET - value: 0x5000 - - name: NS_RAM_OFFSET - value: 0x6000 - name: SL_STACK_SIZE value: 2048 - name: SL_HEAP_SIZE value: 0 + # Non-Secure Memory layout + - name: NS_FLASH_OFFSET + value: 0x5000 + + - name: NS_RAM_OFFSET + value: 0x2000 + condition: + - bootloader_apploader + - name: NS_RAM_OFFSET + value: 0x6000 + unless: + - bootloader_apploader + include: - path: platform/bootloader file_list: @@ -61,7 +70,10 @@ provides: - name: bootloader_secure_incompatible requires: + - name: device_init + condition: [bootloader_apploader] - name: emlib + - name: tz_service_syscfg - name: bootloader_tz_secure - name: bootloader_tz_utils @@ -84,11 +96,26 @@ config_file: file_id: btl_core_config condition: - device_sdid_205 + unless: + - bootloader_apploader + - path: platform/bootloader/config/s2/device_sdid_205/apploader/btl_core_s_cfg.h + file_id: btl_core_config + condition: + - device_sdid_205 + - bootloader_apploader + # Series-2 - path: platform/bootloader/config/s2/device_series_2/btl_core_s_cfg.h file_id: btl_core_config unless: - device_sdid_205 + - bootloader_apploader + - path: platform/bootloader/config/s2/device_series_2/apploader/btl_core_s_cfg.h + file_id: btl_core_config + condition: + - bootloader_apploader + unless: + - device_sdid_205 template_contribution: - name: bootloader_enable @@ -99,6 +126,12 @@ template_contribution: value: 0x20000000 - name: memory_ram_size value: 0x6000 + unless: + - bootloader_apploader + - name: memory_ram_size + value: 0x2000 + condition: + - bootloader_apploader - name: bootloader_flash_addr value: 0x0 @@ -120,12 +153,15 @@ template_contribution: value: 0x8000000 condition: - device_sdid_220 # xG25 - - name: bootloader_main_size - value: 0x5000 - name: bootloader_flash_addr value: 0x08000000 condition: - device_sdid_230 # XG27 + + # Bootloader size + - name: bootloader_main_size + value: 0x5000 + toolchain_settings: - option: gcc_compiler_option value: -std=gnu99 diff --git a/platform/bootloader/component/bootloader_crc_nonsecure.slcc b/platform/bootloader/component/bootloader_crc_nonsecure.slcc index 4bfce1c35d..6ed4b423d2 100644 --- a/platform/bootloader/component/bootloader_crc_nonsecure.slcc +++ b/platform/bootloader/component/bootloader_crc_nonsecure.slcc @@ -1,5 +1,5 @@ id: bootloader_crc_nonsecure -label: Cyclic Redundancy Check +label: Cyclic Redundancy Check (Non-Secure) package: bootloader description: > Software implementations of 16- and 32-bit CRC diff --git a/platform/bootloader/component/bootloader_debug_nonsecure.slcc b/platform/bootloader/component/bootloader_debug_nonsecure.slcc index fbd7990693..ac605f5769 100644 --- a/platform/bootloader/component/bootloader_debug_nonsecure.slcc +++ b/platform/bootloader/component/bootloader_debug_nonsecure.slcc @@ -1,5 +1,5 @@ id: bootloader_debug_nonsecure -label: Debug +label: Debug (Non-Secure) package: bootloader description: > Build debug instrumentation into the bootloader. diff --git a/platform/bootloader/component/bootloader_delay_driver_nonsecure.slcc b/platform/bootloader/component/bootloader_delay_driver_nonsecure.slcc index a0900fbf1b..b7fc8ac360 100644 --- a/platform/bootloader/component/bootloader_delay_driver_nonsecure.slcc +++ b/platform/bootloader/component/bootloader_delay_driver_nonsecure.slcc @@ -1,5 +1,5 @@ id: bootloader_delay_driver_nonsecure -label: Bootloader Delay Driver +label: Bootloader Delay Driver (Non-Secure) package: bootloader description: > Micro and millisecond delays diff --git a/platform/bootloader/component/bootloader_ezsp_spi_nonsecure.slcc b/platform/bootloader/component/bootloader_ezsp_spi_nonsecure.slcc index 93ad801a88..26310924e3 100644 --- a/platform/bootloader/component/bootloader_ezsp_spi_nonsecure.slcc +++ b/platform/bootloader/component/bootloader_ezsp_spi_nonsecure.slcc @@ -1,5 +1,5 @@ id: bootloader_ezsp_spi_nonsecure -label: "EZSP-SPI" +label: "EZSP-SPI (Non-Secure)" package: bootloader description: Firmware upgrade over SPI using the EZSP protocol. Configure pinout in the SPI Peripheral component category: Platform|Bootloader|TrustZone NonSecure|Communication diff --git a/platform/bootloader/component/bootloader_image_parser_nonsecure.slcc b/platform/bootloader/component/bootloader_image_parser_nonsecure.slcc index ca98777dcb..889a1eefe6 100644 --- a/platform/bootloader/component/bootloader_image_parser_nonsecure.slcc +++ b/platform/bootloader/component/bootloader_image_parser_nonsecure.slcc @@ -1,5 +1,5 @@ id: bootloader_image_parser_nonsecure -label: Image Parser +label: Image Parser (Non-Secure) package: bootloader description: > Image parser diff --git a/platform/bootloader/component/bootloader_include_parser_nonsecure.slcc b/platform/bootloader/component/bootloader_include_parser_nonsecure.slcc index 2b0b68e5af..87533ab5cb 100644 --- a/platform/bootloader/component/bootloader_include_parser_nonsecure.slcc +++ b/platform/bootloader/component/bootloader_include_parser_nonsecure.slcc @@ -1,5 +1,5 @@ id: bootloader_include_parser_nonsecure -label: Bootloader Include Parser +label: Bootloader Include Parser (Non-Secure) package: bootloader description: > Image Parser Header Files diff --git a/platform/bootloader/component/bootloader_internal_storage.slcc b/platform/bootloader/component/bootloader_internal_storage.slcc index a1eaab2bbc..5a791c4e3f 100644 --- a/platform/bootloader/component/bootloader_internal_storage.slcc +++ b/platform/bootloader/component/bootloader_internal_storage.slcc @@ -39,4 +39,4 @@ config_file: - path: platform/bootloader/config/s2/btl_internal_storage_cfg.h file_id: btl_internal_storage_config condition: - - device_series_2 + - device_series_2 \ No newline at end of file diff --git a/platform/bootloader/component/bootloader_serial_driver_nonsecure.slcc b/platform/bootloader/component/bootloader_serial_driver_nonsecure.slcc index f8f07763df..89a3353838 100644 --- a/platform/bootloader/component/bootloader_serial_driver_nonsecure.slcc +++ b/platform/bootloader/component/bootloader_serial_driver_nonsecure.slcc @@ -1,5 +1,5 @@ id: bootloader_serial_driver_nonsecure -label: Bootloader Serial Driver +label: Bootloader Serial Driver (Non-Secure) package: bootloader description: > DMA-driven Serial driver. diff --git a/platform/bootloader/component/bootloader_spi_peripheral_driver_nonsecure.slcc b/platform/bootloader/component/bootloader_spi_peripheral_driver_nonsecure.slcc index d3d2423b87..f644e4e8de 100644 --- a/platform/bootloader/component/bootloader_spi_peripheral_driver_nonsecure.slcc +++ b/platform/bootloader/component/bootloader_spi_peripheral_driver_nonsecure.slcc @@ -1,5 +1,5 @@ id: bootloader_spi_peripheral_driver_nonsecure -label: Bootloader SPI Peripheral Driver +label: Bootloader SPI Peripheral Driver (Non-Secure) package: bootloader description: > DMA-driven SPI Peripheral driver. diff --git a/platform/bootloader/component/bootloader_tz_nonsecure.slcc b/platform/bootloader/component/bootloader_tz_nonsecure.slcc index 9abecd9216..87ace12af7 100644 --- a/platform/bootloader/component/bootloader_tz_nonsecure.slcc +++ b/platform/bootloader/component/bootloader_tz_nonsecure.slcc @@ -3,9 +3,8 @@ label: "Bootloader TrustZone Non-Secure" description: > Set up bootloader configuration to create TrustZone Non-Secure bootloader. package: platform -category: Platform|Common +category: Platform|Bootloader|TrustZone NonSecure quality: beta -root_path: platform/common define: - name: BOOTLOADER_NONSECURE value: 1 diff --git a/platform/bootloader/component/bootloader_tz_secure.slcc b/platform/bootloader/component/bootloader_tz_secure.slcc index 2181480e4a..77bd573a8b 100644 --- a/platform/bootloader/component/bootloader_tz_secure.slcc +++ b/platform/bootloader/component/bootloader_tz_secure.slcc @@ -3,9 +3,8 @@ label: "Bootloader TrustZone Secure" description: > Set up bootloader configuration to create TrustZone Secure bootloader. package: platform -category: Platform|Common +category: Platform|Bootloader|TrustZone Secure quality: beta -root_path: platform/common define: - name: BOOTLOADER_SECURE value: 1 diff --git a/platform/bootloader/component/bootloader_tz_secure_config.slcc b/platform/bootloader/component/bootloader_tz_secure_config.slcc new file mode 100644 index 0000000000..ffa6916d7c --- /dev/null +++ b/platform/bootloader/component/bootloader_tz_secure_config.slcc @@ -0,0 +1,24 @@ +id: bootloader_tz_secure_config +package: platform +description: >- + This component includes the TZ secure configuration file. +category: Platform|Bootloader|TrustZone Secure +ui_hints: + visibility: never +quality: beta +component_root_path: platform/bootloader + +provides: + - name: bootloader_tz_secure_config + +requires: + - name: trustzone_secure + +include: + - path: config + file_list: + - path: sl_trustzone_secure_config.h + +template_contribution: + - name: component_catalog + value: trustzone_secure_config diff --git a/platform/bootloader/component/bootloader_tz_utils.slcc b/platform/bootloader/component/bootloader_tz_utils.slcc index 5fa5e97df4..d7c47c71f2 100644 --- a/platform/bootloader/component/bootloader_tz_utils.slcc +++ b/platform/bootloader/component/bootloader_tz_utils.slcc @@ -3,7 +3,7 @@ label: Bootloader TZ utilities package: bootloader description: > Provides the TZ utilities -category: Platform|Bootloader|Secure|Utils +category: Platform|Bootloader|TrustZone Secure|Utils quality: production source: - path: platform/bootloader/core/btl_tz_utils.c diff --git a/platform/bootloader/component/bootloader_uart_xmodem_nonsecure.slcc b/platform/bootloader/component/bootloader_uart_xmodem_nonsecure.slcc index 9fbde036a0..793f720f9e 100644 --- a/platform/bootloader/component/bootloader_uart_xmodem_nonsecure.slcc +++ b/platform/bootloader/component/bootloader_uart_xmodem_nonsecure.slcc @@ -1,5 +1,5 @@ id: bootloader_uart_xmodem_nonsecure -label: "UART XMODEM" +label: "UART XMODEM (Non-Secure)" package: bootloader description: Firmware upgrade over UART using the XMODEM-CRC file transfer protocol category: Platform|Bootloader|TrustZone NonSecure|Communication diff --git a/platform/bootloader/component/bootloader_xmodem_parser_nonsecure.slcc b/platform/bootloader/component/bootloader_xmodem_parser_nonsecure.slcc index 179aef755e..c45a639653 100644 --- a/platform/bootloader/component/bootloader_xmodem_parser_nonsecure.slcc +++ b/platform/bootloader/component/bootloader_xmodem_parser_nonsecure.slcc @@ -1,5 +1,5 @@ id: bootloader_xmodem_parser_nonsecure -label: "XMODEM Parser" +label: "XMODEM Parser (Non-Secure)" package: bootloader description: XMODEM parser implementation. category: Platform|Bootloader|TrustZone NonSecure|Communication diff --git a/platform/bootloader/config/btl_config.h b/platform/bootloader/config/btl_config.h index 4f59a3cde7..8370fcf3f1 100644 --- a/platform/bootloader/config/btl_config.h +++ b/platform/bootloader/config/btl_config.h @@ -41,7 +41,7 @@ MISRAC_ENABLE #endif #ifndef BOOTLOADER_VERSION_MAIN_CUSTOMER -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 0 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 #endif #define BOOTLOADER_VERSION_MAIN (BOOTLOADER_VERSION_MAIN_MAJOR << 24 \ @@ -62,7 +62,7 @@ MISRAC_ENABLE #define BTL_UPGRADE_LOCATION_BASE 0x8000UL #endif // _SILICON_LABS_32B_SERIES_1 -#ifndef BTL_UPGRADE_LOCATION +#if !defined(BTL_UPGRADE_LOCATION) && !defined(BOOTLOADER_NONSECURE) #define BTL_UPGRADE_LOCATION (FLASH_BASE + BTL_UPGRADE_LOCATION_BASE) #endif diff --git a/platform/bootloader/config/btl_storage_slot_cfg.h b/platform/bootloader/config/btl_storage_slot_cfg.h index 1fd1ca296c..f74aadfc7d 100644 --- a/platform/bootloader/config/btl_storage_slot_cfg.h +++ b/platform/bootloader/config/btl_storage_slot_cfg.h @@ -31,9 +31,11 @@ #define SLOT0_ENABLE 0 // Start Address +// #define SLOT0_START 0 // Slot Size +// #define SLOT0_SIZE 65536 // Enable Slot 1 @@ -41,9 +43,11 @@ #define SLOT1_ENABLE 0 // Start Address +// #define SLOT1_START 0 // Slot Size +// #define SLOT1_SIZE 69632 // Enable Slot 2 @@ -51,9 +55,11 @@ #define SLOT2_ENABLE 0 // Start Address +// #define SLOT2_START 0 // Slot Size +// #define SLOT2_SIZE 73728 // // @@ -94,6 +100,7 @@ #define BTL_STORAGE_NUM_SLOTS (0) #define BTL_STORAGE_SLOTS \ { \ + { 0, 0 }, \ } \ // Number of slots in bootload list #define BTL_STORAGE_BOOTLOAD_LIST_LENGTH BTL_STORAGE_NUM_SLOTS diff --git a/platform/bootloader/config/s1/device_sdid_80/btl_core_cfg.h b/platform/bootloader/config/s1/device_sdid_80/btl_core_cfg.h index 6242d7e213..2226fc05f5 100644 --- a/platform/bootloader/config/s1/device_sdid_80/btl_core_cfg.h +++ b/platform/bootloader/config/s1/device_sdid_80/btl_core_cfg.h @@ -90,7 +90,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 0 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 // Use custom Bootloader Application Size // Default: 0 diff --git a/platform/bootloader/config/s1/device_sdid_80/device_has_radio/btl_core_cfg.h b/platform/bootloader/config/s1/device_sdid_80/device_has_radio/btl_core_cfg.h index d940fd0996..5383b2b193 100644 --- a/platform/bootloader/config/s1/device_sdid_80/device_has_radio/btl_core_cfg.h +++ b/platform/bootloader/config/s1/device_sdid_80/device_has_radio/btl_core_cfg.h @@ -90,7 +90,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 0 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 // Use custom Bootloader Application Size // Default: 0 diff --git a/platform/bootloader/config/s1/device_series_1/btl_core_cfg.h b/platform/bootloader/config/s1/device_series_1/btl_core_cfg.h index cd5ac94b08..b6add5ce01 100644 --- a/platform/bootloader/config/s1/device_series_1/btl_core_cfg.h +++ b/platform/bootloader/config/s1/device_series_1/btl_core_cfg.h @@ -91,7 +91,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 0 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 // Use custom Bootloader Application Size // Default: 0 diff --git a/platform/bootloader/config/s2/device_sdid_205/apploader/btl_core_cfg.h b/platform/bootloader/config/s2/device_sdid_205/apploader/btl_core_cfg.h index 8a2b9254c2..98ac9ed2bf 100644 --- a/platform/bootloader/config/s2/device_sdid_205/apploader/btl_core_cfg.h +++ b/platform/bootloader/config/s2/device_sdid_205/apploader/btl_core_cfg.h @@ -14,8 +14,8 @@ * sections of the MSLA applicable to Source Code. * ******************************************************************************/ -#ifndef BTL_CORE_APPLOADER_CONFIG_H -#define BTL_CORE_APPLOADER_CONFIG_H +#ifndef BTL_CORE_CONFIG_H +#define BTL_CORE_CONFIG_H // <<< Use Configuration Wizard in Context Menu >>> // Bootloader Core Configuration @@ -103,7 +103,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 0 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 // Use custom Bootloader Application Size // Default: 0 @@ -125,4 +125,4 @@ // <<< end of configuration section >>> -#endif // BTL_CORE_APPLOADER_CONFIG_H +#endif // BTL_CORE_CONFIG_H diff --git a/platform/bootloader/config/s2/device_sdid_205/apploader/btl_core_s_cfg.h b/platform/bootloader/config/s2/device_sdid_205/apploader/btl_core_s_cfg.h new file mode 100644 index 0000000000..06ef7bbf09 --- /dev/null +++ b/platform/bootloader/config/s2/device_sdid_205/apploader/btl_core_s_cfg.h @@ -0,0 +1,118 @@ +/***************************************************************************//** + * @file + * @brief Configuration header of Bootloader Core for device_sdid_205 + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_CORE_S_CONFIG_H +#define BTL_CORE_S_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> +// Bootloader Core Configuration + +// Require signed firmware upgrade files +// Default: 0 +// Require that firmware upgrade files are authenticated using asymmetric signature verification. +#define BOOTLOADER_ENFORCE_SIGNED_UPGRADE 0 + +// Require encrypted firmware upgrade files +// Default: 0 +// Require that firmware upgrade files are encrypted. +#define BOOTLOADER_ENFORCE_ENCRYPTED_UPGRADE 0 + +// Use symmetric key stored in Application Properties Struct +// Default: 0 +// Use the symmetric key stored in Application Properties Struct for encryption and decryption. +#define BOOTLOADER_USE_SYMMETRIC_KEY_FROM_APP_PROPERTIES 1 + +// Enable secure boot +// Default: 0 +// Enforce signature verification on the application image in internal flash before every boot. +#define BOOTLOADER_ENFORCE_SECURE_BOOT 0 + +// Prevent write/erase of verified application +// Default: 0 +// Lock the application area in flash after the signature verification is passed. This option is only valid if secure boot is +// enabled. If end address of the signature does not touch a page boundary, the remaining flash memory in the page becomes unavailable. +#define APPLICATION_WRITE_DISABLE 0 + +// Enable application rollback protection +// Default: 0 +// Prevent applications from being downgraded. The application version can remain the same for upgrades. The +// bootloader will only allow applications to increment its version x times. Bootloader can be upgraded thenceforth +// to allow applications to increment its version again. This option is not applicable on the devices with Secure +// Element configured to perform full page lock. +#define BOOTLOADER_ROLLBACK_PROTECTION 0 + +// Minimum application version allowed +// Default: 0 +// The minimum version of the applications allowed for boot and upgrade. Prevent applications from being downgraded +// to the version below this. +#define BOOTLOADER_ROLLBACK_PROTECTION_MINIMUM_VERSION 0 +// + +// Enable certificate support +// Default: 0 +// Enforce signature verification on the application image using the certificate of the bootloader image. +// To utilize certificate secure boot authentication, secure Element should be configured to authenticate +// the bootloader image by configuring (certificate based) secure boot option in Secure Element OTP. This +// option will also allow certificate based authentication of the GBL files. +#define BOOTLOADER_SUPPORT_CERTIFICATES 0 + +// Reject direct signed images +// Default: 0 +// On every boot, look for a certificate on application images and only accept the application images with a certificate. +#define BOOTLOADER_REJECT_DIRECT_SIGNED_IMG 0 +// + +// + +// Prevent bootloader write/erase +// Default: 0 +// Write lock bootloader area before entering application. The bootloader area in flash will be locked until the next reboot. +// This does not affect bootloader upgrades, but prevents the application running in main flash from disturbing the bootloader. +// On Series-1 devices this is only applicable to devices that use the bootloader area of flash (EFR32xG12 and later). +#define BOOTLOADER_WRITE_DISABLE 0 + +// Base address of bootloader upgrade image +// Default: 0x8000 +// At the upgrade stage of the bootloader, the running main bootloader extracts the upgrade image from the GBL file, +// and stores it in internal flash at the address chosen. The address need to be a multiple of the page size. +#define BTL_UPGRADE_LOCATION_BASE 0x18000UL + +// Bootloader Version Main Customer +// Default: 0 +// Bootloader Version Main Customer +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 + +// Use custom Bootloader Application Size +// Default: 0 +#define USE_CUSTOM_APP_SIZE 0 + +// Enter Bootloader App Space Size +// Default: 0 +// Bootloader App Space Size +#define CUSTOM_BTL_APP_SPACE_SIZE 0 +// + +#if USE_CUSTOM_APP_SIZE +#define BTL_APP_SPACE_SIZE CUSTOM_BTL_APP_SPACE_SIZE +#else +#define BTL_APP_SPACE_SIZE (FLASH_BASE + FLASH_SIZE) - BTL_APPLICATION_BASE +#endif + +// + +// <<< end of configuration section >>> + +#endif // BTL_CORE_S_CONFIG_H diff --git a/platform/bootloader/config/s2/device_sdid_205/btl_core_cfg.h b/platform/bootloader/config/s2/device_sdid_205/btl_core_cfg.h index e1f60e56d0..f758196781 100644 --- a/platform/bootloader/config/s2/device_sdid_205/btl_core_cfg.h +++ b/platform/bootloader/config/s2/device_sdid_205/btl_core_cfg.h @@ -114,7 +114,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 0 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 // Use custom Bootloader Application Size // Default: 0 diff --git a/platform/bootloader/config/s2/device_sdid_205/btl_core_s_cfg.h b/platform/bootloader/config/s2/device_sdid_205/btl_core_s_cfg.h index a1a8d3337a..94f384973d 100644 --- a/platform/bootloader/config/s2/device_sdid_205/btl_core_s_cfg.h +++ b/platform/bootloader/config/s2/device_sdid_205/btl_core_s_cfg.h @@ -93,7 +93,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 0 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 // Use custom Bootloader Application Size // Default: 0 diff --git a/platform/bootloader/config/s2/device_series_2/apploader/btl_core_cfg.h b/platform/bootloader/config/s2/device_series_2/apploader/btl_core_cfg.h index 18863d51d2..774d3782f8 100644 --- a/platform/bootloader/config/s2/device_series_2/apploader/btl_core_cfg.h +++ b/platform/bootloader/config/s2/device_series_2/apploader/btl_core_cfg.h @@ -14,8 +14,8 @@ * sections of the MSLA applicable to Source Code. * ******************************************************************************/ -#ifndef BTL_CORE_APPLOADER_CONFIG_H -#define BTL_CORE_APPLOADER_CONFIG_H +#ifndef BTL_CORE_CONFIG_H +#define BTL_CORE_CONFIG_H // <<< Use Configuration Wizard in Context Menu >>> // Bootloader Core Configuration @@ -103,7 +103,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 0 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 // Use custom Bootloader Application Size // Default: 0 @@ -125,4 +125,4 @@ // <<< end of configuration section >>> -#endif // BTL_CORE_APPLOADER_CONFIG_H +#endif // BTL_CORE_CONFIG_H diff --git a/platform/bootloader/config/s2/device_series_2/apploader/btl_core_s_cfg.h b/platform/bootloader/config/s2/device_series_2/apploader/btl_core_s_cfg.h new file mode 100644 index 0000000000..9a8c57087e --- /dev/null +++ b/platform/bootloader/config/s2/device_series_2/apploader/btl_core_s_cfg.h @@ -0,0 +1,123 @@ +/***************************************************************************//** + * @file + * @brief Configuration header of Bootloader Core for Series 2 devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_CORE_S_CONFIG_H +#define BTL_CORE_S_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> +// Bootloader Core Configuration + +// Require signed firmware upgrade files +// Default: 0 +// Require that firmware upgrade files are authenticated using asymmetric signature verification. +#define BOOTLOADER_ENFORCE_SIGNED_UPGRADE 0 + +// Require encrypted firmware upgrade files +// Default: 0 +// Require that firmware upgrade files are encrypted. +#define BOOTLOADER_ENFORCE_ENCRYPTED_UPGRADE 0 + +// Use symmetric key stored in Secure Element storage +// Default: 0 +// Use the symmetric key stored in Secure Element storage for encryption and decryption. +#define BOOTLOADER_USE_SYMMETRIC_KEY_FROM_SE_STORAGE 0 + +// Use symmetric key stored in Application Properties Struct +// Default: 0 +// Use the symmetric key stored in Application Properties Struct for encryption and decryption. +#define BOOTLOADER_USE_SYMMETRIC_KEY_FROM_APP_PROPERTIES 1 + +// Enable secure boot +// Default: 0 +// Enforce signature verification on the application image in internal flash before every boot. +#define BOOTLOADER_ENFORCE_SECURE_BOOT 0 + +// Prevent write/erase of verified application +// Default: 0 +// Lock the application area in flash after the signature verification is passed. This option is only valid if secure boot is +// enabled. If end address of the signature does not touch a page boundary, the remaining flash memory in the page becomes unavailable. +#define APPLICATION_WRITE_DISABLE 0 + +// Enable application rollback protection +// Default: 0 +// Prevent applications from being downgraded. The application version can remain the same for upgrades. The +// bootloader will only allow applications to increment its version x times. Bootloader can be upgraded thenceforth +// to allow applications to increment its version again. This option is not applicable on the devices with Secure +// Element configured to perform full page lock. +#define BOOTLOADER_ROLLBACK_PROTECTION 0 + +// Minimum application version allowed +// Default: 0 +// The minimum version of the applications allowed for boot and upgrade. Prevent applications from being downgraded +// to the version below this. +#define BOOTLOADER_ROLLBACK_PROTECTION_MINIMUM_VERSION 0 +// + +// Enable certificate support +// Default: 0 +// Enforce signature verification on the application image using the certificate of the bootloader image. +// To utilize certificate secure boot authentication, secure Element should be configured to authenticate +// the bootloader image by configuring (certificate based) secure boot option in Secure Element OTP. This +// option will also allow certificate based authentication of the GBL files. +#define BOOTLOADER_SUPPORT_CERTIFICATES 0 + +// Reject direct signed images +// Default: 0 +// On every boot, look for a certificate on application images and only accept the application images with a certificate. +#define BOOTLOADER_REJECT_DIRECT_SIGNED_IMG 0 +// + +// + +// Prevent bootloader write/erase +// Default: 0 +// Write lock bootloader area before entering application. The bootloader area in flash will be locked until the next reboot. +// This does not affect bootloader upgrades, but prevents the application running in main flash from disturbing the bootloader. +// On Series-1 devices this is only applicable to devices that use the bootloader area of flash (EFR32xG12 and later). +#define BOOTLOADER_WRITE_DISABLE 0 + +// Base address of bootloader upgrade image +// Default: 0x8000 +// At the upgrade stage of the bootloader, the running main bootloader extracts the upgrade image from the GBL file, +// and stores it in internal flash at the address chosen. The address need to be a multiple of the page size. +#define BTL_UPGRADE_LOCATION_BASE 0x18000UL + +// Bootloader Version Main Customer +// Default: 0 +// Bootloader Version Main Customer +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 + +// Use custom Bootloader Application Size +// Default: 0 +#define USE_CUSTOM_APP_SIZE 0 + +// Enter Bootloader App Space Size +// Default: 0 +// Bootloader App Space Size +#define CUSTOM_BTL_APP_SPACE_SIZE 0 +// + +#if USE_CUSTOM_APP_SIZE +#define BTL_APP_SPACE_SIZE CUSTOM_BTL_APP_SPACE_SIZE +#else +#define BTL_APP_SPACE_SIZE (FLASH_BASE + FLASH_SIZE) - BTL_APPLICATION_BASE +#endif + +// + +// <<< end of configuration section >>> + +#endif // BTL_CORE_S_CONFIG_H diff --git a/platform/bootloader/config/s2/device_series_2/btl_core_cfg.h b/platform/bootloader/config/s2/device_series_2/btl_core_cfg.h index a92a79ff9c..ec055bfc46 100644 --- a/platform/bootloader/config/s2/device_series_2/btl_core_cfg.h +++ b/platform/bootloader/config/s2/device_series_2/btl_core_cfg.h @@ -114,7 +114,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 0 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 // Use custom Bootloader Application Size // Default: 0 diff --git a/platform/bootloader/config/s2/device_series_2/btl_core_s_cfg.h b/platform/bootloader/config/s2/device_series_2/btl_core_s_cfg.h index a9274e7867..e1964c93d0 100644 --- a/platform/bootloader/config/s2/device_series_2/btl_core_s_cfg.h +++ b/platform/bootloader/config/s2/device_series_2/btl_core_s_cfg.h @@ -98,7 +98,7 @@ // Bootloader Version Main Customer // Default: 0 // Bootloader Version Main Customer -#define BOOTLOADER_VERSION_MAIN_CUSTOMER 0 +#define BOOTLOADER_VERSION_MAIN_CUSTOMER 1 // Use custom Bootloader Application Size // Default: 0 diff --git a/platform/bootloader/config/sl_trustzone_secure_config.h b/platform/bootloader/config/sl_trustzone_secure_config.h new file mode 100644 index 0000000000..289ba07656 --- /dev/null +++ b/platform/bootloader/config/sl_trustzone_secure_config.h @@ -0,0 +1,38 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs TrustZone configuration of peripheral secure attributes. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_TRUSTZONE_SECURE_CONFIG_H +#define SL_TRUSTZONE_SECURE_CONFIG_H + +#define SL_TRUSTZONE_PERIPHERAL_CMU_S (0) + +#define SL_TRUSTZONE_PERIPHERAL_GPIO_S (0) + +#endif // SL_TRUSTZONE_SECURE_CONFIG_H diff --git a/platform/bootloader/core/btl_bootload.c b/platform/bootloader/core/btl_bootload.c index cf5298b379..c048fa9553 100644 --- a/platform/bootloader/core/btl_bootload.c +++ b/platform/bootloader/core/btl_bootload.c @@ -343,13 +343,21 @@ SL_WEAK void bootload_bootloaderCallback(uint32_t offset, // OOB checks // i) if NOT (BTL_UPGRADE_LOCATION <= address < max_address), // with integer overflow check for address + // Skip offset > (uint32_t) (UINT32_MAX - BTL_UPGRADE_LOCATION) + // if BTL_UPGRADE_LOCATION is zero + #if (BTL_UPGRADE_LOCATION != 0UL) if ((offset > (uint32_t) (UINT32_MAX - BTL_UPGRADE_LOCATION)) - || (address >= max_address)) { + || (address >= max_address)) + #else + if (address >= max_address) + #endif + { BTL_DEBUG_PRINT("OOB, address not in allowed range; (address) 0x"); BTL_DEBUG_PRINT_WORD_HEX(address); BTL_DEBUG_PRINT_LF(); return; } + // ii) Semantically equivalent to (address + length > max_address), // but without the risk of integer overflow (or underflow, because of (i)) if (length > (uint32_t) (max_address - address)) { @@ -778,6 +786,12 @@ SL_WEAK bool bootload_commitBootloaderUpgrade(uint32_t upgradeAddress, uint32_t return false; } +#if defined(_SILICON_LABS_32B_SERIES_2) + // The CRC32 checksum has been appended to the image and it has already been checked above + // so just disregard it. This give us the correct image size. + size = size - 4u; +#endif + #if defined(SEMAILBOX_PRESENT) #if defined(_CMU_CLKEN1_SEMAILBOXHOST_MASK) CMU->CLKEN1_SET = CMU_CLKEN1_SEMAILBOXHOST; diff --git a/platform/bootloader/core/btl_bootload_ns.c b/platform/bootloader/core/btl_bootload_ns.c index 3cac9f78e0..2c2142b284 100644 --- a/platform/bootloader/core/btl_bootload_ns.c +++ b/platform/bootloader/core/btl_bootload_ns.c @@ -27,6 +27,7 @@ extern bool bootload_nsc_checkSeUpgradeVersion(uint32_t upgradeVersion); extern bool bootload_nsc_commitSeUpgrade(void); extern bool bootload_nsc_commitBootloaderUpgrade(uint32_t size); extern uint32_t bootload_nsc_getBootloaderVersion(void); +extern bool bootload_nsc_getApplicationVersion(uint32_t *version); // ----------------------------------------------------------------------------- // NS functions @@ -52,3 +53,8 @@ uint32_t bootload_getBootloaderVersion(void) { return bootload_nsc_getBootloaderVersion(); } + +bool bootload_getApplicationVersion(uint32_t *version) +{ + return bootload_nsc_getApplicationVersion(version); +} diff --git a/platform/bootloader/core/btl_bootload_ns.h b/platform/bootloader/core/btl_bootload_ns.h index 505e5a47f7..cdd69ec5b7 100644 --- a/platform/bootloader/core/btl_bootload_ns.h +++ b/platform/bootloader/core/btl_bootload_ns.h @@ -43,6 +43,8 @@ bool bootload_commitSeUpgrade(void); bool bootload_commitBootloaderUpgrade(uint32_t size); // Get the version of the bootloader. uint32_t bootload_getBootloaderVersion(void); +// Get the version of the application. +bool bootload_getApplicationVersion(uint32_t *version); /** @endcond */ diff --git a/platform/bootloader/core/btl_bootload_veneers.c b/platform/bootloader/core/btl_bootload_veneers.c index 8cecadbeaa..5afa9f577b 100644 --- a/platform/bootloader/core/btl_bootload_veneers.c +++ b/platform/bootloader/core/btl_bootload_veneers.c @@ -50,3 +50,9 @@ uint32_t bootload_nsc_getBootloaderVersion(void) { return bootload_getBootloaderVersion(); } + +__attribute__((cmse_nonsecure_entry)) +bool bootload_nsc_getApplicationVersion(uint32_t *version) +{ + return bootload_getApplicationVersion(version); +} diff --git a/platform/bootloader/core/btl_main_s.c b/platform/bootloader/core/btl_main_s.c index f0355e824b..c5701fe326 100644 --- a/platform/bootloader/core/btl_main_s.c +++ b/platform/bootloader/core/btl_main_s.c @@ -26,6 +26,10 @@ #include "debug/btl_debug.h" +#if defined(BOOTLOADER_APPLOADER) +#include "sl_device_init_clocks.h" +#endif + #ifdef BTL_GPIO_ACTIVATION #include "gpio/gpio-activation/btl_gpio_activation.h" #endif @@ -42,6 +46,8 @@ // ----------------------------------------------------------------------------- // Defines +#define INFINITE_LOOP() while (1) {} + #if defined(__GNUC__) #define ROM_END_SIZE 0 extern const size_t __rom_end__; @@ -66,7 +72,9 @@ extern void memory_boundary_test(void); __STATIC_INLINE bool enterBootloader(void); SL_NORETURN static void bootToApp(uint32_t); +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) static void btl_getPeripheralList(uint32_t *ppusatd0, uint32_t *ppusatd1); +#endif __STATIC_INLINE void lockBootloaderArea(void); // ----------------------------------------------------------------------------- @@ -188,36 +196,200 @@ const ApplicationProperties_t sl_app_properties = { void MemManage_Handler(void) { + #if defined(DEBUG_EFM) + INFINITE_LOOP(); + #else reset_resetWithReason(BOOTLOADER_RESET_REASON_FATAL); + #endif } void HardFault_Handler(void) { + #if defined(DEBUG_EFM) + INFINITE_LOOP(); + #else reset_resetWithReason(BOOTLOADER_RESET_REASON_FATAL); + #endif } #if defined(SCB_SHCSR_USGFAULTENA_Msk) void UsageFault_Handler(void) { + #if defined(DEBUG_EFM) + INFINITE_LOOP(); + #else reset_resetWithReason(BOOTLOADER_RESET_REASON_FATAL); + #endif } #endif #if defined(SCB_SHCSR_BUSFAULTENA_Msk) void BusFault_Handler(void) { + #if defined(DEBUG_EFM) + INFINITE_LOOP(); + #else reset_resetWithReason(BOOTLOADER_RESET_REASON_FATAL); + #endif } #endif void SMU_SECURE_IRQHandler(void) { + #if defined(DEBUG_EFM) + INFINITE_LOOP(); + #else reset_resetWithReason(BOOTLOADER_RESET_REASON_TZ_FAULT); + #endif } void SecureFault_Handler(void) { + #if defined(DEBUG_EFM) + INFINITE_LOOP(); + #else reset_resetWithReason(BOOTLOADER_RESET_REASON_TZ_FAULT); + #endif +} + +#if defined(BOOTLOADER_APPLOADER) +/**************************************************************************//** + * @brief Configures secure state of bus masters using the SMU. + * + * This function is device dependent. Assumes that the SMU is clocked. + *****************************************************************************/ +static inline void smu_configure_bus_masters(void) +{ + // Configure all bus-masters as secure except for the RADIOSUBSYSTEM. + SMU->BMPUSATD0_CLR = SMU_BMPUSATD0_RADIOSUBSYSTEM; +} +#endif // BOOTLOADER_APPLOADER + +#if defined(BOOTLOADER_APPLOADER) +/**************************************************************************//** + * @brief Configures secure attributes of peripherals using the SMU. + * + * This function is device dependent. Assumes that the SMU is clocked. + *****************************************************************************/ +static inline void smu_configure_peripherals(void) +{ + #if defined(SEMAILBOX_PRESENT) + SMU->PPUSATD0_CLR = _SMU_PPUSATD0_MASK + & ~(SMU_PPUSATD0_SYSCFG + | SMU_PPUSATD0_MSC + | SMU_PPUSATD0_GPCRC + | SMU_PPUSATD0_LDMA + | SMU_PPUSATD0_LDMAXBAR); + SMU->PPUSATD1_CLR = _SMU_PPUSATD1_MASK + & ~(SMU_PPUSATD1_SMU + | SMU_PPUSATD1_SEMAILBOX); + #elif defined(CRYPTOACC_PRESENT) + SMU->PPUSATD0_CLR = _SMU_PPUSATD0_MASK + & ~(SMU_PPUSATD0_SYSCFG + | SMU_PPUSATD0_MSC + | SMU_PPUSATD0_GPCRC + | SMU_PPUSATD0_LDMA + | SMU_PPUSATD0_LDMAXBAR); + SMU->PPUSATD1_CLR = _SMU_PPUSATD1_MASK + & ~(SMU_PPUSATD1_SMU + | SMU_PPUSATD1_CRYPTOACC); + #endif +} +#endif // BOOTLOADER_APPLOADER + +#if defined(BOOTLOADER_APPLOADER) +/**************************************************************************//** + * @brief Configure interrupt target states. + * + * Interrupts must either point at the secure or non-secure world. After reset + * everything points to the secure world, and this function redirects all + * intterupts to non-secure to better support existing applications. + *****************************************************************************/ +static inline void configure_interrupt_target_states(void) +{ + // Start by setting all Interrupt Non-Secure State (ITNS) bits. This results + // in all IRQs being targeted at the NS world. + for (size_t i = 0; i < sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0]); i++) { + NVIC->ITNS[i] = 0xFFFFFFFF; + } + + // Clear the ITNS bits corresponding to all IRQs belonging to S peripherals. + #if defined(SEMAILBOX_PRESENT) + NVIC_ClearTargetState(SEMBRX_IRQn); + NVIC_ClearTargetState(SEMBTX_IRQn); + NVIC_ClearTargetState(SMU_SECURE_IRQn); + #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + NVIC_ClearTargetState(SMU_PRIVILEGED_IRQn); + #else + NVIC_ClearTargetState(SMU_S_PRIVILEGED_IRQn); + #endif + NVIC_ClearTargetState(LDMA_IRQn); + NVIC_ClearTargetState(SYSCFG_IRQn); + NVIC_ClearTargetState(MSC_IRQn); + #elif defined(CRYPTOACC_PRESENT) + NVIC_ClearTargetState(CRYPTOACC_IRQn); + NVIC_ClearTargetState(TRNG_IRQn); + NVIC_ClearTargetState(PKE_IRQn); + NVIC_ClearTargetState(SMU_SECURE_IRQn); + NVIC_ClearTargetState(SMU_S_PRIVILEGED_IRQn); + NVIC_ClearTargetState(LDMA_IRQn); + NVIC_ClearTargetState(SYSCFG_IRQn); + NVIC_ClearTargetState(MSC_IRQn); + #endif +} +#endif // BOOTLOADER_APPLOADER + +/**************************************************************************//** + * @brief Enable SMU security fault interrupts. + * + * Assumes that the SMU is clocked. + *****************************************************************************/ +static inline void smu_enable_security_fault_interrupts(void) +{ + NVIC_ClearPendingIRQ(SMU_SECURE_IRQn); + SMU->IF_CLR = SMU_IF_PPUSEC | SMU_IF_BMPUSEC; + NVIC_EnableIRQ(SMU_SECURE_IRQn); + SMU->IEN = SMU_IEN_PPUSEC | SMU_IEN_BMPUSEC; +} + +/**************************************************************************//** + * @brief Enables SecureFault, BusFault, UsageFault, and MemFault system + * exceptions. + *****************************************************************************/ +static inline void enable_fault_exceptions(void) +{ + // Enable SecureFault, BusFault, UsageFault and MemFault. + SCB->SHCSR |= SCB_SHCSR_SECUREFAULTENA_Msk + | SCB_SHCSR_BUSFAULTENA_Msk + | SCB_SHCSR_USGFAULTENA_Msk + | SCB_SHCSR_MEMFAULTENA_Msk; +} + +/**************************************************************************//** + * @brief Enable the FPU for the non-secure app. + *****************************************************************************/ +static inline void enable_ns_fpu(void) +{ + SCB->NSACR |= (SCB_NSACR_CP10_Msk) // enable CP10 Full Access + | (SCB_NSACR_CP11_Msk); // enable CP11 Full Access +} + +/**************************************************************************//** + * @brief Prioritize the secure exceptions + * + * Modify the relative priorities of Secure and Non-secure interrupts, + * so that the priority range for Secure interrupts extends to higher + * priorities than the range for Non-secure interrupts. + *****************************************************************************/ +static inline void prioritise_secure_exceptions(void) +{ + #define AIRCR_UNLOCK_VECTKEY 0x5FAUL + + uint32_t scb_AIRCR = SCB->AIRCR; + uint32_t scb_vectkey = AIRCR_UNLOCK_VECTKEY; + SCB->AIRCR = SCB_AIRCR_PRIS_Msk + | (scb_vectkey << SCB_AIRCR_VECTKEY_Pos) + | (scb_AIRCR & ~SCB_AIRCR_VECTKEY_Msk); } /**************************************************************************//** @@ -284,17 +456,12 @@ static void setup_mpu(void) * @brief Setup TrustZone boundaries * * Sets up the static isolation boundaries which are constant throughout - * the runtime of the system. + * the runtime of the system. Assumes that the SMU is clocked. *****************************************************************************/ static void setup_static_boundaries(void) { -#if defined(CMU_CLKEN1_SMU) - CMU->CLKEN1_SET = CMU_CLKEN1_SMU; -#endif - // Memory map configuration // Uses the SMU to split flash into S/NSC/NS, and RAM into S/NS. - SMU->LOCK = SMU_LOCK_SMULOCKKEY_UNLOCK; // Flash configuration @@ -309,53 +476,51 @@ static void setup_static_boundaries(void) // NSC - NS boundary SMU->ESAUMRB56 = (SRAM_BASE + NS_RAM_OFFSET) & _SMU_ESAUMRB56_MASK; - // Security fault interrupt - SMU->IF_CLR = SMU_IF_PPUSEC | SMU_IF_BMPUSEC; - SMU->IEN_SET = SMU_IEN_BMPUSEC; - SMU->IEN_SET = SMU_IEN_PPUSEC; - NVIC_ClearPendingIRQ(SMU_SECURE_IRQn); - NVIC_EnableIRQ(SMU_SECURE_IRQn); +#if defined(BOOTLOADER_APPLOADER) + // Make the info page NS. + SMU->ESAURTYPES0 = SMU_ESAURTYPES0_ESAUR3NS; +#endif // Lock SMU config SMU->LOCK = 0; - SAU->RNR = 0; // NS + SAU->RNR = 0; // Flash SAU->RBAR = ((uint32_t)&linker_sg_begin) & SAU_RBAR_BADDR_Msk; SAU->RLAR = ((BTL_APPLICATION_BASE - 1u) & SAU_RLAR_LADDR_Msk) + | (0 << SAU_RLAR_NSC_Pos) | SAU_RLAR_ENABLE_Msk; - SAU->RNR = 1; // NS + SAU->RNR = 1; // NS Peripherals SAU->RBAR = PERIPHERALS_BASE_NS_START & SAU_RBAR_BADDR_Msk; SAU->RLAR = ((PERIPHERALS_BASE_NS_END) &SAU_RLAR_LADDR_Msk) + | (0 << SAU_RLAR_NSC_Pos) | SAU_RLAR_ENABLE_Msk; - SAU->RNR = 2; // NS + SAU->RNR = 2; // SRAM SAU->RBAR = (SRAM_BASE + NS_RAM_OFFSET) & SAU_RBAR_BADDR_Msk; SAU->RLAR = ((SRAM_BASE + SRAM_SIZE - 1u) & SAU_RLAR_LADDR_Msk) + | (0 << SAU_RLAR_NSC_Pos) + | SAU_RLAR_ENABLE_Msk; +#if defined(BOOTLOADER_APPLOADER) + SAU->RNR = 3; // User Data + SAU->RBAR = MSC_FLASH_USERDATA_MEM_BASE & SAU_RBAR_BADDR_Msk; + SAU->RLAR = (MSC_FLASH_USERDATA_MEM_END & SAU_RLAR_LADDR_Msk) + | (0 << SAU_RLAR_NSC_Pos) + | SAU_RLAR_ENABLE_Msk; + SAU->RNR = 4; // Device Info + SAU->RBAR = MSC_FLASH_DEVINFO_MEM_BASE & SAU_RBAR_BADDR_Msk; + SAU->RLAR = (MSC_FLASH_DEVINFO_MEM_END & SAU_RLAR_LADDR_Msk) + | (0 << SAU_RLAR_NSC_Pos) | SAU_RLAR_ENABLE_Msk; + SAU->RNR = 5; // Chip Config + SAU->RBAR = MSC_FLASH_CHIPCONFIG_MEM_BASE & SAU_RBAR_BADDR_Msk; + SAU->RLAR = (MSC_FLASH_CHIPCONFIG_MEM_END & SAU_RLAR_LADDR_Msk) + | (0 << SAU_RLAR_NSC_Pos) + | SAU_RLAR_ENABLE_Msk; +#endif // BOOTLOADER_APPLOADER TZ_SAU_Enable(); __DSB(); __ISB(); - // Enables BUS, MEM, USG and Secure faults - // Enable BusFault, UsageFault and MemFault - SCB->SHCSR |= 0x0 -#if defined(SCB_SHCSR_SECUREFAULTENA_Msk) - | SCB_SHCSR_SECUREFAULTENA_Msk -#endif -#if defined(SCB_SHCSR_BUSFAULTENA_Msk) - | SCB_SHCSR_BUSFAULTENA_Msk -#endif -#if defined(SCB_SHCSR_USGFAULTENA_Msk) - | SCB_SHCSR_USGFAULTENA_Msk -#endif -#if defined(SCB_SHCSR_MEMFAULTENA_Msk) - | SCB_SHCSR_MEMFAULTENA_Msk -#endif - ; - - // Enable FPU for non-secure code - SCB->NSACR |= ( (SCB_NSACR_CP10_Msk) // enable CP10 Full Access - | (SCB_NSACR_CP11_Msk) ); // enable CP11 Full Access - lockBootloaderArea(); + enable_ns_fpu(); setup_mpu(); #if defined(TEST_BOOTLOADER_MEMORY_BOUNDARY) memory_boundary_test(); @@ -572,8 +737,19 @@ void SystemInit2(void) int main(void) { CHIP_Init(); +#if defined(BOOTLOADER_APPLOADER) + sl_device_init_clocks(); +#endif BTL_DEBUG_PRINTLN("BTL entry"); +#if defined(CMU_CLKEN1_SMU) + CMU->CLKEN1_SET = CMU_CLKEN1_SMU; +#endif + + enable_fault_exceptions(); + prioritise_secure_exceptions(); + smu_enable_security_fault_interrupts(); + #if defined(EMU_CMD_EM01VSCALE2) && defined(EMU_STATUS_VSCALEBUSY) // Device supports voltage scaling, and the bootloader may have been entered // with a downscaled voltage. Scale voltage up to allow flash programming. @@ -584,9 +760,30 @@ int main(void) } } #endif +#if defined(BOOTLOADER_APPLOADER) + // Only redirect the interrupts to non-secure for the AppLoader usecase. + // All the interrupts can be owned by the secure code for all the other bootloader + // sample apps. + configure_interrupt_target_states(); + // All the peripherals as well as the busmasters are considered secure for all the + // bootloader sample apps except for the AppLoader. + smu_configure_peripherals(); + smu_configure_bus_masters(); +#endif // BOOTLOADER_APPLOADER + setup_static_boundaries(); + + // Lock the whole bootloader flash unconditionally + lockBootloaderArea(); + +#if defined(CMU_CLKEN1_SMU) +#if defined(BOOTLOADER_APPLOADER) + CMU_NS->CLKEN1_CLR = CMU_CLKEN1_SMU; +#else + CMU->CLKEN1_CLR = CMU_CLKEN1_SMU; +#endif // BOOTLOADER_APPLOADER +#endif // CMU_CLKEN1_SMU btl_init(); - setup_static_boundaries(); jump_to_ns(); // Should never reach this point diff --git a/platform/bootloader/core/btl_util.h b/platform/bootloader/core/btl_util.h index c5c7fe3111..1a400e3861 100644 --- a/platform/bootloader/core/btl_util.h +++ b/platform/bootloader/core/btl_util.h @@ -1,6 +1,9 @@ #ifndef BTL_UTIL_H #define BTL_UTIL_H +#define BTL_STR_HELPER(x) #x +#define QUOTE(x) BTL_STR_HELPER(x) + #if defined(__CSTAT__) #define MISRAC_DISABLE _Pragma( \ "cstat_disable= \ diff --git a/platform/bootloader/esf.properties b/platform/bootloader/esf.properties index e93adfbdae..14e8a38458 100644 --- a/platform/bootloader/esf.properties +++ b/platform/bootloader/esf.properties @@ -12,7 +12,6 @@ version=2.1.0 label=Gecko Bootloader description=Gecko Bootloader for EFM32 and EFR32 devices -prop.file.appDirectory=. application/ prop.file.templatesFile=bootloader_beta_templates.xml bootloader_internal_templates.xml bootloader_production_templates.xml prop.file.docsFile=documentation/gecko_bootloader_documentation.xml prop.protocolKey=BOOTLOADER diff --git a/platform/bootloader/parser/gbl/btl_gbl_parser.c b/platform/bootloader/parser/gbl/btl_gbl_parser.c index 3dd01a4e2d..4a72a658a3 100644 --- a/platform/bootloader/parser/gbl/btl_gbl_parser.c +++ b/platform/bootloader/parser/gbl/btl_gbl_parser.c @@ -1196,8 +1196,9 @@ static int32_t parser_parseNewTagHeader(ParserContext_t *parserContext, if (PARSER_REQUIRE_AUTHENTICITY) { parserContext->internalState = GblParserStateError; return BOOTLOADER_ERROR_PARSER_UNEXPECTED; + } else { + parserContext->internalState = GblParserStateFinalize; } - parserContext->internalState = GblParserStateFinalize; break; #if defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) diff --git a/platform/bootloader/sample-apps/bootloader-apploader/bootloader-apploader-nonsecure.slcp b/platform/bootloader/sample-apps/bootloader-apploader/bootloader-apploader-nonsecure.slcp new file mode 100644 index 0000000000..1956536bb1 --- /dev/null +++ b/platform/bootloader/sample-apps/bootloader-apploader/bootloader-apploader-nonsecure.slcp @@ -0,0 +1,29 @@ +project_name: bootloader-apploader-nonsecure +package: bootloader +quality: beta +label: Bootloader - SoC Bluetooth AppLoader OTA DFU Non-Secure part of Bootloader using TrustZone +description: > + TrustZone is used to split into a Secure and Non-Secure bootloader. This is the non-secure part of the bootloader. The secure part of the bootloader, which contains the core functionalities needs to be built separately and used together with the non-secure part of the bootloader. + +category: Example|Bootloader +filter: + - name: "Device Type" + value: ["SoC"] + - name: "Project Difficulty" + value: ["Advanced"] + - name: "MCU" + value: ["Bootloader"] + + +component: + - id: bootloader_core_nonsecure + - id: bootloader_apploader_nonsecure + - id: bootloader_image_parser_nonsecure + - id: bootloader_include_parser_nonsecure + +readme: + - path: readme.md +ui_hints: + highlight: readme.md +tag: + - "companion:bootloader-apploader-secure.slcp" \ No newline at end of file diff --git a/platform/bootloader/sample-apps/bootloader-apploader/bootloader-apploader-secure.slcp b/platform/bootloader/sample-apps/bootloader-apploader/bootloader-apploader-secure.slcp new file mode 100644 index 0000000000..e9ff3b52d9 --- /dev/null +++ b/platform/bootloader/sample-apps/bootloader-apploader/bootloader-apploader-secure.slcp @@ -0,0 +1,35 @@ +project_name: bootloader-apploader-secure +package: bootloader +quality: beta +label: Bootloader - SoC Bluetooth AppLoader OTA DFU Secure part of Bootloader using TrustZone +description: > + TrustZone is used to split into a Secure and Non-Secure bootloader. This is the secure part of the bootloader. The non-secure part of the bootloader, which contains the communication interfaces needs to be built separately and used together with the secure part of the bootloader. + +category: Example|Bootloader +filter: + - name: "Device Type" + value: ["SoC"] + - name: "Project Difficulty" + value: ["Advanced"] + - name: "MCU" + value: ["Bootloader"] + +component: + - id: bootloader_core_secure + - id: bootloader_image_parser + - id: bootloader_apploader_secure + - id: bootloader_debug + - id: bootloader_tz_secure_config + +configuration: + - name: SL_VCOM_ENABLE + value: 1 + +define: + - name: BOOTLOADER_SUPPORT_COMMUNICATION + value: 1 + +readme: + - path: readme.md +ui_hints: + highlight: readme.md \ No newline at end of file diff --git a/platform/bootloader/sample-apps/bootloader-apploader/bootloader-apploader.slcp b/platform/bootloader/sample-apps/bootloader-apploader/bootloader-apploader.slcp index 4c8fa2377e..0ff9887303 100644 --- a/platform/bootloader/sample-apps/bootloader-apploader/bootloader-apploader.slcp +++ b/platform/bootloader/sample-apps/bootloader-apploader/bootloader-apploader.slcp @@ -18,11 +18,7 @@ filter: component: - id: bootloader_core - id: bootloader_apploader - - id: bootloader_crc - - id: bootloader_aes_sha_ecdsa - - id: bootloader_delay_driver - id: bootloader_image_parser - - id: bootloader_token_management - id: bootloader_debug readme: diff --git a/platform/bootloader/storage/internal_flash/btl_storage_internal_flash.c b/platform/bootloader/storage/internal_flash/btl_storage_internal_flash.c index 88b3cd5e1f..9dcadca45d 100644 --- a/platform/bootloader/storage/internal_flash/btl_storage_internal_flash.c +++ b/platform/bootloader/storage/internal_flash/btl_storage_internal_flash.c @@ -146,12 +146,16 @@ int32_t storage_writeRaw(uint32_t address, uint8_t *data, size_t numBytes) if (!verifyErased(address, numBytes)) { return BOOTLOADER_ERROR_STORAGE_NEEDS_ERASE; } - //Ensure that numBytes is a multiple of 4 - if (numBytes & 3U) { - return BOOTLOADER_ERROR_STORAGE_NEEDS_ALIGN; - } + #if (BOOTLOADER_MSC_DMA_WRITE == 1) - if (flash_writeBuffer_dma(address, data, numBytes, BOOTLOADER_MSC_DMA_CHANNEL)) { + if ((uint32_t) data & 3UL) { + //Data address not aligned. Use normal write. + if (flash_writeBuffer(address, data, numBytes)) { + return BOOTLOADER_OK; + } else { + return BOOTLOADER_ERROR_STORAGE_INVALID_ADDRESS; + } + } else if (flash_writeBuffer_dma(address, data, numBytes, BOOTLOADER_MSC_DMA_CHANNEL)) { return BOOTLOADER_OK; } #else diff --git a/platform/common/inc/sl_common.h b/platform/common/inc/sl_common.h index a34b044242..ed0ff57f00 100644 --- a/platform/common/inc/sl_common.h +++ b/platform/common/inc/sl_common.h @@ -263,7 +263,7 @@ extern "C" { ******************************************************************************/ __STATIC_INLINE uint32_t SL_CTZ(uint32_t value) { -#if (__CORTEX_M >= 3) +#if defined(__CORTEX_M) && (__CORTEX_M >= 3U) return __CLZ(__RBIT(value)); #else @@ -297,13 +297,13 @@ __STATIC_INLINE uint32_t SL_RBIT(uint32_t value) { uint32_t result; -#if (__CORTEX_M >= 0x03U) +#if defined(__CORTEX_M) && (__CORTEX_M >= 0x03U) result = __RBIT(value); #else int32_t s = 4 * 8 - 1; result = value; - for (value >>= 1U; value; value >>= 1U) { + for (value >>= 1U; value != 0U; value >>= 1U) { result <<= 1U; result |= value & 1U; s--; @@ -323,9 +323,9 @@ __STATIC_INLINE uint32_t SL_RBIT(uint32_t value) * @return * A 16-bit reversed value. ******************************************************************************/ -__STATIC_INLINE uint32_t SL_RBIT16(uint32_t value) +__STATIC_INLINE uint16_t SL_RBIT16(uint16_t value) { - return SL_RBIT(value) >> 16; + return (uint16_t)(SL_RBIT(value) >> 16); } /***************************************************************************//** diff --git a/platform/common/inc/sl_gsdk_version.h b/platform/common/inc/sl_gsdk_version.h index f78a692752..16dac84b0d 100644 --- a/platform/common/inc/sl_gsdk_version.h +++ b/platform/common/inc/sl_gsdk_version.h @@ -31,7 +31,7 @@ #define SL_GSDK_MAJOR_VERSION 4 #define SL_GSDK_MINOR_VERSION 1 -#define SL_GSDK_PATCH_VERSION 0 +#define SL_GSDK_PATCH_VERSION 1 #define SL_GSDK_VERSION ((SL_GSDK_MAJOR_VERSION << 8) \ | (SL_GSDK_MINOR_VERSION << 4) \ diff --git a/platform/common/toolchain/gcc/linkerfile.ld.jinja b/platform/common/toolchain/gcc/linkerfile.ld.jinja index bed281e92b..3da5cefc9d 100644 --- a/platform/common/toolchain/gcc/linkerfile.ld.jinja +++ b/platform/common/toolchain/gcc/linkerfile.ld.jinja @@ -320,6 +320,10 @@ SECTIONS KEEP(*(.internal_storage*)) } > FLASH + {#- + Exclude the NVM3 region for the TZ secure applications + #} + {% if trustzone_secure is not defined %} {%- if linker_zwave_nvm is defined %} .zwave_nvm (DSECT) : { KEEP(*(.zwavenvm*)) @@ -341,9 +345,13 @@ SECTIONS {%- else %} linker_storage_end = linker_nvm_begin; {%- endif %} + __nvm3Base = linker_nvm_begin; + {%- else %} {#- trustzone_secure #} + linker_storage_end = __main_flash_end__; + {%- endif %} {#- trustzone_secure #} + linker_storage_begin = linker_storage_end - SIZEOF(.internal_storage); linker_storage_size = SIZEOF(.internal_storage); - __nvm3Base = linker_nvm_begin; {%- if bootloader_enable %} _app_rollback_protection_size = 0x{{ '%0x' % (app_rollback_protection_size | sum) }}; @@ -356,10 +364,12 @@ SECTIONS ASSERT((linker_storage_begin >= (__etext + SIZEOF(.data))), "FLASH memory overflowed !") {%- endif %} +{% if trustzone_secure is not defined %} {%- if app_flash_start and app_flash_size %} app_flash_end = 0x{{ '%0x' % (app_flash_start) }} + 0x{{ '%0x' % (app_flash_size) }}; ASSERT( (linker_nvm_begin + SIZEOF(.nvm)) <= app_flash_end, "NVM3 is excessing the flash size !") {%- endif %} +{%- endif %} {#- trustzone_secure #} {%- if (memory_ram_start and not memory_ram_size) or (memory_ram_size and not memory_ram_start) %} ASSERT( 0, "memory_ram_start and memory_ram_size, Should define/undefine both!") diff --git a/platform/common/toolchain/iar/linkerfile.icf.jinja b/platform/common/toolchain/iar/linkerfile.icf.jinja index ba9f9c71c5..4be1e4ff1b 100644 --- a/platform/common/toolchain/iar/linkerfile.icf.jinja +++ b/platform/common/toolchain/iar/linkerfile.icf.jinja @@ -121,6 +121,10 @@ define block apploader with alignment = {{ flash_page_size }} keep { section .binapploader }; {%- endif %} +{#- + Exclude the NVM3 region for the TZ secure applications +#} +{% if trustzone_secure is not defined %} {%- if linker_zwave_nvm is defined %} define block zwavenvm with alignment = {{ flash_page_size }} { @@ -134,7 +138,7 @@ define block nvm with alignment = {{ flash_page_size }} section SIMEE, }; keep { block nvm }; - +{%- endif %} {#- trustzone_secure #} {%- if trustzone_secure %} define block Veneer$$CMSE with alignment = {{ 32 }} { @@ -201,10 +205,12 @@ place at start of ROM_region { block application }; "storage_regions": place at end of MAIN_FLASH_region { block storage, +{% if trustzone_secure is not defined %} {%- if linker_zwave_nvm is defined %} block zwavenvm, {%- endif %} block nvm, +{%- endif %} {#- trustzone_secure #} {%- if trustzone_secure %} block Veneer$$CMSE {%- endif %} diff --git a/platform/driver/button/inc/sl_simple_button.h b/platform/driver/button/inc/sl_simple_button.h index 058aca7c90..307156ecf5 100644 --- a/platform/driver/button/inc/sl_simple_button.h +++ b/platform/driver/button/inc/sl_simple_button.h @@ -21,6 +21,10 @@ #include "sl_button.h" #include "em_gpio.h" +#ifdef __cplusplus +extern "C" { +#endif + /***************************************************************************//** * @addtogroup button * @{ @@ -204,4 +208,8 @@ void sl_simple_button_disable(const sl_button_t *handle); /// /// @} end group simple_button ********************************************************/ +#ifdef __cplusplus +} +#endif + #endif // SL_SIMPLE_BUTTON_H diff --git a/platform/driver/coulomb/src/sli_coulomb_counter.h b/platform/driver/coulomb/src/sli_coulomb_counter.h index 159956a017..472c5399c3 100644 --- a/platform/driver/coulomb/src/sli_coulomb_counter.h +++ b/platform/driver/coulomb/src/sli_coulomb_counter.h @@ -34,6 +34,10 @@ #include "sl_coulomb_counter.h" #include "sl_slist.h" +#ifdef __cplusplus +extern "C" { +#endif + /// @cond DO_NOT_INCLUDE_WITH_DOXYGEN #define EMU_VSCALE0 0 #define EMU_VSCALE1 1 @@ -305,4 +309,8 @@ float sli_coulomb_counter_hal_cal_get_load_current(int8_t ccl_level); ******************************************************************************/ float sli_coulomb_counter_hal_get_osc_frequency(void); +#ifdef __cplusplus +} +#endif + #endif /* SLI_COULOMB_COUNTER_DRIVER_H */ diff --git a/platform/driver/cycle_counter/inc/sl_cycle_counter.h b/platform/driver/cycle_counter/inc/sl_cycle_counter.h index 23e2e0dfcd..708f6a18a0 100644 --- a/platform/driver/cycle_counter/inc/sl_cycle_counter.h +++ b/platform/driver/cycle_counter/inc/sl_cycle_counter.h @@ -37,6 +37,10 @@ #include "em_device.h" #include "sl_status.h" +#ifdef __cplusplus +extern "C" { +#endif + /***************************************************************************//** * @addtogroup cycle_counter Cycle Counter * @brief Provides an interface to the cycle counter of the DWT unit. @@ -193,4 +197,9 @@ __INLINE uint32_t sl_cycle_counter_get_counter(void) } /** @} (end group cycle_counter) */ + +#ifdef __cplusplus +} +#endif + #endif diff --git a/platform/driver/leddrv/inc/sl_pwm_led.h b/platform/driver/leddrv/inc/sl_pwm_led.h index 82b91fa5c5..8cddab2db5 100644 --- a/platform/driver/leddrv/inc/sl_pwm_led.h +++ b/platform/driver/leddrv/inc/sl_pwm_led.h @@ -21,6 +21,10 @@ #include "em_timer.h" #include "em_cmu.h" +#ifdef __cplusplus +extern "C" { +#endif + /// A Simple PWM LED typedef struct { void (*set_color)(void *context, uint16_t color); ///< Member function to set color of PWM LED @@ -85,4 +89,8 @@ void sl_pwm_led_set_color(void *led, uint16_t color); ******************************************************************************/ void sl_pwm_led_get_color(void *led, uint16_t *color); +#ifdef __cplusplus +} +#endif + #endif diff --git a/platform/driver/leddrv/inc/sl_simple_led.h b/platform/driver/leddrv/inc/sl_simple_led.h index abad0dd768..cff43b4bca 100644 --- a/platform/driver/leddrv/inc/sl_simple_led.h +++ b/platform/driver/leddrv/inc/sl_simple_led.h @@ -22,6 +22,10 @@ #include "em_gpio.h" #include +#ifdef __cplusplus +extern "C" { +#endif + /***************************************************************************//** * @addtogroup led * @{ @@ -204,4 +208,8 @@ sl_led_state_t sl_simple_led_get_state(void *led_handle); /// /// @} end group simple_led ********************************************************/ +#ifdef __cplusplus +} +#endif + #endif // SL_SIMPLE_LED_H diff --git a/platform/driver/leddrv/inc/sl_simple_rgb_pwm_led.h b/platform/driver/leddrv/inc/sl_simple_rgb_pwm_led.h index 0be8e0f2f1..78edcb7d1a 100644 --- a/platform/driver/leddrv/inc/sl_simple_rgb_pwm_led.h +++ b/platform/driver/leddrv/inc/sl_simple_rgb_pwm_led.h @@ -23,6 +23,10 @@ #include "em_gpio.h" #include +#ifdef __cplusplus +extern "C" { +#endif + /***************************************************************************//** * @addtogroup led * @{ @@ -321,4 +325,8 @@ void sl_led_get_rgb_color(const sl_led_rgb_pwm_t *rgb, ///< LED Instance hand /// /// @} end group led ********************************************************/ +#ifdef __cplusplus +} +#endif + #endif // SL_SIMPLE_RGB_PWM_LED_H diff --git a/platform/driver/leddrv/inc/sl_simple_rgbw_pwm_led.h b/platform/driver/leddrv/inc/sl_simple_rgbw_pwm_led.h index fe661a6ad6..019f355254 100644 --- a/platform/driver/leddrv/inc/sl_simple_rgbw_pwm_led.h +++ b/platform/driver/leddrv/inc/sl_simple_rgbw_pwm_led.h @@ -23,6 +23,10 @@ #include "em_gpio.h" #include +#ifdef __cplusplus +extern "C" { +#endif + /***************************************************************************//** * @addtogroup led * @{ @@ -348,4 +352,8 @@ void sl_led_get_rgbw_color(const sl_led_rgbw_pwm_t *rgbw, ///< LED Instance h /// /// @} end group led ********************************************************/ +#ifdef __cplusplus +} +#endif + #endif // SL_SIMPLE_RGBW_PWM_LED_H diff --git a/platform/driver/leddrv/inst/sl_simple_rgb_pwm_led_instances.c.jinja b/platform/driver/leddrv/inst/sl_simple_rgb_pwm_led_instances.c.jinja index 56601e30f2..3ee713e7b1 100644 --- a/platform/driver/leddrv/inst/sl_simple_rgb_pwm_led_instances.c.jinja +++ b/platform/driver/leddrv/inst/sl_simple_rgb_pwm_led_instances.c.jinja @@ -74,7 +74,7 @@ sl_simple_rgb_pwm_led_context_t simple_rgb_pwm_{{ inst | lower }}_context = { .resolution = SL_SIMPLE_RGB_PWM_LED_{{ inst | upper }}_RESOLUTION, }; -const sl_led_rgb_pwm_t sl_{{ inst | lower }} = { +const sl_led_rgb_pwm_t sl_simple_rgb_pwm_led_{{ inst | lower }} = { .led_common.context = &simple_rgb_pwm_{{ inst | lower }}_context, .led_common.init = sl_simple_rgb_pwm_led_init, .led_common.turn_on = sl_simple_rgb_pwm_led_turn_on, @@ -90,6 +90,6 @@ const sl_led_rgb_pwm_t sl_{{ inst | lower }} = { void sl_simple_rgb_pwm_led_init_instances(void) { {% for inst in simple_rgb_pwm_led_instance %} - sl_led_init((sl_led_t *)&sl_{{ inst | lower }}); + sl_led_init((sl_led_t *)&sl_simple_rgb_pwm_led_{{ inst | lower }}); {% endfor %} } diff --git a/platform/driver/leddrv/inst/sl_simple_rgb_pwm_led_instances.h.jinja b/platform/driver/leddrv/inst/sl_simple_rgb_pwm_led_instances.h.jinja index 2d0fa68ce1..55fc0fb91e 100644 --- a/platform/driver/leddrv/inst/sl_simple_rgb_pwm_led_instances.h.jinja +++ b/platform/driver/leddrv/inst/sl_simple_rgb_pwm_led_instances.h.jinja @@ -21,7 +21,7 @@ #include "sl_simple_rgb_pwm_led.h" {% for inst in simple_rgb_pwm_led_instance -%} -extern const sl_led_rgb_pwm_t sl_{{ inst | lower }}; +extern const sl_led_rgb_pwm_t sl_simple_rgb_pwm_led_{{ inst | lower }}; {% endfor %} void sl_simple_rgb_pwm_led_init_instances(void); diff --git a/platform/driver/leddrv/inst/sl_simple_rgbw_pwm_led_instances.c.jinja b/platform/driver/leddrv/inst/sl_simple_rgbw_pwm_led_instances.c.jinja index f241bef388..d1ad1b011c 100644 --- a/platform/driver/leddrv/inst/sl_simple_rgbw_pwm_led_instances.c.jinja +++ b/platform/driver/leddrv/inst/sl_simple_rgbw_pwm_led_instances.c.jinja @@ -89,7 +89,7 @@ sl_simple_rgbw_pwm_led_context_t simple_rgbw_pwm_{{ inst | lower }}_context = { .resolution = SL_SIMPLE_RGBW_PWM_LED_{{ inst | upper }}_RESOLUTION, }; -const sl_led_rgbw_pwm_t sl_{{ inst | lower }} = { +const sl_led_rgbw_pwm_t sl_simple_rgbw_pwm_led_{{ inst | lower }} = { .led_common.context = &simple_rgbw_pwm_{{ inst | lower }}_context, .led_common.init = sl_simple_rgbw_pwm_led_init, .led_common.turn_on = sl_simple_rgbw_pwm_led_turn_on, @@ -105,6 +105,6 @@ const sl_led_rgbw_pwm_t sl_{{ inst | lower }} = { void sl_simple_rgbw_pwm_led_init_instances(void) { {% for inst in simple_rgbw_pwm_led_instance %} - sl_led_init((sl_led_t *)&sl_{{ inst | lower }}); + sl_led_init((sl_led_t *)&sl_simple_rgbw_pwm_led_{{ inst | lower }}); {% endfor %} } diff --git a/platform/driver/leddrv/inst/sl_simple_rgbw_pwm_led_instances.h.jinja b/platform/driver/leddrv/inst/sl_simple_rgbw_pwm_led_instances.h.jinja index d6e98029ec..9416fcd386 100644 --- a/platform/driver/leddrv/inst/sl_simple_rgbw_pwm_led_instances.h.jinja +++ b/platform/driver/leddrv/inst/sl_simple_rgbw_pwm_led_instances.h.jinja @@ -21,7 +21,7 @@ #include "sl_simple_rgbw_pwm_led.h" {% for inst in simple_rgbw_pwm_led_instance -%} -extern const sl_led_rgbw_pwm_t sl_{{ inst | lower }}; +extern const sl_led_rgbw_pwm_t sl_simple_rgbw_pwm_led_{{ inst | lower }}; {% endfor %} void sl_simple_rgbw_pwm_led_init_instances(void); diff --git a/platform/driver/mvp/config/sl_mvp_config.h b/platform/driver/mvp/config/sl_mvp_config.h index 6de3577917..4adf6aaa74 100644 --- a/platform/driver/mvp/config/sl_mvp_config.h +++ b/platform/driver/mvp/config/sl_mvp_config.h @@ -65,6 +65,13 @@ // Default: 0 #define SL_MVP_POWER_MODE 0 +// Enable additional speed optimizations for MVP operations +// By enabling this, the MVP will attempt to optimize select operations +// to run faster, at the expence of increased RAM usage. +// Note: This may increase RAM usage greatly. +// Default: 0 +#define SL_MVP_OPTIMIZE_SPEED 0 + #endif /* SL_MVP_CONFIG_H */ // <<< end of configuration section >>> diff --git a/platform/driver/mvp/inc/sl_mvp_ml_conv2d.h b/platform/driver/mvp/inc/sl_mvp_ml_conv2d.h index 09a81dc09c..15e9dca594 100644 --- a/platform/driver/mvp/inc/sl_mvp_ml_conv2d.h +++ b/platform/driver/mvp/inc/sl_mvp_ml_conv2d.h @@ -72,6 +72,7 @@ typedef struct { int dilation_width; /**< Dilation width factor. */ int input_offset; /**< Zero value for the input tensor. */ int output_offset; /**< Zero value for the output tensor.*/ + float16_t *scratch_buffer; /**< Pointer to scratch buffer */ } sli_mvp_ml_conv2d_s8_params_t; /***************************************************************************//** @@ -108,6 +109,19 @@ sl_status_t sli_mvp_ml_conv2d_s8(const sli_mvp_ml_conv2d_s8_params_t *params); ******************************************************************************/ bool sli_mvp_ml_conv2d_s8_is_supported(const sli_mvp_ml_conv2d_s8_params_t *params); +/***************************************************************************//** + * @brief + * Return the required scratch buffer size for the Conv2D operation + * + * @param[in] params Pointer to a data structure containing information on + * all input parameters, refer to + * @ref sli_mvp_ml_conv2d_s8_params_t. + * + * @return + * Required scratch buffer size in bytes + ******************************************************************************/ +int sli_mvp_ml_conv2d_s8_get_scratch_buffer_size(const sli_mvp_ml_conv2d_s8_params_t *params); + /** @} (end addtogroup mvp) */ /// @endcond diff --git a/platform/driver/mvp/src/sl_mvp_ml_conv2d.c b/platform/driver/mvp/src/sl_mvp_ml_conv2d.c index 4606ddd745..c8abfcbf22 100644 --- a/platform/driver/mvp/src/sl_mvp_ml_conv2d.c +++ b/platform/driver/mvp/src/sl_mvp_ml_conv2d.c @@ -28,6 +28,7 @@ * ******************************************************************************/ +#include "sl_mvp_config.h" #include "sl_mvp_ml_conv2d.h" #include "sl_mvp.h" #include "sl_mvp_util.h" @@ -77,6 +78,28 @@ bool sli_mvp_ml_conv2d_s8_is_supported(const sli_mvp_ml_conv2d_s8_params_t *para return conv2d(params, false) == SL_STATUS_OK; } +/***************************************************************************//** + * + * Return the required scratch buffer size to perform the Conv2D operation + * + ******************************************************************************/ +int sli_mvp_ml_conv2d_s8_get_scratch_buffer_size(const sli_mvp_ml_conv2d_s8_params_t *params) +{ + int scratch_buffer_size = 0; + + #if SL_MVP_OPTIMIZE_SPEED == 1 + // Required scratch buffer size is the input tensor as float16_t + const int input_depth = params->in_channels; + const int input_height = params->input_height; + const int input_width = params->input_width; + scratch_buffer_size = (input_width * input_height * input_depth) * sizeof(float16_t); + #else + (void)params; + #endif + + return scratch_buffer_size; +} + static sl_status_t conv2d(const sli_mvp_ml_conv2d_s8_params_t *params, bool execute) { // Consume all input parameters. @@ -95,6 +118,10 @@ static sl_status_t conv2d(const sli_mvp_ml_conv2d_s8_params_t *params, bool exec const float16_t zero = 0.0f; int8_t *output = params->output; + #if SL_MVP_OPTIMIZE_SPEED == 1 + float16_t *scaled_input = (float16_t*)params->scratch_buffer; + #endif + sl_status_t status = SL_STATUS_OK; sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); @@ -140,6 +167,118 @@ static sl_status_t conv2d(const sli_mvp_ml_conv2d_s8_params_t *params, bool exec const int output_width = params->output_width; const int32_t output_offset = params->output_offset; + +#if (SL_MVP_OPTIMIZE_SPEED == 1) + + // If SL_MVP_OPTIMIZE_SPEED is enabled, calculate the input accumulator scaler + // in a separate program. The scaled inputs are stored in a temporary array + // and used directly by the conv2D algorithm. + for (int batch = 0; batch < batches; ++batch) { + int input_stride_dim2 = 1; + int input_size_dim2 = input_depth; + int input_stride_dim1 = input_size_dim2; + int input_size_dim1 = input_width; + int input_stride_dim0 = input_size_dim2 * input_size_dim1; + int input_size_dim0 = input_height; + + int input_index = sli_mvp_util_offset_nhwc(input_height, input_width, input_depth, + batch /* out_channel_start */, + 0, + 0, + 0); + + // Condition to pack two reals to use both FMACs in MVP and double throughput. + const bool use_parallel_mac_input_scaling = (input_size_dim2 % 2 == 0) + && (input_stride_dim1 % 2 == 0) + && (input_stride_dim0 % 2 == 0) + && (input_index % 2 == 0); + + if (use_parallel_mac_input_scaling) { + input_size_dim2 /= 2; + input_stride_dim1 /= 2; + input_stride_dim0 /= 2; + } + + SLI_MVP_CHECK(input_stride_dim0 <= (int)SLI_MVP_MAX_VECTOR_STRIDE); + + sli_mvp_pb_begin_program(p); + + // Input array + sli_mvp_pb_config_array_full(p->p, + SLI_MVP_ARRAY(0), + (void*)&input[input_index], + use_parallel_mac_input_scaling == true + ? SLI_MVP_DATATYPE_COMPLEX_INT8 + : SLI_MVP_DATATYPE_INT8, + input_size_dim0, + input_size_dim1, + input_size_dim2, + input_stride_dim0, + input_stride_dim1, + input_stride_dim2, + &status); + + // Output array + sli_mvp_pb_config_array_full(p->p, + SLI_MVP_ARRAY(1), + (void*)&scaled_input[input_index], + use_parallel_mac_input_scaling == true + ? SLI_MVP_DATATYPE_COMPLEX_BINARY16 + : SLI_MVP_DATATYPE_BINARY16, + input_size_dim0, + input_size_dim1, + input_size_dim2, + input_stride_dim0, + input_stride_dim1, + input_stride_dim2, + &status); + + sli_mvp_prog_set_reg_f16(p->p, SLI_MVP_R0, SLI_MVP_ACCUMULATOR_SCALER); + if (use_parallel_mac_input_scaling) { + sli_mvp_prog_set_reg_f16c(p->p, SLI_MVP_R1, input_offset_scaled, input_offset_scaled); + } else { + sli_mvp_prog_set_reg_f16(p->p, SLI_MVP_R1, input_offset_scaled); + } + + sli_mvp_pb_begin_loop(p, input_size_dim0, &status); // input width + sli_mvp_pb_begin_loop(p, input_size_dim1, &status); // input height + sli_mvp_pb_begin_loop(p, input_size_dim2, &status); // input depth + // LOAD(ARRAY0, R5) Input + // LOAD(ARRAY1, R7) Filter + // R6 = MACC(R5, R0, R1) Compute(r_input_i, MACC, r_input_i, c_accumulator_scaler, c_input_offset_scaled) + sli_mvp_pb_compute(p, + SLI_MVP_OP(MACC), + SLI_MVP_ALU_Z(SLI_MVP_R6) + | SLI_MVP_ALU_X(SLI_MVP_R5) + | SLI_MVP_ALU_Y(SLI_MVP_R0) + | SLI_MVP_ALU_A(SLI_MVP_R1), + SLI_MVP_LOAD(0, SLI_MVP_R5, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM2), + SLI_MVP_STORE(SLI_MVP_R6, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM2), + &status); + + sli_mvp_pb_end_loop(p); // input depth + sli_mvp_pb_postloop_incr_dim(p, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM1); + sli_mvp_pb_postloop_incr_dim(p, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM1); + sli_mvp_pb_end_loop(p); // input height + sli_mvp_pb_postloop_incr_dim(p, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM0); + sli_mvp_pb_postloop_incr_dim(p, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM0); + sli_mvp_pb_end_loop(p); // input width + + + // Check if any errors found during program generation. + if (status != SL_STATUS_OK) { + if (execute) { + EFM_ASSERT(false); + } + return status; + } + + if (execute) { + sli_mvp_pb_execute_program(p); + } + } +#endif + // Implemented as single parameterizable MVP program. // Note that there is some flexibility lost by having to compute full output // values at once vs. being able to have a partial sum stored in the output @@ -156,6 +295,8 @@ static sl_status_t conv2d(const sli_mvp_ml_conv2d_s8_params_t *params, bool exec const int out_x_center_max = sli_div_floor_int(in_x_origin_center_max + pad_width, stride_width); for (int out_x_min = 0, out_x_max; out_x_min < output_width; out_x_min = out_x_max + 1) { + /* Truncate filter width to actual filter width when filter starts outside of + valid input area, i.e. padded area */ const int in_x_origin_min = (out_x_min * stride_width) - pad_width; const int filter_x_start = SL_MAX(0, -in_x_origin_min); const int filter_x_end = SL_MIN(filter_width, input_width - in_x_origin_min); @@ -360,7 +501,23 @@ static sl_status_t conv2d(const sli_mvp_ml_conv2d_s8_params_t *params, bool exec // Array2 bias // Array3 scaler // Array4 output - + #if (SL_MVP_OPTIMIZE_SPEED == 1) + // Use the prescaled input values + sli_mvp_pb_config_array_full(p->p, + SLI_MVP_ARRAY(0), + (void*)&scaled_input[input_index_base], + use_parallel_mac == true + ? SLI_MVP_DATATYPE_COMPLEX_BINARY16 + : SLI_MVP_DATATYPE_BINARY16, + input_size_vec, + input_size_row, + input_size_col, + input_stride_vec, + input_stride_row, + input_stride_col, + &status); + #else + // Use unscaled input values sli_mvp_pb_config_array_full(p->p, SLI_MVP_ARRAY(0), (void*)&input[input_index_base], @@ -374,6 +531,7 @@ static sl_status_t conv2d(const sli_mvp_ml_conv2d_s8_params_t *params, bool exec input_stride_row, input_stride_col, &status); + #endif sli_mvp_pb_config_array_full(p->p, SLI_MVP_ARRAY(1), @@ -442,6 +600,26 @@ static sl_status_t conv2d(const sli_mvp_ml_conv2d_s8_params_t *params, bool exec sli_mvp_pb_begin_loop(p, filter_height_truncated, &status); { sli_mvp_pb_begin_loop(p, input_size_col, &status); { + #if (SL_MVP_OPTIMIZE_SPEED == 1) + // Accumulate input * filter + + // R5 = MAC(R6, R7, R5) Compute(r_acc, MACR2A, r_input_i, r_filter_i, r_acc) + sli_mvp_pb_compute(p, + SLI_MVP_OP(MACR2A), + SLI_MVP_ALU_Z(SLI_MVP_R5) + | SLI_MVP_ALU_X(SLI_MVP_R6) + | SLI_MVP_ALU_Y(SLI_MVP_R7) + | SLI_MVP_ALU_A(SLI_MVP_R5), + SLI_MVP_LOAD(0, SLI_MVP_R6, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_COL) + | SLI_MVP_LOAD(1, SLI_MVP_R7, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_COL), + SLI_MVP_NONE, + &status); + + #else // SL_MVP_OPTIMIZE_SPEED == 0 + + // 1. Scale the inputs by accumulator scaler and offset + // 2. Accumulate input * filter + // LOAD(ARRAY0, R6) Input // LOAD(ARRAY1, R7) Filter // R6 = MACC(R6, R0, R1) Compute(r_input_i, MACC, r_input_i, c_accumulator_scaler, c_input_offset_scaled) @@ -466,6 +644,7 @@ static sl_status_t conv2d(const sli_mvp_ml_conv2d_s8_params_t *params, bool exec SLI_MVP_NONE, SLI_MVP_NONE, &status); + #endif } sli_mvp_pb_end_loop(p); // input_size_col sli_mvp_pb_postloop_incr_dim(p, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_ROW); diff --git a/platform/emdrv/component/nvm3_default.slcc b/platform/emdrv/component/nvm3_default.slcc index 8f5828368e..47534e3c23 100644 --- a/platform/emdrv/component/nvm3_default.slcc +++ b/platform/emdrv/component/nvm3_default.slcc @@ -23,9 +23,10 @@ config_file: condition: [device_series_1] - path: platform/emdrv/nvm3/config/s2/nvm3_default_config.h condition: [device_series_2] + unless: [trustzone_secure] source: - path: platform/emdrv/nvm3/src/nvm3_default_common_linker.c - unless: [trustzone_nonsecure] + unless: [trustzone_nonsecure, trustzone_secure] include: - path: platform/emdrv/nvm3/inc file_list: @@ -43,6 +44,7 @@ template_contribution: event: platform_init include: nvm3_default.h handler: nvm3_initDefault + unless: [trustzone_secure] documentation: docset: gecko-platform document: driver/api/group-nvm3default diff --git a/platform/emdrv/nvm3/lib/libnvm3_CM0P_gcc.a b/platform/emdrv/nvm3/lib/libnvm3_CM0P_gcc.a index 5a568dd5ea..edae29b601 100644 --- a/platform/emdrv/nvm3/lib/libnvm3_CM0P_gcc.a +++ b/platform/emdrv/nvm3/lib/libnvm3_CM0P_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:71b739fb41ce6976a251e701a6c9d3d5ab04298a748662231e1cf1254254f671 -size 33870 +oid sha256:86c5159503cf3230e85025cc1422835a4e4db3d4feb19949bb6877b64ae4fc56 +size 34078 diff --git a/platform/emdrv/nvm3/lib/libnvm3_CM0P_iar.a b/platform/emdrv/nvm3/lib/libnvm3_CM0P_iar.a index b11fa84a5a..b2be9e79ce 100644 --- a/platform/emdrv/nvm3/lib/libnvm3_CM0P_iar.a +++ b/platform/emdrv/nvm3/lib/libnvm3_CM0P_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:cc3c32645214dadd21307f49517acc5ba2e996be3f1d3b94e948a211f86005a1 -size 75258 +oid sha256:711288c51d65896b7622252971de6916879858ce6fd4cd852964c39fa8efd6b1 +size 75406 diff --git a/platform/emdrv/nvm3/lib/libnvm3_CM33_gcc.a b/platform/emdrv/nvm3/lib/libnvm3_CM33_gcc.a index a0477ecb48..e8ac501afb 100644 --- a/platform/emdrv/nvm3/lib/libnvm3_CM33_gcc.a +++ b/platform/emdrv/nvm3/lib/libnvm3_CM33_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:01420b5c6adc64b02e757d90622e6033fbca78e5796e0a09575f73c9fde65559 -size 33318 +oid sha256:8c19f206a54d1d4b70361808d3a08d4af168d9ac117c5201867782f73b727e0e +size 33522 diff --git a/platform/emdrv/nvm3/lib/libnvm3_CM33_iar.a b/platform/emdrv/nvm3/lib/libnvm3_CM33_iar.a index 9964e37ac3..084f751bf8 100644 --- a/platform/emdrv/nvm3/lib/libnvm3_CM33_iar.a +++ b/platform/emdrv/nvm3/lib/libnvm3_CM33_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:681bc13e6666373257b4b1b24250e51713b759b933c1df42ebcdbf71378e709a -size 113284 +oid sha256:a931625ff5a97ee1615affaffddf96fad64214c93baa780007292b2de48176ad +size 113440 diff --git a/platform/emdrv/nvm3/lib/libnvm3_CM3_gcc.a b/platform/emdrv/nvm3/lib/libnvm3_CM3_gcc.a index 8fae0b535e..6cd6eb2e8f 100644 --- a/platform/emdrv/nvm3/lib/libnvm3_CM3_gcc.a +++ b/platform/emdrv/nvm3/lib/libnvm3_CM3_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:593cf3b0567e2ad56372a54d2dfa8f5c6a0dcecc51cca807eba5b192faf8c003 -size 33222 +oid sha256:92d6e9d7211dd67e76699490a6c793cfd3520f2482135004df9d0e14291c8bab +size 33426 diff --git a/platform/emdrv/nvm3/lib/libnvm3_CM3_iar.a b/platform/emdrv/nvm3/lib/libnvm3_CM3_iar.a index 3c2b9c006e..a6ec41645a 100644 --- a/platform/emdrv/nvm3/lib/libnvm3_CM3_iar.a +++ b/platform/emdrv/nvm3/lib/libnvm3_CM3_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3aa3861b252212f6e0280def9e076475238e152e439c9329a257525d4cee932b -size 114998 +oid sha256:c37c4871557e9e59a43d663754b9405b59193ea9f62d2e338f864a953c6f2e71 +size 115148 diff --git a/platform/emdrv/nvm3/lib/libnvm3_CM4_gcc.a b/platform/emdrv/nvm3/lib/libnvm3_CM4_gcc.a index 6a00039667..07abf1ffae 100644 --- a/platform/emdrv/nvm3/lib/libnvm3_CM4_gcc.a +++ b/platform/emdrv/nvm3/lib/libnvm3_CM4_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3b53777522127964e52014e68d77103f288c8a5fffb79a4e038ea1b10a957aa7 -size 33290 +oid sha256:14b3cf1cd39737adf49c177563f0cc3fccea2ed8115bfc2162defb81ef0335f8 +size 33494 diff --git a/platform/emdrv/nvm3/lib/libnvm3_CM4_iar.a b/platform/emdrv/nvm3/lib/libnvm3_CM4_iar.a index d2e42be41f..ab8681001e 100644 --- a/platform/emdrv/nvm3/lib/libnvm3_CM4_iar.a +++ b/platform/emdrv/nvm3/lib/libnvm3_CM4_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b53807b3cb59760e840576a684a86157bc09b5050ab6f73e698eddf546061e26 -size 115770 +oid sha256:f08ae85661453ecdf807def3edfbea9fb71f53fa306fc03ea40cb97ea02bce50 +size 115916 diff --git a/platform/emlib/component/emlib_syscfg.slcc b/platform/emlib/component/emlib_syscfg.slcc index 8734f97a4d..d28cca13b6 100644 --- a/platform/emlib/component/emlib_syscfg.slcc +++ b/platform/emlib/component/emlib_syscfg.slcc @@ -18,4 +18,4 @@ provides: requires: - name: emlib_common - name: tz_service_syscfg - condition: [tz_secure_key_library_ns] \ No newline at end of file + condition: [trustzone_nonsecure] \ No newline at end of file diff --git a/platform/emlib/inc/em_bus.h b/platform/emlib/inc/em_bus.h index 3209a80a51..6b2e977b9f 100644 --- a/platform/emlib/inc/em_bus.h +++ b/platform/emlib/inc/em_bus.h @@ -145,7 +145,7 @@ __STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, EFM_ASSERT(bit < 32U); #if defined(PER_REG_BLOCK_SET_OFFSET) && defined(PER_REG_BLOCK_CLR_OFFSET) uint32_t aliasAddr; - if (val) { + if (val != 0U) { aliasAddr = (uint32_t)addr + PER_REG_BLOCK_SET_OFFSET; } else { aliasAddr = (uint32_t)addr + PER_REG_BLOCK_CLR_OFFSET; diff --git a/platform/emlib/inc/em_cmu.h b/platform/emlib/inc/em_cmu.h index 4a2f1ad7c9..8401ad2c9d 100644 --- a/platform/emlib/inc/em_cmu.h +++ b/platform/emlib/inc/em_cmu.h @@ -1278,9 +1278,11 @@ void CMU_HFRCODPLLBandSet(CMU_HFRCODPLLFreq_TypeDef freq); bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init); #if defined(USBPLL_PRESENT) void CMU_USBPLLInit(const CMU_PLL_Init_TypeDef *pllInit); +__STATIC_INLINE void CMU_WaitUSBPLLLock(void); #endif #if defined(RFFPLL_PRESENT) void CMU_RFFPLLInit(const CMU_RFFPLL_Init_TypeDef *pllInit); +__STATIC_INLINE void CMU_WaitRFFPLLLock(void); #endif void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit); #if defined(HFXO0_BUFOUT) @@ -1379,7 +1381,7 @@ __STATIC_INLINE void CMU_DPLLUnlock(void) { DPLL0->EN_CLR = DPLL_EN_EN; #if defined(DPLL_EN_DISABLING) - while (DPLL0->EN & DPLL_EN_DISABLING) { + while ((DPLL0->EN & DPLL_EN_DISABLING) != 0U) { } #endif } @@ -1560,7 +1562,9 @@ __STATIC_INLINE void CMU_WdogUnlock(void) __STATIC_INLINE void CMU_WaitUSBPLLLock() { while ((USBPLL0->STATUS & (PLL_STATUS_PLLRDY | PLL_STATUS_PLLLOCK)) - != (PLL_STATUS_PLLRDY | PLL_STATUS_PLLLOCK)) ; + != (PLL_STATUS_PLLRDY | PLL_STATUS_PLLLOCK)) { + /* Wait for USB PLL lock and ready */ + } } #endif @@ -1572,7 +1576,9 @@ __STATIC_INLINE void CMU_WaitUSBPLLLock() __STATIC_INLINE void CMU_WaitRFFPLLLock() { while ((RFFPLL0->STATUS & (RFFPLL_STATUS_RFFPLLRADIORDY | RFFPLL_STATUS_RFFPLLSYSRDY)) - != (RFFPLL_STATUS_RFFPLLRADIORDY | RFFPLL_STATUS_RFFPLLSYSRDY)) ; + != (RFFPLL_STATUS_RFFPLLRADIORDY | RFFPLL_STATUS_RFFPLLSYSRDY)) { + /* Wait for RFF PLL lock and ready. */ + } } #endif @@ -3348,14 +3354,15 @@ __STATIC_INLINE void CMU_CalibrateStop(void) /***************************************************************************//** * @brief - * Convert dividend to logarithmic value. It only works for even + * Convert divider to logarithmic value. It only works for even * numbers equal to 2^n. * * @param[in] div - * An unscaled dividend. + * An unscaled divider. * * @return - * Logarithm of 2, as used by fixed prescalers. + * Logarithm base 2 (binary) value, i.e. exponent as used by fixed + * 2^n prescalers. ******************************************************************************/ __STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div) { @@ -3585,14 +3592,17 @@ __STATIC_INLINE SL_DEPRECATED_API_SDK_4_1 void CMU_AUXHFRCOFreqSet(CMU_AUXHFRCOF #if !defined(_SILICON_LABS_32B_SERIES_0) /***************************************************************************//** * @brief - * Convert prescaler dividend to a logarithmic value. It only works for even + * Convert prescaler divider to a logarithmic value. It only works for even * numbers equal to 2^n. * * @param[in] presc - * An unscaled dividend (dividend = presc + 1). + * Prescaler value used to set the frequency divider. The divider is equal to + * ('presc' + 1). If a divider value is passed for 'presc', 'presc' will be + * equal to (divider - 1). * * @return - * Logarithm of 2, as used by fixed 2^n prescalers. + * Logarithm base 2 (binary) value, i.e. exponent as used by fixed + * 2^n prescalers. ******************************************************************************/ __STATIC_INLINE uint32_t CMU_PrescToLog2(uint32_t presc) { @@ -3601,7 +3611,8 @@ __STATIC_INLINE uint32_t CMU_PrescToLog2(uint32_t presc) /* Integer prescalers take argument less than 32768. */ EFM_ASSERT(presc < 32768U); - /* Count leading zeroes and "reverse" result. */ + /* Count leading zeroes and "reverse" result. Consider divider value to get + * exponent n from 2^n, so ('presc' +1). */ log2 = 31UL - __CLZ(presc + (uint32_t) 1); /* Check that prescaler is a 2^n number. */ diff --git a/platform/emlib/inc/em_emu.h b/platform/emlib/inc/em_emu.h index 7ac7851a8a..43765987dd 100644 --- a/platform/emlib/inc/em_emu.h +++ b/platform/emlib/inc/em_emu.h @@ -141,9 +141,9 @@ typedef enum { typedef enum { /** No connection. */ emuBuBuInactPwrCon_None = EMU_BUCTRL_BUINACTPWRCON_NONE, - /** Allow power from backup to main. */ - emuBuBuInactPwrCon_MainBu = EMU_BUCTRL_BUINACTPWRCON_MAINBU, /** Allow power from main to backup. */ + emuBuBuInactPwrCon_MainBu = EMU_BUCTRL_BUINACTPWRCON_MAINBU, + /** Allow power from backup to main. */ emuBuBuInactPwrCon_BuMain = EMU_BUCTRL_BUINACTPWRCON_BUMAIN, /** Backup and main power are connected. */ emuBuBuInactPwrCon_NoDiode = EMU_BUCTRL_BUINACTPWRCON_NODIODE, @@ -155,9 +155,9 @@ typedef enum { typedef enum { /** No connection. */ emuBuBuActPwrCon_None = EMU_BUCTRL_BUACTPWRCON_NONE, - /** Allow power from backup to main. */ - emuBuBuActPwrCon_MainBu = EMU_BUCTRL_BUACTPWRCON_MAINBU, /** Allow power from main to backup. */ + emuBuBuActPwrCon_MainBu = EMU_BUCTRL_BUACTPWRCON_MAINBU, + /** Allow power from backup to main. */ emuBuBuActPwrCon_BuMain = EMU_BUCTRL_BUACTPWRCON_BUMAIN, /** Backup and main power are connected. */ emuBuBuActPwrCon_NoDiode = EMU_BUCTRL_BUACTPWRCON_NODIODE, @@ -451,17 +451,16 @@ typedef enum { /** DCDC Boost EM01 peak current setting. */ typedef enum { - emuDcdcBoostEM01PeakCurrent_Load36mA = _DCDC_BSTEM01CTRL_IPKVAL_Load36mA, /**< Load 36mA, peak current 90mA. */ - emuDcdcBoostEM01PeakCurrent_Load40mA = _DCDC_BSTEM01CTRL_IPKVAL_Load40mA, /**< Load 40mA, peak current 100mA. */ - emuDcdcBoostEM01PeakCurrent_Load44mA = _DCDC_BSTEM01CTRL_IPKVAL_Load44mA, /**< Load 44mA, peak current 110mA. */ - emuDcdcBoostEM01PeakCurrent_Load48mA = _DCDC_BSTEM01CTRL_IPKVAL_Load48mA, /**< Load 48mA, peak current 120mA. */ - emuDcdcBoostEM01PeakCurrent_Load52mA = _DCDC_BSTEM01CTRL_IPKVAL_Load52mA, /**< Load 52mA, peak current 130mA. */ - emuDcdcBoostEM01PeakCurrent_Load56mA = _DCDC_BSTEM01CTRL_IPKVAL_Load56mA, /**< Load 56mA, peak current 140mA. */ - emuDcdcBoostEM01PeakCurrent_Load60mA = _DCDC_BSTEM01CTRL_IPKVAL_Load60mA, /**< Load 60mA, peak current 150mA. */ - emuDcdcBoostEM01PeakCurrent_Load64mA = _DCDC_BSTEM01CTRL_IPKVAL_Load64mA, /**< Load 64mA, peak current 160mA. */ - emuDcdcBoostEM01PeakCurrent_Load68mA = _DCDC_BSTEM01CTRL_IPKVAL_Load68mA, /**< Load 68mA, peak current 170mA. */ - emuDcdcBoostEM01PeakCurrent_Load72mA = _DCDC_BSTEM01CTRL_IPKVAL_Load72mA, /**< Load 72mA, peak current 180mA. */ - emuDcdcBoostEM01PeakCurrent_Load80mA = _DCDC_BSTEM01CTRL_IPKVAL_Load80mA /**< Load 80mA, peak current 200mA. */ + emuDcdcBoostEM01PeakCurrent_Load10mA = _DCDC_BSTEM01CTRL_IPKVAL_Load10mA, /**< Load 10mA */ + emuDcdcBoostEM01PeakCurrent_Load11mA = _DCDC_BSTEM01CTRL_IPKVAL_Load11mA, /**< Load 11mA */ + emuDcdcBoostEM01PeakCurrent_Load13mA = _DCDC_BSTEM01CTRL_IPKVAL_Load13mA, /**< Load 13mA */ + emuDcdcBoostEM01PeakCurrent_Load15mA = _DCDC_BSTEM01CTRL_IPKVAL_Load15mA, /**< Load 15mA */ + emuDcdcBoostEM01PeakCurrent_Load16mA = _DCDC_BSTEM01CTRL_IPKVAL_Load16mA, /**< Load 16mA */ + emuDcdcBoostEM01PeakCurrent_Load18mA = _DCDC_BSTEM01CTRL_IPKVAL_Load18mA, /**< Load 18mA */ + emuDcdcBoostEM01PeakCurrent_Load20mA = _DCDC_BSTEM01CTRL_IPKVAL_Load20mA, /**< Load 20mA */ + emuDcdcBoostEM01PeakCurrent_Load21mA = _DCDC_BSTEM01CTRL_IPKVAL_Load21mA, /**< Load 21mA */ + emuDcdcBoostEM01PeakCurrent_Load23mA = _DCDC_BSTEM01CTRL_IPKVAL_Load23mA, /**< Load 23mA */ + emuDcdcBoostEM01PeakCurrent_Load25mA = _DCDC_BSTEM01CTRL_IPKVAL_Load25mA, /**< Load 25mA */ } EMU_DcdcBoostEM01PeakCurrent_TypeDef; /** DCDC Boost Toff max timeout */ @@ -490,7 +489,7 @@ typedef enum { /** DCDC Boost EM23 peak current setting. */ typedef enum { - emuDcdcBoostEM23PeakCurrent_Load10mA = _DCDC_BSTEM23CTRL_IPKVAL_Load10mA, /**< Load 10mA, peak current 150mA. */ + emuDcdcBoostEM23PeakCurrent_Load10mA = _DCDC_BSTEM23CTRL_IPKVAL_Load10mA, /**< Load 10mA */ } EMU_DcdcBoostEM23PeakCurrent_TypeDef; #endif /* EMU_SERIES2_DCDC_BOOST_PRESENT) */ @@ -883,7 +882,7 @@ typedef struct { true, /**< disable DCDC boost mode with BOOST_EN=0 */ \ emuDcdcBoostDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \ emuDcdcBoostDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \ - emuDcdcBoostEM01PeakCurrent_Load72mA, /**< Default peak current in EM0/1. */ \ + emuDcdcBoostEM01PeakCurrent_Load25mA, /**< Default peak current in EM0/1. */ \ emuDcdcBoostEM23PeakCurrent_Load10mA /**< Default peak current in EM2/3. */ \ } #endif /* EMU_SERIES2_DCDC_BOOST_PRESENT */ @@ -1197,11 +1196,11 @@ void EMU_BoostExternalShutdownEnable(bool enable); #if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) \ || defined(EMU_SERIES2_DCDC_BUCK_PRESENT) bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit); +bool EMU_DCDCPowerOff(void); #endif #if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) void EMU_EM01PeakCurrentSet(const EMU_DcdcPeakCurrent_TypeDef peakCurrentEM01); -bool EMU_DCDCPowerOff(void); #if defined(_DCDC_PFMXCTRL_IPKVAL_MASK) void EMU_DCDCSetPFMXModePeakCurrent(uint32_t value); #endif diff --git a/platform/emlib/inc/em_iadc.h b/platform/emlib/inc/em_iadc.h index 31fb3f1c60..6cf2721a05 100644 --- a/platform/emlib/inc/em_iadc.h +++ b/platform/emlib/inc/em_iadc.h @@ -661,11 +661,17 @@ typedef enum { /** Internal 1.2V Band Gap Reference (buffered) to ground */ iadcCfgReferenceInt1V2 = _IADC_CFG_REFSEL_VBGR, - /** External reference (unbuffered) VREFP to VREFN. Up to 1.25V. */ + /** External reference (unbuffered) VREFP to VREFN. + * VEVREF up to AVDD. When inputs are routed to external GPIO pins, + * the maximum pin voltage is limited to the lower + * of the IOVDD and AVDD supplies. + * The internal calibration values correspond to a 1.25V reference, + * use of other voltages may require recalibration. + * See AN1189: Incremental Analog to Digital Converter (IADC) */ iadcCfgReferenceExt1V25 = _IADC_CFG_REFSEL_VREF, #if defined(_IADC_CFG_REFSEL_VREF2P5) - /** External reference (unbuffered) VREFP to VREFN. Up to 1.25V. */ + /** External reference (unbuffered) VREFP to VREFN. Supports 2.5V in high accuracy mode. */ iadcCfgReferenceExt2V5 = _IADC_CFG_REFSEL_VREF2P5, #endif diff --git a/platform/emlib/inc/em_msc.h b/platform/emlib/inc/em_msc.h index 1eed5d241c..5897420bd2 100644 --- a/platform/emlib/inc/em_msc.h +++ b/platform/emlib/inc/em_msc.h @@ -322,7 +322,7 @@ __STATIC_INLINE bool MSC_LockGetLocked(void) return (bool)sli_tz_ns_interface_dispatch_simple( (sli_tz_simple_veneer_fn)sli_tz_msc_get_locked, SLI_TZ_DISPATCH_UNUSED_ARG); -#elif (_MSC_STATUS_REGLOCK_MASK) +#elif defined(_MSC_STATUS_REGLOCK_MASK) return (MSC->STATUS & _MSC_STATUS_REGLOCK_MASK) != MSC_STATUS_REGLOCK_UNLOCKED; #else return (MSC->LOCK & _MSC_LOCK_MASK) != MSC_LOCK_LOCKKEY_UNLOCK; diff --git a/platform/emlib/inc/em_syscfg.h b/platform/emlib/inc/em_syscfg.h index 53e3a8c17c..fb10b4a920 100644 --- a/platform/emlib/inc/em_syscfg.h +++ b/platform/emlib/inc/em_syscfg.h @@ -33,7 +33,7 @@ #include "em_device.h" -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) +#if defined(SL_TRUSTZONE_NONSECURE) #include "sli_tz_service_syscfg.h" #endif @@ -52,7 +52,7 @@ extern "C" { ******************************************************************************/ __STATIC_INLINE uint32_t SYSCFG_readChipRev(void) { -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) +#if defined(SL_TRUSTZONE_NONSECURE) return sli_tz_syscfg_read_chiprev_register(); #else return SYSCFG->CHIPREV; @@ -66,7 +66,7 @@ __STATIC_INLINE uint32_t SYSCFG_readChipRev(void) ******************************************************************************/ __STATIC_INLINE void SYSCFG_setDmem0RamCtrlRamwsenBit(void) { -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) +#if defined(SL_TRUSTZONE_NONSECURE) sli_tz_syscfg_set_dmem0ramctrl_ramwsen_bit(); #else @@ -79,7 +79,7 @@ __STATIC_INLINE void SYSCFG_setDmem0RamCtrlRamwsenBit(void) ******************************************************************************/ __STATIC_INLINE void SYSCFG_clearDmem0RamCtrlRamwsenBit(void) { -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) +#if defined(SL_TRUSTZONE_NONSECURE) sli_tz_syscfg_clear_dmem0ramctrl_ramwsen_bit(); #else SYSCFG->DMEM0RAMCTRL = SYSCFG->DMEM0RAMCTRL & ~_SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK; @@ -91,7 +91,7 @@ __STATIC_INLINE void SYSCFG_clearDmem0RamCtrlRamwsenBit(void) ******************************************************************************/ __STATIC_INLINE uint32_t SYSCFG_getDmem0RamCtrlRamwsenBit(void) { -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) +#if defined(SL_TRUSTZONE_NONSECURE) return sli_tz_syscfg_get_dmem0ramctrl_ramwsen_bit(); #else return (SYSCFG->DMEM0RAMCTRL & _SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK) >> _SYSCFG_DMEM0RAMCTRL_RAMWSEN_SHIFT; @@ -106,7 +106,7 @@ __STATIC_INLINE uint32_t SYSCFG_getDmem0RamCtrlRamwsenBit(void) ******************************************************************************/ __STATIC_INLINE uint32_t SYSCFG_readDmem0RetnCtrl(void) { -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) +#if defined(SL_TRUSTZONE_NONSECURE) return sli_tz_syscfg_read_dmem0retnctrl_register(); #else return SYSCFG->DMEM0RETNCTRL; @@ -119,7 +119,7 @@ __STATIC_INLINE uint32_t SYSCFG_readDmem0RetnCtrl(void) ******************************************************************************/ __STATIC_INLINE void SYSCFG_maskDmem0RetnCtrl(uint32_t mask) { -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) +#if defined(SL_TRUSTZONE_NONSECURE) sli_tz_syscfg_mask_dmem0retnctrl_register(mask); #else SYSCFG->DMEM0RETNCTRL = SYSCFG->DMEM0RETNCTRL | mask; @@ -131,7 +131,7 @@ __STATIC_INLINE void SYSCFG_maskDmem0RetnCtrl(uint32_t mask) ******************************************************************************/ __STATIC_INLINE void SYSCFG_zeroDmem0RetnCtrl(void) { -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) +#if defined(SL_TRUSTZONE_NONSECURE) sli_tz_syscfg_zero_dmem0retnctrl_register(); #else SYSCFG->DMEM0RETNCTRL = 0x0UL; @@ -145,7 +145,7 @@ __STATIC_INLINE void SYSCFG_zeroDmem0RetnCtrl(void) ******************************************************************************/ __STATIC_INLINE void SYSCFG_setSysTicExtClkEnCfgSysTic(void) { -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) +#if defined(SL_TRUSTZONE_NONSECURE) sli_tz_syscfg_set_systicextclken_cfgsystic(); #else SYSCFG->CFGSYSTIC = (SYSCFG->CFGSYSTIC | _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK); @@ -157,7 +157,7 @@ __STATIC_INLINE void SYSCFG_setSysTicExtClkEnCfgSysTic(void) ******************************************************************************/ __STATIC_INLINE void SYSCFG_clearSysTicExtClkEnCfgSysTic(void) { -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) +#if defined(SL_TRUSTZONE_NONSECURE) sli_tz_syscfg_clear_systicextclken_cfgsystic(); #else SYSCFG->CFGSYSTIC = (SYSCFG->CFGSYSTIC & ~_SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK); diff --git a/platform/emlib/src/em_cmu.c b/platform/emlib/src/em_cmu.c index 7c7f318778..0196b074f5 100644 --- a/platform/emlib/src/em_cmu.c +++ b/platform/emlib/src/em_cmu.c @@ -7551,7 +7551,8 @@ uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock) * have a prescaler. See the CMU overview in the reference manual. * * @param[in] presc - * The clock prescaler. + * The clock prescaler. The prescaler value is linked to the clock divider by: + * divider = 'presc' + 1. ******************************************************************************/ void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc) { diff --git a/platform/emlib/src/em_emu.c b/platform/emlib/src/em_emu.c index 6de8b26591..79c8ce130f 100644 --- a/platform/emlib/src/em_emu.c +++ b/platform/emlib/src/em_emu.c @@ -44,16 +44,16 @@ #endif /* Consistency check, since restoring assumes similar bit positions in */ /* CMU OSCENCMD and STATUS regs. */ -#if (CMU_STATUS_AUXHFRCOENS != CMU_OSCENCMD_AUXHFRCOEN) +#if defined(CMU_STATUS_AUXHFRCOENS) && (CMU_STATUS_AUXHFRCOENS != CMU_OSCENCMD_AUXHFRCOEN) #error Conflict in AUXHFRCOENS and AUXHFRCOEN bitpositions #endif -#if (CMU_STATUS_HFXOENS != CMU_OSCENCMD_HFXOEN) +#if defined(CMU_STATUS_HFXOENS) && (CMU_STATUS_HFXOENS != CMU_OSCENCMD_HFXOEN) #error Conflict in HFXOENS and HFXOEN bitpositions #endif -#if (CMU_STATUS_LFRCOENS != CMU_OSCENCMD_LFRCOEN) +#if defined(CMU_STATUS_LFRCOENS) && (CMU_STATUS_LFRCOENS != CMU_OSCENCMD_LFRCOEN) #error Conflict in LFRCOENS and LFRCOEN bitpositions #endif -#if (CMU_STATUS_LFXOENS != CMU_OSCENCMD_LFXOEN) +#if defined(CMU_STATUS_LFXOENS) && (CMU_STATUS_LFXOENS != CMU_OSCENCMD_LFXOEN) #error Conflict in LFXOENS and LFXOEN bitpositions #endif @@ -1364,7 +1364,7 @@ void EMU_EnterEM4(void) } #endif -#if (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG) && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) /* Workaround for bug that may cause a Hard Fault on EM4 entry */ CMU_ClockSelectSet(cmuClock_SYSCLK, cmuSelect_FSRCO); /* Switch from DCDC regulation mode to bypass mode before entering EM4. */ diff --git a/platform/emlib/src/em_iadc.c b/platform/emlib/src/em_iadc.c index 1624f1879b..0f7aa84715 100644 --- a/platform/emlib/src/em_iadc.c +++ b/platform/emlib/src/em_iadc.c @@ -186,7 +186,7 @@ void IADC_init(IADC_TypeDef *iadc, { uint32_t tmp; uint32_t config; - uint8_t wantedPrescale; + uint16_t wantedPrescale; uint8_t srcClkPrescale; uint32_t adcClkPrescale; uint8_t timebase; @@ -980,7 +980,7 @@ uint32_t IADC_calcAdcClkPrescale(IADC_TypeDef *iadc, // Limit to max allowed register setting ret = SL_MIN(ret, (_IADC_SCHED_PRESCALE_MASK >> _IADC_SCHED_PRESCALE_SHIFT)); - return (uint8_t)ret; + return (uint16_t)ret; } /***************************************************************************//** diff --git a/platform/emlib/src/em_ldma.c b/platform/emlib/src/em_ldma.c index 2d2bacf4ac..2754046132 100644 --- a/platform/emlib/src/em_ldma.c +++ b/platform/emlib/src/em_ldma.c @@ -95,7 +95,7 @@ void LDMA_DeInit(void) #endif CMU_ClockEnable(cmuClock_LDMA, false); -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) CMU_ClockEnable(cmuClock_LDMAXBAR, false); #endif } @@ -163,7 +163,7 @@ void LDMA_Init(const LDMA_Init_t *init) EFM_ASSERT(init->ldmaInitIrqPriority < (1 << __NVIC_PRIO_BITS)); CMU_ClockEnable(cmuClock_LDMA, true); -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) CMU_ClockEnable(cmuClock_LDMAXBAR, true); #endif diff --git a/platform/hwconf_data/hwconfig.hwdata b/platform/hwconf_data/hwconfig.hwdata index 5d03e591be..c42a75ea92 100644 --- a/platform/hwconf_data/hwconfig.hwdata +++ b/platform/hwconf_data/hwconfig.hwdata @@ -1,243 +1,243 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/platform/micrium_os/micrium-cano.properties b/platform/micrium_os/micrium-cano.properties index 87988770b3..d50235be54 100644 --- a/platform/micrium_os/micrium-cano.properties +++ b/platform/micrium_os/micrium-cano.properties @@ -1,6 +1,6 @@ -version=5.13.0 -dependantSdkVersion=4.1.0 +version=5.13.1 +dependantSdkVersion=4.1.1 label=Micrium OS CANopen description=SL-MOS-CANX-PKG000-P-SPL prop.subLabel=Micrium\\ OS\\ CANopen diff --git a/platform/micrium_os/micrium-fsxx.properties b/platform/micrium_os/micrium-fsxx.properties index 957a2eb347..6698d1b1af 100644 --- a/platform/micrium_os/micrium-fsxx.properties +++ b/platform/micrium_os/micrium-fsxx.properties @@ -1,6 +1,6 @@ -version=5.13.0 -dependantSdkVersion=4.1.0 +version=5.13.1 +dependantSdkVersion=4.1.1 label=Micrium OS File System description=SL-MOS-FSXX-PKG000-P-SPL prop.subLabel=Micrium\\ OS\\ File\\ System diff --git a/platform/micrium_os/micrium-ioxx.properties b/platform/micrium_os/micrium-ioxx.properties index 74917e78f7..f1e53c9edb 100644 --- a/platform/micrium_os/micrium-ioxx.properties +++ b/platform/micrium_os/micrium-ioxx.properties @@ -1,6 +1,6 @@ -version=5.13.0 -dependantSdkVersion=4.1.0 +version=5.13.1 +dependantSdkVersion=4.1.1 label=Micrium OS IO description=SL-MOS-IOX-PKG000-P-SPL prop.subLabel=Micrium\\ OS\\ IO diff --git a/platform/micrium_os/micrium-krnx.properties b/platform/micrium_os/micrium-krnx.properties index 759496db6a..5b3a7bd645 100644 --- a/platform/micrium_os/micrium-krnx.properties +++ b/platform/micrium_os/micrium-krnx.properties @@ -1,10 +1,10 @@ id=com.silabs.sdk.micrium -version=5.13.00 -dependantSdkVersion=4.1.0 +version=5.13.10 +dependantSdkVersion=4.1.1 label=Micrium OS Kernel description=SL-MOS-KRNX-000000-P-P1 -prop.subLabel=Micrium\\ OS\\ Kernel\\ 5.13.00 +prop.subLabel=Micrium\\ OS\\ Kernel\\ 5.13.10 prop.installedUnit=krnx diff --git a/platform/micrium_os/micrium-tcpx.properties b/platform/micrium_os/micrium-tcpx.properties index deedbd503f..6f322d4b55 100644 --- a/platform/micrium_os/micrium-tcpx.properties +++ b/platform/micrium_os/micrium-tcpx.properties @@ -1,6 +1,6 @@ -version=5.13.0 -dependantSdkVersion=4.1.0 +version=5.13.1 +dependantSdkVersion=4.1.1 label=Micrium OS Network description=SL-MOS-TCPX-PKG000-P-SPL prop.subLabel=Micrium\\ OS\\ Network diff --git a/platform/micrium_os/micrium-usbd.properties b/platform/micrium_os/micrium-usbd.properties index 4b36aadbf1..e0e4c8ab52 100644 --- a/platform/micrium_os/micrium-usbd.properties +++ b/platform/micrium_os/micrium-usbd.properties @@ -1,6 +1,6 @@ -version=5.13.0 -dependantSdkVersion=4.1.0 +version=5.13.1 +dependantSdkVersion=4.1.1 label=Micrium OS USB Device description=SL-MOS-USBD-PKG000-P- SPL prop.subLabel=Micrium\\ OS\\ USB\\ Device diff --git a/platform/micrium_os/micrium-usbh.properties b/platform/micrium_os/micrium-usbh.properties index 762eabd699..305bae146f 100644 --- a/platform/micrium_os/micrium-usbh.properties +++ b/platform/micrium_os/micrium-usbh.properties @@ -1,6 +1,6 @@ -version=5.13.0 -dependantSdkVersion=4.1.0 +version=5.13.1 +dependantSdkVersion=4.1.1 label=Micrium OS USB Host description=SL-MOS-USBH-PKG000-P- SPL prop.subLabel=Micrium\\ OS\\ USB\\ Host diff --git a/platform/micrium_os/net/source/http/server/http_server_mem.c b/platform/micrium_os/net/source/http/server/http_server_mem.c index fe3667c5d1..8dc25e5b18 100644 --- a/platform/micrium_os/net/source/http/server/http_server_mem.c +++ b/platform/micrium_os/net/source/http/server/http_server_mem.c @@ -59,12 +59,6 @@ #define HTTPs_CFG_POOLS_INIT_NBR 1 -/******************************************************************************************************** - * FORM DEFINES - *******************************************************************************************************/ - -#define HTTPs_FORM_BOUNDARY_STR_LEN_MAX 72u - /******************************************************************************************************** ******************************************************************************************************** * GLOBAL VARIABLES @@ -164,7 +158,7 @@ void HTTPsMem_InstanceInit(MEM_SEG *p_mem_seg, RTOS_ERR_SET(*p_err, RTOS_ERR_NONE); -exit: + exit: return; } @@ -212,7 +206,7 @@ HTTPs_OS_TASK_OBJ *HTTPsMem_InstanceTaskInit(RTOS_ERR *p_err) RTOS_ERR_SET(*p_err, RTOS_ERR_NONE); -exit: + exit: return (p_os_task_obj); } @@ -393,7 +387,7 @@ void HTTPsMem_InstanceWorkingDirInit(HTTPs_INSTANCE *p_instance, RTOS_ERR_SET(*p_err, RTOS_ERR_NONE); -exit: + exit: return; } #endif @@ -943,7 +937,7 @@ HTTPs_CONN *HTTPsMem_ConnGet(HTTPs_INSTANCE *p_instance, #if ((HTTPs_CFG_FORM_EN == DEF_ENABLED) \ && (HTTPs_CFG_FORM_MULTIPART_EN == DEF_ENABLED)) -exit_free_host: + exit_free_host: #if (HTTPs_CFG_ABSOLUTE_URI_EN == DEF_ENABLED) Mem_DynPoolBlkFree(&p_instance->PoolHost, // Release host previously acquired. p_conn->HostPtr, @@ -954,7 +948,7 @@ HTTPs_CONN *HTTPsMem_ConnGet(HTTPs_INSTANCE *p_instance, #endif #if (HTTPs_CFG_ABSOLUTE_URI_EN == DEF_ENABLED) -exit_free_path: + exit_free_path: Mem_DynPoolBlkFree(&p_instance->PoolPath, // Release path previously acquired. p_conn->PathPtr, &local_err); @@ -962,21 +956,21 @@ HTTPs_CONN *HTTPsMem_ConnGet(HTTPs_INSTANCE *p_instance, p_conn->PathPtr = DEF_NULL; #endif -exit_free_buf: + exit_free_buf: Mem_DynPoolBlkFree(&p_instance->PoolBuf, // Release buf previously acquired. p_conn->BufPtr, &local_err); RTOS_ASSERT_CRITICAL((RTOS_ERR_CODE_GET(local_err) == RTOS_ERR_NONE), RTOS_ERR_ASSERT_CRITICAL_FAIL, DEF_NULL); p_conn->BufPtr = DEF_NULL; -exit_free_conn: + exit_free_conn: Mem_DynPoolBlkFree(&p_instance->PoolConn, // Release conn previously acquired. p_conn, &local_err); RTOS_ASSERT_CRITICAL((RTOS_ERR_CODE_GET(local_err) == RTOS_ERR_NONE), RTOS_ERR_ASSERT_CRITICAL_FAIL, DEF_NULL); p_conn = DEF_NULL; -exit: + exit: return (p_conn); } @@ -1273,7 +1267,7 @@ CPU_BOOLEAN HTTPsMem_TokenGet(HTTPs_INSTANCE *p_instance, goto exit; -exit_release_blk: + exit_release_blk: { RTOS_ERR local_err; @@ -1283,7 +1277,7 @@ CPU_BOOLEAN HTTPsMem_TokenGet(HTTPs_INSTANCE *p_instance, RTOS_ASSERT_CRITICAL((RTOS_ERR_CODE_GET(local_err) == RTOS_ERR_NONE), RTOS_ERR_ASSERT_CRITICAL_FAIL, DEF_FAIL); } -exit: + exit: return (result); } #endif @@ -1414,21 +1408,21 @@ HTTPs_KEY_VAL *HTTPsMem_QueryStrKeyValBlkGet(HTTPs_INSTANCE *p_instance, goto exit; -exit_release_key: + exit_release_key: Mem_DynPoolBlkFree(&p_instance->PoolQueryStrKeyStr, // Key String block previously acquired. p_key_val->KeyPtr, &local_err); RTOS_ASSERT_CRITICAL((RTOS_ERR_CODE_GET(local_err) == RTOS_ERR_NONE), RTOS_ERR_ASSERT_CRITICAL_FAIL, DEF_NULL); p_key_val->KeyPtr = DEF_NULL; -exit_release_blk: + exit_release_blk: Mem_DynPoolBlkFree(&p_instance->PoolKeyVal, // Key-Val block previously acquired. p_key_val, &local_err); RTOS_ASSERT_CRITICAL((RTOS_ERR_CODE_GET(local_err) == RTOS_ERR_NONE), RTOS_ERR_ASSERT_CRITICAL_FAIL, DEF_NULL); p_key_val = DEF_NULL; -exit: + exit: return (p_key_val); } #endif @@ -1585,21 +1579,21 @@ HTTPs_KEY_VAL *HTTPsMem_FormKeyValBlkGet(HTTPs_INSTANCE *p_instance, goto exit; -exit_release_key: + exit_release_key: Mem_DynPoolBlkFree(&p_instance->PoolFormKeyStr, // Key String block previously acquired. p_key_val->KeyPtr, &local_err); RTOS_ASSERT_CRITICAL((RTOS_ERR_CODE_GET(local_err) == RTOS_ERR_NONE), RTOS_ERR_ASSERT_CRITICAL_FAIL, DEF_NULL); p_key_val->KeyPtr = DEF_NULL; -exit_release_blk: + exit_release_blk: Mem_DynPoolBlkFree(&p_instance->PoolKeyVal, // Key-Val block previously acquired. p_key_val, &local_err); RTOS_ASSERT_CRITICAL((RTOS_ERR_CODE_GET(local_err) == RTOS_ERR_NONE), RTOS_ERR_ASSERT_CRITICAL_FAIL, DEF_NULL); p_key_val = DEF_NULL; -exit: + exit: return (p_key_val); } #endif diff --git a/platform/micrium_os/net/source/http/server/http_server_priv.h b/platform/micrium_os/net/source/http/server/http_server_priv.h index e5a8690b1b..8074edbaf3 100644 --- a/platform/micrium_os/net/source/http/server/http_server_priv.h +++ b/platform/micrium_os/net/source/http/server/http_server_priv.h @@ -171,6 +171,12 @@ #define HTTPs_FLAG_RESP_CHUNKED DEF_BIT_04 #define HTTPs_FLAG_RESP_CHUNKED_HOOK DEF_BIT_05 +/******************************************************************************************************** + * FORM DEFINES + *******************************************************************************************************/ + +#define HTTPs_FORM_BOUNDARY_STR_LEN_MAX 72u + /******************************************************************************************************** ******************************************************************************************************** * DATA TYPES diff --git a/platform/micrium_os/net/source/http/server/http_server_req.c b/platform/micrium_os/net/source/http/server/http_server_req.c index 5842ede500..3f665d8845 100644 --- a/platform/micrium_os/net/source/http/server/http_server_req.c +++ b/platform/micrium_os/net/source/http/server/http_server_req.c @@ -1563,6 +1563,11 @@ static void HTTPsReq_HdrParse(HTTPs_INSTANCE *p_instance, len); len = p_field_end - p_val; + if (len > HTTPs_FORM_BOUNDARY_STR_LEN_MAX) { + *p_err = HTTPs_ERR_REQ_FORMAT_INVALID; + return; + } + // Copy boundary val to Conn struct. Str_Copy_N(p_conn->FormBoundaryPtr, p_val, diff --git a/platform/middleware/glib/dmd/dmd.h b/platform/middleware/glib/dmd/dmd.h index a36507d68b..59e25ac729 100644 --- a/platform/middleware/glib/dmd/dmd.h +++ b/platform/middleware/glib/dmd/dmd.h @@ -44,6 +44,11 @@ #include #include "em_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + /* TODO: remove this and replace with include types and ecodes */ /** Base of DMD error codes */ #define ECODE_DMD_BASE 0x00000000 @@ -332,4 +337,8 @@ EMSTATUS DMD_runTests(uint32_t tests, uint32_t *result); /** @} (end addtogroup dmd) */ /** @} (end addtogroup glib) */ +#ifdef __cplusplus +} +#endif + #endif /* __DISPLAY_DMD_H__ */ diff --git a/platform/middleware/glib/dmd/etm043010edh6/dmd_etm043010edh6.h b/platform/middleware/glib/dmd/etm043010edh6/dmd_etm043010edh6.h index 69a8263be0..7427cb6e6e 100644 --- a/platform/middleware/glib/dmd/etm043010edh6/dmd_etm043010edh6.h +++ b/platform/middleware/glib/dmd/etm043010edh6/dmd_etm043010edh6.h @@ -20,6 +20,10 @@ #include "emstatus.h" +#ifdef __cplusplus +extern "C" { +#endif + #define DMD_HORIZONTAL_SIZE (480) #define DMD_VERTICAL_SIZE (272) #define DMD_DISPLAY_BACKLIGHT_PORT (gpioPortI) @@ -30,4 +34,8 @@ EMSTATUS DMD_startDrawing(void); EMSTATUS DMD_stopDrawing(void); +#ifdef __cplusplus +} +#endif + #endif /* __DMD_ETM043010EDH6_H__ */ diff --git a/platform/middleware/glib/dmd/ssd2119/dmd_ssd2119.h b/platform/middleware/glib/dmd/ssd2119/dmd_ssd2119.h index bb9886347c..644e956a80 100644 --- a/platform/middleware/glib/dmd/ssd2119/dmd_ssd2119.h +++ b/platform/middleware/glib/dmd/ssd2119/dmd_ssd2119.h @@ -20,6 +20,10 @@ #include "dmd/dmd.h" +#ifdef __cplusplus +extern "C" { +#endif + /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /** Frame update frequency of display */ @@ -33,4 +37,8 @@ EMSTATUS DMDIF_init(uint32_t cmdRegAddr, uint32_t dataRegAddr); /** @endcond */ +#ifdef __cplusplus +} +#endif + #endif diff --git a/platform/middleware/glib/dmd/ssd2119/dmdif_ssd2119_ebi.h b/platform/middleware/glib/dmd/ssd2119/dmdif_ssd2119_ebi.h index 07b6d4ee3c..48ff7143b8 100644 --- a/platform/middleware/glib/dmd/ssd2119/dmdif_ssd2119_ebi.h +++ b/platform/middleware/glib/dmd/ssd2119/dmdif_ssd2119_ebi.h @@ -21,6 +21,10 @@ #include #include "em_types.h" +#ifdef __cplusplus +extern "C" { +#endif + /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /* Module Prototypes */ @@ -35,4 +39,8 @@ EMSTATUS DMDIF_delay(uint32_t ms); /** @endcond */ +#ifdef __cplusplus +} +#endif + #endif diff --git a/platform/middleware/glib/dmd/ssd2119/dmdif_ssd2119_spi.h b/platform/middleware/glib/dmd/ssd2119/dmdif_ssd2119_spi.h index 6ea66921aa..0c10291356 100644 --- a/platform/middleware/glib/dmd/ssd2119/dmdif_ssd2119_spi.h +++ b/platform/middleware/glib/dmd/ssd2119/dmdif_ssd2119_spi.h @@ -20,6 +20,10 @@ #include +#ifdef __cplusplus +extern "C" { +#endif + /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /* Module Prototypes */ @@ -33,4 +37,8 @@ EMSTATUS DMDIF_delay(uint32_t ms); /** @endcond */ +#ifdef __cplusplus +} +#endif + #endif diff --git a/platform/middleware/glib/glib/bmp.h b/platform/middleware/glib/glib/bmp.h index fa08cc50ed..04681259d9 100644 --- a/platform/middleware/glib/glib/bmp.h +++ b/platform/middleware/glib/glib/bmp.h @@ -27,6 +27,10 @@ #include "bmp_conf.h" +#ifdef __cplusplus +extern "C" { +#endif + /***************************************************************************//** * @addtogroup glib * @{ @@ -175,4 +179,8 @@ int32_t BMP_getFileSize(void); /** @} (end addtogroup bmp) */ /** @} (end addtogroup glib) */ +#ifdef __cplusplus +} +#endif + #endif /* __BMP_H_ */ diff --git a/platform/middleware/glib/glib/glib.h b/platform/middleware/glib/glib/glib.h index cb4f71028f..d5b7e3db4c 100644 --- a/platform/middleware/glib/glib/glib.h +++ b/platform/middleware/glib/glib/glib.h @@ -264,7 +264,7 @@ typedef struct __GLIB_Font_t{ /** The font class is used to tell glib if the font contains numbers only * or characters and numbers */ - GLIB_Font_Class class; + GLIB_Font_Class fontClass; } GLIB_Font_t; /** @brief Rectangle structure diff --git a/platform/middleware/glib/glib/glib_string.c b/platform/middleware/glib/glib/glib_string.c index 8296ec7b01..97d89b72db 100644 --- a/platform/middleware/glib/glib/glib_string.c +++ b/platform/middleware/glib/glib/glib_string.c @@ -73,7 +73,7 @@ EMSTATUS GLIB_drawChar(GLIB_Context_t *pContext, char myChar, int32_t x, int32_t } /* Sets the index in the font array */ - if (pContext->font.class == NumbersOnlyFont) { + if (pContext->font.fontClass == NumbersOnlyFont) { fontIdx = (myChar - '0'); if (myChar == ':') { fontIdx = 10; @@ -190,7 +190,7 @@ EMSTATUS GLIB_drawString(GLIB_Context_t *pContext, const char* pString, uint32_t return GLIB_ERROR_INVALID_ARGUMENT; } - if (pContext->font.class == InvalidFont) { + if (pContext->font.fontClass == InvalidFont) { return GLIB_ERROR_INVALID_CHAR; } diff --git a/platform/radio/mac/component/lower_mac_spinel.slcc b/platform/radio/mac/component/lower_mac_spinel.slcc index f2632a3c8b..3b0bb9f5c1 100644 --- a/platform/radio/mac/component/lower_mac_spinel.slcc +++ b/platform/radio/mac/component/lower_mac_spinel.slcc @@ -32,7 +32,6 @@ include: - path: backbone_router/multicast_listeners_table.hpp - path: backbone_router/ndproxy_table.hpp - path: border_router/infra_if.hpp - - path: border_router/router_advertisement.hpp - path: border_router/routing_manager.hpp - path: coap/coap.hpp - path: coap/coap_message.hpp @@ -177,6 +176,7 @@ include: - path: net/ip6_types.hpp - path: net/ip6_mpl.hpp - path: net/nd_agent.hpp + - path: net/nd6.hpp - path: net/netif.hpp - path: net/sntp_client.hpp - path: net/socket.hpp @@ -350,6 +350,7 @@ include: - path: lib/url/url.hpp - path: lib/spinel/spinel_interface.hpp - path: lib/hdlc/hdlc.hpp + - path: lib/spinel/radio_spinel_metrics.h - path: lib/spinel/spinel.h - path: lib/spinel/spinel_platform.h - path: "util/third_party/openthread/src/lib/spinel" diff --git a/platform/radio/mac/lower-mac-spinel-config.h b/platform/radio/mac/lower-mac-spinel-config.h index 864d337234..b978fe15aa 100644 --- a/platform/radio/mac/lower-mac-spinel-config.h +++ b/platform/radio/mac/lower-mac-spinel-config.h @@ -100,6 +100,9 @@ //Dont use PSA for multiPAN builds. #define OPENTHREAD_CONFIG_PLATFORM_KEY_REFERENCES_ENABLE 0 +// for mfglib commands +#define OPENTHREAD_CONFIG_DIAG_ENABLE 1 + // <<< end of configuration section >>> #endif // LOWER_MAC_SPINEL_CONFIG_H diff --git a/platform/radio/mac/rail_mux/sl_rail_mux.c b/platform/radio/mac/rail_mux/sl_rail_mux.c index 89d5646f23..28b502c2bd 100644 --- a/platform/radio/mac/rail_mux/sl_rail_mux.c +++ b/platform/radio/mac/rail_mux/sl_rail_mux.c @@ -1735,7 +1735,7 @@ static RAIL_Status_t fn_start_pending_tx(void) for (i = 0; i < SUPPORTED_PROTOCOL_COUNT; i++) { // Pending scheduled TX if (fn_get_context_flag_by_index(i, RAIL_MUX_PROTOCOL_FLAGS_SCHEDULED_TX_PENDING)) { - RAIL_Status_t status; + RAIL_Status_t status = RAIL_STATUS_NO_ERROR; if ( !check_lock_permissions(i)) { // Post a tx blocked event to notify mac state machines fn_mux_rail_events_callback(mux_rail_handle, RAIL_EVENT_TX_BLOCKED); diff --git a/platform/radio/rail_lib/apps/railtest/app_ci/info_ci.c b/platform/radio/rail_lib/apps/railtest/app_ci/info_ci.c index 180c348629..9039fb133a 100644 --- a/platform/radio/rail_lib/apps/railtest/app_ci/info_ci.c +++ b/platform/radio/rail_lib/apps/railtest/app_ci/info_ci.c @@ -936,6 +936,10 @@ void printChipFeatures(sl_cli_command_arg_t *args) "RAIL_SUPPORTS_SQ_PHY", RAIL_SUPPORTS_SQ_PHY ? "Yes" : "No", RAIL_SupportsSQPhy(railHandle) ? "Yes" : "No"); + responsePrintMulti("Feature:%s,CompileTime:%s,RunTime:%s", + "RAIL_SUPPORTS_RX_RAW_DATA", + RAIL_SUPPORTS_RX_RAW_DATA ? "Yes" : "No", + RAIL_SupportsRxRawData(railHandle) ? "Yes" : "No"); responsePrintMulti("Feature:%s,CompileTime:%s,RunTime:%s", "RAIL_SUPPORTS_DIRECT_MODE", RAIL_SUPPORTS_DIRECT_MODE ? "Yes" : "No", diff --git a/platform/radio/rail_lib/apps/railtest/app_ci/trx_ci.c b/platform/radio/rail_lib/apps/railtest/app_ci/trx_ci.c index dafc4f05bb..adaa1964c9 100644 --- a/platform/radio/rail_lib/apps/railtest/app_ci/trx_ci.c +++ b/platform/radio/rail_lib/apps/railtest/app_ci/trx_ci.c @@ -403,14 +403,16 @@ void setRxOptions(sl_cli_command_arg_t *args) responsePrint(sl_cli_get_command_string(args, 0), "storeCrc:%s,ignoreCrcErrors:%s,enableDualSync:%s," "trackAborted:%s,removeAppendedInfo:%s,rxAntenna:%s," - "frameDet:%s", + "frameDet:%s,skipDCCal:%s,skipSynthCa:%s", (rxOptions & RAIL_RX_OPTION_STORE_CRC) ? "True" : "False", (rxOptions & RAIL_RX_OPTION_IGNORE_CRC_ERRORS) ? "True" : "False", (rxOptions & RAIL_RX_OPTION_ENABLE_DUALSYNC) ? "True" : "False", (rxOptions & RAIL_RX_OPTION_TRACK_ABORTED_FRAMES) ? "True" : "False", (rxOptions & RAIL_RX_OPTION_REMOVE_APPENDED_INFO) ? "True" : "False", configuredRxAntenna(rxOptions), - (rxOptions & RAIL_RX_OPTION_DISABLE_FRAME_DETECTION) ? "Off" : "On"); + (rxOptions & RAIL_RX_OPTION_DISABLE_FRAME_DETECTION) ? "Off" : "On", + (rxOptions & RAIL_RX_OPTION_SKIP_DC_CAL) ? "True" : "False", + (rxOptions & RAIL_RX_OPTION_SKIP_SYNTH_CAL) ? "True" : "False"); } void setTxTone(sl_cli_command_arg_t *args) diff --git a/platform/radio/rail_lib/apps/railtest/app_common.h b/platform/radio/rail_lib/apps/railtest/app_common.h index f93f58ee8b..6322055c63 100644 --- a/platform/radio/rail_lib/apps/railtest/app_common.h +++ b/platform/radio/rail_lib/apps/railtest/app_common.h @@ -574,7 +574,7 @@ AppMode_t currentAppMode(void); void enableAppMode(AppMode_t appMode, bool enable, char *command); bool enableAppModeSync(AppMode_t appMode, bool enable, char *command); void setNextAppMode(AppMode_t appMode, char *command); -void changeAppModeIfPending(); +void changeAppModeIfPending(void); const char *appModeNames(AppMode_t appMode); bool inAppMode(AppMode_t appMode, char *command); bool inRadioState(RAIL_RadioState_t state, char *command); diff --git a/platform/radio/rail_lib/apps/railtest/app_main.c b/platform/radio/rail_lib/apps/railtest/app_main.c index e22e19d39a..a1b6c3c6c9 100644 --- a/platform/radio/rail_lib/apps/railtest/app_main.c +++ b/platform/radio/rail_lib/apps/railtest/app_main.c @@ -340,7 +340,8 @@ void sl_rail_test_internal_app_init(void) responsePrintEnable(printingEnabled); // Print app initialization information. RAILTEST_PRINTF("\n"); - responsePrint("reset", "App:%s,Built:%s", SL_RAIL_TEST_APP_NAME, buildDateTime); + responsePrint("reset", "App:%s,Built:%s,Cause:0x%x", + SL_RAIL_TEST_APP_NAME, buildDateTime, resetCause); printChipInfo(); getPti(NULL); diff --git a/platform/radio/rail_lib/apps/railtest/app_modes.c b/platform/radio/rail_lib/apps/railtest/app_modes.c index bf225d4dff..5df7af2e75 100644 --- a/platform/radio/rail_lib/apps/railtest/app_modes.c +++ b/platform/radio/rail_lib/apps/railtest/app_modes.c @@ -49,12 +49,12 @@ volatile bool transitionPend = false; RAIL_TxOptions_t antOptions = RAIL_TX_OPTIONS_DEFAULT; RAIL_StreamMode_t streamMode = RAIL_STREAM_PN9_STREAM; -AppMode_t currentAppMode() +AppMode_t currentAppMode(void) { return currAppMode; } -AppMode_t previousAppMode() +AppMode_t previousAppMode(void) { return prevAppMode; } @@ -186,7 +186,7 @@ static void setAppModeInternal(void) } // This should be called from a main loop, to update the AppMode -void changeAppModeIfPending() +void changeAppModeIfPending(void) { if (transitionPend) { transitionPend = false; diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111a256v2_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111a256v2_gcc.a index 2e8679c532..4bd094c16f 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111a256v2_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111a256v2_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a07a42b42d55981a52dae19e060335f164702c5262db7e2e72a69e0ba5c9b12d +oid sha256:a448145f891ccaa3d149050677f44a180668bdc8272926ab1df7671ce6367e57 size 51130 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111a256v2_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111a256v2_iar.a index ef127a8f1b..4d02e947a6 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111a256v2_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111a256v2_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:afff7c1e81d39a985ad47948f7289a1fe762720e97ec0c43239acdd400093c3d -size 36044 +oid sha256:815d94ad949dd07c65ca06ef399397b4f1f73fdae461096fdc0163f61616a61c +size 36042 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111e256v2_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111e256v2_gcc.a index 3d5b20650b..b26f694b05 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111e256v2_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111e256v2_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d8b25f0c7d2db5942cf9829a62e7c81cab99a181860eebdad998429c3e9c76dc +oid sha256:9280e4e6ad546b964d85b5e2cce8e2392ac236f316641dd4de4f05f2322f6727 size 51130 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111e256v2_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111e256v2_iar.a index 9a4510b479..289de555cb 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111e256v2_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm111e256v2_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b78f02d1b8208f385ee1036a5da6c6b41731ea3e151586760b52bbdc173e117d -size 36044 +oid sha256:31181f084b3fc437123b3cb19bd797a07d0b5eb7ac331dec9765e29c447676cb +size 36042 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm113a256v2_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm113a256v2_gcc.a index edea63afa4..97c7664496 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm113a256v2_gcc.a +++ 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b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm11s12f256ga_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:606a2866867850dbfeafac9854ac409fdb346e4962f11a97b4d4f8517bdb6e0c -size 36070 +oid sha256:2ff5ca48cf718205958af4b69f69c770b6b6eb11b22138d6d33a70277e549add +size 36068 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm11s22f256ga_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm11s22f256ga_gcc.a index c255e55c8c..6fed57e863 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm11s22f256ga_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm11s22f256ga_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1fcf83664388a8ac18987d01287c427d1281d0626ae880c5127557cd95720200 +oid sha256:9262543a94a995695f0da7a2853eeac525ce7db941e9eee78e803e6e2fa229e6 size 51138 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm11s22f256ga_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm11s22f256ga_iar.a index 1b21fae0ba..3b89a19278 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm11s22f256ga_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm11s22f256ga_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8e772f3ea1c6daf7bbcb55ae8fb90cf953461df454257decdeb49b9662d067b5 -size 36070 +oid sha256:cd82811b7de5d5d3e21310e8fdbc96b10e5d0b95dc37103b01b0dcad70333921 +size 36068 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm121a256v2_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm121a256v2_gcc.a index 76815802b6..46b7c2bfd1 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm121a256v2_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm121a256v2_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:50f54bbb11c5f42c3dc4258d07bb0b1190b42aac813c3f630f1b7c5aac141056 +oid sha256:34120a363e803d89f771ffab458f7f8fd822f79bad0ea157ecc51c8aacce7e86 size 51130 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm121a256v2_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm121a256v2_iar.a index 70968ddcca..5a5c3aaaf3 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm121a256v2_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm121a256v2_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b4b9c11f143cac47cd56efd3bda7f854d077892da9be221133e8dbdf0b257684 -size 36044 +oid sha256:3f13d918f7197e639d7c76ce61d32f1fd343946f575637fcbf04916bb8417169 +size 36042 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm121n256v2_gcc.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm121n256v2_gcc.a index 5ce9bd151f..8c864de558 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm121n256v2_gcc.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm121n256v2_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1b9ed76a0ebfc7e385d969699de5156b097538b63b79489eed3ed1ac7d8b23a4 +oid sha256:7ef7b36c3053b5196fa1f1d1e408c9163dfbb5edcc738244705cd849b1dcc9a3 size 51130 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm121n256v2_iar.a b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm121n256v2_iar.a index 047e39059c..d9a77c160e 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm121n256v2_iar.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_config_bgm121n256v2_iar.a @@ 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b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg1_iar_release.a index 8cdb3c1573..24a27ea304 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg1_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg1_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c5756e25438d824a268b990f10641584bb6c2a5a3882d31a059562dd1bbb444a -size 968032 +oid sha256:e92bf8c59496ed8797b21d4e40f4b44d0b6412141c96a5f9442942f189eb29d2 +size 969942 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg21_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg21_gcc_release.a index e454df9daa..88e34c9a97 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg21_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg21_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ed887bc8542ff5adbcb6444a6ace2cb73f481bf55aba775f78a04143c1f1cbd7 -size 457282 +oid sha256:b27f21a01ebe4ab776d3235d4e278258163df9fe7dc286b4b825fc78a641f421 +size 459016 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg21_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg21_iar_release.a index 4d2213a489..cd03f7ab55 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg21_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg21_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7c585144787553b2a52a99c253add83f65a586f42fa4d030dc27e227619f23d2 -size 993898 +oid sha256:9e17deb39e004e9a02cd9e6a4af9d25b9ef297d3c64f93ed4fe8234eb2efe882 +size 991724 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg22_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg22_gcc_release.a index b02751faad..c1db911e95 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg22_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg22_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d3a4c5bbbefa8f28eeb1e2111a4c34dd4d75d75c9c480ea28f92da729c95203d -size 480050 +oid sha256:30fff3b0e3791244ff6473a0c1fb97d80c8d8a3012f26fa4768fa1d4d5567fa4 +size 481372 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg22_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg22_iar_release.a index c8911c9a4c..4de834c038 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg22_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg22_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:bebd4d7f796dce37bff01aa263f7449b27eff65bd2c9751e9ea017a79226ee2e -size 1032658 +oid sha256:c7415c0e745cefec4b628827e480338601b9a09f6963851987b680e861c06f3a +size 1031392 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg23_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg23_gcc_release.a index 2d7bd50a44..847c2ff400 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg23_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg23_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ac15f3539a858d951929e29f745f14415c30d797c2ce59677a2e62ab6b222cfc -size 493360 +oid sha256:8dc56c3b80ae6d57c32d252c8d991f17b8a4c5474606ee2a448862401021e188 +size 494618 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg23_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg23_iar_release.a index 7fa0b08795..3c168d59d3 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg23_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg23_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:493aebd7ee5b6718641befad9c96b7e0ee66a439c5aa531766b882a6e7fc7dab -size 1076192 +oid sha256:843c97478ebbd04a98c67f99a554be070939f3c95c1efd4c623630d20bb0a1fd +size 1076206 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg24_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg24_gcc_release.a index cdba2d8eaf..43c8f89bd3 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg24_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg24_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:daf328f8f724ae47ae7fc30076e351df500e102b5f3971f13fa65a49c90ea000 -size 479606 +oid sha256:6672bbaf7b41f299ba120ef272c255005ffd1c11fc7fb48c7542a952dfdb807e +size 481124 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg24_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg24_iar_release.a index 573775eb45..d453aebd8c 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg24_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg24_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8fd350a95c8758394144a4382f4c344c2f873c5e12b215a97c3480578df9cf03 -size 1042026 +oid sha256:78dc304ec89509ffd6487b9a05c1e102c855480f7005c4a760ea44855d505dcd +size 1043016 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg25_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg25_gcc_release.a index 61ec2c2285..52dba22fa2 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg25_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg25_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ed776ce129c18d22a2711f17bd8fcad8d80957ecbae176ec955f05d2e51a5ac0 -size 571474 +oid sha256:0273a02552c6b4ead821584c4238f88b7973b6d5c7ae001a9881cec07be98a00 +size 572768 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg25_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg25_iar_release.a index d5ee936fb9..3a14469d9a 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg25_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg25_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1ec5f19a3c9fe206d902d37fdee8e57773b18d301582ca1a03138fe5677bc42b -size 1152114 +oid sha256:5205b9a554bab34c1d69fda02be11fee4a69807fd3805506bf88bb9dd34bda1f +size 1150744 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg27_gcc_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg27_gcc_release.a index 520bc0699c..a517d06b0e 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg27_gcc_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg27_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fcef67433bebb9f38bd7b3e1f27480d13ae147768c1951553e3086f5b37bbeda -size 479902 +oid sha256:1defe5604574718f4407fa23e2514969d9399e7db5769047911f9a1d347cbf96 +size 481216 diff --git a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg27_iar_release.a b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg27_iar_release.a index e16806c303..c21abe2f09 100644 --- a/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg27_iar_release.a +++ b/platform/radio/rail_lib/autogen/librail_release/librail_multiprotocol_module_efr32xg27_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:82271cf277fc99833418bb2f483f03ab426aa6d0757e12b5381aa9ddc2bd3028 -size 1033006 +oid sha256:fcf6dda1854d56f5452d931b4a3879ae50b01dd1cea9b306d3c8d042793bc820 +size 1031736 diff --git a/platform/radio/rail_lib/autogen/ver_def.h b/platform/radio/rail_lib/autogen/ver_def.h index 331f9b05b8..5663b7e2d2 100644 --- a/platform/radio/rail_lib/autogen/ver_def.h +++ b/platform/radio/rail_lib/autogen/ver_def.h @@ -42,11 +42,11 @@ typedef struct // LOCAL_COMMITS_FLAG << 1 | DIRTY_FLAG) } FW_GIT_INFO_t; -#define GIT_INFO_SHORT_HASH (0xf36d410bUL) +#define GIT_INFO_SHORT_HASH (0x481e5817UL) #define GIT_INFO_TAG_MAJOR (2) #define GIT_INFO_TAG_MINOR (13) -#define GIT_INFO_TAG_REV (0) -#define GIT_INFO_TAG_BUILD (2) +#define GIT_INFO_TAG_REV (1) +#define GIT_INFO_TAG_BUILD (0) #define GIT_INFO_DETAILS (0x00) #endif // __RAIL_AUTOGEN_VER_DEF_H__ diff --git a/platform/radio/rail_lib/chip/efr32/efr32xg1x/rail_chip_specific.h b/platform/radio/rail_lib/chip/efr32/efr32xg1x/rail_chip_specific.h index 068aab0546..cc487f1fc8 100644 --- a/platform/radio/rail_lib/chip/efr32/efr32xg1x/rail_chip_specific.h +++ b/platform/radio/rail_lib/chip/efr32/efr32xg1x/rail_chip_specific.h @@ -39,6 +39,20 @@ #include "rail_features.h" +#if (defined(DOXYGEN_SHOULD_SKIP_THIS) && !defined(RAIL_ENUM)) +// Copied from rail_types.h to satisfy doxygen build. +/// The RAIL library does not use enumerations because the ARM EABI leaves their +/// size ambiguous, which causes problems if the application is built +/// with different flags than the library. Instead, uint8_t typedefs +/// are used in compiled code for all enumerations. For documentation purposes, this is +/// converted to an actual enumeration since it's much easier to read in Doxygen. +#define RAIL_ENUM(name) enum name +/// This macro is a more generic version of the \ref RAIL_ENUM() macro that +/// allows the size of the type to be overridden instead of forcing the use of +/// a uint8_t. See \ref RAIL_ENUM() for more information. +#define RAIL_ENUM_GENERIC(name, type) enum name +#endif//(defined(DOXYGEN_SHOULD_SKIP_THIS) && !defined(RAIL_ENUM)) + #ifdef __cplusplus extern "C" { #endif diff --git a/platform/radio/rail_lib/chip/efr32/efr32xg2x/rail_chip_specific.h b/platform/radio/rail_lib/chip/efr32/efr32xg2x/rail_chip_specific.h index 39ceff72f8..7d02607632 100644 --- a/platform/radio/rail_lib/chip/efr32/efr32xg2x/rail_chip_specific.h +++ b/platform/radio/rail_lib/chip/efr32/efr32xg2x/rail_chip_specific.h @@ -39,6 +39,20 @@ #include "rail_features.h" +#if (defined(DOXYGEN_SHOULD_SKIP_THIS) && !defined(RAIL_ENUM)) +// Copied from rail_types.h to satisfy doxygen build. +/// The RAIL library does not use enumerations because the ARM EABI leaves their +/// size ambiguous, which causes problems if the application is built +/// with different flags than the library. Instead, uint8_t typedefs +/// are used in compiled code for all enumerations. For documentation purposes, this is +/// converted to an actual enumeration since it's much easier to read in Doxygen. +#define RAIL_ENUM(name) enum name +/// This macro is a more generic version of the \ref RAIL_ENUM() macro that +/// allows the size of the type to be overridden instead of forcing the use of +/// a uint8_t. See \ref RAIL_ENUM() for more information. +#define RAIL_ENUM_GENERIC(name, type) enum name +#endif//(defined(DOXYGEN_SHOULD_SKIP_THIS) && !defined(RAIL_ENUM)) + #ifdef __cplusplus extern "C" { #endif @@ -339,8 +353,8 @@ typedef struct RAIL_AntennaConfig { /** EFR32-specific IR calibration bit */ #define RAIL_CAL_RX_IRCAL (0x00010000U) -#if RAIL_SUPPORTS_OFDM_PA /** EFR32-specific Tx IR calibration bit */ +#if RAIL_SUPPORTS_OFDM_PA #define RAIL_CAL_OFDM_TX_IRCAL (0x00100000U) #else #define RAIL_CAL_OFDM_TX_IRCAL (0U) @@ -377,7 +391,7 @@ typedef struct RAIL_AntennaConfig { #endif /** - * @def RAIL_RF_PATHS_SUBG + * @def RAIL_RF_PATHS_SUBGIG * @brief Indicates the number of sub-GHz RF Paths supported */ #if _SILICON_LABS_32B_SERIES_2_CONFIG == 3 @@ -401,6 +415,10 @@ typedef struct RAIL_AntennaConfig { */ #if RAIL_RF_PATHS > 1 #define RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS 1 +#else +#ifdef DOXYGEN_SHOULD_SKIP_THIS // Leave undefined except for doxygen +#define RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS 0 +#endif//DOXYGEN_SHOULD_SKIP_THIS #endif #if RAIL_SUPPORTS_OFDM_PA @@ -1270,6 +1288,14 @@ RAIL_ENUM(RAIL_TxPowerMode_t) { #endif #endif +/** + * @def RAIL_TX_POWER_MODE_NAMES_2P4GIG + * @brief The names of the TX power modes for 2.4 GHz band. + * + * A list of the names for the TX power modes on the EFR32 series 2 parts + * supporting 2.4 GHz operation. + * This macro is useful for test applications and debugging output. + */ #if RAIL_FEAT_2G4_RADIO #if (_SILICON_LABS_32B_SERIES_2_CONFIG == 1) #define RAIL_TX_POWER_MODE_NAMES_2P4GIG \ @@ -1277,21 +1303,24 @@ RAIL_ENUM(RAIL_TxPowerMode_t) { "RAIL_TX_POWER_MODE_2P4GIG_MP", \ "RAIL_TX_POWER_MODE_2P4GIG_LP", \ "RAIL_TX_POWER_MODE_2P4GIG_HIGHEST", -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) +#else // (_SILICON_LABS_32B_SERIES_2_CONFIG == 2|4|7) #define RAIL_TX_POWER_MODE_NAMES_2P4GIG \ "RAIL_TX_POWER_MODE_2P4GIG_HP", \ "RAIL_TX_POWER_MODE_2P4GIG_LP", \ "RAIL_TX_POWER_MODE_2P4GIG_HIGHEST", -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) -#define RAIL_TX_POWER_MODE_NAMES_2P4GIG \ - "RAIL_TX_POWER_MODE_2P4GIG_HP", \ - "RAIL_TX_POWER_MODE_2P4GIG_HIGHEST", #endif #else #define RAIL_TX_POWER_MODE_NAMES_2P4GIG #endif //RAIL_FEAT_2G4_RADIO + +/** + * @def RAIL_TX_POWER_MODE_NAMES_SUBGIG + * @brief The names of the TX power modes for Sub-GHz band. + * + * A list of the names for the TX power modes on the EFR32 series 2 parts + * supporting Sub-GHz operation. + * This macro is useful for test applications and debugging output. + */ #if RAIL_FEAT_SUBGIG_RADIO #if RAIL_SUPPORTS_EFF #define RAIL_TX_POWER_MODE_NAMES_SUBGIG \ @@ -1312,6 +1341,14 @@ RAIL_ENUM(RAIL_TxPowerMode_t) { #define RAIL_TX_POWER_MODE_NAMES_SUBGIG #endif +/** + * @def RAIL_TX_POWER_MODE_NAMES_OFDM_PA + * @brief The names of the TX power modes for the OFDM PA. + * + * A list of the names for the TX power modes on EFR32 series 2 parts + * with an OFDM PA. + * This macro is useful for test applications and debugging output. + */ #if RAIL_SUPPORTS_OFDM_PA #define RAIL_TX_POWER_MODE_NAMES_OFDM_PA \ "RAIL_TX_POWER_MODE_OFDM_PA", @@ -1319,6 +1356,14 @@ RAIL_ENUM(RAIL_TxPowerMode_t) { #define RAIL_TX_POWER_MODE_NAMES_OFDM_PA #endif +/** + * @def RAIL_TX_POWER_MODE_NAMES_SUBGIG_EFF + * @brief The names of the TX power modes for Sub-GHz band with an EFF. + * + * A list of the names for the Sub-GHz TX power modes on EFR32 series 2 parts + * with an EFF. + * This macro is useful for test applications and debugging output. + */ #if RAIL_SUPPORTS_EFF #if RAIL_FEAT_SUBGIG_RADIO #define RAIL_TX_POWER_MODE_NAMES_SUBGIG_EFF \ @@ -1328,6 +1373,19 @@ RAIL_ENUM(RAIL_TxPowerMode_t) { #else #define RAIL_TX_POWER_MODE_NAMES_SUBGIG_EFF #endif +#else +#define RAIL_TX_POWER_MODE_NAMES_SUBGIG_EFF +#endif//RAIL_SUPPORTS_EFF + +/** + * @def RAIL_TX_POWER_MODE_NAMES_OFDM_PA_EFF + * @brief The names of the TX power modes for the OFDM PA with an EFF. + * + * A list of the names for the TX power modes on EFR32 series 2 parts + * with an OFDM PA and EFF. + * This macro is useful for test applications and debugging output. + */ +#if RAIL_SUPPORTS_EFF #if RAIL_SUPPORTS_OFDM_PA #define RAIL_TX_POWER_MODE_NAMES_OFDM_PA_EFF \ "RAIL_TX_POWER_MODE_OFDM_PA_EFF_30DBM", \ @@ -1338,7 +1396,6 @@ RAIL_ENUM(RAIL_TxPowerMode_t) { #define RAIL_TX_POWER_MODE_NAMES_OFDM_PA_EFF #endif #else -#define RAIL_TX_POWER_MODE_NAMES_SUBGIG_EFF #define RAIL_TX_POWER_MODE_NAMES_OFDM_PA_EFF #endif//RAIL_SUPPORTS_EFF diff --git a/platform/radio/rail_lib/common/rail.h b/platform/radio/rail_lib/common/rail.h index 75c64ad23f..0ea254247b 100644 --- a/platform/radio/rail_lib/common/rail.h +++ b/platform/radio/rail_lib/common/rail.h @@ -6023,6 +6023,251 @@ RAIL_Status_t RAIL_ConfigHFXOThermistor(RAIL_Handle_t railHandle, * @{ */ +/** + * Indicate whether RAIL supports 2.4 GHz band operation on this chip. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if the 2.4 GHz band is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_2P4GHZ_BAND. + */ +bool RAIL_Supports2p4GHzBand(RAIL_Handle_t railHandle); + +/** + * Indicate whether RAIL supports SubGHz band operation on this chip. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if the SubGHz band is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_SUBGHZ_BAND. + */ +bool RAIL_SupportsSubGHzBand(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports dual 2.4 GHz and SubGHz band operation. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if the dual band is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_DUAL_BAND. + */ +bool RAIL_SupportsDualBand(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports bit masked address filtering + * + * @param[in] railHandle A RAIL instance handle. + * @return true if bit masked address filtering is supported; false otherwise. + * + * Runtime refinement of compile-time + * \ref RAIL_SUPPORTS_ADDR_FILTER_ADDRESS_BIT_MASK. + */ +bool RAIL_SupportsAddrFilterAddressBitMask(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports address filter mask information + * for incoming packets in + * \ref RAIL_RxPacketInfo_t::filterMask and + * \ref RAIL_IEEE802154_Address_t::filterMask. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if address filter information is supported; false otherwise + * (in which case \ref RAIL_RxPacketInfo_t::filterMask value is undefined). + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_ADDR_FILTER_MASK. + */ +bool RAIL_SupportsAddrFilterMask(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports alternate TX power settings. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if alternate TX power settings are supported; false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_SUPPORTS_ALTERNATE_TX_POWER. + */ +bool RAIL_SupportsAlternateTxPower(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports antenna diversity. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if antenna diversity is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_ANTENNA_DIVERSITY. + * + * @note Certain radio configurations may not support this feature even + * if the chip in general claims to support it. + */ +bool RAIL_SupportsAntennaDiversity(RAIL_Handle_t railHandle); + +/** + * Indicate whether RAIL supports AUXADC measurements on this chip. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if AUXADC measurements are supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_AUXADC. + */ +bool RAIL_SupportsAuxAdc(RAIL_Handle_t railHandle); + +/** + * Indicate whether RAIL supports channel hopping on this chip. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if channel hopping is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_CHANNEL_HOPPING. + */ +bool RAIL_SupportsChannelHopping(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports direct mode. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if direct mode is supported; false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_SUPPORTS_DIRECT_MODE. + */ +bool RAIL_SupportsDirectMode(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports dual sync words. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if dual sync words are supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_DUAL_SYNC_WORDS. + * + * @note Certain radio configurations may not support this feature even + * if the chip in general claims to support it. + */ +bool RAIL_SupportsDualSyncWords(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports EFF. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if EFF identifier is supported; false otherwise. + */ +bool RAIL_SupportsEff(RAIL_Handle_t railHandle); + +/** + * Indicate whether RAIL supports thermistor measurements on this chip. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if thermistor measurements are supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_EXTERNAL_THERMISTOR. + */ +bool RAIL_SupportsExternalThermistor(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports MFM protocol. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if MFM protocol is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_MFM. + */ +bool RAIL_SupportsMfm(RAIL_Handle_t railHandle); + +/** + * Indicate whether RAIL supports OFDM band operation on this chip. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if OFDM operation is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_OFDM_PA. + */ +bool RAIL_SupportsOFDMPA(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports a high-precision LFRCO. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if high-precision LFRCO is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_PRECISION_LFRCO. + */ +bool RAIL_SupportsPrecisionLFRCO(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports radio entropy. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if radio entropy is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_RADIO_ENTROPY. + */ +bool RAIL_SupportsRadioEntropy(RAIL_Handle_t railHandle); + +/** + * Indicate whether RAIL supports RFSENSE Energy Detection Mode on this chip. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if RFSENSE Energy Detection Mode is supported; false otherwise. + * + * Runtime refinement of compile-time + * \ref RAIL_SUPPORTS_RFSENSE_ENERGY_DETECTION. + */ +bool RAIL_SupportsRfSenseEnergyDetection(RAIL_Handle_t railHandle); + +/** + * Indicate whether RAIL supports RFSENSE Selective(OOK) Mode on this chip. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if RFSENSE Selective(OOK) Mode is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_RFSENSE_SELECTIVE_OOK. + */ +bool RAIL_SupportsRfSenseSelectiveOok(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports configurable RSSI threshold + * set by \ref RAIL_SetRssiDetectThreshold(). + * + * @param[in] railHandle A RAIL instance handle. + * @return true if setting configurable RSSI is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_RSSI_DETECT_THRESHOLD. + */ +bool RAIL_SupportsRssiDetectThreshold(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports RX direct mode data to FIFO. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if direct mode data to FIFO is supported; false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_SUPPORTS_RX_DIRECT_MODE_DATA_TO_FIFO. + */ +bool RAIL_SupportsRxDirectModeDataToFifo(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports raw RX data + * sources other than \ref RAIL_RxDataSource_t::RX_PACKET_DATA. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if direct mode is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_RX_RAW_DATA. + */ +bool RAIL_SupportsRxRawData(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports SQ-based PHY. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if the SQ-based PHY is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_SQ_PHY. + */ +bool RAIL_SupportsSQPhy(RAIL_Handle_t railHandle); + /** * Indicate whether this chip supports a particular power mode (PA). * @note Consider using \ref RAIL_SupportsTxPowerModeAlt to also get the power @@ -6064,6 +6309,412 @@ bool RAIL_SupportsTxPowerModeAlt(RAIL_Handle_t railHandle, RAIL_TxPowerLevel_t *maxPowerLevel, RAIL_TxPowerLevel_t *minPowerLevel); +/** + * Indicate whether this chip supports automatic TX to TX transitions. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if TX to TX transitions are supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_TX_TO_TX. + */ +bool RAIL_SupportsTxToTx(RAIL_Handle_t railHandle); + +/** + * Indicate whether RAIL supports the BLE protocol on this chip. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_PROTOCOL_BLE. + */ +bool RAIL_SupportsProtocolBLE(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports BLE 1Mbps Non-Viterbi PHY. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE 1Mbps Non-Viterbi is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_1MBPS_NON_VITERBI. + */ +bool RAIL_BLE_Supports1MbpsNonViterbi(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports BLE 1Mbps Viterbi PHY. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE 1Mbps Viterbi is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_1MBPS_VITERBI. + */ +bool RAIL_BLE_Supports1MbpsViterbi(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports BLE 1Mbps operation. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE 1Mbps operation is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_1MBPS. + */ +static inline +bool RAIL_BLE_Supports1Mbps(RAIL_Handle_t railHandle) +{ + return (RAIL_BLE_Supports1MbpsNonViterbi(railHandle) + || RAIL_BLE_Supports1MbpsViterbi(railHandle)); +} + +/** + * Indicate whether this chip supports BLE 2Mbps Non-Viterbi PHY. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE 2Mbps Non-Viterbi is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_2MBPS_NON_VITERBI. + */ +bool RAIL_BLE_Supports2MbpsNonViterbi(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports BLE 2Mbps Viterbi PHY. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE 2Mbps Viterbi is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_2MBPS_VITERBI. + */ +bool RAIL_BLE_Supports2MbpsViterbi(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports BLE 2Mbps operation. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE 2Mbps operation is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_2MBPS. + */ +static inline +bool RAIL_BLE_Supports2Mbps(RAIL_Handle_t railHandle) +{ + return (RAIL_BLE_Supports2MbpsNonViterbi(railHandle) + || RAIL_BLE_Supports2MbpsViterbi(railHandle)); +} + +/** + * Indicate whether this chip supports BLE Antenna Switching needed for + * Angle-of-Arrival receives or Angle-of-Departure transmits. + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE Antenna Switching is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_ANTENNA_SWITCHING. + */ +bool RAIL_BLE_SupportsAntennaSwitching(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports BLE Coded PHY used for Long-Range. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE Coded PHY is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_CODED_PHY. + */ +bool RAIL_BLE_SupportsCodedPhy(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports BLE CTE (Constant Tone Extension) + * needed for Angle-of-Arrival/Departure transmits. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE CTE is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_CTE. + */ +bool RAIL_BLE_SupportsCte(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports BLE IQ Sampling needed for + * Angle-of-Arrival/Departure receives. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE IQ Sampling is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_IQ_SAMPLING. + */ +bool RAIL_BLE_SupportsIQSampling(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports BLE PHY switch to RX + * functionality, which is used to switch BLE PHYs at a specific time + * to receive auxiliary packets. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE PHY switch to RX is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_PHY_SWITCH_TO_RX. + */ +bool RAIL_BLE_SupportsPhySwitchToRx(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports the Quuppa PHY. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if the Quuppa is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_QUUPPA. + */ +bool RAIL_BLE_SupportsQuuppa(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports BLE signal identifier. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if signal identifier is supported; false otherwise. + */ +bool RAIL_BLE_SupportsSignalIdentifier(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports BLE Simulscan PHY used for simultaneous + * BLE 1Mbps and Coded PHY reception. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE Simulscan PHY is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_SIMULSCAN_PHY. + */ +bool RAIL_BLE_SupportsSimulscanPhy(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports the IEEE 802.15.4 protocol. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if the 802.15.4 protocol is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_PROTOCOL_IEEE802154. + */ +bool RAIL_SupportsProtocolIEEE802154(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports the IEEE 802.15.4 Wi-Fi Coexistence PHY. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if the 802.15.4 COEX PHY is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_IEEE802154_SUPPORTS_COEX_PHY. + */ +bool RAIL_IEEE802154_SupportsCoexPhy(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports the IEEE 802.15.4 PHY with custom settings. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if the 802.15.4 PHY with custom settings is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_IEEE802154_SUPPORTS_CUSTOM1_PHY. + */ +bool RAIL_IEEE802154_SupportsCustom1Phy(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports the IEEE 802.15.4 + * front end module optimized PHY. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if a front end module is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_IEEE802154_SUPPORTS_FEM_PHY. + */ +bool RAIL_IEEE802154_SupportsFemPhy(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports canceling the frame-pending lookup + * event \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND when the radio + * transitions to a state that renders the the reporting of this event moot + * (i.e., too late for the stack to influence the outgoing ACK). + * + * @param[in] railHandle A RAIL instance handle. + * @return true if canceling the lookup event is supported; false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_IEEE802154_SUPPORTS_CANCEL_FRAME_PENDING_LOOKUP. + */ +bool RAIL_IEEE802154_SupportsCancelFramePendingLookup(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports early triggering of the frame-pending + * lookup event \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND + * just after MAC address fields have been received. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if early triggering is supported; false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_IEEE802154_SUPPORTS_EARLY_FRAME_PENDING_LOOKUP. + */ +bool RAIL_IEEE802154_SupportsEarlyFramePendingLookup(RAIL_Handle_t railHandle); + +/** + * Indicate whether RAIL supports dual PA mode on this chip. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if the dual PA mode is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_IEEE802154_SUPPORTS_DUAL_PA_CONFIG. + */ +bool RAIL_IEEE802154_SupportsDualPaConfig(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports IEEE 802.15.4E-2012 Enhanced ACKing. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if 802.15.4E Enhanced ACKing is supported; false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_IEEE802154_SUPPORTS_E_ENHANCED_ACK. + */ +bool RAIL_IEEE802154_SupportsEEnhancedAck(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports IEEE 802.15.4E-2012 Multipurpose frame + * reception. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if Multipurpose frame reception is supported; false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_IEEE802154_SUPPORTS_E_MULTIPURPOSE_FRAMES. + */ +bool RAIL_IEEE802154_SupportsEMultipurposeFrames(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports the IEEE 802.15.4E-2012 feature + * subset needed for Zigbee R22 GB868. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if 802.15.4E GB868 subset is supported; false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_IEEE802154_SUPPORTS_E_SUBSET_GB868. + */ +bool RAIL_IEEE802154_SupportsESubsetGB868(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports IEEE 802.15.4G-2012 reception and + * transmission of frames with 4-byte CRC. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if 802.15.4G 4-byte CRC is supported; false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_IEEE802154_SUPPORTS_G_4BYTE_CRC. + */ +bool RAIL_IEEE802154_SupportsG4ByteCrc(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports IEEE 802.15.4G dynamic FEC + * + * @param[in] railHandle A RAIL instance handle. + * @return true if dynamic FEC is supported; false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_IEEE802154_SUPPORTS_G_DYNFEC. + */ +bool RAIL_IEEE802154_SupportsGDynFec(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports Wi-SUN mode switching + * + * @param[in] railHandle A RAIL instance handle. + * @return true if Wi-SUN mode switching is supported; false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_IEEE802154_SUPPORTS_G_MODESWITCH. + */ +bool RAIL_IEEE802154_SupportsGModeSwitch(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports IEEE 802.15.4G-2012 feature + * subset needed for Zigbee R22 GB868. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if 802.15.4G GB868 subset is supported; false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868. + */ +bool RAIL_IEEE802154_SupportsGSubsetGB868(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports IEEE 802.15.4G-2012 reception + * of unwhitened frames. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if 802.15.4G unwhitened frame reception is supported; + * false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_RX. + */ +bool RAIL_IEEE802154_SupportsGUnwhitenedRx(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports IEEE 802.15.4G-2012 transmission + * of unwhitened frames. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if 802.15.4G unwhitened frame transmit is supported; + * false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_TX. + */ +bool RAIL_IEEE802154_SupportsGUnwhitenedTx(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports the Z-Wave protocol. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if the Z-Wave protocol is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_PROTOCOL_ZWAVE. + */ +bool RAIL_SupportsProtocolZWave(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports the Z-Wave concurrent PHY. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if the Z-Wave concurrent PHY is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_ZWAVE_SUPPORTS_CONC_PHY. + */ +bool RAIL_ZWAVE_SupportsConcPhy(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports the Z-Wave energy detect PHY. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if the Z-Wave energy detect PHY is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_ZWAVE_SUPPORTS_ED_PHY. + */ +bool RAIL_ZWAVE_SupportsEnergyDetectPhy(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports Z-Wave Region in PTI. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if ZWAVE Region in PTI is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_ZWAVE_SUPPORTS_REGION_PTI. + */ +bool RAIL_ZWAVE_SupportsRegionPti(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports IEEE 802.15.4 signal identifier. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if signal identifier is supported; false otherwise. + */ +bool RAIL_IEEE802154_SupportsSignalIdentifier(RAIL_Handle_t railHandle); + /** @} */ // end of group Features /** @} */ // end of group RAIL_API diff --git a/platform/radio/rail_lib/common/rail_assert_error_codes.h b/platform/radio/rail_lib/common/rail_assert_error_codes.h index e9ada19089..83b9978a2e 100644 --- a/platform/radio/rail_lib/common/rail_assert_error_codes.h +++ b/platform/radio/rail_lib/common/rail_assert_error_codes.h @@ -49,83 +49,161 @@ extern "C" { */ RAIL_ENUM_GENERIC(RAIL_AssertErrorCodes_t, uint32_t) { + /** Appended info missing from Rx packet. */ RAIL_ASSERT_FAILED_APPENDED_INFO_MISSING = 0, + /** Receive FIFO too small for IR calibration. */ RAIL_ASSERT_FAILED_RX_FIFO_BYTES = 1, + /** Error reading back packet payload. */ RAIL_ASSERT_FAILED_RX_FIFO_ZERO_BYTES_READ = 2, + /** Receive fifo entry has invalid status. */ RAIL_ASSERT_FAILED_ILLEGAL_RXLEN_ENTRY_STATUS = 3, + /** Receive fifo entry bad packet length. */ RAIL_ASSERT_FAILED_BAD_PACKET_LENGTH = 4, + /** Unable to configure radio for IR calibration. */ RAIL_ASSERT_FAILED_SYNTH_DIVCTRL_ENUM_CONVERSION_ERROR = 5, + /** Reached unexpected state while handling Rx fifo events. */ RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RX_FIFO = 6, + /** Reached unexpected state while handling RXLEN fifo events. */ RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RXLEN_FIFO = 7, + /** Reached unexpected state while handling Tx fifo events. */ RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TX_FIFO = 8, + /** Reached unexpected state while handling Tx ACK fifo events. */ RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TXACK_FIFO = 9, + /** No memory to store receive packet. */ RAIL_ASSERT_FAILED_PBUFFER_NOT_DEFINED = 10, + /** Packet length longer than the receive FIFO size. */ RAIL_ASSERT_FAILED_INSUFFICIENT_BYTES_IN_RX_PACKET = 11, + /** Invalid radio clock prescaler. */ RAIL_ASSERT_FAILED_CLOCK_PRESCALER = 12, + /** Error synchronizing the RAIL timebase after sleep. */ RAIL_ASSERT_FAILED_RTCC_POST_WAKEUP = 13, + /** VCO frequency outside supported range. */ RAIL_ASSERT_FAILED_SYNTH_VCO_FREQUENCY = 14, + /** Radio active while changing channels. */ RAIL_ASSERT_FAILED_RAC_STATE = 15, + /** Invalid Synth VCOCTRL field calculation. */ RAIL_ASSERT_FAILED_SYNTH_INVALID_VCOCTRL = 16, + /** Nested attempt to lock the sequencer. */ RAIL_ASSERT_FAILED_NESTED_SEQUENCER_LOCK = 17, + /** RSSI averaging enabled without a valid callback. */ RAIL_ASSERT_FAILED_RSSI_AVERAGE_DONE = 18, + /** Invalid dynamic frame length setting provided (dflBits). */ RAIL_ASSERT_FAILED_DFL_BITS_SIZE = 19, + /** Unable to seed radio pseudo random number generator. */ RAIL_ASSERT_FAILED_PROTIMER_RANDOM_SEED = 20, + /** Timeout exceeds EFR32XG1 register size. */ RAIL_ASSERT_FAILED_EFR32XG1_REGISTER_SIZE = 21, + /** Invalid timer channel specified. */ RAIL_ASSERT_FAILED_PROTIMER_CHANNEL = 22, + /** Timer value larger than RAIL timebase. */ RAIL_ASSERT_FAILED_TIMER_REQUIRES_WRAP = 23, + /** LBT config exceeds EFR32XG1 register size. */ RAIL_ASSERT_FAILED_BASECNTTOP = 24, + /** Deprecated CSMA/LBT retry callback unexpectedly called. */ RAIL_ASSERT_FAILED_DEPRECATED_LBTRETRY = 25, + /** Could not synchronize RAIL timebase with the RTC. */ RAIL_ASSERT_FAILED_RTCC_SYNC_MISSED = 26, + /** Clock source not ready. */ RAIL_ASSERT_FAILED_CLOCK_SOURCE_NOT_READY = 27, + /** Attempted to set RAIL timings to invalid value. */ RAIL_ASSERT_FAILED_TIMINGS_INVALID = 28, + /** NULL was supplied as a RAIL_Handle_t argument. */ RAIL_ASSERT_NULL_HANDLE = 29, + /** Scheduled timer not running. */ RAIL_ASSERT_FAILED_SCHED_TIMER_NOT_RUNNING = 30, + /** API improperly called while protocol inactive. */ RAIL_ASSERT_FAILED_NO_ACTIVE_CONFIG = 31, + /** No active handle after switch. */ RAIL_ASSERT_FAILED_NO_ACTIVE_HANDLE_SWITCH = 32, + /** Reserved for future use. */ RAIL_ASSERT_FAILED_RESERVED33 = 33, + /** No active handle for scheduled rx. */ RAIL_ASSERT_FAILED_NO_ACTIVE_HANDLE_SCHEDRX = 34, + /** Invalid handle for scheduled tx. */ RAIL_ASSERT_FAILED_INVALID_HANDLE_SCHEDTX = 35, + /** Inactive handle for scheduled tx. */ RAIL_ASSERT_FAILED_INACTIVE_HANDLE_SCHEDTX = 36, + /** Invalid config index to switch to. */ RAIL_ASSERT_FAILED_CONFIG_INDEX_INVALID = 37, + /** No active handle for single protocol. */ RAIL_ASSERT_FAILED_NO_ACTIVE_HANDLE_SINGLEPROTOCOL = 38, + /** This function is deprecated and must not be called. */ RAIL_ASSERT_DEPRECATED_FUNCTION = 39, + /** Multiprotocol task started with no event to run. */ RAIL_ASSERT_MULTIPROTOCOL_NO_EVENT = 40, + /** Invalid interrupt enabled. */ RAIL_ASSERT_FAILED_INVALID_INTERRUPT_ENABLED = 41, + /** Power conversion functions called before curves were initialized. */ RAIL_ASSERT_CONVERSION_CURVES_NOT_INITIALIZED = 42, + /** Division by zero. */ RAIL_ASSERT_DIVISION_BY_ZERO = 43, + /** Function cannot be called without access to the hardware. */ RAIL_ASSERT_CANT_USE_HARDWARE = 44, + /** Pointer parameter was passed as NULL. */ RAIL_ASSERT_NULL_PARAMETER = 45, + /** Invalid task type passed to RAIL_SetTaskPriority. */ RAIL_ASSERT_INVALID_TASK_TYPE = 46, + /** Synth radio config buffer for channel hopping too small. */ RAIL_ASSERT_SMALL_SYNTH_RADIO_CONFIG_BUFFER = 47, + /** Buffer provided for RX Channel Hopping is too small. */ RAIL_ASSERT_CHANNEL_HOPPING_BUFFER_TOO_SHORT = 48, + /** Invalid action was attempted on a module. */ RAIL_ASSERT_INVALID_MODULE_ACTION = 49, + /** The radio config for this channel is not compatible with channel hopping. */ RAIL_ASSERT_CHANNEL_HOPPING_INVALID_RADIO_CONFIG = 50, + /** Channel change failed. */ RAIL_ASSERT_CHANNEL_CHANGE_FAILED = 51, + /** Attempted to read invalid register. */ RAIL_ASSERT_INVALID_REGISTER = 52, + /** Can't read register value from NULL state. */ RAIL_ASSERT_FAILED_LO_DIV_NULL_STATE = 53, + /** DMP radio config caching failed. */ RAIL_ASSERT_CACHE_CONFIG_FAILED = 54, + /** NULL was supplied as a RAIL_StateTransitions_t argument. */ RAIL_ASSERT_NULL_TRANSITIONS = 55, + /** LDMA transfer failed. */ RAIL_ASSERT_BAD_LDMA_TRANSFER = 56, + /** Attempted to wake up with invalid RTCC sync data. */ RAIL_ASSERT_INVALID_RTCC_SYNC_VALUES = 57, + /** Radio sequencer hit a fault condition. */ RAIL_ASSERT_SEQUENCER_FAULT = 58, + /** Bus fault. */ RAIL_ASSERT_BUS_ERROR = 59, + /** The current radio config cannot be used with packet filtering. */ RAIL_ASSERT_INVALID_FILTERING_CONFIG = 60, + /** Retiming configuration error. */ RAIL_ASSERT_RETIMING_CONFIG = 61, + /** TX CRC configuration is corrupt. */ RAIL_ASSERT_FAILED_TX_CRC_CONFIG = 62, + /** The current PA config does not allow for this operation. */ RAIL_ASSERT_INVALID_PA_OPERATION = 63, + /** The sequencer selected an invalid PA. */ RAIL_ASSERT_SEQ_INVALID_PA_SELECTED = 64, + /** Invalid/unsupported channel config. */ RAIL_ASSERT_FAILED_INVALID_CHANNEL_CONFIG = 65, + /** The dynamic frame length configuration is invalid. */ RAIL_ASSERT_INVALID_DYNAMIC_FRAME_LENGTH = 66, + /** Failed to enable EM1P energy mode. */ RAIL_ASSERT_FAILED_EM1P_ENTRY = 67, + /** Failed to disable EM1P energy mode. */ RAIL_ASSERT_FAILED_EM1P_EXIT = 68, + /** Failed to disable RTCC synchronization. */ RAIL_ASSERT_FAILED_RTCC_SYNC_STOP = 69, + /** Multitimer linked list corrupted. */ RAIL_ASSERT_FAILED_MULTITIMER_CORRUPT = 70, + /** Unable to configure radio for temperature calibration. */ RAIL_ASSERT_FAILED_TEMPCAL_ERROR = 71, + /** Invalid EFF configuration. */ RAIL_ASSERT_INVALID_EFF_CONFIGURATION = 72, + /** Invalid RFFPLL configuration. */ RAIL_ASSERT_INVALID_RFFPLL_CONFIGURATION = 73, + /** Secure access fault. */ RAIL_ASSERT_SECURE_ACCESS_FAULT = 74, + /** SYSRTC0 not running. */ RAIL_ASSERT_FAILED_SYSRTC0_NOT_RUNNING = 75, + /** Radio Configurator not updated. */ RAIL_ASSERT_RADIO_CONFIG_NOT_UP_TO_DATE = 76, + /** Failed to set the event for configurable RSSI threshold. */ RAIL_ASSERT_FAILED_RSSI_THRESHOLD = 77, }; diff --git a/platform/radio/rail_lib/common/rail_features.h b/platform/radio/rail_lib/common/rail_features.h index 02e0e8c3a1..3d12752378 100644 --- a/platform/radio/rail_lib/common/rail_features.h +++ b/platform/radio/rail_lib/common/rail_features.h @@ -28,12 +28,12 @@ * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ -#include "em_device.h" -#include "rail_types.h" #ifndef __RAIL_FEATURES_H__ #define __RAIL_FEATURES_H__ +#include "em_device.h" + #ifdef __cplusplus extern "C" { #endif @@ -73,16 +73,6 @@ extern "C" { /// Backwards-compatible synonym of \ref RAIL_SUPPORTS_DUAL_BAND. #define RAIL_FEAT_DUAL_BAND_RADIO RAIL_SUPPORTS_DUAL_BAND -/** - * Indicate whether this chip supports dual 2.4 GHz and SubGHz band operation. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if the dual band is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_DUAL_BAND. - */ -bool RAIL_SupportsDualBand(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports the 2.4 GHz band. /// See also runtime refinement \ref RAIL_Supports2p4GHzBand(). #if (((_SILICON_LABS_EFR32_RADIO_TYPE == _SILICON_LABS_EFR32_RADIO_DUALBAND) \ @@ -95,16 +85,6 @@ bool RAIL_SupportsDualBand(RAIL_Handle_t railHandle); /// Backwards-compatible synonym of \ref RAIL_SUPPORTS_2P4GHZ_BAND. #define RAIL_FEAT_2G4_RADIO RAIL_SUPPORTS_2P4GHZ_BAND -/** - * Indicate whether RAIL supports 2.4 GHz band operation on this chip. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if the 2.4 GHz band is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_2P4GHZ_BAND. - */ -bool RAIL_Supports2p4GHzBand(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports SubGHz bands. /// See also runtime refinement \ref RAIL_SupportsSubGHzBand(). #if (((_SILICON_LABS_EFR32_RADIO_TYPE == _SILICON_LABS_EFR32_RADIO_DUALBAND) \ @@ -117,16 +97,6 @@ bool RAIL_Supports2p4GHzBand(RAIL_Handle_t railHandle); /// Backwards-compatible synonym of \ref RAIL_SUPPORTS_SUBGHZ_BAND. #define RAIL_FEAT_SUBGIG_RADIO RAIL_SUPPORTS_SUBGHZ_BAND -/** - * Indicate whether RAIL supports SubGHz band operation on this chip. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if the SubGHz band is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_SUBGHZ_BAND. - */ -bool RAIL_SupportsSubGHzBand(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports OFDM PA. /// See also runtime refinement \ref RAIL_SupportsOFDMPA(). #if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) @@ -135,16 +105,6 @@ bool RAIL_SupportsSubGHzBand(RAIL_Handle_t railHandle); #define RAIL_SUPPORTS_OFDM_PA 0 #endif -/** - * Indicate whether RAIL supports OFDM band operation on this chip. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if OFDM operation is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_OFDM_PA. - */ -bool RAIL_SupportsOFDMPA(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports /// bit masked address filtering. /// See also runtime refinement \ref RAIL_SupportsAddrFilterAddressBitMask(). @@ -154,17 +114,6 @@ bool RAIL_SupportsOFDMPA(RAIL_Handle_t railHandle); #define RAIL_SUPPORTS_ADDR_FILTER_ADDRESS_BIT_MASK 0 #endif -/** - * Indicate whether this chip supports bit masked address filtering - * - * @param[in] railHandle A RAIL instance handle. - * @return true if bit masked address filtering is supported; false otherwise. - * - * Runtime refinement of compile-time - * \ref RAIL_SUPPORTS_ADDR_FILTER_ADDRESS_BIT_MASK. - */ -bool RAIL_SupportsAddrFilterAddressBitMask(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports /// address filter mask information for incoming packets in /// \ref RAIL_RxPacketInfo_t::filterMask and @@ -176,20 +125,6 @@ bool RAIL_SupportsAddrFilterAddressBitMask(RAIL_Handle_t railHandle); #define RAIL_SUPPORTS_ADDR_FILTER_MASK 0 #endif -/** - * Indicate whether this chip supports address filter mask information - * for incoming packets in - * \ref RAIL_RxPacketInfo_t::filterMask and - * \ref RAIL_IEEE802154_Address_t::filterMask. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if address filter information is supported; false otherwise - * (in which case \ref RAIL_RxPacketInfo_t::filterMask value is undefined). - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_ADDR_FILTER_MASK. - */ -bool RAIL_SupportsAddrFilterMask(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports /// alternate power settings for the Power Amplifier. /// See also runtime refinement \ref RAIL_SupportsAlternateTxPower(). @@ -201,17 +136,6 @@ bool RAIL_SupportsAddrFilterMask(RAIL_Handle_t railHandle); /// Backwards-compatible synonym of \ref RAIL_SUPPORTS_ALTERNATE_TX_POWER. #define RAIL_FEAT_ALTERNATE_POWER_TX_SUPPORTED RAIL_SUPPORTS_ALTERNATE_TX_POWER -/** - * Indicate whether this chip supports alternate TX power settings. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if alternate TX power settings are supported; false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_SUPPORTS_ALTERNATE_TX_POWER. - */ -bool RAIL_SupportsAlternateTxPower(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports antenna diversity. /// See also runtime refinement \ref RAIL_SupportsAntennaDiversity(). #if ((_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) \ @@ -230,19 +154,6 @@ bool RAIL_SupportsAlternateTxPower(RAIL_Handle_t railHandle); #define RAIL_SUPPORTS_PATH_DIVERSITY 0 #endif -/** - * Indicate whether this chip supports antenna diversity. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if antenna diversity is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_ANTENNA_DIVERSITY. - * - * @note Certain radio configurations may not support this feature even - * if the chip in general claims to support it. - */ -bool RAIL_SupportsAntennaDiversity(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports channel hopping. /// See also runtime refinement \ref RAIL_SupportsChannelHopping(). #if ((_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG >= 1)) @@ -253,16 +164,6 @@ bool RAIL_SupportsAntennaDiversity(RAIL_Handle_t railHandle); /// Backwards-compatible synonym of \ref RAIL_SUPPORTS_CHANNEL_HOPPING. #define RAIL_FEAT_CHANNEL_HOPPING RAIL_SUPPORTS_CHANNEL_HOPPING -/** - * Indicate whether RAIL supports channel hopping on this chip. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if channel hopping is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_CHANNEL_HOPPING. - */ -bool RAIL_SupportsChannelHopping(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports dual sync words. /// See also runtime refinement \ref RAIL_SupportsDualSyncWords(). #if 1 @@ -271,19 +172,6 @@ bool RAIL_SupportsChannelHopping(RAIL_Handle_t railHandle); #define RAIL_SUPPORTS_DUAL_SYNC_WORDS 0 #endif -/** - * Indicate whether this chip supports dual sync words. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if dual sync words are supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_DUAL_SYNC_WORDS. - * - * @note Certain radio configurations may not support this feature even - * if the chip in general claims to support it. - */ -bool RAIL_SupportsDualSyncWords(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports automatic transitions /// from TX to TX. /// See also runtime refinement \ref RAIL_SupportsTxToTx(). @@ -293,16 +181,6 @@ bool RAIL_SupportsDualSyncWords(RAIL_Handle_t railHandle); #define RAIL_SUPPORTS_TX_TO_TX 0 #endif -/** - * Indicate whether this chip supports automatic TX to TX transitions. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if TX to TX transitions are supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_TX_TO_TX. - */ -bool RAIL_SupportsTxToTx(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports thermistor measurements. /// See also runtime refinement \ref RAIL_SupportsExternalThermistor(). #if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ @@ -316,16 +194,6 @@ bool RAIL_SupportsTxToTx(RAIL_Handle_t railHandle); /// Backwards-compatible synonym of \ref RAIL_SUPPORTS_EXTERNAL_THERMISTOR. #define RAIL_FEAT_EXTERNAL_THERMISTOR RAIL_SUPPORTS_EXTERNAL_THERMISTOR -/** - * Indicate whether RAIL supports thermistor measurements on this chip. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if thermistor measurements are supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_EXTERNAL_THERMISTOR. - */ -bool RAIL_SupportsExternalThermistor(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports AUXADC measurements. /// See also runtime refinement \ref RAIL_SupportsAuxAdc(). #if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ @@ -335,16 +203,6 @@ bool RAIL_SupportsExternalThermistor(RAIL_Handle_t railHandle); #define RAIL_SUPPORTS_AUXADC 0 #endif -/** - * Indicate whether RAIL supports AUXADC measurements on this chip. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if AUXADC measurements are supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_AUXADC. - */ -bool RAIL_SupportsAuxAdc(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports a high-precision /// LFRCO. /// Best to use the runtime refinement \ref RAIL_SupportsPrecisionLFRCO() @@ -355,16 +213,6 @@ bool RAIL_SupportsAuxAdc(RAIL_Handle_t railHandle); #define RAIL_SUPPORTS_PRECISION_LFRCO 0 #endif -/** - * Indicate whether this chip supports a high-precision LFRCO. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if high-precision LFRCO is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_PRECISION_LFRCO. - */ -bool RAIL_SupportsPrecisionLFRCO(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports radio entropy. /// See also runtime refinement \ref RAIL_SupportsRadioEntropy(). #if 1 @@ -373,16 +221,6 @@ bool RAIL_SupportsPrecisionLFRCO(RAIL_Handle_t railHandle); #define RAIL_SUPPORTS_RADIO_ENTROPY 0 #endif -/** - * Indicate whether this chip supports radio entropy. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if radio entropy is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_RADIO_ENTROPY. - */ -bool RAIL_SupportsRadioEntropy(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports /// RFSENSE Energy Detection Mode. /// See also runtime refinement \ref RAIL_SupportsRfSenseEnergyDetection(). @@ -392,17 +230,6 @@ bool RAIL_SupportsRadioEntropy(RAIL_Handle_t railHandle); #define RAIL_SUPPORTS_RFSENSE_ENERGY_DETECTION 0 #endif -/** - * Indicate whether RAIL supports RFSENSE Energy Detection Mode on this chip. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if RFSENSE Energy Detection Mode is supported; false otherwise. - * - * Runtime refinement of compile-time - * \ref RAIL_SUPPORTS_RFSENSE_ENERGY_DETECTION. - */ -bool RAIL_SupportsRfSenseEnergyDetection(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports /// RFSENSE Selective(OOK) Mode. /// See also runtime refinement \ref RAIL_SupportsRfSenseSelectiveOok(). @@ -415,16 +242,6 @@ bool RAIL_SupportsRfSenseEnergyDetection(RAIL_Handle_t railHandle); #define RAIL_FEAT_RFSENSE_SELECTIVE_OOK_MODE_SUPPORTED \ RAIL_SUPPORTS_RFSENSE_SELECTIVE_OOK -/** - * Indicate whether RAIL supports RFSENSE Selective(OOK) Mode on this chip. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if RFSENSE Selective(OOK) Mode is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_RFSENSE_SELECTIVE_OOK. - */ -bool RAIL_SupportsRfSenseSelectiveOok(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports the Energy Friendly /// Front End Module (EFF). /// See also runtime refinement \ref RAIL_SupportsEff(). @@ -434,14 +251,6 @@ bool RAIL_SupportsRfSenseSelectiveOok(RAIL_Handle_t railHandle); #define RAIL_SUPPORTS_EFF 0 #endif -/** - * Indicate whether this chip supports EFF. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if EFF identifier is supported; false otherwise. - */ -bool RAIL_SupportsEff(RAIL_Handle_t railHandle); - // BLE features // Some features may not be available on all platforms // due to radio hardware limitations. @@ -454,16 +263,6 @@ bool RAIL_SupportsEff(RAIL_Handle_t railHandle); #define RAIL_SUPPORTS_PROTOCOL_BLE 0 #endif -/** - * Indicate whether RAIL supports the BLE protocol on this chip. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_PROTOCOL_BLE. - */ -bool RAIL_SupportsProtocolBLE(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports BLE 1Mbps /// Non-Viterbi PHY. /// See also runtime refinement \ref RAIL_BLE_Supports1MbpsNonViterbi(). @@ -473,16 +272,6 @@ bool RAIL_SupportsProtocolBLE(RAIL_Handle_t railHandle); #define RAIL_BLE_SUPPORTS_1MBPS_NON_VITERBI 0 #endif -/** - * Indicate whether this chip supports BLE 1Mbps Non-Viterbi PHY. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE 1Mbps Non-Viterbi is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_1MBPS_NON_VITERBI. - */ -bool RAIL_BLE_Supports1MbpsNonViterbi(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports BLE 1Mbps Viterbi /// PHY. /// See also runtime refinement \ref RAIL_BLE_Supports1MbpsViterbi(). @@ -492,36 +281,11 @@ bool RAIL_BLE_Supports1MbpsNonViterbi(RAIL_Handle_t railHandle); #define RAIL_BLE_SUPPORTS_1MBPS_VITERBI 0 #endif -/** - * Indicate whether this chip supports BLE 1Mbps Viterbi PHY. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE 1Mbps Viterbi is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_1MBPS_VITERBI. - */ -bool RAIL_BLE_Supports1MbpsViterbi(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports BLE 1Mbps operation. /// See also runtime refinement \ref RAIL_BLE_Supports1Mbps(). #define RAIL_BLE_SUPPORTS_1MBPS \ (RAIL_BLE_SUPPORTS_1MBPS_NON_VITERBI || RAIL_BLE_SUPPORTS_1MBPS_VITERBI) -/** - * Indicate whether this chip supports BLE 1Mbps operation. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE 1Mbps operation is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_1MBPS. - */ -static inline -bool RAIL_BLE_Supports1Mbps(RAIL_Handle_t railHandle) -{ - return (RAIL_BLE_Supports1MbpsNonViterbi(railHandle) - || RAIL_BLE_Supports1MbpsViterbi(railHandle)); -} - /// Boolean to indicate whether the selected chip supports BLE 2Mbps /// Non-Viterbi PHY. /// See also runtime refinement \ref RAIL_BLE_Supports2MbpsNonViterbi(). @@ -531,16 +295,6 @@ bool RAIL_BLE_Supports1Mbps(RAIL_Handle_t railHandle) #define RAIL_BLE_SUPPORTS_2MBPS_NON_VITERBI 0 #endif -/** - * Indicate whether this chip supports BLE 2Mbps Non-Viterbi PHY. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE 2Mbps Non-Viterbi is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_2MBPS_NON_VITERBI. - */ -bool RAIL_BLE_Supports2MbpsNonViterbi(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports BLE 2Mbps Viterbi /// PHY. /// See also runtime refinement \ref RAIL_BLE_Supports2MbpsViterbi(). @@ -550,36 +304,11 @@ bool RAIL_BLE_Supports2MbpsNonViterbi(RAIL_Handle_t railHandle); #define RAIL_BLE_SUPPORTS_2MBPS_VITERBI 0 #endif -/** - * Indicate whether this chip supports BLE 2Mbps Viterbi PHY. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE 2Mbps Viterbi is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_2MBPS_VITERBI. - */ -bool RAIL_BLE_Supports2MbpsViterbi(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports BLE 2Mbps operation. /// See also runtime refinement \ref RAIL_BLE_Supports2Mbps(). #define RAIL_BLE_SUPPORTS_2MBPS \ (RAIL_BLE_SUPPORTS_2MBPS_NON_VITERBI || RAIL_BLE_SUPPORTS_2MBPS_VITERBI) -/** - * Indicate whether this chip supports BLE 2Mbps operation. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE 2Mbps operation is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_2MBPS. - */ -static inline -bool RAIL_BLE_Supports2Mbps(RAIL_Handle_t railHandle) -{ - return (RAIL_BLE_Supports2MbpsNonViterbi(railHandle) - || RAIL_BLE_Supports2MbpsViterbi(railHandle)); -} - /// Boolean to indicate whether the selected chip supports BLE /// Antenna Switching needed for Angle-of-Arrival receives or /// Angle-of-Departure transmits. @@ -590,16 +319,6 @@ bool RAIL_BLE_Supports2Mbps(RAIL_Handle_t railHandle) #define RAIL_BLE_SUPPORTS_ANTENNA_SWITCHING 0 #endif -/** - * Indicate whether this chip supports BLE Antenna Switching needed for - * Angle-of-Arrival receives or Angle-of-Departure transmits. - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE Antenna Switching is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_ANTENNA_SWITCHING. - */ -bool RAIL_BLE_SupportsAntennaSwitching(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports the BLE Coded PHY /// used for Long-Range. /// See also runtime refinement \ref RAIL_BLE_SupportsCodedPhy(). @@ -615,16 +334,6 @@ bool RAIL_BLE_SupportsAntennaSwitching(RAIL_Handle_t railHandle); /// Backwards-compatible synonym of \ref RAIL_BLE_SUPPORTS_CODED_PHY. #define RAIL_FEAT_BLE_CODED RAIL_BLE_SUPPORTS_CODED_PHY -/** - * Indicate whether this chip supports BLE Coded PHY used for Long-Range. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE Coded PHY is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_CODED_PHY. - */ -bool RAIL_BLE_SupportsCodedPhy(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports the BLE Simulscan PHY /// used for simultaneous BLE 1Mbps and Coded PHY reception. /// See also runtime refinement \ref RAIL_BLE_SupportsSimulscanPhy(). @@ -636,17 +345,6 @@ bool RAIL_BLE_SupportsCodedPhy(RAIL_Handle_t railHandle); #define RAIL_BLE_SUPPORTS_SIMULSCAN_PHY 0 #endif -/** - * Indicate whether this chip supports BLE Simulscan PHY used for simultaneous - * BLE 1Mbps and Coded PHY reception. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE Simulscan PHY is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_SIMULSCAN_PHY. - */ -bool RAIL_BLE_SupportsSimulscanPhy(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports BLE /// CTE (Constant Tone Extension) needed for Angle-of-Arrival/Departure /// transmits. @@ -659,17 +357,6 @@ bool RAIL_BLE_SupportsSimulscanPhy(RAIL_Handle_t railHandle); #define RAIL_BLE_SUPPORTS_CTE 0 #endif -/** - * Indicate whether this chip supports BLE CTE (Constant Tone Extension) - * needed for Angle-of-Arrival/Departure transmits. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE CTE is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_CTE. - */ -bool RAIL_BLE_SupportsCte(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports the /// Quuppa PHY. /// See also runtime refinement \ref RAIL_BLE_SupportsQuuppa(). @@ -679,16 +366,6 @@ bool RAIL_BLE_SupportsCte(RAIL_Handle_t railHandle); #define RAIL_BLE_SUPPORTS_QUUPPA 0 #endif -/** - * Indicate whether this chip supports the Quuppa PHY. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if the Quuppa is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_QUUPPA. - */ -bool RAIL_BLE_SupportsQuuppa(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports BLE /// IQ Sampling needed for Angle-of-Arrival/Departure receives. /// See also runtime refinement \ref RAIL_BLE_SupportsIQSampling(). @@ -700,17 +377,6 @@ bool RAIL_BLE_SupportsQuuppa(RAIL_Handle_t railHandle); #define RAIL_BLE_SUPPORTS_IQ_SAMPLING 0 #endif -/** - * Indicate whether this chip supports BLE IQ Sampling needed for - * Angle-of-Arrival/Departure receives. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE IQ Sampling is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_IQ_SAMPLING. - */ -bool RAIL_BLE_SupportsIQSampling(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports some BLE AOX /// features. #define RAIL_BLE_SUPPORTS_AOX \ @@ -733,18 +399,6 @@ bool RAIL_BLE_SupportsIQSampling(RAIL_Handle_t railHandle); /// Backwards-compatible synonym of \ref RAIL_BLE_SUPPORTS_PHY_SWITCH_TO_RX. #define RAIL_FEAT_BLE_PHY_SWITCH_TO_RX RAIL_BLE_SUPPORTS_PHY_SWITCH_TO_RX -/** - * Indicate whether this chip supports BLE PHY switch to RX - * functionality, which is used to switch BLE PHYs at a specific time - * to receive auxiliary packets. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE PHY switch to RX is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_PHY_SWITCH_TO_RX. - */ -bool RAIL_BLE_SupportsPhySwitchToRx(RAIL_Handle_t railHandle); - // IEEE 802.15.4 features // Some features may not be available on all platforms // due to radio hardware limitations. @@ -757,16 +411,6 @@ bool RAIL_BLE_SupportsPhySwitchToRx(RAIL_Handle_t railHandle); #define RAIL_SUPPORTS_PROTOCOL_IEEE802154 0 #endif -/** - * Indicate whether this chip supports the IEEE 802.15.4 protocol. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if the 802.15.4 protocol is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_PROTOCOL_IEEE802154. - */ -bool RAIL_SupportsProtocolIEEE802154(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports the /// 802.15.4 Wi-Fi Coexistence PHY. /// See also runtime refinement \ref RAIL_IEEE802154_SupportsCoexPhy(). @@ -778,31 +422,10 @@ bool RAIL_SupportsProtocolIEEE802154(RAIL_Handle_t railHandle); /// Backwards-compatible synonym of \ref RAIL_IEEE802154_SUPPORTS_COEX_PHY. #define RAIL_FEAT_802154_COEX_PHY RAIL_IEEE802154_SUPPORTS_COEX_PHY -/** - * Indicate whether this chip supports the IEEE 802.15.4 Wi-Fi Coexistence PHY. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if the 802.15.4 COEX PHY is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_IEEE802154_SUPPORTS_COEX_PHY. - */ -bool RAIL_IEEE802154_SupportsCoexPhy(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports a front end module. /// See also runtime refinement \ref RAIL_IEEE802154_SupportsFemPhy(). #define RAIL_IEEE802154_SUPPORTS_FEM_PHY (RAIL_SUPPORTS_PROTOCOL_IEEE802154 && RAIL_SUPPORTS_2P4GHZ_BAND) -/** - * Indicate whether this chip supports the IEEE 802.15.4 - * front end module optimized PHY. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if a front end module is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_IEEE802154_SUPPORTS_FEM_PHY. - */ -bool RAIL_IEEE802154_SupportsFemPhy(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports /// IEEE 802.15.4E-2012 feature subset needed for Zigbee R22 GB868. /// See also runtime refinement \ref @@ -817,23 +440,11 @@ bool RAIL_IEEE802154_SupportsFemPhy(RAIL_Handle_t railHandle); #define RAIL_FEAT_IEEE802154_E_GB868_SUPPORTED \ RAIL_IEEE802154_SUPPORTS_E_SUBSET_GB868 -/** - * Indicate whether this chip supports the IEEE 802.15.4E-2012 feature - * subset needed for Zigbee R22 GB868. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if 802.15.4E GB868 subset is supported; false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_IEEE802154_SUPPORTS_E_SUBSET_GB868. - */ -bool RAIL_IEEE802154_SupportsESubsetGB868(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports /// IEEE 802.15.4E-2012 Enhanced ACKing. /// See also runtime refinement \ref /// RAIL_IEEE802154_SupportsEEnhancedAck(). -#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1) +#if 1 #define RAIL_IEEE802154_SUPPORTS_E_ENHANCED_ACK RAIL_IEEE802154_SUPPORTS_E_SUBSET_GB868 #else #define RAIL_IEEE802154_SUPPORTS_E_ENHANCED_ACK 0 @@ -843,17 +454,6 @@ bool RAIL_IEEE802154_SupportsESubsetGB868(RAIL_Handle_t railHandle); #define RAIL_FEAT_IEEE802154_E_ENH_ACK_SUPPORTED \ RAIL_IEEE802154_SUPPORTS_E_ENHANCED_ACK -/** - * Indicate whether this chip supports IEEE 802.15.4E-2012 Enhanced ACKing. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if 802.15.4E Enhanced ACKing is supported; false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_IEEE802154_SUPPORTS_E_ENHANCED_ACK. - */ -bool RAIL_IEEE802154_SupportsEEnhancedAck(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports /// receiving IEEE 802.15.4E-2012 Multipurpose frames. /// See also runtime refinement \ref @@ -868,18 +468,6 @@ bool RAIL_IEEE802154_SupportsEEnhancedAck(RAIL_Handle_t railHandle); #define RAIL_FEAT_IEEE802154_MULTIPURPOSE_FRAME_SUPPORTED \ RAIL_IEEE802154_SUPPORTS_E_MULTIPURPOSE_FRAMES -/** - * Indicate whether this chip supports IEEE 802.15.4E-2012 Multipurpose frame - * reception. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if Multipurpose frame reception is supported; false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_IEEE802154_SUPPORTS_E_MULTIPURPOSE_FRAMES. - */ -bool RAIL_IEEE802154_SupportsEMultipurposeFrames(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports /// IEEE 802.15.4G-2012 feature subset needed for Zigbee R22 GB868. /// See also runtime refinement \ref @@ -895,18 +483,6 @@ bool RAIL_IEEE802154_SupportsEMultipurposeFrames(RAIL_Handle_t railHandle); #define RAIL_FEAT_IEEE802154_G_GB868_SUPPORTED \ RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 -/** - * Indicate whether this chip supports IEEE 802.15.4G-2012 feature - * subset needed for Zigbee R22 GB868. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if 802.15.4G GB868 subset is supported; false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868. - */ -bool RAIL_IEEE802154_SupportsGSubsetGB868(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports /// dynamic FEC #if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) @@ -916,17 +492,6 @@ bool RAIL_IEEE802154_SupportsGSubsetGB868(RAIL_Handle_t railHandle); #define RAIL_IEEE802154_SUPPORTS_G_DYNFEC 0 #endif -/** - * Indicate whether this chip supports IEEE 802.15.4G dynamic FEC - * - * @param[in] railHandle A RAIL instance handle. - * @return true if dynamic FEC is supported; false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_IEEE802154_SUPPORTS_G_DYNFEC. - */ -bool RAIL_IEEE802154_SupportsGDynFec(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports /// Wi-SUN mode switching /// See also runtime refinement \ref @@ -938,17 +503,6 @@ bool RAIL_IEEE802154_SupportsGDynFec(RAIL_Handle_t railHandle); #define RAIL_IEEE802154_SUPPORTS_G_MODESWITCH 0 #endif -/** - * Indicate whether this chip supports Wi-SUN mode switching - * - * @param[in] railHandle A RAIL instance handle. - * @return true if Wi-SUN mode switching is supported; false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_IEEE802154_SUPPORTS_G_MODESWITCH. - */ -bool RAIL_IEEE802154_SupportsGModeSwitch(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports /// IEEE 802.15.4G-2012 reception and transmission of frames /// with 4-byte CRC. @@ -962,18 +516,6 @@ bool RAIL_IEEE802154_SupportsGModeSwitch(RAIL_Handle_t railHandle); #define RAIL_FEAT_IEEE802154_G_4BYTE_CRC_SUPPORTED \ RAIL_IEEE802154_SUPPORTS_G_4BYTE_CRC -/** - * Indicate whether this chip supports IEEE 802.15.4G-2012 reception and - * transmission of frames with 4-byte CRC. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if 802.15.4G 4-byte CRC is supported; false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_IEEE802154_SUPPORTS_G_4BYTE_CRC. - */ -bool RAIL_IEEE802154_SupportsG4ByteCrc(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports /// IEEE 802.15.4G-2012 reception of unwhitened frames. /// See also runtime refinement \ref @@ -988,19 +530,6 @@ bool RAIL_IEEE802154_SupportsG4ByteCrc(RAIL_Handle_t railHandle); #define RAIL_FEAT_IEEE802154_G_UNWHITENED_RX_SUPPORTED \ RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_RX -/** - * Indicate whether this chip supports IEEE 802.15.4G-2012 reception - * of unwhitened frames. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if 802.15.4G unwhitened frame reception is supported; - * false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_RX. - */ -bool RAIL_IEEE802154_SupportsGUnwhitenedRx(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports /// IEEE 802.15.4G-2012 transmission of unwhitened frames. /// See also runtime refinement \ref @@ -1015,19 +544,6 @@ bool RAIL_IEEE802154_SupportsGUnwhitenedRx(RAIL_Handle_t railHandle); #define RAIL_FEAT_IEEE802154_G_UNWHITENED_TX_SUPPORTED \ RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_TX -/** - * Indicate whether this chip supports IEEE 802.15.4G-2012 transmission - * of unwhitened frames. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if 802.15.4G unwhitened frame transmit is supported; - * false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_TX. - */ -bool RAIL_IEEE802154_SupportsGUnwhitenedTx(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports /// canceling the frame-pending lookup event /// \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND @@ -1036,7 +552,7 @@ bool RAIL_IEEE802154_SupportsGUnwhitenedTx(RAIL_Handle_t railHandle); /// the stack to influence the outgoing ACK). /// See also runtime refinement \ref /// RAIL_IEEE802154_SupportsCancelFramePendingLookup(). -#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1) +#if 1 #define RAIL_IEEE802154_SUPPORTS_CANCEL_FRAME_PENDING_LOOKUP RAIL_SUPPORTS_PROTOCOL_IEEE802154 #else #define RAIL_IEEE802154_SUPPORTS_CANCEL_FRAME_PENDING_LOOKUP 0 @@ -1046,20 +562,6 @@ bool RAIL_IEEE802154_SupportsGUnwhitenedTx(RAIL_Handle_t railHandle); #define RAIL_FEAT_IEEE802154_CANCEL_FP_LOOKUP_SUPPORTED \ RAIL_IEEE802154_SUPPORTS_CANCEL_FRAME_PENDING_LOOKUP -/** - * Indicate whether this chip supports canceling the frame-pending lookup - * event \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND when the radio - * transitions to a state that renders the the reporting of this event moot - * (i.e., too late for the stack to influence the outgoing ACK). - * - * @param[in] railHandle A RAIL instance handle. - * @return true if canceling the lookup event is supported; false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_IEEE802154_SUPPORTS_CANCEL_FRAME_PENDING_LOOKUP. - */ -bool RAIL_IEEE802154_SupportsCancelFramePendingLookup(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports /// early triggering of the frame-pending lookup event /// \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND @@ -1076,19 +578,6 @@ bool RAIL_IEEE802154_SupportsCancelFramePendingLookup(RAIL_Handle_t railHandle); #define RAIL_FEAT_IEEE802154_EARLY_FP_LOOKUP_SUPPORTED \ RAIL_IEEE802154_SUPPORTS_EARLY_FRAME_PENDING_LOOKUP -/** - * Indicate whether this chip supports early triggering of the frame-pending - * lookup event \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND - * just after MAC address fields have been received. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if early triggering is supported; false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_IEEE802154_SUPPORTS_EARLY_FRAME_PENDING_LOOKUP. - */ -bool RAIL_IEEE802154_SupportsEarlyFramePendingLookup(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports dual PA configs for mode switch /// or concurrent mode. /// See also runtime refinement \ref RAIL_IEEE802154_SupportsDualPaConfig(). @@ -1098,16 +587,6 @@ bool RAIL_IEEE802154_SupportsEarlyFramePendingLookup(RAIL_Handle_t railHandle); #define RAIL_IEEE802154_SUPPORTS_DUAL_PA_CONFIG 0 #endif -/** - * Indicate whether RAIL supports dual PA mode on this chip. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if the dual PA mode is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_IEEE802154_SUPPORTS_DUAL_PA_CONFIG. - */ -bool RAIL_IEEE802154_SupportsDualPaConfig(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports IEEE 802.15.4 PHY /// with custom settings #if ((_SILICON_LABS_32B_SERIES_1_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_1_CONFIG == 3)) @@ -1116,16 +595,6 @@ bool RAIL_IEEE802154_SupportsDualPaConfig(RAIL_Handle_t railHandle); #define RAIL_IEEE802154_SUPPORTS_CUSTOM1_PHY 0 #endif -/** - * Indicate whether this chip supports the IEEE 802.15.4 PHY with custom settings. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if the 802.15.4 PHY with custom settings is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_IEEE802154_SUPPORTS_CUSTOM1_PHY. - */ -bool RAIL_IEEE802154_SupportsCustom1Phy(RAIL_Handle_t railHandle); - // Z-Wave features // Some features may not be available on all platforms // due to radio hardware limitations. @@ -1140,16 +609,6 @@ bool RAIL_IEEE802154_SupportsCustom1Phy(RAIL_Handle_t railHandle); /// Backwards-compatible synonym of \ref RAIL_SUPPORTS_PROTOCOL_ZWAVE. #define RAIL_FEAT_ZWAVE_SUPPORTED RAIL_SUPPORTS_PROTOCOL_ZWAVE -/** - * Indicate whether this chip supports the Z-Wave protocol. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if the Z-Wave protocol is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_PROTOCOL_ZWAVE. - */ -bool RAIL_SupportsProtocolZWave(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports energy detect PHY. /// See also runtime refinement \ref RAIL_ZWAVE_SupportsEnergyDetectPhy(). #if (_SILICON_LABS_32B_SERIES_1_CONFIG >= 3) @@ -1158,16 +617,6 @@ bool RAIL_SupportsProtocolZWave(RAIL_Handle_t railHandle); #define RAIL_ZWAVE_SUPPORTS_ED_PHY 0 #endif -/** - * Indicate whether this chip supports the Z-Wave energy detect PHY. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if the Z-Wave energy detect PHY is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_ZWAVE_SUPPORTS_ED_PHY. - */ -bool RAIL_ZWAVE_SupportsEnergyDetectPhy(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports concurrent PHY. /// See also runtime refinement \ref RAIL_ZWAVE_SupportsConcPhy(). #if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) @@ -1176,16 +625,6 @@ bool RAIL_ZWAVE_SupportsEnergyDetectPhy(RAIL_Handle_t railHandle); #define RAIL_ZWAVE_SUPPORTS_CONC_PHY 0 #endif -/** - * Indicate whether this chip supports the Z-Wave concurrent PHY. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if the Z-Wave concurrent PHY is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_ZWAVE_SUPPORTS_CONC_PHY. - */ -bool RAIL_ZWAVE_SupportsConcPhy(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports SQ-based PHY. /// See also runtime refinement \ref RAIL_SupportsSQPhy(). #if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ @@ -1196,16 +635,6 @@ bool RAIL_ZWAVE_SupportsConcPhy(RAIL_Handle_t railHandle); #define RAIL_SUPPORTS_SQ_PHY 0 #endif -/** - * Indicate whether this chip supports SQ-based PHY. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if the SQ-based PHY is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_SQ_PHY. - */ -bool RAIL_SupportsSQPhy(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the code supports Z-Wave /// region information in PTI and /// newer RAIL_ZWAVE_RegionConfig_t structure @@ -1218,15 +647,14 @@ bool RAIL_SupportsSQPhy(RAIL_Handle_t railHandle); /// Backwards-compatible synonym of \ref RAIL_ZWAVE_SUPPORTS_REGION_PTI. #define RAIL_FEAT_ZWAVE_REGION_PTI RAIL_ZWAVE_SUPPORTS_REGION_PTI -/** - * Indicate whether this chip supports Z-Wave Region in PTI. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if ZWAVE Region in PTI is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_ZWAVE_SUPPORTS_REGION_PTI. - */ -bool RAIL_ZWAVE_SupportsRegionPti(RAIL_Handle_t railHandle); +/// Boolean to indicate whether the selected chip supports raw RX data +/// sources other than \ref RAIL_RxDataSource_t::RX_PACKET_DATA. +/// See also runtime refinement \ref RAIL_SupportsRxRawData(). +#if 1 +#define RAIL_SUPPORTS_RX_RAW_DATA 1 +#else +#define RAIL_SUPPORTS_RX_RAW_DATA 0 +#endif /// Boolean to indicate whether the selected chip supports /// direct mode. @@ -1237,17 +665,6 @@ bool RAIL_ZWAVE_SupportsRegionPti(RAIL_Handle_t railHandle); #define RAIL_SUPPORTS_DIRECT_MODE 0 #endif -/** - * Indicate whether this chip supports direct mode. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if direct mode is supported; false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_SUPPORTS_DIRECT_MODE. - */ -bool RAIL_SupportsDirectMode(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports /// RX direct mode data to FIFO. /// See also runtime refinement \ref RAIL_SupportsRxDirectModeDataToFifo(). @@ -1257,17 +674,6 @@ bool RAIL_SupportsDirectMode(RAIL_Handle_t railHandle); #define RAIL_SUPPORTS_RX_DIRECT_MODE_DATA_TO_FIFO 0 #endif -/** - * Indicate whether this chip supports RX direct mode data to FIFO. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if direct mode data to FIFO is supported; false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_SUPPORTS_RX_DIRECT_MODE_DATA_TO_FIFO. - */ -bool RAIL_SupportsRxDirectModeDataToFifo(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports /// MFM protocol. /// See also runtime refinement \ref RAIL_SupportsMfm(). @@ -1277,16 +683,6 @@ bool RAIL_SupportsRxDirectModeDataToFifo(RAIL_Handle_t railHandle); #define RAIL_SUPPORTS_MFM 0 #endif -/** - * Indicate whether this chip supports MFM protocol. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if MFM protocol is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_MFM. - */ -bool RAIL_SupportsMfm(RAIL_Handle_t railHandle); - #if (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) /// Boolean to indicate whether the selected chip supports /// 802.15.4 signal detection @@ -1303,22 +699,6 @@ bool RAIL_SupportsMfm(RAIL_Handle_t railHandle); #define RAIL_BLE_SUPPORTS_SIGNAL_IDENTIFIER 0 #endif -/** - * Indicate whether this chip supports IEEE 802.15.4 signal identifier. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if signal identifier is supported; false otherwise. - */ -bool RAIL_IEEE802154_SupportsSignalIdentifier(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports BLE signal identifier. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if signal identifier is supported; false otherwise. - */ -bool RAIL_BLE_SupportsSignalIdentifier(RAIL_Handle_t railHandle); - /// Boolean to indicate whether the selected chip supports /// configurable RSSI threshold set by \ref RAIL_SetRssiDetectThreshold(). #if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ @@ -1328,17 +708,6 @@ bool RAIL_BLE_SupportsSignalIdentifier(RAIL_Handle_t railHandle); #define RAIL_SUPPORTS_RSSI_DETECT_THRESHOLD (0U) #endif -/** - * Indicate whether this chip supports configurable RSSI threshold - * set by \ref RAIL_SetRssiDetectThreshold(). - * - * @param[in] railHandle A RAIL instance handle. - * @return true if setting configurable RSSI is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_RSSI_DETECT_THRESHOLD. - */ -bool RAIL_SupportsRssiDetectThreshold(RAIL_Handle_t railHandle); - /** @} */ // end of group Features /** @} */ // end of group RAIL_API diff --git a/platform/radio/rail_lib/common/rail_types.h b/platform/radio/rail_lib/common/rail_types.h index 638417269f..170c00dab9 100644 --- a/platform/radio/rail_lib/common/rail_types.h +++ b/platform/radio/rail_lib/common/rail_types.h @@ -2966,6 +2966,12 @@ RAIL_ENUM_GENERIC(RAIL_RxOptions_t, uint32_t) { RAIL_RX_OPTION_ANTENNA1_SHIFT, /** Shift position of \ref RAIL_RX_OPTION_DISABLE_FRAME_DETECTION bit. */ RAIL_RX_OPTION_DISABLE_FRAME_DETECTION_SHIFT, + #ifndef DOXYGEN_SHOULD_SKIP_THIS + /** Shift position of \ref RAIL_RX_OPTION_SKIP_DC_CAL bit. */ + RAIL_RX_OPTION_SKIP_DC_CAL_SHIFT, + /** Shift position of \ref RAIL_RX_OPTION_SKIP_SYNTH_CAL bit. */ + RAIL_RX_OPTION_SKIP_SYNTH_CAL_SHIFT, + #endif //DOXYGEN_SHOULD_SKIP_THIS }; /** A value representing no options enabled. */ @@ -3064,6 +3070,26 @@ RAIL_ENUM_GENERIC(RAIL_RxOptions_t, uint32_t) { */ #define RAIL_RX_OPTION_DISABLE_FRAME_DETECTION (1UL << RAIL_RX_OPTION_DISABLE_FRAME_DETECTION_SHIFT) +#ifndef DOXYGEN_SHOULD_SKIP_THIS +/** + * An option to skip DC calibration when transitioning from RX to RX. This can be + * useful for reducing the state transition time, but risks impacting + * receive capability. Enabling this bypasses DC calibration (like + * \ref RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_DC_CAL) + * Defaults to false. + */ +#define RAIL_RX_OPTION_SKIP_DC_CAL (1UL << RAIL_RX_OPTION_SKIP_DC_CAL_SHIFT) + +/** + * An option to skip synth calibration when transitioning from RX to RX. This can + * be useful for reducing the state transition time, but risks impacting receive + * capability. Enabling this bypasses synth calibration (like + * \ref RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_SYNTH_CAL) + * Defaults to false. + */ +#define RAIL_RX_OPTION_SKIP_SYNTH_CAL (1U << RAIL_RX_OPTION_SKIP_SYNTH_CAL_SHIFT) +#endif //DOXYGEN_SHOULD_SKIP_THIS + /** A value representing all possible options. */ #define RAIL_RX_OPTIONS_ALL 0xFFFFFFFFUL diff --git a/platform/radio/rail_lib/plugin/coexistence/common/coexistence.c b/platform/radio/rail_lib/plugin/coexistence/common/coexistence.c index 4e6f1cf75a..e64f77309f 100644 --- a/platform/radio/rail_lib/plugin/coexistence/common/coexistence.c +++ b/platform/radio/rail_lib/plugin/coexistence/common/coexistence.c @@ -47,6 +47,11 @@ static COEX_GpioHandle_t gntHandle = NULL; /** PTA request GPIO configuration */ static COEX_GpioHandle_t reqHandle = NULL; +#if SL_RAIL_UTIL_COEX_OUTPUT_OVERRIDE_GPIO_INPUT +/** PTA external request GPIO configuration */ +static COEX_GpioHandle_t externalReqHandle = NULL; +#endif // SL_RAIL_UTIL_COEX_OUTPUT_OVERRIDE_GPIO_INPUT + /** PTA PWM request GPIO configuration */ static COEX_GpioHandle_t pwmReqHandle = NULL; @@ -118,13 +123,22 @@ static COEX_GpioConfig_t gntCfg = { static COEX_GpioConfig_t reqCfg = { #if SL_RAIL_UTIL_COEX_OVERRIDE_GPIO_INPUT - .index = COEX_GPIO_INDEX_REQ, + .index = COEX_GPIO_INDEX_INTERNAL_REQ, #endif //SL_RAIL_UTIL_COEX_OVERRIDE_GPIO_INPUT .options = (COEX_GpioOptions_t)(COEX_GPIO_OPTION_INT_DEASSERTED | COEX_GPIO_OPTION_OUTPUT), .cb = &COEX_REQ_ISR }; +#ifdef SL_RAIL_UTIL_COEX_OUTPUT_OVERRIDE_GPIO_INPUT +static COEX_GpioConfig_t externalReqCfg = { + .index = COEX_GPIO_INDEX_REQ, + .options = (COEX_GpioOptions_t)(COEX_GPIO_OPTION_INT_DEASSERTED + | COEX_GPIO_OPTION_OUTPUT), + .cb = &COEX_REQ_ISR +}; +#endif + static COEX_GpioConfig_t pwmReqCfg = { .options = (COEX_GpioOptions_t)(COEX_GPIO_OPTION_OUTPUT | COEX_GPIO_OPTION_SHARED) @@ -511,7 +525,10 @@ bool COEX_SetGpioInputOverride(COEX_GpioIndex_t gpioIndex, bool enable) } else { gpioInputOverride &= ~gpioMask; } - setGpioFlag(overrideGpioHandles[gpioIndex]); + if (gpioIndex != COEX_GPIO_INDEX_INTERNAL_REQ) { + setGpio(overrideGpioHandles[gpioIndex], enable); + setGpioFlag(overrideGpioHandles[gpioIndex]); + } } return true; } @@ -581,10 +598,19 @@ bool COEX_ConfigGrant(COEX_GpioHandle_t gpioHandle) return true; } +#if SL_RAIL_UTIL_COEX_OUTPUT_OVERRIDE_GPIO_INPUT +bool COEX_ConfigExternalRequest(COEX_GpioHandle_t gpioHandle) +{ + overrideGpioHandles[COEX_GPIO_INDEX_REQ] = gpioHandle; + configGpio(gpioHandle, &externalReqHandle, &externalReqCfg); + return true; +} +#endif //SL_RAIL_UTIL_COEX_OUTPUT_OVERRIDE_GPIO_INPUT + bool COEX_ConfigRequest(COEX_GpioHandle_t gpioHandle) { #if SL_RAIL_UTIL_COEX_OVERRIDE_GPIO_INPUT - overrideGpioHandles[COEX_GPIO_INDEX_REQ] = gpioHandle; + overrideGpioHandles[COEX_GPIO_INDEX_INTERNAL_REQ] = gpioHandle; #endif //SL_RAIL_UTIL_COEX_OVERRIDE_GPIO_INPUT if ((coexCfg.options & COEX_OPTION_REQ_SHARED) != 0U) { reqCfg.options |= COEX_GPIO_OPTION_SHARED; diff --git a/platform/radio/rail_lib/plugin/coexistence/common/coexistence.h b/platform/radio/rail_lib/plugin/coexistence/common/coexistence.h index 664d911970..aade582095 100644 --- a/platform/radio/rail_lib/plugin/coexistence/common/coexistence.h +++ b/platform/radio/rail_lib/plugin/coexistence/common/coexistence.h @@ -101,6 +101,7 @@ COEX_ENUM(COEX_GpioIndex_t) { COEX_GPIO_INDEX_GNT = 3, COEX_GPIO_INDEX_PHY_SELECT = 4, COEX_GPIO_INDEX_WIFI_TX = 5, + COEX_GPIO_INDEX_INTERNAL_REQ = 6, COEX_GPIO_INDEX_COUNT }; @@ -452,6 +453,22 @@ bool COEX_SetPwmRequest(COEX_Req_t coexReq, */ bool COEX_ConfigRequest(COEX_GpioHandle_t gpioHandle); +/** + * Configure the COEX external request GPIO. + * + * @param[in] gpioHandle A GPIO instance handle. + * @return This function returns true if the request GPIO + * was successfully configured, false otherwise. + * + * The external request GPIO is used with + * \ref COEX_GetGpioInputOverride to simulate + * a request from an external coexistence device. + * This GPIO output can be used to debug shared request. + * + * @note Pass NULL to disable the external request GPIO. + */ +bool COEX_ConfigExternalRequest(COEX_GpioHandle_t gpioHandle); + /** * Configure the COEX PWM request GPIO. * diff --git a/platform/radio/rail_lib/plugin/coexistence/config/efr32xg1/sl_rail_util_coex_config.h b/platform/radio/rail_lib/plugin/coexistence/config/efr32xg1/sl_rail_util_coex_config.h new file mode 100644 index 0000000000..9782cda2fd --- /dev/null +++ b/platform/radio/rail_lib/plugin/coexistence/config/efr32xg1/sl_rail_util_coex_config.h @@ -0,0 +1,157 @@ +/***************************************************************************//** + * @file + * @brief Coexistence configuration header file + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_COEX_CONFIG_H +#define SL_RAIL_UTIL_COEX_CONFIG_H + +#include "sl_rail_util_coex_common_config.h" + +// <<< sl:start pin_tool >>> + +#if SL_RAIL_UTIL_COEX_GNT_ENABLED +// Pin used for grant (GNT) signal +// SL_RAIL_UTIL_COEX_GNT +// $[GPIO_SL_RAIL_UTIL_COEX_GNT] +// #define SL_RAIL_UTIL_COEX_GNT_PORT gpioPortC +// #define SL_RAIL_UTIL_COEX_GNT_PIN 9 +// [GPIO_SL_RAIL_UTIL_COEX_GNT]$ +#ifndef SL_RAIL_UTIL_COEX_GNT_PORT +#error "SL_RAIL_UTIL_COEX_GNT undefined" +#endif //SL_RAIL_UTIL_COEX_GNT_PORT +#endif //SL_RAIL_UTIL_COEX_GNT_ENABLED + +#if SL_RAIL_UTIL_COEX_PRI_ENABLED +// Pin used for PRIORITY signal +// SL_RAIL_UTIL_COEX_PRI +// $[GPIO_SL_RAIL_UTIL_COEX_PRI] +// #define SL_RAIL_UTIL_COEX_PRI_PORT gpioPortD +// #define SL_RAIL_UTIL_COEX_PRI_PIN 13 +// [GPIO_SL_RAIL_UTIL_COEX_PRI]$ +#ifndef SL_RAIL_UTIL_COEX_PRI_PORT +#error "SL_RAIL_UTIL_COEX_PRI undefined" +#endif //SL_RAIL_UTIL_COEX_PRI_PORT +#endif //SL_RAIL_UTIL_COEX_PRI_ENABLED + +#if SL_RAIL_UTIL_COEX_REQ_ENABLED +// Pin used for Request signal +// SL_RAIL_UTIL_COEX_REQ +// $[GPIO_SL_RAIL_UTIL_COEX_REQ] +// #define SL_RAIL_UTIL_COEX_REQ_PORT gpioPortC +// #define SL_RAIL_UTIL_COEX_REQ_PIN 10 +// [GPIO_SL_RAIL_UTIL_COEX_REQ]$ +#ifndef SL_RAIL_UTIL_COEX_REQ_PORT +#error "SL_RAIL_UTIL_COEX_REQ undefined" +#endif //SL_RAIL_UTIL_COEX_REQ_PORT +#endif //SL_RAIL_UTIL_COEX_REQ_ENABLED + +#if SL_RAIL_UTIL_COEX_PWM_REQ_ENABLED && SL_RAIL_UTIL_COEX_REQ_SHARED +// Pin used for PWM Request signal +// SL_RAIL_UTIL_COEX_PWM_REQ +// $[GPIO_SL_RAIL_UTIL_COEX_PWM_REQ] +// #define SL_RAIL_UTIL_COEX_PWM_REQ_PORT gpioPortC +// #define SL_RAIL_UTIL_COEX_PWM_REQ_PIN 11 +// [GPIO_SL_RAIL_UTIL_COEX_PWM_REQ]$ +#ifndef SL_RAIL_UTIL_COEX_PWM_REQ_PORT +#error "SL_RAIL_UTIL_COEX_PWM_REQ undefined" +#endif //SL_RAIL_UTIL_COEX_PWM_REQ_PORT +#endif //SL_RAIL_UTIL_COEX_PWM_REQ_ENABLED && SL_RAIL_UTIL_COEX_REQ_SHARED + +#if SL_RAIL_UTIL_COEX_RHO_ENABLED +// Pin used for Radio Holdoff signal +// SL_RAIL_UTIL_COEX_RHO +// $[GPIO_SL_RAIL_UTIL_COEX_RHO] +// #define SL_RAIL_UTIL_COEX_RHO_PORT gpioPortC +// #define SL_RAIL_UTIL_COEX_RHO_PIN 8 +// [GPIO_SL_RAIL_UTIL_COEX_RHO]$ +#ifndef SL_RAIL_UTIL_COEX_RHO_PORT +#error "SL_RAIL_UTIL_COEX_RHO undefined" +#endif //SL_RAIL_UTIL_COEX_RHO_PORT +#endif //SL_RAIL_UTIL_COEX_RHO_ENABLED + +#if SL_RAIL_UTIL_COEX_DP_ENABLED +// Pin used for Directional Priority output signal +// SL_RAIL_UTIL_COEX_DP_OUT +// $[PRS_SL_RAIL_UTIL_COEX_DP_OUT] +// #define SL_RAIL_UTIL_COEX_DP_OUT_CHANNEL 3 + +// PRS CH3 on PD12 +// #define SL_RAIL_UTIL_COEX_DP_OUT_PORT gpioPortD +// #define SL_RAIL_UTIL_COEX_DP_OUT_PIN 12 +// #define SL_RAIL_UTIL_COEX_DP_OUT_LOC 11 +// [PRS_SL_RAIL_UTIL_COEX_DP_OUT]$ + +// Inverted REQUEST PRS channel +// SL_RAIL_UTIL_COEX_DP_REQUEST_INV +// $[PRS_SL_RAIL_UTIL_COEX_DP_REQUEST_INV] +// #define SL_RAIL_UTIL_COEX_DP_REQUEST_INV_CHANNEL 4 + +// [PRS_SL_RAIL_UTIL_COEX_DP_REQUEST_INV]$ + +// Directional PRIORITY Timer module +// SL_RAIL_UTIL_COEX_DP_TIMER +// $[TIMER_SL_RAIL_UTIL_COEX_DP_TIMER] +// #define SL_RAIL_UTIL_COEX_DP_TIMER_PERIPHERAL TIMER1 +// #define SL_RAIL_UTIL_COEX_DP_TIMER_PERIPHERAL_NO 1 +#ifndef SL_RAIL_UTIL_COEX_DP_TIMER_PERIPHERAL +#error "SL_RAIL_UTIL_COEX_DP_TIMER_PERIPHERAL undefined" +#endif //SL_RAIL_UTIL_COEX_DP_TIMER_PERIPHERAL + +// #define SL_RAIL_UTIL_COEX_DP_TIMER_CC0_CHANNEL 1 +// TIMER1 CC1 on PC11 +// #define SL_RAIL_UTIL_COEX_DP_TIMER_CC0_PORT gpioPortC +// #define SL_RAIL_UTIL_COEX_DP_TIMER_CC0_PIN 10 +// #define SL_RAIL_UTIL_COEX_DP_TIMER_CC0_LOC 15 +// [TIMER_SL_RAIL_UTIL_COEX_DP_TIMER]$ +#ifndef SL_RAIL_UTIL_COEX_DP_TIMER_PERIPHERAL +#error "SL_RAIL_UTIL_COEX_DP_TIMER_PERIPHERAL undefined" +#endif //SL_RAIL_UTIL_COEX_DP_TIMER_PERIPHERAL +#endif //SL_RAIL_UTIL_COEX_DP_ENABLED + +#if SL_RAIL_UTIL_COEX_RX_ACTIVE_ENABLED +// Pin used for RX active signal +// SL_RAIL_UTIL_COEX_RX_ACTIVE +// $[PRS_SL_RAIL_UTIL_COEX_RX_ACTIVE] +// #define SL_RAIL_UTIL_COEX_RX_ACTIVE_CHANNEL 8 + +// PRS CH8 on PD13 +// #define SL_RAIL_UTIL_COEX_RX_ACTIVE_PORT gpioPortD +// #define SL_RAIL_UTIL_COEX_RX_ACTIVE_PIN 13 +// [PRS_SL_RAIL_UTIL_COEX_RX_ACTIVE]$ +#ifndef SL_RAIL_UTIL_COEX_RX_ACTIVE_PORT +#error "SL_RAIL_UTIL_COEX_RX_ACTIVE_PORT undefined" +#endif //SL_RAIL_UTIL_COEX_RX_ACTIVE_PORT +#ifndef SL_RAIL_UTIL_COEX_RX_ACTIVE_CHANNEL +#error "SL_RAIL_UTIL_COEX_RX_ACTIVE_CHANNEL undefined" +#endif //SL_RAIL_UTIL_COEX_RX_ACTIVE_CHANNEL +#endif //SL_RAIL_UTIL_COEX_RX_ACTIVE_ENABLED + +// <<< sl:end pin_tool >>> + +#endif // SL_RAIL_UTIL_COEX_CONFIG_H diff --git a/platform/radio/rail_lib/plugin/coexistence/config/efr32xg1x/sl_rail_util_coex_config.h b/platform/radio/rail_lib/plugin/coexistence/config/efr32xg1x/sl_rail_util_coex_config.h index f633db7df4..ab487e48f7 100644 --- a/platform/radio/rail_lib/plugin/coexistence/config/efr32xg1x/sl_rail_util_coex_config.h +++ b/platform/radio/rail_lib/plugin/coexistence/config/efr32xg1x/sl_rail_util_coex_config.h @@ -81,9 +81,9 @@ // #define SL_RAIL_UTIL_COEX_PRI_PORT gpioPortD // #define SL_RAIL_UTIL_COEX_PRI_PIN 13 // [GPIO_SL_RAIL_UTIL_COEX_PRI]$ -#ifndef SL_RAIL_UTIL_COEX_PRI_PORT +#if !defined(SL_RAIL_UTIL_COEX_PRI_PORT) && !SL_RAIL_UTIL_COEX_DP_ENABLED #error "SL_RAIL_UTIL_COEX_PRI undefined" -#endif //SL_RAIL_UTIL_COEX_PRI_PORT +#endif //!defined(SL_RAIL_UTIL_COEX_PRI_PORT) && !SL_RAIL_UTIL_COEX_DP_ENABLED #endif //SL_RAIL_UTIL_COEX_PRI_ENABLED #if SL_RAIL_UTIL_COEX_REQ_ENABLED diff --git a/platform/radio/rail_lib/plugin/coexistence/config/efr32xg2x/sl_rail_util_coex_config.h b/platform/radio/rail_lib/plugin/coexistence/config/efr32xg2x/sl_rail_util_coex_config.h index 59379ade37..751342a77d 100644 --- a/platform/radio/rail_lib/plugin/coexistence/config/efr32xg2x/sl_rail_util_coex_config.h +++ b/platform/radio/rail_lib/plugin/coexistence/config/efr32xg2x/sl_rail_util_coex_config.h @@ -85,9 +85,9 @@ // #define SL_RAIL_UTIL_COEX_PRI_PORT gpioPortD // #define SL_RAIL_UTIL_COEX_PRI_PIN 13 // [GPIO_SL_RAIL_UTIL_COEX_PRI]$ -#ifndef SL_RAIL_UTIL_COEX_PRI_PORT +#if !defined(SL_RAIL_UTIL_COEX_PRI_PORT) && !SL_RAIL_UTIL_COEX_DP_ENABLED #error "SL_RAIL_UTIL_COEX_PRI undefined" -#endif //SL_RAIL_UTIL_COEX_PRI_PORT +#endif //!defined(SL_RAIL_UTIL_COEX_PRI_PORT) && !SL_RAIL_UTIL_COEX_DP_ENABLED #endif //SL_RAIL_UTIL_COEX_PRI_ENABLED #if SL_RAIL_UTIL_COEX_REQ_ENABLED @@ -135,7 +135,7 @@ // PRS CH3 on PD12 // #define SL_RAIL_UTIL_COEX_DP_OUT_PORT gpioPortD // #define SL_RAIL_UTIL_COEX_DP_OUT_PIN 12 -// [PRS_SL_RAIL_UTIL_COEX_DP]$ +// [PRS_SL_RAIL_UTIL_COEX_DP_OUT]$ // Directional Priority timer module // SL_RAIL_UTIL_COEX_DP_TIMER diff --git a/platform/radio/rail_lib/plugin/coexistence/hal/efr32/coexistence-hal.c b/platform/radio/rail_lib/plugin/coexistence/hal/efr32/coexistence-hal.c index de22dacd3f..2fa3c8c3ca 100644 --- a/platform/radio/rail_lib/plugin/coexistence/hal/efr32/coexistence-hal.c +++ b/platform/radio/rail_lib/plugin/coexistence/hal/efr32/coexistence-hal.c @@ -84,6 +84,17 @@ COEX_HAL_GpioConfig_t sli_coex_ptaReqCfg = { }; #endif //SL_RAIL_UTIL_COEX_REQ_PORT +#ifdef SL_RAIL_UTIL_COEX_EXTERNAL_REQ_PORT +COEX_HAL_GpioConfig_t sli_coex_ptaExternalReqCfg = { + .signal = INVALID_SIGNAL, + .source = INVALID_SOURCE, + .intNo = INVALID_INTERRUPT, + .port = SL_RAIL_UTIL_COEX_EXTERNAL_REQ_PORT, + .pin = SL_RAIL_UTIL_COEX_EXTERNAL_REQ_PIN, + .polarity = SL_RAIL_UTIL_COEX_REQ_ASSERT_LEVEL +}; +#endif //SL_RAIL_UTIL_COEX_EXTERNAL_REQ_PORT + #ifdef SL_RAIL_UTIL_COEX_PWM_REQ_PORT COEX_HAL_GpioConfig_t sli_coex_ptaPwmReqCfg = { .signal = INVALID_SIGNAL, @@ -222,6 +233,11 @@ static void setGpio(COEX_GpioHandle_t gpioHandle, bool enabled) if (gpioHandle != NULL) { COEX_HAL_GpioConfig_t *gpio = (COEX_HAL_GpioConfig_t*)gpioHandle; +#if SL_RAIL_UTIL_COEX_OUTPUT_OVERRIDE_GPIO_INPUT + if (gpio->config.index == COEX_GPIO_INDEX_INTERNAL_REQ) { + COEX_SetGpioInputOverride(COEX_GPIO_INDEX_INTERNAL_REQ, enabled); + } +#endif if (enabled == gpio->polarity) { GPIO_PinOutSet((GPIO_Port_TypeDef)gpio->port, gpio->pin); } else { @@ -251,7 +267,11 @@ static void configGpio(COEX_GpioHandle_t gpioHandle, COEX_GpioConfig_t *coexGpio COEX_HAL_GpioConfig_t *gpio = (COEX_HAL_GpioConfig_t*)gpioHandle; bool defaultAsserted = (coexGpio->options & COEX_GPIO_OPTION_DEFAULT_ASSERTED) != 0U; gpio->config = *coexGpio; - +#if SL_RAIL_UTIL_COEX_OUTPUT_OVERRIDE_GPIO_INPUT + if ((coexGpio->options & COEX_GPIO_OPTION_OUTPUT) == 0U) { + coexGpio->options |= COEX_GPIO_OPTION_SHARED; + } +#endif //SL_RAIL_UTIL_COEX_OUTPUT_OVERRIDE_GPIO_INPUT if ((coexGpio->options & COEX_GPIO_OPTION_SHARED) != 0U) { gpio->mode = gpio->polarity ? GPIO_CONFIG_OR : GPIO_CONFIG_AND; } else if ((coexGpio->options & COEX_GPIO_OPTION_OUTPUT) != 0U) { @@ -283,6 +303,11 @@ static bool isGpioOutSet(COEX_GpioHandle_t gpioHandle, bool defaultValue) { if (gpioHandle != NULL) { COEX_HAL_GpioConfig_t *gpio = (COEX_HAL_GpioConfig_t*)gpioHandle; +#if SL_RAIL_UTIL_COEX_OUTPUT_OVERRIDE_GPIO_INPUT + if (gpio->config.index == COEX_GPIO_INDEX_INTERNAL_REQ) { + return COEX_GetGpioInputOverride(COEX_GPIO_INDEX_INTERNAL_REQ); + } +#endif return !!GPIO_PinOutGet((GPIO_Port_TypeDef)gpio->port, gpio->pin) == !!gpio->polarity; } else { @@ -378,6 +403,18 @@ bool COEX_HAL_ConfigRequest(COEX_HAL_GpioConfig_t *gpioConfig) return status; } +bool COEX_HAL_ConfigExternalRequest(COEX_HAL_GpioConfig_t *gpioConfig) +{ + bool status = false; + + gpioConfig->isr = &COEX_HAL_REQ_ISR; + status = COEX_ConfigExternalRequest(gpioConfig); + if (status) { + reqCallback = gpioConfig->config.cb; + } + return status; +} + bool COEX_HAL_ConfigRadioHoldOff(COEX_HAL_GpioConfig_t *gpioConfig) { bool status = false; @@ -549,6 +586,13 @@ void COEX_HAL_Init(void) #ifdef SL_RAIL_UTIL_COEX_REQ_PORT COEX_HAL_ConfigRequest(&sli_coex_ptaReqCfg); #endif //SL_RAIL_UTIL_COEX_REQ_PORT + #if SL_RAIL_UTIL_COEX_OUTPUT_OVERRIDE_GPIO_INPUT + #if SL_RAIL_UTIL_COEX_EXTERNAL_REQ_PORT + COEX_HAL_ConfigExternalRequest(&sli_coex_ptaExternalReqCfg); + #else + COEX_HAL_ConfigExternalRequest(&sli_coex_ptaReqCfg); + #endif //SL_RAIL_UTIL_COEX_EXTERNAL_REQ_PORT + #endif //SL_RAIL_UTIL_COEX_OUTPUT_OVERRIDE_GPIO_INPUT #ifdef SL_RAIL_UTIL_COEX_PRI_PORT COEX_HAL_ConfigPriority(&sli_coex_ptaPriCfg); #endif //SL_RAIL_UTIL_COEX_PRI_PORT diff --git a/platform/radio/rail_lib/plugin/coexistence/hal/efr32/coexistence-hal.h b/platform/radio/rail_lib/plugin/coexistence/hal/efr32/coexistence-hal.h index 7383dcb0f4..f147189ee3 100644 --- a/platform/radio/rail_lib/plugin/coexistence/hal/efr32/coexistence-hal.h +++ b/platform/radio/rail_lib/plugin/coexistence/hal/efr32/coexistence-hal.h @@ -71,6 +71,7 @@ typedef struct COEX_HAL_GpioConfig { void COEX_HAL_Init(void); bool COEX_HAL_ConfigRequest(COEX_HAL_GpioConfig_t *gpioConfig); +bool COEX_HAL_ConfigExternalRequest(COEX_HAL_GpioConfig_t *gpioConfig); bool COEX_HAL_ConfigPwmRequest(COEX_HAL_GpioConfig_t *gpioConfig); bool COEX_HAL_ConfigRadioHoldOff(COEX_HAL_GpioConfig_t *gpioConfig); bool COEX_HAL_ConfigPriority(COEX_HAL_GpioConfig_t *gpioConfig); diff --git a/platform/radio/rail_lib/plugin/coexistence/protocol/ble/coexistence-ble.c b/platform/radio/rail_lib/plugin/coexistence/protocol/ble/coexistence-ble.c index c73a3f25d9..848e86fb52 100644 --- a/platform/radio/rail_lib/plugin/coexistence/protocol/ble/coexistence-ble.c +++ b/platform/radio/rail_lib/plugin/coexistence/protocol/ble/coexistence-ble.c @@ -65,7 +65,7 @@ static inline bool isCoexEnabled(void) } /* Update constant pwm state */ -static void sl_bt_updatepwm() +static void sl_bt_updatepwm(void) { COEX_Req_t req; if (ll_coex.pwmEnable) { diff --git a/platform/radio/rail_lib/plugin/coexistence/protocol/ble/coexistence-ble.h b/platform/radio/rail_lib/plugin/coexistence/protocol/ble/coexistence-ble.h index 9092633391..49646e1e6c 100644 --- a/platform/radio/rail_lib/plugin/coexistence/protocol/ble/coexistence-ble.h +++ b/platform/radio/rail_lib/plugin/coexistence/protocol/ble/coexistence-ble.h @@ -91,8 +91,8 @@ typedef struct { #define SL_BT_COEX_OPTION_REQUEST_WINDOW_MASK 0xffff0000 void sl_bt_init_coex(const sl_bt_coex_init_t *coexInit); -void sl_bt_class_coex_init(); -static inline void sl_bt_init_coex_hal() +void sl_bt_class_coex_init(void); +static inline void sl_bt_init_coex_hal(void) { //#if (HAL_COEX_ENABLE) // Initialise coexistence interface @@ -135,7 +135,7 @@ typedef struct { uint8_t coex_pwm_period; /** PWM Period in ms, if 0 Pwm is disabled*/ uint8_t coex_pwm_dutycycle; /** PWM dutycycle percentage, if 0 pwm is disabled, if >= 100 scanPwm line is always enabled*/ } sl_bt_ll_coex_config_t; -#define SL_BT_COEX_DEFAULT_CONFIG { 175, 255, SL_RAIL_UTIL_COEX_PWM_REQ_PERIOD, SL_RAIL_UTIL_COEX_PWM_REQ_DUTYCYCLE } +#define SL_BT_COEX_DEFAULT_CONFIG { 175, 255, (SL_RAIL_UTIL_COEX_PWM_REQ_PERIOD + 1) / 2, SL_RAIL_UTIL_COEX_PWM_REQ_DUTYCYCLE } /** * Update coex configuration diff --git a/platform/radio/rail_lib/plugin/coexistence/protocol/ieee802154/coexistence-802154.c b/platform/radio/rail_lib/plugin/coexistence/protocol/ieee802154/coexistence-802154.c index 93ff273cda..b36ba6dd48 100644 --- a/platform/radio/rail_lib/plugin/coexistence/protocol/ieee802154/coexistence-802154.c +++ b/platform/radio/rail_lib/plugin/coexistence/protocol/ieee802154/coexistence-802154.c @@ -257,6 +257,9 @@ extern bool halFemPhyChanged(void); || RUNTIME_PHY_SELECT) \ #if SL_RAIL_UTIL_COEX_PHY_ENABLED + #ifdef _SILICON_LABS_32B_SERIES_1_CONFIG_1 + #error "COEX PHY is not supported on the selected platform." + #endif static uint8_t phySelectTimeoutMs = PTA_PHY_SELECT_TIMEOUT_MAX; #else //!SL_RAIL_UTIL_COEX_PHY_ENABLED static uint8_t phySelectTimeoutMs = 0U; diff --git a/platform/radio/rail_lib/plugin/coexistence/protocol/ieee802154_uc/coexistence-802154-cli.c b/platform/radio/rail_lib/plugin/coexistence/protocol/ieee802154_uc/coexistence-802154-cli.c index 691266ae63..79863a726b 100644 --- a/platform/radio/rail_lib/plugin/coexistence/protocol/ieee802154_uc/coexistence-802154-cli.c +++ b/platform/radio/rail_lib/plugin/coexistence/protocol/ieee802154_uc/coexistence-802154-cli.c @@ -32,10 +32,106 @@ #include "response_print.h" #include "coexistence-802154.h" +#if RAILTEST +#define EMBER_COUNTER_STRINGS \ + "PTA Lo Pri Req", \ + "PTA Hi Pri Req", \ + "PTA Lo Pri Denied", \ + "PTA Hi Pri Denied", \ + "PTA Lo Pri Tx Abrt", \ + "PTA Hi Pri Tx Abrt", \ + NULL + +const char * titleStrings[] = { + EMBER_COUNTER_STRINGS +}; + +uint16_t emberCounters[SL_RAIL_UTIL_COEX_EVENT_COUNT]; + +void emberClearCounters(void) +{ + memset(&emberCounters, 0, sizeof(emberCounters)); +} + +void sl_rail_util_coex_counter_on_event(sl_rail_util_coex_event_t event) +{ + emberCounters[event] += 1; +} +#else +extern const char * titleStrings[]; +extern uint16_t emberCounters[]; +extern void emberClearCounters(void); +#endif + +static void printCounter(uint8_t id) +{ + responsePrintContinue("%s: %u", titleStrings[id], emberCounters[id]); +} + +static void printLastCounter(uint8_t id) +{ + responsePrintEnd("%s: %u", titleStrings[id], emberCounters[id]); +} + +void cli_coex_154_print_counters(sl_cli_command_arg_t *args) +{ + responsePrintStart(sl_cli_get_command_string(args, 0)); + printCounter(SL_RAIL_UTIL_COEX_EVENT_LO_PRI_REQUESTED); + printCounter(SL_RAIL_UTIL_COEX_EVENT_HI_PRI_REQUESTED); + printCounter(SL_RAIL_UTIL_COEX_EVENT_LO_PRI_DENIED); + printCounter(SL_RAIL_UTIL_COEX_EVENT_HI_PRI_DENIED); + printCounter(SL_RAIL_UTIL_COEX_EVENT_LO_PRI_TX_ABORTED); + printLastCounter(SL_RAIL_UTIL_COEX_EVENT_HI_PRI_TX_ABORTED); +} + +void cli_coex_154_clear_counters(sl_cli_command_arg_t *args) +{ + (void)args; + emberClearCounters(); + responsePrint(sl_cli_get_command_string(args, 0), "Status:0x%x", 0); +} + void cli_coex_154_get_options(sl_cli_command_arg_t *args) { sl_rail_util_coex_options_t options = sl_rail_util_coex_get_options(); - responsePrint(sl_cli_get_command_string(args, 0), "Options:0x%x", options); + responsePrintStart(sl_cli_get_command_string(args, 0)); + responsePrintContinue("Options:0x%x," + "rxRetryTimoutMs:%u," + "ackHoldoff:%s," + "abortTx:%s," + "txHipri:%s," + "rxHipri:%s," + "rxRetryHipri:%s," + "rxRetryReq:%s," + "radioHoldOff:%s," + "toggleReqOnMacRetransmit:%s," + "forceHoldoff:%s," + "MACHoldoff:%s," + "reqFilterPass:%s," + "hipriFilterPass:%s," + "ccaThreshold:%u", + options, + (uint8_t)(options & SL_RAIL_UTIL_COEX_OPT_RX_RETRY_TIMEOUT_MS), + ((options & SL_RAIL_UTIL_COEX_OPT_ACK_HOLDOFF) ? "True" : "False"), + ((options & SL_RAIL_UTIL_COEX_OPT_ABORT_TX) ? "True" : "False"), + ((options & SL_RAIL_UTIL_COEX_OPT_TX_HIPRI) ? "True" : "False"), + ((options & SL_RAIL_UTIL_COEX_OPT_RX_HIPRI) ? "True" : "False"), + ((options & SL_RAIL_UTIL_COEX_OPT_RX_RETRY_HIPRI) ? "True" : "False"), + ((options & SL_RAIL_UTIL_COEX_OPT_RX_RETRY_REQ) ? "True" : "False"), + ((options & SL_RAIL_UTIL_COEX_OPT_RHO_ENABLED) ? "True" : "False"), + ((options & SL_RAIL_UTIL_COEX_OPT_TOGGLE_REQ_ON_MACRETRANSMIT) ? "True" : "False"), + ((options & SL_RAIL_UTIL_COEX_OPT_FORCE_HOLDOFF) ? "True" : "False"), + ((options & SL_RAIL_UTIL_COEX_OPT_MAC_HOLDOFF) ? "True" : "False"), + ((options & SL_RAIL_UTIL_COEX_OPT_REQ_FILTER_PASS) ? "True" : "False"), + ((options & SL_RAIL_UTIL_COEX_OPT_HIPRI_FILTER_PASS) ? "True" : "False"), + (uint8_t)(options & SL_RAIL_UTIL_COEX_OPT_CCA_THRESHOLD)); + + responsePrintEnd("MACRetryThreshold:%u," + "MACFailThreshold:%u," + "longReq:%s", + (uint8_t)(options & SL_RAIL_UTIL_COEX_OPT_MAC_RETRY_THRESHOLD), + (uint8_t)(options & SL_RAIL_UTIL_COEX_OPT_MAC_FAIL_THRESHOLD), + ((options & SL_RAIL_UTIL_COEX_OPT_LONG_REQ) ? "True" : "False")); } void cli_coex_154_set_options(sl_cli_command_arg_t *args) diff --git a/platform/radio/rail_lib/plugin/coexistence/protocol/ieee802154_uc/coexistence-802154.c b/platform/radio/rail_lib/plugin/coexistence/protocol/ieee802154_uc/coexistence-802154.c index 08efe9d82a..775bc42087 100644 --- a/platform/radio/rail_lib/plugin/coexistence/protocol/ieee802154_uc/coexistence-802154.c +++ b/platform/radio/rail_lib/plugin/coexistence/protocol/ieee802154_uc/coexistence-802154.c @@ -236,6 +236,9 @@ extern void emRadioHoldOffIsr(bool active); || COEX_RHO_SUPPORT) \ #if SL_RAIL_UTIL_COEX_PHY_ENABLED + #ifdef _SILICON_LABS_32B_SERIES_1_CONFIG_1 + #error "COEX PHY is not supported on the selected platform." + #endif static uint8_t phySelectTimeoutMs = SL_RAIL_UTIL_COEX_PHY_SELECT_TIMEOUT_MAX; #else //!SL_RAIL_UTIL_COEX_PHY_ENABLED static uint8_t phySelectTimeoutMs = 0U; diff --git a/platform/radio/rail_lib/plugin/coexistence/protocol/ieee802154_uc/sl_zigbee_coexistence_cli.c b/platform/radio/rail_lib/plugin/coexistence/protocol/ieee802154_uc/sl_zigbee_coexistence_cli.c index 428a89594a..1906e72070 100644 --- a/platform/radio/rail_lib/plugin/coexistence/protocol/ieee802154_uc/sl_zigbee_coexistence_cli.c +++ b/platform/radio/rail_lib/plugin/coexistence/protocol/ieee802154_uc/sl_zigbee_coexistence_cli.c @@ -287,7 +287,8 @@ static const char * const gpioNames[] = { "PTA_GPIO_INDEX_REQ", "PTA_GPIO_INDEX_GNT", "PTA_GPIO_INDEX_PHY_SELECT", - "PTA_GPIO_INDEX_WIFI_TX" + "PTA_GPIO_INDEX_WIFI_TX", + "PTA_GPIO_INDEX_INTERNAL_REQ" }; #endif //SL_RAIL_UTIL_COEX_OVERRIDE_GPIO_INPUT diff --git a/platform/radio/rail_lib/plugin/component/rail_util_coex.slcc b/platform/radio/rail_lib/plugin/component/rail_util_coex.slcc index c24adfecd0..1aebe71247 100644 --- a/platform/radio/rail_lib/plugin/component/rail_util_coex.slcc +++ b/platform/radio/rail_lib/plugin/component/rail_util_coex.slcc @@ -38,9 +38,16 @@ documentation: docset: rail document: rail-util-coex config_file: + - path: platform/radio/rail_lib/plugin/coexistence/config/efr32xg1/sl_rail_util_coex_config.h + condition: + - device_series_1 + - device_sdid_80 + file_id: rail_util_coex_config - path: platform/radio/rail_lib/plugin/coexistence/config/efr32xg1x/sl_rail_util_coex_config.h condition: - device_series_1 + unless: + - device_sdid_80 file_id: rail_util_coex_config - path: platform/radio/rail_lib/plugin/coexistence/config/efr32xg2x/sl_rail_util_coex_config.h condition: diff --git a/platform/radio/rail_lib/plugin/component/rail_util_coex_ieee802154_cli.slcc b/platform/radio/rail_lib/plugin/component/rail_util_coex_ieee802154_cli.slcc index 16a8ef8d35..38791d84fb 100644 --- a/platform/radio/rail_lib/plugin/component/rail_util_coex_ieee802154_cli.slcc +++ b/platform/radio/rail_lib/plugin/component/rail_util_coex_ieee802154_cli.slcc @@ -121,3 +121,13 @@ template_contribution: help: "GPIO index" - type: uint8 help: "0=Disable 1=Enable" + - name: cli_command + value: + name: coex_154_print_counters + handler: cli_coex_154_print_counters + help: " Print coexistence specific counters" + - name: cli_command + value: + name: coex_154_clear_counters + handler: cli_coex_154_clear_counters + help: " Reset coexistence specific counters" diff --git a/platform/radio/rail_lib/plugin/fem_util/sl_fem_util.c b/platform/radio/rail_lib/plugin/fem_util/sl_fem_util.c index 1a242b8e39..2969468dd0 100644 --- a/platform/radio/rail_lib/plugin/fem_util/sl_fem_util.c +++ b/platform/radio/rail_lib/plugin/fem_util/sl_fem_util.c @@ -72,7 +72,7 @@ #define SL_FEM_UTIL_TX_LOC SL_FEM_UTIL_RX_LOC #endif #elif !defined(SL_FEM_UTIL_TX_CHANNEL) - #error "BSP_FEM_TX_CHANNEL must be defined." + #error "SL_FEM_UTIL_TX_CHANNEL must be defined." #endif #endif // SL_FEM_UTIL_TX_ENABLE == 1 diff --git a/platform/radio/rail_lib/plugin/rail_util_built_in_phys/efr32xg24/sl_rail_ble_config_38M4Hz.c b/platform/radio/rail_lib/plugin/rail_util_built_in_phys/efr32xg24/sl_rail_ble_config_38M4Hz.c index 81a93b822e..0df81372af 100644 --- a/platform/radio/rail_lib/plugin/rail_util_built_in_phys/efr32xg24/sl_rail_ble_config_38M4Hz.c +++ b/platform/radio/rail_lib/plugin/rail_util_built_in_phys/efr32xg24/sl_rail_ble_config_38M4Hz.c @@ -165,7 +165,7 @@ static const uint32_t phyInfo_2[] = { (uint32_t) NULL, 0UL, 0UL, - 999997UL, + 999978UL, (uint32_t) NULL, (uint32_t) NULL, }; @@ -187,7 +187,7 @@ static const uint32_t phyInfo_3[] = { (uint32_t) NULL, 0UL, 0UL, - 999997UL, + 999978UL, (uint32_t) NULL, (uint32_t) NULL, }; @@ -342,7 +342,7 @@ const uint32_t sl_rail_ble_phy_1Mbps_viterbi_38M4Hz_modemConfigBase[] = { 0xFFFFFFFFUL, }; -const uint32_t sl_rail_ble_phy_1Mbps_viterbi_38M4Hz_modemConfig[] = { +const uint32_t sl_rail_ble_phy_1Mbps_viterbi_38M4Hz_0_37_modemConfig[] = { 0x03014FFCUL, (uint32_t) &phyInfo_0, 0x00014010UL, 0x00004101UL, 0x0004403CUL, 0x00000000UL, @@ -439,7 +439,7 @@ const uint32_t sl_rail_ble_phy_1Mbps_viterbi_38M4Hz_modemConfig[] = { 0xFFFFFFFFUL, }; -const uint32_t sl_rail_ble_phy_2Mbps_viterbi_38M4Hz_0_34_modemConfig[] = { +const uint32_t sl_rail_ble_phy_2Mbps_viterbi_38M4Hz_0_37_modemConfig[] = { 0x03014FFCUL, (uint32_t) &phyInfo_1, 0x00014010UL, 0x00004101UL, 0x0004403CUL, 0x00000000UL, @@ -633,7 +633,7 @@ const uint32_t sl_rail_ble_phy_2Mbps_aox_38M4Hz_0_34_modemConfig[] = { 0xFFFFFFFFUL, }; -const uint32_t sl_rail_ble_phy_125kbps_38M4Hz_modemConfig[] = { +const uint32_t sl_rail_ble_phy_125kbps_38M4Hz_0_37_modemConfig[] = { 0x03014FFCUL, (uint32_t) &phyInfo_2, 0x00014010UL, 0x00004100UL, 0x0004403CUL, 0x00000010UL, @@ -677,9 +677,9 @@ const uint32_t sl_rail_ble_phy_125kbps_38M4Hz_modemConfig[] = { /* 40B8 */ 0x00000000UL, /* 40BC */ 0x00000000UL, /* 40C0 */ 0x00000000UL, - 0x0101411CUL, 0x8C418000UL, + 0x0101411CUL, 0x8C2C3000UL, 0x01074138UL, 0xF00A20BCUL, - /* 413C */ 0x0051B783UL, + /* 413C */ 0x0051C04AUL, /* 4140 */ 0x40000001UL, /* 4144 */ 0x123556B7UL, /* 4148 */ 0x50087800UL, @@ -730,7 +730,7 @@ const uint32_t sl_rail_ble_phy_125kbps_38M4Hz_modemConfig[] = { 0xFFFFFFFFUL, }; -const uint32_t sl_rail_ble_phy_500kbps_38M4Hz_modemConfig[] = { +const uint32_t sl_rail_ble_phy_500kbps_38M4Hz_0_37_modemConfig[] = { 0x03014FFCUL, (uint32_t) &phyInfo_3, 0x00014010UL, 0x00004100UL, 0x0004403CUL, 0x00000010UL, @@ -774,9 +774,9 @@ const uint32_t sl_rail_ble_phy_500kbps_38M4Hz_modemConfig[] = { /* 40B8 */ 0x00000000UL, /* 40BC */ 0x00000000UL, /* 40C0 */ 0x00000000UL, - 0x0101411CUL, 0x8C418000UL, + 0x0101411CUL, 0x8C2C3000UL, 0x01074138UL, 0xF00A20BCUL, - /* 413C */ 0x0051B783UL, + /* 413C */ 0x0051C04AUL, /* 4140 */ 0x40000001UL, /* 4144 */ 0x123556B7UL, /* 4148 */ 0x50087800UL, @@ -827,7 +827,7 @@ const uint32_t sl_rail_ble_phy_500kbps_38M4Hz_modemConfig[] = { 0xFFFFFFFFUL, }; -const uint32_t sl_rail_ble_phy_simulscan_38M4Hz_modemConfig[] = { +const uint32_t sl_rail_ble_phy_simulscan_38M4Hz_0_37_modemConfig[] = { 0x03014FFCUL, (uint32_t) &phyInfo_4, 0x00014010UL, 0x00004100UL, 0x0004403CUL, 0x00000010UL, @@ -926,31 +926,12 @@ const uint32_t sl_rail_ble_phy_simulscan_38M4Hz_modemConfig[] = { const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_1Mbps_viterbi_38M4Hz_channels[] = { { - .phyConfigDeltaAdd = sl_rail_ble_phy_1Mbps_viterbi_38M4Hz_modemConfig, - .baseFrequency = 2402000000, - .channelSpacing = 2000000, - .physicalChannelOffset = 0, - .channelNumberStart = 0, - .channelNumberEnd = 39, - .maxPower = RAIL_TX_POWER_MAX, - .attr = &channelConfigEntryAttr_0, -#ifdef RADIO_CONFIG_ENABLE_CONC_PHY - .entryType = 0, -#endif -#ifdef RADIO_CONFIG_ENABLE_STACK_INFO - .stackInfo = NULL, -#endif - }, -}; - -const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_2Mbps_viterbi_38M4Hz_channels[] = { - { - .phyConfigDeltaAdd = sl_rail_ble_phy_2Mbps_viterbi_38M4Hz_0_34_modemConfig, + .phyConfigDeltaAdd = sl_rail_ble_phy_1Mbps_viterbi_38M4Hz_0_37_modemConfig, .baseFrequency = 2402000000, .channelSpacing = 2000000, .physicalChannelOffset = 0, .channelNumberStart = 0, - .channelNumberEnd = 34, + .channelNumberEnd = 37, .maxPower = RAIL_TX_POWER_MAX, .attr = &channelConfigEntryAttr_0, #ifdef RADIO_CONFIG_ENABLE_CONC_PHY @@ -961,13 +942,13 @@ const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_2Mbps_viterbi_38M4Hz_channels[] #endif }, { - .phyConfigDeltaAdd = sl_rail_ble_phy_2Mbps_viterbi_38M4Hz_0_34_modemConfig, + .phyConfigDeltaAdd = sl_rail_ble_phy_1Mbps_viterbi_38M4Hz_0_37_modemConfig, .baseFrequency = 2402000000, .channelSpacing = 2000000, .physicalChannelOffset = 0, - .channelNumberStart = 35, - .channelNumberEnd = 35, - .maxPower = 182, + .channelNumberStart = 38, + .channelNumberEnd = 38, + .maxPower = 183, .attr = &channelConfigEntryAttr_0, #ifdef RADIO_CONFIG_ENABLE_CONC_PHY .entryType = 0, @@ -977,13 +958,13 @@ const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_2Mbps_viterbi_38M4Hz_channels[] #endif }, { - .phyConfigDeltaAdd = sl_rail_ble_phy_2Mbps_viterbi_38M4Hz_0_34_modemConfig, + .phyConfigDeltaAdd = sl_rail_ble_phy_1Mbps_viterbi_38M4Hz_0_37_modemConfig, .baseFrequency = 2402000000, .channelSpacing = 2000000, .physicalChannelOffset = 0, - .channelNumberStart = 36, - .channelNumberEnd = 36, - .maxPower = 157, + .channelNumberStart = 39, + .channelNumberEnd = 39, + .maxPower = 140, .attr = &channelConfigEntryAttr_0, #ifdef RADIO_CONFIG_ENABLE_CONC_PHY .entryType = 0, @@ -992,14 +973,17 @@ const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_2Mbps_viterbi_38M4Hz_channels[] .stackInfo = NULL, #endif }, +}; + +const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_2Mbps_viterbi_38M4Hz_channels[] = { { - .phyConfigDeltaAdd = sl_rail_ble_phy_2Mbps_viterbi_38M4Hz_0_34_modemConfig, + .phyConfigDeltaAdd = sl_rail_ble_phy_2Mbps_viterbi_38M4Hz_0_37_modemConfig, .baseFrequency = 2402000000, .channelSpacing = 2000000, .physicalChannelOffset = 0, - .channelNumberStart = 37, + .channelNumberStart = 0, .channelNumberEnd = 37, - .maxPower = 125, + .maxPower = RAIL_TX_POWER_MAX, .attr = &channelConfigEntryAttr_0, #ifdef RADIO_CONFIG_ENABLE_CONC_PHY .entryType = 0, @@ -1009,13 +993,13 @@ const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_2Mbps_viterbi_38M4Hz_channels[] #endif }, { - .phyConfigDeltaAdd = sl_rail_ble_phy_2Mbps_viterbi_38M4Hz_0_34_modemConfig, + .phyConfigDeltaAdd = sl_rail_ble_phy_2Mbps_viterbi_38M4Hz_0_37_modemConfig, .baseFrequency = 2402000000, .channelSpacing = 2000000, .physicalChannelOffset = 0, .channelNumberStart = 38, .channelNumberEnd = 38, - .maxPower = 83, + .maxPower = 160, .attr = &channelConfigEntryAttr_0, #ifdef RADIO_CONFIG_ENABLE_CONC_PHY .entryType = 0, @@ -1025,7 +1009,7 @@ const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_2Mbps_viterbi_38M4Hz_channels[] #endif }, { - .phyConfigDeltaAdd = sl_rail_ble_phy_2Mbps_viterbi_38M4Hz_0_34_modemConfig, + .phyConfigDeltaAdd = sl_rail_ble_phy_2Mbps_viterbi_38M4Hz_0_37_modemConfig, .baseFrequency = 2402000000, .channelSpacing = 2000000, .physicalChannelOffset = 0, @@ -1143,17 +1127,49 @@ const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_2Mbps_aox_38M4Hz_channels[] = { const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_125kbps_38M4Hz_channels[] = { { - .phyConfigDeltaAdd = sl_rail_ble_phy_125kbps_38M4Hz_modemConfig, + .phyConfigDeltaAdd = sl_rail_ble_phy_125kbps_38M4Hz_0_37_modemConfig, .baseFrequency = 2402000000, .channelSpacing = 2000000, .physicalChannelOffset = 0, .channelNumberStart = 0, - .channelNumberEnd = 39, + .channelNumberEnd = 37, .maxPower = RAIL_TX_POWER_MAX, .attr = &channelConfigEntryAttr_1, #ifdef RADIO_CONFIG_ENABLE_CONC_PHY .entryType = 0, #endif +#ifdef RADIO_CONFIG_ENABLE_STACK_INFO + .stackInfo = NULL, +#endif + }, + { + .phyConfigDeltaAdd = sl_rail_ble_phy_125kbps_38M4Hz_0_37_modemConfig, + .baseFrequency = 2402000000, + .channelSpacing = 2000000, + .physicalChannelOffset = 0, + .channelNumberStart = 38, + .channelNumberEnd = 38, + .maxPower = 183, + .attr = &channelConfigEntryAttr_1, +#ifdef RADIO_CONFIG_ENABLE_CONC_PHY + .entryType = 0, +#endif +#ifdef RADIO_CONFIG_ENABLE_STACK_INFO + .stackInfo = NULL, +#endif + }, + { + .phyConfigDeltaAdd = sl_rail_ble_phy_125kbps_38M4Hz_0_37_modemConfig, + .baseFrequency = 2402000000, + .channelSpacing = 2000000, + .physicalChannelOffset = 0, + .channelNumberStart = 39, + .channelNumberEnd = 39, + .maxPower = 140, + .attr = &channelConfigEntryAttr_1, +#ifdef RADIO_CONFIG_ENABLE_CONC_PHY + .entryType = 0, +#endif #ifdef RADIO_CONFIG_ENABLE_STACK_INFO .stackInfo = NULL, #endif @@ -1162,17 +1178,49 @@ const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_125kbps_38M4Hz_channels[] = { const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_500kbps_38M4Hz_channels[] = { { - .phyConfigDeltaAdd = sl_rail_ble_phy_500kbps_38M4Hz_modemConfig, + .phyConfigDeltaAdd = sl_rail_ble_phy_500kbps_38M4Hz_0_37_modemConfig, .baseFrequency = 2402000000, .channelSpacing = 2000000, .physicalChannelOffset = 0, .channelNumberStart = 0, - .channelNumberEnd = 39, + .channelNumberEnd = 37, .maxPower = RAIL_TX_POWER_MAX, .attr = &channelConfigEntryAttr_1, #ifdef RADIO_CONFIG_ENABLE_CONC_PHY .entryType = 0, #endif +#ifdef RADIO_CONFIG_ENABLE_STACK_INFO + .stackInfo = NULL, +#endif + }, + { + .phyConfigDeltaAdd = sl_rail_ble_phy_500kbps_38M4Hz_0_37_modemConfig, + .baseFrequency = 2402000000, + .channelSpacing = 2000000, + .physicalChannelOffset = 0, + .channelNumberStart = 38, + .channelNumberEnd = 38, + .maxPower = 183, + .attr = &channelConfigEntryAttr_1, +#ifdef RADIO_CONFIG_ENABLE_CONC_PHY + .entryType = 0, +#endif +#ifdef RADIO_CONFIG_ENABLE_STACK_INFO + .stackInfo = NULL, +#endif + }, + { + .phyConfigDeltaAdd = sl_rail_ble_phy_500kbps_38M4Hz_0_37_modemConfig, + .baseFrequency = 2402000000, + .channelSpacing = 2000000, + .physicalChannelOffset = 0, + .channelNumberStart = 39, + .channelNumberEnd = 39, + .maxPower = 140, + .attr = &channelConfigEntryAttr_1, +#ifdef RADIO_CONFIG_ENABLE_CONC_PHY + .entryType = 0, +#endif #ifdef RADIO_CONFIG_ENABLE_STACK_INFO .stackInfo = NULL, #endif @@ -1181,17 +1229,49 @@ const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_500kbps_38M4Hz_channels[] = { const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_simulscan_38M4Hz_channels[] = { { - .phyConfigDeltaAdd = sl_rail_ble_phy_simulscan_38M4Hz_modemConfig, + .phyConfigDeltaAdd = sl_rail_ble_phy_simulscan_38M4Hz_0_37_modemConfig, .baseFrequency = 2402000000, .channelSpacing = 2000000, .physicalChannelOffset = 0, .channelNumberStart = 0, - .channelNumberEnd = 39, + .channelNumberEnd = 37, .maxPower = RAIL_TX_POWER_MAX, .attr = &channelConfigEntryAttr_1, #ifdef RADIO_CONFIG_ENABLE_CONC_PHY .entryType = 0, #endif +#ifdef RADIO_CONFIG_ENABLE_STACK_INFO + .stackInfo = NULL, +#endif + }, + { + .phyConfigDeltaAdd = sl_rail_ble_phy_simulscan_38M4Hz_0_37_modemConfig, + .baseFrequency = 2402000000, + .channelSpacing = 2000000, + .physicalChannelOffset = 0, + .channelNumberStart = 38, + .channelNumberEnd = 38, + .maxPower = 183, + .attr = &channelConfigEntryAttr_1, +#ifdef RADIO_CONFIG_ENABLE_CONC_PHY + .entryType = 0, +#endif +#ifdef RADIO_CONFIG_ENABLE_STACK_INFO + .stackInfo = NULL, +#endif + }, + { + .phyConfigDeltaAdd = sl_rail_ble_phy_simulscan_38M4Hz_0_37_modemConfig, + .baseFrequency = 2402000000, + .channelSpacing = 2000000, + .physicalChannelOffset = 0, + .channelNumberStart = 39, + .channelNumberEnd = 39, + .maxPower = 140, + .attr = &channelConfigEntryAttr_1, +#ifdef RADIO_CONFIG_ENABLE_CONC_PHY + .entryType = 0, +#endif #ifdef RADIO_CONFIG_ENABLE_STACK_INFO .stackInfo = NULL, #endif @@ -1202,7 +1282,7 @@ const RAIL_ChannelConfig_t sl_rail_ble_phy_1Mbps_viterbi_38M4Hz_channelConfig = .phyConfigBase = sl_rail_ble_phy_1Mbps_viterbi_38M4Hz_modemConfigBase, .phyConfigDeltaSubtract = NULL, .configs = sl_rail_ble_phy_1Mbps_viterbi_38M4Hz_channels, - .length = 1U, + .length = 3U, .signature = 0UL, }; @@ -1210,7 +1290,7 @@ const RAIL_ChannelConfig_t sl_rail_ble_phy_2Mbps_viterbi_38M4Hz_channelConfig = .phyConfigBase = sl_rail_ble_phy_1Mbps_viterbi_38M4Hz_modemConfigBase, .phyConfigDeltaSubtract = NULL, .configs = sl_rail_ble_phy_2Mbps_viterbi_38M4Hz_channels, - .length = 6U, + .length = 3U, .signature = 0UL, }; @@ -1226,7 +1306,7 @@ const RAIL_ChannelConfig_t sl_rail_ble_phy_125kbps_38M4Hz_channelConfig = { .phyConfigBase = sl_rail_ble_phy_1Mbps_viterbi_38M4Hz_modemConfigBase, .phyConfigDeltaSubtract = NULL, .configs = sl_rail_ble_phy_125kbps_38M4Hz_channels, - .length = 1U, + .length = 3U, .signature = 0UL, }; @@ -1234,7 +1314,7 @@ const RAIL_ChannelConfig_t sl_rail_ble_phy_500kbps_38M4Hz_channelConfig = { .phyConfigBase = sl_rail_ble_phy_1Mbps_viterbi_38M4Hz_modemConfigBase, .phyConfigDeltaSubtract = NULL, .configs = sl_rail_ble_phy_500kbps_38M4Hz_channels, - .length = 1U, + .length = 3U, .signature = 0UL, }; @@ -1242,6 +1322,6 @@ const RAIL_ChannelConfig_t sl_rail_ble_phy_simulscan_38M4Hz_channelConfig = { .phyConfigBase = sl_rail_ble_phy_1Mbps_viterbi_38M4Hz_modemConfigBase, .phyConfigDeltaSubtract = NULL, .configs = sl_rail_ble_phy_simulscan_38M4Hz_channels, - .length = 1U, + .length = 3U, .signature = 0UL, }; diff --git a/platform/radio/rail_lib/plugin/rail_util_built_in_phys/efr32xg24/sl_rail_ble_config_39MHz.c b/platform/radio/rail_lib/plugin/rail_util_built_in_phys/efr32xg24/sl_rail_ble_config_39MHz.c index c21a67b72f..3c255f67d9 100644 --- a/platform/radio/rail_lib/plugin/rail_util_built_in_phys/efr32xg24/sl_rail_ble_config_39MHz.c +++ b/platform/radio/rail_lib/plugin/rail_util_built_in_phys/efr32xg24/sl_rail_ble_config_39MHz.c @@ -165,7 +165,7 @@ static const uint32_t phyInfo_2[] = { (uint32_t) NULL, 0UL, 0UL, - 999997UL, + 999978UL, (uint32_t) NULL, (uint32_t) NULL, }; @@ -187,7 +187,7 @@ static const uint32_t phyInfo_3[] = { (uint32_t) NULL, 0UL, 0UL, - 999997UL, + 999978UL, (uint32_t) NULL, (uint32_t) NULL, }; @@ -342,7 +342,7 @@ const uint32_t sl_rail_ble_phy_1Mbps_viterbi_39MHz_modemConfigBase[] = { 0xFFFFFFFFUL, }; -const uint32_t sl_rail_ble_phy_1Mbps_viterbi_39MHz_modemConfig[] = { +const uint32_t sl_rail_ble_phy_1Mbps_viterbi_39MHz_0_37_modemConfig[] = { 0x03014FFCUL, (uint32_t) &phyInfo_0, 0x00014010UL, 0x00004101UL, 0x0004403CUL, 0x00000000UL, @@ -439,7 +439,7 @@ const uint32_t sl_rail_ble_phy_1Mbps_viterbi_39MHz_modemConfig[] = { 0xFFFFFFFFUL, }; -const uint32_t sl_rail_ble_phy_2Mbps_viterbi_39MHz_0_34_modemConfig[] = { +const uint32_t sl_rail_ble_phy_2Mbps_viterbi_39MHz_0_37_modemConfig[] = { 0x03014FFCUL, (uint32_t) &phyInfo_1, 0x00014010UL, 0x00004101UL, 0x0004403CUL, 0x00000000UL, @@ -633,7 +633,7 @@ const uint32_t sl_rail_ble_phy_2Mbps_aox_39MHz_0_34_modemConfig[] = { 0xFFFFFFFFUL, }; -const uint32_t sl_rail_ble_phy_125kbps_39MHz_modemConfig[] = { +const uint32_t sl_rail_ble_phy_125kbps_39MHz_0_37_modemConfig[] = { 0x03014FFCUL, (uint32_t) &phyInfo_2, 0x00014010UL, 0x00004100UL, 0x0004403CUL, 0x00000010UL, @@ -677,9 +677,9 @@ const uint32_t sl_rail_ble_phy_125kbps_39MHz_modemConfig[] = { /* 40B8 */ 0x00000000UL, /* 40BC */ 0x00000000UL, /* 40C0 */ 0x00000000UL, - 0x0101411CUL, 0x8C418000UL, + 0x0101411CUL, 0x8C2C3000UL, 0x01074138UL, 0xF00A20BCUL, - /* 413C */ 0x0051B782UL, + /* 413C */ 0x0051C049UL, /* 4140 */ 0x40000001UL, /* 4144 */ 0x123556B7UL, /* 4148 */ 0x50087800UL, @@ -730,7 +730,7 @@ const uint32_t sl_rail_ble_phy_125kbps_39MHz_modemConfig[] = { 0xFFFFFFFFUL, }; -const uint32_t sl_rail_ble_phy_500kbps_39MHz_modemConfig[] = { +const uint32_t sl_rail_ble_phy_500kbps_39MHz_0_37_modemConfig[] = { 0x03014FFCUL, (uint32_t) &phyInfo_3, 0x00014010UL, 0x00004100UL, 0x0004403CUL, 0x00000010UL, @@ -774,9 +774,9 @@ const uint32_t sl_rail_ble_phy_500kbps_39MHz_modemConfig[] = { /* 40B8 */ 0x00000000UL, /* 40BC */ 0x00000000UL, /* 40C0 */ 0x00000000UL, - 0x0101411CUL, 0x8C418000UL, + 0x0101411CUL, 0x8C2C3000UL, 0x01074138UL, 0xF00A20BCUL, - /* 413C */ 0x0051B782UL, + /* 413C */ 0x0051C049UL, /* 4140 */ 0x40000001UL, /* 4144 */ 0x123556B7UL, /* 4148 */ 0x50087800UL, @@ -827,7 +827,7 @@ const uint32_t sl_rail_ble_phy_500kbps_39MHz_modemConfig[] = { 0xFFFFFFFFUL, }; -const uint32_t sl_rail_ble_phy_simulscan_39MHz_modemConfig[] = { +const uint32_t sl_rail_ble_phy_simulscan_39MHz_0_37_modemConfig[] = { 0x03014FFCUL, (uint32_t) &phyInfo_4, 0x00014010UL, 0x00004100UL, 0x0004403CUL, 0x00000010UL, @@ -926,31 +926,12 @@ const uint32_t sl_rail_ble_phy_simulscan_39MHz_modemConfig[] = { const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_1Mbps_viterbi_39MHz_channels[] = { { - .phyConfigDeltaAdd = sl_rail_ble_phy_1Mbps_viterbi_39MHz_modemConfig, - .baseFrequency = 2402000000, - .channelSpacing = 2000000, - .physicalChannelOffset = 0, - .channelNumberStart = 0, - .channelNumberEnd = 39, - .maxPower = RAIL_TX_POWER_MAX, - .attr = &channelConfigEntryAttr_0, -#ifdef RADIO_CONFIG_ENABLE_CONC_PHY - .entryType = 0, -#endif -#ifdef RADIO_CONFIG_ENABLE_STACK_INFO - .stackInfo = NULL, -#endif - }, -}; - -const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_2Mbps_viterbi_39MHz_channels[] = { - { - .phyConfigDeltaAdd = sl_rail_ble_phy_2Mbps_viterbi_39MHz_0_34_modemConfig, + .phyConfigDeltaAdd = sl_rail_ble_phy_1Mbps_viterbi_39MHz_0_37_modemConfig, .baseFrequency = 2402000000, .channelSpacing = 2000000, .physicalChannelOffset = 0, .channelNumberStart = 0, - .channelNumberEnd = 34, + .channelNumberEnd = 37, .maxPower = RAIL_TX_POWER_MAX, .attr = &channelConfigEntryAttr_0, #ifdef RADIO_CONFIG_ENABLE_CONC_PHY @@ -961,13 +942,13 @@ const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_2Mbps_viterbi_39MHz_channels[] = #endif }, { - .phyConfigDeltaAdd = sl_rail_ble_phy_2Mbps_viterbi_39MHz_0_34_modemConfig, + .phyConfigDeltaAdd = sl_rail_ble_phy_1Mbps_viterbi_39MHz_0_37_modemConfig, .baseFrequency = 2402000000, .channelSpacing = 2000000, .physicalChannelOffset = 0, - .channelNumberStart = 35, - .channelNumberEnd = 35, - .maxPower = 182, + .channelNumberStart = 38, + .channelNumberEnd = 38, + .maxPower = 183, .attr = &channelConfigEntryAttr_0, #ifdef RADIO_CONFIG_ENABLE_CONC_PHY .entryType = 0, @@ -977,13 +958,13 @@ const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_2Mbps_viterbi_39MHz_channels[] = #endif }, { - .phyConfigDeltaAdd = sl_rail_ble_phy_2Mbps_viterbi_39MHz_0_34_modemConfig, + .phyConfigDeltaAdd = sl_rail_ble_phy_1Mbps_viterbi_39MHz_0_37_modemConfig, .baseFrequency = 2402000000, .channelSpacing = 2000000, .physicalChannelOffset = 0, - .channelNumberStart = 36, - .channelNumberEnd = 36, - .maxPower = 157, + .channelNumberStart = 39, + .channelNumberEnd = 39, + .maxPower = 140, .attr = &channelConfigEntryAttr_0, #ifdef RADIO_CONFIG_ENABLE_CONC_PHY .entryType = 0, @@ -992,14 +973,17 @@ const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_2Mbps_viterbi_39MHz_channels[] = .stackInfo = NULL, #endif }, +}; + +const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_2Mbps_viterbi_39MHz_channels[] = { { - .phyConfigDeltaAdd = sl_rail_ble_phy_2Mbps_viterbi_39MHz_0_34_modemConfig, + .phyConfigDeltaAdd = sl_rail_ble_phy_2Mbps_viterbi_39MHz_0_37_modemConfig, .baseFrequency = 2402000000, .channelSpacing = 2000000, .physicalChannelOffset = 0, - .channelNumberStart = 37, + .channelNumberStart = 0, .channelNumberEnd = 37, - .maxPower = 125, + .maxPower = RAIL_TX_POWER_MAX, .attr = &channelConfigEntryAttr_0, #ifdef RADIO_CONFIG_ENABLE_CONC_PHY .entryType = 0, @@ -1009,13 +993,13 @@ const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_2Mbps_viterbi_39MHz_channels[] = #endif }, { - .phyConfigDeltaAdd = sl_rail_ble_phy_2Mbps_viterbi_39MHz_0_34_modemConfig, + .phyConfigDeltaAdd = sl_rail_ble_phy_2Mbps_viterbi_39MHz_0_37_modemConfig, .baseFrequency = 2402000000, .channelSpacing = 2000000, .physicalChannelOffset = 0, .channelNumberStart = 38, .channelNumberEnd = 38, - .maxPower = 83, + .maxPower = 160, .attr = &channelConfigEntryAttr_0, #ifdef RADIO_CONFIG_ENABLE_CONC_PHY .entryType = 0, @@ -1025,7 +1009,7 @@ const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_2Mbps_viterbi_39MHz_channels[] = #endif }, { - .phyConfigDeltaAdd = sl_rail_ble_phy_2Mbps_viterbi_39MHz_0_34_modemConfig, + .phyConfigDeltaAdd = sl_rail_ble_phy_2Mbps_viterbi_39MHz_0_37_modemConfig, .baseFrequency = 2402000000, .channelSpacing = 2000000, .physicalChannelOffset = 0, @@ -1143,17 +1127,49 @@ const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_2Mbps_aox_39MHz_channels[] = { const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_125kbps_39MHz_channels[] = { { - .phyConfigDeltaAdd = sl_rail_ble_phy_125kbps_39MHz_modemConfig, + .phyConfigDeltaAdd = sl_rail_ble_phy_125kbps_39MHz_0_37_modemConfig, .baseFrequency = 2402000000, .channelSpacing = 2000000, .physicalChannelOffset = 0, .channelNumberStart = 0, - .channelNumberEnd = 39, + .channelNumberEnd = 37, .maxPower = RAIL_TX_POWER_MAX, .attr = &channelConfigEntryAttr_1, #ifdef RADIO_CONFIG_ENABLE_CONC_PHY .entryType = 0, #endif +#ifdef RADIO_CONFIG_ENABLE_STACK_INFO + .stackInfo = NULL, +#endif + }, + { + .phyConfigDeltaAdd = sl_rail_ble_phy_125kbps_39MHz_0_37_modemConfig, + .baseFrequency = 2402000000, + .channelSpacing = 2000000, + .physicalChannelOffset = 0, + .channelNumberStart = 38, + .channelNumberEnd = 38, + .maxPower = 183, + .attr = &channelConfigEntryAttr_1, +#ifdef RADIO_CONFIG_ENABLE_CONC_PHY + .entryType = 0, +#endif +#ifdef RADIO_CONFIG_ENABLE_STACK_INFO + .stackInfo = NULL, +#endif + }, + { + .phyConfigDeltaAdd = sl_rail_ble_phy_125kbps_39MHz_0_37_modemConfig, + .baseFrequency = 2402000000, + .channelSpacing = 2000000, + .physicalChannelOffset = 0, + .channelNumberStart = 39, + .channelNumberEnd = 39, + .maxPower = 140, + .attr = &channelConfigEntryAttr_1, +#ifdef RADIO_CONFIG_ENABLE_CONC_PHY + .entryType = 0, +#endif #ifdef RADIO_CONFIG_ENABLE_STACK_INFO .stackInfo = NULL, #endif @@ -1162,17 +1178,49 @@ const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_125kbps_39MHz_channels[] = { const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_500kbps_39MHz_channels[] = { { - .phyConfigDeltaAdd = sl_rail_ble_phy_500kbps_39MHz_modemConfig, + .phyConfigDeltaAdd = sl_rail_ble_phy_500kbps_39MHz_0_37_modemConfig, .baseFrequency = 2402000000, .channelSpacing = 2000000, .physicalChannelOffset = 0, .channelNumberStart = 0, - .channelNumberEnd = 39, + .channelNumberEnd = 37, .maxPower = RAIL_TX_POWER_MAX, .attr = &channelConfigEntryAttr_1, #ifdef RADIO_CONFIG_ENABLE_CONC_PHY .entryType = 0, #endif +#ifdef RADIO_CONFIG_ENABLE_STACK_INFO + .stackInfo = NULL, +#endif + }, + { + .phyConfigDeltaAdd = sl_rail_ble_phy_500kbps_39MHz_0_37_modemConfig, + .baseFrequency = 2402000000, + .channelSpacing = 2000000, + .physicalChannelOffset = 0, + .channelNumberStart = 38, + .channelNumberEnd = 38, + .maxPower = 183, + .attr = &channelConfigEntryAttr_1, +#ifdef RADIO_CONFIG_ENABLE_CONC_PHY + .entryType = 0, +#endif +#ifdef RADIO_CONFIG_ENABLE_STACK_INFO + .stackInfo = NULL, +#endif + }, + { + .phyConfigDeltaAdd = sl_rail_ble_phy_500kbps_39MHz_0_37_modemConfig, + .baseFrequency = 2402000000, + .channelSpacing = 2000000, + .physicalChannelOffset = 0, + .channelNumberStart = 39, + .channelNumberEnd = 39, + .maxPower = 140, + .attr = &channelConfigEntryAttr_1, +#ifdef RADIO_CONFIG_ENABLE_CONC_PHY + .entryType = 0, +#endif #ifdef RADIO_CONFIG_ENABLE_STACK_INFO .stackInfo = NULL, #endif @@ -1181,17 +1229,49 @@ const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_500kbps_39MHz_channels[] = { const RAIL_ChannelConfigEntry_t sl_rail_ble_phy_simulscan_39MHz_channels[] = { { - .phyConfigDeltaAdd = sl_rail_ble_phy_simulscan_39MHz_modemConfig, + .phyConfigDeltaAdd = sl_rail_ble_phy_simulscan_39MHz_0_37_modemConfig, .baseFrequency = 2402000000, .channelSpacing = 2000000, .physicalChannelOffset = 0, .channelNumberStart = 0, - .channelNumberEnd = 39, + .channelNumberEnd = 37, .maxPower = RAIL_TX_POWER_MAX, .attr = &channelConfigEntryAttr_1, #ifdef RADIO_CONFIG_ENABLE_CONC_PHY .entryType = 0, #endif +#ifdef RADIO_CONFIG_ENABLE_STACK_INFO + .stackInfo = NULL, +#endif + }, + { + .phyConfigDeltaAdd = sl_rail_ble_phy_simulscan_39MHz_0_37_modemConfig, + .baseFrequency = 2402000000, + .channelSpacing = 2000000, + .physicalChannelOffset = 0, + .channelNumberStart = 38, + .channelNumberEnd = 38, + .maxPower = 183, + .attr = &channelConfigEntryAttr_1, +#ifdef RADIO_CONFIG_ENABLE_CONC_PHY + .entryType = 0, +#endif +#ifdef RADIO_CONFIG_ENABLE_STACK_INFO + .stackInfo = NULL, +#endif + }, + { + .phyConfigDeltaAdd = sl_rail_ble_phy_simulscan_39MHz_0_37_modemConfig, + .baseFrequency = 2402000000, + .channelSpacing = 2000000, + .physicalChannelOffset = 0, + .channelNumberStart = 39, + .channelNumberEnd = 39, + .maxPower = 140, + .attr = &channelConfigEntryAttr_1, +#ifdef RADIO_CONFIG_ENABLE_CONC_PHY + .entryType = 0, +#endif #ifdef RADIO_CONFIG_ENABLE_STACK_INFO .stackInfo = NULL, #endif @@ -1202,7 +1282,7 @@ const RAIL_ChannelConfig_t sl_rail_ble_phy_1Mbps_viterbi_39MHz_channelConfig = { .phyConfigBase = sl_rail_ble_phy_1Mbps_viterbi_39MHz_modemConfigBase, .phyConfigDeltaSubtract = NULL, .configs = sl_rail_ble_phy_1Mbps_viterbi_39MHz_channels, - .length = 1U, + .length = 3U, .signature = 0UL, }; @@ -1210,7 +1290,7 @@ const RAIL_ChannelConfig_t sl_rail_ble_phy_2Mbps_viterbi_39MHz_channelConfig = { .phyConfigBase = sl_rail_ble_phy_1Mbps_viterbi_39MHz_modemConfigBase, .phyConfigDeltaSubtract = NULL, .configs = sl_rail_ble_phy_2Mbps_viterbi_39MHz_channels, - .length = 6U, + .length = 3U, .signature = 0UL, }; @@ -1226,7 +1306,7 @@ const RAIL_ChannelConfig_t sl_rail_ble_phy_125kbps_39MHz_channelConfig = { .phyConfigBase = sl_rail_ble_phy_1Mbps_viterbi_39MHz_modemConfigBase, .phyConfigDeltaSubtract = NULL, .configs = sl_rail_ble_phy_125kbps_39MHz_channels, - .length = 1U, + .length = 3U, .signature = 0UL, }; @@ -1234,7 +1314,7 @@ const RAIL_ChannelConfig_t sl_rail_ble_phy_500kbps_39MHz_channelConfig = { .phyConfigBase = sl_rail_ble_phy_1Mbps_viterbi_39MHz_modemConfigBase, .phyConfigDeltaSubtract = NULL, .configs = sl_rail_ble_phy_500kbps_39MHz_channels, - .length = 1U, + .length = 3U, .signature = 0UL, }; @@ -1242,6 +1322,6 @@ const RAIL_ChannelConfig_t sl_rail_ble_phy_simulscan_39MHz_channelConfig = { .phyConfigBase = sl_rail_ble_phy_1Mbps_viterbi_39MHz_modemConfigBase, .phyConfigDeltaSubtract = NULL, .configs = sl_rail_ble_phy_simulscan_39MHz_channels, - .length = 1U, + .length = 3U, .signature = 0UL, }; diff --git a/platform/radio/rail_lib/plugin/rail_util_ieee802154/sl_rail_util_ieee802154_rail_event.c b/platform/radio/rail_lib/plugin/rail_util_ieee802154/sl_rail_util_ieee802154_rail_event.c index 1269b8c38e..44d9eb0721 100644 --- a/platform/radio/rail_lib/plugin/rail_util_ieee802154/sl_rail_util_ieee802154_rail_event.c +++ b/platform/radio/rail_lib/plugin/rail_util_ieee802154/sl_rail_util_ieee802154_rail_event.c @@ -37,6 +37,8 @@ static inline bool isReceivingFrame(RAIL_Handle_t railHandle) == RAIL_RF_STATE_RX_ACTIVE; } +static bool ack_waiting = false; + void sl_rail_util_ieee801254_on_rail_event(RAIL_Handle_t railHandle, RAIL_Events_t events) { if (events & (RAIL_EVENT_RX_SYNC1_DETECT @@ -59,11 +61,27 @@ void sl_rail_util_ieee801254_on_rail_event(RAIL_Handle_t railHandle, RAIL_Events (void) sl_rail_util_ieee802154_on_event(SL_RAIL_UTIL_IEEE802154_STACK_EVENT_TX_ABORTED, (uint32_t) RAIL_IsAutoAckWaitingForAck(railHandle)); } + if (events & RAIL_EVENT_RX_PACKET_RECEIVED) { + (void) sl_rail_util_ieee802154_on_event(SL_RAIL_UTIL_IEEE802154_STACK_EVENT_RX_ENDED, + (uint32_t) isReceivingFrame(railHandle)); + } + if (events & RAIL_EVENT_RX_ACK_TIMEOUT) { + (void) sl_rail_util_ieee802154_on_event(SL_RAIL_UTIL_IEEE802154_STACK_EVENT_TX_ACK_TIMEDOUT, 0); + } if ((events & RAIL_EVENT_TX_PACKET_SENT) != RAIL_EVENTS_NONE) { - (void) sl_rail_util_ieee802154_on_event((RAIL_IsAutoAckWaitingForAck(railHandle) + ack_waiting = RAIL_IsAutoAckWaitingForAck(railHandle); + (void) sl_rail_util_ieee802154_on_event((ack_waiting ? SL_RAIL_UTIL_IEEE802154_STACK_EVENT_TX_ACK_WAITING : SL_RAIL_UTIL_IEEE802154_STACK_EVENT_TX_ENDED), 0U); } + if (events & RAIL_EVENT_RX_PACKET_RECEIVED) { + (void) sl_rail_util_ieee802154_on_event(SL_RAIL_UTIL_IEEE802154_STACK_EVENT_RX_ENDED, + (uint32_t) isReceivingFrame(railHandle)); + if (ack_waiting) { + ack_waiting = false; + (void) sl_rail_util_ieee802154_on_event(SL_RAIL_UTIL_IEEE802154_STACK_EVENT_TX_ACK_RECEIVED, 0U); + } + } if (events & RAIL_EVENT_TX_START_CCA) { // We are starting RXWARM for a CCA check (void) sl_rail_util_ieee802154_on_event(SL_RAIL_UTIL_IEEE802154_STACK_EVENT_TX_CCA_SOON, 0U); @@ -87,6 +105,10 @@ void sl_rail_util_ieee801254_on_rail_event(RAIL_Handle_t railHandle, RAIL_Events (void) sl_rail_util_ieee802154_on_event(SL_RAIL_UTIL_IEEE802154_STACK_EVENT_RX_FILTERED, (uint32_t) isReceivingFrame(railHandle)); } + if (events & RAIL_EVENT_RX_ACK_TIMEOUT) { + ack_waiting = false; + (void) sl_rail_util_ieee802154_on_event(SL_RAIL_UTIL_IEEE802154_STACK_EVENT_TX_ACK_TIMEDOUT, 0); + } if (events & RAIL_EVENT_TXACK_PACKET_SENT) { (void) sl_rail_util_ieee802154_on_event(SL_RAIL_UTIL_IEEE802154_STACK_EVENT_RX_ACK_SENT, (uint32_t) isReceivingFrame(railHandle)); diff --git a/platform/release-highlights.txt b/platform/release-highlights.txt index 592345f0f5..041e213158 100644 --- a/platform/release-highlights.txt +++ b/platform/release-highlights.txt @@ -1,23 +1,3 @@ -Gecko Platform 4.1.0.0 - -- Initial release of CPC -- Added support for EFR32xG24; MGM240, EFR32MR21 and FGM230 -- Several code size improvements related to Power Manager, HFXO Manager and em_crypto - -- Tools and Dependencies - - Updated compiler support to GCC 10.3-2021.10 and IAR 9.20.4 - - Updated CMSIS to version 5.8.0 - -- Drivers - - Added a new component to synchronize UART/PTI settings between WSTK mainboard and the radio board - - Added support for Analog Joystick driver to use the joystick functionality on mainboard v2 - -- Security - - Mbed TLS is updated to version 3.1.0 - - Added software support for TrustZone, BETA quality - -- Bootloader - - Jedec driver support for external SPI flash - - Added a new bootloader sample application for devices with external SPI flash - +Gecko Platform 4.1.1.0 +- Targeted quality improvements and bug fixes diff --git a/platform/service/cli/inc/sl_cli_threaded_host.h b/platform/service/cli/inc/sl_cli_threaded_host.h index f2760c9223..19c061950a 100644 --- a/platform/service/cli/inc/sl_cli_threaded_host.h +++ b/platform/service/cli/inc/sl_cli_threaded_host.h @@ -55,4 +55,7 @@ void sli_cli_handle_input_and_history(sl_cli_handle_t handle); void sli_cli_threaded_host_init(void); +bool sli_cli_is_input_handled(void); + +int sli_cli_get_pipe_read_fd(void); #endif // EZSP_HOST diff --git a/platform/service/cli/src/sl_cli_threaded_host.c b/platform/service/cli/src/sl_cli_threaded_host.c index 3eb719b5e2..15697286c8 100644 --- a/platform/service/cli/src/sl_cli_threaded_host.c +++ b/platform/service/cli/src/sl_cli_threaded_host.c @@ -31,6 +31,7 @@ #include "sli_cli_io.h" #include "sl_cli_input.h" #include "sl_cli_threaded_host.h" +#include // for pipe() #if defined(EZSP_HOST) && !defined(EMBER_TEST) @@ -41,6 +42,11 @@ pthread_t thread_rx; static volatile bool tick_handle_input = false; +#define INVALID_FD -1 +static int sl_cli_threaded_host_pipe_fds[2] = { INVALID_FD, INVALID_FD }; +#define PIPE_DATA_READER sl_cli_threaded_host_pipe_fds[0] +#define PIPE_DATA_WRITER sl_cli_threaded_host_pipe_fds[1] + static inline void sema_init(struct semaphore *s, uint32_t value) { #ifdef __APPLE__ @@ -70,11 +76,22 @@ static inline void sema_post(struct semaphore *s) #endif // __APPLE__ } +bool sli_cli_is_input_handled(void) +{ + return tick_handle_input; +} + +int sli_cli_get_pipe_read_fd(void) +{ + return PIPE_DATA_READER; +} + void *threaded_tick(void *ptr) { int c; bool newline = false; tick_handle_input = false; + char newLineChars[] = "\r\n"; // used by PIPE_DATA_WRITER to wake up the host app (void) ptr; @@ -119,6 +136,8 @@ void *threaded_tick(void *ptr) } while ((c != EOF) && (!newline)); if (newline) { + // Write a new line to the pipe to wake up the host app + write(PIPE_DATA_WRITER, &newLineChars, 2); #ifdef PRINT_SEMA_POST_ACTIVITY fprintf(stderr, "[sema_post]"); #endif // PRINT_SEMA_POST_ACTIVITY @@ -159,6 +178,15 @@ void sli_cli_threaded_host_init(void) assert(0); } + // CLI is processed in a thread running threaded_tick while the host app + // can be blocked at the select() running in the main thread. Hence, create + // pipe descriptors here that can be used to wake up the host app. + iret = pipe(sl_cli_threaded_host_pipe_fds); + if (iret) { + fprintf(stderr, "pipe:%d\n", iret); + assert(0); + } + is_pthread_initilized = true; } diff --git a/platform/service/component/device_init.slcc b/platform/service/component/device_init.slcc index 7397a6c657..d4d6173acb 100644 --- a/platform/service/component/device_init.slcc +++ b/platform/service/component/device_init.slcc @@ -11,11 +11,17 @@ provides: - name: device_init requires: - name: device_init_dcdc - condition: [device_has_dcdc] + condition: [device_series_1, device_has_dcdc] + - name: device_init_dcdc + condition: [device_series_2, device_has_dcdc, device_dcdc_buck] + - name: device_init_dcdc_boost + condition: [device_series_2, device_has_dcdc, device_dcdc_boost] - name: device_init_hfrco condition: [device_sdid_200] - name: device_init_lfrco condition: [device_sdid_205, bluetooth_stack] + - name: device_init_lfrco + condition: [device_sdid_215, bluetooth_stack] - name: device_init_hfxo condition: [hardware_board_has_hfxo] - name: device_init_usbpll diff --git a/platform/service/component/iostream_swo.slcc b/platform/service/component/iostream_swo.slcc index 77510f47de..8893e2f162 100644 --- a/platform/service/component/iostream_swo.slcc +++ b/platform/service/component/iostream_swo.slcc @@ -5,6 +5,8 @@ description: IO Stream over Single Wire Output (SWO) communication protocol. category: Services|IO Stream quality: production root_path: platform/service/iostream +config_file: + - path: "config/sl_iostream_swo_config.h" provides: - name: iostream_swo - name: iostream_transport_core diff --git a/platform/service/component/legacy_hal_soc.slcc b/platform/service/component/legacy_hal_soc.slcc index e02803b2ba..a521daf3d0 100644 --- a/platform/service/component/legacy_hal_soc.slcc +++ b/platform/service/component/legacy_hal_soc.slcc @@ -27,6 +27,7 @@ requires: - name: emlib_rmu - name: status - name: token_manager + - name: legacy_hal_wdog - name: iostream_usart_core condition: - iostream diff --git a/platform/service/component/legacy_hal_wdog.slcc b/platform/service/component/legacy_hal_wdog.slcc new file mode 100644 index 0000000000..e2a6d7ab7a --- /dev/null +++ b/platform/service/component/legacy_hal_wdog.slcc @@ -0,0 +1,41 @@ +id: legacy_hal_wdog +label: Legacy HAL Watchdog +package: platform +category: Services +quality: production +description: > + Legacy HAL Watchdog. + + + SL_LEGACY_HAL_WDOGn chooses which watchdog to use. By default it's WDOG0. + + + SL_LEGACY_HAL_DISABLE_WATCHDOG disables calling halInternalEnableWatchDog in base-replacement.c's halInit() even if the component is added. +requires: + - name: component_catalog +provides: + - name: legacy_hal_wdog +root_path: ./ + +config_file: + - path: platform/service/legacy_hal_wdog/config/sl_legacy_hal_wdog_config.h + +define: + - name: SL_LEGACY_HAL_ENABLE_WATCHDOG + value: 1 + +source: + - path: platform/service/legacy_hal_wdog/src/sl_legacy_hal_wdog.c + +include: + - path: platform/service/legacy_hal_wdog/inc + file_list: + - path: sl_legacy_hal_wdog.h + +template_contribution: + - name: component_catalog + value: legacy_hal_wdog + +documentation: + docset: gecko-platform + document: service/api/group-legacyhal diff --git a/platform/service/cpc/inc/sl_cpc.h b/platform/service/cpc/inc/sl_cpc.h index 4d783e1702..8c030d6fee 100644 --- a/platform/service/cpc/inc/sl_cpc.h +++ b/platform/service/cpc/inc/sl_cpc.h @@ -31,6 +31,10 @@ #ifndef SL_CPC_H #define SL_CPC_H +#if defined(__linux__) +#error Wrong platform - this header file is intended for the secondary application +#endif + #if defined(SL_COMPONENT_CATALOG_PRESENT) #include "sl_component_catalog.h" #endif diff --git a/platform/service/cpc/inc/sli_cpc_system_common.h b/platform/service/cpc/inc/sli_cpc_system_common.h index 8870ce57a8..68c620f84c 100644 --- a/platform/service/cpc/inc/sli_cpc_system_common.h +++ b/platform/service/cpc/inc/sli_cpc_system_common.h @@ -65,7 +65,8 @@ SL_ENUM_GENERIC(sli_cpc_property_id_t, uint32_t) PROP_LAST_STATUS = 0x00, PROP_PROTOCOL_VERSION = 0x01, PROP_CAPABILITIES = 0x02, - PROP_SECONDARY_VERSION = 0x03, + PROP_SECONDARY_CPC_VERSION = 0x03, + PROP_SECONDARY_APP_VERSION = 0x04, PROP_RX_CAPABILITY = 0x20, PROP_FC_VALIDATION_VALUE = 0x30, PROP_BOOTLOADER_INFO = 0x200, diff --git a/platform/service/cpc/src/sl_cpc.c b/platform/service/cpc/src/sl_cpc.c index 71e0274cfc..5ab2f90940 100644 --- a/platform/service/cpc/src/sl_cpc.c +++ b/platform/service/cpc/src/sl_cpc.c @@ -913,7 +913,7 @@ void sli_cpc_drv_notify_tx_complete(sl_cpc_buffer_handle_t *buffer_handle) // Notify caller that it can free the tx buffer now arg->on_iframe_write_completed(arg->id, buffer_handle->data, arg->arg, SL_STATUS_TRANSMIT_INCOMPLETE); } else if ((frame_type == SLI_CPC_HDLC_FRAME_TYPE_UNNUMBERED) - && (arg->on_iframe_write_completed != NULL)) { + && (arg->on_uframe_write_completed != NULL)) { arg->on_uframe_write_completed(arg->id, buffer_handle->data, arg->arg, SL_STATUS_TRANSMIT_INCOMPLETE); } buffer_handle->data = NULL; @@ -926,6 +926,7 @@ void sli_cpc_drv_notify_tx_complete(sl_cpc_buffer_handle_t *buffer_handle) if (buffer_handle->on_write_complete_pending) { // Push to the dispatcher queue in order to call on_write_completed outside of IRQ context sli_cpc_dispatcher_push(&dispatcher_handle, process_deferred_on_write_completed, buffer_handle); + buffer_handle->on_write_complete_pending = false; } // Drop the buffer restart re_transmit_timer if it was not acknowledged (still referenced) @@ -2329,7 +2330,7 @@ static sl_status_t process_tx_queue(void) } /* - * recompute FCS as the payload is now encrypted and there is + * Recompute FCS as the payload is now encrypted and there is * an additional security tag to take into account. */ fcs = sli_cpc_get_crc_sw_with_security(frame->data, diff --git a/platform/service/cpc/src/sl_cpc_system_secondary.c b/platform/service/cpc/src/sl_cpc_system_secondary.c index 492c3102e7..56e52b6bca 100644 --- a/platform/service/cpc/src/sl_cpc_system_secondary.c +++ b/platform/service/cpc/src/sl_cpc_system_secondary.c @@ -112,6 +112,16 @@ static void enter_irq_timer_callback(sl_sleeptimer_timer_handle_t *handle, void *data); __WEAK void system_on_information_received(uint8_t endpoint_id, void *arg); +__WEAK const char* sl_cpc_secondary_app_version(void); + +/***************************************************************************//** + * Called when secondary app version is requested. + * The format is up to the user. The string should be null terminated. + ******************************************************************************/ +__WEAK const char* sl_cpc_secondary_app_version(void) +{ + return "UNDEFINED"; +} /***************************************************************************//** * Initialize CPC System @@ -453,16 +463,16 @@ static void on_property_get_protocol_version(sli_cpc_system_cmd_t *tx_command) /***************************************************************************//** * Command ID: CMD_PROPERTY_GET - * Property ID: PROP_SECONDARY_VERSION + * Property ID: PROP_SECONDARY_CPC_VERSION * Ship the hardcoded major and minor version number back to the primary. ******************************************************************************/ -static void on_property_get_secondary_version(sli_cpc_system_cmd_t *tx_command) +static void on_property_get_secondary_cpc_version(sli_cpc_system_cmd_t *tx_command) { sli_cpc_system_property_cmd_t *prop_cmd_buff; uint32_t* version; prop_cmd_buff = (sli_cpc_system_property_cmd_t*) tx_command->payload; - prop_cmd_buff->property_id = PROP_SECONDARY_VERSION; + prop_cmd_buff->property_id = PROP_SECONDARY_CPC_VERSION; version = (uint32_t*)(prop_cmd_buff->payload); version[0] = SL_GSDK_MAJOR_VERSION; @@ -472,6 +482,26 @@ static void on_property_get_secondary_version(sli_cpc_system_cmd_t *tx_command) tx_command->header.length = sizeof(sli_cpc_property_id_t) + (3 * sizeof(uint32_t)); } +/***************************************************************************//** + * Command ID: CMD_PROPERTY_GET + * Property ID: PROP_SECONDARY_APP_VERSION + * Send a string version of the secondary application to the primary + ******************************************************************************/ +static void on_property_get_secondary_app_version(sli_cpc_system_cmd_t *tx_command) +{ + sli_cpc_system_property_cmd_t *prop_cmd_buff; + const char* app_version; + uint32_t app_version_len; + + prop_cmd_buff = (sli_cpc_system_property_cmd_t*) tx_command->payload; + prop_cmd_buff->property_id = PROP_SECONDARY_APP_VERSION; + app_version = sl_cpc_secondary_app_version(); + app_version_len = strlen(app_version) + 1; + memcpy(prop_cmd_buff->payload, app_version, app_version_len > SL_CPC_RX_PAYLOAD_MAX_LENGTH ? SL_CPC_RX_PAYLOAD_MAX_LENGTH : app_version_len); + + tx_command->header.length = sizeof(sli_cpc_property_id_t) + app_version_len; +} + /***************************************************************************//** * Command ID: CMD_PROPERTY_GET * Property ID: PROP_CAPABILITIES @@ -587,15 +617,15 @@ static void on_property_get_security_state(sli_cpc_system_cmd_t *tx_command) tx_property = (sli_cpc_system_property_cmd_t*) tx_command->payload; security_state = (uint32_t*)(tx_property->payload); -#ifdef SL_CATALOG_CPC_SECURITY_SECONDARY_PRESENT +#ifdef SL_CATALOG_CPC_SECURITY_PRESENT tx_property->property_id = PROP_SECURITY_STATE; - *security_state = 0; + *security_state = sl_cpc_security_get_state(); #else tx_property->property_id = PROP_LAST_STATUS; *security_state = STATUS_UNIMPLEMENTED; #endif - tx_command->header.length = sizeof(sli_cpc_property_id_t) + sizeof(sli_cpc_system_reboot_mode_t); + tx_command->header.length = sizeof(sli_cpc_property_id_t) + sizeof(uint32_t); } /***************************************************************************//** @@ -913,8 +943,12 @@ static void on_property_get(sli_cpc_system_cmd_t *rx_command, on_property_get_protocol_version(reply); break; - case PROP_SECONDARY_VERSION: - on_property_get_secondary_version(reply); + case PROP_SECONDARY_CPC_VERSION: + on_property_get_secondary_cpc_version(reply); + break; + + case PROP_SECONDARY_APP_VERSION: + on_property_get_secondary_app_version(reply); break; case PROP_CAPABILITIES: @@ -994,7 +1028,8 @@ static void on_property_set(sli_cpc_system_cmd_t* rx_command, switch (rx_property_cmd->property_id) { case PROP_LAST_STATUS: case PROP_PROTOCOL_VERSION: - case PROP_SECONDARY_VERSION: + case PROP_SECONDARY_CPC_VERSION: + case PROP_SECONDARY_APP_VERSION: case PROP_CAPABILITIES: case PROP_BOOTLOADER_INFO: case PROP_SECURITY_STATE: @@ -1076,7 +1111,8 @@ static void on_poll(uint8_t endpoint_id, if (rx_property_cmd->property_id == PROP_RX_CAPABILITY || rx_property_cmd->property_id == PROP_CAPABILITIES || rx_property_cmd->property_id == PROP_PROTOCOL_VERSION - || rx_property_cmd->property_id == PROP_SECONDARY_VERSION) { + || rx_property_cmd->property_id == PROP_SECONDARY_CPC_VERSION + || rx_property_cmd->property_id == PROP_SECONDARY_APP_VERSION) { on_property_get(rx_command, (sli_cpc_system_cmd_t *)*reply_data, reply_data_lenght); } break; diff --git a/platform/service/iostream/config/sl_iostream_swo_config.h b/platform/service/iostream/config/sl_iostream_swo_config.h new file mode 100644 index 0000000000..4f84df2f7e --- /dev/null +++ b/platform/service/iostream/config/sl_iostream_swo_config.h @@ -0,0 +1,43 @@ +/***************************************************************************//** + * @file + * @brief SL_IOSTREAM_SWO Config. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_IOSTREAM_SWO_CONFIG_H +#define SL_IOSTREAM_SWO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SWO settings +// Only write byte per byte +// Must be enabled to be compatible with Commander SWO console +// Default: 1 +#define SL_IOSTREAM_SWO_WRITE_BYTE_PER_BYTE 1 + +// +// <<< end of configuration section >>> +#endif diff --git a/platform/service/iostream/init/sl_iostream_init_eusart_instances.c.jinja b/platform/service/iostream/init/sl_iostream_init_eusart_instances.c.jinja index 329db8f6ce..725c01ac94 100644 --- a/platform/service/iostream/init/sl_iostream_init_eusart_instances.c.jinja +++ b/platform/service/iostream/init/sl_iostream_init_eusart_instances.c.jinja @@ -62,7 +62,7 @@ sl_status_t sl_iostream_eusart_init_{{ instance }}(void) #if (SL_IOSTREAM_EUSART_{{ instance | upper }}_FLOW_CONTROL_TYPE != uartFlowControlSoftware) .flow_control = SL_IOSTREAM_EUSART_{{ instance | upper }}_FLOW_CONTROL_TYPE, #else - .flow_control = usartHwFlowControlNone, + .flow_control = eusartHwFlowControlNone, #endif .enable_high_frequency = SL_IOSTREAM_EUSART_{{ instance | upper }}_ENABLE_HIGH_FREQUENCY, .clock = SL_IOSTREAM_EUSART_CLOCK_REF(SL_IOSTREAM_EUSART_{{ instance | upper }}_PERIPHERAL_NO), diff --git a/platform/service/iostream/src/sl_iostream_swo.c b/platform/service/iostream/src/sl_iostream_swo.c index b0eac7a5a0..d941563de3 100644 --- a/platform/service/iostream/src/sl_iostream_swo.c +++ b/platform/service/iostream/src/sl_iostream_swo.c @@ -32,6 +32,7 @@ #include "sl_iostream_swo.h" #include "sl_status.h" #include "sl_debug_swo.h" +#include "sl_iostream_swo_config.h" #if defined(SL_CATALOG_POWER_MANAGER_PRESENT) #include "sl_power_manager.h" @@ -181,9 +182,12 @@ static sl_status_t swo_write(void *context, size_t buffer_length) { sl_status_t ret = SL_STATUS_OK; + uint8_t *buf_8 = (uint8_t *)buffer; +#if (SL_IOSTREAM_SWO_WRITE_BYTE_PER_BYTE == 0) uint32_t *buf_32 = (uint32_t*)(buffer); uint16_t *buf_16; - uint8_t *buf_8; +#endif + #if defined(SL_CATALOG_KERNEL_PRESENT) swo_stream_context_t *swo_context = (swo_stream_context_t *)context; if (osKernelGetState() == osKernelRunning) { @@ -196,6 +200,15 @@ static sl_status_t swo_write(void *context, (void)context; #endif +#if (SL_IOSTREAM_SWO_WRITE_BYTE_PER_BYTE == 1) + // Write buffer + for (size_t i = 0; i < buffer_length; i++) { + ret = sl_debug_swo_write_u8(0, buf_8[i]); + if (ret != SL_STATUS_OK) { + goto early_return; + } + } +#else // Write the maximum number of words while (buffer_length >= sizeof(uint32_t)) { ret = sl_debug_swo_write_u32(0, *buf_32); @@ -222,6 +235,7 @@ static sl_status_t swo_write(void *context, if (buffer_length == sizeof(uint8_t)) { ret = sl_debug_swo_write_u8(0, *buf_8); } +#endif early_return: #if defined(SL_CATALOG_KERNEL_PRESENT) diff --git a/platform/service/iostream/src/sl_iostream_uart.c b/platform/service/iostream/src/sl_iostream_uart.c index a75bdf753b..66b548f025 100644 --- a/platform/service/iostream/src/sl_iostream_uart.c +++ b/platform/service/iostream/src/sl_iostream_uart.c @@ -377,10 +377,12 @@ void sli_uart_push_rxd_data(void *context, uart_context->sleep = SL_POWER_MANAGER_WAKEUP; #endif - if (uart_context->rx_count == uart_context->rx_buffer_length) { - uint8_t xoff = XOFF; - nolock_uart_write(context, &xoff, sizeof(xoff)); - uart_context->remote_xon = false; + if (uart_context->sw_flow_control) { + if (uart_context->rx_count == uart_context->rx_buffer_length) { + uint8_t xoff = XOFF; + nolock_uart_write(context, &xoff, sizeof(xoff)); + uart_context->remote_xon = false; + } } } diff --git a/platform/service/legacy_hal/inc/bootloader-common.h b/platform/service/legacy_hal/inc/bootloader-common.h index 9826e894e5..e3ca1c590c 100644 --- a/platform/service/legacy_hal/inc/bootloader-common.h +++ b/platform/service/legacy_hal/inc/bootloader-common.h @@ -26,7 +26,12 @@ /** @brief Define the bootloader status type. */ typedef uint8_t BL_Status; +#ifndef __EMBERSTATUS_TYPE__ +#define __EMBERSTATUS_TYPE__ +#ifndef DOXYGEN_SHOULD_SKIP_THIS typedef uint8_t EmberStatus; +#endif +#endif // __EMBERSTATUS_TYPE__ #define EBL_MIN_TAG_SIZE 128U #define IMAGE_STAMP_SIZE 8U diff --git a/platform/service/legacy_hal/src/base-replacement.c b/platform/service/legacy_hal/src/base-replacement.c index 82a51e9c22..78b3e8366c 100644 --- a/platform/service/legacy_hal/src/base-replacement.c +++ b/platform/service/legacy_hal/src/base-replacement.c @@ -56,6 +56,10 @@ #include "sl_simple_button_instances.h" #endif +#if defined(SL_CATALOG_LEGACY_HAL_WDOG_PRESENT) +#include "sl_legacy_hal_wdog_config.h" +#endif + #define EMBER_SUCCESS (0x00u) #define EMBER_ERR_FATAL (0x01u) #define EMBER_SLEEP_INTERRUPTED (0x85u) @@ -153,101 +157,15 @@ void halInit(void) EMU_UnlatchPinRetention(); -#if defined(SL_LEGACY_HAL_ENABLE_WATCHDOG) && !defined(SL_LEGACY_HAL_DISABLE_WATCHDOG) +#if ((SL_LEGACY_HAL_ENABLE_WATCHDOG == 1) && (SL_LEGACY_HAL_DISABLE_WATCHDOG == 0)) halInternalEnableWatchDog(); -#endif // SL_LEGACY_HAL_ENABLE_WATCHDOG && !SL_LEGACY_HAL_DISABLE_WATCHDOG +#endif // ((SL_LEGACY_HAL_ENABLE_WATCHDOG == 1) && (SL_LEGACY_HAL_DISABLE_WATCHDOG == 0)) halInternalStartSystemTimer(); RAIL_InitTxPowerCurvesAlt(&RAIL_TxPowerCurvesVbat); } -// Watchdog functions - -void halInternalEnableWatchDog(void) -{ - // Enable LE interface -#if !defined(_SILICON_LABS_32B_SERIES_2) - CMU_ClockEnable(cmuClock_HFLE, true); - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2) && !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - CMU_ClockEnable(cmuClock_WDOG0, true); -#endif - - // Make sure FULL reset is used on WDOG timeout -#if defined(_RMU_CTRL_WDOGRMODE_MASK) - RMU_ResetControl(rmuResetWdog, rmuResetModeFull); -#endif - - WDOG_Init_TypeDef init = WDOG_INIT_DEFAULT; - -#if defined(_WDOG_CTRL_CLKSEL_MASK) - init.clkSel = wdogClkSelLFRCO; -#else - // Series 2 devices select watchdog oscillator with the CMU. - CMU_ClockSelectSet(cmuClock_WDOG0, cmuSelect_LFRCO); -#endif - - WDOGn_Init(DEFAULT_WDOG, &init); -} - -void halResetWatchdog(void) -{ -#if defined(_CMU_HFBUSCLKEN0_LE_MASK) - if ((CMU->HFBUSCLKEN0 & _CMU_HFBUSCLKEN0_LE_MASK) != 0) { - WDOGn_Feed(DEFAULT_WDOG); - } -#elif defined(_CMU_CLKEN0_WDOG0_MASK) - if ((CMU->CLKEN0 & _CMU_CLKEN0_WDOG0_MASK) != 0) { - WDOGn_Feed(DEFAULT_WDOG); - } -#else - WDOGn_Feed(DEFAULT_WDOG); -#endif -} - -void halInternalDisableWatchDog(uint8_t magicKey) -{ -#if defined(_CMU_HFBUSCLKEN0_LE_MASK) - if ((CMU->HFBUSCLKEN0 & _CMU_HFBUSCLKEN0_LE_MASK) != 0) { - if ( magicKey == MICRO_DISABLE_WATCH_DOG_KEY ) { - WDOGn_Enable(DEFAULT_WDOG, false); - } - } -#elif defined(_CMU_CLKEN0_WDOG0_MASK) - if ((CMU->CLKEN0 & _CMU_CLKEN0_WDOG0_MASK) != 0) { - if ( magicKey == MICRO_DISABLE_WATCH_DOG_KEY ) { - WDOGn_Enable(DEFAULT_WDOG, false); - } - } -#else - if ( magicKey == MICRO_DISABLE_WATCH_DOG_KEY ) { - WDOGn_Enable(DEFAULT_WDOG, false); - } -#endif -} - -bool halInternalWatchDogEnabled(void) -{ -#if defined(_CMU_HFBUSCLKEN0_LE_MASK) - if ((CMU->HFBUSCLKEN0 & _CMU_HFBUSCLKEN0_LE_MASK) != 0) { - return WDOGn_IsEnabled(DEFAULT_WDOG); - } else { - return 0; - } -#elif defined(_CMU_CLKEN0_WDOG0_MASK) - if ((CMU->CLKEN0 & _CMU_CLKEN0_WDOG0_MASK) != 0) { - return WDOGn_IsEnabled(DEFAULT_WDOG); - } else { - return 0; - } -#else - return WDOGn_IsEnabled(DEFAULT_WDOG); -#endif -} - void halReboot(void) { halInternalSysReset(RESET_SOFTWARE_REBOOT); diff --git a/platform/service/legacy_hal_wdog/config/sl_legacy_hal_wdog_config.h b/platform/service/legacy_hal_wdog/config/sl_legacy_hal_wdog_config.h new file mode 100644 index 0000000000..83b6757553 --- /dev/null +++ b/platform/service/legacy_hal_wdog/config/sl_legacy_hal_wdog_config.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file sl_legacy_hal_wdog_config.h + * @brief Legacy HAL watchdog configuration file. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_LEGACY_HAL_WDOG_CONFIG_H +#define SL_LEGACY_HAL_WDOG_CONFIG_H + +// Legacy HAL WDOG Configurations + +// Disable calling halInternalEnableWatchDog in base-replacement.c's halInit(). +// Default: 0 +#define SL_LEGACY_HAL_DISABLE_WATCHDOG 0 +// + +// WDOG to use for SL_LEGACY_HAL_WDOGn. +// Default: 0 +// <0=> WDOG0 +// <1=> WDOD1 +#define SL_LEGACY_HAL_WDOGn 0 + +// + +#endif /* SL_LEGACY_HAL_WDOG_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/platform/service/legacy_hal_wdog/inc/sl_legacy_hal_wdog.h b/platform/service/legacy_hal_wdog/inc/sl_legacy_hal_wdog.h new file mode 100644 index 0000000000..f02659bcf6 --- /dev/null +++ b/platform/service/legacy_hal_wdog/inc/sl_legacy_hal_wdog.h @@ -0,0 +1,75 @@ +/***************************************************************************//** + * @file sl_legacy_hal_wdog.h + * @brief Legacy HAL Watchdog + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories, Inc, www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#include PLATFORM_HEADER + +#include +#include "hal.h" +#include "em_cmu.h" +#include "em_wdog.h" +#include "em_rmu.h" +#include "sl_component_catalog.h" + +#include "sl_legacy_hal_wdog_config.h" + +#if (SL_LEGACY_HAL_WDOGn == 0) + +#if defined(WDOG0) +#define SL_LEGACY_HAL_WDOG WDOG0 +#endif // WDOG0 + +#if defined(WDOG0_IRQn) +#define SL_LEGACY_HAL_WDOG_IRQn WDOG0_IRQn +#endif // WDOG0_IRQn + +#if defined(WDOG0_IRQHandler) +#define SL_LEGACY_HAL_WDOG_IRQHandler (WDOG0_IRQHandler) +#endif // WDOG0_IRQHandler + +#if cmuClock_WDOG0 +#define SL_LEGACY_HAL_WDOG_CMUCLOCK (cmuClock_WDOG0) +#endif // cmuClock_WDOG0 + +#if _CMU_CLKEN0_WDOG0_MASK +#define SL_LEGACY_HAL_WDOG_CMU_CLKENx_WDOGx_MASK (_CMU_CLKEN0_WDOG0_MASK) +#endif //_CMU_CLKEN0_WDOG0_MASK + +#endif + +#if (SL_LEGACY_HAL_WDOGn == 1) + +#if defined(WDOG1) +#define SL_LEGACY_HAL_WDOG WDOG1 +#endif // WDOG1 + +#if defined(WDOG1_IRQn) +#define SL_LEGACY_HAL_WDOG_IRQn WDOG1_IRQn +#endif // WDOG1_IRQn + +#if defined(WDOG1_IRQHandler) +#define SL_LEGACY_HAL_WDOG_IRQHandler (WDOG1_IRQHandler) +#endif // WDOG1_IRQHandler + +#if cmuClock_WDOG1 +#define SL_LEGACY_HAL_WDOG_CMUCLOCK (cmuClock_WDOG1) +#endif // cmuClock_WDOG1 + +#if _CMU_CLKEN1_WDOG1_MASK +#define SL_LEGACY_HAL_WDOG_CMU_CLKENx_WDOGx_MASK (_CMU_CLKEN1_WDOG1_MASK) +#endif //_CMU_CLKEN1_WDOG1_MASK + +#endif diff --git a/platform/service/legacy_hal_wdog/src/sl_legacy_hal_wdog.c b/platform/service/legacy_hal_wdog/src/sl_legacy_hal_wdog.c new file mode 100644 index 0000000000..81c408cd5d --- /dev/null +++ b/platform/service/legacy_hal_wdog/src/sl_legacy_hal_wdog.c @@ -0,0 +1,147 @@ +/***************************************************************************//** + * @file sl_legacy_hal_wdog.c + * @brief Legacy HAL Watchdog + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories, Inc, www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#include PLATFORM_HEADER +#include "sl_legacy_hal_wdog.h" + +// sl_legacy_hal_wdog.h needs to be able to define all SL_LEGACY_HAL_WDOG_* +// before these function will compile. +#if defined(SL_LEGACY_HAL_WDOG) \ + && defined(SL_LEGACY_HAL_WDOG_IRQn) \ + && defined(SL_LEGACY_HAL_WDOG_IRQHandler) \ + && defined(SL_LEGACY_HAL_WDOG_CMUCLOCK) \ + && defined(SL_LEGACY_HAL_WDOG_CMU_CLKENx_WDOGx_MASK) + +void halInternalEnableWatchDog(void) +{ + // Enable LE interface +#if !defined(_SILICON_LABS_32B_SERIES_2) + CMU_ClockEnable(cmuClock_HFLE, true); + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2) && !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + CMU_ClockEnable(SL_LEGACY_HAL_WDOG_CMUCLOCK, true); +#endif + + // Make sure FULL reset is used on WDOG timeout +#if defined(_RMU_CTRL_WDOGRMODE_MASK) + RMU_ResetControl(rmuResetWdog, rmuResetModeFull); +#endif + + /* Note: WDOG_INIT_DEFAULT comes from platform/emlib/inc/em_wdog.h */ + WDOG_Init_TypeDef init = WDOG_INIT_DEFAULT; + + /* Trigger watchdog reset after 2 seconds (64k / 32k) and + * warning interrupt is triggered after 1.5 seconds (75% of timeout). */ + init.perSel = wdogPeriod_64k; + init.warnSel = wdogWarnTime75pct; + +#if defined(_WDOG_CTRL_CLKSEL_MASK) + init.clkSel = wdogClkSelLFRCO; +#else + // Series 2 devices select watchdog oscillator with the CMU. + CMU_ClockSelectSet(SL_LEGACY_HAL_WDOG_CMUCLOCK, cmuSelect_LFRCO); +#endif + + WDOGn_Init(SL_LEGACY_HAL_WDOG, &init); + + /* Enable WARN interrupt. */ +#if defined(WDOG_IF_WARN) && !defined(BOOTLOADER) + NVIC_ClearPendingIRQ(SL_LEGACY_HAL_WDOG_IRQn); + WDOGn_IntClear(SL_LEGACY_HAL_WDOG, WDOG_IF_WARN); + NVIC_EnableIRQ(SL_LEGACY_HAL_WDOG_IRQn); + WDOGn_IntEnable(SL_LEGACY_HAL_WDOG, WDOG_IEN_WARN); +#endif +} + +void halResetWatchdog(void) +{ +#if defined(_CMU_HFBUSCLKEN0_LE_MASK) + if ((CMU->HFBUSCLKEN0 & _CMU_HFBUSCLKEN0_LE_MASK) != 0) { + WDOGn_Feed(SL_LEGACY_HAL_WDOG); + } +#elif defined(SL_LEGACY_HAL_WDOG_CMU_CLKENx_WDOGx_MASK) + if ((CMU->CLKEN0 & SL_LEGACY_HAL_WDOG_CMU_CLKENx_WDOGx_MASK) != 0) { + WDOGn_Feed(SL_LEGACY_HAL_WDOG); + } +#else + WDOGn_Feed(SL_LEGACY_HAL_WDOG); +#endif +} + +void halInternalDisableWatchDog(uint8_t magicKey) +{ +#if defined(_CMU_HFBUSCLKEN0_LE_MASK) + if ((CMU->HFBUSCLKEN0 & _CMU_HFBUSCLKEN0_LE_MASK) != 0) { + if ( magicKey == MICRO_DISABLE_WATCH_DOG_KEY ) { + WDOGn_Enable(SL_LEGACY_HAL_WDOG, false); + } + } +#elif defined(SL_LEGACY_HAL_WDOG_CMU_CLKENx_WDOGx_MASK) + if ((CMU->CLKEN0 & SL_LEGACY_HAL_WDOG_CMU_CLKENx_WDOGx_MASK) != 0) { + if ( magicKey == MICRO_DISABLE_WATCH_DOG_KEY ) { + WDOGn_Enable(SL_LEGACY_HAL_WDOG, false); + } + } +#else + if ( magicKey == MICRO_DISABLE_WATCH_DOG_KEY ) { + WDOGn_Enable(SL_LEGACY_HAL_WDOG, false); + } +#endif +} + +bool halInternalWatchDogEnabled(void) +{ +#if defined(_CMU_HFBUSCLKEN0_LE_MASK) + if ((CMU->HFBUSCLKEN0 & _CMU_HFBUSCLKEN0_LE_MASK) != 0) { + return WDOGn_IsEnabled(SL_LEGACY_HAL_WDOG); + } else { + return 0; + } +#elif defined(SL_LEGACY_HAL_WDOG_CMU_CLKENx_WDOGx_MASK) + if ((CMU->CLKEN0 & SL_LEGACY_HAL_WDOG_CMU_CLKENx_WDOGx_MASK) != 0) { + return WDOGn_IsEnabled(SL_LEGACY_HAL_WDOG); + } else { + return 0; + } +#else + return WDOGn_IsEnabled(SL_LEGACY_HAL_WDOG); +#endif +} + +#else + +void halInternalEnableWatchDog(void) +{ +} + +void halResetWatchdog(void) +{ +} + +void halInternalDisableWatchDog(uint8_t magicKey) +{ + (void) magicKey; +} + +bool halInternalWatchDogEnabled(void) +{ + return false; +} + +#endif diff --git a/platform/service/sim_eeprom/sim_eeprom1/lib/libsim_eeprom1_CM4_gcc.a b/platform/service/sim_eeprom/sim_eeprom1/lib/libsim_eeprom1_CM4_gcc.a index c063e13b55..0e06853085 100644 --- a/platform/service/sim_eeprom/sim_eeprom1/lib/libsim_eeprom1_CM4_gcc.a +++ b/platform/service/sim_eeprom/sim_eeprom1/lib/libsim_eeprom1_CM4_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:58827a1c97219541ff4b0be2f714fca02af9d51f613ee86774e3a01ed76bd8ed +oid sha256:9805b0a5612eee82dd222f809b25b6ba0180061f646b7d76fc9a2aece05d3129 size 43360 diff --git a/platform/service/sim_eeprom/sim_eeprom1/lib/libsim_eeprom1_CM4_iar.a b/platform/service/sim_eeprom/sim_eeprom1/lib/libsim_eeprom1_CM4_iar.a index cc7af10cbc..4632dfb4f1 100644 --- a/platform/service/sim_eeprom/sim_eeprom1/lib/libsim_eeprom1_CM4_iar.a +++ b/platform/service/sim_eeprom/sim_eeprom1/lib/libsim_eeprom1_CM4_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a830d4a6a81811ceabac52731748c6156b79ea6fb631e0c58cdf7729fa5aa90d -size 30368 +oid sha256:df0b6b9dda8a166a03cda8457fb6885a4d9dd9dafe117fa470e0499f3f888804 +size 30366 diff --git a/platform/service/sim_eeprom/sim_eeprom1_to_sim_eeprom2_upgrade/lib/libsim_eeprom1_to_sim_eeprom2_upgrade_CM4_gcc.a b/platform/service/sim_eeprom/sim_eeprom1_to_sim_eeprom2_upgrade/lib/libsim_eeprom1_to_sim_eeprom2_upgrade_CM4_gcc.a index bc9af93182..7c36e889a3 100644 --- a/platform/service/sim_eeprom/sim_eeprom1_to_sim_eeprom2_upgrade/lib/libsim_eeprom1_to_sim_eeprom2_upgrade_CM4_gcc.a +++ b/platform/service/sim_eeprom/sim_eeprom1_to_sim_eeprom2_upgrade/lib/libsim_eeprom1_to_sim_eeprom2_upgrade_CM4_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:df5ccfa1ccf3cf6b85daee77f9daee05fbd59c5bd2b33eb1a430a1a165e3e3af +oid sha256:b7ff4742fd3e9b4893b0c48fd6515912bf3e0e66c3c06ea84c49c3c4806b83e1 size 31290 diff --git a/platform/service/sim_eeprom/sim_eeprom1_to_sim_eeprom2_upgrade/lib/libsim_eeprom1_to_sim_eeprom2_upgrade_CM4_iar.a b/platform/service/sim_eeprom/sim_eeprom1_to_sim_eeprom2_upgrade/lib/libsim_eeprom1_to_sim_eeprom2_upgrade_CM4_iar.a index 29a1346f65..10a818ef3b 100644 --- a/platform/service/sim_eeprom/sim_eeprom1_to_sim_eeprom2_upgrade/lib/libsim_eeprom1_to_sim_eeprom2_upgrade_CM4_iar.a +++ b/platform/service/sim_eeprom/sim_eeprom1_to_sim_eeprom2_upgrade/lib/libsim_eeprom1_to_sim_eeprom2_upgrade_CM4_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1f1f089b711a46e0b8f49aca0293d2190f2a227cb5b041f63591dc03be3fa453 +oid sha256:431ac558e494d984597313c368adf0ae9b0ef98b5764bad49e4ab084528a4ffd size 19654 diff --git a/platform/service/sim_eeprom/sim_eeprom2/lib/libsim_eeprom2_CM4_gcc.a b/platform/service/sim_eeprom/sim_eeprom2/lib/libsim_eeprom2_CM4_gcc.a index dc5ecdae0b..be2a57861d 100644 --- a/platform/service/sim_eeprom/sim_eeprom2/lib/libsim_eeprom2_CM4_gcc.a +++ b/platform/service/sim_eeprom/sim_eeprom2/lib/libsim_eeprom2_CM4_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:02f54540e5fc148284a692b650377713b0ceb619bd30f618dc4bff3acce5ce85 +oid sha256:ac3bc12882cdc1c06e1b61909f8cdc0e16a340a75198d6af155022a867e74708 size 54856 diff --git a/platform/service/sim_eeprom/sim_eeprom2/lib/libsim_eeprom2_CM4_iar.a b/platform/service/sim_eeprom/sim_eeprom2/lib/libsim_eeprom2_CM4_iar.a index 7d22cc895d..f76ba09521 100644 --- a/platform/service/sim_eeprom/sim_eeprom2/lib/libsim_eeprom2_CM4_iar.a +++ b/platform/service/sim_eeprom/sim_eeprom2/lib/libsim_eeprom2_CM4_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:30a4c594f554c67576b17e73f3ba3457d26fa63dd8c05e155b0c6202a0c25f57 -size 49084 +oid sha256:e08a27f1aa58abb1d458475524d0359eda008f22dccab88ce4fb128e73fb3532 +size 49082 diff --git a/platform/service/sim_eeprom/sim_eeprom2_to_nvm3_upgrade/lib/libsim_eeprom2_to_nvm3_upgrade_CM4_gcc.a b/platform/service/sim_eeprom/sim_eeprom2_to_nvm3_upgrade/lib/libsim_eeprom2_to_nvm3_upgrade_CM4_gcc.a index 2241e627ce..777f37be7b 100644 --- a/platform/service/sim_eeprom/sim_eeprom2_to_nvm3_upgrade/lib/libsim_eeprom2_to_nvm3_upgrade_CM4_gcc.a +++ b/platform/service/sim_eeprom/sim_eeprom2_to_nvm3_upgrade/lib/libsim_eeprom2_to_nvm3_upgrade_CM4_gcc.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:669290372cb428b7e0396126174f9b33fed2dfe0a6379904150cc26de3a0ba59 +oid sha256:feabba3202932f4e0105b495f92eb8de3b5aeaf859a82f8b41e5547bd12e0402 size 21194 diff --git a/platform/service/sim_eeprom/sim_eeprom2_to_nvm3_upgrade/lib/libsim_eeprom2_to_nvm3_upgrade_CM4_iar.a b/platform/service/sim_eeprom/sim_eeprom2_to_nvm3_upgrade/lib/libsim_eeprom2_to_nvm3_upgrade_CM4_iar.a index 5fa52403f1..75d19ada76 100644 --- a/platform/service/sim_eeprom/sim_eeprom2_to_nvm3_upgrade/lib/libsim_eeprom2_to_nvm3_upgrade_CM4_iar.a +++ b/platform/service/sim_eeprom/sim_eeprom2_to_nvm3_upgrade/lib/libsim_eeprom2_to_nvm3_upgrade_CM4_iar.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:adf1f60ac36bef004eae4ae8cfff87eb1d2a4478f727106129a70bfe12992648 +oid sha256:e3ecf536949e3e4e1d95eb135eb186db145f333e9cf51ca45dfe701843696464 size 11724 diff --git a/platform/service/token_manager/src/sl_token_def.c b/platform/service/token_manager/src/sl_token_def.c index 8607a234b1..7e877ab12e 100644 --- a/platform/service/token_manager/src/sl_token_def.c +++ b/platform/service/token_manager/src/sl_token_def.c @@ -18,8 +18,7 @@ #include #include #define EUI64_SIZE 8 -typedef uint8_t EmberEUI64[EUI64_SIZE]; -typedef uint16_t EmberNodeId; +#include "ember-types.h" #include "stack/config/ember-configuration-defaults.h" //-- Build structure defines (these define all the data types of the tokens). diff --git a/protocol/bluetooth/api/sl_bt.xapi b/protocol/bluetooth/api/sl_bt.xapi index 9e76e5e548..18bd900a95 100644 --- a/protocol/bluetooth/api/sl_bt.xapi +++ b/protocol/bluetooth/api/sl_bt.xapi @@ -1,5 +1,5 @@ - + @@ -2037,6 +2037,11 @@ + + + + + diff --git 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a/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg12_iar_release.a +++ b/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg12_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d7f584d880082b642d51f4752e125f9c569d458d40f71a9bf0300b2dd8bd2fcb -size 464910 +oid sha256:bfc75aed87686280419aec75609b57e601c0f6091c87b21b8ddfcd573d1e6b63 +size 465842 diff --git a/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg13_gcc_release.a b/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg13_gcc_release.a index 86a43ac557..59e89d3bc4 100644 --- a/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg13_gcc_release.a +++ b/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg13_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5da42d268237755f55a050437fffc1d6d14db6c865b7e105dbad02cf2d354803 -size 243438 +oid sha256:1da2d606e157fac7ffddb8d95b4c1ef2cfe18d72f3a8cc7345dd30098a2643ad +size 243684 diff --git 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a/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg1_gcc_release.a +++ b/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg1_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8b9530d6202136566bf99d2c5d02ca7e373038585a174d98221f418ffeaaed9a -size 243430 +oid sha256:aff55ca5263dd285a05c602c36e739e0c8d973d2dc5a0b9002eba0b88508ca12 +size 243668 diff --git a/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg1_iar_release.a b/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg1_iar_release.a index bb2094e6fb..7f9442027c 100644 --- a/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg1_iar_release.a +++ b/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg1_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:777f5c31637d291f2d80e8631b5984066665e8f2ea68d39b4f7b4e4d5247f5ac -size 464866 +oid sha256:29855701821675903dfc386ce5129b91a32992cf02020c668a5b9029c5b6883f +size 465790 diff --git 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a/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg22_iar_release.a +++ b/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg22_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e987607071d66f2f344b12ebc2575973509872ffb77cef8aec89382a7a3b3ac2 -size 477510 +oid sha256:560410b336555956ab2fee7782cf0fb0b34fb5babd57cc1f748a0f402229a254 +size 478432 diff --git a/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg24_gcc_release.a b/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg24_gcc_release.a index 9be5e18d0f..1088fbc057 100644 --- a/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg24_gcc_release.a +++ b/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg24_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2750eb3b11a928d8e363889bf468420a67dfed288c6efaf46c8731b9c7fad9d3 -size 239970 +oid sha256:a5b86d1982903bdf3bd66da31cd44473bdedd4b3916902a1db7fee26fca6cb12 +size 240220 diff --git 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a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg12_gcc_release.a +++ b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg12_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:77ad364b15d71b15b91511f22bd865d6a28f29a9c23e13c53cff6e1e776416ba -size 6305122 +oid sha256:91b0f125daffdfb60a2086cc47a3b35703cc37986ed0f43ecbdcb57acbc2299c +size 6391476 diff --git a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg12_iar_release.a b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg12_iar_release.a index 0800f43a26..30531ee12d 100644 --- a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg12_iar_release.a +++ b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg12_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1ddd4b3372a08dd168d34a9560b73feb65ebeebc0793a9d00afea12c0f4a8aae -size 14672008 +oid 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a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg21_iar_release.a +++ b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg21_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:03108ec87fdf499df3df3c46ecf50b34342eb36245e60429f0a18036ffd9ba73 -size 14836768 +oid sha256:354dd5ce5e1647303506ced57da736a051f8424f2d8b3fc8ecf04dcc8163d53d +size 15463860 diff --git a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg22_gcc_release.a b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg22_gcc_release.a index 33db2a1499..8e24d5a0f9 100644 --- a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg22_gcc_release.a +++ b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg22_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1331a3188c9af97f47aaa57f84b6a7963322c4bc749a5742973c183ec13e056a -size 6354562 +oid sha256:4b70e726e72002d2563259f22b7eacbbe23ce5b093e33ea4dbb114cf2743b29b +size 6440908 diff --git a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg22_iar_release.a b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg22_iar_release.a index fe2d9d1ab1..d219c3f190 100644 --- a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg22_iar_release.a +++ b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg22_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1c34ccf74884ce6a6f507d13ba08cb18a435b750ec35d2429636d7bcd8b17921 -size 14856678 +oid sha256:00eba7bbe643491587629a509bcebd8dff9dbfa4d345257a2eaaa521d27a3c61 +size 15483612 diff --git a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg24_gcc_release.a b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg24_gcc_release.a index c8923e70e0..f73acaf63e 100644 --- a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg24_gcc_release.a +++ b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg24_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:cf7ef2202c0d1ae85c33054a0af1e52f518919f6107968c41c202f37e2f9b537 -size 6364290 +oid sha256:a33a329d66c145d74a13c4615f13d75e9075a2ecc5b847dc6fcc107e4a2b1297 +size 6450604 diff --git a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg24_iar_release.a b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg24_iar_release.a index 9d90592e9b..374cefc2dd 100644 --- a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg24_iar_release.a +++ b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg24_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c5ab0a8fc3e6ac12a526da4b2f5c1358306d363ffa6e19d0b15dffd8edce17be -size 14870260 +oid sha256:416ece7758e147272895f8a956ae258ee71cbf393313ae1ee5f3096ab5ee46f0 +size 15497108 diff --git a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg27_gcc_release.a b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg27_gcc_release.a index b5ca79b115..ae652496e3 100644 --- a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg27_gcc_release.a +++ b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg27_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0811e21075a87b3293c4f3afc39c7e898d24ca09098fe65f5a689c3691264859 -size 6355526 +oid sha256:ec45f2769cc7d9e88a1b4411bb05e8a43d1b6973f0faefdb0b80085d8d4ccda4 +size 6441816 diff --git a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg27_iar_release.a b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg27_iar_release.a index c205bccfc2..933bdcea83 100644 --- a/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg27_iar_release.a +++ b/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg27_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c8c5f0840a8a4e1efd51985110a7c7b2d99ecc6e21da91ca40727416da61a288 -size 14865552 +oid sha256:459ddc71c79a42ffb1a2d7a470de120dc169272faeba4df16d38337b4cdf9513 +size 15492398 diff --git a/protocol/bluetooth/component/apploader.slcc b/protocol/bluetooth/component/apploader.slcc index 4239c70275..637565afb0 100644 --- a/protocol/bluetooth/component/apploader.slcc +++ b/protocol/bluetooth/component/apploader.slcc @@ -1,8 +1,16 @@ id: "apploader" -label: "AppLoader application binary for EFR series 1 devices" +label: "AppLoader Support for Applications" package: "Bluetooth" description: > - Bluetooth Apploader application for OTA DFU. + Bluetooth AppLoader application for OTA DFU. + + On series 1 devices, this component adds AppLoader binary to the application. + + On series 2 and above devices, it moves the application start address to give space for an AppLoader OTA DFU + Bootloader. It also requires a Gecko Bootloader with an AppLoader OTA DFU plugin to be present on the device. + + AppLoader is a minimal version of the Bluetooth stack designed to enable device firmware updates over BLE connections + It allows to update application using in-place update where the old application is directly overwritten with the new one. category: "Bluetooth|OTA" quality: "production" root_path: "protocol/bluetooth" diff --git a/protocol/bluetooth/component/apploader_lib.slcc b/protocol/bluetooth/component/apploader_lib.slcc index c93752ea0e..71870e91fb 100644 --- a/protocol/bluetooth/component/apploader_lib.slcc +++ b/protocol/bluetooth/component/apploader_lib.slcc @@ -1,9 +1,11 @@ id: "apploader_lib" -label: "AppLoader library for EFR series 2 and above" +label: "AppLoader library for Gecko Bootloader" package: "Bluetooth" description: > - Bluetooth Apploader library for OTA DFU. The Apploader runs as a plugin - of the Bootloader. + Bluetooth AppLoader library for Gecko Bootloader with AppLoader OTA DFU plugin for series 2 devices and above. + + AppLoader is a minimal version of the Bluetooth stack designed to enable device firmware updates over BLE connections + It allows to update application using in-place update where the old application is directly overwritten with the new one. category: "Bluetooth|OTA" quality: "production" root_path: "protocol/bluetooth" diff --git a/protocol/bluetooth/component/apploader_util.slcc b/protocol/bluetooth/component/apploader_util.slcc index 89da33a729..b0f6de41f6 100644 --- a/protocol/bluetooth/component/apploader_util.slcc +++ b/protocol/bluetooth/component/apploader_util.slcc @@ -1,5 +1,5 @@ id: "apploader_util" -label: "Apploader Utility" +label: "AppLoader Utility" package: "Bluetooth" description: > This component provides utility functions related to OTA DFU, such as a diff --git a/protocol/bluetooth/component/bluetooth_feature_legacy_scanner.slcc b/protocol/bluetooth/component/bluetooth_feature_legacy_scanner.slcc index c9202786e7..60545a1362 100644 --- a/protocol/bluetooth/component/bluetooth_feature_legacy_scanner.slcc +++ b/protocol/bluetooth/component/bluetooth_feature_legacy_scanner.slcc @@ -22,7 +22,7 @@ requires: - name: "bluetooth_controller" - name: "bluetooth_feature_scanner" provides: - - name: "bluetooth_feature_legcy_scanner" + - name: "bluetooth_feature_legacy_scanner" - name: "bluetooth_feature_central_connection" allow_multiple: true - name: "bluetooth_feature_connection_creation" diff --git a/protocol/bluetooth/component/bluetooth_feature_whitelisting.slcc b/protocol/bluetooth/component/bluetooth_feature_whitelisting.slcc index 1a678f04fb..244bf9d53d 100644 --- a/protocol/bluetooth/component/bluetooth_feature_whitelisting.slcc +++ b/protocol/bluetooth/component/bluetooth_feature_whitelisting.slcc @@ -14,6 +14,7 @@ root_path: "protocol/bluetooth" requires: - name: "bluetooth_stack" - name: "bluetooth_feature_gap" + - name: "bluetooth_feature_scanner" provides: - name: "bluetooth_feature_whitelisting" template_contribution: diff --git a/protocol/bluetooth/component/btmesh_crypto.slcc b/protocol/bluetooth/component/btmesh_crypto.slcc index 496f04fda2..9192004a54 100644 --- a/protocol/bluetooth/component/btmesh_crypto.slcc +++ b/protocol/bluetooth/component/btmesh_crypto.slcc @@ -101,11 +101,5 @@ requires: - name: "btmesh_feature_crypto_key_cache" condition: - "device_series_2" - unless: - - "trustzone_nonsecure" - - name: "btmesh_feature_crypto_key_cache_dummy" - condition: - - "device_series_2" - - "trustzone_nonsecure" provides: - name: "btmesh_crypto" diff --git a/protocol/bluetooth/component/btmesh_feature_crypto_key_cache.slcc b/protocol/bluetooth/component/btmesh_feature_crypto_key_cache.slcc index 2cd63469cf..2497b5e2e3 100644 --- a/protocol/bluetooth/component/btmesh_feature_crypto_key_cache.slcc +++ b/protocol/bluetooth/component/btmesh_feature_crypto_key_cache.slcc @@ -11,126 +11,322 @@ library: condition: - "toolchain_gcc" - "device_family_efr32bg21" + unless: + - "trustzone_nonsecure" - path: "lib/EFR32BG21/IAR/libbtmesh_crypto_key_cache.a" condition: - "toolchain_iar" - "device_family_efr32bg21" + unless: + - "trustzone_nonsecure" + - path: "lib/EFR32BG21/GCC/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_gcc" + - "device_family_efr32bg21" + - "trustzone_nonsecure" + - path: "lib/EFR32BG21/IAR/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_iar" + - "device_family_efr32bg21" + - "trustzone_nonsecure" #BGM21 - path: "lib/EFR32BG21/GCC/libbtmesh_crypto_key_cache.a" condition: - "toolchain_gcc" - "device_family_bgm21" + unless: + - "trustzone_nonsecure" - path: "lib/EFR32BG21/IAR/libbtmesh_crypto_key_cache.a" condition: - "toolchain_iar" - "device_family_bgm21" + unless: + - "trustzone_nonsecure" + - path: "lib/EFR32BG21/GCC/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_gcc" + - "device_family_bgm21" + - "trustzone_nonsecure" + - path: "lib/EFR32BG21/IAR/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_iar" + - "device_family_bgm21" + - "trustzone_nonsecure" #EFR32MG21 - path: "lib/EFR32MG21/GCC/libbtmesh_crypto_key_cache.a" condition: - "toolchain_gcc" - "device_family_efr32mg21" + unless: + - "trustzone_nonsecure" - path: "lib/EFR32MG21/IAR/libbtmesh_crypto_key_cache.a" condition: - "toolchain_iar" - "device_family_efr32mg21" + unless: + - "trustzone_nonsecure" + - path: "lib/EFR32MG21/GCC/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_gcc" + - "device_family_efr32mg21" + - "trustzone_nonsecure" + - path: "lib/EFR32MG21/IAR/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_iar" + - "device_family_efr32mg21" + - "trustzone_nonsecure" #MGM21 - path: "lib/EFR32MG21/GCC/libbtmesh_crypto_key_cache.a" condition: - "toolchain_gcc" - "device_family_mgm21" + unless: + - "trustzone_nonsecure" - path: "lib/EFR32MG21/IAR/libbtmesh_crypto_key_cache.a" condition: - "toolchain_iar" - "device_family_mgm21" + unless: + - "trustzone_nonsecure" + - path: "lib/EFR32MG21/GCC/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_gcc" + - "device_family_mgm21" + - "trustzone_nonsecure" + - path: "lib/EFR32MG21/IAR/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_iar" + - "device_family_mgm21" + - "trustzone_nonsecure" #EFR32BG22 - path: "lib/EFR32BG22/GCC/libbtmesh_crypto_key_cache.a" condition: - "toolchain_gcc" - "device_family_efr32bg22" + unless: + - "trustzone_nonsecure" - path: "lib/EFR32BG22/IAR/libbtmesh_crypto_key_cache.a" condition: - "toolchain_iar" - "device_family_efr32bg22" + unless: + - "trustzone_nonsecure" + - path: "lib/EFR32BG22/GCC/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_gcc" + - "device_family_efr32bg22" + - "trustzone_nonsecure" + - path: "lib/EFR32BG22/IAR/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_iar" + - "device_family_efr32bg22" + - "trustzone_nonsecure" #BGM22 - path: "lib/EFR32BG22/GCC/libbtmesh_crypto_key_cache.a" condition: - "toolchain_gcc" - "device_family_bgm22" + unless: + - "trustzone_nonsecure" - path: "lib/EFR32BG22/IAR/libbtmesh_crypto_key_cache.a" condition: - "toolchain_iar" - "device_family_bgm22" + unless: + - "trustzone_nonsecure" + - path: "lib/EFR32BG22/GCC/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_gcc" + - "device_family_bgm22" + - "trustzone_nonsecure" + - path: "lib/EFR32BG22/IAR/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_iar" + - "device_family_bgm22" + - "trustzone_nonsecure" #EFR32MG22 - path: "lib/EFR32MG22/GCC/libbtmesh_crypto_key_cache.a" condition: - "toolchain_gcc" - "device_family_efr32mg22" + unless: + - "trustzone_nonsecure" - path: "lib/EFR32MG22/IAR/libbtmesh_crypto_key_cache.a" condition: - "toolchain_iar" - "device_family_efr32mg22" -#EFR32MG22 + unless: + - "trustzone_nonsecure" + - path: "lib/EFR32MG22/GCC/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_gcc" + - "device_family_efr32mg22" + - "trustzone_nonsecure" + - path: "lib/EFR32MG22/IAR/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_iar" + - "device_family_efr32mg22" + - "trustzone_nonsecure" +#MGM22 - path: "lib/EFR32MG22/GCC/libbtmesh_crypto_key_cache.a" condition: - "toolchain_gcc" - "device_family_mgm22" + unless: + - "trustzone_nonsecure" - path: "lib/EFR32MG22/IAR/libbtmesh_crypto_key_cache.a" condition: - "toolchain_iar" - "device_family_mgm22" + unless: + - "trustzone_nonsecure" + - path: "lib/EFR32MG22/GCC/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_gcc" + - "device_family_mgm22" + - "trustzone_nonsecure" + - path: "lib/EFR32MG22/IAR/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_iar" + - "device_family_mgm22" + - "trustzone_nonsecure" #MGM24 - path: "lib/EFR32MG24/GCC/libbtmesh_crypto_key_cache.a" condition: - "toolchain_gcc" - "device_family_mgm24" + unless: + - "trustzone_nonsecure" - path: "lib/EFR32MG24/IAR/libbtmesh_crypto_key_cache.a" condition: - "toolchain_iar" - "device_family_mgm24" + unless: + - "trustzone_nonsecure" + - path: "lib/EFR32MG24/GCC/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_gcc" + - "device_family_mgm24" + - "trustzone_nonsecure" + - path: "lib/EFR32MG24/IAR/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_iar" + - "device_family_mgm24" + - "trustzone_nonsecure" #BGM24 - path: "lib/EFR32BG24/GCC/libbtmesh_crypto_key_cache.a" condition: - "toolchain_gcc" - "device_family_bgm24" + unless: + - "trustzone_nonsecure" - path: "lib/EFR32BG24/IAR/libbtmesh_crypto_key_cache.a" condition: - "toolchain_iar" - "device_family_bgm24" + unless: + - "trustzone_nonsecure" + - path: "lib/EFR32BG24/GCC/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_gcc" + - "device_family_bgm24" + - "trustzone_nonsecure" + - path: "lib/EFR32BG24/IAR/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_iar" + - "device_family_bgm24" + - "trustzone_nonsecure" #EFR32BG24 - path: "lib/EFR32BG24/GCC/libbtmesh_crypto_key_cache.a" condition: - "toolchain_gcc" - "device_family_efr32bg24" + unless: + - "trustzone_nonsecure" - path: "lib/EFR32BG24/IAR/libbtmesh_crypto_key_cache.a" condition: - "toolchain_iar" - "device_family_efr32bg24" + unless: + - "trustzone_nonsecure" + - path: "lib/EFR32BG24/GCC/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_gcc" + - "device_family_efr32bg24" + - "trustzone_nonsecure" + - path: "lib/EFR32BG24/IAR/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_iar" + - "device_family_efr32bg24" + - "trustzone_nonsecure" #EFR32MG24 - path: "lib/EFR32MG24/GCC/libbtmesh_crypto_key_cache.a" condition: - "toolchain_gcc" - "device_family_efr32mg24" + unless: + - "trustzone_nonsecure" - path: "lib/EFR32MG24/IAR/libbtmesh_crypto_key_cache.a" condition: - "toolchain_iar" - "device_family_efr32mg24" + unless: + - "trustzone_nonsecure" + - path: "lib/EFR32MG24/GCC/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_gcc" + - "device_family_efr32mg24" + - "trustzone_nonsecure" + - path: "lib/EFR32MG24/IAR/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_iar" + - "device_family_efr32mg24" + - "trustzone_nonsecure" #EFR32MG27 - path: "lib/EFR32MG27/GCC/libbtmesh_crypto_key_cache.a" condition: - "toolchain_gcc" - "device_family_efr32mg27" + unless: + - "trustzone_nonsecure" - path: "lib/EFR32MG27/IAR/libbtmesh_crypto_key_cache.a" condition: - "toolchain_iar" - "device_family_efr32mg27" + unless: + - "trustzone_nonsecure" + - path: "lib/EFR32MG27/GCC/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_gcc" + - "device_family_efr32mg27" + - "trustzone_nonsecure" + - path: "lib/EFR32MG27/IAR/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_iar" + - "device_family_efr32mg27" + - "trustzone_nonsecure" #EFR32BG27 - path: "lib/EFR32BG27/GCC/libbtmesh_crypto_key_cache.a" condition: - "toolchain_gcc" - "device_family_efr32bg27" + unless: + - "trustzone_nonsecure" - path: "lib/EFR32BG27/IAR/libbtmesh_crypto_key_cache.a" condition: - "toolchain_iar" - "device_family_efr32bg27" + unless: + - "trustzone_nonsecure" + - path: "lib/EFR32BG27/GCC/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_gcc" + - "device_family_efr32bg27" + - "trustzone_nonsecure" + - path: "lib/EFR32BG27/IAR/libbtmesh_crypto_key_cache_dummy.a" + condition: + - "toolchain_iar" + - "device_family_efr32bg27" + - "trustzone_nonsecure" provides: - name: "btmesh_feature_crypto_key_cache" diff --git a/protocol/bluetooth/component/btmesh_feature_crypto_key_cache_dummy.slcc b/protocol/bluetooth/component/btmesh_feature_crypto_key_cache_dummy.slcc deleted file mode 100644 index caa8ad5196..0000000000 --- a/protocol/bluetooth/component/btmesh_feature_crypto_key_cache_dummy.slcc +++ /dev/null @@ -1,136 +0,0 @@ -id: "btmesh_feature_crypto_key_cache_dummy" -label: "Dummy RAM cache for cryptographic keys" -package: "Btmesh" -description: "Dummy (nonfunctional) RAM cache that provides no performance improvement." -category: "Bluetooth Mesh" -quality: "production" -root_path: "protocol/bluetooth" -library: -#EFR32BG21 - - path: "lib/EFR32BG21/GCC/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_gcc" - - "device_family_efr32bg21" - - path: "lib/EFR32BG21/IAR/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_iar" - - "device_family_efr32bg21" -#BGM21 - - path: "lib/EFR32BG21/GCC/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_gcc" - - "device_family_bgm21" - - path: "lib/EFR32BG21/IAR/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_iar" - - "device_family_bgm21" -#EFR32MG21 - - path: "lib/EFR32MG21/GCC/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_gcc" - - "device_family_efr32mg21" - - path: "lib/EFR32MG21/IAR/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_iar" - - "device_family_efr32mg21" -#MGM21 - - path: "lib/EFR32MG21/GCC/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_gcc" - - "device_family_mgm21" - - path: "lib/EFR32MG21/IAR/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_iar" - - "device_family_mgm21" -#EFR32BG22 - - path: "lib/EFR32BG22/GCC/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_gcc" - - "device_family_efr32bg22" - - path: "lib/EFR32BG22/IAR/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_iar" - - "device_family_efr32bg22" -#BGM22 - - path: "lib/EFR32BG22/GCC/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_gcc" - - "device_family_bgm22" - - path: "lib/EFR32BG22/IAR/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_iar" - - "device_family_bgm22" -#EFR32MG22 - - path: "lib/EFR32MG22/GCC/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_gcc" - - "device_family_efr32mg22" - - path: "lib/EFR32MG22/IAR/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_iar" - - "device_family_efr32mg22" -#EFR32MG22 - - path: "lib/EFR32MG22/GCC/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_gcc" - - "device_family_mgm22" - - path: "lib/EFR32MG22/IAR/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_iar" - - "device_family_mgm22" -#MGM24 - - path: "lib/EFR32MG24/GCC/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_gcc" - - "device_family_mgm24" - - path: "lib/EFR32MG24/IAR/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_iar" - - "device_family_mgm24" -#BGM24 - - path: "lib/EFR32BG24/GCC/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_gcc" - - "device_family_bgm24" - - path: "lib/EFR32BG24/IAR/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_iar" - - "device_family_bgm24" -#EFR32BG24 - - path: "lib/EFR32BG24/GCC/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_gcc" - - "device_family_efr32bg24" - - path: "lib/EFR32BG24/IAR/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_iar" - - "device_family_efr32bg24" -#EFR32MG24 - - path: "lib/EFR32MG24/GCC/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_gcc" - - "device_family_efr32mg24" - - path: "lib/EFR32MG24/IAR/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_iar" - - "device_family_efr32mg24" -#EFR32MG27 - - path: "lib/EFR32MG27/GCC/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_gcc" - - "device_family_efr32mg27" - - path: "lib/EFR32MG27/IAR/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_iar" - - "device_family_efr32mg27" -#EFR32BG27 - - path: "lib/EFR32BG27/GCC/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_gcc" - - "device_family_efr32bg27" - - path: "lib/EFR32BG27/IAR/libbtmesh_crypto_key_cache_dummy.a" - condition: - - "toolchain_iar" - - "device_family_efr32bg27" -provides: - - name: "btmesh_feature_crypto_key_cache_dummy" diff --git a/protocol/bluetooth/config/sl_btmesh_config.h b/protocol/bluetooth/config/sl_btmesh_config.h index d7262202a0..69fced17e0 100644 --- a/protocol/bluetooth/config/sl_btmesh_config.h +++ b/protocol/bluetooth/config/sl_btmesh_config.h @@ -76,7 +76,7 @@ // Maximum number of provisioned devices allowed // Default: 0 -// Define the number of provisioned devices the application needs. Only applicable for provisioner +// Define the number of provisioned devices the application needs. Only applicable for provisioner. Please note that provisiner reserves one entry for its own data #define SL_BTMESH_CONFIG_MAX_PROVISIONED_DEVICES (0) // Maximum number of Application Keys allowed for each Provisioned Device diff --git a/protocol/bluetooth/inc/sl_bt_api.h b/protocol/bluetooth/inc/sl_bt_api.h index 7525d41580..928bc9effb 100644 --- a/protocol/bluetooth/inc/sl_bt_api.h +++ b/protocol/bluetooth/inc/sl_bt_api.h @@ -8836,10 +8836,20 @@ typedef enum * * Configure coexistence options at runtime. * - * @param[in] mask Enum @ref sl_bt_coex_option_t. Mask defines which coexistence - * options are changed. - * @param[in] options Enum @ref sl_bt_coex_option_t. Value of options to be - * changed. This parameter is used together with the mask parameter. + * @param[in] mask Bitmask of following coexistence options to change + * - @ref sl_bt_coex_option_enable : (0x100) Enable coexistence + * feature + * - @ref sl_bt_coex_option_tx_abort : (0x400) Abort transmission if + * grant is denied + * - @ref sl_bt_coex_option_high_priority : (0x800) Enable priority + * signal + * @param[in] options Bitmask of following coexistence option values to set + * - @ref sl_bt_coex_option_enable : (0x100) Enable coexistence + * feature + * - @ref sl_bt_coex_option_tx_abort : (0x400) Abort transmission if + * grant is denied + * - @ref sl_bt_coex_option_high_priority : (0x800) Enable priority + * signal * * @return SL_STATUS_OK if successful. Error code otherwise. * diff --git a/protocol/bluetooth/inc/sl_bt_version.h b/protocol/bluetooth/inc/sl_bt_version.h index d7d9e2861c..bc5ed10dfe 100644 --- a/protocol/bluetooth/inc/sl_bt_version.h +++ b/protocol/bluetooth/inc/sl_bt_version.h @@ -18,9 +18,9 @@ #define SL_BT_VERSION_H #define BG_VERSION_MAJOR 4 -#define BG_VERSION_MINOR 0 +#define BG_VERSION_MINOR 1 #define BG_VERSION_PATCH 0 -#define BG_VERSION_BUILD 191 -#define BG_VERSION_HASH {0x59,0xff,0x57,0xcf,0x18,0x84,0xff,0x85,0xba,0xce,0x2e,0x8c,0x3d,0x3d,0x42,0x83,0x2b,0xe9,0xe9,0xa1} +#define BG_VERSION_BUILD 273 +#define BG_VERSION_HASH {0x0e,0x6a,0xc3,0xfb,0xc0,0xe1,0x78,0xe1,0xd6,0x4c,0xdd,0x73,0x16,0x0a,0x47,0xde,0xe3,0xd9,0x3c,0xed} #endif diff --git a/protocol/bluetooth/lib/EFR32BG12P/GCC/binapploader.o b/protocol/bluetooth/lib/EFR32BG12P/GCC/binapploader.o index 91bc7d3bed..b099cb4c14 100644 --- a/protocol/bluetooth/lib/EFR32BG12P/GCC/binapploader.o +++ b/protocol/bluetooth/lib/EFR32BG12P/GCC/binapploader.o @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0a24a310a9e6ea0b02063f5c7f29ea5a89d7e22c022033b5e3e48421cf9d3b0a +oid sha256:e316e84ded7c4c5c0ce9641cea84185004ff1cf8849866c9fbed90250f814985 size 47652 diff --git a/protocol/bluetooth/lib/EFR32BG12P/GCC/binapploader_nvm3.o b/protocol/bluetooth/lib/EFR32BG12P/GCC/binapploader_nvm3.o index 9e81331cbe..681b7540a1 100644 --- a/protocol/bluetooth/lib/EFR32BG12P/GCC/binapploader_nvm3.o +++ b/protocol/bluetooth/lib/EFR32BG12P/GCC/binapploader_nvm3.o @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8ebd280b6f7e4e458c272438c77566d73b28be73ca474224087125d114f80856 +oid sha256:efe9aba206f09f630b67cd6a08168b4bf744455f21a75a6ae3fa4f2b3e57762e size 53796 diff --git a/protocol/bluetooth/lib/EFR32BG12P/GCC/libbluetooth.a b/protocol/bluetooth/lib/EFR32BG12P/GCC/libbluetooth.a index 63774c2956..5580cab2ce 100644 --- a/protocol/bluetooth/lib/EFR32BG12P/GCC/libbluetooth.a +++ b/protocol/bluetooth/lib/EFR32BG12P/GCC/libbluetooth.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f263cc7a21f9c557249438725fef638c8dad416a04313893e004d0d9239c4e0a -size 2274506 +oid sha256:a8732f1fddaaf2d96ee32b141725079c0c997294ab7dbcd51c42a2351273e4ec +size 2404554 diff --git a/protocol/bluetooth/lib/EFR32BG12P/GCC/libbluetooth_mesh.a b/protocol/bluetooth/lib/EFR32BG12P/GCC/libbluetooth_mesh.a index 2b188d4ea7..ce6fd68251 100644 --- a/protocol/bluetooth/lib/EFR32BG12P/GCC/libbluetooth_mesh.a +++ b/protocol/bluetooth/lib/EFR32BG12P/GCC/libbluetooth_mesh.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:64c2a9fc59ab2d5af1f4cf13c0d0d7b05b0b20391366d57e28dc23a5549d1c11 -size 1547236 +oid sha256:9f91bfdb8d46a4487c8e00589eeeee4b855969643a13e7c93295aa3ed635cf2d +size 1547632 diff --git a/protocol/bluetooth/lib/EFR32BG12P/GCC/libpsstore.a b/protocol/bluetooth/lib/EFR32BG12P/GCC/libpsstore.a index be06655ba0..40db28d998 100644 --- a/protocol/bluetooth/lib/EFR32BG12P/GCC/libpsstore.a +++ b/protocol/bluetooth/lib/EFR32BG12P/GCC/libpsstore.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9071fe2d3d0f18c82e60142c97ed7b9442e6e4960b75a9e484ff5a07e13da564 +oid sha256:d20ebeef9b1edd9f578d4ec2f28c384f5adc827c3d65ce0a870bdcb978ebb8bc size 12822 diff --git a/protocol/bluetooth/lib/EFR32BG12P/IAR/binapploader.o b/protocol/bluetooth/lib/EFR32BG12P/IAR/binapploader.o index 91bc7d3bed..b099cb4c14 100644 --- a/protocol/bluetooth/lib/EFR32BG12P/IAR/binapploader.o +++ b/protocol/bluetooth/lib/EFR32BG12P/IAR/binapploader.o @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0a24a310a9e6ea0b02063f5c7f29ea5a89d7e22c022033b5e3e48421cf9d3b0a +oid sha256:e316e84ded7c4c5c0ce9641cea84185004ff1cf8849866c9fbed90250f814985 size 47652 diff --git a/protocol/bluetooth/lib/EFR32BG12P/IAR/binapploader_nvm3.o b/protocol/bluetooth/lib/EFR32BG12P/IAR/binapploader_nvm3.o index 9e81331cbe..681b7540a1 100644 --- a/protocol/bluetooth/lib/EFR32BG12P/IAR/binapploader_nvm3.o +++ b/protocol/bluetooth/lib/EFR32BG12P/IAR/binapploader_nvm3.o @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8ebd280b6f7e4e458c272438c77566d73b28be73ca474224087125d114f80856 +oid sha256:efe9aba206f09f630b67cd6a08168b4bf744455f21a75a6ae3fa4f2b3e57762e size 53796 diff --git a/protocol/bluetooth/lib/EFR32BG12P/IAR/libbluetooth.a b/protocol/bluetooth/lib/EFR32BG12P/IAR/libbluetooth.a index afece2fc98..4962052128 100644 --- a/protocol/bluetooth/lib/EFR32BG12P/IAR/libbluetooth.a +++ b/protocol/bluetooth/lib/EFR32BG12P/IAR/libbluetooth.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:eb098d88660a84400914048ece7390010f1db962aeca09ccbade47d105878309 -size 5759250 +oid sha256:e1e825e271b6c2619f9efea97747742d8599db392bf47e8b4eda25f75103e0e9 +size 5973636 diff --git a/protocol/bluetooth/lib/EFR32BG12P/IAR/libbluetooth_mesh.a b/protocol/bluetooth/lib/EFR32BG12P/IAR/libbluetooth_mesh.a index 6ec842f221..2f763456b0 100644 --- a/protocol/bluetooth/lib/EFR32BG12P/IAR/libbluetooth_mesh.a +++ b/protocol/bluetooth/lib/EFR32BG12P/IAR/libbluetooth_mesh.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0b16a3d7c73c1121a0aae84f86e56eb7173f99e60643d415e812833b8b452cfc -size 4359560 +oid sha256:b16e2415703b4235090f1e486d2c75f1152cbddd4fb9af258c2640a8527b01c7 +size 4334924 diff --git a/protocol/bluetooth/lib/EFR32BG12P/IAR/libpsstore.a b/protocol/bluetooth/lib/EFR32BG12P/IAR/libpsstore.a index 75300f9ca7..f9a724e428 100644 --- a/protocol/bluetooth/lib/EFR32BG12P/IAR/libpsstore.a +++ b/protocol/bluetooth/lib/EFR32BG12P/IAR/libpsstore.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e282cecbbb3572a3c2c6e94534092220324c4bc2aadcf9fdb94378634cc1ef44 -size 30780 +oid sha256:7e7f3b220dc9c8d5b7c2fca5ce0f8cb9f660dac0ab15c64dca5ba41138da95ad +size 30714 diff --git a/protocol/bluetooth/lib/EFR32BG13P/GCC/binapploader.o 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a/protocol/bluetooth/lib/EFR32BG13P/GCC/libbluetooth.a b/protocol/bluetooth/lib/EFR32BG13P/GCC/libbluetooth.a index 53ed06f434..7ed86d17d5 100644 --- a/protocol/bluetooth/lib/EFR32BG13P/GCC/libbluetooth.a +++ b/protocol/bluetooth/lib/EFR32BG13P/GCC/libbluetooth.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:90f76f74bdcc3d182d907a690ea9ab26d45049af428cbb2ec71fbf69ad9d2fa7 -size 2274626 +oid sha256:e7289672ede34b45d424c4b9a4ef821d94beff84ef825f2cb466f337dc3d35d8 +size 2404674 diff --git a/protocol/bluetooth/lib/EFR32BG13P/GCC/libbluetooth_mesh.a b/protocol/bluetooth/lib/EFR32BG13P/GCC/libbluetooth_mesh.a index d45292a140..094b3e47ed 100644 --- a/protocol/bluetooth/lib/EFR32BG13P/GCC/libbluetooth_mesh.a +++ b/protocol/bluetooth/lib/EFR32BG13P/GCC/libbluetooth_mesh.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:428130fa4ce2638bb78808d7d718c0303453ae156847219d0826a6cd980067aa -size 1547236 +oid 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a/protocol/bluetooth/lib/EFR32MG22/IAR/libbtmesh_crypto_key_cache.a +++ b/protocol/bluetooth/lib/EFR32MG22/IAR/libbtmesh_crypto_key_cache.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0927dea21347878207f014489865fee821fe90dec18f227f0d355b2ab022da9e -size 11330 +oid sha256:6d0d829ab05cd9e18e7a0ed70188a6d6033c0695b637f3815c3a1d248ece5df3 +size 11298 diff --git a/protocol/bluetooth/lib/EFR32MG22/IAR/libbtmesh_crypto_key_cache_dummy.a b/protocol/bluetooth/lib/EFR32MG22/IAR/libbtmesh_crypto_key_cache_dummy.a index 62bc32a442..2c2261d62f 100644 --- a/protocol/bluetooth/lib/EFR32MG22/IAR/libbtmesh_crypto_key_cache_dummy.a +++ b/protocol/bluetooth/lib/EFR32MG22/IAR/libbtmesh_crypto_key_cache_dummy.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:691c338daec09ef9d21f927741043de3d4f9d020d0b525e20661400a35b08f0e -size 6602 +oid sha256:074435a9852f8a96c820ec09a710dda77277174ca45cee1af2faa18058bc2d98 +size 6570 diff --git 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+size 458568 diff --git a/protocol/bluetooth/lib/EFR32MG27/GCC/libbluetooth.a b/protocol/bluetooth/lib/EFR32MG27/GCC/libbluetooth.a index c90cc9acea..59dac2fa06 100644 --- a/protocol/bluetooth/lib/EFR32MG27/GCC/libbluetooth.a +++ b/protocol/bluetooth/lib/EFR32MG27/GCC/libbluetooth.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:dfb409025649079a07842b00347a0d1afb188d5d3dd6da061ddfdf3b842f82ec -size 2293522 +oid sha256:e7b93129892fa0c9e39d579bdc0712a22690c1ebb4ea50586119bbf4964ff731 +size 2424590 diff --git a/protocol/bluetooth/lib/EFR32MG27/GCC/libbluetooth_mesh.a b/protocol/bluetooth/lib/EFR32MG27/GCC/libbluetooth_mesh.a index 335dc50bdc..b0880bd03a 100644 --- a/protocol/bluetooth/lib/EFR32MG27/GCC/libbluetooth_mesh.a +++ b/protocol/bluetooth/lib/EFR32MG27/GCC/libbluetooth_mesh.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5d412d90e2bffdd5fe6b8639cd20e927c09921e9ace46d784f9edffeb5f5fe09 -size 1561092 +oid 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+1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:eac3474a06a8e8f79645b0439a83d10f60b8318411694773ea750940841fdb2b -size 5832648 +oid sha256:99e8b6c7dddb81f72a0775e1a047491df3cebc7b699a29a9b1114fa5542f4484 +size 6050294 diff --git a/protocol/bluetooth/lib/EFR32MG27/IAR/libbluetooth_mesh.a b/protocol/bluetooth/lib/EFR32MG27/IAR/libbluetooth_mesh.a index 4eb327d6eb..2e89295c2c 100644 --- a/protocol/bluetooth/lib/EFR32MG27/IAR/libbluetooth_mesh.a +++ b/protocol/bluetooth/lib/EFR32MG27/IAR/libbluetooth_mesh.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:cc8e03ded35ffe192cc3669f6cacb33f3cec64c957f32e354f91395c2e356557 -size 4394304 +oid sha256:e8266cb6a67353c092e8c17f0b82fa58c08c723f5f51731c526c1acdfa6b6537 +size 4369162 diff --git a/protocol/bluetooth/lib/EFR32MG27/IAR/libbtmesh_crypto_key_cache.a b/protocol/bluetooth/lib/EFR32MG27/IAR/libbtmesh_crypto_key_cache.a index 1635fb43a3..d1b1b45a78 100644 --- a/protocol/bluetooth/lib/EFR32MG27/IAR/libbtmesh_crypto_key_cache.a +++ b/protocol/bluetooth/lib/EFR32MG27/IAR/libbtmesh_crypto_key_cache.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4f8feece98bf274bb4ff722d7332d089080d8943d68a871d8aa413755f8c8882 -size 11330 +oid sha256:0617d7aa4a284a3dd2900e2eececa0bf639528eba62ef6641b673dd824042c4d +size 11298 diff --git a/protocol/bluetooth/lib/EFR32MG27/IAR/libbtmesh_crypto_key_cache_dummy.a b/protocol/bluetooth/lib/EFR32MG27/IAR/libbtmesh_crypto_key_cache_dummy.a index 51f1fa0191..7dfebae237 100644 --- a/protocol/bluetooth/lib/EFR32MG27/IAR/libbtmesh_crypto_key_cache_dummy.a +++ b/protocol/bluetooth/lib/EFR32MG27/IAR/libbtmesh_crypto_key_cache_dummy.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:01abef203bd68ef1550ffce3e78e29fadbb8ee73ef76781be840b988f84da9cd -size 6602 +oid sha256:67f9959073ae68cb9f73dd6bc886decbb0f9d4fc9b82b8af07ee451552512d0c +size 6570 diff --git a/protocol/bluetooth/src/sl_bt_ncp_host_api.c b/protocol/bluetooth/src/sl_bt_ncp_host_api.c index b06fe8695c..63adcde757 100644 --- a/protocol/bluetooth/src/sl_bt_ncp_host_api.c +++ b/protocol/bluetooth/src/sl_bt_ncp_host_api.c @@ -2,7 +2,7 @@ * @brief SL_BT_API commands for NCP host ******************************************************************************* * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this @@ -53,6 +53,10 @@ sl_status_t sl_bt_dfu_flash_upload(size_t data_len, const uint8_t* data) { struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + if ((1+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_dfu_flash_upload.data.len=data_len; memcpy(cmd->data.cmd_dfu_flash_upload.data.data,data,data_len); @@ -179,6 +183,10 @@ sl_status_t sl_bt_system_linklayer_configure(uint8_t key, struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; cmd->data.cmd_system_linklayer_configure.key=key; + if ((2+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_system_linklayer_configure.data.len=data_len; memcpy(cmd->data.cmd_system_linklayer_configure.data.data,data,data_len); @@ -294,6 +302,10 @@ sl_status_t sl_bt_system_data_buffer_write(size_t data_len, struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + if ((1+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_system_data_buffer_write.data.len=data_len; memcpy(cmd->data.cmd_system_data_buffer_write.data.data,data,data_len); @@ -385,6 +397,10 @@ sl_status_t sl_bt_gap_set_data_channel_classification(size_t channel_map_len, struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + if ((1+channel_map_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_gap_set_data_channel_classification.channel_map.len=channel_map_len; memcpy(cmd->data.cmd_gap_set_data_channel_classification.channel_map.data,channel_map,channel_map_len); @@ -647,6 +663,10 @@ SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_set_data(uint8_t advertising_se cmd->data.cmd_advertiser_set_data.advertising_set=advertising_set; cmd->data.cmd_advertiser_set_data.packet_type=packet_type; + if ((3+adv_data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_advertiser_set_data.adv_data.len=adv_data_len; memcpy(cmd->data.cmd_advertiser_set_data.adv_data.data,adv_data,adv_data_len); @@ -740,6 +760,10 @@ sl_status_t sl_bt_legacy_advertiser_set_data(uint8_t advertising_set, cmd->data.cmd_legacy_advertiser_set_data.advertising_set=advertising_set; cmd->data.cmd_legacy_advertiser_set_data.type=type; + if ((3+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_legacy_advertiser_set_data.data.len=data_len; memcpy(cmd->data.cmd_legacy_advertiser_set_data.data.data,data,data_len); @@ -833,6 +857,10 @@ sl_status_t sl_bt_extended_advertiser_set_data(uint8_t advertising_set, struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; cmd->data.cmd_extended_advertiser_set_data.advertising_set=advertising_set; + if ((2+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_extended_advertiser_set_data.data.len=data_len; memcpy(cmd->data.cmd_extended_advertiser_set_data.data.data,data,data_len); @@ -926,6 +954,10 @@ sl_status_t sl_bt_periodic_advertiser_set_data(uint8_t advertising_set, struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; cmd->data.cmd_periodic_advertiser_set_data.advertising_set=advertising_set; + if ((2+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_periodic_advertiser_set_data.data.len=data_len; memcpy(cmd->data.cmd_periodic_advertiser_set_data.data.data,data,data_len); @@ -1551,6 +1583,10 @@ sl_status_t sl_bt_gatt_discover_primary_services_by_uuid(uint8_t connection, struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; cmd->data.cmd_gatt_discover_primary_services_by_uuid.connection=connection; + if ((2+uuid_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_gatt_discover_primary_services_by_uuid.uuid.len=uuid_len; memcpy(cmd->data.cmd_gatt_discover_primary_services_by_uuid.uuid.data,uuid,uuid_len); @@ -1606,6 +1642,10 @@ sl_status_t sl_bt_gatt_discover_characteristics_by_uuid(uint8_t connection, cmd->data.cmd_gatt_discover_characteristics_by_uuid.connection=connection; cmd->data.cmd_gatt_discover_characteristics_by_uuid.service=service; + if ((6+uuid_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_gatt_discover_characteristics_by_uuid.uuid.len=uuid_len; memcpy(cmd->data.cmd_gatt_discover_characteristics_by_uuid.uuid.data,uuid,uuid_len); @@ -1714,6 +1754,10 @@ sl_status_t sl_bt_gatt_read_multiple_characteristic_values(uint8_t connection, struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; cmd->data.cmd_gatt_read_multiple_characteristic_values.connection=connection; + if ((2+characteristic_list_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_gatt_read_multiple_characteristic_values.characteristic_list.len=characteristic_list_len; memcpy(cmd->data.cmd_gatt_read_multiple_characteristic_values.characteristic_list.data,characteristic_list,characteristic_list_len); @@ -1735,6 +1779,10 @@ sl_status_t sl_bt_gatt_read_characteristic_value_by_uuid(uint8_t connection, cmd->data.cmd_gatt_read_characteristic_value_by_uuid.connection=connection; cmd->data.cmd_gatt_read_characteristic_value_by_uuid.service=service; + if ((6+uuid_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_gatt_read_characteristic_value_by_uuid.uuid.len=uuid_len; memcpy(cmd->data.cmd_gatt_read_characteristic_value_by_uuid.uuid.data,uuid,uuid_len); @@ -1756,6 +1804,10 @@ sl_status_t sl_bt_gatt_write_characteristic_value(uint8_t connection, cmd->data.cmd_gatt_write_characteristic_value.connection=connection; cmd->data.cmd_gatt_write_characteristic_value.characteristic=characteristic; + if ((4+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_gatt_write_characteristic_value.value.len=value_len; memcpy(cmd->data.cmd_gatt_write_characteristic_value.value.data,value,value_len); @@ -1778,6 +1830,10 @@ sl_status_t sl_bt_gatt_write_characteristic_value_without_response(uint8_t conne cmd->data.cmd_gatt_write_characteristic_value_without_response.connection=connection; cmd->data.cmd_gatt_write_characteristic_value_without_response.characteristic=characteristic; + if ((4+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_gatt_write_characteristic_value_without_response.value.len=value_len; memcpy(cmd->data.cmd_gatt_write_characteristic_value_without_response.value.data,value,value_len); @@ -1803,6 +1859,10 @@ sl_status_t sl_bt_gatt_prepare_characteristic_value_write(uint8_t connection, cmd->data.cmd_gatt_prepare_characteristic_value_write.connection=connection; cmd->data.cmd_gatt_prepare_characteristic_value_write.characteristic=characteristic; cmd->data.cmd_gatt_prepare_characteristic_value_write.offset=offset; + if ((6+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_gatt_prepare_characteristic_value_write.value.len=value_len; memcpy(cmd->data.cmd_gatt_prepare_characteristic_value_write.value.data,value,value_len); @@ -1828,6 +1888,10 @@ sl_status_t sl_bt_gatt_prepare_characteristic_value_reliable_write(uint8_t conne cmd->data.cmd_gatt_prepare_characteristic_value_reliable_write.connection=connection; cmd->data.cmd_gatt_prepare_characteristic_value_reliable_write.characteristic=characteristic; cmd->data.cmd_gatt_prepare_characteristic_value_reliable_write.offset=offset; + if ((6+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_gatt_prepare_characteristic_value_reliable_write.value.len=value_len; memcpy(cmd->data.cmd_gatt_prepare_characteristic_value_reliable_write.value.data,value,value_len); @@ -1884,6 +1948,10 @@ sl_status_t sl_bt_gatt_write_descriptor_value(uint8_t connection, cmd->data.cmd_gatt_write_descriptor_value.connection=connection; cmd->data.cmd_gatt_write_descriptor_value.descriptor=descriptor; + if ((4+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_gatt_write_descriptor_value.value.len=value_len; memcpy(cmd->data.cmd_gatt_write_descriptor_value.value.data,value,value_len); @@ -1923,6 +1991,10 @@ sl_status_t sl_bt_gattdb_add_service(uint16_t session, cmd->data.cmd_gattdb_add_service.session=session; cmd->data.cmd_gattdb_add_service.type=type; cmd->data.cmd_gattdb_add_service.property=property; + if ((5+uuid_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_gattdb_add_service.uuid.len=uuid_len; memcpy(cmd->data.cmd_gattdb_add_service.uuid.data,uuid,uuid_len); @@ -2012,6 +2084,10 @@ sl_status_t sl_bt_gattdb_add_uuid16_characteristic(uint16_t session, cmd->data.cmd_gattdb_add_uuid16_characteristic.uuid=uuid; cmd->data.cmd_gattdb_add_uuid16_characteristic.value_type=value_type; cmd->data.cmd_gattdb_add_uuid16_characteristic.maxlen=maxlen; + if ((16+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_gattdb_add_uuid16_characteristic.value.len=value_len; memcpy(cmd->data.cmd_gattdb_add_uuid16_characteristic.value.data,value,value_len); @@ -2047,6 +2123,10 @@ sl_status_t sl_bt_gattdb_add_uuid128_characteristic(uint16_t session, cmd->data.cmd_gattdb_add_uuid128_characteristic.uuid=uuid; cmd->data.cmd_gattdb_add_uuid128_characteristic.value_type=value_type; cmd->data.cmd_gattdb_add_uuid128_characteristic.maxlen=maxlen; + if ((30+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_gattdb_add_uuid128_characteristic.value.len=value_len; memcpy(cmd->data.cmd_gattdb_add_uuid128_characteristic.value.data,value,value_len); @@ -2097,6 +2177,10 @@ sl_status_t sl_bt_gattdb_add_uuid16_descriptor(uint16_t session, cmd->data.cmd_gattdb_add_uuid16_descriptor.uuid=uuid; cmd->data.cmd_gattdb_add_uuid16_descriptor.value_type=value_type; cmd->data.cmd_gattdb_add_uuid16_descriptor.maxlen=maxlen; + if ((15+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_gattdb_add_uuid16_descriptor.value.len=value_len; memcpy(cmd->data.cmd_gattdb_add_uuid16_descriptor.value.data,value,value_len); @@ -2130,6 +2214,10 @@ sl_status_t sl_bt_gattdb_add_uuid128_descriptor(uint16_t session, cmd->data.cmd_gattdb_add_uuid128_descriptor.uuid=uuid; cmd->data.cmd_gattdb_add_uuid128_descriptor.value_type=value_type; cmd->data.cmd_gattdb_add_uuid128_descriptor.maxlen=maxlen; + if ((29+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_gattdb_add_uuid128_descriptor.value.len=value_len; memcpy(cmd->data.cmd_gattdb_add_uuid128_descriptor.value.data,value,value_len); @@ -2297,6 +2385,10 @@ sl_status_t sl_bt_gatt_server_find_attribute(uint16_t start, struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; cmd->data.cmd_gatt_server_find_attribute.start=start; + if ((3+type_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_gatt_server_find_attribute.type.len=type_len; memcpy(cmd->data.cmd_gatt_server_find_attribute.type.data,type,type_len); @@ -2365,6 +2457,10 @@ sl_status_t sl_bt_gatt_server_write_attribute_value(uint16_t attribute, cmd->data.cmd_gatt_server_write_attribute_value.attribute=attribute; cmd->data.cmd_gatt_server_write_attribute_value.offset=offset; + if ((5+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_gatt_server_write_attribute_value.value.len=value_len; memcpy(cmd->data.cmd_gatt_server_write_attribute_value.value.data,value,value_len); @@ -2389,6 +2485,10 @@ sl_status_t sl_bt_gatt_server_send_user_read_response(uint8_t connection, cmd->data.cmd_gatt_server_send_user_read_response.connection=connection; cmd->data.cmd_gatt_server_send_user_read_response.characteristic=characteristic; cmd->data.cmd_gatt_server_send_user_read_response.att_errorcode=att_errorcode; + if ((5+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_gatt_server_send_user_read_response.value.len=value_len; memcpy(cmd->data.cmd_gatt_server_send_user_read_response.value.data,value,value_len); @@ -2430,6 +2530,10 @@ sl_status_t sl_bt_gatt_server_send_notification(uint8_t connection, cmd->data.cmd_gatt_server_send_notification.connection=connection; cmd->data.cmd_gatt_server_send_notification.characteristic=characteristic; + if ((4+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_gatt_server_send_notification.value.len=value_len; memcpy(cmd->data.cmd_gatt_server_send_notification.value.data,value,value_len); @@ -2451,6 +2555,10 @@ sl_status_t sl_bt_gatt_server_send_indication(uint8_t connection, cmd->data.cmd_gatt_server_send_indication.connection=connection; cmd->data.cmd_gatt_server_send_indication.characteristic=characteristic; + if ((4+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_gatt_server_send_indication.value.len=value_len; memcpy(cmd->data.cmd_gatt_server_send_indication.value.data,value,value_len); @@ -2470,6 +2578,10 @@ sl_status_t sl_bt_gatt_server_notify_all(uint16_t characteristic, struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; cmd->data.cmd_gatt_server_notify_all.characteristic=characteristic; + if ((3+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_gatt_server_notify_all.value.len=value_len; memcpy(cmd->data.cmd_gatt_server_notify_all.value.data,value,value_len); @@ -2514,6 +2626,10 @@ sl_status_t sl_bt_gatt_server_send_user_prepare_write_response(uint8_t connectio cmd->data.cmd_gatt_server_send_user_prepare_write_response.characteristic=characteristic; cmd->data.cmd_gatt_server_send_user_prepare_write_response.att_errorcode=att_errorcode; cmd->data.cmd_gatt_server_send_user_prepare_write_response.offset=offset; + if ((7+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_gatt_server_send_user_prepare_write_response.value.len=value_len; memcpy(cmd->data.cmd_gatt_server_send_user_prepare_write_response.value.data,value,value_len); @@ -2612,6 +2728,10 @@ sl_status_t sl_bt_nvm_save(uint16_t key, struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; cmd->data.cmd_nvm_save.key=key; + if ((3+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_nvm_save.value.len=value_len; memcpy(cmd->data.cmd_nvm_save.value.data,value,value_len); @@ -3099,6 +3219,10 @@ sl_status_t sl_bt_sm_set_bonding_data(uint8_t connection, cmd->data.cmd_sm_set_bonding_data.connection=connection; cmd->data.cmd_sm_set_bonding_data.type=type; + if ((3+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_sm_set_bonding_data.data.len=data_len; memcpy(cmd->data.cmd_sm_set_bonding_data.data.data,data,data_len); @@ -3115,6 +3239,10 @@ sl_status_t sl_bt_ota_set_device_name(size_t name_len, const uint8_t* name) { struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + if ((1+name_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_ota_set_device_name.name.len=name_len; memcpy(cmd->data.cmd_ota_set_device_name.name.data,name,name_len); @@ -3134,6 +3262,10 @@ sl_status_t sl_bt_ota_set_advertising_data(uint8_t packet_type, struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; cmd->data.cmd_ota_set_advertising_data.packet_type=packet_type; + if ((2+adv_data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_ota_set_advertising_data.adv_data.len=adv_data_len; memcpy(cmd->data.cmd_ota_set_advertising_data.adv_data.data,adv_data,adv_data_len); @@ -3310,6 +3442,10 @@ sl_status_t sl_bt_l2cap_channel_send_data(uint8_t connection, cmd->data.cmd_l2cap_channel_send_data.connection=connection; cmd->data.cmd_l2cap_channel_send_data.cid=cid; + if ((4+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_l2cap_channel_send_data.data.len=data_len; memcpy(cmd->data.cmd_l2cap_channel_send_data.data.data,data,data_len); @@ -3366,6 +3502,10 @@ sl_status_t sl_bt_cte_transmitter_set_dtm_parameters(uint8_t cte_length, cmd->data.cmd_cte_transmitter_set_dtm_parameters.cte_length=cte_length; cmd->data.cmd_cte_transmitter_set_dtm_parameters.cte_type=cte_type; + if ((3+switching_pattern_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_cte_transmitter_set_dtm_parameters.switching_pattern.len=switching_pattern_len; memcpy(cmd->data.cmd_cte_transmitter_set_dtm_parameters.switching_pattern.data,switching_pattern,switching_pattern_len); @@ -3401,6 +3541,10 @@ sl_status_t sl_bt_cte_transmitter_enable_connection_cte(uint8_t connection, cmd->data.cmd_cte_transmitter_enable_connection_cte.connection=connection; cmd->data.cmd_cte_transmitter_enable_connection_cte.cte_types=cte_types; + if ((3+switching_pattern_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_cte_transmitter_enable_connection_cte.switching_pattern.len=switching_pattern_len; memcpy(cmd->data.cmd_cte_transmitter_enable_connection_cte.switching_pattern.data,switching_pattern,switching_pattern_len); @@ -3441,6 +3585,10 @@ sl_status_t sl_bt_cte_transmitter_enable_connectionless_cte(uint8_t handle, cmd->data.cmd_cte_transmitter_enable_connectionless_cte.cte_length=cte_length; cmd->data.cmd_cte_transmitter_enable_connectionless_cte.cte_type=cte_type; cmd->data.cmd_cte_transmitter_enable_connectionless_cte.cte_count=cte_count; + if ((5+switching_pattern_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_cte_transmitter_enable_connectionless_cte.switching_pattern.len=switching_pattern_len; memcpy(cmd->data.cmd_cte_transmitter_enable_connectionless_cte.switching_pattern.data,switching_pattern,switching_pattern_len); @@ -3481,6 +3629,10 @@ sl_status_t sl_bt_cte_transmitter_enable_silabs_cte(uint8_t handle, cmd->data.cmd_cte_transmitter_enable_silabs_cte.cte_length=cte_length; cmd->data.cmd_cte_transmitter_enable_silabs_cte.cte_type=cte_type; cmd->data.cmd_cte_transmitter_enable_silabs_cte.cte_count=cte_count; + if ((5+switching_pattern_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_cte_transmitter_enable_silabs_cte.switching_pattern.len=switching_pattern_len; memcpy(cmd->data.cmd_cte_transmitter_enable_silabs_cte.switching_pattern.data,switching_pattern,switching_pattern_len); @@ -3519,6 +3671,10 @@ sl_status_t sl_bt_cte_receiver_set_dtm_parameters(uint8_t cte_length, cmd->data.cmd_cte_receiver_set_dtm_parameters.cte_length=cte_length; cmd->data.cmd_cte_receiver_set_dtm_parameters.cte_type=cte_type; cmd->data.cmd_cte_receiver_set_dtm_parameters.slot_durations=slot_durations; + if ((4+switching_pattern_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_cte_receiver_set_dtm_parameters.switching_pattern.len=switching_pattern_len; memcpy(cmd->data.cmd_cte_receiver_set_dtm_parameters.switching_pattern.data,switching_pattern,switching_pattern_len); @@ -3638,6 +3794,10 @@ sl_status_t sl_bt_cte_receiver_enable_connection_cte(uint8_t connection, cmd->data.cmd_cte_receiver_enable_connection_cte.cte_length=cte_length; cmd->data.cmd_cte_receiver_enable_connection_cte.cte_type=cte_type; cmd->data.cmd_cte_receiver_enable_connection_cte.slot_durations=slot_durations; + if ((7+switching_pattern_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_cte_receiver_enable_connection_cte.switching_pattern.len=switching_pattern_len; memcpy(cmd->data.cmd_cte_receiver_enable_connection_cte.switching_pattern.data,switching_pattern,switching_pattern_len); @@ -3676,6 +3836,10 @@ sl_status_t sl_bt_cte_receiver_enable_connectionless_cte(uint16_t sync, cmd->data.cmd_cte_receiver_enable_connectionless_cte.sync=sync; cmd->data.cmd_cte_receiver_enable_connectionless_cte.slot_durations=slot_durations; cmd->data.cmd_cte_receiver_enable_connectionless_cte.cte_count=cte_count; + if ((5+switching_pattern_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_cte_receiver_enable_connectionless_cte.switching_pattern.len=switching_pattern_len; memcpy(cmd->data.cmd_cte_receiver_enable_connectionless_cte.switching_pattern.data,switching_pattern,switching_pattern_len); @@ -3712,6 +3876,10 @@ sl_status_t sl_bt_cte_receiver_enable_silabs_cte(uint8_t slot_durations, cmd->data.cmd_cte_receiver_enable_silabs_cte.slot_durations=slot_durations; cmd->data.cmd_cte_receiver_enable_silabs_cte.cte_count=cte_count; + if ((3+switching_pattern_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_cte_receiver_enable_silabs_cte.switching_pattern.len=switching_pattern_len; memcpy(cmd->data.cmd_cte_receiver_enable_silabs_cte.switching_pattern.data,switching_pattern,switching_pattern_len); @@ -3746,6 +3914,10 @@ sl_status_t sl_bt_user_message_to_target(size_t data_len, struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + if ((1+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_user_message_to_target.data.len=data_len; memcpy(cmd->data.cmd_user_message_to_target.data.data,data,data_len); @@ -3767,6 +3939,10 @@ sl_status_t sl_bt_user_manage_event_filter(size_t data_len, struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + if ((1+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_user_manage_event_filter.data.len=data_len; memcpy(cmd->data.cmd_user_manage_event_filter.data.data,data,data_len); diff --git a/protocol/bluetooth/src/sl_btmesh_ncp_host_api.c b/protocol/bluetooth/src/sl_btmesh_ncp_host_api.c index 12096524cc..d044198b08 100644 --- a/protocol/bluetooth/src/sl_btmesh_ncp_host_api.c +++ b/protocol/bluetooth/src/sl_btmesh_ncp_host_api.c @@ -2,7 +2,7 @@ * @brief SL_BT_API commands for NCP host ******************************************************************************* * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * The licensor of this software is Silicon Laboratories Inc. Your use of this @@ -100,6 +100,10 @@ sl_status_t sl_btmesh_node_send_input_oob_request_response(size_t data_len, struct sl_btmesh_packet *rsp = (struct sl_btmesh_packet *)sl_btmesh_rsp_msg; + if ((1+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_node_send_input_oob_request_response.data.len=data_len; memcpy(cmd->data.cmd_node_send_input_oob_request_response.data.data,data,data_len); @@ -392,6 +396,10 @@ sl_status_t sl_btmesh_node_send_static_oob_request_response(size_t data_len, struct sl_btmesh_packet *rsp = (struct sl_btmesh_packet *)sl_btmesh_rsp_msg; + if ((1+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_node_send_static_oob_request_response.data.len=data_len; memcpy(cmd->data.cmd_node_send_static_oob_request_response.data.data,data,data_len); @@ -807,6 +815,10 @@ sl_status_t sl_btmesh_prov_create_network(uint16_t netkey_index, struct sl_btmesh_packet *rsp = (struct sl_btmesh_packet *)sl_btmesh_rsp_msg; cmd->data.cmd_prov_create_network.netkey_index=netkey_index; + if ((3+key_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_prov_create_network.key.len=key_len; memcpy(cmd->data.cmd_prov_create_network.key.data,key,key_len); @@ -831,6 +843,10 @@ sl_status_t sl_btmesh_prov_create_appkey(uint16_t netkey_index, cmd->data.cmd_prov_create_appkey.netkey_index=netkey_index; cmd->data.cmd_prov_create_appkey.appkey_index=appkey_index; + if ((5+key_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_prov_create_appkey.key.len=key_len; memcpy(cmd->data.cmd_prov_create_appkey.key.data,key,key_len); @@ -854,6 +870,10 @@ sl_status_t sl_btmesh_prov_send_oob_pkey_response(uuid_128 uuid, struct sl_btmesh_packet *rsp = (struct sl_btmesh_packet *)sl_btmesh_rsp_msg; cmd->data.cmd_prov_send_oob_pkey_response.uuid=uuid; + if ((17+pkey_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_prov_send_oob_pkey_response.pkey.len=pkey_len; memcpy(cmd->data.cmd_prov_send_oob_pkey_response.pkey.data,pkey,pkey_len); @@ -873,6 +893,10 @@ sl_status_t sl_btmesh_prov_send_oob_auth_response(uuid_128 uuid, struct sl_btmesh_packet *rsp = (struct sl_btmesh_packet *)sl_btmesh_rsp_msg; cmd->data.cmd_prov_send_oob_auth_response.uuid=uuid; + if ((17+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_prov_send_oob_auth_response.data.len=data_len; memcpy(cmd->data.cmd_prov_send_oob_auth_response.data.data,data,data_len); @@ -921,6 +945,10 @@ sl_status_t sl_btmesh_prov_start_key_refresh(uint16_t netkey_index, cmd->data.cmd_prov_start_key_refresh.netkey_index=netkey_index; cmd->data.cmd_prov_start_key_refresh.num_appkeys=num_appkeys; + if ((4+appkey_indices_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_prov_start_key_refresh.appkey_indices.len=appkey_indices_len; memcpy(cmd->data.cmd_prov_start_key_refresh.appkey_indices.data,appkey_indices,appkey_indices_len); @@ -1194,6 +1222,10 @@ sl_status_t sl_btmesh_prov_start_key_refresh_from_phase(uint8_t phase, cmd->data.cmd_prov_start_key_refresh_from_phase.phase=phase; cmd->data.cmd_prov_start_key_refresh_from_phase.netkey_index=netkey_index; cmd->data.cmd_prov_start_key_refresh_from_phase.num_appkeys=num_appkeys; + if ((5+appkey_indices_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_prov_start_key_refresh_from_phase.appkey_indices.len=appkey_indices_len; memcpy(cmd->data.cmd_prov_start_key_refresh_from_phase.appkey_indices.data,appkey_indices,appkey_indices_len); @@ -1231,6 +1263,10 @@ sl_status_t sl_btmesh_prov_test_identity(uint16_t address, cmd->data.cmd_prov_test_identity.address=address; cmd->data.cmd_prov_test_identity.netkey_index=netkey_index; + if ((5+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_prov_test_identity.data.len=data_len; memcpy(cmd->data.cmd_prov_test_identity.data.data,data,data_len); @@ -1370,6 +1406,10 @@ sl_status_t sl_btmesh_vendor_model_send(uint16_t destination_address, cmd->data.cmd_vendor_model_send.nonrelayed=nonrelayed; cmd->data.cmd_vendor_model_send.opcode=opcode; cmd->data.cmd_vendor_model_send.final=final; + if ((15+payload_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_vendor_model_send.payload.len=payload_len; memcpy(cmd->data.cmd_vendor_model_send.payload.data,payload,payload_len); @@ -1397,6 +1437,10 @@ sl_status_t sl_btmesh_vendor_model_set_publication(uint16_t elem_index, cmd->data.cmd_vendor_model_set_publication.model_id=model_id; cmd->data.cmd_vendor_model_set_publication.opcode=opcode; cmd->data.cmd_vendor_model_set_publication.final=final; + if ((9+payload_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_vendor_model_set_publication.payload.len=payload_len; memcpy(cmd->data.cmd_vendor_model_set_publication.payload.data,payload,payload_len); @@ -1460,6 +1504,10 @@ sl_status_t sl_btmesh_vendor_model_init(uint16_t elem_index, cmd->data.cmd_vendor_model_init.vendor_id=vendor_id; cmd->data.cmd_vendor_model_init.model_id=model_id; cmd->data.cmd_vendor_model_init.publish=publish; + if ((8+opcodes_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_vendor_model_init.opcodes.len=opcodes_len; memcpy(cmd->data.cmd_vendor_model_init.opcodes.data,opcodes,opcodes_len); @@ -1517,6 +1565,10 @@ sl_status_t sl_btmesh_vendor_model_send_tracked(uint16_t destination_address, cmd->data.cmd_vendor_model_send_tracked.segment=segment; cmd->data.cmd_vendor_model_send_tracked.opcode=opcode; cmd->data.cmd_vendor_model_send_tracked.final=final; + if ((16+payload_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_vendor_model_send_tracked.payload.len=payload_len; memcpy(cmd->data.cmd_vendor_model_send_tracked.payload.data,payload,payload_len); @@ -1548,6 +1600,10 @@ sl_status_t sl_btmesh_vendor_model_set_publication_tracked(uint16_t elem_index, cmd->data.cmd_vendor_model_set_publication_tracked.segment=segment; cmd->data.cmd_vendor_model_set_publication_tracked.opcode=opcode; cmd->data.cmd_vendor_model_set_publication_tracked.final=final; + if ((10+payload_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_vendor_model_set_publication_tracked.payload.len=payload_len; memcpy(cmd->data.cmd_vendor_model_set_publication_tracked.payload.data,payload,payload_len); @@ -1814,6 +1870,10 @@ sl_status_t sl_btmesh_generic_client_set(uint16_t server_address, cmd->data.cmd_generic_client_set.delay_ms=delay_ms; cmd->data.cmd_generic_client_set.flags=flags; cmd->data.cmd_generic_client_set.type=type; + if ((19+parameters_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_generic_client_set.parameters.len=parameters_len; memcpy(cmd->data.cmd_generic_client_set.parameters.data,parameters,parameters_len); @@ -1845,6 +1905,10 @@ sl_status_t sl_btmesh_generic_client_publish(uint16_t elem_index, cmd->data.cmd_generic_client_publish.delay_ms=delay_ms; cmd->data.cmd_generic_client_publish.flags=flags; cmd->data.cmd_generic_client_publish.type=type; + if ((15+parameters_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_generic_client_publish.parameters.len=parameters_len; memcpy(cmd->data.cmd_generic_client_publish.parameters.data,parameters,parameters_len); @@ -1872,6 +1936,10 @@ sl_status_t sl_btmesh_generic_client_get_params(uint16_t server_address, cmd->data.cmd_generic_client_get_params.model_id=model_id; cmd->data.cmd_generic_client_get_params.appkey_index=appkey_index; cmd->data.cmd_generic_client_get_params.type=type; + if ((10+parameters_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_generic_client_get_params.parameters.len=parameters_len; memcpy(cmd->data.cmd_generic_client_get_params.parameters.data,parameters,parameters_len); @@ -2085,6 +2153,10 @@ sl_status_t sl_btmesh_generic_server_respond(uint16_t client_address, cmd->data.cmd_generic_server_respond.remaining_ms=remaining_ms; cmd->data.cmd_generic_server_respond.flags=flags; cmd->data.cmd_generic_server_respond.type=type; + if ((16+parameters_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_generic_server_respond.parameters.len=parameters_len; memcpy(cmd->data.cmd_generic_server_respond.parameters.data,parameters,parameters_len); @@ -2110,6 +2182,10 @@ sl_status_t sl_btmesh_generic_server_update(uint16_t elem_index, cmd->data.cmd_generic_server_update.model_id=model_id; cmd->data.cmd_generic_server_update.remaining_ms=remaining_ms; cmd->data.cmd_generic_server_update.type=type; + if ((10+parameters_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_generic_server_update.parameters.len=parameters_len; memcpy(cmd->data.cmd_generic_server_update.parameters.data,parameters,parameters_len); @@ -2617,6 +2693,10 @@ sl_status_t sl_btmesh_test_add_local_model_sub_va(uint16_t elem_index, cmd->data.cmd_test_add_local_model_sub_va.elem_index=elem_index; cmd->data.cmd_test_add_local_model_sub_va.vendor_id=vendor_id; cmd->data.cmd_test_add_local_model_sub_va.model_id=model_id; + if ((7+sub_address_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_test_add_local_model_sub_va.sub_address.len=sub_address_len; memcpy(cmd->data.cmd_test_add_local_model_sub_va.sub_address.data,sub_address,sub_address_len); @@ -2640,6 +2720,10 @@ sl_status_t sl_btmesh_test_remove_local_model_sub_va(uint16_t elem_index, cmd->data.cmd_test_remove_local_model_sub_va.elem_index=elem_index; cmd->data.cmd_test_remove_local_model_sub_va.vendor_id=vendor_id; cmd->data.cmd_test_remove_local_model_sub_va.model_id=model_id; + if ((7+sub_address_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_test_remove_local_model_sub_va.sub_address.len=sub_address_len; memcpy(cmd->data.cmd_test_remove_local_model_sub_va.sub_address.data,sub_address,sub_address_len); @@ -2730,6 +2814,10 @@ sl_status_t sl_btmesh_test_set_local_model_pub_va(uint16_t elem_index, cmd->data.cmd_test_set_local_model_pub_va.period=period; cmd->data.cmd_test_set_local_model_pub_va.retrans=retrans; cmd->data.cmd_test_set_local_model_pub_va.credentials=credentials; + if ((13+pub_address_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_test_set_local_model_pub_va.pub_address.len=pub_address_len; memcpy(cmd->data.cmd_test_set_local_model_pub_va.pub_address.data,pub_address,pub_address_len); @@ -2870,6 +2958,10 @@ SL_BGAPI_DEPRECATED sl_status_t sl_btmesh_test_set_local_config(uint16_t id, cmd->data.cmd_test_set_local_config.id=id; cmd->data.cmd_test_set_local_config.netkey_index=netkey_index; + if ((5+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_test_set_local_config.value.len=value_len; memcpy(cmd->data.cmd_test_set_local_config.value.data,value,value_len); @@ -3027,6 +3119,10 @@ sl_status_t sl_btmesh_test_prov_prepare_key_refresh(aes_key_128 net_key, struct sl_btmesh_packet *rsp = (struct sl_btmesh_packet *)sl_btmesh_rsp_msg; memcpy(&cmd->data.cmd_test_prov_prepare_key_refresh.net_key,&net_key,sizeof(aes_key_128)); + if ((17+app_keys_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_test_prov_prepare_key_refresh.app_keys.len=app_keys_len; memcpy(cmd->data.cmd_test_prov_prepare_key_refresh.app_keys.data,app_keys,app_keys_len); @@ -4559,6 +4655,10 @@ sl_status_t sl_btmesh_sensor_server_init(uint16_t elem_index, struct sl_btmesh_packet *rsp = (struct sl_btmesh_packet *)sl_btmesh_rsp_msg; cmd->data.cmd_sensor_server_init.elem_index=elem_index; + if ((3+descriptors_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_sensor_server_init.descriptors.len=descriptors_len; memcpy(cmd->data.cmd_sensor_server_init.descriptors.data,descriptors,descriptors_len); @@ -4599,6 +4699,10 @@ sl_status_t sl_btmesh_sensor_server_send_descriptor_status(uint16_t client_addre cmd->data.cmd_sensor_server_send_descriptor_status.elem_index=elem_index; cmd->data.cmd_sensor_server_send_descriptor_status.appkey_index=appkey_index; cmd->data.cmd_sensor_server_send_descriptor_status.flags=flags; + if ((8+descriptors_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_sensor_server_send_descriptor_status.descriptors.len=descriptors_len; memcpy(cmd->data.cmd_sensor_server_send_descriptor_status.descriptors.data,descriptors,descriptors_len); @@ -4624,6 +4728,10 @@ sl_status_t sl_btmesh_sensor_server_send_status(uint16_t client_address, cmd->data.cmd_sensor_server_send_status.elem_index=elem_index; cmd->data.cmd_sensor_server_send_status.appkey_index=appkey_index; cmd->data.cmd_sensor_server_send_status.flags=flags; + if ((8+sensor_data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_sensor_server_send_status.sensor_data.len=sensor_data_len; memcpy(cmd->data.cmd_sensor_server_send_status.sensor_data.data,sensor_data,sensor_data_len); @@ -4651,6 +4759,10 @@ sl_status_t sl_btmesh_sensor_server_send_column_status(uint16_t client_address, cmd->data.cmd_sensor_server_send_column_status.appkey_index=appkey_index; cmd->data.cmd_sensor_server_send_column_status.flags=flags; cmd->data.cmd_sensor_server_send_column_status.property_id=property_id; + if ((10+sensor_data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_sensor_server_send_column_status.sensor_data.len=sensor_data_len; memcpy(cmd->data.cmd_sensor_server_send_column_status.sensor_data.data,sensor_data,sensor_data_len); @@ -4678,6 +4790,10 @@ sl_status_t sl_btmesh_sensor_server_send_series_status(uint16_t client_address, cmd->data.cmd_sensor_server_send_series_status.appkey_index=appkey_index; cmd->data.cmd_sensor_server_send_series_status.flags=flags; cmd->data.cmd_sensor_server_send_series_status.property_id=property_id; + if ((10+sensor_data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_sensor_server_send_series_status.sensor_data.len=sensor_data_len; memcpy(cmd->data.cmd_sensor_server_send_series_status.sensor_data.data,sensor_data,sensor_data_len); @@ -4705,6 +4821,10 @@ sl_status_t sl_btmesh_sensor_setup_server_send_cadence_status(uint16_t client_ad cmd->data.cmd_sensor_setup_server_send_cadence_status.appkey_index=appkey_index; cmd->data.cmd_sensor_setup_server_send_cadence_status.flags=flags; cmd->data.cmd_sensor_setup_server_send_cadence_status.property_id=property_id; + if ((10+params_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_sensor_setup_server_send_cadence_status.params.len=params_len; memcpy(cmd->data.cmd_sensor_setup_server_send_cadence_status.params.data,params,params_len); @@ -4732,6 +4852,10 @@ sl_status_t sl_btmesh_sensor_setup_server_send_settings_status(uint16_t client_a cmd->data.cmd_sensor_setup_server_send_settings_status.appkey_index=appkey_index; cmd->data.cmd_sensor_setup_server_send_settings_status.flags=flags; cmd->data.cmd_sensor_setup_server_send_settings_status.property_id=property_id; + if ((10+setting_ids_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_sensor_setup_server_send_settings_status.setting_ids.len=setting_ids_len; memcpy(cmd->data.cmd_sensor_setup_server_send_settings_status.setting_ids.data,setting_ids,setting_ids_len); @@ -4761,6 +4885,10 @@ sl_status_t sl_btmesh_sensor_setup_server_send_setting_status(uint16_t client_ad cmd->data.cmd_sensor_setup_server_send_setting_status.flags=flags; cmd->data.cmd_sensor_setup_server_send_setting_status.property_id=property_id; cmd->data.cmd_sensor_setup_server_send_setting_status.setting_id=setting_id; + if ((12+raw_value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_sensor_setup_server_send_setting_status.raw_value.len=raw_value_len; memcpy(cmd->data.cmd_sensor_setup_server_send_setting_status.raw_value.data,raw_value,raw_value_len); @@ -4862,6 +4990,10 @@ sl_status_t sl_btmesh_sensor_client_get_column(uint16_t server_address, cmd->data.cmd_sensor_client_get_column.appkey_index=appkey_index; cmd->data.cmd_sensor_client_get_column.flags=flags; cmd->data.cmd_sensor_client_get_column.property_id=property_id; + if ((10+column_id_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_sensor_client_get_column.column_id.len=column_id_len; memcpy(cmd->data.cmd_sensor_client_get_column.column_id.data,column_id,column_id_len); @@ -4889,6 +5021,10 @@ sl_status_t sl_btmesh_sensor_client_get_series(uint16_t server_address, cmd->data.cmd_sensor_client_get_series.appkey_index=appkey_index; cmd->data.cmd_sensor_client_get_series.flags=flags; cmd->data.cmd_sensor_client_get_series.property_id=property_id; + if ((10+column_ids_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_sensor_client_get_series.column_ids.len=column_ids_len; memcpy(cmd->data.cmd_sensor_client_get_series.column_ids.data,column_ids,column_ids_len); @@ -4939,6 +5075,10 @@ sl_status_t sl_btmesh_sensor_client_set_cadence(uint16_t server_address, cmd->data.cmd_sensor_client_set_cadence.appkey_index=appkey_index; cmd->data.cmd_sensor_client_set_cadence.flags=flags; cmd->data.cmd_sensor_client_set_cadence.property_id=property_id; + if ((10+params_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_sensor_client_set_cadence.params.len=params_len; memcpy(cmd->data.cmd_sensor_client_set_cadence.params.data,params,params_len); @@ -5016,6 +5156,10 @@ sl_status_t sl_btmesh_sensor_client_set_setting(uint16_t server_address, cmd->data.cmd_sensor_client_set_setting.flags=flags; cmd->data.cmd_sensor_client_set_setting.property_id=property_id; cmd->data.cmd_sensor_client_set_setting.setting_id=setting_id; + if ((12+raw_value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_sensor_client_set_setting.raw_value.len=raw_value_len; memcpy(cmd->data.cmd_sensor_client_set_setting.raw_value.data,raw_value,raw_value_len); @@ -5211,6 +5355,10 @@ sl_status_t sl_btmesh_lc_client_set_property(uint16_t server_address, cmd->data.cmd_lc_client_set_property.appkey_index=appkey_index; cmd->data.cmd_lc_client_set_property.flags=flags; cmd->data.cmd_lc_client_set_property.property_id=property_id; + if ((10+params_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_lc_client_set_property.params.len=params_len; memcpy(cmd->data.cmd_lc_client_set_property.params.data,params,params_len); @@ -5402,6 +5550,10 @@ sl_status_t sl_btmesh_lc_setup_server_update_property(uint16_t elem_index, cmd->data.cmd_lc_setup_server_update_property.elem_index=elem_index; cmd->data.cmd_lc_setup_server_update_property.property_id=property_id; + if ((5+params_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } cmd->data.cmd_lc_setup_server_update_property.params.len=params_len; memcpy(cmd->data.cmd_lc_setup_server_update_property.params.data,params,params_len); diff --git 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Should be stored on 2 bytes. */ -#define EMBER_BUILD_NUMBER 191 +#define EMBER_BUILD_NUMBER 273 /** * @brief Full version number stored on 2 bytes, with each of the four digits diff --git a/protocol/openthread/component/ot_cert_libs.slcc b/protocol/openthread/component/ot_cert_libs.slcc new file mode 100644 index 0000000000..807c7e466d --- /dev/null +++ b/protocol/openthread/component/ot_cert_libs.slcc @@ -0,0 +1,170 @@ +id: ot_cert_libs +label: OpenThread Certification configuration +package: OpenThread +category: OpenThread +quality: production +description: Includes OpenThread certification libraries with default certification configuration (Stack and PAL) +provides: + - name: ot_cert_libs + +config_file: + - path: protocol/openthread/config/sl_openthread_features_ftd_cert_config.h + file_id: openthread_features + condition: [ot_stack_ftd] + - path: protocol/openthread/config/sl_openthread_features_mtd_cert_config.h + file_id: openthread_features + condition: [ot_stack_mtd] + +define: + - name: SL_OPENTHREAD_STACK_FEATURES_CONFIG_FILE + value: "\"sl_openthread_features_ftd_cert_config.h\"" + condition: [ot_stack_ftd] + - name: SL_OPENTHREAD_STACK_FEATURES_CONFIG_FILE + value: "\"sl_openthread_features_mtd_cert_config.h\"" + condition: [ot_stack_mtd] + +library: + - path: protocol/openthread/libs/libsl_ot_stack_ftd_efr32mg12_gcc.a + condition: + - toolchain_gcc + - device_sdid_84 + - ot_stack_ftd + - path: protocol/openthread/libs/libsl_ot_stack_mtd_efr32mg12_gcc.a + condition: + - toolchain_gcc + - device_sdid_84 + - ot_stack_mtd + - path: protocol/openthread/libs/libsl_platform_ftd_efr32mg12_gcc.a + condition: + - toolchain_gcc + - device_sdid_84 + - ot_stack_ftd + unless: + - rail_lib_multiprotocol + - path: protocol/openthread/libs/libsl_platform_mtd_efr32mg12_gcc.a + condition: + - toolchain_gcc + - device_sdid_84 + - ot_stack_mtd + unless: + - rail_lib_multiprotocol + - path: protocol/openthread/libs/libsl_platform_ftd_dmp_efr32mg12_gcc.a + condition: + - toolchain_gcc + - device_sdid_84 + - ot_stack_ftd + - rail_lib_multiprotocol + - path: protocol/openthread/libs/libsl_platform_mtd_dmp_efr32mg12_gcc.a + condition: + - toolchain_gcc + - device_sdid_84 + - ot_stack_mtd + - rail_lib_multiprotocol + - path: protocol/openthread/libs/libsl_ot_stack_ftd_efr32mg13_gcc.a + condition: + - toolchain_gcc + - device_sdid_89 + - ot_stack_ftd + - path: protocol/openthread/libs/libsl_ot_stack_mtd_efr32mg13_gcc.a + condition: + - toolchain_gcc + - device_sdid_89 + - ot_stack_mtd + - path: protocol/openthread/libs/libsl_platform_ftd_efr32mg13_gcc.a + condition: + - toolchain_gcc + - device_sdid_89 + - ot_stack_ftd + unless: + - rail_lib_multiprotocol + - path: protocol/openthread/libs/libsl_platform_mtd_efr32mg13_gcc.a + condition: + - toolchain_gcc + - device_sdid_89 + - ot_stack_mtd + unless: + - rail_lib_multiprotocol + - path: protocol/openthread/libs/libsl_platform_ftd_dmp_efr32mg13_gcc.a + condition: + - toolchain_gcc + - device_sdid_89 + - ot_stack_ftd + - rail_lib_multiprotocol + - path: protocol/openthread/libs/libsl_platform_mtd_dmp_efr32mg13_gcc.a + condition: + - toolchain_gcc + - device_sdid_89 + - ot_stack_mtd + - rail_lib_multiprotocol + - path: protocol/openthread/libs/libsl_ot_stack_ftd_efr32mg21_gcc.a + condition: + - toolchain_gcc + - device_sdid_200 + - ot_stack_ftd + - path: protocol/openthread/libs/libsl_ot_stack_mtd_efr32mg21_gcc.a + condition: + - toolchain_gcc + - device_sdid_200 + - ot_stack_mtd + - path: protocol/openthread/libs/libsl_platform_ftd_efr32mg21_gcc.a + condition: + - toolchain_gcc + - device_sdid_200 + - ot_stack_ftd + unless: + - rail_lib_multiprotocol + - path: protocol/openthread/libs/libsl_platform_mtd_efr32mg21_gcc.a + condition: + - toolchain_gcc + - device_sdid_200 + - ot_stack_mtd + unless: + - rail_lib_multiprotocol + - path: protocol/openthread/libs/libsl_platform_ftd_dmp_efr32mg21_gcc.a + condition: + - toolchain_gcc + - device_sdid_200 + - ot_stack_ftd + - rail_lib_multiprotocol + - path: protocol/openthread/libs/libsl_platform_mtd_dmp_efr32mg21_gcc.a + condition: + - toolchain_gcc + - device_sdid_200 + - ot_stack_mtd + - rail_lib_multiprotocol + - path: protocol/openthread/libs/libsl_ot_stack_ftd_efr32mg24_gcc.a + condition: + - toolchain_gcc + - device_sdid_215 + - ot_stack_ftd + - path: protocol/openthread/libs/libsl_ot_stack_mtd_efr32mg24_gcc.a + condition: + - toolchain_gcc + - device_sdid_215 + - ot_stack_mtd + - path: protocol/openthread/libs/libsl_platform_ftd_efr32mg24_gcc.a + condition: + - toolchain_gcc + - device_sdid_215 + - ot_stack_ftd + unless: + - rail_lib_multiprotocol + - path: protocol/openthread/libs/libsl_platform_mtd_efr32mg24_gcc.a + condition: + - toolchain_gcc + - device_sdid_215 + - ot_stack_mtd + unless: + - rail_lib_multiprotocol + - path: protocol/openthread/libs/libsl_platform_ftd_dmp_efr32mg24_gcc.a + condition: + - toolchain_gcc + - device_sdid_215 + - ot_stack_ftd + - rail_lib_multiprotocol + - path: protocol/openthread/libs/libsl_platform_mtd_dmp_efr32mg24_gcc.a + condition: + - toolchain_gcc + - device_sdid_215 + - ot_stack_mtd + - rail_lib_multiprotocol diff --git a/protocol/openthread/component/ot_headers.slcc b/protocol/openthread/component/ot_headers.slcc new file mode 100644 index 0000000000..ee22edc341 --- /dev/null +++ b/protocol/openthread/component/ot_headers.slcc @@ -0,0 +1,340 @@ +id: ot_headers +label: OpenThread headers +package: OpenThread +category: OpenThread +quality: production +description: This component provides the OpenThread header files. +provides: + - name: ot_headers +ui_hints: + visibility: never +root_path: util/third_party/openthread/src/core +include: + - path: ../../include + - path: ../../include/openthread + file_list: + - path: backbone_router.h + - path: backbone_router_ftd.h + - path: border_agent.h + - path: border_router.h + - path: channel_manager.h + - path: channel_monitor.h + - path: child_supervision.h + - path: cli.h + - path: coap_secure.h + - path: coap.h + - path: commissioner.h + - path: config.h + - path: coprocessor_rpc.h + - path: crypto.h + - path: dataset.h + - path: dataset_ftd.h + - path: dataset_updater.h + - path: diag.h + - path: dns.h + - path: dns_client.h + - path: dnssd_server.h + - path: error.h + - path: heap.h + - path: history_tracker.h + - path: icmp6.h + - path: instance.h + - path: ip6.h + - path: jam_detection.h + - path: joiner.h + - path: link.h + - path: link_metrics.h + - path: link_raw.h + - path: logging.h + - path: message.h + - path: multi_radio.h + - path: ncp.h + - path: netdata.h + - path: netdata_publisher.h + - path: netdiag.h + - path: network_time.h + - path: ping_sender.h + - path: random_crypto.h + - path: random_noncrypto.h + - path: server.h + - path: sntp.h + - path: srp_client.h + - path: srp_client_buffers.h + - path: srp_server.h + - path: tasklet.h + - path: tcp.h + - path: tcp_ext.h + - path: thread.h + - path: thread_ftd.h + - path: trel.h + - path: udp.h + - path: platform/alarm-micro.h + - path: platform/alarm-milli.h + - path: platform/crypto.h + - path: platform/diag.h + - path: platform/dso_transport.h + - path: platform/entropy.h + - path: platform/flash.h + - path: platform/infra_if.h + - path: platform/memory.h + - path: platform/misc.h + - path: platform/logging.h + - path: platform/otns.h + - path: platform/radio.h + - path: platform/time.h + - path: platform/udp.h + - path: platform/spi-slave.h + - path: platform/settings.h + - path: platform/messagepool.h + - path: platform/toolchain.h + - path: platform/trel.h + - path: platform/debug_uart.h + - path: ./ + file_list: + - path: openthread-core-config.h + - path: backbone_router/backbone_tmf.hpp + - path: backbone_router/bbr_leader.hpp + - path: backbone_router/bbr_local.hpp + - path: backbone_router/bbr_manager.hpp + - path: backbone_router/multicast_listeners_table.hpp + - path: backbone_router/ndproxy_table.hpp + - path: border_router/infra_if.hpp + - path: border_router/routing_manager.hpp + - path: coap/coap.hpp + - path: coap/coap_message.hpp + - path: coap/coap_secure.hpp + - path: common/appender.hpp + - path: common/arg_macros.hpp + - path: common/array.hpp + - path: common/as_core_type.hpp + - path: common/binary_search.hpp + - path: common/bit_vector.hpp + - path: common/clearable.hpp + - path: common/code_utils.hpp + - path: common/const_cast.hpp + - path: common/crc16.hpp + - path: common/data.hpp + - path: common/debug.hpp + - path: common/encoding.hpp + - path: common/equatable.hpp + - path: common/error.hpp + - path: common/extension.hpp + - path: common/heap.hpp + - path: common/heap_allocatable.hpp + - path: common/heap_array.hpp + - path: common/heap_data.hpp + - path: common/heap_string.hpp + - path: common/instance.hpp + - path: common/iterator_utils.hpp + - path: common/linked_list.hpp + - path: common/locator.hpp + - path: common/locator_getters.hpp + - path: common/log.hpp + - path: common/logging.hpp + - path: common/message.hpp + - path: common/new.hpp + - path: common/non_copyable.hpp + - path: common/notifier.hpp + - path: common/numeric_limits.hpp + - path: common/owned_ptr.hpp + - path: common/owning_list.hpp + - path: common/pool.hpp + - path: common/ptr_wrapper.hpp + - path: common/random.hpp + - path: common/retain_ptr.hpp + - path: common/serial_number.hpp + - path: common/settings.hpp + - path: common/settings_driver.hpp + - path: common/string.hpp + - path: common/tasklet.hpp + - path: common/time.hpp + - path: common/time_ticker.hpp + - path: common/timer.hpp + - path: common/tlvs.hpp + - path: common/trickle_timer.hpp + - path: common/type_traits.hpp + - path: common/uptime.hpp + - path: config/announce_sender.h + - path: config/backbone_router.h + - path: config/border_router.h + - path: config/channel_manager.h + - path: config/channel_monitor.h + - path: config/child_supervision.h + - path: config/coap.h + - path: config/commissioner.h + - path: config/coprocessor_rpc.h + - path: config/crypto.h + - path: config/dataset_updater.h + - path: config/dhcp6_client.h + - path: config/dhcp6_server.h + - path: config/diag.h + - path: config/dns_client.h + - path: config/dns_dso.h + - path: config/dnssd_server.h + - path: config/dtls.h + - path: config/history_tracker.h + - path: config/ip6.h + - path: config/joiner.h + - path: config/link_quality.h + - path: config/link_raw.h + - path: config/logging.h + - path: config/mac.h + - path: config/misc.h + - path: config/mle.h + - path: config/netdata_publisher.h + - path: config/openthread-core-config-check.h + - path: config/parent_search.h + - path: config/ping_sender.h + - path: config/platform.h + - path: config/sntp_client.h + - path: config/srp_client.h + - path: config/srp_server.h + - path: config/radio_link.h + - path: config/time_sync.h + - path: config/tmf.h + - path: coprocessor/rpc.hpp + - path: crypto/aes_ccm.hpp + - path: crypto/aes_ecb.hpp + - path: crypto/context_size.hpp + - path: crypto/ecdsa.hpp + - path: crypto/hkdf_sha256.hpp + - path: crypto/hmac_sha256.hpp + - path: crypto/mbedtls.hpp + - path: crypto/pbkdf2_cmac.hpp + - path: crypto/sha256.hpp + - path: crypto/storage.hpp + - path: diags/factory_diags.hpp + - path: mac/channel_mask.hpp + - path: mac/data_poll_handler.hpp + - path: mac/data_poll_sender.hpp + - path: mac/link_raw.hpp + - path: mac/mac.hpp + - path: mac/mac_filter.hpp + - path: mac/mac_frame.hpp + - path: mac/mac_links.hpp + - path: mac/mac_types.hpp + - path: mac/sub_mac.hpp + - path: meshcop/announce_begin_client.hpp + - path: meshcop/border_agent.hpp + - path: meshcop/commissioner.hpp + - path: meshcop/dataset.hpp + - path: meshcop/dataset_local.hpp + - path: meshcop/dataset_manager.hpp + - path: meshcop/dataset_updater.hpp + - path: meshcop/dtls.hpp + - path: meshcop/energy_scan_client.hpp + - path: meshcop/extended_panid.hpp + - path: meshcop/joiner.hpp + - path: meshcop/joiner_router.hpp + - path: meshcop/meshcop.hpp + - path: meshcop/meshcop_leader.hpp + - path: meshcop/meshcop_tlvs.hpp + - path: meshcop/network_name.hpp + - path: meshcop/panid_query_client.hpp + - path: meshcop/timestamp.hpp + - path: net/checksum.hpp + - path: net/dhcp6.hpp + - path: net/dhcp6_client.hpp + - path: net/dhcp6_server.hpp + - path: net/dns_client.hpp + - path: net/dns_dso.hpp + - path: net/dns_types.hpp + - path: net/dnssd_server.hpp + - path: net/icmp6.hpp + - path: net/ip4_address.hpp + - path: net/ip6.hpp + - path: net/ip6_address.hpp + - path: net/ip6_filter.hpp + - path: net/ip6_headers.hpp + - path: net/ip6_mpl.hpp + - path: net/ip6_types.hpp + - path: net/nd_agent.hpp + - path: net/nd6.hpp + - path: net/netif.hpp + - path: net/sntp_client.hpp + - path: net/socket.hpp + - path: net/srp_client.hpp + - path: net/srp_server.hpp + - path: net/tcp6.hpp + - path: net/udp6.hpp + - path: radio/radio.hpp + - path: radio/trel_interface.hpp + - path: radio/trel_link.hpp + - path: radio/trel_packet.hpp + - path: thread/address_resolver.hpp + - path: thread/announce_begin_server.hpp + - path: thread/announce_sender.hpp + - path: thread/anycast_locator.hpp + - path: thread/child_mask.hpp + - path: thread/child_table.hpp + - path: thread/csl_tx_scheduler.hpp + - path: thread/discover_scanner.hpp + - path: thread/dua_manager.hpp + - path: thread/energy_scan_server.hpp + - path: thread/indirect_sender.hpp + - path: thread/indirect_sender_frame_context.hpp + - path: thread/key_manager.hpp + - path: thread/link_metrics.hpp + - path: thread/link_metrics_tlvs.hpp + - path: thread/link_quality.hpp + - path: thread/lowpan.hpp + - path: thread/mesh_forwarder.hpp + - path: thread/mle.hpp + - path: thread/mle_router.hpp + - path: thread/mle_tlvs.hpp + - path: thread/mle_types.hpp + - path: thread/mlr_manager.hpp + - path: thread/mlr_types.hpp + - path: thread/neighbor_table.hpp + - path: thread/network_data.hpp + - path: thread/network_data_leader.hpp + - path: thread/network_data_leader_ftd.hpp + - path: thread/network_data_local.hpp + - path: thread/network_data_notifier.hpp + - path: thread/network_data_publisher.hpp + - path: thread/network_data_service.hpp + - path: thread/network_data_tlvs.hpp + - path: thread/network_data_types.hpp + - path: thread/network_diagnostic.hpp + - path: thread/network_diagnostic_tlvs.hpp + - path: thread/panid_query_server.hpp + - path: thread/radio_selector.hpp + - path: thread/router_table.hpp + - path: thread/src_match_controller.hpp + - path: thread/thread_netif.hpp + - path: thread/thread_tlvs.hpp + - path: thread/time_sync_service.hpp + - path: thread/tmf.hpp + - path: thread/topology.hpp + - path: thread/uri_paths.hpp + - path: utils/channel_manager.hpp + - path: utils/channel_monitor.hpp + - path: utils/child_supervision.hpp + - path: utils/flash.hpp + - path: utils/heap.hpp + - path: utils/history_tracker.hpp + - path: utils/jam_detector.hpp + - path: utils/otns.hpp + - path: utils/parse_cmdline.hpp + - path: utils/ping_sender.hpp + - path: utils/slaac_address.hpp + - path: utils/srp_client_buffers.hpp + - path: ../../third_party/tcplp + file_list: + - path: bsdtcp/cc.h + - path: bsdtcp/cc/cc_module.h + - path: bsdtcp/icmp_var.h + - path: bsdtcp/ip.h + - path: bsdtcp/ip6.h + - path: bsdtcp/sys/queue.h + - path: bsdtcp/tcp.h + - path: bsdtcp/tcp_const.h + - path: bsdtcp/tcp_fsm.h + - path: bsdtcp/tcp_seq.h + - path: bsdtcp/tcp_timer.h + - path: bsdtcp/tcp_var.h + - path: bsdtcp/types.h + - path: lib/bitmap.h + - path: lib/cbuf.h + - path: lib/lbuf.h + - path: tcplp.h diff --git a/protocol/openthread/component/ot_ncp_cpc.slcc b/protocol/openthread/component/ot_ncp_cpc.slcc index 81d4d9d5c7..7a3094123d 100644 --- a/protocol/openthread/component/ot_ncp_cpc.slcc +++ b/protocol/openthread/component/ot_ncp_cpc.slcc @@ -10,6 +10,12 @@ requires: - name: ot_stack - name: ot_ncp - name: cpc_secondary + - name: ot_coex + unless: + - "zigbee_ncp_cpc" + - name: mbedtls_entropy_adc + condition: + - "device_family_efr32mg1" recommends: - id: ot_stack_rcp root_path: util/third_party/openthread/src @@ -29,9 +35,13 @@ define: value: 0 - name: OPENTHREAD_CONFIG_NCP_CPC_ENABLE value: 1 + - name: OPENTHREAD_CONFIG_COPROCESSOR_RPC_OUTPUT_BUFFER_SIZE + value: 512 + condition: + - "device_family_efr32mg1" toolchain_settings: - option: optimize value: speed condition: - - "device_family_efr32mg1p" + - "device_family_efr32mg1" diff --git a/protocol/openthread/component/ot_ncp_source.slcc b/protocol/openthread/component/ot_ncp_source.slcc index 4a377e2833..2a2a5ab5f3 100644 --- a/protocol/openthread/component/ot_ncp_source.slcc +++ b/protocol/openthread/component/ot_ncp_source.slcc @@ -24,6 +24,7 @@ include: file_list: - path: radio_spinel.hpp - path: radio_spinel_impl.hpp + - path: radio_spinel_metrics.h - path: spinel.h - path: spinel_buffer.hpp - path: spinel_decoder.hpp diff --git a/protocol/openthread/component/ot_platform_abstraction_core.slcc b/protocol/openthread/component/ot_platform_abstraction_core.slcc index f075c92e05..b71fb6dc10 100644 --- a/protocol/openthread/component/ot_platform_abstraction_core.slcc +++ b/protocol/openthread/component/ot_platform_abstraction_core.slcc @@ -27,6 +27,11 @@ requires: - name: nvm3_default - name: silabs_core_sl_malloc - name: toolchain_gcc + - name: device_supports_thread + # Temporary workaround for building cert libs with Series 2 generic OPNs + unless: [ot_cert_build] + - name: ot_platform_abstraction_source + unless: [ot_cert_libs] ui_hints: visibility: never include: @@ -36,48 +41,17 @@ include: - path: util/third_party/openthread/examples/platforms/utils file_list: - path: code_utils.h - - path: link_metrics.h - - path: logging_rtt.h - - path: mac_frame.h - - path: soft_source_match_table.h - - path: settings.h - path: uart.h - path: protocol/openthread/platform-abstraction/efr32 file_list: - path: board_config.h - - path: ieee802154mac.h - path: openthread-core-efr32-config.h - path: openthread-core-efr32-config-check.h - - path: ieee802154-packet-utils.hpp - path: platform-efr32.h - - path: platform-band.h - - path: rail_config.h - - path: security_manager.h - - path: sl_packet_utils.h - - path: sl_openthread.h - path: sleep.h condition: - power_manager source: - - path: util/third_party/openthread/examples/platforms/utils/debug_uart.c - - path: util/third_party/openthread/examples/platforms/utils/link_metrics.cpp - - path: util/third_party/openthread/examples/platforms/utils/logging_rtt.c - - path: util/third_party/openthread/examples/platforms/utils/mac_frame.cpp - - path: util/third_party/openthread/examples/platforms/utils/settings_ram.c - - path: util/third_party/openthread/examples/platforms/utils/soft_source_match_table.c - - path: protocol/openthread/platform-abstraction/efr32/alarm.c - - path: protocol/openthread/platform-abstraction/efr32/diag.c - - path: protocol/openthread/platform-abstraction/efr32/entropy.c - - path: protocol/openthread/platform-abstraction/efr32/flash.c - - path: protocol/openthread/platform-abstraction/efr32/logging.c - - path: protocol/openthread/platform-abstraction/efr32/memory.c - - path: protocol/openthread/platform-abstraction/efr32/misc.c - - path: protocol/openthread/platform-abstraction/efr32/crypto.c - - path: protocol/openthread/platform-abstraction/efr32/ieee802154-packet-utils.cpp - - path: protocol/openthread/platform-abstraction/efr32/radio.c - - path: protocol/openthread/platform-abstraction/efr32/security_manager.c - - path: protocol/openthread/platform-abstraction/efr32/startup-gcc.c - - path: protocol/openthread/platform-abstraction/efr32/system.c - path: protocol/openthread/platform-abstraction/efr32/uartdrv_uart.c condition: - uartdrv_usart @@ -131,4 +105,4 @@ template_contribution: value: sl_ot_sleep_init priority: 10 condition: - - power_manager + - power_manager \ No newline at end of file diff --git a/protocol/openthread/component/ot_platform_abstraction_source.slcc b/protocol/openthread/component/ot_platform_abstraction_source.slcc new file mode 100644 index 0000000000..6e42c698af --- /dev/null +++ b/protocol/openthread/component/ot_platform_abstraction_source.slcc @@ -0,0 +1,48 @@ +id: ot_platform_abstraction_source +label: Platform Abstraction (Source) +package: OpenThread +category: OpenThread +quality: production +description: This component provides the source files for the platform abstraction layer between the OpenThread stack and Silicon Labs platform +provides: + - name: ot_platform_abstraction_source +ui_hints: + visibility: never +include: + - path: util/third_party/openthread/examples/platforms/utils + file_list: + - path: code_utils.h + - path: link_metrics.h + - path: logging_rtt.h + - path: mac_frame.h + - path: soft_source_match_table.h + - path: settings.h + - path: protocol/openthread/platform-abstraction/efr32 + file_list: + - path: ieee802154mac.h + - path: ieee802154-packet-utils.hpp + - path: platform-band.h + - path: rail_config.h + - path: security_manager.h + - path: sl_packet_utils.h + - path: sl_openthread.h +source: + - path: util/third_party/openthread/examples/platforms/utils/debug_uart.c + - path: util/third_party/openthread/examples/platforms/utils/link_metrics.cpp + - path: util/third_party/openthread/examples/platforms/utils/logging_rtt.c + - path: util/third_party/openthread/examples/platforms/utils/mac_frame.cpp + - path: util/third_party/openthread/examples/platforms/utils/settings_ram.c + - path: util/third_party/openthread/examples/platforms/utils/soft_source_match_table.c + - path: protocol/openthread/platform-abstraction/efr32/alarm.c + - path: protocol/openthread/platform-abstraction/efr32/diag.c + - path: protocol/openthread/platform-abstraction/efr32/entropy.c + - path: protocol/openthread/platform-abstraction/efr32/flash.c + - path: protocol/openthread/platform-abstraction/efr32/logging.c + - path: protocol/openthread/platform-abstraction/efr32/memory.c + - path: protocol/openthread/platform-abstraction/efr32/misc.c + - path: protocol/openthread/platform-abstraction/efr32/crypto.c + - path: protocol/openthread/platform-abstraction/efr32/ieee802154-packet-utils.cpp + - path: protocol/openthread/platform-abstraction/efr32/radio.c + - path: protocol/openthread/platform-abstraction/efr32/security_manager.c + - path: protocol/openthread/platform-abstraction/efr32/startup-gcc.c + - path: protocol/openthread/platform-abstraction/efr32/system.c diff --git a/protocol/openthread/component/ot_radio_source.slcc b/protocol/openthread/component/ot_radio_source.slcc index d4fbbdcbb9..77b59f3d4b 100644 --- a/protocol/openthread/component/ot_radio_source.slcc +++ b/protocol/openthread/component/ot_radio_source.slcc @@ -8,339 +8,9 @@ provides: - name: ot_radio requires: - name: cpp_support - - name: device_supports_thread ui_hints: visibility: never root_path: util/third_party/openthread/src/core -include: - - path: ../../include - - path: ../../include/openthread - file_list: - - path: backbone_router.h - - path: backbone_router_ftd.h - - path: border_agent.h - - path: border_router.h - - path: channel_manager.h - - path: channel_monitor.h - - path: child_supervision.h - - path: cli.h - - path: coap_secure.h - - path: coap.h - - path: commissioner.h - - path: config.h - - path: coprocessor_rpc.h - - path: crypto.h - - path: dataset.h - - path: dataset_ftd.h - - path: dataset_updater.h - - path: diag.h - - path: dns.h - - path: dns_client.h - - path: dnssd_server.h - - path: error.h - - path: heap.h - - path: history_tracker.h - - path: icmp6.h - - path: instance.h - - path: ip6.h - - path: jam_detection.h - - path: joiner.h - - path: link.h - - path: link_metrics.h - - path: link_raw.h - - path: logging.h - - path: message.h - - path: multi_radio.h - - path: ncp.h - - path: netdata.h - - path: netdata_publisher.h - - path: netdiag.h - - path: network_time.h - - path: ping_sender.h - - path: random_crypto.h - - path: random_noncrypto.h - - path: server.h - - path: sntp.h - - path: srp_client.h - - path: srp_client_buffers.h - - path: srp_server.h - - path: tasklet.h - - path: tcp.h - - path: tcp_ext.h - - path: thread.h - - path: thread_ftd.h - - path: trel.h - - path: udp.h - - path: platform/alarm-micro.h - - path: platform/alarm-milli.h - - path: platform/crypto.h - - path: platform/diag.h - - path: platform/dso_transport.h - - path: platform/entropy.h - - path: platform/flash.h - - path: platform/infra_if.h - - path: platform/memory.h - - path: platform/misc.h - - path: platform/logging.h - - path: platform/otns.h - - path: platform/radio.h - - path: platform/time.h - - path: platform/udp.h - - path: platform/spi-slave.h - - path: platform/settings.h - - path: platform/messagepool.h - - path: platform/toolchain.h - - path: platform/trel.h - - path: platform/debug_uart.h - - path: ./ - file_list: - - path: openthread-core-config.h - - path: backbone_router/backbone_tmf.hpp - - path: backbone_router/bbr_leader.hpp - - path: backbone_router/bbr_local.hpp - - path: backbone_router/bbr_manager.hpp - - path: backbone_router/multicast_listeners_table.hpp - - path: backbone_router/ndproxy_table.hpp - - path: border_router/infra_if.hpp - - path: border_router/router_advertisement.hpp - - path: border_router/routing_manager.hpp - - path: coap/coap.hpp - - path: coap/coap_message.hpp - - path: coap/coap_secure.hpp - - path: common/appender.hpp - - path: common/arg_macros.hpp - - path: common/array.hpp - - path: common/as_core_type.hpp - - path: common/binary_search.hpp - - path: common/bit_vector.hpp - - path: common/clearable.hpp - - path: common/code_utils.hpp - - path: common/const_cast.hpp - - path: common/crc16.hpp - - path: common/data.hpp - - path: common/debug.hpp - - path: common/encoding.hpp - - path: common/equatable.hpp - - path: common/error.hpp - - path: common/extension.hpp - - path: common/heap.hpp - - path: common/heap_allocatable.hpp - - path: common/heap_array.hpp - - path: common/heap_data.hpp - - path: common/heap_string.hpp - - path: common/instance.hpp - - path: common/iterator_utils.hpp - - path: common/linked_list.hpp - - path: common/locator.hpp - - path: common/locator_getters.hpp - - path: common/log.hpp - - path: common/logging.hpp - - path: common/message.hpp - - path: common/new.hpp - - path: common/non_copyable.hpp - - path: common/notifier.hpp - - path: common/numeric_limits.hpp - - path: common/owned_ptr.hpp - - path: common/owning_list.hpp - - path: common/pool.hpp - - path: common/ptr_wrapper.hpp - - path: common/random.hpp - - path: common/retain_ptr.hpp - - path: common/serial_number.hpp - - path: common/settings.hpp - - path: common/settings_driver.hpp - - path: common/string.hpp - - path: common/tasklet.hpp - - path: common/time.hpp - - path: common/time_ticker.hpp - - path: common/timer.hpp - - path: common/tlvs.hpp - - path: common/trickle_timer.hpp - - path: common/type_traits.hpp - - path: common/uptime.hpp - - path: config/announce_sender.h - - path: config/backbone_router.h - - path: config/border_router.h - - path: config/channel_manager.h - - path: config/channel_monitor.h - - path: config/child_supervision.h - - path: config/coap.h - - path: config/commissioner.h - - path: config/coprocessor_rpc.h - - path: config/crypto.h - - path: config/dataset_updater.h - - path: config/dhcp6_client.h - - path: config/dhcp6_server.h - - path: config/diag.h - - path: config/dns_client.h - - path: config/dns_dso.h - - path: config/dnssd_server.h - - path: config/dtls.h - - path: config/history_tracker.h - - path: config/ip6.h - - path: config/joiner.h - - path: config/link_quality.h - - path: config/link_raw.h - - path: config/logging.h - - path: config/mac.h - - path: config/misc.h - - path: config/mle.h - - path: config/netdata_publisher.h - - path: config/openthread-core-config-check.h - - path: config/parent_search.h - - path: config/ping_sender.h - - path: config/platform.h - - path: config/sntp_client.h - - path: config/srp_client.h - - path: config/srp_server.h - - path: config/radio_link.h - - path: config/time_sync.h - - path: config/tmf.h - - path: coprocessor/rpc.hpp - - path: crypto/aes_ccm.hpp - - path: crypto/aes_ecb.hpp - - path: crypto/context_size.hpp - - path: crypto/ecdsa.hpp - - path: crypto/hkdf_sha256.hpp - - path: crypto/hmac_sha256.hpp - - path: crypto/mbedtls.hpp - - path: crypto/pbkdf2_cmac.hpp - - path: crypto/sha256.hpp - - path: crypto/storage.hpp - - path: diags/factory_diags.hpp - - path: mac/channel_mask.hpp - - path: mac/data_poll_handler.hpp - - path: mac/data_poll_sender.hpp - - path: mac/link_raw.hpp - - path: mac/mac.hpp - - path: mac/mac_filter.hpp - - path: mac/mac_frame.hpp - - path: mac/mac_links.hpp - - path: mac/mac_types.hpp - - path: mac/sub_mac.hpp - - path: meshcop/announce_begin_client.hpp - - path: meshcop/border_agent.hpp - - path: meshcop/commissioner.hpp - - path: meshcop/dataset.hpp - - path: meshcop/dataset_local.hpp - - path: meshcop/dataset_manager.hpp - - path: meshcop/dataset_updater.hpp - - path: meshcop/dtls.hpp - - path: meshcop/energy_scan_client.hpp - - path: meshcop/extended_panid.hpp - - path: meshcop/joiner.hpp - - path: meshcop/joiner_router.hpp - - path: meshcop/meshcop.hpp - - path: meshcop/meshcop_leader.hpp - - path: meshcop/meshcop_tlvs.hpp - - path: meshcop/network_name.hpp - - path: meshcop/panid_query_client.hpp - - path: meshcop/timestamp.hpp - - path: net/checksum.hpp - - path: net/dhcp6.hpp - - path: net/dhcp6_client.hpp - - path: net/dhcp6_server.hpp - - path: net/dns_client.hpp - - path: net/dns_dso.hpp - - path: net/dns_types.hpp - - path: net/dnssd_server.hpp - - path: net/icmp6.hpp - - path: net/ip4_address.hpp - - path: net/ip6.hpp - - path: net/ip6_address.hpp - - path: net/ip6_filter.hpp - - path: net/ip6_headers.hpp - - path: net/ip6_mpl.hpp - - path: net/ip6_types.hpp - - path: net/nd_agent.hpp - - path: net/netif.hpp - - path: net/sntp_client.hpp - - path: net/socket.hpp - - path: net/srp_client.hpp - - path: net/srp_server.hpp - - path: net/tcp6.hpp - - path: net/udp6.hpp - - path: radio/radio.hpp - - path: radio/trel_interface.hpp - - path: radio/trel_link.hpp - - path: radio/trel_packet.hpp - - path: thread/address_resolver.hpp - - path: thread/announce_begin_server.hpp - - path: thread/announce_sender.hpp - - path: thread/anycast_locator.hpp - - path: thread/child_mask.hpp - - path: thread/child_table.hpp - - path: thread/csl_tx_scheduler.hpp - - path: thread/discover_scanner.hpp - - path: thread/dua_manager.hpp - - path: thread/energy_scan_server.hpp - - path: thread/indirect_sender.hpp - - path: thread/indirect_sender_frame_context.hpp - - path: thread/key_manager.hpp - - path: thread/link_metrics.hpp - - path: thread/link_metrics_tlvs.hpp - - path: thread/link_quality.hpp - - path: thread/lowpan.hpp - - path: thread/mesh_forwarder.hpp - - path: thread/mle.hpp - - path: thread/mle_router.hpp - - path: thread/mle_tlvs.hpp - - path: thread/mle_types.hpp - - path: thread/mlr_manager.hpp - - path: thread/mlr_types.hpp - - path: thread/neighbor_table.hpp - - path: thread/network_data.hpp - - path: thread/network_data_leader.hpp - - path: thread/network_data_leader_ftd.hpp - - path: thread/network_data_local.hpp - - path: thread/network_data_notifier.hpp - - path: thread/network_data_publisher.hpp - - path: thread/network_data_service.hpp - - path: thread/network_data_tlvs.hpp - - path: thread/network_data_types.hpp - - path: thread/network_diagnostic.hpp - - path: thread/network_diagnostic_tlvs.hpp - - path: thread/panid_query_server.hpp - - path: thread/radio_selector.hpp - - path: thread/router_table.hpp - - path: thread/src_match_controller.hpp - - path: thread/thread_netif.hpp - - path: thread/thread_tlvs.hpp - - path: thread/time_sync_service.hpp - - path: thread/tmf.hpp - - path: thread/topology.hpp - - path: thread/uri_paths.hpp - - path: utils/channel_manager.hpp - - path: utils/channel_monitor.hpp - - path: utils/child_supervision.hpp - - path: utils/flash.hpp - - path: utils/heap.hpp - - path: utils/history_tracker.hpp - - path: utils/jam_detector.hpp - - path: utils/otns.hpp - - path: utils/parse_cmdline.hpp - - path: utils/ping_sender.hpp - - path: utils/slaac_address.hpp - - path: utils/srp_client_buffers.hpp - - path: ../../third_party/tcplp - file_list: - - path: bsdtcp/cc.h - - path: bsdtcp/cc/cc_module.h - - path: bsdtcp/icmp_var.h - - path: bsdtcp/ip.h - - path: bsdtcp/ip6.h - - path: bsdtcp/sys/queue.h - - path: bsdtcp/tcp.h - - path: bsdtcp/tcp_const.h - - path: bsdtcp/tcp_fsm.h - - path: bsdtcp/tcp_seq.h - - path: bsdtcp/tcp_timer.h - - path: bsdtcp/tcp_var.h - - path: bsdtcp/types.h - - path: lib/bitmap.h - - path: lib/cbuf.h - - path: lib/lbuf.h - - path: tcplp.h source: - path: api/coprocessor_rpc_api.cpp - path: api/diags_api.cpp @@ -384,4 +54,4 @@ source: - path: utils/parse_cmdline.cpp template_contribution: - name: application_type - value: "APPLICATION_TYPE_THREAD" + value: "APPLICATION_TYPE_THREAD" \ No newline at end of file diff --git a/protocol/openthread/component/ot_reference_device.slcc b/protocol/openthread/component/ot_reference_device.slcc new file mode 100644 index 0000000000..3a78ed77c2 --- /dev/null +++ b/protocol/openthread/component/ot_reference_device.slcc @@ -0,0 +1,22 @@ +id: ot_reference_device +label: OpenThread Reference Device configuration +package: OpenThread +category: OpenThread +quality: production +description: Includes OpenThread Reference Device configuration +provides: + - name: ot_reference_device + +config_file: + - path: protocol/openthread/config/sl_openthread_reference_device_config.h + file_id: openthread_features + # Projects can either have reference device configuration or certification + # configuration (or none). This condition enforces mutual exclusivity. + unless: [ot_cert_libs] + +define: + - name: SL_OPENTHREAD_STACK_FEATURES_CONFIG_FILE + value: "\"sl_openthread_reference_device_config.h\"" + # Projects can either have reference device configuration or certification + # configuration (or none). This condition enforces mutual exclusivity. + unless: [ot_cert_libs] diff --git a/protocol/openthread/component/ot_stack_ftd.slcc b/protocol/openthread/component/ot_stack_ftd.slcc index 71fcc31e89..fb98efd0fc 100644 --- a/protocol/openthread/component/ot_stack_ftd.slcc +++ b/protocol/openthread/component/ot_stack_ftd.slcc @@ -6,17 +6,23 @@ quality: production description: This component provides the OpenThread stack for a Full Thread Device (FTD) provides: - name: ot_stack + - name: ot_stack_ftd requires: - name: ot_stack_common + unless: [ot_cert_libs] + - name: ot_headers - name: ot_platform_abstraction - name: ot_thirdparty - name: ot_psa_crypto config_file: - path: protocol/openthread/config/sl_openthread_features_config.h + file_id: openthread_features + unless: [ot_cert_libs,ot_reference_device] - path: protocol/openthread/config/sl_openthread_generic_config.h define: - name: SL_OPENTHREAD_STACK_FEATURES_CONFIG_FILE value: "\"sl_openthread_features_config.h\"" + unless: [ot_cert_libs,ot_reference_device] - name: OPENTHREAD_CONFIG_FILE value: "\"sl_openthread_generic_config.h\"" - name: OPENTHREAD_FTD @@ -24,4 +30,4 @@ define: - name: OPENTHREAD_SPINEL_CONFIG_OPENTHREAD_MESSAGE_ENABLE value: 1 condition: - - ot_ncp \ No newline at end of file + - ot_ncp diff --git a/protocol/openthread/component/ot_stack_mtd.slcc b/protocol/openthread/component/ot_stack_mtd.slcc index a53b4af29c..546c7e87f2 100644 --- a/protocol/openthread/component/ot_stack_mtd.slcc +++ b/protocol/openthread/component/ot_stack_mtd.slcc @@ -6,17 +6,23 @@ quality: production description: This component provides the OpenThread stack for a Minimal Thread Device (MTD) provides: - name: ot_stack + - name: ot_stack_mtd requires: - name: ot_stack_common + unless: [ot_cert_libs] + - name: ot_headers - name: ot_platform_abstraction - name: ot_thirdparty - name: ot_psa_crypto config_file: - path: protocol/openthread/config/sl_openthread_features_config.h + file_id: openthread_features + unless: [ot_cert_libs,ot_reference_device] - path: protocol/openthread/config/sl_openthread_generic_config.h define: - name: SL_OPENTHREAD_STACK_FEATURES_CONFIG_FILE value: "\"sl_openthread_features_config.h\"" + unless: [ot_cert_libs,ot_reference_device] - name: OPENTHREAD_CONFIG_FILE value: "\"sl_openthread_generic_config.h\"" - name: OPENTHREAD_MTD @@ -24,4 +30,4 @@ define: - name: OPENTHREAD_SPINEL_CONFIG_OPENTHREAD_MESSAGE_ENABLE value: 1 condition: - - ot_ncp \ No newline at end of file + - ot_ncp diff --git a/protocol/openthread/component/ot_stack_rcp.slcc b/protocol/openthread/component/ot_stack_rcp.slcc index dbb0548f62..a66f5253c5 100644 --- a/protocol/openthread/component/ot_stack_rcp.slcc +++ b/protocol/openthread/component/ot_stack_rcp.slcc @@ -9,6 +9,7 @@ provides: requires: - name: ot_ncp - name: ot_radio + - name: ot_headers - name: ot_platform_abstraction - name: ot_thirdparty config_file: diff --git a/protocol/openthread/component/ot_stack_source.slcc b/protocol/openthread/component/ot_stack_source.slcc index 7378ce7953..1bb9ff0e5a 100644 --- a/protocol/openthread/component/ot_stack_source.slcc +++ b/protocol/openthread/component/ot_stack_source.slcc @@ -8,6 +8,7 @@ provides: - name: ot_stack_common requires: - name: ot_radio + - name: ot_stack_tcp ui_hints: visibility: never root_path: util/third_party/openthread/src/core @@ -61,7 +62,6 @@ source: - path: backbone_router/multicast_listeners_table.cpp - path: backbone_router/ndproxy_table.cpp - path: border_router/infra_if.cpp - - path: border_router/router_advertisement.cpp - path: border_router/routing_manager.cpp - path: coap/coap.cpp - path: coap/coap_message.cpp @@ -125,6 +125,7 @@ source: - path: net/ip6_headers.cpp - path: net/ip6_mpl.cpp - path: net/nd_agent.cpp + - path: net/nd6.cpp - path: net/netif.cpp - path: net/sntp_client.cpp - path: net/socket.cpp @@ -182,18 +183,6 @@ source: - path: utils/ping_sender.cpp - path: utils/slaac_address.cpp - path: utils/srp_client_buffers.cpp - - path: ../../third_party/tcplp/bsdtcp/cc/cc_newreno.c - - path: ../../third_party/tcplp/bsdtcp/tcp_input.c - - path: ../../third_party/tcplp/bsdtcp/tcp_output.c - - path: ../../third_party/tcplp/bsdtcp/tcp_reass.c - - path: ../../third_party/tcplp/bsdtcp/tcp_sack.c - - path: ../../third_party/tcplp/bsdtcp/tcp_subr.c - - path: ../../third_party/tcplp/bsdtcp/tcp_timer.c - - path: ../../third_party/tcplp/bsdtcp/tcp_timewait.c - - path: ../../third_party/tcplp/bsdtcp/tcp_usrreq.c - - path: ../../third_party/tcplp/lib/bitmap.c - - path: ../../third_party/tcplp/lib/cbuf.c - - path: ../../third_party/tcplp/lib/lbuf.c template_contribution: - name: component_catalog value: openthread_stack diff --git a/protocol/openthread/component/ot_stack_tcp.slcc b/protocol/openthread/component/ot_stack_tcp.slcc new file mode 100644 index 0000000000..8ef6d98bc7 --- /dev/null +++ b/protocol/openthread/component/ot_stack_tcp.slcc @@ -0,0 +1,29 @@ +id: ot_stack_tcp +label: Stack (TCP) +package: OpenThread +category: OpenThread +quality: production +description: This component provides the OpenThread TCP support +provides: + - name: ot_stack_tcp +ui_hints: + visibility: never +root_path: util/third_party/openthread/third_party/tcplp +source: + - path: bsdtcp/cc/cc_newreno.c + - path: bsdtcp/tcp_input.c + - path: bsdtcp/tcp_output.c + - path: bsdtcp/tcp_reass.c + - path: bsdtcp/tcp_sack.c + - path: bsdtcp/tcp_subr.c + - path: bsdtcp/tcp_timer.c + - path: bsdtcp/tcp_timewait.c + - path: bsdtcp/tcp_usrreq.c + - path: lib/bitmap.c + - path: lib/cbuf.c + - path: lib/lbuf.c +toolchain_settings: + - option: gcc_compiler_option + value: "-Wno-sign-compare" + - option: gcc_compiler_option + value: "-Wno-unused-parameter" diff --git a/protocol/openthread/component/ot_thirdparty.slcc b/protocol/openthread/component/ot_thirdparty.slcc index 55926b2659..705f1560b3 100644 --- a/protocol/openthread/component/ot_thirdparty.slcc +++ b/protocol/openthread/component/ot_thirdparty.slcc @@ -9,3 +9,14 @@ provides: requires: - name: ot_mbedtls - name: segger_rtt +define: + - name: BUFFER_SIZE_DOWN + value: 0 + - name: BUFFER_SIZE_UP + value: 768 + unless: + - "device_family_efr32mg1" + - name: BUFFER_SIZE_UP + value: 128 + condition: + - "device_family_efr32mg1" diff --git a/protocol/openthread/config/sl_openthread_features_ftd_cert_config.h b/protocol/openthread/config/sl_openthread_features_ftd_cert_config.h new file mode 100644 index 0000000000..1a6b5e6a95 --- /dev/null +++ b/protocol/openthread/config/sl_openthread_features_ftd_cert_config.h @@ -0,0 +1,318 @@ +#ifndef _SL_OPENTHREAD_FEATURES_CONFIG_H +#define _SL_OPENTHREAD_FEATURES_CONFIG_H +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +// +// OpenThread Stack Configurations + +// Thread Stack Protocol Version +// +// Thread 1.1 +// Thread 1.2 +// Thread 1.3 +// Thread 1.2 and Thread 1.3 are compatible with Thread 1.1. +// Current Default: OT_THREAD_VERSION_1_3 +#ifndef OPENTHREAD_CONFIG_THREAD_VERSION +#define OPENTHREAD_CONFIG_THREAD_VERSION OT_THREAD_VERSION_1_3 +#endif +// + +#if (OPENTHREAD_CONFIG_THREAD_VERSION >= OT_THREAD_VERSION_1_2) +// The following features require at least Thread Stack Protocol Version 1.2 +// Backbone Router +#ifndef OPENTHREAD_CONFIG_BACKBONE_ROUTER_ENABLE +#define OPENTHREAD_CONFIG_BACKBONE_ROUTER_ENABLE 0 +#endif +// CSL Auto Synchronization using data polling +#ifndef OPENTHREAD_CONFIG_MAC_CSL_AUTO_SYNC_ENABLE +#define OPENTHREAD_CONFIG_MAC_CSL_AUTO_SYNC_ENABLE 1 +#endif +// CSL (Coordinated Sampled Listening) Debug +#ifndef OPENTHREAD_CONFIG_MAC_CSL_DEBUG_ENABLE +#define OPENTHREAD_CONFIG_MAC_CSL_DEBUG_ENABLE 0 +#endif +// CSL (Coordinated Sampled Listening) Receiver +#ifndef OPENTHREAD_CONFIG_MAC_CSL_RECEIVER_ENABLE +#define OPENTHREAD_CONFIG_MAC_CSL_RECEIVER_ENABLE 0 +#endif +// DUA (Domain Unicast Address) +#ifndef OPENTHREAD_CONFIG_DUA_ENABLE +#define OPENTHREAD_CONFIG_DUA_ENABLE 1 +#endif +// Link Metrics Initiator +#ifndef OPENTHREAD_CONFIG_MLE_LINK_METRICS_INITIATOR_ENABLE +#define OPENTHREAD_CONFIG_MLE_LINK_METRICS_INITIATOR_ENABLE 1 +#endif +// Link Metrics Subject +#ifndef OPENTHREAD_CONFIG_MLE_LINK_METRICS_SUBJECT_ENABLE +#define OPENTHREAD_CONFIG_MLE_LINK_METRICS_SUBJECT_ENABLE 1 +#endif +// Multicast Listener Registration +#ifndef OPENTHREAD_CONFIG_MLR_ENABLE +#define OPENTHREAD_CONFIG_MLR_ENABLE 1 +#endif +// DNS Client (Thread 1.3) +#ifndef OPENTHREAD_CONFIG_DNS_CLIENT_ENABLE +#define OPENTHREAD_CONFIG_DNS_CLIENT_ENABLE 1 +#endif +// DNS-SD Server (Thread 1.3) +#ifndef OPENTHREAD_CONFIG_DNSSD_SERVER_ENABLE +#define OPENTHREAD_CONFIG_DNSSD_SERVER_ENABLE 0 +#endif +// Service Registration Protocol (SRP) Client (Thread 1.3) +#ifndef OPENTHREAD_CONFIG_SRP_CLIENT_ENABLE +#define OPENTHREAD_CONFIG_SRP_CLIENT_ENABLE 1 +#endif +// Service Registration Protocol (SRP) Server (Thread 1.3) +#ifndef OPENTHREAD_CONFIG_SRP_SERVER_ENABLE +#define OPENTHREAD_CONFIG_SRP_SERVER_ENABLE 0 +#endif +// TCPlp (Low power TCP over OpenThread) (Thread 1.3) +#ifndef OPENTHREAD_CONFIG_TCP_ENABLE +#define OPENTHREAD_CONFIG_TCP_ENABLE 0 +#endif +// Thread over Infrastructure (Thread 1.3: NCP only) +#ifndef OPENTHREAD_CONFIG_RADIO_LINK_TREL_ENABLE +#define OPENTHREAD_CONFIG_RADIO_LINK_TREL_ENABLE 0 +#endif +// +#endif // OPENTHREAD_CONFIG_THREAD_VERSION >= OT_THREAD_VERSION_1_2 + +// Border Agent +#ifndef OPENTHREAD_CONFIG_BORDER_AGENT_ENABLE +#define OPENTHREAD_CONFIG_BORDER_AGENT_ENABLE 0 +#endif +// +// Border Router +#ifndef OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE +#define OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE 0 +#endif +// +// Channel Manager +#ifndef OPENTHREAD_CONFIG_CHANNEL_MANAGER_ENABLE +#define OPENTHREAD_CONFIG_CHANNEL_MANAGER_ENABLE 0 +#endif +// +// Channel Monitor +#ifndef OPENTHREAD_CONFIG_CHANNEL_MONITOR_ENABLE +#define OPENTHREAD_CONFIG_CHANNEL_MONITOR_ENABLE 0 +#endif +// +// Child Supervision +#ifndef OPENTHREAD_CONFIG_CHILD_SUPERVISION_ENABLE +#define OPENTHREAD_CONFIG_CHILD_SUPERVISION_ENABLE 0 +#endif +// +// Commissioner +#ifndef OPENTHREAD_CONFIG_COMMISSIONER_ENABLE +#define OPENTHREAD_CONFIG_COMMISSIONER_ENABLE 0 +#endif +// +// COAP API +#ifndef OPENTHREAD_CONFIG_COAP_API_ENABLE +#define OPENTHREAD_CONFIG_COAP_API_ENABLE 1 +#endif +// +// COAP Observe (RFC7641) API +#ifndef OPENTHREAD_CONFIG_COAP_OBSERVE_API_ENABLE +#define OPENTHREAD_CONFIG_COAP_OBSERVE_API_ENABLE 0 +#endif +// +// COAP Secure API +#ifndef OPENTHREAD_CONFIG_COAP_SECURE_API_ENABLE +#define OPENTHREAD_CONFIG_COAP_SECURE_API_ENABLE 0 +#endif +// +// DHCP6 Client +#ifndef OPENTHREAD_CONFIG_DHCP6_CLIENT_ENABLE +#define OPENTHREAD_CONFIG_DHCP6_CLIENT_ENABLE 1 +#endif +// +// DHCP6 Server +#ifndef OPENTHREAD_CONFIG_DHCP6_SERVER_ENABLE +#define OPENTHREAD_CONFIG_DHCP6_SERVER_ENABLE 0 +#endif +// +// Diagnostic +#ifndef OPENTHREAD_CONFIG_DIAG_ENABLE +#define OPENTHREAD_CONFIG_DIAG_ENABLE 0 +#endif +// +// ECDSA (Elliptic Curve Digital Signature Algorithm) (Required for Matter support) +#ifndef OPENTHREAD_CONFIG_ECDSA_ENABLE +#define OPENTHREAD_CONFIG_ECDSA_ENABLE 1 +#endif +// +// External Heap +#ifndef OPENTHREAD_CONFIG_HEAP_EXTERNAL_ENABLE +#define OPENTHREAD_CONFIG_HEAP_EXTERNAL_ENABLE 1 +#endif +// +// IPv6 Fragmentation +#ifndef OPENTHREAD_CONFIG_IP6_FRAGMENTATION_ENABLE +#define OPENTHREAD_CONFIG_IP6_FRAGMENTATION_ENABLE 0 +#endif +// +// Maximum number of IPv6 unicast addresses allowed to be externally added +#ifndef OPENTHREAD_CONFIG_IP6_MAX_EXT_UCAST_ADDRS +#define OPENTHREAD_CONFIG_IP6_MAX_EXT_UCAST_ADDRS 4 +#endif +// +// Maximum number of IPv6 multicast addresses allowed to be externally added +#ifndef OPENTHREAD_CONFIG_IP6_MAX_EXT_MCAST_ADDRS +#define OPENTHREAD_CONFIG_IP6_MAX_EXT_MCAST_ADDRS 4 +#endif +// +// Jam Detection +#ifndef OPENTHREAD_CONFIG_JAM_DETECTION_ENABLE +#define OPENTHREAD_CONFIG_JAM_DETECTION_ENABLE 0 +#endif +// +// Joiner +#ifndef OPENTHREAD_CONFIG_JOINER_ENABLE +#define OPENTHREAD_CONFIG_JOINER_ENABLE 1 +#endif +// +// Legacy Network +#ifndef OPENTHREAD_CONFIG_LEGACY_ENABLE +#define OPENTHREAD_CONFIG_LEGACY_ENABLE 0 +#endif +// +// Link Raw Service +#ifndef OPENTHREAD_CONFIG_LINK_RAW_ENABLE +#define OPENTHREAD_CONFIG_LINK_RAW_ENABLE 0 +#endif +// +// MAC Filter +#ifndef OPENTHREAD_CONFIG_MAC_FILTER_ENABLE +#define OPENTHREAD_CONFIG_MAC_FILTER_ENABLE 0 +#endif +// +// MLE Long Routes extension (experimental) +#ifndef OPENTHREAD_CONFIG_MLE_LONG_ROUTES_ENABLE +#define OPENTHREAD_CONFIG_MLE_LONG_ROUTES_ENABLE 0 +#endif +// +// MultiPAN RCP +#ifndef OPENTHREAD_CONFIG_MULTIPAN_RCP_ENABLE +#define OPENTHREAD_CONFIG_MULTIPAN_RCP_ENABLE 0 +#endif +// +// Multiple OpenThread Instances +#ifndef OPENTHREAD_CONFIG_MULTIPLE_INSTANCE_ENABLE +#define OPENTHREAD_CONFIG_MULTIPLE_INSTANCE_ENABLE 0 +#endif +// +// OTNS (OpenThread Network Simulator) +#ifndef OPENTHREAD_CONFIG_OTNS_ENABLE +#define OPENTHREAD_CONFIG_OTNS_ENABLE 0 +#endif +// +// Ping Sender Module +#ifndef OPENTHREAD_CONFIG_PING_SENDER_ENABLE +#define OPENTHREAD_CONFIG_PING_SENDER_ENABLE 1 +#endif +// +// Platform UDP +#ifndef OPENTHREAD_CONFIG_PLATFORM_UDP_ENABLE +#define OPENTHREAD_CONFIG_PLATFORM_UDP_ENABLE 0 +#endif +// +// Reference Device for Thread Test Harness +#ifndef OPENTHREAD_CONFIG_REFERENCE_DEVICE_ENABLE +#define OPENTHREAD_CONFIG_REFERENCE_DEVICE_ENABLE 0 +#endif +// +// Service Entries in Thread Network Data +#ifndef OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE +#define OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE 0 +#endif +// +// RAM (volatile-only storage) +#ifndef OPENTHREAD_SETTINGS_RAM +#define OPENTHREAD_SETTINGS_RAM 0 +#endif +// +// SLAAC Addresses +#ifndef OPENTHREAD_CONFIG_IP6_SLAAC_ENABLE +#define OPENTHREAD_CONFIG_IP6_SLAAC_ENABLE 1 +#endif +// +// SNTP Client +#ifndef OPENTHREAD_CONFIG_SNTP_CLIENT_ENABLE +#define OPENTHREAD_CONFIG_SNTP_CLIENT_ENABLE 0 +#endif +// +// TMF Network Diagnostics for MTD +#ifndef OPENTHREAD_CONFIG_TMF_NETWORK_DIAG_MTD_ENABLE +#define OPENTHREAD_CONFIG_TMF_NETWORK_DIAG_MTD_ENABLE 0 +#endif +// +// Time Synchronization Service +#define OPENTHREAD_CONFIG_TIME_SYNC_ENABLE 0 +// +// UDP Forward +#ifndef OPENTHREAD_CONFIG_UDP_FORWARD_ENABLE +#define OPENTHREAD_CONFIG_UDP_FORWARD_ENABLE 0 +#endif +// +// Enable Mac beacon payload parsing support +#ifndef OPENTHREAD_CONFIG_MAC_BEACON_PAYLOAD_PARSING_ENABLE +#define OPENTHREAD_CONFIG_MAC_BEACON_PAYLOAD_PARSING_ENABLE 1 +#endif +// +// +// Logging +// LOG_OUTPUT +// NONE +// APP +// PLATFORM_DEFINED +// Default: OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED +#ifndef OPENTHREAD_CONFIG_LOG_OUTPUT +#define OPENTHREAD_CONFIG_LOG_OUTPUT OPENTHREAD_CONFIG_LOG_OUTPUT_APP +#endif + +// DYNAMIC_LOG_LEVEL +#ifndef OPENTHREAD_CONFIG_LOG_LEVEL_DYNAMIC_ENABLE +#define OPENTHREAD_CONFIG_LOG_LEVEL_DYNAMIC_ENABLE 0 +#endif + +// Enable Logging +#define OPENTHREAD_FULL_LOGS_ENABLE 0 +#if OPENTHREAD_FULL_LOGS_ENABLE + +// Note: Enabling higher log levels, which include logging packet details, can cause delays which may result in join failures. +// LOG_LEVEL +// NONE +// CRIT +// WARN +// NOTE +// INFO +// DEBG +// Default: OT_LOG_LEVEL_DEBG +#ifndef OPENTHREAD_CONFIG_LOG_LEVEL +#define OPENTHREAD_CONFIG_LOG_LEVEL OT_LOG_LEVEL_DEBG +#endif +// CLI +#ifndef OPENTHREAD_CONFIG_LOG_CLI +#define OPENTHREAD_CONFIG_LOG_CLI 1 +#endif +// PKT_DUMP +#ifndef OPENTHREAD_CONFIG_LOG_PKT_DUMP +#define OPENTHREAD_CONFIG_LOG_PKT_DUMP 1 +#endif +// PLATFORM +#ifndef OPENTHREAD_CONFIG_LOG_PLATFORM +#define OPENTHREAD_CONFIG_LOG_PLATFORM 1 +#endif +// PREPEND_LEVEL +#ifndef OPENTHREAD_CONFIG_LOG_PREPEND_LEVEL +#define OPENTHREAD_CONFIG_LOG_PREPEND_LEVEL 1 +#endif + +#endif +// +// +// + +// <<< end of configuration section >>> +#endif // _SL_OPENTHREAD_FEATURES_CONFIG_H \ No newline at end of file diff --git a/protocol/openthread/config/sl_openthread_features_mtd_cert_config.h b/protocol/openthread/config/sl_openthread_features_mtd_cert_config.h new file mode 100644 index 0000000000..34743db474 --- /dev/null +++ b/protocol/openthread/config/sl_openthread_features_mtd_cert_config.h @@ -0,0 +1,318 @@ +#ifndef _SL_OPENTHREAD_FEATURES_CONFIG_H +#define _SL_OPENTHREAD_FEATURES_CONFIG_H +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +// +// OpenThread Stack Configurations + +// Thread Stack Protocol Version +// +// Thread 1.1 +// Thread 1.2 +// Thread 1.3 +// Thread 1.2 and Thread 1.3 are compatible with Thread 1.1. +// Current Default: OT_THREAD_VERSION_1_3 +#ifndef OPENTHREAD_CONFIG_THREAD_VERSION +#define OPENTHREAD_CONFIG_THREAD_VERSION OT_THREAD_VERSION_1_3 +#endif +// + +#if (OPENTHREAD_CONFIG_THREAD_VERSION >= OT_THREAD_VERSION_1_2) +// The following features require at least Thread Stack Protocol Version 1.2 +// Backbone Router +#ifndef OPENTHREAD_CONFIG_BACKBONE_ROUTER_ENABLE +#define OPENTHREAD_CONFIG_BACKBONE_ROUTER_ENABLE 0 +#endif +// CSL Auto Synchronization using data polling +#ifndef OPENTHREAD_CONFIG_MAC_CSL_AUTO_SYNC_ENABLE +#define OPENTHREAD_CONFIG_MAC_CSL_AUTO_SYNC_ENABLE 1 +#endif +// CSL (Coordinated Sampled Listening) Debug +#ifndef OPENTHREAD_CONFIG_MAC_CSL_DEBUG_ENABLE +#define OPENTHREAD_CONFIG_MAC_CSL_DEBUG_ENABLE 0 +#endif +// CSL (Coordinated Sampled Listening) Receiver +#ifndef OPENTHREAD_CONFIG_MAC_CSL_RECEIVER_ENABLE +#define OPENTHREAD_CONFIG_MAC_CSL_RECEIVER_ENABLE 1 +#endif +// DUA (Domain Unicast Address) +#ifndef OPENTHREAD_CONFIG_DUA_ENABLE +#define OPENTHREAD_CONFIG_DUA_ENABLE 1 +#endif +// Link Metrics Initiator +#ifndef OPENTHREAD_CONFIG_MLE_LINK_METRICS_INITIATOR_ENABLE +#define OPENTHREAD_CONFIG_MLE_LINK_METRICS_INITIATOR_ENABLE 1 +#endif +// Link Metrics Subject +#ifndef OPENTHREAD_CONFIG_MLE_LINK_METRICS_SUBJECT_ENABLE +#define OPENTHREAD_CONFIG_MLE_LINK_METRICS_SUBJECT_ENABLE 0 +#endif +// Multicast Listener Registration +#ifndef OPENTHREAD_CONFIG_MLR_ENABLE +#define OPENTHREAD_CONFIG_MLR_ENABLE 1 +#endif +// DNS Client (Thread 1.3) +#ifndef OPENTHREAD_CONFIG_DNS_CLIENT_ENABLE +#define OPENTHREAD_CONFIG_DNS_CLIENT_ENABLE 1 +#endif +// DNS-SD Server (Thread 1.3) +#ifndef OPENTHREAD_CONFIG_DNSSD_SERVER_ENABLE +#define OPENTHREAD_CONFIG_DNSSD_SERVER_ENABLE 0 +#endif +// Service Registration Protocol (SRP) Client (Thread 1.3) +#ifndef OPENTHREAD_CONFIG_SRP_CLIENT_ENABLE +#define OPENTHREAD_CONFIG_SRP_CLIENT_ENABLE 1 +#endif +// Service Registration Protocol (SRP) Server (Thread 1.3) +#ifndef OPENTHREAD_CONFIG_SRP_SERVER_ENABLE +#define OPENTHREAD_CONFIG_SRP_SERVER_ENABLE 0 +#endif +// TCPlp (Low power TCP over OpenThread) (Thread 1.3) +#ifndef OPENTHREAD_CONFIG_TCP_ENABLE +#define OPENTHREAD_CONFIG_TCP_ENABLE 0 +#endif +// Thread over Infrastructure (Thread 1.3: NCP only) +#ifndef OPENTHREAD_CONFIG_RADIO_LINK_TREL_ENABLE +#define OPENTHREAD_CONFIG_RADIO_LINK_TREL_ENABLE 0 +#endif +// +#endif // OPENTHREAD_CONFIG_THREAD_VERSION >= OT_THREAD_VERSION_1_2 + +// Border Agent +#ifndef OPENTHREAD_CONFIG_BORDER_AGENT_ENABLE +#define OPENTHREAD_CONFIG_BORDER_AGENT_ENABLE 0 +#endif +// +// Border Router +#ifndef OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE +#define OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE 0 +#endif +// +// Channel Manager +#ifndef OPENTHREAD_CONFIG_CHANNEL_MANAGER_ENABLE +#define OPENTHREAD_CONFIG_CHANNEL_MANAGER_ENABLE 0 +#endif +// +// Channel Monitor +#ifndef OPENTHREAD_CONFIG_CHANNEL_MONITOR_ENABLE +#define OPENTHREAD_CONFIG_CHANNEL_MONITOR_ENABLE 0 +#endif +// +// Child Supervision +#ifndef OPENTHREAD_CONFIG_CHILD_SUPERVISION_ENABLE +#define OPENTHREAD_CONFIG_CHILD_SUPERVISION_ENABLE 0 +#endif +// +// Commissioner +#ifndef OPENTHREAD_CONFIG_COMMISSIONER_ENABLE +#define OPENTHREAD_CONFIG_COMMISSIONER_ENABLE 0 +#endif +// +// COAP API +#ifndef OPENTHREAD_CONFIG_COAP_API_ENABLE +#define OPENTHREAD_CONFIG_COAP_API_ENABLE 1 +#endif +// +// COAP Observe (RFC7641) API +#ifndef OPENTHREAD_CONFIG_COAP_OBSERVE_API_ENABLE +#define OPENTHREAD_CONFIG_COAP_OBSERVE_API_ENABLE 0 +#endif +// +// COAP Secure API +#ifndef OPENTHREAD_CONFIG_COAP_SECURE_API_ENABLE +#define OPENTHREAD_CONFIG_COAP_SECURE_API_ENABLE 0 +#endif +// +// DHCP6 Client +#ifndef OPENTHREAD_CONFIG_DHCP6_CLIENT_ENABLE +#define OPENTHREAD_CONFIG_DHCP6_CLIENT_ENABLE 1 +#endif +// +// DHCP6 Server +#ifndef OPENTHREAD_CONFIG_DHCP6_SERVER_ENABLE +#define OPENTHREAD_CONFIG_DHCP6_SERVER_ENABLE 0 +#endif +// +// Diagnostic +#ifndef OPENTHREAD_CONFIG_DIAG_ENABLE +#define OPENTHREAD_CONFIG_DIAG_ENABLE 0 +#endif +// +// ECDSA (Elliptic Curve Digital Signature Algorithm) (Required for Matter support) +#ifndef OPENTHREAD_CONFIG_ECDSA_ENABLE +#define OPENTHREAD_CONFIG_ECDSA_ENABLE 1 +#endif +// +// External Heap +#ifndef OPENTHREAD_CONFIG_HEAP_EXTERNAL_ENABLE +#define OPENTHREAD_CONFIG_HEAP_EXTERNAL_ENABLE 1 +#endif +// +// IPv6 Fragmentation +#ifndef OPENTHREAD_CONFIG_IP6_FRAGMENTATION_ENABLE +#define OPENTHREAD_CONFIG_IP6_FRAGMENTATION_ENABLE 0 +#endif +// +// Maximum number of IPv6 unicast addresses allowed to be externally added +#ifndef OPENTHREAD_CONFIG_IP6_MAX_EXT_UCAST_ADDRS +#define OPENTHREAD_CONFIG_IP6_MAX_EXT_UCAST_ADDRS 4 +#endif +// +// Maximum number of IPv6 multicast addresses allowed to be externally added +#ifndef OPENTHREAD_CONFIG_IP6_MAX_EXT_MCAST_ADDRS +#define OPENTHREAD_CONFIG_IP6_MAX_EXT_MCAST_ADDRS 4 +#endif +// +// Jam Detection +#ifndef OPENTHREAD_CONFIG_JAM_DETECTION_ENABLE +#define OPENTHREAD_CONFIG_JAM_DETECTION_ENABLE 0 +#endif +// +// Joiner +#ifndef OPENTHREAD_CONFIG_JOINER_ENABLE +#define OPENTHREAD_CONFIG_JOINER_ENABLE 1 +#endif +// +// Legacy Network +#ifndef OPENTHREAD_CONFIG_LEGACY_ENABLE +#define OPENTHREAD_CONFIG_LEGACY_ENABLE 0 +#endif +// +// Link Raw Service +#ifndef OPENTHREAD_CONFIG_LINK_RAW_ENABLE +#define OPENTHREAD_CONFIG_LINK_RAW_ENABLE 0 +#endif +// +// MAC Filter +#ifndef OPENTHREAD_CONFIG_MAC_FILTER_ENABLE +#define OPENTHREAD_CONFIG_MAC_FILTER_ENABLE 0 +#endif +// +// MLE Long Routes extension (experimental) +#ifndef OPENTHREAD_CONFIG_MLE_LONG_ROUTES_ENABLE +#define OPENTHREAD_CONFIG_MLE_LONG_ROUTES_ENABLE 0 +#endif +// +// MultiPAN RCP +#ifndef OPENTHREAD_CONFIG_MULTIPAN_RCP_ENABLE +#define OPENTHREAD_CONFIG_MULTIPAN_RCP_ENABLE 0 +#endif +// +// Multiple OpenThread Instances +#ifndef OPENTHREAD_CONFIG_MULTIPLE_INSTANCE_ENABLE +#define OPENTHREAD_CONFIG_MULTIPLE_INSTANCE_ENABLE 0 +#endif +// +// OTNS (OpenThread Network Simulator) +#ifndef OPENTHREAD_CONFIG_OTNS_ENABLE +#define OPENTHREAD_CONFIG_OTNS_ENABLE 0 +#endif +// +// Ping Sender Module +#ifndef OPENTHREAD_CONFIG_PING_SENDER_ENABLE +#define OPENTHREAD_CONFIG_PING_SENDER_ENABLE 1 +#endif +// +// Platform UDP +#ifndef OPENTHREAD_CONFIG_PLATFORM_UDP_ENABLE +#define OPENTHREAD_CONFIG_PLATFORM_UDP_ENABLE 0 +#endif +// +// Reference Device for Thread Test Harness +#ifndef OPENTHREAD_CONFIG_REFERENCE_DEVICE_ENABLE +#define OPENTHREAD_CONFIG_REFERENCE_DEVICE_ENABLE 0 +#endif +// +// Service Entries in Thread Network Data +#ifndef OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE +#define OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE 0 +#endif +// +// RAM (volatile-only storage) +#ifndef OPENTHREAD_SETTINGS_RAM +#define OPENTHREAD_SETTINGS_RAM 0 +#endif +// +// SLAAC Addresses +#ifndef OPENTHREAD_CONFIG_IP6_SLAAC_ENABLE +#define OPENTHREAD_CONFIG_IP6_SLAAC_ENABLE 1 +#endif +// +// SNTP Client +#ifndef OPENTHREAD_CONFIG_SNTP_CLIENT_ENABLE +#define OPENTHREAD_CONFIG_SNTP_CLIENT_ENABLE 0 +#endif +// +// TMF Network Diagnostics for MTD +#ifndef OPENTHREAD_CONFIG_TMF_NETWORK_DIAG_MTD_ENABLE +#define OPENTHREAD_CONFIG_TMF_NETWORK_DIAG_MTD_ENABLE 0 +#endif +// +// Time Synchronization Service +#define OPENTHREAD_CONFIG_TIME_SYNC_ENABLE 0 +// +// UDP Forward +#ifndef OPENTHREAD_CONFIG_UDP_FORWARD_ENABLE +#define OPENTHREAD_CONFIG_UDP_FORWARD_ENABLE 0 +#endif +// +// Enable Mac beacon payload parsing support +#ifndef OPENTHREAD_CONFIG_MAC_BEACON_PAYLOAD_PARSING_ENABLE +#define OPENTHREAD_CONFIG_MAC_BEACON_PAYLOAD_PARSING_ENABLE 1 +#endif +// +// +// Logging +// LOG_OUTPUT +// NONE +// APP +// PLATFORM_DEFINED +// Default: OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED +#ifndef OPENTHREAD_CONFIG_LOG_OUTPUT +#define OPENTHREAD_CONFIG_LOG_OUTPUT OPENTHREAD_CONFIG_LOG_OUTPUT_APP +#endif + +// DYNAMIC_LOG_LEVEL +#ifndef OPENTHREAD_CONFIG_LOG_LEVEL_DYNAMIC_ENABLE +#define OPENTHREAD_CONFIG_LOG_LEVEL_DYNAMIC_ENABLE 0 +#endif + +// Enable Logging +#define OPENTHREAD_FULL_LOGS_ENABLE 0 +#if OPENTHREAD_FULL_LOGS_ENABLE + +// Note: Enabling higher log levels, which include logging packet details, can cause delays which may result in join failures. +// LOG_LEVEL +// NONE +// CRIT +// WARN +// NOTE +// INFO +// DEBG +// Default: OT_LOG_LEVEL_DEBG +#ifndef OPENTHREAD_CONFIG_LOG_LEVEL +#define OPENTHREAD_CONFIG_LOG_LEVEL OT_LOG_LEVEL_DEBG +#endif +// CLI +#ifndef OPENTHREAD_CONFIG_LOG_CLI +#define OPENTHREAD_CONFIG_LOG_CLI 1 +#endif +// PKT_DUMP +#ifndef OPENTHREAD_CONFIG_LOG_PKT_DUMP +#define OPENTHREAD_CONFIG_LOG_PKT_DUMP 1 +#endif +// PLATFORM +#ifndef OPENTHREAD_CONFIG_LOG_PLATFORM +#define OPENTHREAD_CONFIG_LOG_PLATFORM 1 +#endif +// PREPEND_LEVEL +#ifndef OPENTHREAD_CONFIG_LOG_PREPEND_LEVEL +#define OPENTHREAD_CONFIG_LOG_PREPEND_LEVEL 1 +#endif + +#endif +// +// +// + +// <<< end of configuration section >>> +#endif // _SL_OPENTHREAD_FEATURES_CONFIG_H diff --git a/protocol/openthread/config/sl_openthread_generic_config.h b/protocol/openthread/config/sl_openthread_generic_config.h index 7e2c8a0db6..098bfa7369 100644 --- a/protocol/openthread/config/sl_openthread_generic_config.h +++ b/protocol/openthread/config/sl_openthread_generic_config.h @@ -68,7 +68,7 @@ #define PACKAGE_NAME "SL-OPENTHREAD" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "SL-OPENTHREAD/2.1.0.0_GitHub-8f92d2dc8" +#define PACKAGE_STRING "SL-OPENTHREAD/2.1.1.0_GitHub-2ce3d3bf0" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "openthread" @@ -80,13 +80,13 @@ * Note: When adding the label below with OpenThread version, please make * sure it is a valid GitHub version. Avoid merge or local commit hashes. */ -#define PACKAGE_VERSION "2.1.0.0_GitHub-8f92d2dc8" +#define PACKAGE_VERSION "2.1.1.0_GitHub-2ce3d3bf0" /* Define to 1 if you have the ANSI C header files. */ #define STDC_HEADERS 1 /* Version number of package */ -#define VERSION "2.1.0.0_GitHub-8f92d2dc8" +#define VERSION "2.1.1.0_GitHub-2ce3d3bf0" /* Define WORDS_BIGENDIAN to 1 if your processor stores words with the most significant byte first (like Motorola and SPARC, unlike Intel). */ diff --git a/protocol/openthread/config/sl_openthread_reference_device_config.h b/protocol/openthread/config/sl_openthread_reference_device_config.h new file mode 100644 index 0000000000..d8e073ff01 --- /dev/null +++ b/protocol/openthread/config/sl_openthread_reference_device_config.h @@ -0,0 +1,318 @@ +#ifndef _SL_OPENTHREAD_FEATURES_CONFIG_H +#define _SL_OPENTHREAD_FEATURES_CONFIG_H +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +// +// OpenThread Stack Configurations + +// Thread Stack Protocol Version +// +// Thread 1.1 +// Thread 1.2 +// Thread 1.3 +// Thread 1.2 and Thread 1.3 are compatible with Thread 1.1. +// Current Default: OT_THREAD_VERSION_1_3 +#ifndef OPENTHREAD_CONFIG_THREAD_VERSION +#define OPENTHREAD_CONFIG_THREAD_VERSION OT_THREAD_VERSION_1_3 +#endif +// + +#if (OPENTHREAD_CONFIG_THREAD_VERSION >= OT_THREAD_VERSION_1_2) +// The following features require at least Thread Stack Protocol Version 1.2 +// Backbone Router +#ifndef OPENTHREAD_CONFIG_BACKBONE_ROUTER_ENABLE +#define OPENTHREAD_CONFIG_BACKBONE_ROUTER_ENABLE 1 +#endif +// CSL Auto Synchronization using data polling +#ifndef OPENTHREAD_CONFIG_MAC_CSL_AUTO_SYNC_ENABLE +#define OPENTHREAD_CONFIG_MAC_CSL_AUTO_SYNC_ENABLE 1 +#endif +// CSL (Coordinated Sampled Listening) Debug +#ifndef OPENTHREAD_CONFIG_MAC_CSL_DEBUG_ENABLE +#define OPENTHREAD_CONFIG_MAC_CSL_DEBUG_ENABLE 0 +#endif +// CSL (Coordinated Sampled Listening) Receiver +#ifndef OPENTHREAD_CONFIG_MAC_CSL_RECEIVER_ENABLE +#define OPENTHREAD_CONFIG_MAC_CSL_RECEIVER_ENABLE 1 +#endif +// DUA (Domain Unicast Address) +#ifndef OPENTHREAD_CONFIG_DUA_ENABLE +#define OPENTHREAD_CONFIG_DUA_ENABLE 1 +#endif +// Link Metrics Initiator +#ifndef OPENTHREAD_CONFIG_MLE_LINK_METRICS_INITIATOR_ENABLE +#define OPENTHREAD_CONFIG_MLE_LINK_METRICS_INITIATOR_ENABLE 1 +#endif +// Link Metrics Subject +#ifndef OPENTHREAD_CONFIG_MLE_LINK_METRICS_SUBJECT_ENABLE +#define OPENTHREAD_CONFIG_MLE_LINK_METRICS_SUBJECT_ENABLE 1 +#endif +// Multicast Listener Registration +#ifndef OPENTHREAD_CONFIG_MLR_ENABLE +#define OPENTHREAD_CONFIG_MLR_ENABLE 1 +#endif +// DNS Client (Thread 1.3) +#ifndef OPENTHREAD_CONFIG_DNS_CLIENT_ENABLE +#define OPENTHREAD_CONFIG_DNS_CLIENT_ENABLE 1 +#endif +// DNS-SD Server (Thread 1.3) +#ifndef OPENTHREAD_CONFIG_DNSSD_SERVER_ENABLE +#define OPENTHREAD_CONFIG_DNSSD_SERVER_ENABLE 1 +#endif +// Service Registration Protocol (SRP) Client (Thread 1.3) +#ifndef OPENTHREAD_CONFIG_SRP_CLIENT_ENABLE +#define OPENTHREAD_CONFIG_SRP_CLIENT_ENABLE 1 +#endif +// Service Registration Protocol (SRP) Server (Thread 1.3) +#ifndef OPENTHREAD_CONFIG_SRP_SERVER_ENABLE +#define OPENTHREAD_CONFIG_SRP_SERVER_ENABLE 1 +#endif +// TCPlp (Low power TCP over OpenThread) (Thread 1.3) +#ifndef OPENTHREAD_CONFIG_TCP_ENABLE +#define OPENTHREAD_CONFIG_TCP_ENABLE 0 +#endif +// Thread over Infrastructure (Thread 1.3: NCP only) +#ifndef OPENTHREAD_CONFIG_RADIO_LINK_TREL_ENABLE +#define OPENTHREAD_CONFIG_RADIO_LINK_TREL_ENABLE 0 +#endif +// +#endif // OPENTHREAD_CONFIG_THREAD_VERSION >= OT_THREAD_VERSION_1_2 + +// Border Agent +#ifndef OPENTHREAD_CONFIG_BORDER_AGENT_ENABLE +#define OPENTHREAD_CONFIG_BORDER_AGENT_ENABLE 0 +#endif +// +// Border Router +#ifndef OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE +#define OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE 1 +#endif +// +// Channel Manager +#ifndef OPENTHREAD_CONFIG_CHANNEL_MANAGER_ENABLE +#define OPENTHREAD_CONFIG_CHANNEL_MANAGER_ENABLE 0 +#endif +// +// Channel Monitor +#ifndef OPENTHREAD_CONFIG_CHANNEL_MONITOR_ENABLE +#define OPENTHREAD_CONFIG_CHANNEL_MONITOR_ENABLE 0 +#endif +// +// Child Supervision +#ifndef OPENTHREAD_CONFIG_CHILD_SUPERVISION_ENABLE +#define OPENTHREAD_CONFIG_CHILD_SUPERVISION_ENABLE 0 +#endif +// +// Commissioner +#ifndef OPENTHREAD_CONFIG_COMMISSIONER_ENABLE +#define OPENTHREAD_CONFIG_COMMISSIONER_ENABLE 1 +#endif +// +// COAP API +#ifndef OPENTHREAD_CONFIG_COAP_API_ENABLE +#define OPENTHREAD_CONFIG_COAP_API_ENABLE 1 +#endif +// +// COAP Observe (RFC7641) API +#ifndef OPENTHREAD_CONFIG_COAP_OBSERVE_API_ENABLE +#define OPENTHREAD_CONFIG_COAP_OBSERVE_API_ENABLE 1 +#endif +// +// COAP Secure API +#ifndef OPENTHREAD_CONFIG_COAP_SECURE_API_ENABLE +#define OPENTHREAD_CONFIG_COAP_SECURE_API_ENABLE 1 +#endif +// +// DHCP6 Client +#ifndef OPENTHREAD_CONFIG_DHCP6_CLIENT_ENABLE +#define OPENTHREAD_CONFIG_DHCP6_CLIENT_ENABLE 1 +#endif +// +// DHCP6 Server +#ifndef OPENTHREAD_CONFIG_DHCP6_SERVER_ENABLE +#define OPENTHREAD_CONFIG_DHCP6_SERVER_ENABLE 1 +#endif +// +// Diagnostic +#ifndef OPENTHREAD_CONFIG_DIAG_ENABLE +#define OPENTHREAD_CONFIG_DIAG_ENABLE 0 +#endif +// +// ECDSA (Elliptic Curve Digital Signature Algorithm) (Required for Matter support) +#ifndef OPENTHREAD_CONFIG_ECDSA_ENABLE +#define OPENTHREAD_CONFIG_ECDSA_ENABLE 1 +#endif +// +// External Heap +#ifndef OPENTHREAD_CONFIG_HEAP_EXTERNAL_ENABLE +#define OPENTHREAD_CONFIG_HEAP_EXTERNAL_ENABLE 1 +#endif +// +// IPv6 Fragmentation +#ifndef OPENTHREAD_CONFIG_IP6_FRAGMENTATION_ENABLE +#define OPENTHREAD_CONFIG_IP6_FRAGMENTATION_ENABLE 0 +#endif +// +// Maximum number of IPv6 unicast addresses allowed to be externally added +#ifndef OPENTHREAD_CONFIG_IP6_MAX_EXT_UCAST_ADDRS +#define OPENTHREAD_CONFIG_IP6_MAX_EXT_UCAST_ADDRS 4 +#endif +// +// Maximum number of IPv6 multicast addresses allowed to be externally added +#ifndef OPENTHREAD_CONFIG_IP6_MAX_EXT_MCAST_ADDRS +#define OPENTHREAD_CONFIG_IP6_MAX_EXT_MCAST_ADDRS 4 +#endif +// +// Jam Detection +#ifndef OPENTHREAD_CONFIG_JAM_DETECTION_ENABLE +#define OPENTHREAD_CONFIG_JAM_DETECTION_ENABLE 0 +#endif +// +// Joiner +#ifndef OPENTHREAD_CONFIG_JOINER_ENABLE +#define OPENTHREAD_CONFIG_JOINER_ENABLE 1 +#endif +// +// Legacy Network +#ifndef OPENTHREAD_CONFIG_LEGACY_ENABLE +#define OPENTHREAD_CONFIG_LEGACY_ENABLE 0 +#endif +// +// Link Raw Service +#ifndef OPENTHREAD_CONFIG_LINK_RAW_ENABLE +#define OPENTHREAD_CONFIG_LINK_RAW_ENABLE 0 +#endif +// +// MAC Filter +#ifndef OPENTHREAD_CONFIG_MAC_FILTER_ENABLE +#define OPENTHREAD_CONFIG_MAC_FILTER_ENABLE 1 +#endif +// +// MLE Long Routes extension (experimental) +#ifndef OPENTHREAD_CONFIG_MLE_LONG_ROUTES_ENABLE +#define OPENTHREAD_CONFIG_MLE_LONG_ROUTES_ENABLE 0 +#endif +// +// MultiPAN RCP +#ifndef OPENTHREAD_CONFIG_MULTIPAN_RCP_ENABLE +#define OPENTHREAD_CONFIG_MULTIPAN_RCP_ENABLE 0 +#endif +// +// Multiple OpenThread Instances +#ifndef OPENTHREAD_CONFIG_MULTIPLE_INSTANCE_ENABLE +#define OPENTHREAD_CONFIG_MULTIPLE_INSTANCE_ENABLE 0 +#endif +// +// OTNS (OpenThread Network Simulator) +#ifndef OPENTHREAD_CONFIG_OTNS_ENABLE +#define OPENTHREAD_CONFIG_OTNS_ENABLE 0 +#endif +// +// Ping Sender Module +#ifndef OPENTHREAD_CONFIG_PING_SENDER_ENABLE +#define OPENTHREAD_CONFIG_PING_SENDER_ENABLE 1 +#endif +// +// Platform UDP +#ifndef OPENTHREAD_CONFIG_PLATFORM_UDP_ENABLE +#define OPENTHREAD_CONFIG_PLATFORM_UDP_ENABLE 0 +#endif +// +// Reference Device for Thread Test Harness +#ifndef OPENTHREAD_CONFIG_REFERENCE_DEVICE_ENABLE +#define OPENTHREAD_CONFIG_REFERENCE_DEVICE_ENABLE 1 +#endif +// +// Service Entries in Thread Network Data +#ifndef OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE +#define OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE 1 +#endif +// +// RAM (volatile-only storage) +#ifndef OPENTHREAD_SETTINGS_RAM +#define OPENTHREAD_SETTINGS_RAM 0 +#endif +// +// SLAAC Addresses +#ifndef OPENTHREAD_CONFIG_IP6_SLAAC_ENABLE +#define OPENTHREAD_CONFIG_IP6_SLAAC_ENABLE 1 +#endif +// +// SNTP Client +#ifndef OPENTHREAD_CONFIG_SNTP_CLIENT_ENABLE +#define OPENTHREAD_CONFIG_SNTP_CLIENT_ENABLE 0 +#endif +// +// TMF Network Diagnostics for MTD +#ifndef OPENTHREAD_CONFIG_TMF_NETWORK_DIAG_MTD_ENABLE +#define OPENTHREAD_CONFIG_TMF_NETWORK_DIAG_MTD_ENABLE 0 +#endif +// +// Time Synchronization Service +#define OPENTHREAD_CONFIG_TIME_SYNC_ENABLE 0 +// +// UDP Forward +#ifndef OPENTHREAD_CONFIG_UDP_FORWARD_ENABLE +#define OPENTHREAD_CONFIG_UDP_FORWARD_ENABLE 0 +#endif +// +// Enable Mac beacon payload parsing support +#ifndef OPENTHREAD_CONFIG_MAC_BEACON_PAYLOAD_PARSING_ENABLE +#define OPENTHREAD_CONFIG_MAC_BEACON_PAYLOAD_PARSING_ENABLE 1 +#endif +// +// +// Logging +// LOG_OUTPUT +// NONE +// APP +// PLATFORM_DEFINED +// Default: OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED +#ifndef OPENTHREAD_CONFIG_LOG_OUTPUT +#define OPENTHREAD_CONFIG_LOG_OUTPUT OPENTHREAD_CONFIG_LOG_OUTPUT_APP +#endif + +// DYNAMIC_LOG_LEVEL +#ifndef OPENTHREAD_CONFIG_LOG_LEVEL_DYNAMIC_ENABLE +#define OPENTHREAD_CONFIG_LOG_LEVEL_DYNAMIC_ENABLE 0 +#endif + +// Enable Logging +#define OPENTHREAD_FULL_LOGS_ENABLE 0 +#if OPENTHREAD_FULL_LOGS_ENABLE + +// Note: Enabling higher log levels, which include logging packet details, can cause delays which may result in join failures. +// LOG_LEVEL +// NONE +// CRIT +// WARN +// NOTE +// INFO +// DEBG +// Default: OT_LOG_LEVEL_DEBG +#ifndef OPENTHREAD_CONFIG_LOG_LEVEL +#define OPENTHREAD_CONFIG_LOG_LEVEL OT_LOG_LEVEL_DEBG +#endif +// CLI +#ifndef OPENTHREAD_CONFIG_LOG_CLI +#define OPENTHREAD_CONFIG_LOG_CLI 1 +#endif +// PKT_DUMP +#ifndef OPENTHREAD_CONFIG_LOG_PKT_DUMP +#define OPENTHREAD_CONFIG_LOG_PKT_DUMP 1 +#endif +// PLATFORM +#ifndef OPENTHREAD_CONFIG_LOG_PLATFORM +#define OPENTHREAD_CONFIG_LOG_PLATFORM 1 +#endif +// PREPEND_LEVEL +#ifndef OPENTHREAD_CONFIG_LOG_PREPEND_LEVEL +#define OPENTHREAD_CONFIG_LOG_PREPEND_LEVEL 1 +#endif + +#endif +// +// +// + +// <<< end of configuration section >>> +#endif // _SL_OPENTHREAD_FEATURES_CONFIG_H diff --git a/protocol/openthread/documentation/release-highlights.txt b/protocol/openthread/documentation/release-highlights.txt index d497c30ccf..0a0a6919d2 100644 --- a/protocol/openthread/documentation/release-highlights.txt +++ b/protocol/openthread/documentation/release-highlights.txt @@ -1,6 +1,3 @@ -Silicon Labs OpenThread SDK 2.1.0.0 -- Alpha SPI support for OpenThread RCP without CPC -- Thread 1.2 and 1.3 support for OpenThread -- Updated GCC compiler version to 10.3.1 -- Alpha Concurrent Multiprotocol Zigbee in NCP mode and Open-Thread in RCP mode -- Alpha Dynamic Multiprotocol Blue-tooth and multi-PAN 802.15.4 in RCP mode +Silicon Labs OpenThread SDK 2.1.1.0 +- Targeted quality improvements and bug fixes + diff --git a/protocol/openthread/documentation/slOpenthread_docContent.xml b/protocol/openthread/documentation/slOpenthread_docContent.xml index e20464556c..84fccd219a 100644 --- a/protocol/openthread/documentation/slOpenthread_docContent.xml +++ b/protocol/openthread/documentation/slOpenthread_docContent.xml @@ -1,16 +1,8 @@ - - - - - - + + + @@ -88,6 +84,10 @@ + + + - - - - - - - This multiprotocol radio co-processor (RCP) application supports running OpenThread, Zigbee, and Bluetooth stacks simultaneously on a host processor. It uses concurrent multiprotocol (CMP) / multi-PAN functionality to run the 802.15.4 networks simultaneously on the same channel, and dynamic multiprotocol (DMP) to run the Bluetooth Link Layer simultaneously. The host stacks and the RCP communicate using the Co-Processor Communication protocol (CPC), which acts as a protocol multiplexer and serial transport layer. The host applications connect to the CPC daemon, which in turn connects to the EFR via a SPI link. Refer to *AN1333: Running Zigbee, OpenThread, and Bluetooth Concurrently on a Linux Host with a Multiprotocol Co-processor* for more information on running the multiprotocol RCP with different host applications. + + + + + + + - - - - - - - This multiprotocol radio co-processor (RCP) application supports running OpenThread, Zigbee, and Bluetooth stacks simultaneously on a host processor. It uses concurrent multiprotocol (CMP) / multi-PAN functionality to run the 802.15.4 networks simultaneously on the same channel, and dynamic multiprotocol (DMP) to run the Bluetooth Link Layer simultaneously. The host stacks and the RCP communicate using the Co-Processor Communication protocol (CPC), which acts as a protocol multiplexer and serial transport layer. The host applications connect to the CPC daemon, which in turn connects to the EFR via a SPI link. Refer to *AN1333: Running Zigbee, OpenThread, and Bluetooth Concurrently on a Linux Host with a Multiprotocol Co-processor* for more information on running the multiprotocol RCP with different host applications. + + + + + + + - - - - - - - This multiprotocol radio co-processor (RCP) application supports running OpenThread, Zigbee, and Bluetooth stacks simultaneously on a host processor. It uses concurrent multiprotocol (CMP) / multi-PAN functionality to run the 802.15.4 networks simultaneously on the same channel, and dynamic multiprotocol (DMP) to run the Bluetooth Link Layer simultaneously. The host stacks and the RCP communicate using the Co-Processor Communication protocol (CPC), which acts as a protocol multiplexer and serial transport layer. The host applications connect to the CPC daemon, which in turn connects to the EFR via a SPI link. Refer to *AN1333: Running Zigbee, OpenThread, and Bluetooth Concurrently on a Linux Host with a Multiprotocol Co-processor* for more information on running the multiprotocol RCP with different host applications. + + + + + + + - - - - - - - This multiprotocol radio co-processor (RCP) application supports running OpenThread, Zigbee, and Bluetooth stacks simultaneously on a host processor. It uses concurrent multiprotocol (CMP) / multi-PAN functionality to run the 802.15.4 networks simultaneously on the same channel, and dynamic multiprotocol (DMP) to run the Bluetooth Link Layer simultaneously. The host stacks and the RCP communicate using the Co-Processor Communication protocol (CPC), which acts as a protocol multiplexer and serial transport layer. The host applications connect to the CPC daemon, which in turn connects to the EFR via a SPI link. Refer to *AN1333: Running Zigbee, OpenThread, and Bluetooth Concurrently on a Linux Host with a Multiprotocol Co-processor* for more information on running the multiprotocol RCP with different host applications. + + + + + + + - - - - - - - This multiprotocol radio co-processor (RCP) application supports running OpenThread, Zigbee, and Bluetooth stacks simultaneously on a host processor. It uses concurrent multiprotocol (CMP) / multi-PAN functionality to run the 802.15.4 networks simultaneously on the same channel, and dynamic multiprotocol (DMP) to run the Bluetooth Link Layer simultaneously. The host stacks and the RCP communicate using the Co-Processor Communication protocol (CPC), which acts as a protocol multiplexer and serial transport layer. The host applications connect to the CPC daemon, which in turn connects to the EFR via a SPI link. Refer to *AN1333: Running Zigbee, OpenThread, and Bluetooth Concurrently on a Linux Host with a Multiprotocol Co-processor* for more information on running the multiprotocol RCP with different host applications. + + + + + + + - - - - - - - This multiprotocol radio co-processor (RCP) application supports running OpenThread, Zigbee, and Bluetooth stacks simultaneously on a host processor. It uses concurrent multiprotocol (CMP) / multi-PAN functionality to run the 802.15.4 networks simultaneously on the same channel, and dynamic multiprotocol (DMP) to run the Bluetooth Link Layer simultaneously. The host stacks and the RCP communicate using the Co-Processor Communication protocol (CPC), which acts as a protocol multiplexer and serial transport layer. The host applications connect to the CPC daemon, which in turn connects to the EFR via a UART link. Refer to *AN1333: Running Zigbee, OpenThread, and Bluetooth Concurrently on a Linux Host with a Multiprotocol Co-processor* for more information on running the multiprotocol RCP with different host applications. + + + + + + + - - - - - - - This multiprotocol radio co-processor (RCP) application supports running OpenThread, Zigbee, and Bluetooth stacks simultaneously on a host processor. It uses concurrent multiprotocol (CMP) / multi-PAN functionality to run the 802.15.4 networks simultaneously on the same channel, and dynamic multiprotocol (DMP) to run the Bluetooth Link Layer simultaneously. The host stacks and the RCP communicate using the Co-Processor Communication protocol (CPC), which acts as a protocol multiplexer and serial transport layer. The host applications connect to the CPC daemon, which in turn connects to the EFR via a UART link. Refer to *AN1333: Running Zigbee, OpenThread, and Bluetooth Concurrently on a Linux Host with a Multiprotocol Co-processor* for more information on running the multiprotocol RCP with different host applications. + + + + + + + - - - - - - - This multiprotocol radio co-processor (RCP) application supports running OpenThread, Zigbee, and Bluetooth stacks simultaneously on a host processor. It uses concurrent multiprotocol (CMP) / multi-PAN functionality to run the 802.15.4 networks simultaneously on the same channel, and dynamic multiprotocol (DMP) to run the Bluetooth Link Layer simultaneously. The host stacks and the RCP communicate using the Co-Processor Communication protocol (CPC), which acts as a protocol multiplexer and serial transport layer. The host applications connect to the CPC daemon, which in turn connects to the EFR via a UART link. Refer to *AN1333: Running Zigbee, OpenThread, and Bluetooth Concurrently on a Linux Host with a Multiprotocol Co-processor* for more information on running the multiprotocol RCP with different host applications. + + + + + + + - - - - - - - This multiprotocol radio co-processor (RCP) application supports running OpenThread, Zigbee, and Bluetooth stacks simultaneously on a host processor. It uses concurrent multiprotocol (CMP) / multi-PAN functionality to run the 802.15.4 networks simultaneously on the same channel, and dynamic multiprotocol (DMP) to run the Bluetooth Link Layer simultaneously. The host stacks and the RCP communicate using the Co-Processor Communication protocol (CPC), which acts as a protocol multiplexer and serial transport layer. The host applications connect to the CPC daemon, which in turn connects to the EFR via a UART link. Refer to *AN1333: Running Zigbee, OpenThread, and Bluetooth Concurrently on a Linux Host with a Multiprotocol Co-processor* for more information on running the multiprotocol RCP with different host applications. + + + + + + + - - - - - - - This multiprotocol radio co-processor (RCP) application supports running OpenThread, Zigbee, and Bluetooth stacks simultaneously on a host processor. It uses concurrent multiprotocol (CMP) / multi-PAN functionality to run the 802.15.4 networks simultaneously on the same channel, and dynamic multiprotocol (DMP) to run the Bluetooth Link Layer simultaneously. The host stacks and the RCP communicate using the Co-Processor Communication protocol (CPC), which acts as a protocol multiplexer and serial transport layer. The host applications connect to the CPC daemon, which in turn connects to the EFR via a UART link. Refer to *AN1333: Running Zigbee, OpenThread, and Bluetooth Concurrently on a Linux Host with a Multiprotocol Co-processor* for more information on running the multiprotocol RCP with different host applications. + + + + + + + diff --git a/protocol/openthread/openthread_alpha_templates.xml b/protocol/openthread/openthread_alpha_templates.xml index 6069c8cce2..4d252d0539 100644 --- a/protocol/openthread/openthread_alpha_templates.xml +++ b/protocol/openthread/openthread_alpha_templates.xml @@ -6,7 +6,7 @@ - + @@ -21,7 +21,7 @@ - + diff --git a/protocol/openthread/openthread_production_demos.xml b/protocol/openthread/openthread_production_demos.xml index c5f22bfaa9..7f1aa77785 100644 --- a/protocol/openthread/openthread_production_demos.xml +++ b/protocol/openthread/openthread_production_demos.xml @@ -1,575 +1,575 @@ - - - - - - - This multiprotocol radio co-processor (RCP) application supports running OpenThread and Zigbee stacks simultaneously on a host processor. It uses concurrent multiprotocol (CMP) / multi-PAN functionality to run the 802.15.4 networks simultaneously on the same channel. The host stacks and the RCP communicate using the Co-Processor Communication protocol (CPC), which acts as a protocol multiplexer and serial transport layer. The host applications connect to the CPC daemon, which in turn connects to the EFR via a SPI link. Refer to *AN1333: Running Zigbee, OpenThread, and Bluetooth Concurrently on a Linux Host with a Multiprotocol Co-processor* for more information on running the multiprotocol RCP with different host applications. + + + + + + + - - - - - - - This multiprotocol radio co-processor (RCP) application supports running OpenThread and Zigbee stacks simultaneously on a host processor. It uses concurrent multiprotocol (CMP) / multi-PAN functionality to run the 802.15.4 networks simultaneously on the same channel. The host stacks and the RCP communicate using the Co-Processor Communication protocol (CPC), which acts as a protocol multiplexer and serial transport layer. The host applications connect to the CPC daemon, which in turn connects to the EFR via a SPI link. Refer to *AN1333: Running Zigbee, OpenThread, and Bluetooth Concurrently on a Linux Host with a Multiprotocol Co-processor* for more information on running the multiprotocol RCP with different host applications. + + + + + + + - - - - - - - This multiprotocol radio co-processor (RCP) application supports running OpenThread and Zigbee stacks simultaneously on a host processor. It uses concurrent multiprotocol (CMP) / multi-PAN functionality to run the 802.15.4 networks simultaneously on the same channel. The host stacks and the RCP communicate using the Co-Processor Communication protocol (CPC), which acts as a protocol multiplexer and serial transport layer. The host applications connect to the CPC daemon, which in turn connects to the EFR via a SPI link. Refer to *AN1333: Running Zigbee, OpenThread, and Bluetooth Concurrently on a Linux Host with a Multiprotocol Co-processor* for more information on running the multiprotocol RCP with different host applications. + + + + + + + - - - - - - - This multiprotocol radio co-processor (RCP) application supports running OpenThread and Zigbee stacks simultaneously on a host processor. It uses concurrent multiprotocol (CMP) / multi-PAN functionality to run the 802.15.4 networks simultaneously on the same channel. The host stacks and the RCP communicate using the Co-Processor Communication protocol (CPC), which acts as a protocol multiplexer and serial transport layer. The host applications connect to the CPC daemon, which in turn connects to the EFR via a SPI link. Refer to *AN1333: Running Zigbee, OpenThread, and Bluetooth Concurrently on a Linux Host with a Multiprotocol Co-processor* for more information on running the multiprotocol RCP with different host applications. + + + + + + + - - - - - - - This multiprotocol radio co-processor (RCP) application supports running OpenThread and Zigbee stacks simultaneously on a host processor. It uses concurrent multiprotocol (CMP) / multi-PAN functionality to run the 802.15.4 networks simultaneously on the same channel. The host stacks and the RCP communicate using the Co-Processor Communication protocol (CPC), which acts as a protocol multiplexer and serial transport layer. The host applications connect to the CPC daemon, which in turn connects to the EFR via a SPI link. Refer to *AN1333: Running Zigbee, OpenThread, and Bluetooth Concurrently on a Linux Host with a Multiprotocol Co-processor* for more information on running the multiprotocol RCP with different host applications. + + + + + + + - - - - - - - This multiprotocol radio co-processor (RCP) application supports running OpenThread and Zigbee stacks simultaneously on a host processor. It uses concurrent multiprotocol (CMP) / multi-PAN functionality to run the 802.15.4 networks simultaneously on the same channel. The host stacks and the RCP communicate using the Co-Processor Communication protocol (CPC), which acts as a protocol multiplexer and serial transport layer. The host applications connect to the CPC daemon, which in turn connects to the EFR via a SPI link. Refer to *AN1333: Running Zigbee, OpenThread, and Bluetooth Concurrently on a Linux Host with a Multiprotocol Co-processor* for more information on running the multiprotocol RCP with different host applications. + + + + + + + - - - - - - - This multiprotocol radio co-processor (RCP) application supports running OpenThread and Zigbee stacks simultaneously on a host processor. It uses concurrent multiprotocol (CMP) / multi-PAN functionality to run the 802.15.4 networks simultaneously on the same channel. The host stacks and the RCP communicate using the Co-Processor Communication protocol (CPC), which acts as a protocol multiplexer and serial transport layer. The host applications connect to the CPC daemon, which in turn connects to the EFR via a UART link. Refer to *AN1333: Running Zigbee, OpenThread, and Bluetooth Concurrently on a Linux Host with a Multiprotocol Co-processor* for more information on running the multiprotocol RCP with different host applications. + + + + + + + - - - - - - - This multiprotocol radio co-processor (RCP) application supports running OpenThread and Zigbee stacks simultaneously on a host processor. It uses concurrent multiprotocol (CMP) / multi-PAN functionality to run the 802.15.4 networks simultaneously on the same channel. The host stacks and the RCP communicate using the Co-Processor Communication protocol (CPC), which acts as a protocol multiplexer and serial transport layer. The host applications connect to the CPC daemon, which in turn connects to the EFR via a UART link. Refer to *AN1333: Running Zigbee, OpenThread, and Bluetooth Concurrently on a Linux Host with a Multiprotocol Co-processor* for more information on running the multiprotocol RCP with different host applications. + + + + + + + - - - - - - - This multiprotocol radio co-processor (RCP) application supports running OpenThread and Zigbee stacks simultaneously on a host processor. It uses concurrent multiprotocol (CMP) / multi-PAN functionality to run the 802.15.4 networks simultaneously on the same channel. The host stacks and the RCP communicate using the Co-Processor Communication protocol (CPC), which acts as a protocol multiplexer and serial transport layer. The host applications connect to the CPC daemon, which in turn connects to the EFR via a UART link. Refer to *AN1333: Running Zigbee, OpenThread, and Bluetooth Concurrently on a Linux Host with a Multiprotocol Co-processor* for more information on running the multiprotocol RCP with different host applications. + + + + + + + - - - - - - - This multiprotocol radio co-processor (RCP) application supports running OpenThread and Zigbee stacks simultaneously on a host processor. It uses concurrent multiprotocol (CMP) / multi-PAN functionality to run the 802.15.4 networks simultaneously on the same channel. The host stacks and the RCP communicate using the Co-Processor Communication protocol (CPC), which acts as a protocol multiplexer and serial transport layer. The host applications connect to the CPC daemon, which in turn connects to the EFR via a UART link. Refer to *AN1333: Running Zigbee, OpenThread, and Bluetooth Concurrently on a Linux Host with a Multiprotocol Co-processor* for more information on running the multiprotocol RCP with different host applications. + + + + + + + - - - - - - - This multiprotocol radio co-processor (RCP) application supports running OpenThread and Zigbee stacks simultaneously on a host processor. It uses concurrent multiprotocol (CMP) / multi-PAN functionality to run the 802.15.4 networks simultaneously on the same channel. The host stacks and the RCP communicate using the Co-Processor Communication protocol (CPC), which acts as a protocol multiplexer and serial transport layer. The host applications connect to the CPC daemon, which in turn connects to the EFR via a UART link. Refer to *AN1333: Running Zigbee, OpenThread, and Bluetooth Concurrently on a Linux Host with a Multiprotocol Co-processor* for more information on running the multiprotocol RCP with different host applications. + + + + + + + - - - - - - - This multiprotocol radio co-processor (RCP) application supports running OpenThread and Zigbee stacks simultaneously on a host processor. It uses concurrent multiprotocol (CMP) / multi-PAN functionality to run the 802.15.4 networks simultaneously on the same channel. The host stacks and the RCP communicate using the Co-Processor Communication protocol (CPC), which acts as a protocol multiplexer and serial transport layer. The host applications connect to the CPC daemon, which in turn connects to the EFR via a UART link. Refer to *AN1333: Running Zigbee, OpenThread, and Bluetooth Concurrently on a Linux Host with a Multiprotocol Co-processor* for more information on running the multiprotocol RCP with different host applications. + + + + + + + - - - - - - - This is a simple OpenThread Full Thread Device NCP application. This is equivalent to the ot-ncp-ftd application in the OpenThread GitHub repo. + + + + + + + - - - - - - - This is a simple OpenThread Full Thread Device NCP application. This is equivalent to the ot-ncp-ftd application in the OpenThread GitHub repo. + + + + + + + - - - - - - - This is a simple OpenThread Full Thread Device NCP application. This is equivalent to the ot-ncp-ftd application in the OpenThread GitHub repo. + + + + + + + - - - - - - - This is a simple OpenThread Full Thread Device NCP application. This is equivalent to the ot-ncp-ftd application in the OpenThread GitHub repo. + + + + + + + - - - - - - - This is a simple OpenThread Full Thread Device NCP application. This is equivalent to the ot-ncp-ftd application in the OpenThread GitHub repo. + + + + + + + - - - - - - - This is a simple OpenThread Minimal Thread Device NCP application. This is equivalent to the ot-ncp-mtd application in the OpenThread GitHub repo. + + + + + + + - - - - - - - This is a simple OpenThread Minimal Thread Device NCP application. This is equivalent to the ot-ncp-mtd application in the OpenThread GitHub repo. + + + + + + + - - - - - - - This is a simple OpenThread Minimal Thread Device NCP application. This is equivalent to the ot-ncp-mtd application in the OpenThread GitHub repo. + + + + + + + - - - - - - - This is a simple OpenThread Minimal Thread Device NCP application. This is equivalent to the ot-ncp-mtd application in the OpenThread GitHub repo. + + + + + + + - - - - - - - This is a simple OpenThread Minimal Thread Device NCP application. This is equivalent to the ot-ncp-mtd application in the OpenThread GitHub repo. + + + + + + + - - - - - - - This is a simple OpenThread RCP application. This is equivalent to the ot-rcp application in the OpenThread GitHub repo. + + + + + + + - - - - - - - This is a simple OpenThread RCP application. This is equivalent to the ot-rcp application in the OpenThread GitHub repo. + + + + + + + - - - - - - - This is a simple OpenThread RCP application. This is equivalent to the ot-rcp application in the OpenThread GitHub repo. + + + + + + + - - - - - - - This is a simple OpenThread RCP application. This is equivalent to the ot-rcp application in the OpenThread GitHub repo. + + + + + + + - - - - - - - This is a simple OpenThread RCP application. This is equivalent to the ot-rcp application in the OpenThread GitHub repo. + + + + + + + - - - - - - - This is a very simple CLI application to test the OpenThread stack on a Full Thread Device. This is equivalent to the ot-cli-ftd application in the OpenThread GitHub repo. + + + + + + + - - - - - - - This is a very simple CLI application to test the OpenThread stack on a Full Thread Device. This is equivalent to the ot-cli-ftd application in the OpenThread GitHub repo. + + + + + + + - - - - - - - This is a very simple CLI application to test the OpenThread stack on a Full Thread Device. This is equivalent to the ot-cli-ftd application in the OpenThread GitHub repo. + + + + + + + - - - - - - - This is a very simple CLI application to test the OpenThread stack on a Full Thread Device. This is equivalent to the ot-cli-ftd application in the OpenThread GitHub repo. + + + + + + + - - - - - - - This is a very simple CLI application to test the OpenThread stack on a Full Thread Device. This is equivalent to the ot-cli-ftd application in the OpenThread GitHub repo. + + + + + + + - - - - - - - This is a very simple CLI application to test the OpenThread stack on a Minimal Thread Device. This is equivalent to the ot-cli-mtd application in the OpenThread GitHub repo. + + + + + + + - - - - - - - This is a very simple CLI application to test the OpenThread stack on a Minimal Thread Device. This is equivalent to the ot-cli-mtd application in the OpenThread GitHub repo. + + + + + + + - - - - - - - This is a very simple CLI application to test the OpenThread stack on a Minimal Thread Device. This is equivalent to the ot-cli-mtd application in the OpenThread GitHub repo. + + + + + + + - - - - - - - This is a very simple CLI application to test the OpenThread stack on a Minimal Thread Device. This is equivalent to the ot-cli-mtd application in the OpenThread GitHub repo. + + + + + + + - - - - - - - This is a very simple CLI application to test the OpenThread stack on a Minimal Thread Device. This is equivalent to the ot-cli-mtd application in the OpenThread GitHub repo. + + + + + + + - - - - - - - This is a sample application to start and form a Thread network on an FTD for the sleepy-demo. + + + + + + + - - - - - - - This is a sample application to start and form a Thread network on an FTD for the sleepy-demo. + + + + + + + - - - - - - - This is a sample application to start and form a Thread network on an FTD for the sleepy-demo. + + + + + + + - - - - - - - This is a sample application to start and form a Thread network on an FTD for the sleepy-demo. + + + + + + + - - - - - - - This is a sample application to start and form a Thread network on an FTD for the sleepy-demo. + + + + + + + - - - - - - - This is a sample application to demonstrate Sleepy End Device behaviour on an MTD using the EFR32's low power EM2 mode. + + + + + + + - - - - - - - This is a sample application to demonstrate Sleepy End Device behaviour on an MTD using the EFR32's low power EM2 mode. + + + + + + + - - - - - - - This is a sample application to demonstrate Sleepy End Device behaviour on an MTD using the EFR32's low power EM2 mode. + + + + + + + - - - - - - - This is a sample application to demonstrate Sleepy End Device behaviour on an MTD using the EFR32's low power EM2 mode. + + + + + + + - - - - - - - This is a sample application to demonstrate Sleepy End Device behaviour on an MTD using the EFR32's low power EM2 mode. + + + + + + + - - - - - - - This is a simple application to test DMP (Dynamic MultiProtocol) with OpenThread and Bluetooth running on FreeRTOS. + + + + + + + - - - - - - - This is a simple application to test DMP (Dynamic MultiProtocol) with OpenThread and Bluetooth running on FreeRTOS. + + + + + + + - - - - - - - This is a simple application to test DMP (Dynamic MultiProtocol) with OpenThread and Bluetooth running on FreeRTOS. + + + + + + + - - - - - - - This is a simple application to test DMP (Dynamic MultiProtocol) with OpenThread and Bluetooth running on FreeRTOS. + + + + + + + - - - - - - - This is a simple application to test DMP (Dynamic MultiProtocol) with OpenThread and Bluetooth running on FreeRTOS. + + + + + + + diff --git a/protocol/openthread/openthread_production_templates.xml b/protocol/openthread/openthread_production_templates.xml index e1862a099a..9483163839 100644 --- a/protocol/openthread/openthread_production_templates.xml +++ b/protocol/openthread/openthread_production_templates.xml @@ -6,7 +6,7 @@ - + @@ -21,7 +21,7 @@ - + @@ -36,7 +36,7 @@ - + @@ -51,7 +51,7 @@ - + @@ -66,7 +66,7 @@ - + @@ -81,8 +81,8 @@ - - + + @@ -96,8 +96,8 @@ - - + + @@ -111,8 +111,8 @@ - - + + @@ -126,7 +126,7 @@ - + @@ -141,7 +141,7 @@ - + diff --git a/protocol/openthread/platform-abstraction/efr32/ieee802154-packet-utils.cpp b/protocol/openthread/platform-abstraction/efr32/ieee802154-packet-utils.cpp index 618d96fe05..7a25c54d56 100644 --- a/protocol/openthread/platform-abstraction/efr32/ieee802154-packet-utils.cpp +++ b/protocol/openthread/platform-abstraction/efr32/ieee802154-packet-utils.cpp @@ -314,3 +314,15 @@ bool efr32IsFramePending(otRadioFrame *aFrame) { return static_cast(aFrame)->GetFramePending(); } + +otPanId efr32GetDstPanId(otRadioFrame *aFrame) +{ + otPanId aPanId = 0xFFFF; + + if(static_cast(aFrame)->IsDstPanIdPresent()) + { + static_cast(aFrame)->GetDstPanId(aPanId); + } + + return aPanId; +} diff --git a/protocol/openthread/platform-abstraction/efr32/openthread-core-efr32-config.h b/protocol/openthread/platform-abstraction/efr32/openthread-core-efr32-config.h index 5a096c6687..0e056907ac 100644 --- a/protocol/openthread/platform-abstraction/efr32/openthread-core-efr32-config.h +++ b/protocol/openthread/platform-abstraction/efr32/openthread-core-efr32-config.h @@ -164,6 +164,22 @@ #define OPENTHREAD_CONFIG_PLATFORM_INFO "EFR32" #endif +/** + * @def OPENTHREAD_CONFIG_SRP_CLIENT_BUFFERS_MAX_SERVICES + * + * Specifies number of service entries in the SRP client service pool. + * + * This config is applicable only when `OPENTHREAD_CONFIG_SRP_CLIENT_BUFFERS_ENABLE` is enabled. + * + */ +#ifndef OPENTHREAD_CONFIG_SRP_CLIENT_BUFFERS_MAX_SERVICES +#if OPENTHREAD_CONFIG_REFERENCE_DEVICE_ENABLE +#define OPENTHREAD_CONFIG_SRP_CLIENT_BUFFERS_MAX_SERVICES 10 +#else +#define OPENTHREAD_CONFIG_SRP_CLIENT_BUFFERS_MAX_SERVICES 2 +#endif +#endif + /** * @def OPENTHREAD_CONFIG_MAC_CSL_AUTO_SYNC_ENABLE * diff --git a/protocol/openthread/platform-abstraction/efr32/radio.c b/protocol/openthread/platform-abstraction/efr32/radio.c index 3e957c8ef0..fb4277f52d 100644 --- a/protocol/openthread/platform-abstraction/efr32/radio.c +++ b/protocol/openthread/platform-abstraction/efr32/radio.c @@ -90,8 +90,13 @@ //------------------------------------------------------------------------------ // Enums, macros and static variables -#define LOW_BYTE(n) ((uint8_t)((n)&0xFF)) +#ifndef LOW_BYTE +#define LOW_BYTE(n) ((uint8_t)((n) & 0xFF)) +#endif //LOW_BTE + +#ifndef HIGH_BYTE #define HIGH_BYTE(n) ((uint8_t)(LOW_BYTE((n) >> 8))) +#endif //HIGH_BYTE //Intentionally maintaining separate groups for series-1 and series-2 devices //This gives flexibility to add new elements to be read, like CCA Thresholds. @@ -804,7 +809,7 @@ static otError radioScheduleRx(uint8_t aChannel, uint32_t aStart, uint32_t aDura .startMode = RAIL_TIME_ABSOLUTE, .end = aDuration, .endMode = RAIL_TIME_DELAY, - .rxTransitionEndSchedule = 0, // This lets us idle after a scheduled-rx + .rxTransitionEndSchedule = 1, // This lets us idle after a scheduled-rx .hardWindowEnd = 0 }; // This lets us receive a packet near a window-end-event status = RAIL_ScheduleRx(gRailHandle, aChannel, &rxCfg, &bgRxSchedulerInfo); @@ -1924,24 +1929,44 @@ static bool writeIeee802154EnhancedAck( RAIL_Handle_t aRailHandle, } otMacAddress aSrcAddress; - uint8_t linkMetricsDataLen = 0; - uint8_t *dataPtr = NULL; - bool setFramePending = false; + uint8_t linkMetricsDataLen = 0; + uint8_t *dataPtr = NULL; + bool setFramePending = false; otMacFrameGetSrcAddr(&receivedFrame, &aSrcAddress); if (sIsSrcMatchEnabled && (aSrcAddress.mType != OT_MAC_ADDRESS_TYPE_NONE)) { - if (aSrcAddress.mType == OT_MAC_ADDRESS_TYPE_EXTENDED) +#if _SILICON_LABS_32B_SERIES_1_CONFIG == 1 && OPENTHREAD_RADIO && OPENTHREAD_CONFIG_MULTIPAN_RCP_ENABLE == 1 + if (iid == 0) // on MG1 the RAIL filter mask doesn't work so search all tables { - setFramePending = (utilsSoftSrcMatchExtFindEntry(iid , &aSrcAddress.mAddress.mExtAddress) >= 0); + for (uint8_t i = 1; i <= RADIO_CONFIG_SRC_MATCH_PANID_NUM; i++) + { + setFramePending = (aSrcAddress.mType == OT_MAC_ADDRESS_TYPE_EXTENDED + ? (utilsSoftSrcMatchExtFindEntry(i , &aSrcAddress.mAddress.mExtAddress) >= 0) + : (utilsSoftSrcMatchShortFindEntry(i, aSrcAddress.mAddress.mShortAddress) >= 0)); + if (setFramePending) + { + break; + } + } } else +#endif { - setFramePending = (utilsSoftSrcMatchShortFindEntry(iid, aSrcAddress.mAddress.mShortAddress) >= 0); + setFramePending = (aSrcAddress.mType == OT_MAC_ADDRESS_TYPE_EXTENDED + ? (utilsSoftSrcMatchExtFindEntry(iid , &aSrcAddress.mAddress.mExtAddress) >= 0) + : (utilsSoftSrcMatchShortFindEntry(iid, aSrcAddress.mAddress.mShortAddress) >= 0)); } } +#if _SILICON_LABS_32B_SERIES_1_CONFIG == 1 && OPENTHREAD_RADIO && OPENTHREAD_CONFIG_MULTIPAN_RCP_ENABLE == 1 + otPanId destPanId; + + destPanId = efr32GetDstPanId(&receivedFrame); + iid = utilsSoftSrcMatchFindIidFromPanId(destPanId); +#endif + // Generate our IE header. // Write IE data for enhanced ACK (link metrics + allocate bytes for CSL) @@ -2069,6 +2094,24 @@ static void dataRequestCommandCallback(RAIL_Handle_t aRailHandle) otEXPECT(status == RAIL_STATUS_NO_ERROR); uint8_t iid = getIidFromFilterMask(packetInfo.filterMask); +#if _SILICON_LABS_32B_SERIES_1_CONFIG == 1 && OPENTHREAD_RADIO && OPENTHREAD_CONFIG_MULTIPAN_RCP_ENABLE == 1 + if (iid == 0) // on MG1 the RAIL filter mask doesn't work so search all tables + { + for (uint8_t i = 1; i <= RADIO_CONFIG_SRC_MATCH_PANID_NUM; i++) + { + framePendingSet = (sourceAddress.length == RAIL_IEEE802154_LongAddress + ? (utilsSoftSrcMatchExtFindEntry(i , (otExtAddress *)sourceAddress.longAddress) >= 0) + : (utilsSoftSrcMatchShortFindEntry(i, sourceAddress.shortAddress) >= 0)); + if (framePendingSet) + { + status = RAIL_IEEE802154_SetFramePending(aRailHandle); + otEXPECT(status == RAIL_STATUS_NO_ERROR); + break; + } + } + } + else +#endif if ((sourceAddress.length == RAIL_IEEE802154_LongAddress && utilsSoftSrcMatchExtFindEntry(iid, (otExtAddress *)sourceAddress.longAddress) >= 0) || (sourceAddress.length == RAIL_IEEE802154_ShortAddress && @@ -2977,7 +3020,7 @@ static void emRadioHoldOffInternalIsr(uint8_t active) } // External API used by Coex Component -void emRadioHoldOffIsr(bool active) +SL_WEAK void emRadioHoldOffIsr(bool active) { emRadioHoldOffInternalIsr((uint8_t) active | (rhoActive & ~RHO_EXT_ACTIVE)); } @@ -3005,3 +3048,74 @@ void efr32RadioClearCoexCounters(void) #endif // SL_OPENTHREAD_COEX_COUNTER_ENABLE #endif // SL_CATALOG_RAIL_UTIL_COEX_PRESENT + + +#if OPENTHREAD_CONFIG_DIAG_ENABLE + +otError otPlatDiagTxStreamRandom(void) +{ + RAIL_Status_t status; + uint16_t streamChannel; + + RAIL_GetChannel(gRailHandle, &streamChannel); + + otLogInfoPlat("Diag Stream PN9 Process", NULL); + + status = RAIL_StartTxStream(gRailHandle, streamChannel, RAIL_STREAM_PN9_STREAM); + assert(status == RAIL_STATUS_NO_ERROR); + + return status; +} + +otError otPlatDiagTxStreamTone(void) +{ + RAIL_Status_t status; + uint16_t streamChannel; + + RAIL_GetChannel(gRailHandle, &streamChannel); + + otLogInfoPlat("Diag Stream CARRIER-WAVE Process", NULL); + + status = RAIL_StartTxStream(gRailHandle, streamChannel, RAIL_STREAM_CARRIER_WAVE); + assert(status == RAIL_STATUS_NO_ERROR); + + return status; +} + +otError otPlatDiagTxStreamStop(void) +{ + RAIL_Status_t status; + + otLogInfoPlat("Diag Stream STOP Process", NULL); + + status = RAIL_StopTxStream(gRailHandle); + assert(status == RAIL_STATUS_NO_ERROR); + + return status; +} + +otError otPlatDiagTxStreamAddrMatch(uint8_t enable) +{ + RAIL_Status_t status; + + otLogInfoPlat("Diag Stream Disable addressMatch", NULL); + + status = RAIL_IEEE802154_SetPromiscuousMode(gRailHandle, + !enable); + assert(status == RAIL_STATUS_NO_ERROR); + + return status; +} + +otError otPlatDiagTxStreamAutoAck(uint8_t autoAckEnabled) +{ + RAIL_Status_t status = RAIL_STATUS_NO_ERROR; + + otLogInfoPlat("Diag Stream Disable autoAck", NULL); + + RAIL_PauseRxAutoAck(gRailHandle, !autoAckEnabled); + + return status; +} + +#endif // OPENTHREAD_CONFIG_DIAG_ENABLE \ No newline at end of file diff --git a/protocol/openthread/platform-abstraction/efr32/sl_packet_utils.h b/protocol/openthread/platform-abstraction/efr32/sl_packet_utils.h index 67f0d9d4d0..59ac6d48a4 100644 --- a/protocol/openthread/platform-abstraction/efr32/sl_packet_utils.h +++ b/protocol/openthread/platform-abstraction/efr32/sl_packet_utils.h @@ -61,6 +61,16 @@ void efr32PlatProcessTransmitAesCcm(otRadioFrame *aFrame, const otExtAddress *aE */ bool efr32IsFramePending(otRadioFrame *aFrame); +/** + * This function returns the Destination PanId, if present. + * + * @param[in] aFrame A pointer to the MAC frame buffer. + * + * @retval DstPanId If present. + * @retval BcastPanId If Dest PanId is compressed. + */ +otPanId efr32GetDstPanId(otRadioFrame *aFrame); + #ifdef __cplusplus } // extern "C" #endif diff --git a/protocol/openthread/sample-apps/ot-ble-dmp/app.c b/protocol/openthread/sample-apps/ot-ble-dmp/app.c index e7b25a3c4d..82bb59d549 100644 --- a/protocol/openthread/sample-apps/ot-ble-dmp/app.c +++ b/protocol/openthread/sample-apps/ot-ble-dmp/app.c @@ -28,6 +28,8 @@ #include "openthread-system.h" #include "app.h" +#include "reset_util.h" + #include "sl_component_catalog.h" #ifdef SL_CATALOG_POWER_MANAGER_PRESENT #include "sl_power_manager.h" @@ -37,19 +39,6 @@ #include "sl_simple_button.h" #endif -#if OPENTHREAD_EXAMPLES_SIMULATION -#include -#include - -jmp_buf gResetJump; - -void __gcov_flush(); -#endif - -#ifndef OPENTHREAD_ENABLE_COVERAGE -#define OPENTHREAD_ENABLE_COVERAGE 0 -#endif - /** * This function initializes the CLI app. * @@ -148,16 +137,7 @@ void sl_ot_cli_init(void) void app_init(void) { -#if OPENTHREAD_EXAMPLES_SIMULATION - if (setjmp(gResetJump)) - { - alarm(0); -#if OPENTHREAD_ENABLE_COVERAGE - __gcov_flush(); -#endif - execvp(argv[0], argv); // TO DO: argc, argv? - } -#endif + OT_SETUP_RESET_JUMP(argv); } /**************************************************************************//** diff --git a/protocol/openthread/sample-apps/ot-ble-dmp/ot-ble-dmp.slcp b/protocol/openthread/sample-apps/ot-ble-dmp/ot-ble-dmp.slcp index a4bbc6f3b4..770ff68c3a 100644 --- a/protocol/openthread/sample-apps/ot-ble-dmp/ot-ble-dmp.slcp +++ b/protocol/openthread/sample-apps/ot-ble-dmp/ot-ble-dmp.slcp @@ -38,6 +38,9 @@ include: - path: . file_list: - path: app.h + - path: ../../../../util/third_party/openthread/src/lib/platform + file_list: + - path: reset_util.h source: - path: main.c diff --git a/protocol/openthread/sample-apps/ot-cli/app.c b/protocol/openthread/sample-apps/ot-cli/app.c index 79c4de0e6c..f32b946dd0 100644 --- a/protocol/openthread/sample-apps/ot-cli/app.c +++ b/protocol/openthread/sample-apps/ot-cli/app.c @@ -28,6 +28,8 @@ #include "openthread-system.h" #include "app.h" +#include "reset_util.h" + #include "sl_component_catalog.h" #ifdef SL_CATALOG_POWER_MANAGER_PRESENT #include "sl_power_manager.h" @@ -38,19 +40,6 @@ #include "sl_simple_button.h" #endif -#if OPENTHREAD_EXAMPLES_SIMULATION -#include -#include - -jmp_buf gResetJump; - -void __gcov_flush(); -#endif - -#ifndef OPENTHREAD_ENABLE_COVERAGE -#define OPENTHREAD_ENABLE_COVERAGE 0 -#endif - /** * This function initializes the CLI app. * @@ -149,16 +138,7 @@ void sl_ot_cli_init(void) void app_init(void) { -#if OPENTHREAD_EXAMPLES_SIMULATION - if (setjmp(gResetJump)) - { - alarm(0); -#if OPENTHREAD_ENABLE_COVERAGE - __gcov_flush(); -#endif - execvp(argv[0], argv); // TO DO: argc, argv? - } -#endif + OT_SETUP_RESET_JUMP(argv); } /**************************************************************************//** diff --git a/protocol/openthread/sample-apps/ot-cli/ot-cli-ftd.slcp b/protocol/openthread/sample-apps/ot-cli/ot-cli-ftd.slcp index 9dfee57868..66781f4f27 100644 --- a/protocol/openthread/sample-apps/ot-cli/ot-cli-ftd.slcp +++ b/protocol/openthread/sample-apps/ot-cli/ot-cli-ftd.slcp @@ -8,6 +8,7 @@ quality: production component: - id: brd4001a + - id: ot_reference_device - id: ot_stack_ftd - id: ot_cli_source - id: uartdrv_usart @@ -26,6 +27,9 @@ include: - path: . file_list: - path: app.h + - path: ../../../../util/third_party/openthread/src/lib/platform + file_list: + - path: reset_util.h source: - path: main.c @@ -38,36 +42,6 @@ configuration: value: 1 - name: SL_MBEDTLS_KEY_EXCHANGE_PSK_ENABLED value: 1 - - name: OPENTHREAD_CONFIG_BACKBONE_ROUTER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_OBSERVE_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_SECURE_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COMMISSIONER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_DHCP6_CLIENT_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_DHCP6_SERVER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_DNSSD_SERVER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_JOINER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_MAC_FILTER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_REFERENCE_DEVICE_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_SRP_SERVER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_LOG_OUTPUT - value: OPENTHREAD_CONFIG_LOG_OUTPUT_APP - name: UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION value: 0 condition: [freertos, uartdrv_usart] diff --git a/protocol/openthread/sample-apps/ot-cli/ot-cli-mtd.slcp b/protocol/openthread/sample-apps/ot-cli/ot-cli-mtd.slcp index 0c99d96230..cb0c5370da 100644 --- a/protocol/openthread/sample-apps/ot-cli/ot-cli-mtd.slcp +++ b/protocol/openthread/sample-apps/ot-cli/ot-cli-mtd.slcp @@ -8,6 +8,7 @@ quality: production component: - id: brd4001a + - id: ot_reference_device - id: ot_stack_mtd - id: ot_cli_source - id: uartdrv_usart @@ -26,6 +27,9 @@ include: - path: . file_list: - path: app.h + - path: ../../../../util/third_party/openthread/src/lib/platform + file_list: + - path: reset_util.h source: - path: main.c @@ -38,22 +42,6 @@ configuration: value: 1 - name: SL_MBEDTLS_KEY_EXCHANGE_PSK_ENABLED value: 1 - - name: OPENTHREAD_CONFIG_COAP_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_OBSERVE_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_SECURE_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_DHCP6_CLIENT_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_JOINER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_MAC_FILTER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_REFERENCE_DEVICE_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_LOG_OUTPUT - value: OPENTHREAD_CONFIG_LOG_OUTPUT_APP - name: UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION value: 0 condition: [freertos, uartdrv_usart] diff --git a/protocol/openthread/sample-apps/ot-ncp/app.c b/protocol/openthread/sample-apps/ot-ncp/app.c index 55e2066321..b3af052835 100644 --- a/protocol/openthread/sample-apps/ot-ncp/app.c +++ b/protocol/openthread/sample-apps/ot-ncp/app.c @@ -25,18 +25,7 @@ #include "openthread-system.h" #include "app.h" -#if OPENTHREAD_EXAMPLES_SIMULATION -#include -#include - -jmp_buf gResetJump; - -void __gcov_flush(); -#endif - -#ifndef OPENTHREAD_ENABLE_COVERAGE -#define OPENTHREAD_ENABLE_COVERAGE 0 -#endif +#include "reset_util.h" /** * This function initializes the NCP app. @@ -85,16 +74,7 @@ void sl_ot_ncp_init(void) void app_init(void) { -#if OPENTHREAD_EXAMPLES_SIMULATION - if (setjmp(gResetJump)) - { - alarm(0); -#if OPENTHREAD_ENABLE_COVERAGE - __gcov_flush(); -#endif - execvp(argv[0], argv); // TO DO: argc, argv? - } -#endif + OT_SETUP_RESET_JUMP(argv); } /**************************************************************************//** diff --git a/protocol/openthread/sample-apps/ot-ncp/ot-ncp-ftd.slcp b/protocol/openthread/sample-apps/ot-ncp/ot-ncp-ftd.slcp index 1c7e134b05..bfa623e4c1 100644 --- a/protocol/openthread/sample-apps/ot-ncp/ot-ncp-ftd.slcp +++ b/protocol/openthread/sample-apps/ot-ncp/ot-ncp-ftd.slcp @@ -8,6 +8,7 @@ quality: production component: - id: brd4001a + - id: ot_reference_device - id: ot_stack_ftd - id: ot_ncp_source - id: uartdrv_usart @@ -19,6 +20,9 @@ include: - path: . file_list: - path: app.h + - path: ../../../../util/third_party/openthread/src/lib/platform + file_list: + - path: reset_util.h source: - path: main.c @@ -31,36 +35,6 @@ configuration: value: 1 - name: SL_MBEDTLS_KEY_EXCHANGE_PSK_ENABLED value: 1 - - name: OPENTHREAD_CONFIG_BACKBONE_ROUTER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_OBSERVE_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_SECURE_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COMMISSIONER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_DHCP6_CLIENT_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_DHCP6_SERVER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_DNSSD_SERVER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_JOINER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_MAC_FILTER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_REFERENCE_DEVICE_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_SRP_SERVER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_LOG_OUTPUT - value: OPENTHREAD_CONFIG_LOG_OUTPUT_APP tag: - prebuilt_demo diff --git a/protocol/openthread/sample-apps/ot-ncp/ot-ncp-mtd.slcp b/protocol/openthread/sample-apps/ot-ncp/ot-ncp-mtd.slcp index 9d79627395..7df486542d 100644 --- a/protocol/openthread/sample-apps/ot-ncp/ot-ncp-mtd.slcp +++ b/protocol/openthread/sample-apps/ot-ncp/ot-ncp-mtd.slcp @@ -8,6 +8,7 @@ quality: production component: - id: brd4001a + - id: ot_reference_device - id: ot_stack_mtd - id: ot_ncp_source - id: uartdrv_usart @@ -19,6 +20,9 @@ include: - path: . file_list: - path: app.h + - path: ../../../../util/third_party/openthread/src/lib/platform + file_list: + - path: reset_util.h source: - path: main.c @@ -31,22 +35,6 @@ configuration: value: 1 - name: SL_MBEDTLS_KEY_EXCHANGE_PSK_ENABLED value: 1 - - name: OPENTHREAD_CONFIG_COAP_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_OBSERVE_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_SECURE_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_DHCP6_CLIENT_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_JOINER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_MAC_FILTER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_REFERENCE_DEVICE_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_LOG_OUTPUT - value: OPENTHREAD_CONFIG_LOG_OUTPUT_APP tag: - prebuilt_demo diff --git a/protocol/openthread/sample-apps/ot-ncp/ot-rcp.slcp b/protocol/openthread/sample-apps/ot-ncp/ot-rcp.slcp index 855c4c5af5..86f6ff186c 100644 --- a/protocol/openthread/sample-apps/ot-ncp/ot-rcp.slcp +++ b/protocol/openthread/sample-apps/ot-ncp/ot-rcp.slcp @@ -8,6 +8,7 @@ quality: production component: - id: brd4001a + - id: ot_reference_device - id: ot_stack_rcp - id: uartdrv_usart instance: @@ -18,6 +19,9 @@ include: - path: . file_list: - path: app.h + - path: ../../../../util/third_party/openthread/src/lib/platform + file_list: + - path: reset_util.h source: - path: main.c @@ -28,38 +32,6 @@ configuration: value: 1 - name: OPENTHREAD_CONFIG_HEAP_EXTERNAL_ENABLE value: 0 - - name: OPENTHREAD_CONFIG_BACKBONE_ROUTER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_BORDER_AGENT_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_OBSERVE_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_SECURE_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COMMISSIONER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_DHCP6_CLIENT_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_DHCP6_SERVER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_DNSSD_SERVER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_JOINER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_MAC_FILTER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_REFERENCE_DEVICE_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_SRP_SERVER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_LOG_OUTPUT - value: OPENTHREAD_CONFIG_LOG_OUTPUT_APP tag: - prebuilt_demo diff --git a/protocol/openthread/sample-apps/ot-ncp/rcp-spi-802154-blehci.slcp b/protocol/openthread/sample-apps/ot-ncp/rcp-spi-802154-blehci.slcp index dd482fe2f7..b7aae536bf 100644 --- a/protocol/openthread/sample-apps/ot-ncp/rcp-spi-802154-blehci.slcp +++ b/protocol/openthread/sample-apps/ot-ncp/rcp-spi-802154-blehci.slcp @@ -19,6 +19,7 @@ quality: alpha component: - id: brd4001a + - id: ot_reference_device - id: ot_stack_rcp - id: ot_ncp_cpc - id: cpc_secondary_driver_spi_usart @@ -41,6 +42,9 @@ include: - path: . file_list: - path: app.h + - path: ../../../../util/third_party/openthread/src/lib/platform + file_list: + - path: reset_util.h source: - path: main.c @@ -75,36 +79,12 @@ configuration: - name: OPENTHREAD_CONFIG_HEAP_EXTERNAL_ENABLE value: 0 - - name: OPENTHREAD_CONFIG_BORDER_AGENT_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_OBSERVE_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_SECURE_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COMMISSIONER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_DHCP6_CLIENT_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_DHCP6_SERVER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_DNSSD_SERVER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_JOINER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_REFERENCE_DEVICE_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_SRP_SERVER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE - value: 1 - name: OPENTHREAD_CONFIG_LOG_OUTPUT value: OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED - name: OPENTHREAD_CONFIG_MULTIPAN_RCP_ENABLE value: 1 + - name: OPENTHREAD_CONFIG_DIAG_ENABLE + value: 1 - name: OPENTHREAD_CONFIG_PLATFORM_KEY_REFERENCES_ENABLE value: 0 diff --git a/protocol/openthread/sample-apps/ot-ncp/rcp-spi-802154.slcp b/protocol/openthread/sample-apps/ot-ncp/rcp-spi-802154.slcp index 3ebe38cf0b..6be10497c9 100644 --- a/protocol/openthread/sample-apps/ot-ncp/rcp-spi-802154.slcp +++ b/protocol/openthread/sample-apps/ot-ncp/rcp-spi-802154.slcp @@ -18,6 +18,7 @@ quality: production component: - id: brd4001a + - id: ot_reference_device - id: ot_stack_rcp - id: ot_ncp_cpc - id: cpc_secondary_driver_spi_usart @@ -30,6 +31,9 @@ include: - path: . file_list: - path: app.h + - path: ../../../../util/third_party/openthread/src/lib/platform + file_list: + - path: reset_util.h source: - path: main.c @@ -40,32 +44,8 @@ configuration: value: 2752 - name: OPENTHREAD_CONFIG_HEAP_EXTERNAL_ENABLE value: 0 - - name: OPENTHREAD_CONFIG_BORDER_AGENT_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_OBSERVE_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_SECURE_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COMMISSIONER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_DHCP6_CLIENT_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_DHCP6_SERVER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_DNSSD_SERVER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_JOINER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_REFERENCE_DEVICE_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_SRP_SERVER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE - value: 1 + - name: OPENTHREAD_CONFIG_DIAG_ENABLE + value: 1 - name: OPENTHREAD_CONFIG_LOG_OUTPUT value: OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED - name: OPENTHREAD_CONFIG_MULTIPAN_RCP_ENABLE diff --git a/protocol/openthread/sample-apps/ot-ncp/rcp-uart-802154-blehci.slcp b/protocol/openthread/sample-apps/ot-ncp/rcp-uart-802154-blehci.slcp index 758c373ed0..4f158603d2 100644 --- a/protocol/openthread/sample-apps/ot-ncp/rcp-uart-802154-blehci.slcp +++ b/protocol/openthread/sample-apps/ot-ncp/rcp-uart-802154-blehci.slcp @@ -19,6 +19,7 @@ quality: alpha component: - id: brd4001a + - id: ot_reference_device - id: ot_stack_rcp - id: ot_ncp_cpc - id: cpc_secondary_driver_uart_usart @@ -41,6 +42,9 @@ include: - path: . file_list: - path: app.h + - path: ../../../../util/third_party/openthread/src/lib/platform + file_list: + - path: reset_util.h source: - path: main.c @@ -81,36 +85,12 @@ configuration: value: usartHwFlowControlCtsAndRts - name: OPENTHREAD_CONFIG_HEAP_EXTERNAL_ENABLE value: 0 - - name: OPENTHREAD_CONFIG_BORDER_AGENT_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_OBSERVE_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_SECURE_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COMMISSIONER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_DHCP6_CLIENT_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_DHCP6_SERVER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_DNSSD_SERVER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_JOINER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_REFERENCE_DEVICE_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_SRP_SERVER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE - value: 1 - name: OPENTHREAD_CONFIG_LOG_OUTPUT value: OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED - name: OPENTHREAD_CONFIG_MULTIPAN_RCP_ENABLE value: 1 + - name: OPENTHREAD_CONFIG_DIAG_ENABLE + value: 1 - name: OPENTHREAD_CONFIG_PLATFORM_KEY_REFERENCES_ENABLE value: 0 diff --git a/protocol/openthread/sample-apps/ot-ncp/rcp-uart-802154.slcp b/protocol/openthread/sample-apps/ot-ncp/rcp-uart-802154.slcp index 4714716e97..718a072791 100644 --- a/protocol/openthread/sample-apps/ot-ncp/rcp-uart-802154.slcp +++ b/protocol/openthread/sample-apps/ot-ncp/rcp-uart-802154.slcp @@ -18,6 +18,7 @@ quality: production component: - id: brd4001a + - id: ot_reference_device - id: ot_stack_rcp - id: ot_ncp_cpc - id: cpc_secondary_driver_uart_usart @@ -30,6 +31,9 @@ include: - path: . file_list: - path: app.h + - path: ../../../../util/third_party/openthread/src/lib/platform + file_list: + - path: reset_util.h source: - path: main.c @@ -46,32 +50,8 @@ configuration: value: usartHwFlowControlCtsAndRts - name: OPENTHREAD_CONFIG_HEAP_EXTERNAL_ENABLE value: 0 - - name: OPENTHREAD_CONFIG_BORDER_AGENT_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_OBSERVE_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_SECURE_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COMMISSIONER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_DHCP6_CLIENT_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_DHCP6_SERVER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_DNSSD_SERVER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_JOINER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_REFERENCE_DEVICE_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_SRP_SERVER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE - value: 1 + - name: OPENTHREAD_CONFIG_DIAG_ENABLE + value: 1 - name: OPENTHREAD_CONFIG_LOG_OUTPUT value: OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED - name: OPENTHREAD_CONFIG_MULTIPAN_RCP_ENABLE diff --git a/protocol/openthread/sample-apps/sleepy-demo/sleepy-demo-ftd.slcp b/protocol/openthread/sample-apps/sleepy-demo/sleepy-demo-ftd.slcp index 18a8b5dbb2..cdb59ce18f 100644 --- a/protocol/openthread/sample-apps/sleepy-demo/sleepy-demo-ftd.slcp +++ b/protocol/openthread/sample-apps/sleepy-demo/sleepy-demo-ftd.slcp @@ -8,6 +8,7 @@ quality: production component: - id: brd4001a + - id: ot_reference_device - id: ot_stack_ftd - id: ot_cli_source - id: uartdrv_usart @@ -36,30 +37,6 @@ configuration: value: 1 - name: SL_MBEDTLS_KEY_EXCHANGE_PSK_ENABLED value: 1 - - name: OPENTHREAD_CONFIG_BACKBONE_ROUTER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_OBSERVE_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_SECURE_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COMMISSIONER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_DHCP6_CLIENT_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_DHCP6_SERVER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_JOINER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_REFERENCE_DEVICE_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_LOG_OUTPUT - value: OPENTHREAD_CONFIG_LOG_OUTPUT_APP - name: SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE value: 128 # Increase from default 32 condition: [iostream_usart] diff --git a/protocol/openthread/sample-apps/sleepy-demo/sleepy-demo-mtd.slcp b/protocol/openthread/sample-apps/sleepy-demo/sleepy-demo-mtd.slcp index 902ef82941..9842c56391 100644 --- a/protocol/openthread/sample-apps/sleepy-demo/sleepy-demo-mtd.slcp +++ b/protocol/openthread/sample-apps/sleepy-demo/sleepy-demo-mtd.slcp @@ -8,6 +8,7 @@ quality: production component: - id: brd4001a + - id: ot_reference_device - id: ot_stack_mtd - id: ot_cli_source - id: uartdrv_usart @@ -48,20 +49,6 @@ configuration: value: 1 - name: SL_MBEDTLS_KEY_EXCHANGE_PSK_ENABLED value: 1 - - name: OPENTHREAD_CONFIG_COAP_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_OBSERVE_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_COAP_SECURE_API_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_DHCP6_CLIENT_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_JOINER_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_REFERENCE_DEVICE_ENABLE - value: 1 - - name: OPENTHREAD_CONFIG_LOG_OUTPUT - value: OPENTHREAD_CONFIG_LOG_OUTPUT_APP - name: SL_STACK_SIZE value: 4608 diff --git a/protocol/openthread/sample-apps/sleepy-demo/sleepy-ftd.c b/protocol/openthread/sample-apps/sleepy-demo/sleepy-ftd.c index 250bd991eb..880d251dfd 100644 --- a/protocol/openthread/sample-apps/sleepy-demo/sleepy-ftd.c +++ b/protocol/openthread/sample-apps/sleepy-demo/sleepy-ftd.c @@ -71,7 +71,7 @@ void setNetworkConfiguration(void) * Network Name, Mesh Local Prefix, Extended PAN ID, PAN ID, Delay Timer, * Channel, Channel Mask Page 0, Network Key, PSKc, Security Policy */ - aDataset.mActiveTimestamp = 1; + aDataset.mActiveTimestamp.mSeconds = 1; aDataset.mComponents.mIsActiveTimestampPresent = true; /* Set Channel to 15 */ diff --git a/protocol/openthread/sample-apps/sleepy-demo/sleepy-mtd.c b/protocol/openthread/sample-apps/sleepy-demo/sleepy-mtd.c index 045afe821b..944495f5a2 100644 --- a/protocol/openthread/sample-apps/sleepy-demo/sleepy-mtd.c +++ b/protocol/openthread/sample-apps/sleepy-demo/sleepy-mtd.c @@ -103,7 +103,7 @@ void setNetworkConfiguration(void) * Network Name, Mesh Local Prefix, Extended PAN ID, PAN ID, Delay Timer, * Channel, Channel Mask Page 0, Network Key, PSKc, Security Policy */ - aDataset.mActiveTimestamp = 1; + aDataset.mActiveTimestamp.mSeconds = 1; aDataset.mComponents.mIsActiveTimestampPresent = true; /* Set Channel to 15 */ diff --git a/protocol/wisun/app/wisun_rcp/sl_ring.c b/protocol/wisun/app/wisun_rcp/sl_ring.c index 073a1b67c2..6d1a61438b 100644 --- a/protocol/wisun/app/wisun_rcp/sl_ring.c +++ b/protocol/wisun/app/wisun_rcp/sl_ring.c @@ -31,12 +31,34 @@ int ring_push(struct ring *ring, uint8_t data) { BUG_ON(!ring->buf); BUG_ON((ring->size_mask + 1) & ring->size_mask); - if (ring_data_len(ring) > ring->size_mask) + if (ring_data_len(ring) + 1 > ring_buffer_size(ring)) return -1; // Full ring->buf[ring->count_wr++ & ring->size_mask] = data; return 0; } +int ring_push_buf(struct ring *ring, uint8_t *data, size_t len) +{ + size_t remaining; + unsigned int count_wr; + + BUG_ON(!ring->buf); + BUG_ON((ring->size_mask + 1) & ring->size_mask); + if (ring_data_len(ring) + len > ring_buffer_size(ring)) + return -1; // Full + + count_wr = ring->count_wr & ring->size_mask; + remaining = ring_buffer_size(ring) - count_wr; + if (len > remaining) { + memcpy(ring->buf + count_wr, data, remaining); + memcpy(ring->buf, data + remaining, len - remaining); + } else { + memcpy(ring->buf + count_wr, data, len); + } + ring->count_wr += len; + return 0; +} + int ring_pop(struct ring *ring) { BUG_ON(!ring->buf); @@ -46,6 +68,30 @@ int ring_pop(struct ring *ring) return ring->buf[ring->count_rd++ & ring->size_mask]; } +int ring_pop_buf(struct ring *ring, uint8_t *data, size_t len) +{ + size_t remaining; + unsigned int count_rd; + + BUG_ON(!ring->buf); + BUG_ON((ring->size_mask + 1) & ring->size_mask); + if (ring_is_empty(ring)) + return -1; // Empty + + if (len < ring_data_len(ring)) + len = ring_data_len(ring); + count_rd = ring->count_rd & ring->size_mask; + remaining = ring_buffer_size(ring) - count_rd; + if (len > remaining) { + memcpy(data, ring->buf + count_rd, remaining); + memcpy(data + remaining, ring->buf, len - remaining); + } else { + memcpy(data, ring->buf + count_rd, len); + } + ring->count_rd += len; + return len; +} + int ring_get(struct ring *ring, unsigned int index) { BUG_ON(!ring->buf); diff --git a/protocol/wisun/app/wisun_rcp/sl_ring.h b/protocol/wisun/app/wisun_rcp/sl_ring.h index a58cca1e64..5986f1fff2 100644 --- a/protocol/wisun/app/wisun_rcp/sl_ring.h +++ b/protocol/wisun/app/wisun_rcp/sl_ring.h @@ -64,7 +64,9 @@ struct ring { void ring_init(struct ring *ring, void *buf, size_t buf_size); int ring_push(struct ring *ring, uint8_t data); +int ring_push_buf(struct ring *ring, uint8_t *data, size_t len); int ring_pop(struct ring *ring); +int ring_pop_buf(struct ring *ring, uint8_t *data, size_t len); int ring_get(struct ring *ring, unsigned int index); bool ring_is_empty(struct ring *ring); unsigned int ring_data_len(struct ring *ring); diff --git a/protocol/wisun/app/wisun_rcp/sl_wsrcp.c b/protocol/wisun/app/wisun_rcp/sl_wsrcp.c index d9de3e37ff..a6e3c64347 100644 --- a/protocol/wisun/app/wisun_rcp/sl_wsrcp.c +++ b/protocol/wisun/app/wisun_rcp/sl_wsrcp.c @@ -20,6 +20,7 @@ #include "sl_micrium_debug.h" #include "sl_wsrcp.h" +#include "sl_wsrcp_utils.h" #include "sl_wsrcp_mac.h" #include "sl_wsrcp_uart.h" #include "sl_wsrcp_log.h" @@ -29,13 +30,7 @@ struct sl_wsrcp_app g_rcp_ctxt = { 0 }; static int wisun_rcp_uart_tx(void *cb_data, const void *buf, int buf_len) { - struct sl_wsrcp_app *rcp_app = &g_rcp_ctxt; - int ret; - - osMutexAcquire(rcp_app->uart_tx_lock, osWaitForever); - ret = uart_tx(cb_data, buf, buf_len); - osMutexRelease(rcp_app->uart_tx_lock); - return ret; + return uart_tx(cb_data, buf, buf_len); } static int wisun_rcp_uart_rx(void *cb_data, void *buf, int buf_len) @@ -43,12 +38,26 @@ static int wisun_rcp_uart_rx(void *cb_data, void *buf, int buf_len) return uart_rx(cb_data, buf, buf_len); } +void uart_rx_ready(struct sl_wsrcp_uart *uart_ctxt) +{ + struct sl_wsrcp_app *rcp_app = container_of(uart_ctxt, struct sl_wsrcp_app, uart); + + osEventFlagsSet(rcp_app->main_events, RX_UART); +} + +void uart_crc_error(struct sl_wsrcp_uart *uart_ctxt, uint16_t crc, int frame_len, uint8_t header, uint8_t irq_err_counter) +{ + struct sl_wsrcp_app *rcp_app = container_of(uart_ctxt, struct sl_wsrcp_app, uart); + + wsmac_report_rx_crc_error(rcp_app->rcp_mac, crc, frame_len, header, irq_err_counter); +} + void wisun_rcp_main(void *arg) { struct sl_wsrcp_app *rcp_app = arg; uint32_t flags; - rcp_app->rcp_mac = wsmac_register(wisun_rcp_uart_tx, wisun_rcp_uart_rx, rcp_app); + rcp_app->rcp_mac = wsmac_register(wisun_rcp_uart_tx, wisun_rcp_uart_rx, &rcp_app->uart); for (;;) { flags = osEventFlagsWait(rcp_app->main_events, RX_UART, osFlagsWaitAny, osWaitForever); if (flags & 0x10000000) @@ -69,12 +78,11 @@ void wisun_rcp_init(void) .stack_size = 2048, // Default value is not enough }; - uart_init(rcp_app); + uart_init(&rcp_app->uart); SEGGER_RTT_SetFlagsUpBuffer(0, SEGGER_RTT_MODE_NO_BLOCK_SKIP); export_debugger_data(); // Note: this function is launched before the Operating System, you can't // acquire anymutex in. - rcp_app->uart_tx_lock = osMutexNew(NULL); rcp_app->main_events = osEventFlagsNew(NULL); rcp_app->main_task = osThreadNew(wisun_rcp_main, rcp_app, &thread_attr); } @@ -82,4 +90,9 @@ void wisun_rcp_init(void) SL_WEAK void assertEFM(const char *file, int line) { BUG("assert in %s:%d\n", file, line); +} + +void HardFault_Handler(void) +{ + NVIC_SystemReset(); } \ No newline at end of file diff --git a/protocol/wisun/app/wisun_rcp/sl_wsrcp.h b/protocol/wisun/app/wisun_rcp/sl_wsrcp.h index fbb5296940..45a455f9f5 100644 --- a/protocol/wisun/app/wisun_rcp/sl_wsrcp.h +++ b/protocol/wisun/app/wisun_rcp/sl_wsrcp.h @@ -18,13 +18,10 @@ #include #include #include +#include +#include -#if defined(EUSART_PRESENT) -#include -#else -#include -#endif - +#include "sl_wsrcp_uart.h" #include "sl_ring.h" struct ws_mac_ctxt; @@ -34,19 +31,10 @@ enum { }; struct sl_wsrcp_app { -#if defined(EUSART_PRESENT) - EUSART_TypeDef *sdk_uart; -#else - USART_TypeDef *sdk_uart; -#endif - osMutexId_t uart_tx_lock; - uint8_t rx_buf_data[4096]; - struct ring rx_buf; - int irq_rxof_cnt; - osEventFlagsId_t main_events; osThreadId_t main_task; + struct sl_wsrcp_uart uart; struct sl_wsrcp_mac *rcp_mac; }; diff --git a/protocol/wisun/app/wisun_rcp/sl_wsrcp_crc.c b/protocol/wisun/app/wisun_rcp/sl_wsrcp_crc.c new file mode 100644 index 0000000000..f9192f029e --- /dev/null +++ b/protocol/wisun/app/wisun_rcp/sl_wsrcp_crc.c @@ -0,0 +1,61 @@ +/***************************************************************************//** + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available here[1]. This software is distributed to you in + * Source Code format and is governed by the sections of the MSLA applicable to + * Source Code. + * + * [1] www.silabs.com/about-us/legal/master-software-license-agreement + * + ******************************************************************************/ +#include "sl_wsrcp_crc.h" + +// width=16 poly=0x1021 init=0xffff refin=true refout=true xorout=0xffff check=0x906e residue=0xf0b8 name="CRC-16/IBM-SDLC" +// https://reveng.sourceforge.io/crc-catalogue/16.htm#crc.cat.crc-16-ibm-sdlc +uint16_t crc16(const uint8_t *data, int len) +{ + uint16_t crc = 0xFFFF; + // Generated from http://www.sunshine2k.de/coding/javascript/crc/crc_js.html + static const uint16_t crc_table[256] = { + 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf, 0x8c48, + 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7, 0x1081, 0x0108, + 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e, 0x9cc9, 0x8d40, 0xbfdb, + 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876, 0x2102, 0x308b, 0x0210, 0x1399, + 0x6726, 0x76af, 0x4434, 0x55bd, 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, + 0xfae7, 0xc87c, 0xd9f5, 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, + 0x54b5, 0x453c, 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, + 0xc974, 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb, + 0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3, 0x5285, + 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a, 0xdecd, 0xcf44, + 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72, 0x6306, 0x728f, 0x4014, + 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9, 0xef4e, 0xfec7, 0xcc5c, 0xddd5, + 0xa96a, 0xb8e3, 0x8a78, 0x9bf1, 0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, + 0x242a, 0x16b1, 0x0738, 0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, + 0x9af9, 0x8b70, 0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, + 0xf0b7, 0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff, + 0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036, 0x18c1, + 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e, 0xa50a, 0xb483, + 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5, 0x2942, 0x38cb, 0x0a50, + 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd, 0xb58b, 0xa402, 0x9699, 0x8710, + 0xf3af, 0xe226, 0xd0bd, 0xc134, 0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, + 0x6e6e, 0x5cf5, 0x4d7c, 0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, + 0xa33a, 0xb2b3, 0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, + 0x3efb, 0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232, + 0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a, 0xe70e, + 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1, 0x6b46, 0x7acf, + 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9, 0xf78f, 0xe606, 0xd49d, + 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330, 0x7bc7, 0x6a4e, 0x58d5, 0x495c, + 0x3de3, 0x2c6a, 0x1ef1, 0x0f78 + }; + + // See "Roll Your Own Table-Driven Implementation" from + // https://zlib.net/crc_v3.txt + while (len--) + crc = crc_table[(crc ^ *data++) & 0xff] ^ (crc >> 8); + return crc ^ 0xFFFF; +} + + diff --git a/protocol/wisun/app/wisun_rcp/sl_wsrcp_crc.h b/protocol/wisun/app/wisun_rcp/sl_wsrcp_crc.h new file mode 100644 index 0000000000..c8a11259d5 --- /dev/null +++ b/protocol/wisun/app/wisun_rcp/sl_wsrcp_crc.h @@ -0,0 +1,23 @@ +/***************************************************************************//** + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available here[1]. This software is distributed to you in + * Source Code format and is governed by the sections of the MSLA applicable to + * Source Code. + * + * [1] www.silabs.com/about-us/legal/master-software-license-agreement + * + ******************************************************************************/ +#ifndef SL_WSRCP_CRC_H +#define SL_WSRCP_CRC_H + +#include + +uint16_t crc16(const uint8_t *data, int len); + +#endif + + diff --git a/protocol/wisun/app/wisun_rcp/sl_wsrcp_eusart.c b/protocol/wisun/app/wisun_rcp/sl_wsrcp_eusart.c index d912b7dce1..824d07e3ec 100644 --- a/protocol/wisun/app/wisun_rcp/sl_wsrcp_eusart.c +++ b/protocol/wisun/app/wisun_rcp/sl_wsrcp_eusart.c @@ -14,36 +14,25 @@ #include #include +#include #include #include +#include +#include + #include "sl_wsrcp.h" #include "sl_wsrcp_log.h" #include "sl_wsrcp_uart.h" +#include "sl_wsrcp_uart_config.h" +#include "sl_wsrcp_utils.h" +static struct sl_wsrcp_uart *g_uart_ctxt; -#define UART_PERIPHERAL EUSART0 -#define UART_PERIPHERAL_NO 0 -#define UART_CLOCK cmuClock_EUSART0 -#define UART_RX_IRQ EUSART0_RX_IRQn - -#define UART_TX_PORT gpioPortA -#define UART_TX_PIN 8 -#define UART_TX_LOC 0 - -#define UART_RX_PORT gpioPortA -#define UART_RX_PIN 9 -#define UART_RX_LOC 0 - - -// Used for debug to display the data sent/received on the bus -static char trace_buffer[128]; - -void uart_init(struct sl_wsrcp_app *rcp_app) +void uart_hw_init(struct sl_wsrcp_uart *uart_ctxt) { - EUSART_UartInit_TypeDef init = EUSART_UART_INIT_DEFAULT_HF; + EUSART_UartInit_TypeDef uart_cfg = EUSART_UART_INIT_DEFAULT_HF; - ring_init(&rcp_app->rx_buf, rcp_app->rx_buf_data, sizeof(rcp_app->rx_buf_data)); - rcp_app->sdk_uart = UART_PERIPHERAL; + g_uart_ctxt = uart_ctxt; //CORE_SetNvicRamTableHandler(UART_RX_IRQ, uart_rx_irq); NVIC_ClearPendingIRQ(UART_RX_IRQ); NVIC_EnableIRQ(UART_RX_IRQ); @@ -51,45 +40,46 @@ void uart_init(struct sl_wsrcp_app *rcp_app) CMU_ClockEnable(cmuClock_HFPER, true); #endif CMU_ClockEnable(cmuClock_GPIO, true); - CMU_ClockEnable(UART_CLOCK, true); - GPIO_PinModeSet(UART_TX_PORT, UART_TX_PIN, gpioModePushPull, 1); - GPIO_PinModeSet(UART_RX_PORT, UART_RX_PIN, gpioModeInputPull, 1); - EUSART_UartInitHf(rcp_app->sdk_uart, &init); - - GPIO->EUSARTROUTE[EUSART_NUM(UART_PERIPHERAL)].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN | GPIO_EUSART_ROUTEEN_RXPEN; - GPIO->EUSARTROUTE[EUSART_NUM(UART_PERIPHERAL)].TXROUTE = (UART_TX_PORT << _GPIO_EUSART_TXROUTE_PORT_SHIFT) - | (UART_TX_PIN << _GPIO_EUSART_TXROUTE_PIN_SHIFT); - GPIO->EUSARTROUTE[EUSART_NUM(UART_PERIPHERAL)].RXROUTE = (UART_RX_PORT << _GPIO_EUSART_RXROUTE_PORT_SHIFT) - | (UART_RX_PIN << _GPIO_EUSART_RXROUTE_PIN_SHIFT); CMU_ClockEnable(cmuClock_PRS, true); CMU_ClockEnable(UART_CLOCK, true); CMU_ClockSelectSet(cmuClock_EM01GRPCCLK, cmuSelect_HFRCODPLL); if (UART_CLOCK == cmuClock_EUSART0) { CMU_ClockSelectSet(cmuClock_EUSART0CLK, cmuSelect_EM01GRPCCLK); } - EUSART_IntClear(rcp_app->sdk_uart, 0xFFFFFFFF); - EUSART_IntEnable(rcp_app->sdk_uart, EUSART_IF_RXFL); - EUSART_Enable(rcp_app->sdk_uart, eusartEnable); + + GPIO_PinModeSet(UART_PORT_TX, UART_PIN_TX, gpioModePushPull, 1); + GPIO_PinModeSet(UART_PORT_RX, UART_PIN_RX, gpioModeInputPull, 1); + GPIO->EUSARTROUTE[EUSART_NUM(UART_PERIPHERAL)].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN | GPIO_EUSART_ROUTEEN_RXPEN; + GPIO->EUSARTROUTE[EUSART_NUM(UART_PERIPHERAL)].TXROUTE = (UART_PORT_TX << _GPIO_EUSART_TXROUTE_PORT_SHIFT) + | (UART_PIN_TX << _GPIO_EUSART_TXROUTE_PIN_SHIFT); + GPIO->EUSARTROUTE[EUSART_NUM(UART_PERIPHERAL)].RXROUTE = (UART_PORT_RX << _GPIO_EUSART_RXROUTE_PORT_SHIFT) + | (UART_PIN_RX << _GPIO_EUSART_RXROUTE_PIN_SHIFT); + + uart_cfg.enable = eusartDisable; + EUSART_UartInitHf(uart_ctxt->hw_regs, &uart_cfg); + + uart_ctxt->hw_regs->CFG1_SET = EUSART_CFG1_RXTIMEOUT_SEVENFRAMES; + EUSART_IntClear(uart_ctxt->hw_regs, 0xFFFFFFFF); + // EUSART_IntEnable(uart_ctxt->hw_regs, EUSART_IEN_RXFL); + EUSART_IntEnable(uart_ctxt->hw_regs, EUSART_IEN_RXOF); + EUSART_IntEnable(uart_ctxt->hw_regs, EUSART_IEN_RXTO); + EUSART_Enable(uart_ctxt->hw_regs, eusartEnable); } void EUSART0_RX_IRQHandler(void) { - struct sl_wsrcp_app *rcp_app = &g_rcp_ctxt; - int ret; + struct sl_wsrcp_uart *uart_ctxt = g_uart_ctxt; - if ((EUSART_IntGetEnabled(rcp_app->sdk_uart) & EUSART_IF_RXFL) == 0u) { - WARN("unexpected IRQ"); + BUG_ON(!uart_ctxt); + if (uart_ctxt->hw_regs->IF & EUSART_IF_RXTO) { + uart_handle_rx_dma_timeout(uart_ctxt); + EUSART_IntClear(uart_ctxt->hw_regs, EUSART_IF_RXTO); return; } - - ret = ring_push(&rcp_app->rx_buf, EUSART_Rx(rcp_app->sdk_uart)); - BUG_ON(ret, "buffer overflow"); - osEventFlagsSet(rcp_app->main_events, RX_UART); - - EUSART_IntClear(rcp_app->sdk_uart, EUSART_IF_RXFL); -} - -void uart_tx_byte(struct sl_wsrcp_app *rcp_app, uint8_t data) -{ - EUSART_Tx(rcp_app->sdk_uart, data); + if (uart_ctxt->hw_regs->IF & EUSART_IF_RXOF) { + uart_handle_rx_overflow(uart_ctxt); + EUSART_IntClear(uart_ctxt->hw_regs, EUSART_IF_RXOF); + return; + } + WARN("unexpected IRQ"); } diff --git a/protocol/wisun/app/wisun_rcp/sl_wsrcp_uart.c b/protocol/wisun/app/wisun_rcp/sl_wsrcp_uart.c index dbe3ba3250..37b704ca5f 100644 --- a/protocol/wisun/app/wisun_rcp/sl_wsrcp_uart.c +++ b/protocol/wisun/app/wisun_rcp/sl_wsrcp_uart.c @@ -15,101 +15,161 @@ #include #include #include + #include "sl_wsrcp.h" +#include "sl_wsrcp_crc.h" #include "sl_wsrcp_log.h" +#include "sl_wsrcp_utils.h" #include "sl_wsrcp_uart.h" +#include "sl_wsrcp_uart_config.h" #include "sl_wsrcp_mac.h" // Used for debug to display the data sent/received on the bus static char trace_buffer[128]; -// width=16 poly=0x1021 init=0xffff refin=true refout=true xorout=0xffff check=0x906e residue=0xf0b8 name="CRC-16/IBM-SDLC" -// https://reveng.sourceforge.io/crc-catalogue/16.htm#crc.cat.crc-16-ibm-sdlc -static uint16_t crc16(const uint8_t *data, int len) +__WEAK void uart_rx_ready(struct sl_wsrcp_uart *uart_ctxt) +{ + (void)uart_ctxt; +} + +__WEAK void uart_crc_error(struct sl_wsrcp_uart *uart_ctxt, uint16_t crc, int frame_len, uint8_t header, uint8_t irq_overflow_cnt) +{ + (void)uart_ctxt; + (void)crc; + (void)frame_len; + (void)header; + (void)irq_overflow_cnt; +} + +static bool uart_handle_rx_dma_complete(unsigned int chan, unsigned int seq_num, void *user_param) +{ + struct sl_wsrcp_uart *uart_ctxt = user_param; + int ret; + unsigned int i; + + (void)chan; + (void)seq_num; + + for (i = 0; i < sizeof(uart_ctxt->buf_rx[0]); i++) { + ret = ring_push(&uart_ctxt->rx_ring, uart_ctxt->buf_rx[uart_ctxt->descr_cnt_rx][i]); + BUG_ON(ret, "buffer overflow"); + } + uart_ctxt->descr_cnt_rx += 1; + uart_ctxt->descr_cnt_rx %= ARRAY_SIZE(uart_ctxt->buf_rx); + uart_rx_ready(uart_ctxt); + return true; +} + +static bool uart_handle_tx_dma_complete(unsigned int chan, unsigned int seq_num, void *user_param) +{ + struct sl_wsrcp_uart *uart_ctxt = user_param; + + (void)chan; + (void)seq_num; + + osSemaphoreRelease(uart_ctxt->tx_dma_lock); + return true; +} + +void uart_handle_rx_dma_timeout(struct sl_wsrcp_uart *uart_ctxt) +{ + LDMA_TransferCfg_t ldma_cfg = LDMA_TRANSFER_CFG_PERIPHERAL(UART_LDMA_SIGNAL_RX); + int remaining, descr_cnt_rx, ret; + size_t i; + + // Begin of realtime constrained section + // (with USART, we need to execute that in less than 5µs for a 2Mbps UART link) + // (with EUSART, thanks to it 16bytes depth fifo , we need to execute the + // code below in less than 40µs for a 4Mbps UART link) + DMADRV_StopTransfer(uart_ctxt->dma_chan_rx); + DMADRV_TransferRemainingCount(uart_ctxt->dma_chan_rx, &remaining); + descr_cnt_rx = uart_ctxt->descr_cnt_rx; + uart_ctxt->descr_cnt_rx += 1; + uart_ctxt->descr_cnt_rx %= ARRAY_SIZE(uart_ctxt->buf_rx); + DMADRV_LdmaStartTransfer(uart_ctxt->dma_chan_rx, &ldma_cfg, + &(uart_ctxt->descr_rx[uart_ctxt->descr_cnt_rx]), + uart_handle_rx_dma_complete, uart_ctxt); + // End of realtime constrained section + + for (i = 0; i < sizeof(uart_ctxt->buf_rx[0]) - remaining; i++) { + ret = ring_push(&uart_ctxt->rx_ring, uart_ctxt->buf_rx[descr_cnt_rx][i]); + BUG_ON(ret, "buffer overflow"); + } + uart_rx_ready(uart_ctxt); +} + +void uart_handle_rx_overflow(struct sl_wsrcp_uart *uart_ctxt) { - uint16_t crc = 0xFFFF; - // Generated from http://www.sunshine2k.de/coding/javascript/crc/crc_js.html - static const uint16_t crc_table[256] = { - 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf, 0x8c48, - 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7, 0x1081, 0x0108, - 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e, 0x9cc9, 0x8d40, 0xbfdb, - 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876, 0x2102, 0x308b, 0x0210, 0x1399, - 0x6726, 0x76af, 0x4434, 0x55bd, 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, - 0xfae7, 0xc87c, 0xd9f5, 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, - 0x54b5, 0x453c, 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, - 0xc974, 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb, - 0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3, 0x5285, - 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a, 0xdecd, 0xcf44, - 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72, 0x6306, 0x728f, 0x4014, - 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9, 0xef4e, 0xfec7, 0xcc5c, 0xddd5, - 0xa96a, 0xb8e3, 0x8a78, 0x9bf1, 0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, - 0x242a, 0x16b1, 0x0738, 0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, - 0x9af9, 0x8b70, 0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, - 0xf0b7, 0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff, - 0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036, 0x18c1, - 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e, 0xa50a, 0xb483, - 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5, 0x2942, 0x38cb, 0x0a50, - 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd, 0xb58b, 0xa402, 0x9699, 0x8710, - 0xf3af, 0xe226, 0xd0bd, 0xc134, 0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, - 0x6e6e, 0x5cf5, 0x4d7c, 0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, - 0xa33a, 0xb2b3, 0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, - 0x3efb, 0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232, - 0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a, 0xe70e, - 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1, 0x6b46, 0x7acf, - 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9, 0xf78f, 0xe606, 0xd49d, - 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330, 0x7bc7, 0x6a4e, 0x58d5, 0x495c, - 0x3de3, 0x2c6a, 0x1ef1, 0x0f78 - }; - - // See "Roll Your Own Table-Driven Implementation" from - // https://zlib.net/crc_v3.txt - while (len--) - crc = crc_table[(crc ^ *data++) & 0xff] ^ (crc >> 8); - return crc ^ 0xFFFF; + WARN("IRQ overflow"); + uart_ctxt->irq_overflow_cnt++; } -static int uart_tx_escaped_byte(struct sl_wsrcp_app *rcp_app, uint8_t byte) +static int append_escaped_byte(uint8_t *buffer, uint8_t byte) { if (byte == 0x7D || byte == 0x7E) { - uart_tx_byte(rcp_app, 0x7D); - uart_tx_byte(rcp_app, byte ^ 0x20); + buffer[0] = 0x7D; + buffer[1] = byte ^ 0x20; return 2; } else { - uart_tx_byte(rcp_app, byte); + buffer[0] = byte; return 1; } } -int uart_tx(struct sl_wsrcp_app *rcp_app, const void *buf, int buf_len) +int uart_tx(struct sl_wsrcp_uart *uart_ctxt, const void *buf, int buf_len) { + LDMA_TransferCfg_t ldma_cfg = LDMA_TRANSFER_CFG_PERIPHERAL(UART_LDMA_SIGNAL_TX); + LDMA_Descriptor_t *dma_descr; uint16_t crc = crc16(buf, buf_len); const uint8_t *buf8 = buf; - int i, frame_len; + uint8_t *dma_buf; + int buf_cnt = 0; + size_t xfer_cnt; + + // Only double buffering is supported + BUG_ON(ARRAY_SIZE(uart_ctxt->descr_tx) != 2); + BUG_ON(sizeof(uart_ctxt->buf_tx[0]) > DMADRV_MAX_XFER_COUNT); + + osMutexAcquire(uart_ctxt->tx_lock, osWaitForever); + while (buf_cnt < buf_len) { + dma_buf = uart_ctxt->buf_tx[uart_ctxt->descr_cnt_tx]; + dma_descr = &uart_ctxt->descr_tx[uart_ctxt->descr_cnt_tx]; + xfer_cnt = 0; + while (buf_cnt < buf_len && xfer_cnt < sizeof(uart_ctxt->buf_tx[0]) - 7) { + xfer_cnt += append_escaped_byte(dma_buf + xfer_cnt, buf8[buf_cnt]); + buf_cnt++; + } + if (buf_cnt == buf_len) { + xfer_cnt += append_escaped_byte(dma_buf + xfer_cnt, crc & 0xFF); + xfer_cnt += append_escaped_byte(dma_buf + xfer_cnt, crc >> 8); + dma_buf[xfer_cnt++] = 0x7E; + } + xfer_cnt--; + dma_descr->xfer.xferCnt = xfer_cnt; + osSemaphoreAcquire(uart_ctxt->tx_dma_lock, osWaitForever); + DMADRV_LdmaStartTransfer(uart_ctxt->dma_chan_tx, &ldma_cfg, + dma_descr, uart_handle_tx_dma_complete, uart_ctxt); + uart_ctxt->descr_cnt_tx = (uart_ctxt->descr_cnt_tx + 1) % ARRAY_SIZE(uart_ctxt->descr_tx); + } + osMutexRelease(uart_ctxt->tx_lock); - frame_len = 0; - for (i = 0; i < buf_len; i++) - frame_len += uart_tx_escaped_byte(rcp_app, buf8[i]); - frame_len += uart_tx_escaped_byte(rcp_app, crc & 0xFF); - frame_len += uart_tx_escaped_byte(rcp_app, crc >> 8); - uart_tx_byte(rcp_app, 0x7E); TRACE(TR_HDLC, "hdlc tx: %s (%d bytes)", bytes_str(buf, buf_len, NULL, trace_buffer, sizeof(trace_buffer), DELIM_SPACE | ELLIPSIS_STAR), buf_len); - - return frame_len; + return buf_len; } -int uart_rx(struct sl_wsrcp_app *rcp_app, void *buf, int buf_len) +int uart_rx(struct sl_wsrcp_uart *uart_ctxt, void *buf, int buf_len) { uint8_t *buf8 = buf; uint16_t crc; int i, frame_len; int data; - while (ring_get(&rcp_app->rx_buf, 0) == 0x7E) - ring_pop(&rcp_app->rx_buf); + while (ring_get(&uart_ctxt->rx_ring, 0) == 0x7E) + ring_pop(&uart_ctxt->rx_ring); for (i = 0, data = 0; data != 0x7E; i++) { - data = ring_get(&rcp_app->rx_buf, i); + data = ring_get(&uart_ctxt->rx_ring, i); if (data < 0) return 0; } @@ -117,10 +177,10 @@ int uart_rx(struct sl_wsrcp_app *rcp_app, void *buf, int buf_len) frame_len = 0; do { BUG_ON(frame_len >= buf_len); - data = ring_pop(&rcp_app->rx_buf); + data = ring_pop(&uart_ctxt->rx_ring); BUG_ON(data < 0); if (data == 0x7D) - buf8[frame_len++] = ring_pop(&rcp_app->rx_buf) ^ 0x20; + buf8[frame_len++] = ring_pop(&uart_ctxt->rx_ring) ^ 0x20; else if (data != 0x7E) buf8[frame_len++] = data; } while (data != 0x7E); @@ -130,11 +190,70 @@ int uart_rx(struct sl_wsrcp_app *rcp_app, void *buf, int buf_len) crc = crc16(buf8, frame_len); if (memcmp(buf8 + frame_len, &crc, sizeof(uint16_t))) { WARN("bad crc, frame dropped"); - wsmac_report_rx_crc_error(rcp_app->rcp_mac, *(uint16_t *)(buf8 + frame_len), frame_len, buf8[0], rcp_app->irq_rxof_cnt); - rcp_app->irq_rxof_cnt = 0; + uart_crc_error(uart_ctxt, *(uint16_t *)(buf8 + frame_len), frame_len, buf8[0], uart_ctxt->irq_overflow_cnt); + uart_ctxt->irq_overflow_cnt = 0; return 0; } TRACE(TR_HDLC, "hdlc rx: %s (%d bytes)", bytes_str(buf, frame_len, NULL, trace_buffer, sizeof(trace_buffer), DELIM_SPACE | ELLIPSIS_STAR), frame_len); return frame_len; } + +void uart_init(struct sl_wsrcp_uart *uart_ctxt) +{ + LDMA_TransferCfg_t ldma_cfg = LDMA_TRANSFER_CFG_PERIPHERAL(UART_LDMA_SIGNAL_RX); + unsigned int i, next; + + ring_init(&uart_ctxt->rx_ring, uart_ctxt->rx_ring_data, sizeof(uart_ctxt->rx_ring_data)); + uart_ctxt->tx_lock = osMutexNew(NULL); + uart_ctxt->tx_dma_lock = osSemaphoreNew(1, 1, NULL); + uart_ctxt->hw_regs = UART_PERIPHERAL; + for (i = 0; i < ARRAY_SIZE(uart_ctxt->descr_rx); i++) { + uart_ctxt->descr_rx[i].xfer.structType = ldmaCtrlStructTypeXfer; + uart_ctxt->descr_rx[i].xfer.blockSize = ldmaCtrlBlockSizeUnit1; + uart_ctxt->descr_rx[i].xfer.reqMode = ldmaCtrlReqModeBlock; + uart_ctxt->descr_rx[i].xfer.doneIfs = 1; + + uart_ctxt->descr_rx[i].xfer.size = ldmaCtrlSizeByte; + uart_ctxt->descr_rx[i].xfer.xferCnt = sizeof(uart_ctxt->buf_rx[0]) - 1; + + uart_ctxt->descr_rx[i].xfer.srcInc = ldmaCtrlSrcIncNone; + uart_ctxt->descr_rx[i].xfer.srcAddrMode = ldmaCtrlSrcAddrModeAbs; + uart_ctxt->descr_rx[i].xfer.srcAddr = (uintptr_t)&(uart_ctxt->hw_regs->RXDATA); + + uart_ctxt->descr_rx[i].xfer.dstInc = ldmaCtrlDstIncOne; + uart_ctxt->descr_rx[i].xfer.dstAddrMode = ldmaCtrlDstAddrModeAbs; + uart_ctxt->descr_rx[i].xfer.dstAddr = (uintptr_t)&(uart_ctxt->buf_rx[i]); + + uart_ctxt->descr_rx[i].xfer.linkMode = ldmaLinkModeAbs; + uart_ctxt->descr_rx[i].xfer.link = 1; + + next = i + 1; + next %= ARRAY_SIZE(uart_ctxt->descr_rx); + uart_ctxt->descr_rx[i].xfer.linkAddr = ((uintptr_t)&(uart_ctxt->descr_rx[next])) >> _LDMA_CH_LINK_LINKADDR_SHIFT; + } + + for (i = 0; i < ARRAY_SIZE(uart_ctxt->descr_tx); i++) { + uart_ctxt->descr_tx[i].xfer.structType = ldmaCtrlStructTypeXfer; + uart_ctxt->descr_tx[i].xfer.blockSize = ldmaCtrlBlockSizeUnit1; + uart_ctxt->descr_tx[i].xfer.reqMode = ldmaCtrlReqModeBlock; + uart_ctxt->descr_tx[i].xfer.doneIfs = 1; + + uart_ctxt->descr_tx[i].xfer.size = ldmaCtrlSizeByte; + + uart_ctxt->descr_tx[i].xfer.srcInc = ldmaCtrlDstIncOne; + uart_ctxt->descr_tx[i].xfer.srcAddrMode = ldmaCtrlDstAddrModeAbs; + uart_ctxt->descr_tx[i].xfer.srcAddr = (uintptr_t)&(uart_ctxt->buf_tx[i]); + + uart_ctxt->descr_tx[i].xfer.dstInc = ldmaCtrlSrcIncNone; + uart_ctxt->descr_tx[i].xfer.dstAddrMode = ldmaCtrlSrcAddrModeAbs; + uart_ctxt->descr_tx[i].xfer.dstAddr = (uintptr_t)&(uart_ctxt->hw_regs->TXDATA); + } + uart_hw_init(uart_ctxt); + DMADRV_Init(); + DMADRV_AllocateChannel(&uart_ctxt->dma_chan_tx, NULL); + DMADRV_AllocateChannel(&uart_ctxt->dma_chan_rx, NULL); + DMADRV_LdmaStartTransfer(uart_ctxt->dma_chan_rx, &ldma_cfg, + &(uart_ctxt->descr_rx[0]), + uart_handle_rx_dma_complete, uart_ctxt); +} diff --git a/protocol/wisun/app/wisun_rcp/sl_wsrcp_uart.h b/protocol/wisun/app/wisun_rcp/sl_wsrcp_uart.h index 060b55d6b9..9ffa263aa3 100644 --- a/protocol/wisun/app/wisun_rcp/sl_wsrcp_uart.h +++ b/protocol/wisun/app/wisun_rcp/sl_wsrcp_uart.h @@ -15,12 +15,72 @@ #define SL_WSRCP_UART_H #include +#include +#include +#include +#include +#include -struct sl_wsrcp_app; +#if defined(EUSART_PRESENT) +#include +#else +#include +#endif + +#include "sl_ring.h" + +struct sl_wsrcp_uart { +#if defined(EUSART_PRESENT) + EUSART_TypeDef *hw_regs; +#else + USART_TypeDef *hw_regs; +#endif + + unsigned int dma_chan_tx; + int descr_cnt_tx; + LDMA_Descriptor_t descr_tx[2]; + // Application will be less efficient if a message need to be sent in 2 or + // more buffers. Choose a correct size depending of yours needs. + uint8_t buf_tx[2][1024]; + + unsigned int dma_chan_rx; + int descr_cnt_rx; + LDMA_Descriptor_t descr_rx[16]; + // Reserve enough buffers since interactive session may consume one buffer + // for each char. + uint8_t buf_rx[16][128]; + + osMutexId_t tx_lock; + osSemaphoreId_t tx_dma_lock; + int irq_overflow_cnt; + + // Note it may be possible to drop rx_ring and save 4kB of data. The user + // would get the data directly from buf_rx. However, navigating in buf_rx is + // not easy and is error prone. + struct ring rx_ring; + uint8_t rx_ring_data[4096]; +}; + +void uart_init(struct sl_wsrcp_uart *uart); +int uart_tx(struct sl_wsrcp_uart *uart, const void *buf, int buf_len); +int uart_rx(struct sl_wsrcp_uart *uart, void *buf, int buf_len); + +// Called when a CRC error is detected in receveided frames before the frame is +// discarded. This funtion is declared "weak". So, the user can overload it and +// choose to increment a counter or report the error to the host. +void uart_crc_error(struct sl_wsrcp_uart *uart, uint16_t crc, int frame_len, uint8_t header, uint8_t irq_err_counter); + +// Called from IRQ when new data are available. This funtion is declared "weak". +// So, the user can overload it. The user can post de necessary events from this +// callback (using osEventFlagsSet, osSemaphoreRelease, etc...). The user MUST +// NOT sleep in this function. He should neither handle data in this callback. +void uart_rx_ready(struct sl_wsrcp_uart *uart); + +// Helpers for EUSART and USART drivers +void uart_handle_rx_dma_timeout(struct sl_wsrcp_uart *uart); +void uart_handle_rx_overflow(struct sl_wsrcp_uart *uart); -void uart_init(struct sl_wsrcp_app *rcp_app); -int uart_tx(struct sl_wsrcp_app *rcp_app, const void *buf, int buf_len); -int uart_rx(struct sl_wsrcp_app *rcp_app, void *buf, int buf_len); -void uart_tx_byte(struct sl_wsrcp_app *rcp_app, uint8_t data); +// Must be implemented by EUSART and USART drivers +void uart_hw_init(struct sl_wsrcp_uart *uart); #endif diff --git a/protocol/wisun/app/wisun_rcp/sl_wsrcp_uart_config.h b/protocol/wisun/app/wisun_rcp/sl_wsrcp_uart_config.h new file mode 100644 index 0000000000..23c0718fc9 --- /dev/null +++ b/protocol/wisun/app/wisun_rcp/sl_wsrcp_uart_config.h @@ -0,0 +1,54 @@ +/***************************************************************************//** + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available here[1]. This software is distributed to you in + * Source Code format and is governed by the sections of the MSLA applicable to + * Source Code. + * + * [1] www.silabs.com/about-us/legal/master-software-license-agreement + * + ******************************************************************************/ +#ifndef SL_WSRCP_UART_CONFIG_H +#define SL_WSRCP_UART_CONFIG_H + +#if defined(EUSART_PRESENT) + +#include +#define UART_PERIPHERAL EUSART0 +#define UART_CLOCK cmuClock_EUSART0 +#define UART_RX_IRQ EUSART0_RX_IRQn +#define UART_LDMA_SIGNAL_RX ldmaPeripheralSignal_EUSART0_RXFL +#define UART_LDMA_SIGNAL_TX ldmaPeripheralSignal_EUSART0_TXFL + +#define UART_PORT_TX gpioPortA +#define UART_PIN_TX 8 +#define UART_LOC_TX 0 + +#define UART_PORT_RX gpioPortA +#define UART_PIN_RX 9 +#define UART_LOC_RX 0 + + +#else + +#include +#define UART_PERIPHERAL USART0 +#define UART_CLOCK cmuClock_USART0 +#define UART_RX_IRQ USART0_RX_IRQn +#define UART_LDMA_SIGNAL_RX ldmaPeripheralSignal_USART0_RXDATAV +#define UART_LDMA_SIGNAL_TX ldmaPeripheralSignal_USART0_TXBL + +#define UART_PORT_TX gpioPortA +#define UART_PIN_TX 0 +#define UART_LOC_TX 0 + +#define UART_PORT_RX gpioPortA +#define UART_PIN_RX 1 +#define UART_LOC_RX 0 + +#endif + +#endif diff --git a/protocol/wisun/app/wisun_rcp/sl_wsrcp_usart.c b/protocol/wisun/app/wisun_rcp/sl_wsrcp_usart.c index 1606fa75f6..84d9deb4c3 100644 --- a/protocol/wisun/app/wisun_rcp/sl_wsrcp_usart.c +++ b/protocol/wisun/app/wisun_rcp/sl_wsrcp_usart.c @@ -14,31 +14,28 @@ #include #include +#include #include #include +#include + #include "sl_wsrcp.h" #include "sl_wsrcp_log.h" #include "sl_wsrcp_uart.h" +#include "sl_wsrcp_uart_config.h" +#include "sl_wsrcp_utils.h" -#define UART_PERIPHERAL USART0 -#define UART_PERIPHERAL_NO 0 -#define UART_CLOCK cmuClock_USART0 -#define UART_RX_IRQ USART0_RX_IRQn - -#define UART_TX_PORT gpioPortA -#define UART_TX_PIN 0 -#define UART_TX_LOC 0 +#ifndef USART_ROUTEPEN_TXPEN +#error Not supported +#endif -#define UART_RX_PORT gpioPortA -#define UART_RX_PIN 1 -#define UART_RX_LOC 0 +static struct sl_wsrcp_uart *g_uart_ctxt; -void uart_init(struct sl_wsrcp_app *rcp_app) +void uart_hw_init(struct sl_wsrcp_uart *uart_ctxt) { - USART_InitAsync_TypeDef config = USART_INITASYNC_DEFAULT; + USART_InitAsync_TypeDef uart_cfg = USART_INITASYNC_DEFAULT; - ring_init(&rcp_app->rx_buf, rcp_app->rx_buf_data, sizeof(rcp_app->rx_buf_data)); - rcp_app->sdk_uart = UART_PERIPHERAL; + g_uart_ctxt = uart_ctxt; //CORE_SetNvicRamTableHandler(UART_RX_IRQ, uart_rx_irq); NVIC_ClearPendingIRQ(UART_RX_IRQ); NVIC_EnableIRQ(UART_RX_IRQ); @@ -47,46 +44,46 @@ void uart_init(struct sl_wsrcp_app *rcp_app) #endif CMU_ClockEnable(cmuClock_GPIO, true); CMU_ClockEnable(UART_CLOCK, true); - GPIO_PinModeSet(UART_TX_PORT, UART_TX_PIN, gpioModePushPull, 1); - GPIO_PinModeSet(UART_RX_PORT, UART_RX_PIN, gpioModeInputPull, 1); - config.enable = usartDisable; - USART_InitAsync(rcp_app->sdk_uart, &config); - #if defined(USART_ROUTEPEN_TXPEN) - rcp_app->sdk_uart->ROUTELOC0 &= ~(_USART_ROUTELOC0_TXLOC_MASK | _USART_ROUTELOC0_RXLOC_MASK); - rcp_app->sdk_uart->ROUTELOC0 |= UART_TX_LOC << _USART_ROUTELOC0_TXLOC_SHIFT; - rcp_app->sdk_uart->ROUTELOC0 |= UART_RX_LOC << _USART_ROUTELOC0_RXLOC_SHIFT; - rcp_app->sdk_uart->ROUTEPEN = USART_ROUTEPEN_TXPEN | USART_ROUTEPEN_RXPEN; - #else - #error Not supported - #endif - rcp_app->sdk_uart->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX; - USART_IntClear(rcp_app->sdk_uart, 0xFFFFFFFF); - USART_IntEnable(rcp_app->sdk_uart, USART_IF_RXDATAV); - USART_Enable(rcp_app->sdk_uart, usartEnable); + GPIO_PinModeSet(UART_PORT_TX, UART_PIN_TX, gpioModePushPull, 1); + GPIO_PinModeSet(UART_PORT_RX, UART_PIN_RX, gpioModeInputPull, 1); + + uart_cfg.enable = usartDisable; + USART_InitAsync(uart_ctxt->hw_regs, &uart_cfg); + + uart_ctxt->hw_regs->ROUTELOC0 &= ~(_USART_ROUTELOC0_TXLOC_MASK | _USART_ROUTELOC0_RXLOC_MASK); + uart_ctxt->hw_regs->ROUTELOC0 |= UART_LOC_TX << _USART_ROUTELOC0_TXLOC_SHIFT; + uart_ctxt->hw_regs->ROUTELOC0 |= UART_LOC_RX << _USART_ROUTELOC0_RXLOC_SHIFT; + uart_ctxt->hw_regs->ROUTEPEN = USART_ROUTEPEN_TXPEN | USART_ROUTEPEN_RXPEN; + uart_ctxt->hw_regs->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX; + uart_ctxt->hw_regs->TIMECMP1 = USART_TIMECMP1_TSTOP_RXACT | \ + USART_TIMECMP1_TSTART_RXEOF | \ + USART_TIMECMP1_RESTARTEN | \ + (0xff << _USART_TIMECMP1_TCMPVAL_SHIFT); + + USART_IntClear(uart_ctxt->hw_regs, 0xFFFFFFFF); + //USART_IntEnable(uart_ctxt->hw_regs, USART_IF_RXDATAV); + USART_IntEnable(uart_ctxt->hw_regs, USART_IF_RXOF); + USART_IntEnable(uart_ctxt->hw_regs, USART_IF_TCMP1); + USART_Enable(uart_ctxt->hw_regs, usartEnable); } void USART0_RX_IRQHandler(void) { - struct sl_wsrcp_app *rcp_app = &g_rcp_ctxt; - int ret; + struct sl_wsrcp_uart *uart_ctxt = g_uart_ctxt; - if (!(rcp_app->sdk_uart->STATUS & USART_STATUS_RXDATAV)) { - WARN("unexpected IRQ"); + BUG_ON(!uart_ctxt); + if (uart_ctxt->hw_regs->IF & USART_IF_TCMP1) { + uart_handle_rx_dma_timeout(uart_ctxt); + uart_ctxt->hw_regs->TIMECMP1 &= ~_USART_TIMECMP1_TSTART_MASK; + uart_ctxt->hw_regs->TIMECMP1 |= USART_TIMECMP1_TSTART_RXEOF; + USART_IntClear(uart_ctxt->hw_regs, USART_IF_TCMP1); return; } - - if ((rcp_app->sdk_uart->IF & USART_IF_RXOF)) { - WARN("RX buffer overflow"); - USART_IntClear(rcp_app->sdk_uart, USART_IF_RXOF); - rcp_app->irq_rxof_cnt++; + if (uart_ctxt->hw_regs->IF & USART_IF_RXOF) { + uart_handle_rx_overflow(uart_ctxt); + USART_IntClear(uart_ctxt->hw_regs, USART_IF_RXOF); + return; } - ret = ring_push(&rcp_app->rx_buf, USART_Rx(rcp_app->sdk_uart)); - BUG_ON(ret, "buffer overflow"); - osEventFlagsSet(rcp_app->main_events, RX_UART); -} - -void uart_tx_byte(struct sl_wsrcp_app *rcp_app, uint8_t data) -{ - USART_Tx(rcp_app->sdk_uart, data); + WARN("unexpected IRQ"); } diff --git a/protocol/wisun/app/wisun_rcp/sl_wsrcp_utils.h b/protocol/wisun/app/wisun_rcp/sl_wsrcp_utils.h new file mode 100644 index 0000000000..db7bcbd14f --- /dev/null +++ b/protocol/wisun/app/wisun_rcp/sl_wsrcp_utils.h @@ -0,0 +1,41 @@ +/***************************************************************************//** + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available here[1]. This software is distributed to you in + * Source Code format and is governed by the sections of the MSLA applicable to + * Source Code. + * + * [1] www.silabs.com/about-us/legal/master-software-license-agreement + * + ******************************************************************************/ +#ifndef SL_WSRCP_UTILS_H +#define SL_WSRCP_UTILS_H + +#include +#include +#include +#include + +#define min(x, y) ({ \ + typeof(x) _x = (x); \ + typeof(y) _y = (y); \ + _x < _y ? _x : _y; \ +}) + +#define max(x, y) ({ \ + typeof(x) _x = (x); \ + typeof(y) _y = (y); \ + _x > _y ? _x : _y; \ +}) + +#define container_of(ptr, type, member) (type *)((uintptr_t)(ptr) - ((uintptr_t)(&((type *)0)->member))) +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) + +#define __CTZ(value) __builtin_ctz(value) +#define FIELD_GET(mask, reg) (((reg) & (mask)) >> __CTZ(mask)) +#define FIELD_PREP(mask, val) (((val) << __CTZ(mask)) & (mask)) + +#endif diff --git a/protocol/wisun/component/wisun_rcp.slcc b/protocol/wisun/component/wisun_rcp.slcc index 61ac111941..3e34aa4c04 100644 --- a/protocol/wisun/component/wisun_rcp.slcc +++ b/protocol/wisun/component/wisun_rcp.slcc @@ -15,6 +15,7 @@ requires: - name: "wisun_mac" - name: "wisun_radioconf" - name: "micriumos_kernel" + - name: "dmadrv" - name: "emlib_usart" condition: - device_sdid_84 @@ -35,15 +36,19 @@ include: - path: "sl_micrium_debug.h" - path: "sl_ring.h" - path: "sl_wsrcp.h" + - path: "sl_wsrcp_crc.h" - path: "sl_wsrcp_log.h" - path: "sl_wsrcp_mac.h" + - path: "sl_wsrcp_utils.h" - path: "sl_wsrcp_uart.h" + - path: "sl_wsrcp_uart_config.h" source: - path: "sl_micrium_debug.c" - path: "sl_ring.c" - path: "sl_wsrcp.c" - path: "sl_wsrcp_os_main.c" + - path: "sl_wsrcp_crc.c" - path: "sl_wsrcp_uart.c" - path: "sl_wsrcp_usart.c" condition: [emlib_usart] diff --git a/protocol/wisun/rail/device_sdid_220/radio_settings.radioconf b/protocol/wisun/rail/device_sdid_220/radio_settings.radioconf index fee917c2c1..259cfb14c3 100644 --- a/protocol/wisun/rail/device_sdid_220/radio_settings.radioconf +++ b/protocol/wisun/rail/device_sdid_220/radio_settings.radioconf @@ -159,7 +159,7 @@ SAME_AS_FIRST_CHANNEL 20480 - 20508 + 20514 RAIL_TX_POWER_MAX PHY_IEEE802154_WISUN_868MHz_OFDM_OPT4_EU diff --git a/protocol/wisun/stack/inc/sl_wisun_version.h b/protocol/wisun/stack/inc/sl_wisun_version.h index fcbe03b24f..8c32ffbb6d 100644 --- a/protocol/wisun/stack/inc/sl_wisun_version.h +++ b/protocol/wisun/stack/inc/sl_wisun_version.h @@ -40,7 +40,7 @@ #endif #ifndef SL_WISUN_VERSION_PATCH -#define SL_WISUN_VERSION_PATCH 0 +#define SL_WISUN_VERSION_PATCH 1 #endif #define FORMAT_WISUN_STACK_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) diff --git a/protocol/wisun/stack/libwisun_mac_efr32xg1x.a b/protocol/wisun/stack/libwisun_mac_efr32xg1x.a index e1df4dd50c..288e691ef7 100644 --- a/protocol/wisun/stack/libwisun_mac_efr32xg1x.a +++ b/protocol/wisun/stack/libwisun_mac_efr32xg1x.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:422a74a3b47fd3034e517b40e19b9ab0d9b433219722d629ef9cc54d0dc99641 -size 1472004 +oid sha256:1e86d4847286cf13fde584952e2b5d381a7941e871d871532bf8cbacb35dde12 +size 1471660 diff --git a/protocol/wisun/stack/libwisun_mac_efr32xg2x.a b/protocol/wisun/stack/libwisun_mac_efr32xg2x.a index b8dee015ba..05ff96e7ff 100644 --- a/protocol/wisun/stack/libwisun_mac_efr32xg2x.a +++ b/protocol/wisun/stack/libwisun_mac_efr32xg2x.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0fe34bb61275d9dace59be3ef9ca80bcb514613043a7242c77507b4286426bfc -size 1529080 +oid sha256:3216be1d3b5da1b28092542348b9dd69c40722976918db4be2a2c1a06edfbc91 +size 1528744 diff --git a/protocol/wisun/stack/libwisun_rcp_efr32xg1x.a b/protocol/wisun/stack/libwisun_rcp_efr32xg1x.a index 8134d06aac..79b8c04c4c 100644 --- a/protocol/wisun/stack/libwisun_rcp_efr32xg1x.a +++ b/protocol/wisun/stack/libwisun_rcp_efr32xg1x.a @@ -1,3 +1,3 @@ version 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b/protocol/wisun/stack/libwisun_router_efr32xg1x_freertos_gcc_debug.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:349a212a4d5a872e0802bcefbd74e208f56c42d05ef24bd3195f30ce15f51fda -size 8627242 +oid sha256:da03b0b326a7b38310197e59f2fb20dafdd6eb99565ea6427259f99c8977340f +size 8635822 diff --git a/protocol/wisun/stack/libwisun_router_efr32xg1x_freertos_gcc_release.a b/protocol/wisun/stack/libwisun_router_efr32xg1x_freertos_gcc_release.a index d472ce8e4a..e14ed7da24 100644 --- a/protocol/wisun/stack/libwisun_router_efr32xg1x_freertos_gcc_release.a +++ b/protocol/wisun/stack/libwisun_router_efr32xg1x_freertos_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e404ab7fbf28cbcdcb28e7d7aa03c0416badc7235f7c4258218b44cb2321dd45 -size 8304316 +oid sha256:6cb4fbe691eecb38f3a074ad0e1de9cd5b1f09a114da5b00e9a1f6481cc8e5ae +size 8312624 diff --git a/protocol/wisun/stack/libwisun_router_efr32xg1x_freertos_iar_debug.a b/protocol/wisun/stack/libwisun_router_efr32xg1x_freertos_iar_debug.a index 4fa79aa910..4a4eaa289e 100644 --- a/protocol/wisun/stack/libwisun_router_efr32xg1x_freertos_iar_debug.a +++ b/protocol/wisun/stack/libwisun_router_efr32xg1x_freertos_iar_debug.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d39221b824311fa70715326d32901884dd7de5b1d1a34dee58b6143488f02c6e -size 4192664 +oid sha256:0619fe0319c10a73b7fcf57746f88fef43bc32fbad680ad9cca2149f12849a41 +size 4186052 diff --git a/protocol/wisun/stack/libwisun_router_efr32xg1x_freertos_iar_release.a b/protocol/wisun/stack/libwisun_router_efr32xg1x_freertos_iar_release.a index 98d99087c8..86b1398714 100644 --- a/protocol/wisun/stack/libwisun_router_efr32xg1x_freertos_iar_release.a +++ b/protocol/wisun/stack/libwisun_router_efr32xg1x_freertos_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7b445f87748a816ee416986695a0f1052f10c7f020f7bb31280870d7045ada8d -size 3804490 +oid sha256:8b5283b25a292e699779c15392c7aecfbde50d3915023b6ca059f2bbb5b21ba1 +size 3798032 diff --git a/protocol/wisun/stack/libwisun_router_efr32xg1x_micriumos_gcc_debug.a b/protocol/wisun/stack/libwisun_router_efr32xg1x_micriumos_gcc_debug.a index 39cce3abbc..f6fe25f9d2 100644 --- a/protocol/wisun/stack/libwisun_router_efr32xg1x_micriumos_gcc_debug.a +++ b/protocol/wisun/stack/libwisun_router_efr32xg1x_micriumos_gcc_debug.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2f8de71fdfdf3e76da8437811f6c9b2e85a84100ac752f3d41389b9abfe30af0 -size 8627286 +oid sha256:80b0d6f114fa843ff4b3aa855457679fa6cf0dd556b9c0757830e4bbaa45e9ca +size 8635866 diff --git a/protocol/wisun/stack/libwisun_router_efr32xg1x_micriumos_gcc_release.a b/protocol/wisun/stack/libwisun_router_efr32xg1x_micriumos_gcc_release.a index 78c326bd0f..3618bfd698 100644 --- a/protocol/wisun/stack/libwisun_router_efr32xg1x_micriumos_gcc_release.a +++ b/protocol/wisun/stack/libwisun_router_efr32xg1x_micriumos_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2ba69c8538ffabdcfab09a9e49261d6bb78092c6124f9c733bd17d0ae0938fc3 -size 8304356 +oid sha256:82814ada9d7f519d901b1280c1599ea4b35ee21f00d527eda6f24eba55105428 +size 8312668 diff --git a/protocol/wisun/stack/libwisun_router_efr32xg1x_micriumos_iar_debug.a b/protocol/wisun/stack/libwisun_router_efr32xg1x_micriumos_iar_debug.a index 58147612b9..db22a66630 100644 --- a/protocol/wisun/stack/libwisun_router_efr32xg1x_micriumos_iar_debug.a +++ b/protocol/wisun/stack/libwisun_router_efr32xg1x_micriumos_iar_debug.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0cd6637589b9ced0c25a200c7f4a11b688eb08d9e2db27aad175544a2cf3c34e -size 4114346 +oid sha256:2d75c38dbba9f5b8b57f2dc772abf0d4329f6a23a369e124147297d822610f38 +size 4108254 diff --git a/protocol/wisun/stack/libwisun_router_efr32xg1x_micriumos_iar_release.a b/protocol/wisun/stack/libwisun_router_efr32xg1x_micriumos_iar_release.a index a67f1c468a..95f55b6cdc 100644 --- a/protocol/wisun/stack/libwisun_router_efr32xg1x_micriumos_iar_release.a +++ b/protocol/wisun/stack/libwisun_router_efr32xg1x_micriumos_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5fd1c2137f713bc5397222c811bcffd3e769184fa5e1240a96f8c6ea15f4ba32 -size 3726172 +oid sha256:b8a827d4b9f5b17d61d7c14888752b106e7eb6b5b57b5d9a69d48d2e1f651d13 +size 3720230 diff --git a/protocol/wisun/stack/libwisun_router_efr32xg2x_freertos_gcc_debug.a b/protocol/wisun/stack/libwisun_router_efr32xg2x_freertos_gcc_debug.a index 732cc07a1c..4fae0fe836 100644 --- a/protocol/wisun/stack/libwisun_router_efr32xg2x_freertos_gcc_debug.a +++ b/protocol/wisun/stack/libwisun_router_efr32xg2x_freertos_gcc_debug.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a2ce2959f143ea7317ef454519f9d63547e5d8a28d536111354daf31f99b7b5d -size 8693950 +oid sha256:2433abb42f771ee43ac35da08215c976ec6c786038f75425a5997df48e6b6e03 +size 8702658 diff --git a/protocol/wisun/stack/libwisun_router_efr32xg2x_freertos_gcc_release.a b/protocol/wisun/stack/libwisun_router_efr32xg2x_freertos_gcc_release.a index 6cbf8d7f1d..9a9fdbf3c0 100644 --- a/protocol/wisun/stack/libwisun_router_efr32xg2x_freertos_gcc_release.a +++ b/protocol/wisun/stack/libwisun_router_efr32xg2x_freertos_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:077b145239265418b06f1819d2d52cd9ae9d1be01fdb61c9c7f2a48defaa55d2 -size 8369104 +oid sha256:4b4a787ec70f93024c8e611367aece1e00181a4cd4a72724ad6adb45d26ab033 +size 8377336 diff --git a/protocol/wisun/stack/libwisun_router_efr32xg2x_freertos_iar_debug.a b/protocol/wisun/stack/libwisun_router_efr32xg2x_freertos_iar_debug.a index 5eeb116c71..c2c4c15cc4 100644 --- a/protocol/wisun/stack/libwisun_router_efr32xg2x_freertos_iar_debug.a +++ b/protocol/wisun/stack/libwisun_router_efr32xg2x_freertos_iar_debug.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b261797a85ac02de55f0e6ed61d665e7326a55b88b34aec6c9f8c5fd24127f70 -size 4218894 +oid sha256:a7d50bd57650b205755a234d4c3ff805f748f1dd4e5cd7a6e2e50d18c250562e +size 4211742 diff --git a/protocol/wisun/stack/libwisun_router_efr32xg2x_freertos_iar_release.a b/protocol/wisun/stack/libwisun_router_efr32xg2x_freertos_iar_release.a index d5f00b69fe..fbfc26e999 100644 --- a/protocol/wisun/stack/libwisun_router_efr32xg2x_freertos_iar_release.a +++ b/protocol/wisun/stack/libwisun_router_efr32xg2x_freertos_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:78c6cbe39b0822e5cd4d5f6d71e5b5b169e32ea167a993b8769bfa031980e2ed -size 3828308 +oid sha256:895b484a420b4c260eb40ada983cefe83d48b6ed707fa111524022bef554e698 +size 3822256 diff --git a/protocol/wisun/stack/libwisun_router_efr32xg2x_micriumos_gcc_debug.a b/protocol/wisun/stack/libwisun_router_efr32xg2x_micriumos_gcc_debug.a index a3c5b76264..8cb8dca3e3 100644 --- a/protocol/wisun/stack/libwisun_router_efr32xg2x_micriumos_gcc_debug.a +++ b/protocol/wisun/stack/libwisun_router_efr32xg2x_micriumos_gcc_debug.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:64d2a42a0c2dbe306b21483075c2618e594dcea623d94918f279276b72751c78 -size 8693994 +oid sha256:de84b59b427e1b96e8aaa845298c445901b41d87b7cf2818a97fb0b7943cc091 +size 8702698 diff --git a/protocol/wisun/stack/libwisun_router_efr32xg2x_micriumos_gcc_release.a b/protocol/wisun/stack/libwisun_router_efr32xg2x_micriumos_gcc_release.a index f3cfa09e22..f0d9b8e57c 100644 --- a/protocol/wisun/stack/libwisun_router_efr32xg2x_micriumos_gcc_release.a +++ b/protocol/wisun/stack/libwisun_router_efr32xg2x_micriumos_gcc_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ae5a28240ee19be203d85c98dfd2610dfac5a0e840c8d30d4c0f512e98011973 -size 8369148 +oid sha256:f2b888e4189b4d2ca38f504931461b3e20924b205149e17de512dc0c21744f9f +size 8377380 diff --git a/protocol/wisun/stack/libwisun_router_efr32xg2x_micriumos_iar_debug.a b/protocol/wisun/stack/libwisun_router_efr32xg2x_micriumos_iar_debug.a index 3826129a8c..52b23ccf49 100644 --- a/protocol/wisun/stack/libwisun_router_efr32xg2x_micriumos_iar_debug.a +++ b/protocol/wisun/stack/libwisun_router_efr32xg2x_micriumos_iar_debug.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:240897e789a7c825d3b20f841859bc55f96d875a44594895e0456c981914af50 -size 4140118 +oid sha256:c6aaef6374bed273a81970048dfb233b95622c6c0643c178b6b4d60bc38e5c6e +size 4133496 diff --git a/protocol/wisun/stack/libwisun_router_efr32xg2x_micriumos_iar_release.a b/protocol/wisun/stack/libwisun_router_efr32xg2x_micriumos_iar_release.a index 8ff67732f8..3fdf600bb9 100644 --- a/protocol/wisun/stack/libwisun_router_efr32xg2x_micriumos_iar_release.a +++ b/protocol/wisun/stack/libwisun_router_efr32xg2x_micriumos_iar_release.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fe8a10e9d925ade89f1df7fbb5588110e28010a606282067a3a66f4d2668381b -size 3749532 +oid sha256:f07c5022ee352f7041196e801835cf059b7abd7f56e6a50024496e0cb0b74411 +size 3744006 diff --git a/protocol/z-wave/Apps/DoorLockKeyPad/DoorLockKeyPad.c b/protocol/z-wave/Apps/DoorLockKeyPad/DoorLockKeyPad.c index c8a9304038..1da5b3df08 100644 --- a/protocol/z-wave/Apps/DoorLockKeyPad/DoorLockKeyPad.c +++ b/protocol/z-wave/Apps/DoorLockKeyPad/DoorLockKeyPad.c @@ -13,7 +13,7 @@ #include #include "SizeOf.h" #include "Assert.h" - +#include //#define DEBUGPRINT #include "DebugPrint.h" #include "DebugPrintConfig.h" @@ -177,7 +177,7 @@ static const SAppNodeInfo_t AppNodeInfo = .CommandClasses.SecureIncludedSecureCC.pCommandClasses = cmdClassListSecure }; -static const SRadioConfig_t RadioConfig = +static SRadioConfig_t RadioConfig = { .iListenBeforeTalkThreshold = ELISTENBEFORETALKTRESHOLD_DEFAULT, .iTxPowerLevelMax = APP_MAX_TX_POWER, @@ -614,8 +614,6 @@ ZW_APPLICATION_STATUS ApplicationInit(EResetReason_t eResetReason) zpal_get_app_version_patch(), ZAF_BUILD_NO); - DPRINTF("ApplicationInit eResetReason = %d\n", eResetReason); - CC_Indicator_Init(indicator_set_handler); memset((uint8_t *)&myDoorLock, 0x00, sizeof(myDoorLock)); @@ -624,6 +622,18 @@ ZW_APPLICATION_STATUS ApplicationInit(EResetReason_t eResetReason) // Init file system ApplicationFileSystemInit(&pFileSystemApplication); + // Read Rf region from MFG_ZWAVE_COUNTRY_FREQ + zpal_radio_region_t regionMfg; + ZW_GetMfgTokenDataCountryFreq((void*) ®ionMfg); + if (isRfRegionValid(regionMfg)) { + RadioConfig.eRegion = regionMfg; + } else { + ZW_SetMfgTokenDataCountryRegion((void*) &RadioConfig.eRegion); + } + + DPRINTF("Rf region: %d\n", RadioConfig.eRegion); + DPRINTF("ApplicationInit eResetReason = %d\n", eResetReason); + /************************************************************************************* * CREATE USER TASKS - ZW_ApplicationRegisterTask() and ZW_UserTask_CreateTask() ************************************************************************************* diff --git a/protocol/z-wave/Apps/DoorLockKeyPad/config_app.h b/protocol/z-wave/Apps/DoorLockKeyPad/config_app.h index 15a639b294..712c534bf2 100644 --- a/protocol/z-wave/Apps/DoorLockKeyPad/config_app.h +++ b/protocol/z-wave/Apps/DoorLockKeyPad/config_app.h @@ -88,11 +88,6 @@ #define DEFAULT_USERCODE {'1', '2', '3', '4'} //@ [DEFAULT_USERCODE_ID] -/** - * Max notifications types - */ -#define MAX_NOTIFICATIONS 1 - /** * Security keys */ diff --git a/protocol/z-wave/Apps/LEDBulb/LEDBulb.c b/protocol/z-wave/Apps/LEDBulb/LEDBulb.c index 3c092153a5..a00adfaf8a 100644 --- a/protocol/z-wave/Apps/LEDBulb/LEDBulb.c +++ b/protocol/z-wave/Apps/LEDBulb/LEDBulb.c @@ -13,6 +13,7 @@ #include #include "SizeOf.h" #include "Assert.h" +#include #include "DebugPrintConfig.h" //#define DEBUGPRINT #include "DebugPrint.h" @@ -176,7 +177,7 @@ static const SAppNodeInfo_t AppNodeInfo = .CommandClasses.SecureIncludedSecureCC.pCommandClasses = cmdClassListSecure }; -static const SRadioConfig_t RadioConfig = +static SRadioConfig_t RadioConfig = { .iListenBeforeTalkThreshold = ELISTENBEFORETALKTRESHOLD_DEFAULT, .iTxPowerLevelMax = APP_MAX_TX_POWER, @@ -577,6 +578,15 @@ ApplicationInit(EResetReason_t eResetReason) // Init file system ApplicationFileSystemInit(&pFileSystemApplication); + // Read Rf region from MFG_ZWAVE_COUNTRY_FREQ + zpal_radio_region_t regionMfg; + ZW_GetMfgTokenDataCountryFreq((void*) ®ionMfg); + if (isRfRegionValid(regionMfg)) { + RadioConfig.eRegion = regionMfg; + } else { + ZW_SetMfgTokenDataCountryRegion((void*) &RadioConfig.eRegion); + } + /************************************************************************************* * CREATE USER TASKS - ZW_ApplicationRegisterTask() and ZW_UserTask_CreateTask() ************************************************************************************* diff --git a/protocol/z-wave/Apps/PowerStrip/PowerStrip.c b/protocol/z-wave/Apps/PowerStrip/PowerStrip.c index f73571fbfe..68fe4f1396 100644 --- a/protocol/z-wave/Apps/PowerStrip/PowerStrip.c +++ b/protocol/z-wave/Apps/PowerStrip/PowerStrip.c @@ -13,6 +13,7 @@ #include #include "SizeOf.h" #include "Assert.h" +#include #include "DebugPrintConfig.h" //#define DEBUGPRINT #include "DebugPrint.h" @@ -181,7 +182,7 @@ static SAppNodeInfo_t AppNodeInfo = .CommandClasses.SecureIncludedSecureCC.pCommandClasses = cmdClassListSecure }; -static const SRadioConfig_t RadioConfig = +static SRadioConfig_t RadioConfig = { .iListenBeforeTalkThreshold = ELISTENBEFORETALKTRESHOLD_DEFAULT, .iTxPowerLevelMax = APP_MAX_TX_POWER, @@ -753,6 +754,14 @@ ApplicationInit(EResetReason_t eResetReason) // Init file system ApplicationFileSystemInit(&pFileSystemApplication); + // Read Rf region from MFG_ZWAVE_COUNTRY_FREQ + zpal_radio_region_t regionMfg; + ZW_GetMfgTokenDataCountryFreq((void*) ®ionMfg); + if (isRfRegionValid(regionMfg)) { + RadioConfig.eRegion = regionMfg; + } else { + ZW_SetMfgTokenDataCountryRegion((void*) &RadioConfig.eRegion); + } /************************************************************************************* * CREATE USER TASKS - ZW_ApplicationRegisterTask() and ZW_UserTask_CreateTask() @@ -1502,13 +1511,14 @@ ZCB_NotificationTimerCallback(SSwTimer *pTimer) ZCB_JobStatus(&transmissionResult); } - /* Trigger TSE */ - if (pData) + NOTIFICATION_STATUS notification_enable = CmdClassNotificationGetNotificationStatus(NOTIFICATION_TYPE_POWER_MANAGEMENT, notificationOverLoadendpoint); + if (pData && (NOTIFICATION_STATUS_UNSOLICIT_ACTIVATED == notification_enable)) { + /* Trigger TSE */ ZAF_TSE_Trigger(CC_Notification_report_stx, pData, true); + ChangeState(STATE_APP_TRANSMIT_DATA); } - ChangeState(STATE_APP_TRANSMIT_DATA); } static void ToggleSwitch(uint8_t switchID) diff --git a/protocol/z-wave/Apps/PowerStrip/config_app.h b/protocol/z-wave/Apps/PowerStrip/config_app.h index 61b7dbcdf0..e2d90644a0 100644 --- a/protocol/z-wave/Apps/PowerStrip/config_app.h +++ b/protocol/z-wave/Apps/PowerStrip/config_app.h @@ -78,6 +78,11 @@ #define MAX_ASSOCIATION_GROUPS 4 #define MAX_ASSOCIATION_IN_GROUP 5 +/** + * @brief Maximum number of notification groups for storing End Points - Notification Type pairs. + */ +#define MAX_NUM_OF_NOTIFICATION_GROUPS 2 + /* * File identifiers for application file system * Range: 0x00000 - 0x0FFFF @@ -99,14 +104,6 @@ //@ [AGI_TABLE_ID] -/** - * Configuration for ApplicationUtilities/notification.h + .c - * - * Set to NUMBER_OF_ENDPOINTS because there'is one notification for each endpoint. - */ -#define MAX_NOTIFICATIONS NUMBER_OF_ENDPOINTS - - /** * Security keys */ diff --git a/protocol/z-wave/Apps/SensorPIR/SensorPIR.c b/protocol/z-wave/Apps/SensorPIR/SensorPIR.c index d0717a47af..414ee6bccc 100644 --- a/protocol/z-wave/Apps/SensorPIR/SensorPIR.c +++ b/protocol/z-wave/Apps/SensorPIR/SensorPIR.c @@ -13,8 +13,8 @@ #include "SizeOf.h" #include "Assert.h" +#include #include "DebugPrintConfig.h" - //#define DEBUGPRINT #include "DebugPrint.h" #include "config_app.h" @@ -213,7 +213,7 @@ static const SAppNodeInfo_t AppNodeInfo = .CommandClasses.SecureIncludedSecureCC.pCommandClasses = cmdClassListSecure }; -static const SRadioConfig_t RadioConfig = +static SRadioConfig_t RadioConfig = { .iListenBeforeTalkThreshold = ELISTENBEFORETALKTRESHOLD_DEFAULT, .iTxPowerLevelMax = APP_MAX_TX_POWER, @@ -635,6 +635,15 @@ ApplicationInit(EResetReason_t eResetReason) // Init file system ApplicationFileSystemInit(&pFileSystemApplication); + // Read Rf region from MFG_ZWAVE_COUNTRY_FREQ + zpal_radio_region_t regionMfg; + ZW_GetMfgTokenDataCountryFreq((void*) ®ionMfg); + if (isRfRegionValid(regionMfg)) { + RadioConfig.eRegion = regionMfg; + } else { + ZW_SetMfgTokenDataCountryRegion((void*) &RadioConfig.eRegion); + } + /************************************************************************************* * CREATE USER TASKS - ZW_ApplicationRegisterTask() and ZW_UserTask_CreateTask() ************************************************************************************* diff --git a/protocol/z-wave/Apps/SensorPIR/config_app.h b/protocol/z-wave/Apps/SensorPIR/config_app.h index 4bc2f20624..e0673d3832 100644 --- a/protocol/z-wave/Apps/SensorPIR/config_app.h +++ b/protocol/z-wave/Apps/SensorPIR/config_app.h @@ -91,9 +91,9 @@ //@ [AGI_TABLE_ID] /** - * Max notifications types + * Maximum number of notification groups for storing End Points - Notification Type pairs. */ -#define MAX_NOTIFICATIONS 1 +#define MAX_NUM_OF_NOTIFICATION_GROUPS 1 /** * The value basic set command should use when an event occur. diff --git a/protocol/z-wave/Apps/SerialAPI/SerialAPI_Controller.slcp b/protocol/z-wave/Apps/SerialAPI/SerialAPI_Controller.slcp index dcc3f4d930..e288c1a94e 100644 --- a/protocol/z-wave/Apps/SerialAPI/SerialAPI_Controller.slcp +++ b/protocol/z-wave/Apps/SerialAPI/SerialAPI_Controller.slcp @@ -58,14 +58,13 @@ include: - path: virtual_slave_node_info.h - path: app.h - path: config_app.h -requires: - - name: iostream_swo - condition: [zw_debug] configuration: - name: NVM3_DEFAULT_MAX_OBJECT_SIZE value: 1900 - name: NVM3_DEFAULT_CACHE_SIZE value: 100 + - name: SL_BOARD_ENABLE_VCOM + value: 1 - name: SL_DEVICE_INIT_EMU_EM4_STATE value: emuEM4Hibernate - name: SL_DEVICE_INIT_EMU_EM4_RETAIN_LFRCO diff --git a/protocol/z-wave/Apps/SerialAPI/SerialAPI_Slave.slcp b/protocol/z-wave/Apps/SerialAPI/SerialAPI_Slave.slcp index fb04ed2e2a..3e9157c5a9 100644 --- a/protocol/z-wave/Apps/SerialAPI/SerialAPI_Slave.slcp +++ b/protocol/z-wave/Apps/SerialAPI/SerialAPI_Slave.slcp @@ -58,14 +58,13 @@ include: - path: virtual_slave_node_info.h - path: app.h - path: config_app.h -requires: - - name: iostream_swo - condition: [zw_debug] configuration: - name: NVM3_DEFAULT_MAX_OBJECT_SIZE value: 1900 - name: NVM3_DEFAULT_CACHE_SIZE value: 100 + - name: SL_BOARD_ENABLE_VCOM + value: 1 - name: SL_DEVICE_INIT_EMU_EM4_STATE value: emuEM4Hibernate - name: SL_DEVICE_INIT_EMU_EM4_RETAIN_LFRCO diff --git a/protocol/z-wave/Apps/SerialAPI/cmd_handlers.c b/protocol/z-wave/Apps/SerialAPI/cmd_handlers.c index 3f7b405503..caefa5218e 100644 --- a/protocol/z-wave/Apps/SerialAPI/cmd_handlers.c +++ b/protocol/z-wave/Apps/SerialAPI/cmd_handlers.c @@ -869,24 +869,19 @@ ZW_ADD_CMD(FUNC_ID_MEMORY_GET_ID) { UNUSED(frame); + uint8_t i = 0; /* */ - compl_workbuf[0] = (uint8_t) ((g_pAppHandles->pNetworkInfo->HomeId & 0xff000000) >> 24); - compl_workbuf[1] = (uint8_t) ((g_pAppHandles->pNetworkInfo->HomeId & 0x00ff0000) >> 16); - compl_workbuf[2] = (uint8_t) ((g_pAppHandles->pNetworkInfo->HomeId & 0x0000ff00) >> 8); - compl_workbuf[3] = (uint8_t) (g_pAppHandles->pNetworkInfo->HomeId & 0x000000ff); + compl_workbuf[i++] = (uint8_t) ((g_pAppHandles->pNetworkInfo->HomeId & 0xff000000) >> 24); + compl_workbuf[i++] = (uint8_t) ((g_pAppHandles->pNetworkInfo->HomeId & 0x00ff0000) >> 16); + compl_workbuf[i++] = (uint8_t) ((g_pAppHandles->pNetworkInfo->HomeId & 0x0000ff00) >> 8); + compl_workbuf[i++] = (uint8_t) (g_pAppHandles->pNetworkInfo->HomeId & 0x000000ff); if (SERIAL_API_SETUP_NODEID_BASE_TYPE_16_BIT == nodeIdBaseType) { // 16 bit nodeID - compl_workbuf[4] = (uint8_t)(g_pAppHandles->pNetworkInfo->NodeId >> 8); // MSB - compl_workbuf[5] = (uint8_t)(g_pAppHandles->pNetworkInfo->NodeId & 0xFF); // LSB - DoRespond_workbuf(6); - } - else - { - // Legacy 8 bit nodeID - compl_workbuf[4] = (uint8_t)(g_pAppHandles->pNetworkInfo->NodeId & 0xFF); - DoRespond_workbuf(5); + compl_workbuf[i++] = (uint8_t)(g_pAppHandles->pNetworkInfo->NodeId >> 8); // MSB(16bit) } + compl_workbuf[i++] = (uint8_t)(g_pAppHandles->pNetworkInfo->NodeId & 0xFF); // LSB(16bit)/8bit + DoRespond_workbuf(i); } #endif @@ -1399,13 +1394,13 @@ ZW_ADD_CMD(FUNC_ID_ZW_ADD_NODE_TO_NETWORK) #if defined (SUPPORT_ZW_REMOVE_NODE_ID_FROM_NETWORK) && (SUPPORT_ZW_REMOVE_NODE_ID_FROM_NETWORK == 1) static void RemoveNodeFromNetwork(uint8_t mode, node_id_t node_id, void (*pCallBack)(LEARN_INFO_T *statusInfo)) { - SZwaveCommandPackage pCmdPackage = { - .eCommandType = EZWAVECOMMANDTYPE_REMOVE_NODE_FROM_NETWORK, - .uCommandParams.NetworkManagement.mode = mode, - .uCommandParams.NetworkManagement.pHandle = (ZW_Void_Callback_t)pCallBack - }; + SZwaveCommandPackage pCmdPackage; + pCmdPackage.eCommandType = EZWAVECOMMANDTYPE_REMOVE_NODE_FROM_NETWORK; + pCmdPackage.uCommandParams.NetworkManagement.mode = mode; + pCmdPackage.uCommandParams.NetworkManagement.pHandle = (ZW_Void_Callback_t)pCallBack; + if (0 != node_id) { - pCmdPackage.uCommandParams.NetworkManagement.mode = EZWAVECOMMANDTYPE_REMOVE_NODEID_FROM_NETWORK; + pCmdPackage.eCommandType = EZWAVECOMMANDTYPE_REMOVE_NODEID_FROM_NETWORK; pCmdPackage.uCommandParams.NetworkManagement.nodeID = node_id; } // Put the package on queue (and dont wait for it) @@ -1493,22 +1488,17 @@ static void /*RET Nothing */ ZCB_ComplHandler_ZW_SetLearnMode( uint32_t bStatus) /*IN ZW_SetLearnMode status */ { - uint8_t offset = 0; - BYTE_IN_AR(compl_workbuf, 0) = funcID_ComplHandler_ZW_SetLearnMode; - BYTE_IN_AR(compl_workbuf, 1) = (uint8_t)bStatus; + uint8_t i = 0; + BYTE_IN_AR(compl_workbuf, i++) = funcID_ComplHandler_ZW_SetLearnMode; + BYTE_IN_AR(compl_workbuf, i++) = (uint8_t)bStatus; if (SERIAL_API_SETUP_NODEID_BASE_TYPE_16_BIT == nodeIdBaseType) { - BYTE_IN_AR(compl_workbuf, 2) = (uint8_t)(g_pAppHandles->pNetworkInfo->NodeId >> 8); // MSB - BYTE_IN_AR(compl_workbuf, 3) = (uint8_t)(g_pAppHandles->pNetworkInfo->NodeId & 0xFF); // LSB - offset++; // 16 bit nodeID means the command fields that follow are offset by one byte - } - else - { - BYTE_IN_AR(compl_workbuf, 2) = (uint8_t)(g_pAppHandles->pNetworkInfo->NodeId & 0xFF); // Legacy 8 bit nodeID + BYTE_IN_AR(compl_workbuf, i++) = (uint8_t)(g_pAppHandles->pNetworkInfo->NodeId >> 8); // MSB 16bit node Id } + BYTE_IN_AR(compl_workbuf, i++) = (uint8_t)(g_pAppHandles->pNetworkInfo->NodeId & 0xFF); // LSB(16bit)/Legacy 8 bit node Id /* For safty we transmit len = 0, to indicate that no data follows */ - BYTE_IN_AR(compl_workbuf, offset + 3) = 0; - Request(FUNC_ID_ZW_SET_LEARN_MODE, compl_workbuf, offset + 4); + BYTE_IN_AR(compl_workbuf, i++) = 0; + Request(FUNC_ID_ZW_SET_LEARN_MODE, compl_workbuf, i); } #endif /* ZW_SLAVE */ @@ -1908,6 +1898,7 @@ static uint8_t AssignSucReturnRoute(uint16_t srcNodeID, uint8_t sucNode, ZW_TX_C pAssignReturnRoute->RouteDestinationNodeId = sucNode; memset(pAssignReturnRoute->aPriorityRouteRepeaters, 0, sizeof(pAssignReturnRoute->aPriorityRouteRepeaters)); pAssignReturnRoute->PriorityRouteSpeed = 0; + pAssignReturnRoute->isSucRoute = true; pAssignReturnRoute->Handle = (ZW_Void_Callback_t)pCallBack; FramePackage.eTransmitType = EZWAVETRANSMITTYPE_ASSIGNRETURNROUTE; @@ -1946,6 +1937,7 @@ static uint8_t AssignPrioritySucReturnRoute(uint16_t srcNode, uint8_t sucNode, pAssignReturnRoute->RouteDestinationNodeId = sucNode; memcpy(pAssignReturnRoute->aPriorityRouteRepeaters, pRoute, 4); pAssignReturnRoute->PriorityRouteSpeed = routeSpeed; + pAssignReturnRoute->isSucRoute = true; pAssignReturnRoute->Handle = (ZW_Void_Callback_t)pCallBack; FramePackage.eTransmitType = EZWAVETRANSMITTYPE_ASSIGNRETURNROUTE; diff --git a/protocol/z-wave/Apps/SerialAPI/cmds_management.c b/protocol/z-wave/Apps/SerialAPI/cmds_management.c index ac0640ee46..1c35dd6339 100644 --- a/protocol/z-wave/Apps/SerialAPI/cmds_management.c +++ b/protocol/z-wave/Apps/SerialAPI/cmds_management.c @@ -13,6 +13,7 @@ #include #include #include +#include "zw_config_rf.h" //#define DEBUGPRINT #include @@ -34,6 +35,17 @@ /** Add the SERIAL_API_SETUP command to the bitmask array */ #define BITMASK_ADD_CMD(bitmask, cmd) (bitmask[BYTE_INDEX(cmd)] |= BYTE_OFFSET(cmd)) +#ifndef MAX +/** Return the larger of two values. + * + * \param x An integer-valued expression without side effects. + * \param y An integer-valued expression without side effects. + * + * \return The larger of \p x and \p y. + */ +#define MAX( x, y ) ( ( x ) > ( y ) ? ( x ) : ( y ) ) +#endif // MAX + void func_id_serial_api_get_init_data(uint8_t inputLength, const uint8_t *pInputBuffer, uint8_t *pOutputBuffer, @@ -126,7 +138,7 @@ void func_id_serial_api_setup(uint8_t inputLength, uint8_t i=0; uint8_t cmdRes; zpal_radio_region_t rfRegion; - int8_t iPowerLevel, iPower0dbmMeasured; + zpal_tx_power_t iPowerLevel, iPower0dbmMeasured; /* We assume operation is nonesuccessful */ cmdRes = false; @@ -163,17 +175,20 @@ void func_id_serial_api_setup(uint8_t inputLength, memset(supportedBitmask, 0, sizeof(supportedBitmask)); /* For each command in eSerialAPISetupCmd, find a byte number in supportedBitmask where it should be, * and position (offset) in it and then add it to the array. */ - BITMASK_ADD_CMD(supportedBitmask, SERIAL_API_SETUP_CMD_SUPPORTED); - BITMASK_ADD_CMD(supportedBitmask, SERIAL_API_SETUP_CMD_TX_STATUS_REPORT); - BITMASK_ADD_CMD(supportedBitmask, SERIAL_API_SETUP_CMD_TX_POWERLEVEL_SET); - BITMASK_ADD_CMD(supportedBitmask, SERIAL_API_SETUP_CMD_TX_POWERLEVEL_GET); - BITMASK_ADD_CMD(supportedBitmask, SERIAL_API_SETUP_CMD_TX_GET_MAX_PAYLOAD_SIZE); - BITMASK_ADD_CMD(supportedBitmask, SERIAL_API_SETUP_CMD_TX_GET_MAX_LR_PAYLOAD_SIZE); - BITMASK_ADD_CMD(supportedBitmask, SERIAL_API_SETUP_CMD_RF_REGION_GET); - BITMASK_ADD_CMD(supportedBitmask, SERIAL_API_SETUP_CMD_RF_REGION_SET); - BITMASK_ADD_CMD(supportedBitmask, SERIAL_API_SETUP_CMD_NODEID_BASETYPE_SET); - BITMASK_ADD_CMD(supportedBitmask, SERIAL_API_SETUP_CMD_MAX_LR_TX_PWR_SET); - BITMASK_ADD_CMD(supportedBitmask, SERIAL_API_SETUP_CMD_MAX_LR_TX_PWR_GET); + BITMASK_ADD_CMD(supportedBitmask, SERIAL_API_SETUP_CMD_SUPPORTED); // (1) + BITMASK_ADD_CMD(supportedBitmask, SERIAL_API_SETUP_CMD_TX_STATUS_REPORT); // (2) + BITMASK_ADD_CMD(supportedBitmask, SERIAL_API_SETUP_CMD_TX_POWERLEVEL_SET); // (4) + BITMASK_ADD_CMD(supportedBitmask, SERIAL_API_SETUP_CMD_TX_POWERLEVEL_GET); // (8) + BITMASK_ADD_CMD(supportedBitmask, SERIAL_API_SETUP_CMD_TX_GET_MAX_PAYLOAD_SIZE); // (16) + BITMASK_ADD_CMD(supportedBitmask, SERIAL_API_SETUP_CMD_RF_REGION_GET); // (32) + BITMASK_ADD_CMD(supportedBitmask, SERIAL_API_SETUP_CMD_RF_REGION_SET); // (64) + BITMASK_ADD_CMD(supportedBitmask, SERIAL_API_SETUP_CMD_NODEID_BASETYPE_SET); // (128) + + BITMASK_ADD_CMD(supportedBitmask, SERIAL_API_SETUP_CMD_MAX_LR_TX_PWR_SET); // (3) + BITMASK_ADD_CMD(supportedBitmask, SERIAL_API_SETUP_CMD_MAX_LR_TX_PWR_GET); // (5) + BITMASK_ADD_CMD(supportedBitmask, SERIAL_API_SETUP_CMD_TX_GET_MAX_LR_PAYLOAD_SIZE); // (17) + BITMASK_ADD_CMD(supportedBitmask, SERIAL_API_SETUP_CMD_TX_POWERLEVEL_SET_16_BIT); // (18) + BITMASK_ADD_CMD(supportedBitmask, SERIAL_API_SETUP_CMD_TX_POWERLEVEL_GET_16_BIT); // (19) /* Currently supported command with the highest value is SERIAL_API_SETUP_CMD_NODEID_BASETYPE_SET. No commands after it. */ @@ -227,22 +242,25 @@ void func_id_serial_api_setup(uint8_t inputLength, case SERIAL_API_SETUP_CMD_TX_POWERLEVEL_SET: { - int8_t iTxPower, iAdjust; + zpal_tx_power_t iTxPower, iAdjust; /** * HOST->ZW: SERIAL_API_SETUP_CMD_TX_POWER_SET | NormalTxPowerLevel | Measured0dBmPower - * ZW->HOST: SERIAL_API_SETUP_CMD_TX_POWER_SET | retVal + * ZW->HOST: SERIAL_API_SETUP_CMD_TX_POWER_SET | cmdRes */ if (SERIAL_API_SETUP_CMD_TX_POWERLEVEL_SET_CMD_LENGTH_MIN <= inputLength) { iTxPower = (int8_t)pInputBuffer[1]; - iAdjust = (int8_t)pInputBuffer[2]; - /* Only allow power level between -10dBm and 10dBm (API is in deci dBm) */ - if ((iTxPower > -100 ) && (iTxPower < 100 ) && (iAdjust > -100 ) && (iAdjust < 100 )) - { - cmdRes = SaveApplicationTxPowerlevel(iTxPower, iAdjust); - } + iAdjust = (int8_t)pInputBuffer[2]; + /** + * The min and max boundaries of int8_t are valid boundaries of the parameters that are being stored. + * However, this command does not support a higher value than 127 deci dBm or lower than -127 deci dBm + * for the parameters as a limitation of this SerialAPI command. + * + * Please use SERIAL_API_SETUP_CMD_TX_POWERLEVEL_SET_16_BIT which support our entire tx power range. + */ + cmdRes = SaveApplicationTxPowerlevel(iTxPower, iAdjust); } - BYTE_IN_AR(pOutputBuffer, i++) = cmdRes; + BYTE_IN_AR(pOutputBuffer, i++) = cmdRes; // true if success break; } @@ -252,10 +270,68 @@ void func_id_serial_api_setup(uint8_t inputLength, * ZW->HOST: SERIAL_API_SETUP_CMD_TX_POWER_GET | NormalTxPowerLevel | Measured0dBmPower */ ReadApplicationTxPowerlevel(&iPowerLevel, &iPower0dbmMeasured); + + /** + * This SerialAPI command has the following limitation that it cannot retrieve stored tx power values that are + * larger than 127 deci dBm or lower than -127 deci dBm. + */ + + // Clamp values to fit into the return parameter type of int8_t. + if (iPowerLevel > INT8_MAX) { + iPowerLevel = INT8_MAX; + } else if (iPowerLevel < INT8_MIN) { + iPowerLevel = INT8_MIN; + } + + if (iPower0dbmMeasured > INT8_MAX) { + iPower0dbmMeasured = INT8_MAX; + } else if (iPower0dbmMeasured < INT8_MIN) { + iPower0dbmMeasured = INT8_MIN; + } + BYTE_IN_AR(pOutputBuffer, i++) = (uint8_t)iPowerLevel; BYTE_IN_AR(pOutputBuffer, i++) = (uint8_t)iPower0dbmMeasured; break; + case SERIAL_API_SETUP_CMD_TX_POWERLEVEL_SET_16_BIT: + { + zpal_tx_power_t iTxPower, iAdjust; + /** + * HOST->ZW: SERIAL_API_SETUP_CMD_TX_POWER_SET | NormalTxPowerLevel (MSB) |NormalTxPowerLevel (LSB) | Measured0dBmPower (MSB)| Measured0dBmPower (LSB) + * ZW->HOST: SERIAL_API_SETUP_CMD_TX_POWER_SET | cmdRes + */ + if (SERIAL_API_SETUP_CMD_TX_POWERLEVEL_SET_CMD_LENGTH_MIN <= inputLength) + { + iTxPower = (zpal_tx_power_t)GET_16BIT_VALUE(&pInputBuffer[1]); + iAdjust = (zpal_tx_power_t)GET_16BIT_VALUE(&pInputBuffer[3]); + + /* Only allow power level between -10dBm and 10dBm (API is in deci dBm) */ + if (( iTxPower >= (zpal_radio_get_minimum_lr_tx_power() * 10) ) + && (iTxPower <= MAX(APP_MAX_TX_POWER, zpal_radio_get_maximum_lr_tx_power()) ) + && (iAdjust >= -ZW_TX_POWER_20DBM) + && (iAdjust <= ZW_TX_POWER_20DBM ) /* We might not need these checks as these are made for calibration and + * we can't tell in advance how large or small the value needs to be. */ + ) + { + cmdRes = SaveApplicationTxPowerlevel(iTxPower, iAdjust); + } + } + BYTE_IN_AR(pOutputBuffer, i++) = cmdRes; // true if success + break; + } + + case SERIAL_API_SETUP_CMD_TX_POWERLEVEL_GET_16_BIT: + /** + * HOST->ZW: SERIAL_API_SETUP_CMD_TX_POWER_GET_2 + * ZW->HOST: SERIAL_API_SETUP_CMD_TX_POWER_GET_2 | NormalTxPowerLevel (16bit) | Measured0dBmPower (16bit) + */ + ReadApplicationTxPowerlevel(&iPowerLevel, &iPower0dbmMeasured); + BYTE_IN_AR(pOutputBuffer, i++) = (uint8_t)((iPowerLevel >> 8) & 0xFF); // Big-endian + BYTE_IN_AR(pOutputBuffer, i++) = (uint8_t)(iPowerLevel & 0xFF); + BYTE_IN_AR(pOutputBuffer, i++) = (uint8_t)((iPower0dbmMeasured >> 8) & 0xFF); + BYTE_IN_AR(pOutputBuffer, i++) = (uint8_t)(iPower0dbmMeasured & 0xFF); + break; + case SERIAL_API_SETUP_CMD_TX_GET_MAX_PAYLOAD_SIZE: BYTE_IN_AR(pOutputBuffer, i++) = (uint8_t)ZAF_getAppHandle()->pNetworkInfo->MaxPayloadSize; break; @@ -282,12 +358,12 @@ void func_id_serial_api_setup(uint8_t inputLength, case SERIAL_API_SETUP_CMD_MAX_LR_TX_PWR_SET: /** * HOST->ZW: SERIAL_API_SETUP_CMD_MAX_LR_TX_PWR_SET | maxtxpower (16-bit) - * ZW->HOST: SERIAL_API_SETUP_CMD_MAX_LR_TX_PWR_SET | retVal + * ZW->HOST: SERIAL_API_SETUP_CMD_MAX_LR_TX_PWR_SET | cmdRes */ if (SERIAL_API_SETUP_CMD_MAX_LR_TX_PWR_SET_CMD_LENGTH_MIN <= inputLength) { - uint16_t val = (uint16_t)(((uint16_t)pInputBuffer[1] << 8) | (uint16_t)pInputBuffer[2]); - cmdRes = SaveApplicationMaxLRTxPwr((int16_t)val); + zpal_tx_power_t val = (zpal_tx_power_t)GET_16BIT_VALUE(&pInputBuffer[1]); + cmdRes = SaveApplicationMaxLRTxPwr(val); } BYTE_IN_AR(pOutputBuffer, i++) = cmdRes; break; diff --git a/protocol/z-wave/Apps/SerialAPI/cmds_management.h b/protocol/z-wave/Apps/SerialAPI/cmds_management.h index 694051eb0d..2596eebf3e 100644 --- a/protocol/z-wave/Apps/SerialAPI/cmds_management.h +++ b/protocol/z-wave/Apps/SerialAPI/cmds_management.h @@ -11,18 +11,32 @@ /* FUNC_ID_SERIAL_API_SETUP command definitions */ typedef enum { + /** + * The first 8 commands are given as bit-flags, and when all bits were consumed, a byte-array was created to give + * more room. + * The first 8 flags are the only ones that shall be used to fill the first byte when generating the response in + * pOutputBuffer for the command, SERIAL_API_SETUP_CMD_SUPPORTED. + * This is kept for backwards compatibility. + */ SERIAL_API_SETUP_CMD_UNSUPPORTED, SERIAL_API_SETUP_CMD_SUPPORTED = 1, //1<<0 SERIAL_API_SETUP_CMD_TX_STATUS_REPORT = 2, //1<<1 - SERIAL_API_SETUP_CMD_MAX_LR_TX_PWR_SET = 3, - SERIAL_API_SETUP_CMD_MAX_LR_TX_PWR_GET = 5, - SERIAL_API_SETUP_CMD_TX_POWERLEVEL_SET = 4, //1<<2 - SERIAL_API_SETUP_CMD_TX_POWERLEVEL_GET = 8, //1<<3 + SERIAL_API_SETUP_CMD_TX_POWERLEVEL_SET = 4, //1<<2 @Deprecated + SERIAL_API_SETUP_CMD_TX_POWERLEVEL_GET = 8, //1<<3 @Deprecated SERIAL_API_SETUP_CMD_TX_GET_MAX_PAYLOAD_SIZE = 16, //1<<4 - SERIAL_API_SETUP_CMD_TX_GET_MAX_LR_PAYLOAD_SIZE = 17, //(1<<4) + 1 SERIAL_API_SETUP_CMD_RF_REGION_GET = 32, //1<<5 SERIAL_API_SETUP_CMD_RF_REGION_SET = 64, //1<<6 - SERIAL_API_SETUP_CMD_NODEID_BASETYPE_SET = 128 //1<<7 + SERIAL_API_SETUP_CMD_NODEID_BASETYPE_SET = 128, //1<<7 + /** + * The below values are not flags and shall only be used with BITMASK_ADD_CMD() when generating + * the response for the command, SERIAL_API_SETUP_CMD_SUPPORTED. + */ + SERIAL_API_SETUP_CMD_MAX_LR_TX_PWR_SET = 3, + SERIAL_API_SETUP_CMD_MAX_LR_TX_PWR_GET = 5, + // The values 6 and 7 are unused, but not reserved. + SERIAL_API_SETUP_CMD_TX_GET_MAX_LR_PAYLOAD_SIZE = 17, + SERIAL_API_SETUP_CMD_TX_POWERLEVEL_SET_16_BIT = 18, + SERIAL_API_SETUP_CMD_TX_POWERLEVEL_GET_16_BIT = 19, } eSerialAPISetupCmd; /* SERIAL_API_SETUP_CMD_NODEID_BASETYPE_SET definitions */ @@ -50,6 +64,9 @@ extern eSerialAPISetupNodeIdBaseType nodeIdBaseType; } \ } while (0) +#define GET_16BIT_VALUE(pData) \ + ( ( (uint16_t)((uint8_t*)pData)[0] << 8) | (uint16_t)((uint8_t*)pData)[1] ) /* 16 bit, MSB | LSB */ + /* Commands minimum length (bytes) */ #define SERIAL_API_SETUP_CMD_TX_STATUS_REPORT_CMD_LENGTH_MIN 2 #define SERIAL_API_SETUP_CMD_RF_REGION_SET_CMD_LENGTH_MIN 2 diff --git a/protocol/z-wave/Apps/SerialAPI/comm_interface.c b/protocol/z-wave/Apps/SerialAPI/comm_interface.c index 3c480d6aec..15b9fc8e06 100644 --- a/protocol/z-wave/Apps/SerialAPI/comm_interface.c +++ b/protocol/z-wave/Apps/SerialAPI/comm_interface.c @@ -11,7 +11,7 @@ #include #include "AppTimer.h" #include "Assert.h" - +#include "serial_api_config.h" #define BUFFER_CHECK_TIME_MS 250 #define DEFAULT_ACK_TIMEOUT_MS 1500 @@ -207,6 +207,24 @@ void comm_interface_init(void) { const zpal_uart_config_t uart_config = { +#if defined(SERIAL_API_TX_PIN) + .tx_pin = SERIAL_API_TX_PIN, +#endif /* defined(SERIAL_API_TX_PIN) */ +#if defined(SERIAL_API_TX_PORT) + .tx_port = SERIAL_API_TX_PORT, +#endif /* defined(SERIAL_API_TX_PORT) */ +#if defined(SERIAL_API_TX_LOC) + .tx_loc = SERIAL_API_TX_LOC, +#endif /* defined(SERIAL_API_TX_LOC) */ +#if defined(SERIAL_API_RX_PIN) + .rx_pin = SERIAL_API_RX_PIN, +#endif /* defined(SERIAL_API_RX_PIN) */ +#if defined(SERIAL_API_RX_PORT) + .rx_port = SERIAL_API_RX_PORT, +#endif /* defined(SERIAL_API_RX_PORT) */ +#if defined(SERIAL_API_RX_LOC) + .rx_loc = SERIAL_API_RX_LOC, +#endif /* defined(SERIAL_API_RX_LOC) */ .tx_buffer = tx_data, .tx_buffer_len = COMM_INT_TX_BUFFER_SIZE, .rx_buffer = rx_data, diff --git a/protocol/z-wave/Apps/SerialAPI/controller_supported_func.h b/protocol/z-wave/Apps/SerialAPI/controller_supported_func.h index 1493a9b2e7..c09926f2c7 100644 --- a/protocol/z-wave/Apps/SerialAPI/controller_supported_func.h +++ b/protocol/z-wave/Apps/SerialAPI/controller_supported_func.h @@ -20,14 +20,7 @@ #define SUPPORT_NVM_EXT_READ_LONG_BYTE 1 /* NVM_ext_read_long_byte */ #define SUPPORT_NVM_EXT_WRITE_LONG_BYTE 0 /* NVM_ext_write_long_byte */ #define SUPPORT_NVM_EXT_WRITE_LONG_BUFFER 0 /* NVM_ext_write_long_buffer*/ - -//Safety precaution due to PLATFORM_MTL-6522 -#ifdef ZWAVE_SERIES_800 -#define SUPPORT_NVM_BACKUP_RESTORE 0 /* MemoryGetBuffer */ -#else -#define SUPPORT_NVM_BACKUP_RESTORE 1 /* MemoryGetBuffer */ -#endif - +#define SUPPORT_NVM_BACKUP_RESTORE 1 /* NVM_backup_restore */ #define SUPPORT_PWR_CLK_PD 0 /* PWR_Clk_PD */ #define SUPPORT_PWR_CLK_PUP 0 /* PWR_Clk_PUp */ #define SUPPORT_PWR_SELECT_CLK 0 /* PWR_Select_Clk */ diff --git a/protocol/z-wave/Apps/SerialAPI/serialapi_file.c b/protocol/z-wave/Apps/SerialAPI/serialapi_file.c index f7eb82c401..36df455676 100644 --- a/protocol/z-wave/Apps/SerialAPI/serialapi_file.c +++ b/protocol/z-wave/Apps/SerialAPI/serialapi_file.c @@ -37,7 +37,9 @@ #define APPL_DATA_FILE_SIZE 512 -#define APP_VERSION_NO_20DBM_SUPPORT 0x00070F02 +#define APP_VERSION_7_15_3 0x00070F03 // 7.15.3 (NO_20DBM_SUPPORT) +#define APP_VERSION_7_18_1 0x00071201 /* 7.18.1 - The changes include the capability to set tx power to + * 20+ dBm over the serial link. */ // Used by the application data file. typedef struct SApplicationData @@ -63,13 +65,22 @@ typedef struct SApplicationCmdClassInfo } SApplicationCmdClassInfo; -typedef struct SApplicationConfiguration +typedef struct SApplicationConfiguration_v7_15_3 // Cannot pack this (change size) as it is already in the field. { zpal_radio_region_t rfRegion; - int8_t iTxPower; - int8_t ipower0dbmMeasured; + int8_t iTxPower; // changed to zpal_tx_power_t { aka int16_t } in APP_VERSION_7_18_1 + int8_t ipower0dbmMeasured; // changed to zpal_tx_power_t { aka int16_t } in APP_VERSION_7_18_1 uint8_t radio_debug_enable; - int16_t maxTxPower; + int16_t maxTxPower; // changed to zpal_tx_power_t { aka int16_t } in APP_VERSION_7_18_1 +} SApplicationConfiguration_v7_15_3; + +typedef struct __attribute__((packed)) SApplicationConfiguration // Must be packet as it is saved on NVM. +{ + zpal_radio_region_t rfRegion; + zpal_tx_power_t iTxPower; + zpal_tx_power_t ipower0dbmMeasured; + uint8_t radio_debug_enable; + zpal_tx_power_t maxTxPower; // For LR only } SApplicationConfiguration; #define FILE_SIZE_APPLICATIONDATA (sizeof(SApplicationData)) @@ -82,6 +93,127 @@ static void WriteDefault(void); // Application file system static zpal_nvm_handle_t pFileSystemApplication; + +static void WriteDefaultApplicationConfiguration(void); +static bool ObjectExist(zpal_nvm_object_key_t key); + +bool SerialAPI_GetZWVersion(uint32_t * appVersion) +{ + if( ZPAL_STATUS_OK == zpal_nvm_read(pFileSystemApplication, ZAF_FILE_ID_APP_VERSION, appVersion, ZAF_FILE_SIZE_APP_VERSION) ) + { + return true; + } + return false; +} + +bool SerialAPI_SetZWVersion(const uint32_t * appVersion) +{ + if( ZPAL_STATUS_OK == zpal_nvm_write(pFileSystemApplication, ZAF_FILE_ID_APP_VERSION, appVersion, ZAF_FILE_SIZE_APP_VERSION) ) + { + return true; + } + return false; +} + +static void +SerialAPI_FileSystemMigrationManagement() +{ + //Read present file system version file + uint32_t presentFilesysVersion; + uint32_t expectedFilesysVersion; // This will hold the file system version that current SW will support. + + SerialAPI_GetZWVersion(&presentFilesysVersion); + + expectedFilesysVersion = zpal_get_app_version(); + + if(expectedFilesysVersion < presentFilesysVersion) + { + //System downgrade. Should not be allowed. + ASSERT(false); + } + else if(expectedFilesysVersion > presentFilesysVersion) // File system upgrade needed. Initiating file system migration... + { + /** + * Continuous migration until all needed migrations are performed, + * to lift from any version to the latest file system version. + */ + + // If current version is 7.15.2 or older then update the FILE_ID_APPLICATIONCONFIGURATION file to the current format + if ( presentFilesysVersion < APP_VERSION_7_15_3 ) + { + // Add code for migration of file system to version APP_VERSION_7_15_3 (7.15.3). + + //Get length of legacy file + size_t dataLen; + zpal_nvm_get_object_size(pFileSystemApplication, FILE_ID_APPLICATIONCONFIGURATION, &dataLen); + + //Read legacy file to first members of tApplicationConfiguration + SApplicationConfiguration_v7_15_3 tApplicationConfiguration; + // Initialize, since zpal_nvm_read() might fail. + memset(&tApplicationConfiguration, 0, sizeof(tApplicationConfiguration)); + zpal_nvm_read(pFileSystemApplication, FILE_ID_APPLICATIONCONFIGURATION, &tApplicationConfiguration, dataLen); + + //Write default values to new members of tApplicationConfiguration and update the file. + tApplicationConfiguration.radio_debug_enable = 0; + tApplicationConfiguration.maxTxPower = 140; + zpal_status_t status = zpal_nvm_write(pFileSystemApplication, FILE_ID_APPLICATIONCONFIGURATION, &tApplicationConfiguration, + sizeof(tApplicationConfiguration)); + if (ZPAL_STATUS_OK == status) + { + presentFilesysVersion = APP_VERSION_7_15_3; + } + } + + // Migrate files from file system version APP_VERSION_7_15_3 to APP_VERSION_7_18_1. + if ( presentFilesysVersion < APP_VERSION_7_18_1 ) + { + SApplicationConfiguration_v7_15_3 tApplicationConfiguration_v7_15_3; + SApplicationConfiguration tApplicationConfiguration; + zpal_status_t status; + + status = zpal_nvm_read(pFileSystemApplication, FILE_ID_APPLICATIONCONFIGURATION, &tApplicationConfiguration_v7_15_3, + sizeof(tApplicationConfiguration_v7_15_3)); + if (ZPAL_STATUS_OK != status) + { + WriteDefaultApplicationConfiguration(); + } + else + { + tApplicationConfiguration.rfRegion = tApplicationConfiguration_v7_15_3.rfRegion; + tApplicationConfiguration.iTxPower = tApplicationConfiguration_v7_15_3.iTxPower; + tApplicationConfiguration.ipower0dbmMeasured = tApplicationConfiguration_v7_15_3.ipower0dbmMeasured; + tApplicationConfiguration.radio_debug_enable = tApplicationConfiguration_v7_15_3.radio_debug_enable; + tApplicationConfiguration.maxTxPower = tApplicationConfiguration_v7_15_3.maxTxPower; + + status = zpal_nvm_write(pFileSystemApplication, FILE_ID_APPLICATIONCONFIGURATION, &tApplicationConfiguration, + sizeof(tApplicationConfiguration)); /* Do not use FILE_SIZE_APPLICATIONCONFIGURATION in + * migration functions, instead hard-code the size as + * sizes do change with FW upgrades. */ + if (ZPAL_STATUS_OK == status) + { + presentFilesysVersion = APP_VERSION_7_18_1; + } + } + + // Lifted to version APP_VERSION_7_18_1 + } + + /* + * If this fails, some of the migrations were not performed due to earlier migrations that have failed. + */ + ASSERT(APP_VERSION_7_18_1 <= presentFilesysVersion); + + /** + * @attention This implementation assumes that the build is going to update the ZAF_FILE_ID_APP_VERSION to the current! + */ + + /** + * Write the new file system version number to NMV. + */ + SerialAPI_SetZWVersion(&expectedFilesysVersion); + } +} + uint8_t SerialApiFileInit(void) { // Init application filesystem @@ -93,39 +225,25 @@ uint8_t SerialApiFileInit(void) } uint32_t appVersion; - const zpal_status_t status = zpal_nvm_read(pFileSystemApplication, ZAF_FILE_ID_APP_VERSION, &appVersion, ZAF_FILE_SIZE_APP_VERSION); + bool status = SerialAPI_GetZWVersion(&appVersion); - if (ZPAL_STATUS_OK == status) + if (status) { if (zpal_get_app_version() != appVersion) { - // Add code for migration of file system to higher version here. - - - // If current version is 7.15.2 or older then update the FILE_ID_APPLICATIONCONFIGURATION file to the current format - if (APP_VERSION_NO_20DBM_SUPPORT >= appVersion) { - //Get length of legacy file - size_t dataLen; - zpal_nvm_get_object_size(pFileSystemApplication, FILE_ID_APPLICATIONCONFIGURATION, &dataLen); - - //Read legacy file to first members of tApplicationConfiguration - SApplicationConfiguration tApplicationConfiguration; - zpal_nvm_read(pFileSystemApplication, FILE_ID_APPLICATIONCONFIGURATION, &tApplicationConfiguration, dataLen); - - //Write default values to new members of tApplicationConfiguration and update the file. - tApplicationConfiguration.radio_debug_enable = 0; - tApplicationConfiguration.maxTxPower = 140; - zpal_nvm_write(pFileSystemApplication, FILE_ID_APPLICATIONCONFIGURATION, &tApplicationConfiguration, FILE_SIZE_APPLICATIONCONFIGURATION); - } - appVersion = zpal_get_app_version(); - zpal_nvm_write(pFileSystemApplication, ZAF_FILE_ID_APP_VERSION, &appVersion, ZAF_FILE_SIZE_APP_VERSION); + /** + * In case the file-system is older than supported by this version of the FW, then upgrade. + */ + SerialAPI_FileSystemMigrationManagement(); } } else { + //There are no files on first boot up. Write default files. WriteDefault(); return false; } + return true; } @@ -402,7 +520,7 @@ ReadApplicationRfRegion(zpal_radio_region_t* rfRegion) } uint8_t -SaveApplicationTxPowerlevel(int8_t ipower, int8_t power0dbmMeasured) +SaveApplicationTxPowerlevel(zpal_tx_power_t ipower, zpal_tx_power_t power0dbmMeasured) { SApplicationConfiguration tApplicationConfiguration; uint8_t dataIsWritten = false; @@ -424,7 +542,7 @@ SaveApplicationTxPowerlevel(int8_t ipower, int8_t power0dbmMeasured) uint8_t -ReadApplicationTxPowerlevel(int8_t *ipower, int8_t *power0dbmMeasured) +ReadApplicationTxPowerlevel(zpal_tx_power_t *ipower, zpal_tx_power_t *power0dbmMeasured) { SApplicationConfiguration tApplicationConfiguration; uint8_t dataIsRead = false; @@ -445,7 +563,7 @@ ReadApplicationTxPowerlevel(int8_t *ipower, int8_t *power0dbmMeasured) uint8_t -SaveApplicationMaxLRTxPwr(int16_t maxTxPwr) +SaveApplicationMaxLRTxPwr(zpal_tx_power_t maxTxPwr) { SApplicationConfiguration tApplicationConfiguration; uint8_t dataIsWritten = false; @@ -466,7 +584,7 @@ SaveApplicationMaxLRTxPwr(int16_t maxTxPwr) uint8_t -ReadApplicationMaxLRTxPwr(int16_t *maxTxPwr) +ReadApplicationMaxLRTxPwr(zpal_tx_power_t *maxTxPwr) { SApplicationConfiguration tApplicationConfiguration; uint8_t dataIsRead = false; @@ -530,7 +648,7 @@ uint32_t ReadApplicationVersion(void) { uint32_t appVersion; - zpal_nvm_read(pFileSystemApplication, ZAF_FILE_ID_APP_VERSION, &appVersion, sizeof(appVersion)); + SerialAPI_GetZWVersion(&appVersion); return appVersion; } @@ -579,19 +697,16 @@ WriteDefaultApplicationConfiguration(void) //Write default Application Configuration file SApplicationConfiguration tApplicationConfiguration; memset(&tApplicationConfiguration, 0 , sizeof(SApplicationConfiguration)); - status = zpal_nvm_write(pFileSystemApplication, FILE_ID_APPLICATIONCONFIGURATION, &tApplicationConfiguration, sizeof(SApplicationConfiguration)); - ASSERT(ZPAL_STATUS_OK == status); //Assert has been kept for debugging only, can be removed from production code. This error can only be caused by some internal flash driver/Hw prroblem + status = zpal_nvm_write(pFileSystemApplication, FILE_ID_APPLICATIONCONFIGURATION, &tApplicationConfiguration, FILE_SIZE_APPLICATIONCONFIGURATION); + ASSERT(ZPAL_STATUS_OK == status); //Assert has been kept for debugging only, can be removed from production code. This error can only be caused by some internal flash driver/Hw problem } static void WriteDefaultApplicationFileSystemVersion(void) { - zpal_status_t status; - //Write Application filesystem version uint32_t appVersion = (APP_VERSION << 16) | (APP_REVISION << 8) | APP_PATCH; - status = zpal_nvm_write(pFileSystemApplication, ZAF_FILE_ID_APP_VERSION, &appVersion, sizeof(appVersion)); - ASSERT(ZPAL_STATUS_OK == status); //Assert has been kept for debugging only, can be removed from production code. This error can only be caused by some internal flash driver/Hw prroblem + SerialAPI_SetZWVersion(&appVersion); } static void diff --git a/protocol/z-wave/Apps/SerialAPI/serialapi_file.h b/protocol/z-wave/Apps/SerialAPI/serialapi_file.h index 93120caed8..b1d6684c2d 100644 --- a/protocol/z-wave/Apps/SerialAPI/serialapi_file.h +++ b/protocol/z-wave/Apps/SerialAPI/serialapi_file.h @@ -86,13 +86,13 @@ ReadApplicationRfRegion(zpal_radio_region_t* rfRegion); * @brief Writes the application Tx power configuration to file system */ uint8_t -SaveApplicationTxPowerlevel(int8_t ipower, int8_t power0dbmMeasured); +SaveApplicationTxPowerlevel(zpal_tx_power_t ipower, zpal_tx_power_t power0dbmMeasured); /** * @brief Reads the application Tx power configuration from file system */ uint8_t -ReadApplicationTxPowerlevel(int8_t *ipower, int8_t *power0dbmMeasured); +ReadApplicationTxPowerlevel(zpal_tx_power_t *ipower, zpal_tx_power_t *power0dbmMeasured); /** @@ -102,7 +102,7 @@ ReadApplicationTxPowerlevel(int8_t *ipower, int8_t *power0dbmMeasured); * @return value was saved correctly */ uint8_t -SaveApplicationMaxLRTxPwr(int16_t maxTxPwr); +SaveApplicationMaxLRTxPwr(zpal_tx_power_t maxTxPwr); /** * Reads the application Max LR tx power value configuration from file system @@ -111,7 +111,7 @@ SaveApplicationMaxLRTxPwr(int16_t maxTxPwr); * @return value was read correctly */ uint8_t -ReadApplicationMaxLRTxPwr(int16_t *maxTxPwr); +ReadApplicationMaxLRTxPwr(zpal_tx_power_t *maxTxPwr); /** * @brief Writes radio_debug_enable to file system diff --git a/protocol/z-wave/Apps/SerialAPI/serialappl.c b/protocol/z-wave/Apps/SerialAPI/serialappl.c index 499afb3cc4..fb9cadc091 100644 --- a/protocol/z-wave/Apps/SerialAPI/serialappl.c +++ b/protocol/z-wave/Apps/SerialAPI/serialappl.c @@ -1076,6 +1076,23 @@ ApplicationInit( DebugPrintConfig(m_aDebugPrintBuffer, sizeof(m_aDebugPrintBuffer), zpal_debug_output); #endif + DPRINT("\n\n--------------------------------\n"); + DPRINT("Z-Wave Sample App: Serial API "); +#if defined(ZW_SLAVE) + DPRINT("Slave\n"); +#else /* defined(ZW_SLAVE) */ + DPRINT("Controller\n"); +#endif /* defined(ZW_SLAVE) */ + DPRINTF("SDK: %d.%d.%d ZAF: %d.%d.%d.%d\n", + SDK_VERSION_MAJOR, + SDK_VERSION_MINOR, + SDK_VERSION_PATCH, + zpal_get_app_version_major(), + zpal_get_app_version_minor(), + zpal_get_app_version_patch(), + ZAF_BUILD_NO); + + DPRINTF("ApplicationInit eResetReason = %d\n", eResetReason); appFileSystemInit(); /************************************************************************************* diff --git a/protocol/z-wave/Apps/SwitchOnOff/SwitchOnOff.c b/protocol/z-wave/Apps/SwitchOnOff/SwitchOnOff.c index d0bd762dd8..09daf6a1da 100644 --- a/protocol/z-wave/Apps/SwitchOnOff/SwitchOnOff.c +++ b/protocol/z-wave/Apps/SwitchOnOff/SwitchOnOff.c @@ -13,6 +13,7 @@ #include #include "SizeOf.h" #include "Assert.h" +#include #include "DebugPrintConfig.h" //#define DEBUGPRINT #include "DebugPrint.h" @@ -59,6 +60,7 @@ #include "events.h" #include #include +#include #include #include #include @@ -167,7 +169,7 @@ static const SAppNodeInfo_t AppNodeInfo = .CommandClasses.SecureIncludedSecureCC.pCommandClasses = cmdClassListSecure }; -static const SRadioConfig_t RadioConfig = +static SRadioConfig_t RadioConfig = { .iListenBeforeTalkThreshold = ELISTENBEFORETALKTRESHOLD_DEFAULT, .iTxPowerLevelMax = APP_MAX_TX_POWER, @@ -562,13 +564,23 @@ ApplicationInit(EResetReason_t eResetReason) zpal_get_app_version_patch(), ZAF_BUILD_NO); - DPRINTF("ApplicationInit eResetReason = %d\n", eResetReason); CC_Indicator_Init(indicator_set_handler); // Init file system ApplicationFileSystemInit(&pFileSystemApplication); + // Read Rf region from MFG_ZWAVE_COUNTRY_FREQ + zpal_radio_region_t regionMfg; + ZW_GetMfgTokenDataCountryFreq((void*) ®ionMfg); + if (isRfRegionValid(regionMfg)) { + RadioConfig.eRegion = regionMfg; + } else { + ZW_SetMfgTokenDataCountryRegion((void*) &RadioConfig.eRegion); + } + DPRINTF("Rf region: %d\n", RadioConfig.eRegion); + DPRINTF("ApplicationInit eResetReason = %d\n", eResetReason); + /************************************************************************************* * CREATE USER TASKS - ZW_ApplicationRegisterTask() and ZW_UserTask_CreateTask() ************************************************************************************* diff --git a/protocol/z-wave/Apps/WallController/WallController.c b/protocol/z-wave/Apps/WallController/WallController.c index c58432c6e2..ab159f8ad2 100644 --- a/protocol/z-wave/Apps/WallController/WallController.c +++ b/protocol/z-wave/Apps/WallController/WallController.c @@ -16,6 +16,7 @@ #include #include "SizeOf.h" #include "Assert.h" +#include #include "DebugPrintConfig.h" //#define DEBUGPRINT #include "DebugPrint.h" @@ -188,7 +189,7 @@ static const SAppNodeInfo_t AppNodeInfo = .CommandClasses.SecureIncludedSecureCC.pCommandClasses = cmdClassListSecure }; -static const SRadioConfig_t RadioConfig = +static SRadioConfig_t RadioConfig = { .iListenBeforeTalkThreshold = ELISTENBEFORETALKTRESHOLD_DEFAULT, .iTxPowerLevelMax = APP_MAX_TX_POWER, @@ -614,6 +615,15 @@ ApplicationInit(EResetReason_t eResetReason) // Init file system ApplicationFileSystemInit(&pFileSystemApplication); + // Read Rf region from MFG_ZWAVE_COUNTRY_FREQ + zpal_radio_region_t regionMfg; + ZW_GetMfgTokenDataCountryFreq((void*) ®ionMfg); + if (isRfRegionValid(regionMfg)) { + RadioConfig.eRegion = regionMfg; + } else { + ZW_SetMfgTokenDataCountryRegion((void*) &RadioConfig.eRegion); + } + /************************************************************************************* * CREATE USER TASKS - ZW_ApplicationRegisterTask() and ZW_UserTask_CreateTask() ************************************************************************************* diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2603A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2603A_REGION_EU_size.txt index 7b7e82defe..24ff04147c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2603A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2603A_REGION_EU_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x32150 0x8006000 -_cmd_handlers 0x2d8 0x8038150 -_zw_protocol_cmd_handlers 0xe8 0x8038428 -_zw_protocol_cmd_handlers_lr 0x48 0x8038510 -.ARM.exidx 0x8 0x8038558 -.copy.table 0xc 0x8038560 -.zero.table 0x0 0x803856c +.text 0x32668 0x8006000 +_cmd_handlers 0x2e0 0x8038668 +_zw_protocol_cmd_handlers 0xe8 0x8038948 +_zw_protocol_cmd_handlers_lr 0x48 0x8038a30 +.ARM.exidx 0x8 0x8038a78 +.copy.table 0xc 0x8038a80 +.zero.table 0x0 0x8038a8c .stack 0x600 0x20000000 -.data 0x4cc 0x20000600 -.bss 0xa9f4 0x20000acc -.heap 0x4b40 0x2000b4c0 -.zwave_nvm 0x6000 0x803856c -.nvm 0xa000 0x803e56c +.data 0x4d0 0x20000600 +.bss 0xaa20 0x20000ad0 +.heap 0x4b10 0x2000b4f0 +.zwave_nvm 0x6000 0x8038a8c +.nvm 0xa000 0x803ea8c .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x8280 0x0 -.debug_info 0xe1730 0x0 -.debug_abbrev 0xd78c 0x0 -.debug_loc 0x2f9da 0x0 -.debug_aranges 0x2b50 0x0 -.debug_ranges 0x53f8 0x0 -.debug_line 0x2c3a3 0x0 -.debug_str 0x751ea 0x0 -Total 0x2225d6 +.debug_frame 0x82fc 0x0 +.debug_info 0xe3602 0x0 +.debug_abbrev 0xda61 0x0 +.debug_loc 0x2fcb0 0x0 +.debug_aranges 0x2b88 0x0 +.debug_ranges 0x5448 0x0 +.debug_line 0x2c9fa 0x0 +.debug_str 0x75662 0x0 +Total 0x225b46 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 207416 + 208732 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 65536 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48320 + 48368 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2603A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2603A_REGION_US_LR_size.txt index 7b7e82defe..24ff04147c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2603A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2603A_REGION_US_LR_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x32150 0x8006000 -_cmd_handlers 0x2d8 0x8038150 -_zw_protocol_cmd_handlers 0xe8 0x8038428 -_zw_protocol_cmd_handlers_lr 0x48 0x8038510 -.ARM.exidx 0x8 0x8038558 -.copy.table 0xc 0x8038560 -.zero.table 0x0 0x803856c +.text 0x32668 0x8006000 +_cmd_handlers 0x2e0 0x8038668 +_zw_protocol_cmd_handlers 0xe8 0x8038948 +_zw_protocol_cmd_handlers_lr 0x48 0x8038a30 +.ARM.exidx 0x8 0x8038a78 +.copy.table 0xc 0x8038a80 +.zero.table 0x0 0x8038a8c .stack 0x600 0x20000000 -.data 0x4cc 0x20000600 -.bss 0xa9f4 0x20000acc -.heap 0x4b40 0x2000b4c0 -.zwave_nvm 0x6000 0x803856c -.nvm 0xa000 0x803e56c +.data 0x4d0 0x20000600 +.bss 0xaa20 0x20000ad0 +.heap 0x4b10 0x2000b4f0 +.zwave_nvm 0x6000 0x8038a8c +.nvm 0xa000 0x803ea8c .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x8280 0x0 -.debug_info 0xe1730 0x0 -.debug_abbrev 0xd78c 0x0 -.debug_loc 0x2f9da 0x0 -.debug_aranges 0x2b50 0x0 -.debug_ranges 0x53f8 0x0 -.debug_line 0x2c3a3 0x0 -.debug_str 0x751ea 0x0 -Total 0x2225d6 +.debug_frame 0x82fc 0x0 +.debug_info 0xe3602 0x0 +.debug_abbrev 0xda61 0x0 +.debug_loc 0x2fcb0 0x0 +.debug_aranges 0x2b88 0x0 +.debug_ranges 0x5448 0x0 +.debug_line 0x2c9fa 0x0 +.debug_str 0x75662 0x0 +Total 0x225b46 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 207416 + 208732 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 65536 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48320 + 48368 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2603A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2603A_REGION_US_size.txt index 7b7e82defe..24ff04147c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2603A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD2603A_REGION_US_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x32150 0x8006000 -_cmd_handlers 0x2d8 0x8038150 -_zw_protocol_cmd_handlers 0xe8 0x8038428 -_zw_protocol_cmd_handlers_lr 0x48 0x8038510 -.ARM.exidx 0x8 0x8038558 -.copy.table 0xc 0x8038560 -.zero.table 0x0 0x803856c +.text 0x32668 0x8006000 +_cmd_handlers 0x2e0 0x8038668 +_zw_protocol_cmd_handlers 0xe8 0x8038948 +_zw_protocol_cmd_handlers_lr 0x48 0x8038a30 +.ARM.exidx 0x8 0x8038a78 +.copy.table 0xc 0x8038a80 +.zero.table 0x0 0x8038a8c .stack 0x600 0x20000000 -.data 0x4cc 0x20000600 -.bss 0xa9f4 0x20000acc -.heap 0x4b40 0x2000b4c0 -.zwave_nvm 0x6000 0x803856c -.nvm 0xa000 0x803e56c +.data 0x4d0 0x20000600 +.bss 0xaa20 0x20000ad0 +.heap 0x4b10 0x2000b4f0 +.zwave_nvm 0x6000 0x8038a8c +.nvm 0xa000 0x803ea8c .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x8280 0x0 -.debug_info 0xe1730 0x0 -.debug_abbrev 0xd78c 0x0 -.debug_loc 0x2f9da 0x0 -.debug_aranges 0x2b50 0x0 -.debug_ranges 0x53f8 0x0 -.debug_line 0x2c3a3 0x0 -.debug_str 0x751ea 0x0 -Total 0x2225d6 +.debug_frame 0x82fc 0x0 +.debug_info 0xe3602 0x0 +.debug_abbrev 0xda61 0x0 +.debug_loc 0x2fcb0 0x0 +.debug_aranges 0x2b88 0x0 +.debug_ranges 0x5448 0x0 +.debug_line 0x2c9fa 0x0 +.debug_str 0x75662 0x0 +Total 0x225b46 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 207416 + 208732 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 65536 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48320 + 48368 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4201A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4201A_REGION_EU_size.txt index f31a704479..69ddee9b8b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4201A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4201A_REGION_EU_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x2d154 0x0 -_cmd_handlers 0x2e0 0x2d154 -_zw_protocol_cmd_handlers 0xe8 0x2d434 -_zw_protocol_cmd_handlers_lr 0x48 0x2d51c -.ARM.exidx 0x8 0x2d564 -.copy.table 0xc 0x2d56c -.zero.table 0x0 0x2d578 +.text 0x2d4dc 0x0 +_cmd_handlers 0x2e0 0x2d4dc +_zw_protocol_cmd_handlers 0xe8 0x2d7bc +_zw_protocol_cmd_handlers_lr 0x48 0x2d8a4 +.ARM.exidx 0x8 0x2d8ec +.copy.table 0xc 0x2d8f4 +.zero.table 0x0 0x2d900 .stack 0x600 0x20000000 -.data 0x35c 0x20000600 -.bss 0x74bc 0x2000095c -.heap 0x1e8 0x20007e18 -.zwave_nvm 0x3000 0x2d578 -.nvm 0x9000 0x30578 +.data 0x360 0x20000600 +.bss 0x74e0 0x20000960 +.heap 0x1c0 0x20007e40 +.zwave_nvm 0x3000 0x2d900 +.nvm 0x9000 0x30900 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x5e08 0x0 -.debug_info 0xa9991 0x0 -.debug_abbrev 0xae13 0x0 -.debug_loc 0x1e364 0x0 -.debug_aranges 0x20c0 0x0 -.debug_ranges 0x3df0 0x0 -.debug_line 0x21856 0x0 -.debug_str 0x69b64 0x0 -Total 0x1ab169 +.debug_frame 0x5e40 0x0 +.debug_info 0xaa080 0x0 +.debug_abbrev 0xae57 0x0 +.debug_loc 0x1e532 0x0 +.debug_aranges 0x20d8 0x0 +.debug_ranges 0x3e90 0x0 +.debug_line 0x21ac2 0x0 +.debug_str 0x69dec 0x0 +Total 0x1ac3d6 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 186580 + 187488 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 34328 + 34368 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4201A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4201A_REGION_US_LR_size.txt index f31a704479..69ddee9b8b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4201A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4201A_REGION_US_LR_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x2d154 0x0 -_cmd_handlers 0x2e0 0x2d154 -_zw_protocol_cmd_handlers 0xe8 0x2d434 -_zw_protocol_cmd_handlers_lr 0x48 0x2d51c -.ARM.exidx 0x8 0x2d564 -.copy.table 0xc 0x2d56c -.zero.table 0x0 0x2d578 +.text 0x2d4dc 0x0 +_cmd_handlers 0x2e0 0x2d4dc +_zw_protocol_cmd_handlers 0xe8 0x2d7bc +_zw_protocol_cmd_handlers_lr 0x48 0x2d8a4 +.ARM.exidx 0x8 0x2d8ec +.copy.table 0xc 0x2d8f4 +.zero.table 0x0 0x2d900 .stack 0x600 0x20000000 -.data 0x35c 0x20000600 -.bss 0x74bc 0x2000095c -.heap 0x1e8 0x20007e18 -.zwave_nvm 0x3000 0x2d578 -.nvm 0x9000 0x30578 +.data 0x360 0x20000600 +.bss 0x74e0 0x20000960 +.heap 0x1c0 0x20007e40 +.zwave_nvm 0x3000 0x2d900 +.nvm 0x9000 0x30900 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x5e08 0x0 -.debug_info 0xa9991 0x0 -.debug_abbrev 0xae13 0x0 -.debug_loc 0x1e364 0x0 -.debug_aranges 0x20c0 0x0 -.debug_ranges 0x3df0 0x0 -.debug_line 0x21856 0x0 -.debug_str 0x69b64 0x0 -Total 0x1ab169 +.debug_frame 0x5e40 0x0 +.debug_info 0xaa080 0x0 +.debug_abbrev 0xae57 0x0 +.debug_loc 0x1e532 0x0 +.debug_aranges 0x20d8 0x0 +.debug_ranges 0x3e90 0x0 +.debug_line 0x21ac2 0x0 +.debug_str 0x69dec 0x0 +Total 0x1ac3d6 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 186580 + 187488 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 34328 + 34368 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4201A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4201A_REGION_US_size.txt index ba3fe808da..b67e3d006a 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4201A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4201A_REGION_US_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x2d164 0x0 -_cmd_handlers 0x2e0 0x2d164 -_zw_protocol_cmd_handlers 0xe8 0x2d444 -_zw_protocol_cmd_handlers_lr 0x48 0x2d52c -.ARM.exidx 0x8 0x2d574 -.copy.table 0xc 0x2d57c -.zero.table 0x0 0x2d588 +.text 0x2d4ec 0x0 +_cmd_handlers 0x2e0 0x2d4ec +_zw_protocol_cmd_handlers 0xe8 0x2d7cc +_zw_protocol_cmd_handlers_lr 0x48 0x2d8b4 +.ARM.exidx 0x8 0x2d8fc +.copy.table 0xc 0x2d904 +.zero.table 0x0 0x2d910 .stack 0x600 0x20000000 -.data 0x35c 0x20000600 -.bss 0x74bc 0x2000095c -.heap 0x1e8 0x20007e18 -.zwave_nvm 0x3000 0x2d588 -.nvm 0x9000 0x30588 +.data 0x360 0x20000600 +.bss 0x74e0 0x20000960 +.heap 0x1c0 0x20007e40 +.zwave_nvm 0x3000 0x2d910 +.nvm 0x9000 0x30910 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x5e08 0x0 -.debug_info 0xa9992 0x0 -.debug_abbrev 0xae13 0x0 -.debug_loc 0x1e364 0x0 -.debug_aranges 0x20c0 0x0 -.debug_ranges 0x3df0 0x0 -.debug_line 0x21856 0x0 -.debug_str 0x69b64 0x0 -Total 0x1ab17a +.debug_frame 0x5e40 0x0 +.debug_info 0xaa081 0x0 +.debug_abbrev 0xae57 0x0 +.debug_loc 0x1e532 0x0 +.debug_aranges 0x20d8 0x0 +.debug_ranges 0x3e90 0x0 +.debug_line 0x21ac2 0x0 +.debug_str 0x69dec 0x0 +Total 0x1ac3e7 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 186596 + 187504 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 34328 + 34368 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4202A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4202A_REGION_EU_size.txt index 854072630f..f9e3ad37b5 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4202A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4202A_REGION_EU_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x2d8fc 0x0 -_cmd_handlers 0x2e0 0x2d8fc -_zw_protocol_cmd_handlers 0xe8 0x2dbdc -_zw_protocol_cmd_handlers_lr 0x48 0x2dcc4 -.ARM.exidx 0x8 0x2dd0c -.copy.table 0xc 0x2dd14 -.zero.table 0x0 0x2dd20 +.text 0x2dcb4 0x0 +_cmd_handlers 0x2e0 0x2dcb4 +_zw_protocol_cmd_handlers 0xe8 0x2df94 +_zw_protocol_cmd_handlers_lr 0x48 0x2e07c +.ARM.exidx 0x8 0x2e0c4 +.copy.table 0xc 0x2e0cc +.zero.table 0x0 0x2e0d8 .stack 0x600 0x20000000 -.data 0x360 0x20000600 -.bss 0x7a58 0x20000960 -.heap 0x7c48 0x200083b8 -.zwave_nvm 0x3000 0x2dd20 -.nvm 0x9000 0x30d20 +.data 0x364 0x20000600 +.bss 0x7a8c 0x20000964 +.heap 0x7c10 0x200083f0 +.zwave_nvm 0x3000 0x2e0d8 +.nvm 0x9000 0x310d8 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x5e24 0x0 -.debug_info 0xab038 0x0 -.debug_abbrev 0xade4 0x0 -.debug_loc 0x1e84c 0x0 -.debug_aranges 0x20f0 0x0 -.debug_ranges 0x3e90 0x0 -.debug_line 0x21a3a 0x0 -.debug_str 0x6a109 0x0 -Total 0x1b5ce6 +.debug_frame 0x5e5c 0x0 +.debug_info 0xab726 0x0 +.debug_abbrev 0xae3b 0x0 +.debug_loc 0x1ea1a 0x0 +.debug_aranges 0x2108 0x0 +.debug_ranges 0x3f30 0x0 +.debug_line 0x21ca6 0x0 +.debug_str 0x6a390 0x0 +Total 0x1b6f94 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 188544 + 189500 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 35768 + 35824 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4202A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4202A_REGION_US_LR_size.txt index 854072630f..f9e3ad37b5 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4202A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4202A_REGION_US_LR_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x2d8fc 0x0 -_cmd_handlers 0x2e0 0x2d8fc -_zw_protocol_cmd_handlers 0xe8 0x2dbdc -_zw_protocol_cmd_handlers_lr 0x48 0x2dcc4 -.ARM.exidx 0x8 0x2dd0c -.copy.table 0xc 0x2dd14 -.zero.table 0x0 0x2dd20 +.text 0x2dcb4 0x0 +_cmd_handlers 0x2e0 0x2dcb4 +_zw_protocol_cmd_handlers 0xe8 0x2df94 +_zw_protocol_cmd_handlers_lr 0x48 0x2e07c +.ARM.exidx 0x8 0x2e0c4 +.copy.table 0xc 0x2e0cc +.zero.table 0x0 0x2e0d8 .stack 0x600 0x20000000 -.data 0x360 0x20000600 -.bss 0x7a58 0x20000960 -.heap 0x7c48 0x200083b8 -.zwave_nvm 0x3000 0x2dd20 -.nvm 0x9000 0x30d20 +.data 0x364 0x20000600 +.bss 0x7a8c 0x20000964 +.heap 0x7c10 0x200083f0 +.zwave_nvm 0x3000 0x2e0d8 +.nvm 0x9000 0x310d8 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x5e24 0x0 -.debug_info 0xab038 0x0 -.debug_abbrev 0xade4 0x0 -.debug_loc 0x1e84c 0x0 -.debug_aranges 0x20f0 0x0 -.debug_ranges 0x3e90 0x0 -.debug_line 0x21a3a 0x0 -.debug_str 0x6a109 0x0 -Total 0x1b5ce6 +.debug_frame 0x5e5c 0x0 +.debug_info 0xab726 0x0 +.debug_abbrev 0xae3b 0x0 +.debug_loc 0x1ea1a 0x0 +.debug_aranges 0x2108 0x0 +.debug_ranges 0x3f30 0x0 +.debug_line 0x21ca6 0x0 +.debug_str 0x6a390 0x0 +Total 0x1b6f94 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 188544 + 189500 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 35768 + 35824 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4202A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4202A_REGION_US_size.txt index b5170c5b4d..130a33f9b8 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4202A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4202A_REGION_US_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x2d8fc 0x0 -_cmd_handlers 0x2e0 0x2d8fc -_zw_protocol_cmd_handlers 0xe8 0x2dbdc -_zw_protocol_cmd_handlers_lr 0x48 0x2dcc4 -.ARM.exidx 0x8 0x2dd0c -.copy.table 0xc 0x2dd14 -.zero.table 0x0 0x2dd20 +.text 0x2dcb4 0x0 +_cmd_handlers 0x2e0 0x2dcb4 +_zw_protocol_cmd_handlers 0xe8 0x2df94 +_zw_protocol_cmd_handlers_lr 0x48 0x2e07c +.ARM.exidx 0x8 0x2e0c4 +.copy.table 0xc 0x2e0cc +.zero.table 0x0 0x2e0d8 .stack 0x600 0x20000000 -.data 0x360 0x20000600 -.bss 0x7a58 0x20000960 -.heap 0x7c48 0x200083b8 -.zwave_nvm 0x3000 0x2dd20 -.nvm 0x9000 0x30d20 +.data 0x364 0x20000600 +.bss 0x7a8c 0x20000964 +.heap 0x7c10 0x200083f0 +.zwave_nvm 0x3000 0x2e0d8 +.nvm 0x9000 0x310d8 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x5e24 0x0 -.debug_info 0xab039 0x0 -.debug_abbrev 0xade4 0x0 -.debug_loc 0x1e84c 0x0 -.debug_aranges 0x20f0 0x0 -.debug_ranges 0x3e90 0x0 -.debug_line 0x21a3a 0x0 -.debug_str 0x6a109 0x0 -Total 0x1b5ce7 +.debug_frame 0x5e5c 0x0 +.debug_info 0xab727 0x0 +.debug_abbrev 0xae3b 0x0 +.debug_loc 0x1ea1a 0x0 +.debug_aranges 0x2108 0x0 +.debug_ranges 0x3f30 0x0 +.debug_line 0x21ca6 0x0 +.debug_str 0x6a390 0x0 +Total 0x1b6f95 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 188544 + 189500 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 35768 + 35824 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204C_REGION_EU_size.txt index 8b9bcc73ee..7f58f08710 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204C_REGION_EU_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x31c24 0x8006000 -_cmd_handlers 0x2d8 0x8037c24 -_zw_protocol_cmd_handlers 0xe8 0x8037efc -_zw_protocol_cmd_handlers_lr 0x48 0x8037fe4 -.ARM.exidx 0x8 0x803802c -.copy.table 0xc 0x8038034 -.zero.table 0x0 0x8038040 +.text 0x32144 0x8006000 +_cmd_handlers 0x2e0 0x8038144 +_zw_protocol_cmd_handlers 0xe8 0x8038424 +_zw_protocol_cmd_handlers_lr 0x48 0x803850c +.ARM.exidx 0x8 0x8038554 +.copy.table 0xc 0x803855c +.zero.table 0x0 0x8038568 .stack 0x600 0x20000000 -.data 0x4c8 0x20000600 -.bss 0xa9d0 0x20000ac8 -.heap 0x4b68 0x2000b498 -.zwave_nvm 0x6000 0x8038040 -.nvm 0xa000 0x803e040 +.data 0x4cc 0x20000600 +.bss 0xaa04 0x20000acc +.heap 0x4b30 0x2000b4d0 +.zwave_nvm 0x6000 0x8038568 +.nvm 0xa000 0x803e568 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x8384 0x0 -.debug_info 0xe3272 0x0 -.debug_abbrev 0xda1d 0x0 -.debug_loc 0x2fdbb 0x0 -.debug_aranges 0x2b98 0x0 -.debug_ranges 0x5490 0x0 -.debug_line 0x2cb50 0x0 -.debug_str 0x74bde 0x0 -Total 0x2245e3 +.debug_frame 0x8400 0x0 +.debug_info 0xe5152 0x0 +.debug_abbrev 0xdce4 0x0 +.debug_loc 0x30091 0x0 +.debug_aranges 0x2bd0 0x0 +.debug_ranges 0x54e0 0x0 +.debug_line 0x2d1a7 0x0 +.debug_str 0x75057 0x0 +Total 0x227b5c The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 206088 + 207412 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 65536 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48280 + 48336 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204C_REGION_US_LR_size.txt index 8b9bcc73ee..7f58f08710 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204C_REGION_US_LR_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x31c24 0x8006000 -_cmd_handlers 0x2d8 0x8037c24 -_zw_protocol_cmd_handlers 0xe8 0x8037efc -_zw_protocol_cmd_handlers_lr 0x48 0x8037fe4 -.ARM.exidx 0x8 0x803802c -.copy.table 0xc 0x8038034 -.zero.table 0x0 0x8038040 +.text 0x32144 0x8006000 +_cmd_handlers 0x2e0 0x8038144 +_zw_protocol_cmd_handlers 0xe8 0x8038424 +_zw_protocol_cmd_handlers_lr 0x48 0x803850c +.ARM.exidx 0x8 0x8038554 +.copy.table 0xc 0x803855c +.zero.table 0x0 0x8038568 .stack 0x600 0x20000000 -.data 0x4c8 0x20000600 -.bss 0xa9d0 0x20000ac8 -.heap 0x4b68 0x2000b498 -.zwave_nvm 0x6000 0x8038040 -.nvm 0xa000 0x803e040 +.data 0x4cc 0x20000600 +.bss 0xaa04 0x20000acc +.heap 0x4b30 0x2000b4d0 +.zwave_nvm 0x6000 0x8038568 +.nvm 0xa000 0x803e568 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x8384 0x0 -.debug_info 0xe3272 0x0 -.debug_abbrev 0xda1d 0x0 -.debug_loc 0x2fdbb 0x0 -.debug_aranges 0x2b98 0x0 -.debug_ranges 0x5490 0x0 -.debug_line 0x2cb50 0x0 -.debug_str 0x74bde 0x0 -Total 0x2245e3 +.debug_frame 0x8400 0x0 +.debug_info 0xe5152 0x0 +.debug_abbrev 0xdce4 0x0 +.debug_loc 0x30091 0x0 +.debug_aranges 0x2bd0 0x0 +.debug_ranges 0x54e0 0x0 +.debug_line 0x2d1a7 0x0 +.debug_str 0x75057 0x0 +Total 0x227b5c The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 206088 + 207412 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 65536 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48280 + 48336 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204C_REGION_US_size.txt index 8b9bcc73ee..7f58f08710 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204C_REGION_US_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x31c24 0x8006000 -_cmd_handlers 0x2d8 0x8037c24 -_zw_protocol_cmd_handlers 0xe8 0x8037efc -_zw_protocol_cmd_handlers_lr 0x48 0x8037fe4 -.ARM.exidx 0x8 0x803802c -.copy.table 0xc 0x8038034 -.zero.table 0x0 0x8038040 +.text 0x32144 0x8006000 +_cmd_handlers 0x2e0 0x8038144 +_zw_protocol_cmd_handlers 0xe8 0x8038424 +_zw_protocol_cmd_handlers_lr 0x48 0x803850c +.ARM.exidx 0x8 0x8038554 +.copy.table 0xc 0x803855c +.zero.table 0x0 0x8038568 .stack 0x600 0x20000000 -.data 0x4c8 0x20000600 -.bss 0xa9d0 0x20000ac8 -.heap 0x4b68 0x2000b498 -.zwave_nvm 0x6000 0x8038040 -.nvm 0xa000 0x803e040 +.data 0x4cc 0x20000600 +.bss 0xaa04 0x20000acc +.heap 0x4b30 0x2000b4d0 +.zwave_nvm 0x6000 0x8038568 +.nvm 0xa000 0x803e568 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x8384 0x0 -.debug_info 0xe3272 0x0 -.debug_abbrev 0xda1d 0x0 -.debug_loc 0x2fdbb 0x0 -.debug_aranges 0x2b98 0x0 -.debug_ranges 0x5490 0x0 -.debug_line 0x2cb50 0x0 -.debug_str 0x74bde 0x0 -Total 0x2245e3 +.debug_frame 0x8400 0x0 +.debug_info 0xe5152 0x0 +.debug_abbrev 0xdce4 0x0 +.debug_loc 0x30091 0x0 +.debug_aranges 0x2bd0 0x0 +.debug_ranges 0x54e0 0x0 +.debug_line 0x2d1a7 0x0 +.debug_str 0x75057 0x0 +Total 0x227b5c The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 206088 + 207412 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 65536 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48280 + 48336 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204D_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204D_REGION_EU_size.txt index 9d80a209ab..dcf23e1732 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204D_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204D_REGION_EU_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x31cf8 0x8006000 -_cmd_handlers 0x2d8 0x8037cf8 -_zw_protocol_cmd_handlers 0xe8 0x8037fd0 -_zw_protocol_cmd_handlers_lr 0x48 0x80380b8 -.ARM.exidx 0x8 0x8038100 -.copy.table 0xc 0x8038108 -.zero.table 0x0 0x8038114 +.text 0x32220 0x8006000 +_cmd_handlers 0x2e0 0x8038220 +_zw_protocol_cmd_handlers 0xe8 0x8038500 +_zw_protocol_cmd_handlers_lr 0x48 0x80385e8 +.ARM.exidx 0x8 0x8038630 +.copy.table 0xc 0x8038638 +.zero.table 0x0 0x8038644 .stack 0x600 0x20000000 -.data 0x4cc 0x20000600 -.bss 0xa9d4 0x20000acc -.heap 0x4b60 0x2000b4a0 -.zwave_nvm 0x6000 0x8038114 -.nvm 0xa000 0x803e114 +.data 0x4d0 0x20000600 +.bss 0xaa00 0x20000ad0 +.heap 0x4b30 0x2000b4d0 +.zwave_nvm 0x6000 0x8038644 +.nvm 0xa000 0x803e644 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x83b4 0x0 -.debug_info 0xe34d5 0x0 -.debug_abbrev 0xdb09 0x0 -.debug_loc 0x2fdbb 0x0 -.debug_aranges 0x2bb8 0x0 -.debug_ranges 0x54a0 0x0 -.debug_line 0x2cd36 0x0 -.debug_str 0x74db1 0x0 -Total 0x224e1f +.debug_frame 0x8430 0x0 +.debug_info 0xe53b5 0x0 +.debug_abbrev 0xddd0 0x0 +.debug_loc 0x30091 0x0 +.debug_aranges 0x2bf0 0x0 +.debug_ranges 0x54f0 0x0 +.debug_line 0x2d38d 0x0 +.debug_str 0x7522a 0x0 +Total 0x2283a0 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 206304 + 207636 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 65536 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48288 + 48336 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204D_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204D_REGION_US_LR_size.txt index 9d80a209ab..dcf23e1732 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204D_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204D_REGION_US_LR_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x31cf8 0x8006000 -_cmd_handlers 0x2d8 0x8037cf8 -_zw_protocol_cmd_handlers 0xe8 0x8037fd0 -_zw_protocol_cmd_handlers_lr 0x48 0x80380b8 -.ARM.exidx 0x8 0x8038100 -.copy.table 0xc 0x8038108 -.zero.table 0x0 0x8038114 +.text 0x32220 0x8006000 +_cmd_handlers 0x2e0 0x8038220 +_zw_protocol_cmd_handlers 0xe8 0x8038500 +_zw_protocol_cmd_handlers_lr 0x48 0x80385e8 +.ARM.exidx 0x8 0x8038630 +.copy.table 0xc 0x8038638 +.zero.table 0x0 0x8038644 .stack 0x600 0x20000000 -.data 0x4cc 0x20000600 -.bss 0xa9d4 0x20000acc -.heap 0x4b60 0x2000b4a0 -.zwave_nvm 0x6000 0x8038114 -.nvm 0xa000 0x803e114 +.data 0x4d0 0x20000600 +.bss 0xaa00 0x20000ad0 +.heap 0x4b30 0x2000b4d0 +.zwave_nvm 0x6000 0x8038644 +.nvm 0xa000 0x803e644 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x83b4 0x0 -.debug_info 0xe34d5 0x0 -.debug_abbrev 0xdb09 0x0 -.debug_loc 0x2fdbb 0x0 -.debug_aranges 0x2bb8 0x0 -.debug_ranges 0x54a0 0x0 -.debug_line 0x2cd36 0x0 -.debug_str 0x74db1 0x0 -Total 0x224e1f +.debug_frame 0x8430 0x0 +.debug_info 0xe53b5 0x0 +.debug_abbrev 0xddd0 0x0 +.debug_loc 0x30091 0x0 +.debug_aranges 0x2bf0 0x0 +.debug_ranges 0x54f0 0x0 +.debug_line 0x2d38d 0x0 +.debug_str 0x7522a 0x0 +Total 0x2283a0 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 206304 + 207636 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 65536 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48288 + 48336 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204D_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204D_REGION_US_size.txt index 9d80a209ab..dcf23e1732 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204D_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4204D_REGION_US_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x31cf8 0x8006000 -_cmd_handlers 0x2d8 0x8037cf8 -_zw_protocol_cmd_handlers 0xe8 0x8037fd0 -_zw_protocol_cmd_handlers_lr 0x48 0x80380b8 -.ARM.exidx 0x8 0x8038100 -.copy.table 0xc 0x8038108 -.zero.table 0x0 0x8038114 +.text 0x32220 0x8006000 +_cmd_handlers 0x2e0 0x8038220 +_zw_protocol_cmd_handlers 0xe8 0x8038500 +_zw_protocol_cmd_handlers_lr 0x48 0x80385e8 +.ARM.exidx 0x8 0x8038630 +.copy.table 0xc 0x8038638 +.zero.table 0x0 0x8038644 .stack 0x600 0x20000000 -.data 0x4cc 0x20000600 -.bss 0xa9d4 0x20000acc -.heap 0x4b60 0x2000b4a0 -.zwave_nvm 0x6000 0x8038114 -.nvm 0xa000 0x803e114 +.data 0x4d0 0x20000600 +.bss 0xaa00 0x20000ad0 +.heap 0x4b30 0x2000b4d0 +.zwave_nvm 0x6000 0x8038644 +.nvm 0xa000 0x803e644 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x83b4 0x0 -.debug_info 0xe34d5 0x0 -.debug_abbrev 0xdb09 0x0 -.debug_loc 0x2fdbb 0x0 -.debug_aranges 0x2bb8 0x0 -.debug_ranges 0x54a0 0x0 -.debug_line 0x2cd36 0x0 -.debug_str 0x74db1 0x0 -Total 0x224e1f +.debug_frame 0x8430 0x0 +.debug_info 0xe53b5 0x0 +.debug_abbrev 0xddd0 0x0 +.debug_loc 0x30091 0x0 +.debug_aranges 0x2bf0 0x0 +.debug_ranges 0x54f0 0x0 +.debug_line 0x2d38d 0x0 +.debug_str 0x7522a 0x0 +Total 0x2283a0 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 206304 + 207636 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 65536 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48288 + 48336 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205A_REGION_EU_size.txt index 6a17c565c5..59f0caec3f 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205A_REGION_EU_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x32184 0x8006000 -_cmd_handlers 0x2d8 0x8038184 -_zw_protocol_cmd_handlers 0xe8 0x803845c -_zw_protocol_cmd_handlers_lr 0x48 0x8038544 -.ARM.exidx 0x8 0x803858c -.copy.table 0xc 0x8038594 -.zero.table 0x0 0x80385a0 +.text 0x32694 0x8006000 +_cmd_handlers 0x2e0 0x8038694 +_zw_protocol_cmd_handlers 0xe8 0x8038974 +_zw_protocol_cmd_handlers_lr 0x48 0x8038a5c +.ARM.exidx 0x8 0x8038aa4 +.copy.table 0xc 0x8038aac +.zero.table 0x0 0x8038ab8 .stack 0x600 0x20000000 -.data 0x4c8 0x20000600 -.bss 0xa8b0 0x20000ac8 -.heap 0x4c88 0x2000b378 -.zwave_nvm 0x6000 0x80385a0 -.nvm 0xa000 0x803e5a0 +.data 0x4cc 0x20000600 +.bss 0xa8e4 0x20000acc +.heap 0x4c50 0x2000b3b0 +.zwave_nvm 0x6000 0x8038ab8 +.nvm 0xa000 0x803eab8 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x8360 0x0 -.debug_info 0xe3aa3 0x0 -.debug_abbrev 0xdb53 0x0 -.debug_loc 0x2fb95 0x0 -.debug_aranges 0x2bc8 0x0 -.debug_ranges 0x5490 0x0 -.debug_line 0x2cb01 0x0 -.debug_str 0x7538d 0x0 -Total 0x2259f0 +.debug_frame 0x8268 0x0 +.debug_info 0xe54a1 0x0 +.debug_abbrev 0xde07 0x0 +.debug_loc 0x2eaa2 0x0 +.debug_aranges 0x2c00 0x0 +.debug_ranges 0x54e0 0x0 +.debug_line 0x2ccba 0x0 +.debug_str 0x753ca 0x0 +Total 0x226c4d The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 207464 + 208772 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 65536 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47992 + 48048 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205A_REGION_US_LR_size.txt index 6a17c565c5..59f0caec3f 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205A_REGION_US_LR_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x32184 0x8006000 -_cmd_handlers 0x2d8 0x8038184 -_zw_protocol_cmd_handlers 0xe8 0x803845c -_zw_protocol_cmd_handlers_lr 0x48 0x8038544 -.ARM.exidx 0x8 0x803858c -.copy.table 0xc 0x8038594 -.zero.table 0x0 0x80385a0 +.text 0x32694 0x8006000 +_cmd_handlers 0x2e0 0x8038694 +_zw_protocol_cmd_handlers 0xe8 0x8038974 +_zw_protocol_cmd_handlers_lr 0x48 0x8038a5c +.ARM.exidx 0x8 0x8038aa4 +.copy.table 0xc 0x8038aac +.zero.table 0x0 0x8038ab8 .stack 0x600 0x20000000 -.data 0x4c8 0x20000600 -.bss 0xa8b0 0x20000ac8 -.heap 0x4c88 0x2000b378 -.zwave_nvm 0x6000 0x80385a0 -.nvm 0xa000 0x803e5a0 +.data 0x4cc 0x20000600 +.bss 0xa8e4 0x20000acc +.heap 0x4c50 0x2000b3b0 +.zwave_nvm 0x6000 0x8038ab8 +.nvm 0xa000 0x803eab8 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x8360 0x0 -.debug_info 0xe3aa3 0x0 -.debug_abbrev 0xdb53 0x0 -.debug_loc 0x2fb95 0x0 -.debug_aranges 0x2bc8 0x0 -.debug_ranges 0x5490 0x0 -.debug_line 0x2cb01 0x0 -.debug_str 0x7538d 0x0 -Total 0x2259f0 +.debug_frame 0x8268 0x0 +.debug_info 0xe54a1 0x0 +.debug_abbrev 0xde07 0x0 +.debug_loc 0x2eaa2 0x0 +.debug_aranges 0x2c00 0x0 +.debug_ranges 0x54e0 0x0 +.debug_line 0x2ccba 0x0 +.debug_str 0x753ca 0x0 +Total 0x226c4d The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 207464 + 208772 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 65536 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47992 + 48048 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205A_REGION_US_size.txt index 6a17c565c5..59f0caec3f 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205A_REGION_US_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x32184 0x8006000 -_cmd_handlers 0x2d8 0x8038184 -_zw_protocol_cmd_handlers 0xe8 0x803845c -_zw_protocol_cmd_handlers_lr 0x48 0x8038544 -.ARM.exidx 0x8 0x803858c -.copy.table 0xc 0x8038594 -.zero.table 0x0 0x80385a0 +.text 0x32694 0x8006000 +_cmd_handlers 0x2e0 0x8038694 +_zw_protocol_cmd_handlers 0xe8 0x8038974 +_zw_protocol_cmd_handlers_lr 0x48 0x8038a5c +.ARM.exidx 0x8 0x8038aa4 +.copy.table 0xc 0x8038aac +.zero.table 0x0 0x8038ab8 .stack 0x600 0x20000000 -.data 0x4c8 0x20000600 -.bss 0xa8b0 0x20000ac8 -.heap 0x4c88 0x2000b378 -.zwave_nvm 0x6000 0x80385a0 -.nvm 0xa000 0x803e5a0 +.data 0x4cc 0x20000600 +.bss 0xa8e4 0x20000acc +.heap 0x4c50 0x2000b3b0 +.zwave_nvm 0x6000 0x8038ab8 +.nvm 0xa000 0x803eab8 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x8360 0x0 -.debug_info 0xe3aa3 0x0 -.debug_abbrev 0xdb53 0x0 -.debug_loc 0x2fb95 0x0 -.debug_aranges 0x2bc8 0x0 -.debug_ranges 0x5490 0x0 -.debug_line 0x2cb01 0x0 -.debug_str 0x7538d 0x0 -Total 0x2259f0 +.debug_frame 0x8268 0x0 +.debug_info 0xe54a1 0x0 +.debug_abbrev 0xde07 0x0 +.debug_loc 0x2eaa2 0x0 +.debug_aranges 0x2c00 0x0 +.debug_ranges 0x54e0 0x0 +.debug_line 0x2ccba 0x0 +.debug_str 0x753ca 0x0 +Total 0x226c4d The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 207464 + 208772 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 65536 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47992 + 48048 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205B_REGION_EU_size.txt index 31bbab8163..9b927a4688 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205B_REGION_EU_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x32184 0x8006000 -_cmd_handlers 0x2d8 0x8038184 -_zw_protocol_cmd_handlers 0xe8 0x803845c -_zw_protocol_cmd_handlers_lr 0x48 0x8038544 -.ARM.exidx 0x8 0x803858c -.copy.table 0xc 0x8038594 -.zero.table 0x0 0x80385a0 +.text 0x326a4 0x8006000 +_cmd_handlers 0x2e0 0x80386a4 +_zw_protocol_cmd_handlers 0xe8 0x8038984 +_zw_protocol_cmd_handlers_lr 0x48 0x8038a6c +.ARM.exidx 0x8 0x8038ab4 +.copy.table 0xc 0x8038abc +.zero.table 0x0 0x8038ac8 .stack 0x600 0x20000000 -.data 0x4c8 0x20000600 -.bss 0xa9f0 0x20000ac8 -.heap 0x4b48 0x2000b4b8 -.zwave_nvm 0x6000 0x80385a0 -.nvm 0xa000 0x803e5a0 +.data 0x4cc 0x20000600 +.bss 0xaa24 0x20000acc +.heap 0x4b10 0x2000b4f0 +.zwave_nvm 0x6000 0x8038ac8 +.nvm 0xa000 0x803eac8 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x8384 0x0 -.debug_info 0xe3ced 0x0 -.debug_abbrev 0xdb62 0x0 -.debug_loc 0x2fdaa 0x0 -.debug_aranges 0x2bc8 0x0 -.debug_ranges 0x5490 0x0 -.debug_line 0x2cb52 0x0 -.debug_str 0x7548b 0x0 -Total 0x225fd1 +.debug_frame 0x8400 0x0 +.debug_info 0xe5bcd 0x0 +.debug_abbrev 0xde29 0x0 +.debug_loc 0x30080 0x0 +.debug_aranges 0x2c00 0x0 +.debug_ranges 0x54e0 0x0 +.debug_line 0x2d1a9 0x0 +.debug_str 0x75903 0x0 +Total 0x229549 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 207464 + 208788 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 65536 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48312 + 48368 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205B_REGION_US_LR_size.txt index 31bbab8163..9b927a4688 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205B_REGION_US_LR_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x32184 0x8006000 -_cmd_handlers 0x2d8 0x8038184 -_zw_protocol_cmd_handlers 0xe8 0x803845c -_zw_protocol_cmd_handlers_lr 0x48 0x8038544 -.ARM.exidx 0x8 0x803858c -.copy.table 0xc 0x8038594 -.zero.table 0x0 0x80385a0 +.text 0x326a4 0x8006000 +_cmd_handlers 0x2e0 0x80386a4 +_zw_protocol_cmd_handlers 0xe8 0x8038984 +_zw_protocol_cmd_handlers_lr 0x48 0x8038a6c +.ARM.exidx 0x8 0x8038ab4 +.copy.table 0xc 0x8038abc +.zero.table 0x0 0x8038ac8 .stack 0x600 0x20000000 -.data 0x4c8 0x20000600 -.bss 0xa9f0 0x20000ac8 -.heap 0x4b48 0x2000b4b8 -.zwave_nvm 0x6000 0x80385a0 -.nvm 0xa000 0x803e5a0 +.data 0x4cc 0x20000600 +.bss 0xaa24 0x20000acc +.heap 0x4b10 0x2000b4f0 +.zwave_nvm 0x6000 0x8038ac8 +.nvm 0xa000 0x803eac8 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x8384 0x0 -.debug_info 0xe3ced 0x0 -.debug_abbrev 0xdb62 0x0 -.debug_loc 0x2fdaa 0x0 -.debug_aranges 0x2bc8 0x0 -.debug_ranges 0x5490 0x0 -.debug_line 0x2cb52 0x0 -.debug_str 0x7548b 0x0 -Total 0x225fd1 +.debug_frame 0x8400 0x0 +.debug_info 0xe5bcd 0x0 +.debug_abbrev 0xde29 0x0 +.debug_loc 0x30080 0x0 +.debug_aranges 0x2c00 0x0 +.debug_ranges 0x54e0 0x0 +.debug_line 0x2d1a9 0x0 +.debug_str 0x75903 0x0 +Total 0x229549 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 207464 + 208788 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 65536 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48312 + 48368 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205B_REGION_US_size.txt index 31bbab8163..9b927a4688 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4205B_REGION_US_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x32184 0x8006000 -_cmd_handlers 0x2d8 0x8038184 -_zw_protocol_cmd_handlers 0xe8 0x803845c -_zw_protocol_cmd_handlers_lr 0x48 0x8038544 -.ARM.exidx 0x8 0x803858c -.copy.table 0xc 0x8038594 -.zero.table 0x0 0x80385a0 +.text 0x326a4 0x8006000 +_cmd_handlers 0x2e0 0x80386a4 +_zw_protocol_cmd_handlers 0xe8 0x8038984 +_zw_protocol_cmd_handlers_lr 0x48 0x8038a6c +.ARM.exidx 0x8 0x8038ab4 +.copy.table 0xc 0x8038abc +.zero.table 0x0 0x8038ac8 .stack 0x600 0x20000000 -.data 0x4c8 0x20000600 -.bss 0xa9f0 0x20000ac8 -.heap 0x4b48 0x2000b4b8 -.zwave_nvm 0x6000 0x80385a0 -.nvm 0xa000 0x803e5a0 +.data 0x4cc 0x20000600 +.bss 0xaa24 0x20000acc +.heap 0x4b10 0x2000b4f0 +.zwave_nvm 0x6000 0x8038ac8 +.nvm 0xa000 0x803eac8 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x8384 0x0 -.debug_info 0xe3ced 0x0 -.debug_abbrev 0xdb62 0x0 -.debug_loc 0x2fdaa 0x0 -.debug_aranges 0x2bc8 0x0 -.debug_ranges 0x5490 0x0 -.debug_line 0x2cb52 0x0 -.debug_str 0x7548b 0x0 -Total 0x225fd1 +.debug_frame 0x8400 0x0 +.debug_info 0xe5bcd 0x0 +.debug_abbrev 0xde29 0x0 +.debug_loc 0x30080 0x0 +.debug_aranges 0x2c00 0x0 +.debug_ranges 0x54e0 0x0 +.debug_line 0x2d1a9 0x0 +.debug_str 0x75903 0x0 +Total 0x229549 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 207464 + 208788 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 65536 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48312 + 48368 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4206A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4206A_REGION_EU_size.txt index f31a704479..69ddee9b8b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4206A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4206A_REGION_EU_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x2d154 0x0 -_cmd_handlers 0x2e0 0x2d154 -_zw_protocol_cmd_handlers 0xe8 0x2d434 -_zw_protocol_cmd_handlers_lr 0x48 0x2d51c -.ARM.exidx 0x8 0x2d564 -.copy.table 0xc 0x2d56c -.zero.table 0x0 0x2d578 +.text 0x2d4dc 0x0 +_cmd_handlers 0x2e0 0x2d4dc +_zw_protocol_cmd_handlers 0xe8 0x2d7bc +_zw_protocol_cmd_handlers_lr 0x48 0x2d8a4 +.ARM.exidx 0x8 0x2d8ec +.copy.table 0xc 0x2d8f4 +.zero.table 0x0 0x2d900 .stack 0x600 0x20000000 -.data 0x35c 0x20000600 -.bss 0x74bc 0x2000095c -.heap 0x1e8 0x20007e18 -.zwave_nvm 0x3000 0x2d578 -.nvm 0x9000 0x30578 +.data 0x360 0x20000600 +.bss 0x74e0 0x20000960 +.heap 0x1c0 0x20007e40 +.zwave_nvm 0x3000 0x2d900 +.nvm 0x9000 0x30900 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x5e08 0x0 -.debug_info 0xa9991 0x0 -.debug_abbrev 0xae13 0x0 -.debug_loc 0x1e364 0x0 -.debug_aranges 0x20c0 0x0 -.debug_ranges 0x3df0 0x0 -.debug_line 0x21856 0x0 -.debug_str 0x69b64 0x0 -Total 0x1ab169 +.debug_frame 0x5e40 0x0 +.debug_info 0xaa080 0x0 +.debug_abbrev 0xae57 0x0 +.debug_loc 0x1e532 0x0 +.debug_aranges 0x20d8 0x0 +.debug_ranges 0x3e90 0x0 +.debug_line 0x21ac2 0x0 +.debug_str 0x69dec 0x0 +Total 0x1ac3d6 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 186580 + 187488 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 34328 + 34368 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4206A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4206A_REGION_US_LR_size.txt index f31a704479..69ddee9b8b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4206A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4206A_REGION_US_LR_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x2d154 0x0 -_cmd_handlers 0x2e0 0x2d154 -_zw_protocol_cmd_handlers 0xe8 0x2d434 -_zw_protocol_cmd_handlers_lr 0x48 0x2d51c -.ARM.exidx 0x8 0x2d564 -.copy.table 0xc 0x2d56c -.zero.table 0x0 0x2d578 +.text 0x2d4dc 0x0 +_cmd_handlers 0x2e0 0x2d4dc +_zw_protocol_cmd_handlers 0xe8 0x2d7bc +_zw_protocol_cmd_handlers_lr 0x48 0x2d8a4 +.ARM.exidx 0x8 0x2d8ec +.copy.table 0xc 0x2d8f4 +.zero.table 0x0 0x2d900 .stack 0x600 0x20000000 -.data 0x35c 0x20000600 -.bss 0x74bc 0x2000095c -.heap 0x1e8 0x20007e18 -.zwave_nvm 0x3000 0x2d578 -.nvm 0x9000 0x30578 +.data 0x360 0x20000600 +.bss 0x74e0 0x20000960 +.heap 0x1c0 0x20007e40 +.zwave_nvm 0x3000 0x2d900 +.nvm 0x9000 0x30900 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x5e08 0x0 -.debug_info 0xa9991 0x0 -.debug_abbrev 0xae13 0x0 -.debug_loc 0x1e364 0x0 -.debug_aranges 0x20c0 0x0 -.debug_ranges 0x3df0 0x0 -.debug_line 0x21856 0x0 -.debug_str 0x69b64 0x0 -Total 0x1ab169 +.debug_frame 0x5e40 0x0 +.debug_info 0xaa080 0x0 +.debug_abbrev 0xae57 0x0 +.debug_loc 0x1e532 0x0 +.debug_aranges 0x20d8 0x0 +.debug_ranges 0x3e90 0x0 +.debug_line 0x21ac2 0x0 +.debug_str 0x69dec 0x0 +Total 0x1ac3d6 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 186580 + 187488 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 34328 + 34368 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4206A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4206A_REGION_US_size.txt index ba3fe808da..b67e3d006a 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4206A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4206A_REGION_US_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x2d164 0x0 -_cmd_handlers 0x2e0 0x2d164 -_zw_protocol_cmd_handlers 0xe8 0x2d444 -_zw_protocol_cmd_handlers_lr 0x48 0x2d52c -.ARM.exidx 0x8 0x2d574 -.copy.table 0xc 0x2d57c -.zero.table 0x0 0x2d588 +.text 0x2d4ec 0x0 +_cmd_handlers 0x2e0 0x2d4ec +_zw_protocol_cmd_handlers 0xe8 0x2d7cc +_zw_protocol_cmd_handlers_lr 0x48 0x2d8b4 +.ARM.exidx 0x8 0x2d8fc +.copy.table 0xc 0x2d904 +.zero.table 0x0 0x2d910 .stack 0x600 0x20000000 -.data 0x35c 0x20000600 -.bss 0x74bc 0x2000095c -.heap 0x1e8 0x20007e18 -.zwave_nvm 0x3000 0x2d588 -.nvm 0x9000 0x30588 +.data 0x360 0x20000600 +.bss 0x74e0 0x20000960 +.heap 0x1c0 0x20007e40 +.zwave_nvm 0x3000 0x2d910 +.nvm 0x9000 0x30910 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x5e08 0x0 -.debug_info 0xa9992 0x0 -.debug_abbrev 0xae13 0x0 -.debug_loc 0x1e364 0x0 -.debug_aranges 0x20c0 0x0 -.debug_ranges 0x3df0 0x0 -.debug_line 0x21856 0x0 -.debug_str 0x69b64 0x0 -Total 0x1ab17a +.debug_frame 0x5e40 0x0 +.debug_info 0xaa081 0x0 +.debug_abbrev 0xae57 0x0 +.debug_loc 0x1e532 0x0 +.debug_aranges 0x20d8 0x0 +.debug_ranges 0x3e90 0x0 +.debug_line 0x21ac2 0x0 +.debug_str 0x69dec 0x0 +Total 0x1ac3e7 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 186596 + 187504 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 34328 + 34368 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4207A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4207A_REGION_EU_size.txt index 854072630f..f9e3ad37b5 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4207A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4207A_REGION_EU_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x2d8fc 0x0 -_cmd_handlers 0x2e0 0x2d8fc -_zw_protocol_cmd_handlers 0xe8 0x2dbdc -_zw_protocol_cmd_handlers_lr 0x48 0x2dcc4 -.ARM.exidx 0x8 0x2dd0c -.copy.table 0xc 0x2dd14 -.zero.table 0x0 0x2dd20 +.text 0x2dcb4 0x0 +_cmd_handlers 0x2e0 0x2dcb4 +_zw_protocol_cmd_handlers 0xe8 0x2df94 +_zw_protocol_cmd_handlers_lr 0x48 0x2e07c +.ARM.exidx 0x8 0x2e0c4 +.copy.table 0xc 0x2e0cc +.zero.table 0x0 0x2e0d8 .stack 0x600 0x20000000 -.data 0x360 0x20000600 -.bss 0x7a58 0x20000960 -.heap 0x7c48 0x200083b8 -.zwave_nvm 0x3000 0x2dd20 -.nvm 0x9000 0x30d20 +.data 0x364 0x20000600 +.bss 0x7a8c 0x20000964 +.heap 0x7c10 0x200083f0 +.zwave_nvm 0x3000 0x2e0d8 +.nvm 0x9000 0x310d8 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x5e24 0x0 -.debug_info 0xab038 0x0 -.debug_abbrev 0xade4 0x0 -.debug_loc 0x1e84c 0x0 -.debug_aranges 0x20f0 0x0 -.debug_ranges 0x3e90 0x0 -.debug_line 0x21a3a 0x0 -.debug_str 0x6a109 0x0 -Total 0x1b5ce6 +.debug_frame 0x5e5c 0x0 +.debug_info 0xab726 0x0 +.debug_abbrev 0xae3b 0x0 +.debug_loc 0x1ea1a 0x0 +.debug_aranges 0x2108 0x0 +.debug_ranges 0x3f30 0x0 +.debug_line 0x21ca6 0x0 +.debug_str 0x6a390 0x0 +Total 0x1b6f94 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 188544 + 189500 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 35768 + 35824 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4207A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4207A_REGION_US_LR_size.txt index 854072630f..f9e3ad37b5 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4207A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4207A_REGION_US_LR_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x2d8fc 0x0 -_cmd_handlers 0x2e0 0x2d8fc -_zw_protocol_cmd_handlers 0xe8 0x2dbdc -_zw_protocol_cmd_handlers_lr 0x48 0x2dcc4 -.ARM.exidx 0x8 0x2dd0c -.copy.table 0xc 0x2dd14 -.zero.table 0x0 0x2dd20 +.text 0x2dcb4 0x0 +_cmd_handlers 0x2e0 0x2dcb4 +_zw_protocol_cmd_handlers 0xe8 0x2df94 +_zw_protocol_cmd_handlers_lr 0x48 0x2e07c +.ARM.exidx 0x8 0x2e0c4 +.copy.table 0xc 0x2e0cc +.zero.table 0x0 0x2e0d8 .stack 0x600 0x20000000 -.data 0x360 0x20000600 -.bss 0x7a58 0x20000960 -.heap 0x7c48 0x200083b8 -.zwave_nvm 0x3000 0x2dd20 -.nvm 0x9000 0x30d20 +.data 0x364 0x20000600 +.bss 0x7a8c 0x20000964 +.heap 0x7c10 0x200083f0 +.zwave_nvm 0x3000 0x2e0d8 +.nvm 0x9000 0x310d8 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x5e24 0x0 -.debug_info 0xab038 0x0 -.debug_abbrev 0xade4 0x0 -.debug_loc 0x1e84c 0x0 -.debug_aranges 0x20f0 0x0 -.debug_ranges 0x3e90 0x0 -.debug_line 0x21a3a 0x0 -.debug_str 0x6a109 0x0 -Total 0x1b5ce6 +.debug_frame 0x5e5c 0x0 +.debug_info 0xab726 0x0 +.debug_abbrev 0xae3b 0x0 +.debug_loc 0x1ea1a 0x0 +.debug_aranges 0x2108 0x0 +.debug_ranges 0x3f30 0x0 +.debug_line 0x21ca6 0x0 +.debug_str 0x6a390 0x0 +Total 0x1b6f94 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 188544 + 189500 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 35768 + 35824 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4207A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4207A_REGION_US_size.txt index b5170c5b4d..130a33f9b8 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4207A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4207A_REGION_US_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x2d8fc 0x0 -_cmd_handlers 0x2e0 0x2d8fc -_zw_protocol_cmd_handlers 0xe8 0x2dbdc -_zw_protocol_cmd_handlers_lr 0x48 0x2dcc4 -.ARM.exidx 0x8 0x2dd0c -.copy.table 0xc 0x2dd14 -.zero.table 0x0 0x2dd20 +.text 0x2dcb4 0x0 +_cmd_handlers 0x2e0 0x2dcb4 +_zw_protocol_cmd_handlers 0xe8 0x2df94 +_zw_protocol_cmd_handlers_lr 0x48 0x2e07c +.ARM.exidx 0x8 0x2e0c4 +.copy.table 0xc 0x2e0cc +.zero.table 0x0 0x2e0d8 .stack 0x600 0x20000000 -.data 0x360 0x20000600 -.bss 0x7a58 0x20000960 -.heap 0x7c48 0x200083b8 -.zwave_nvm 0x3000 0x2dd20 -.nvm 0x9000 0x30d20 +.data 0x364 0x20000600 +.bss 0x7a8c 0x20000964 +.heap 0x7c10 0x200083f0 +.zwave_nvm 0x3000 0x2e0d8 +.nvm 0x9000 0x310d8 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x5e24 0x0 -.debug_info 0xab039 0x0 -.debug_abbrev 0xade4 0x0 -.debug_loc 0x1e84c 0x0 -.debug_aranges 0x20f0 0x0 -.debug_ranges 0x3e90 0x0 -.debug_line 0x21a3a 0x0 -.debug_str 0x6a109 0x0 -Total 0x1b5ce7 +.debug_frame 0x5e5c 0x0 +.debug_info 0xab727 0x0 +.debug_abbrev 0xae3b 0x0 +.debug_loc 0x1ea1a 0x0 +.debug_aranges 0x2108 0x0 +.debug_ranges 0x3f30 0x0 +.debug_line 0x21ca6 0x0 +.debug_str 0x6a390 0x0 +Total 0x1b6f95 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 188544 + 189500 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 35768 + 35824 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4208A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4208A_REGION_EU_size.txt index f31a704479..69ddee9b8b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4208A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4208A_REGION_EU_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x2d154 0x0 -_cmd_handlers 0x2e0 0x2d154 -_zw_protocol_cmd_handlers 0xe8 0x2d434 -_zw_protocol_cmd_handlers_lr 0x48 0x2d51c -.ARM.exidx 0x8 0x2d564 -.copy.table 0xc 0x2d56c -.zero.table 0x0 0x2d578 +.text 0x2d4dc 0x0 +_cmd_handlers 0x2e0 0x2d4dc +_zw_protocol_cmd_handlers 0xe8 0x2d7bc +_zw_protocol_cmd_handlers_lr 0x48 0x2d8a4 +.ARM.exidx 0x8 0x2d8ec +.copy.table 0xc 0x2d8f4 +.zero.table 0x0 0x2d900 .stack 0x600 0x20000000 -.data 0x35c 0x20000600 -.bss 0x74bc 0x2000095c -.heap 0x1e8 0x20007e18 -.zwave_nvm 0x3000 0x2d578 -.nvm 0x9000 0x30578 +.data 0x360 0x20000600 +.bss 0x74e0 0x20000960 +.heap 0x1c0 0x20007e40 +.zwave_nvm 0x3000 0x2d900 +.nvm 0x9000 0x30900 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x5e08 0x0 -.debug_info 0xa9991 0x0 -.debug_abbrev 0xae13 0x0 -.debug_loc 0x1e364 0x0 -.debug_aranges 0x20c0 0x0 -.debug_ranges 0x3df0 0x0 -.debug_line 0x21856 0x0 -.debug_str 0x69b64 0x0 -Total 0x1ab169 +.debug_frame 0x5e40 0x0 +.debug_info 0xaa080 0x0 +.debug_abbrev 0xae57 0x0 +.debug_loc 0x1e532 0x0 +.debug_aranges 0x20d8 0x0 +.debug_ranges 0x3e90 0x0 +.debug_line 0x21ac2 0x0 +.debug_str 0x69dec 0x0 +Total 0x1ac3d6 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 186580 + 187488 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 34328 + 34368 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4208A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4208A_REGION_US_LR_size.txt index f31a704479..69ddee9b8b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4208A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4208A_REGION_US_LR_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x2d154 0x0 -_cmd_handlers 0x2e0 0x2d154 -_zw_protocol_cmd_handlers 0xe8 0x2d434 -_zw_protocol_cmd_handlers_lr 0x48 0x2d51c -.ARM.exidx 0x8 0x2d564 -.copy.table 0xc 0x2d56c -.zero.table 0x0 0x2d578 +.text 0x2d4dc 0x0 +_cmd_handlers 0x2e0 0x2d4dc +_zw_protocol_cmd_handlers 0xe8 0x2d7bc +_zw_protocol_cmd_handlers_lr 0x48 0x2d8a4 +.ARM.exidx 0x8 0x2d8ec +.copy.table 0xc 0x2d8f4 +.zero.table 0x0 0x2d900 .stack 0x600 0x20000000 -.data 0x35c 0x20000600 -.bss 0x74bc 0x2000095c -.heap 0x1e8 0x20007e18 -.zwave_nvm 0x3000 0x2d578 -.nvm 0x9000 0x30578 +.data 0x360 0x20000600 +.bss 0x74e0 0x20000960 +.heap 0x1c0 0x20007e40 +.zwave_nvm 0x3000 0x2d900 +.nvm 0x9000 0x30900 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x5e08 0x0 -.debug_info 0xa9991 0x0 -.debug_abbrev 0xae13 0x0 -.debug_loc 0x1e364 0x0 -.debug_aranges 0x20c0 0x0 -.debug_ranges 0x3df0 0x0 -.debug_line 0x21856 0x0 -.debug_str 0x69b64 0x0 -Total 0x1ab169 +.debug_frame 0x5e40 0x0 +.debug_info 0xaa080 0x0 +.debug_abbrev 0xae57 0x0 +.debug_loc 0x1e532 0x0 +.debug_aranges 0x20d8 0x0 +.debug_ranges 0x3e90 0x0 +.debug_line 0x21ac2 0x0 +.debug_str 0x69dec 0x0 +Total 0x1ac3d6 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 186580 + 187488 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 34328 + 34368 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4208A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4208A_REGION_US_size.txt index ba3fe808da..b67e3d006a 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4208A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4208A_REGION_US_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x2d164 0x0 -_cmd_handlers 0x2e0 0x2d164 -_zw_protocol_cmd_handlers 0xe8 0x2d444 -_zw_protocol_cmd_handlers_lr 0x48 0x2d52c -.ARM.exidx 0x8 0x2d574 -.copy.table 0xc 0x2d57c -.zero.table 0x0 0x2d588 +.text 0x2d4ec 0x0 +_cmd_handlers 0x2e0 0x2d4ec +_zw_protocol_cmd_handlers 0xe8 0x2d7cc +_zw_protocol_cmd_handlers_lr 0x48 0x2d8b4 +.ARM.exidx 0x8 0x2d8fc +.copy.table 0xc 0x2d904 +.zero.table 0x0 0x2d910 .stack 0x600 0x20000000 -.data 0x35c 0x20000600 -.bss 0x74bc 0x2000095c -.heap 0x1e8 0x20007e18 -.zwave_nvm 0x3000 0x2d588 -.nvm 0x9000 0x30588 +.data 0x360 0x20000600 +.bss 0x74e0 0x20000960 +.heap 0x1c0 0x20007e40 +.zwave_nvm 0x3000 0x2d910 +.nvm 0x9000 0x30910 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x5e08 0x0 -.debug_info 0xa9992 0x0 -.debug_abbrev 0xae13 0x0 -.debug_loc 0x1e364 0x0 -.debug_aranges 0x20c0 0x0 -.debug_ranges 0x3df0 0x0 -.debug_line 0x21856 0x0 -.debug_str 0x69b64 0x0 -Total 0x1ab17a +.debug_frame 0x5e40 0x0 +.debug_info 0xaa081 0x0 +.debug_abbrev 0xae57 0x0 +.debug_loc 0x1e532 0x0 +.debug_aranges 0x20d8 0x0 +.debug_ranges 0x3e90 0x0 +.debug_line 0x21ac2 0x0 +.debug_str 0x69dec 0x0 +Total 0x1ac3e7 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 186596 + 187504 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 34328 + 34368 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4210A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4210A_REGION_US_LR_size.txt index 9d80a209ab..dcf23e1732 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4210A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_controller_BRD4210A_REGION_US_LR_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_controller.out : section size addr -.text 0x31cf8 0x8006000 -_cmd_handlers 0x2d8 0x8037cf8 -_zw_protocol_cmd_handlers 0xe8 0x8037fd0 -_zw_protocol_cmd_handlers_lr 0x48 0x80380b8 -.ARM.exidx 0x8 0x8038100 -.copy.table 0xc 0x8038108 -.zero.table 0x0 0x8038114 +.text 0x32220 0x8006000 +_cmd_handlers 0x2e0 0x8038220 +_zw_protocol_cmd_handlers 0xe8 0x8038500 +_zw_protocol_cmd_handlers_lr 0x48 0x80385e8 +.ARM.exidx 0x8 0x8038630 +.copy.table 0xc 0x8038638 +.zero.table 0x0 0x8038644 .stack 0x600 0x20000000 -.data 0x4cc 0x20000600 -.bss 0xa9d4 0x20000acc -.heap 0x4b60 0x2000b4a0 -.zwave_nvm 0x6000 0x8038114 -.nvm 0xa000 0x803e114 +.data 0x4d0 0x20000600 +.bss 0xaa00 0x20000ad0 +.heap 0x4b30 0x2000b4d0 +.zwave_nvm 0x6000 0x8038644 +.nvm 0xa000 0x803e644 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x83b4 0x0 -.debug_info 0xe34d5 0x0 -.debug_abbrev 0xdb09 0x0 -.debug_loc 0x2fdbb 0x0 -.debug_aranges 0x2bb8 0x0 -.debug_ranges 0x54a0 0x0 -.debug_line 0x2cd36 0x0 -.debug_str 0x74db1 0x0 -Total 0x224e1f +.debug_frame 0x8430 0x0 +.debug_info 0xe53b5 0x0 +.debug_abbrev 0xddd0 0x0 +.debug_loc 0x30091 0x0 +.debug_aranges 0x2bf0 0x0 +.debug_ranges 0x54f0 0x0 +.debug_line 0x2d38d 0x0 +.debug_str 0x7522a 0x0 +Total 0x2283a0 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 206304 + 207636 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 65536 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48288 + 48336 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4202A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4202A_REGION_EU_size.txt index 35bfd65d2a..d476c5c570 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4202A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4202A_REGION_EU_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x2b44c 0x0 -_cmd_handlers 0x1b8 0x2b44c -_zw_protocol_cmd_handlers 0x70 0x2b604 -_zw_protocol_cmd_handlers_lr 0x30 0x2b674 -.ARM.exidx 0x8 0x2b6a4 -.copy.table 0xc 0x2b6ac -.zero.table 0x0 0x2b6b8 +.text 0x2b6ac 0x0 +_cmd_handlers 0x1b8 0x2b6ac +_zw_protocol_cmd_handlers 0x70 0x2b864 +_zw_protocol_cmd_handlers_lr 0x30 0x2b8d4 +.ARM.exidx 0x8 0x2b904 +.copy.table 0xc 0x2b90c +.zero.table 0x0 0x2b918 .stack 0x1000 0x20000000 .data 0x370 0x20001000 -.bss 0xa750 0x20001370 -.heap 0x4540 0x2000bac0 -.zwave_nvm 0x3000 0x2b6b8 -.nvm 0x9000 0x2e6b8 +.bss 0xa778 0x20001370 +.heap 0x4518 0x2000bae8 +.zwave_nvm 0x3000 0x2b918 +.nvm 0x9000 0x2e918 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6064 0x0 -.debug_info 0xad589 0x0 -.debug_abbrev 0xbdff 0x0 -.debug_loc 0x20d06 0x0 -.debug_aranges 0x21d8 0x0 -.debug_ranges 0x4018 0x0 -.debug_line 0x225c8 0x0 -.debug_str 0x69dea 0x0 -Total 0x1b9dc3 +.debug_frame 0x60c0 0x0 +.debug_info 0xadc11 0x0 +.debug_abbrev 0xbe56 0x0 +.debug_loc 0x20ead 0x0 +.debug_aranges 0x21f8 0x0 +.debug_ranges 0x4098 0x0 +.debug_line 0x227bd 0x0 +.debug_str 0x6a071 0x0 +Total 0x1bae21 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 178728 + 179336 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 49856 + 49896 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4202A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4202A_REGION_US_LR_size.txt index 35bfd65d2a..d476c5c570 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4202A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4202A_REGION_US_LR_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x2b44c 0x0 -_cmd_handlers 0x1b8 0x2b44c -_zw_protocol_cmd_handlers 0x70 0x2b604 -_zw_protocol_cmd_handlers_lr 0x30 0x2b674 -.ARM.exidx 0x8 0x2b6a4 -.copy.table 0xc 0x2b6ac -.zero.table 0x0 0x2b6b8 +.text 0x2b6ac 0x0 +_cmd_handlers 0x1b8 0x2b6ac +_zw_protocol_cmd_handlers 0x70 0x2b864 +_zw_protocol_cmd_handlers_lr 0x30 0x2b8d4 +.ARM.exidx 0x8 0x2b904 +.copy.table 0xc 0x2b90c +.zero.table 0x0 0x2b918 .stack 0x1000 0x20000000 .data 0x370 0x20001000 -.bss 0xa750 0x20001370 -.heap 0x4540 0x2000bac0 -.zwave_nvm 0x3000 0x2b6b8 -.nvm 0x9000 0x2e6b8 +.bss 0xa778 0x20001370 +.heap 0x4518 0x2000bae8 +.zwave_nvm 0x3000 0x2b918 +.nvm 0x9000 0x2e918 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6064 0x0 -.debug_info 0xad589 0x0 -.debug_abbrev 0xbdff 0x0 -.debug_loc 0x20d06 0x0 -.debug_aranges 0x21d8 0x0 -.debug_ranges 0x4018 0x0 -.debug_line 0x225c8 0x0 -.debug_str 0x69dea 0x0 -Total 0x1b9dc3 +.debug_frame 0x60c0 0x0 +.debug_info 0xadc11 0x0 +.debug_abbrev 0xbe56 0x0 +.debug_loc 0x20ead 0x0 +.debug_aranges 0x21f8 0x0 +.debug_ranges 0x4098 0x0 +.debug_line 0x227bd 0x0 +.debug_str 0x6a071 0x0 +Total 0x1bae21 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 178728 + 179336 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 49856 + 49896 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4202A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4202A_REGION_US_size.txt index ca9f49067d..42a3af1ea7 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4202A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4202A_REGION_US_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x2b45c 0x0 -_cmd_handlers 0x1b8 0x2b45c -_zw_protocol_cmd_handlers 0x70 0x2b614 -_zw_protocol_cmd_handlers_lr 0x30 0x2b684 -.ARM.exidx 0x8 0x2b6b4 -.copy.table 0xc 0x2b6bc -.zero.table 0x0 0x2b6c8 +.text 0x2b6bc 0x0 +_cmd_handlers 0x1b8 0x2b6bc +_zw_protocol_cmd_handlers 0x70 0x2b874 +_zw_protocol_cmd_handlers_lr 0x30 0x2b8e4 +.ARM.exidx 0x8 0x2b914 +.copy.table 0xc 0x2b91c +.zero.table 0x0 0x2b928 .stack 0x1000 0x20000000 .data 0x370 0x20001000 -.bss 0xa750 0x20001370 -.heap 0x4540 0x2000bac0 -.zwave_nvm 0x3000 0x2b6c8 -.nvm 0x9000 0x2e6c8 +.bss 0xa778 0x20001370 +.heap 0x4518 0x2000bae8 +.zwave_nvm 0x3000 0x2b928 +.nvm 0x9000 0x2e928 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6064 0x0 -.debug_info 0xad58a 0x0 -.debug_abbrev 0xbdff 0x0 -.debug_loc 0x20d06 0x0 -.debug_aranges 0x21d8 0x0 -.debug_ranges 0x4018 0x0 -.debug_line 0x225c8 0x0 -.debug_str 0x69dea 0x0 -Total 0x1b9dd4 +.debug_frame 0x60c0 0x0 +.debug_info 0xadc12 0x0 +.debug_abbrev 0xbe56 0x0 +.debug_loc 0x20ead 0x0 +.debug_aranges 0x21f8 0x0 +.debug_ranges 0x4098 0x0 +.debug_line 0x227bd 0x0 +.debug_str 0x6a071 0x0 +Total 0x1bae32 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 178744 + 179352 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 49856 + 49896 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204C_REGION_EU_size.txt index 6debba958e..d6addee833 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204C_REGION_EU_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x332f0 0x8006000 -_cmd_handlers 0x1b8 0x80392f0 -_zw_protocol_cmd_handlers 0x70 0x80394a8 -_zw_protocol_cmd_handlers_lr 0x30 0x8039518 -.ARM.exidx 0x8 0x8039548 -.copy.table 0xc 0x8039550 -.zero.table 0x0 0x803955c +.text 0x32888 0x8006000 +_cmd_handlers 0x1b8 0x8038888 +_zw_protocol_cmd_handlers 0x70 0x8038a40 +_zw_protocol_cmd_handlers_lr 0x30 0x8038ab0 +.ARM.exidx 0x8 0x8038ae0 +.copy.table 0xc 0x8038ae8 +.zero.table 0x0 0x8038af4 .stack 0x1000 0x20000000 .data 0x4c8 0x20001000 -.bss 0xb650 0x200014c8 -.heap 0x34e8 0x2000cb18 -.zwave_nvm 0x6000 0x803955c -.nvm 0xa000 0x803f55c +.bss 0xb678 0x200014c8 +.heap 0x34c0 0x2000cb40 +.zwave_nvm 0x6000 0x8038af4 +.nvm 0x8000 0x803eaf4 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9c7c 0x0 -.debug_info 0xfd5bd 0x0 -.debug_abbrev 0x12088 0x0 -.debug_loc 0x41cd8 0x0 -.debug_aranges 0x3370 0x0 -.debug_ranges 0x6610 0x0 -.debug_line 0x3a6c9 0x0 -.debug_str 0x767f6 0x0 -Total 0x268db3 +.debug_frame 0x9c40 0x0 +.debug_info 0xfd267 0x0 +.debug_abbrev 0x11e56 0x0 +.debug_loc 0x419d1 0x0 +.debug_aranges 0x3350 0x0 +.debug_ranges 0x6548 0x0 +.debug_line 0x3a329 0x0 +.debug_str 0x76988 0x0 +Total 0x26578a The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 211492 + 208828 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 54040 + 54080 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204C_REGION_US_LR_size.txt index 6debba958e..d6addee833 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204C_REGION_US_LR_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x332f0 0x8006000 -_cmd_handlers 0x1b8 0x80392f0 -_zw_protocol_cmd_handlers 0x70 0x80394a8 -_zw_protocol_cmd_handlers_lr 0x30 0x8039518 -.ARM.exidx 0x8 0x8039548 -.copy.table 0xc 0x8039550 -.zero.table 0x0 0x803955c +.text 0x32888 0x8006000 +_cmd_handlers 0x1b8 0x8038888 +_zw_protocol_cmd_handlers 0x70 0x8038a40 +_zw_protocol_cmd_handlers_lr 0x30 0x8038ab0 +.ARM.exidx 0x8 0x8038ae0 +.copy.table 0xc 0x8038ae8 +.zero.table 0x0 0x8038af4 .stack 0x1000 0x20000000 .data 0x4c8 0x20001000 -.bss 0xb650 0x200014c8 -.heap 0x34e8 0x2000cb18 -.zwave_nvm 0x6000 0x803955c -.nvm 0xa000 0x803f55c +.bss 0xb678 0x200014c8 +.heap 0x34c0 0x2000cb40 +.zwave_nvm 0x6000 0x8038af4 +.nvm 0x8000 0x803eaf4 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9c7c 0x0 -.debug_info 0xfd5bd 0x0 -.debug_abbrev 0x12088 0x0 -.debug_loc 0x41cd8 0x0 -.debug_aranges 0x3370 0x0 -.debug_ranges 0x6610 0x0 -.debug_line 0x3a6c9 0x0 -.debug_str 0x767f6 0x0 -Total 0x268db3 +.debug_frame 0x9c40 0x0 +.debug_info 0xfd267 0x0 +.debug_abbrev 0x11e56 0x0 +.debug_loc 0x419d1 0x0 +.debug_aranges 0x3350 0x0 +.debug_ranges 0x6548 0x0 +.debug_line 0x3a329 0x0 +.debug_str 0x76988 0x0 +Total 0x26578a The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 211492 + 208828 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 54040 + 54080 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204C_REGION_US_size.txt index 6debba958e..d6addee833 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204C_REGION_US_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x332f0 0x8006000 -_cmd_handlers 0x1b8 0x80392f0 -_zw_protocol_cmd_handlers 0x70 0x80394a8 -_zw_protocol_cmd_handlers_lr 0x30 0x8039518 -.ARM.exidx 0x8 0x8039548 -.copy.table 0xc 0x8039550 -.zero.table 0x0 0x803955c +.text 0x32888 0x8006000 +_cmd_handlers 0x1b8 0x8038888 +_zw_protocol_cmd_handlers 0x70 0x8038a40 +_zw_protocol_cmd_handlers_lr 0x30 0x8038ab0 +.ARM.exidx 0x8 0x8038ae0 +.copy.table 0xc 0x8038ae8 +.zero.table 0x0 0x8038af4 .stack 0x1000 0x20000000 .data 0x4c8 0x20001000 -.bss 0xb650 0x200014c8 -.heap 0x34e8 0x2000cb18 -.zwave_nvm 0x6000 0x803955c -.nvm 0xa000 0x803f55c +.bss 0xb678 0x200014c8 +.heap 0x34c0 0x2000cb40 +.zwave_nvm 0x6000 0x8038af4 +.nvm 0x8000 0x803eaf4 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9c7c 0x0 -.debug_info 0xfd5bd 0x0 -.debug_abbrev 0x12088 0x0 -.debug_loc 0x41cd8 0x0 -.debug_aranges 0x3370 0x0 -.debug_ranges 0x6610 0x0 -.debug_line 0x3a6c9 0x0 -.debug_str 0x767f6 0x0 -Total 0x268db3 +.debug_frame 0x9c40 0x0 +.debug_info 0xfd267 0x0 +.debug_abbrev 0x11e56 0x0 +.debug_loc 0x419d1 0x0 +.debug_aranges 0x3350 0x0 +.debug_ranges 0x6548 0x0 +.debug_line 0x3a329 0x0 +.debug_str 0x76988 0x0 +Total 0x26578a The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 211492 + 208828 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 54040 + 54080 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204D_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204D_REGION_EU_size.txt index f2c3e3d37f..e5b9e09855 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204D_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204D_REGION_EU_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x333bc 0x8006000 -_cmd_handlers 0x1b8 0x80393bc -_zw_protocol_cmd_handlers 0x70 0x8039574 -_zw_protocol_cmd_handlers_lr 0x30 0x80395e4 -.ARM.exidx 0x8 0x8039614 -.copy.table 0xc 0x803961c -.zero.table 0x0 0x8039628 +.text 0x3294c 0x8006000 +_cmd_handlers 0x1b8 0x803894c +_zw_protocol_cmd_handlers 0x70 0x8038b04 +_zw_protocol_cmd_handlers_lr 0x30 0x8038b74 +.ARM.exidx 0x8 0x8038ba4 +.copy.table 0xc 0x8038bac +.zero.table 0x0 0x8038bb8 .stack 0x1000 0x20000000 .data 0x4cc 0x20001000 -.bss 0xb654 0x200014cc -.heap 0x34e0 0x2000cb20 -.zwave_nvm 0x6000 0x8039628 -.nvm 0xa000 0x803f628 +.bss 0xb67c 0x200014cc +.heap 0x34b8 0x2000cb48 +.zwave_nvm 0x6000 0x8038bb8 +.nvm 0x8000 0x803ebb8 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9cac 0x0 -.debug_info 0xfd820 0x0 -.debug_abbrev 0x12174 0x0 -.debug_loc 0x41cd8 0x0 -.debug_aranges 0x3390 0x0 -.debug_ranges 0x6620 0x0 -.debug_line 0x3a8af 0x0 -.debug_str 0x769c9 0x0 -Total 0x2695e7 +.debug_frame 0x9c70 0x0 +.debug_info 0xfd4ca 0x0 +.debug_abbrev 0x11f42 0x0 +.debug_loc 0x419d1 0x0 +.debug_aranges 0x3370 0x0 +.debug_ranges 0x6558 0x0 +.debug_line 0x3a50f 0x0 +.debug_str 0x76b5b 0x0 +Total 0x265fb6 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 211700 + 209028 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 54048 + 54088 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204D_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204D_REGION_US_LR_size.txt index f2c3e3d37f..e5b9e09855 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204D_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204D_REGION_US_LR_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x333bc 0x8006000 -_cmd_handlers 0x1b8 0x80393bc -_zw_protocol_cmd_handlers 0x70 0x8039574 -_zw_protocol_cmd_handlers_lr 0x30 0x80395e4 -.ARM.exidx 0x8 0x8039614 -.copy.table 0xc 0x803961c -.zero.table 0x0 0x8039628 +.text 0x3294c 0x8006000 +_cmd_handlers 0x1b8 0x803894c +_zw_protocol_cmd_handlers 0x70 0x8038b04 +_zw_protocol_cmd_handlers_lr 0x30 0x8038b74 +.ARM.exidx 0x8 0x8038ba4 +.copy.table 0xc 0x8038bac +.zero.table 0x0 0x8038bb8 .stack 0x1000 0x20000000 .data 0x4cc 0x20001000 -.bss 0xb654 0x200014cc -.heap 0x34e0 0x2000cb20 -.zwave_nvm 0x6000 0x8039628 -.nvm 0xa000 0x803f628 +.bss 0xb67c 0x200014cc +.heap 0x34b8 0x2000cb48 +.zwave_nvm 0x6000 0x8038bb8 +.nvm 0x8000 0x803ebb8 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9cac 0x0 -.debug_info 0xfd820 0x0 -.debug_abbrev 0x12174 0x0 -.debug_loc 0x41cd8 0x0 -.debug_aranges 0x3390 0x0 -.debug_ranges 0x6620 0x0 -.debug_line 0x3a8af 0x0 -.debug_str 0x769c9 0x0 -Total 0x2695e7 +.debug_frame 0x9c70 0x0 +.debug_info 0xfd4ca 0x0 +.debug_abbrev 0x11f42 0x0 +.debug_loc 0x419d1 0x0 +.debug_aranges 0x3370 0x0 +.debug_ranges 0x6558 0x0 +.debug_line 0x3a50f 0x0 +.debug_str 0x76b5b 0x0 +Total 0x265fb6 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 211700 + 209028 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 54048 + 54088 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204D_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204D_REGION_US_size.txt index f2c3e3d37f..e5b9e09855 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204D_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4204D_REGION_US_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x333bc 0x8006000 -_cmd_handlers 0x1b8 0x80393bc -_zw_protocol_cmd_handlers 0x70 0x8039574 -_zw_protocol_cmd_handlers_lr 0x30 0x80395e4 -.ARM.exidx 0x8 0x8039614 -.copy.table 0xc 0x803961c -.zero.table 0x0 0x8039628 +.text 0x3294c 0x8006000 +_cmd_handlers 0x1b8 0x803894c +_zw_protocol_cmd_handlers 0x70 0x8038b04 +_zw_protocol_cmd_handlers_lr 0x30 0x8038b74 +.ARM.exidx 0x8 0x8038ba4 +.copy.table 0xc 0x8038bac +.zero.table 0x0 0x8038bb8 .stack 0x1000 0x20000000 .data 0x4cc 0x20001000 -.bss 0xb654 0x200014cc -.heap 0x34e0 0x2000cb20 -.zwave_nvm 0x6000 0x8039628 -.nvm 0xa000 0x803f628 +.bss 0xb67c 0x200014cc +.heap 0x34b8 0x2000cb48 +.zwave_nvm 0x6000 0x8038bb8 +.nvm 0x8000 0x803ebb8 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9cac 0x0 -.debug_info 0xfd820 0x0 -.debug_abbrev 0x12174 0x0 -.debug_loc 0x41cd8 0x0 -.debug_aranges 0x3390 0x0 -.debug_ranges 0x6620 0x0 -.debug_line 0x3a8af 0x0 -.debug_str 0x769c9 0x0 -Total 0x2695e7 +.debug_frame 0x9c70 0x0 +.debug_info 0xfd4ca 0x0 +.debug_abbrev 0x11f42 0x0 +.debug_loc 0x419d1 0x0 +.debug_aranges 0x3370 0x0 +.debug_ranges 0x6558 0x0 +.debug_line 0x3a50f 0x0 +.debug_str 0x76b5b 0x0 +Total 0x265fb6 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 211700 + 209028 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 54048 + 54088 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205A_REGION_EU_size.txt index 12630f8e2d..02a40e219c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205A_REGION_EU_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x33500 0x8006000 -_cmd_handlers 0x1b8 0x8039500 -_zw_protocol_cmd_handlers 0x70 0x80396b8 -_zw_protocol_cmd_handlers_lr 0x30 0x8039728 -.ARM.exidx 0x8 0x8039758 -.copy.table 0xc 0x8039760 -.zero.table 0x0 0x803976c +.text 0x32810 0x8006000 +_cmd_handlers 0x1b8 0x8038810 +_zw_protocol_cmd_handlers 0x70 0x80389c8 +_zw_protocol_cmd_handlers_lr 0x30 0x8038a38 +.ARM.exidx 0x8 0x8038a68 +.copy.table 0xc 0x8038a70 +.zero.table 0x0 0x8038a7c .stack 0x1000 0x20000000 .data 0x4c8 0x20001000 -.bss 0xb540 0x200014c8 -.heap 0x35f8 0x2000ca08 -.zwave_nvm 0x6000 0x803976c -.nvm 0xa000 0x803f76c +.bss 0xb568 0x200014c8 +.heap 0x35d0 0x2000ca30 +.zwave_nvm 0x6000 0x8038a7c +.nvm 0x8000 0x803ea7c .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9a6c 0x0 -.debug_info 0xfbe0a 0x0 -.debug_abbrev 0x12484 0x0 -.debug_loc 0x3ff9a 0x0 -.debug_aranges 0x3370 0x0 -.debug_ranges 0x64f0 0x0 -.debug_line 0x39517 0x0 -.debug_str 0x76d50 0x0 -Total 0x264f46 +.debug_frame 0x96a8 0x0 +.debug_info 0xf96aa 0x0 +.debug_abbrev 0x11bc6 0x0 +.debug_loc 0x3d323 0x0 +.debug_aranges 0x3270 0x0 +.debug_ranges 0x6318 0x0 +.debug_line 0x37fa9 0x0 +.debug_str 0x76936 0x0 +Total 0x25a59d The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 212020 + 208708 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 53768 + 53808 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205A_REGION_US_LR_size.txt index 12630f8e2d..02a40e219c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205A_REGION_US_LR_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x33500 0x8006000 -_cmd_handlers 0x1b8 0x8039500 -_zw_protocol_cmd_handlers 0x70 0x80396b8 -_zw_protocol_cmd_handlers_lr 0x30 0x8039728 -.ARM.exidx 0x8 0x8039758 -.copy.table 0xc 0x8039760 -.zero.table 0x0 0x803976c +.text 0x32810 0x8006000 +_cmd_handlers 0x1b8 0x8038810 +_zw_protocol_cmd_handlers 0x70 0x80389c8 +_zw_protocol_cmd_handlers_lr 0x30 0x8038a38 +.ARM.exidx 0x8 0x8038a68 +.copy.table 0xc 0x8038a70 +.zero.table 0x0 0x8038a7c .stack 0x1000 0x20000000 .data 0x4c8 0x20001000 -.bss 0xb540 0x200014c8 -.heap 0x35f8 0x2000ca08 -.zwave_nvm 0x6000 0x803976c -.nvm 0xa000 0x803f76c +.bss 0xb568 0x200014c8 +.heap 0x35d0 0x2000ca30 +.zwave_nvm 0x6000 0x8038a7c +.nvm 0x8000 0x803ea7c .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9a6c 0x0 -.debug_info 0xfbe0a 0x0 -.debug_abbrev 0x12484 0x0 -.debug_loc 0x3ff9a 0x0 -.debug_aranges 0x3370 0x0 -.debug_ranges 0x64f0 0x0 -.debug_line 0x39517 0x0 -.debug_str 0x76d50 0x0 -Total 0x264f46 +.debug_frame 0x96a8 0x0 +.debug_info 0xf96aa 0x0 +.debug_abbrev 0x11bc6 0x0 +.debug_loc 0x3d323 0x0 +.debug_aranges 0x3270 0x0 +.debug_ranges 0x6318 0x0 +.debug_line 0x37fa9 0x0 +.debug_str 0x76936 0x0 +Total 0x25a59d The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 212020 + 208708 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 53768 + 53808 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205A_REGION_US_size.txt index 12630f8e2d..02a40e219c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205A_REGION_US_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x33500 0x8006000 -_cmd_handlers 0x1b8 0x8039500 -_zw_protocol_cmd_handlers 0x70 0x80396b8 -_zw_protocol_cmd_handlers_lr 0x30 0x8039728 -.ARM.exidx 0x8 0x8039758 -.copy.table 0xc 0x8039760 -.zero.table 0x0 0x803976c +.text 0x32810 0x8006000 +_cmd_handlers 0x1b8 0x8038810 +_zw_protocol_cmd_handlers 0x70 0x80389c8 +_zw_protocol_cmd_handlers_lr 0x30 0x8038a38 +.ARM.exidx 0x8 0x8038a68 +.copy.table 0xc 0x8038a70 +.zero.table 0x0 0x8038a7c .stack 0x1000 0x20000000 .data 0x4c8 0x20001000 -.bss 0xb540 0x200014c8 -.heap 0x35f8 0x2000ca08 -.zwave_nvm 0x6000 0x803976c -.nvm 0xa000 0x803f76c +.bss 0xb568 0x200014c8 +.heap 0x35d0 0x2000ca30 +.zwave_nvm 0x6000 0x8038a7c +.nvm 0x8000 0x803ea7c .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9a6c 0x0 -.debug_info 0xfbe0a 0x0 -.debug_abbrev 0x12484 0x0 -.debug_loc 0x3ff9a 0x0 -.debug_aranges 0x3370 0x0 -.debug_ranges 0x64f0 0x0 -.debug_line 0x39517 0x0 -.debug_str 0x76d50 0x0 -Total 0x264f46 +.debug_frame 0x96a8 0x0 +.debug_info 0xf96aa 0x0 +.debug_abbrev 0x11bc6 0x0 +.debug_loc 0x3d323 0x0 +.debug_aranges 0x3270 0x0 +.debug_ranges 0x6318 0x0 +.debug_line 0x37fa9 0x0 +.debug_str 0x76936 0x0 +Total 0x25a59d The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 212020 + 208708 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 53768 + 53808 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205B_REGION_EU_size.txt index 8b7f50fc6a..473806cb43 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205B_REGION_EU_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x3384c 0x8006000 -_cmd_handlers 0x1b8 0x803984c -_zw_protocol_cmd_handlers 0x70 0x8039a04 -_zw_protocol_cmd_handlers_lr 0x30 0x8039a74 -.ARM.exidx 0x8 0x8039aa4 -.copy.table 0xc 0x8039aac -.zero.table 0x0 0x8039ab8 +.text 0x32de4 0x8006000 +_cmd_handlers 0x1b8 0x8038de4 +_zw_protocol_cmd_handlers 0x70 0x8038f9c +_zw_protocol_cmd_handlers_lr 0x30 0x803900c +.ARM.exidx 0x8 0x803903c +.copy.table 0xc 0x8039044 +.zero.table 0x0 0x8039050 .stack 0x1000 0x20000000 .data 0x4c8 0x20001000 -.bss 0xb670 0x200014c8 -.heap 0x34c8 0x2000cb38 -.zwave_nvm 0x6000 0x8039ab8 -.nvm 0xa000 0x803fab8 +.bss 0xb698 0x200014c8 +.heap 0x34a0 0x2000cb60 +.zwave_nvm 0x6000 0x8039050 +.nvm 0x8000 0x803f050 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9c7c 0x0 -.debug_info 0xfe038 0x0 -.debug_abbrev 0x121cd 0x0 -.debug_loc 0x41cc5 0x0 -.debug_aranges 0x33a0 0x0 -.debug_ranges 0x6610 0x0 -.debug_line 0x3a6c3 0x0 -.debug_str 0x770a3 0x0 -Total 0x26a793 +.debug_frame 0x9c40 0x0 +.debug_info 0xfdce2 0x0 +.debug_abbrev 0x11f9b 0x0 +.debug_loc 0x419c1 0x0 +.debug_aranges 0x3380 0x0 +.debug_ranges 0x6548 0x0 +.debug_line 0x3a323 0x0 +.debug_str 0x77234 0x0 +Total 0x26716c The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 212864 + 210200 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 54072 + 54112 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205B_REGION_US_LR_size.txt index 8b7f50fc6a..473806cb43 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205B_REGION_US_LR_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x3384c 0x8006000 -_cmd_handlers 0x1b8 0x803984c -_zw_protocol_cmd_handlers 0x70 0x8039a04 -_zw_protocol_cmd_handlers_lr 0x30 0x8039a74 -.ARM.exidx 0x8 0x8039aa4 -.copy.table 0xc 0x8039aac -.zero.table 0x0 0x8039ab8 +.text 0x32de4 0x8006000 +_cmd_handlers 0x1b8 0x8038de4 +_zw_protocol_cmd_handlers 0x70 0x8038f9c +_zw_protocol_cmd_handlers_lr 0x30 0x803900c +.ARM.exidx 0x8 0x803903c +.copy.table 0xc 0x8039044 +.zero.table 0x0 0x8039050 .stack 0x1000 0x20000000 .data 0x4c8 0x20001000 -.bss 0xb670 0x200014c8 -.heap 0x34c8 0x2000cb38 -.zwave_nvm 0x6000 0x8039ab8 -.nvm 0xa000 0x803fab8 +.bss 0xb698 0x200014c8 +.heap 0x34a0 0x2000cb60 +.zwave_nvm 0x6000 0x8039050 +.nvm 0x8000 0x803f050 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9c7c 0x0 -.debug_info 0xfe038 0x0 -.debug_abbrev 0x121cd 0x0 -.debug_loc 0x41cc5 0x0 -.debug_aranges 0x33a0 0x0 -.debug_ranges 0x6610 0x0 -.debug_line 0x3a6c3 0x0 -.debug_str 0x770a3 0x0 -Total 0x26a793 +.debug_frame 0x9c40 0x0 +.debug_info 0xfdce2 0x0 +.debug_abbrev 0x11f9b 0x0 +.debug_loc 0x419c1 0x0 +.debug_aranges 0x3380 0x0 +.debug_ranges 0x6548 0x0 +.debug_line 0x3a323 0x0 +.debug_str 0x77234 0x0 +Total 0x26716c The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 212864 + 210200 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 54072 + 54112 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205B_REGION_US_size.txt index 8b7f50fc6a..473806cb43 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4205B_REGION_US_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x3384c 0x8006000 -_cmd_handlers 0x1b8 0x803984c -_zw_protocol_cmd_handlers 0x70 0x8039a04 -_zw_protocol_cmd_handlers_lr 0x30 0x8039a74 -.ARM.exidx 0x8 0x8039aa4 -.copy.table 0xc 0x8039aac -.zero.table 0x0 0x8039ab8 +.text 0x32de4 0x8006000 +_cmd_handlers 0x1b8 0x8038de4 +_zw_protocol_cmd_handlers 0x70 0x8038f9c +_zw_protocol_cmd_handlers_lr 0x30 0x803900c +.ARM.exidx 0x8 0x803903c +.copy.table 0xc 0x8039044 +.zero.table 0x0 0x8039050 .stack 0x1000 0x20000000 .data 0x4c8 0x20001000 -.bss 0xb670 0x200014c8 -.heap 0x34c8 0x2000cb38 -.zwave_nvm 0x6000 0x8039ab8 -.nvm 0xa000 0x803fab8 +.bss 0xb698 0x200014c8 +.heap 0x34a0 0x2000cb60 +.zwave_nvm 0x6000 0x8039050 +.nvm 0x8000 0x803f050 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9c7c 0x0 -.debug_info 0xfe038 0x0 -.debug_abbrev 0x121cd 0x0 -.debug_loc 0x41cc5 0x0 -.debug_aranges 0x33a0 0x0 -.debug_ranges 0x6610 0x0 -.debug_line 0x3a6c3 0x0 -.debug_str 0x770a3 0x0 -Total 0x26a793 +.debug_frame 0x9c40 0x0 +.debug_info 0xfdce2 0x0 +.debug_abbrev 0x11f9b 0x0 +.debug_loc 0x419c1 0x0 +.debug_aranges 0x3380 0x0 +.debug_ranges 0x6548 0x0 +.debug_line 0x3a323 0x0 +.debug_str 0x77234 0x0 +Total 0x26716c The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 212864 + 210200 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 54072 + 54112 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4207A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4207A_REGION_EU_size.txt index 35bfd65d2a..d476c5c570 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4207A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4207A_REGION_EU_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x2b44c 0x0 -_cmd_handlers 0x1b8 0x2b44c -_zw_protocol_cmd_handlers 0x70 0x2b604 -_zw_protocol_cmd_handlers_lr 0x30 0x2b674 -.ARM.exidx 0x8 0x2b6a4 -.copy.table 0xc 0x2b6ac -.zero.table 0x0 0x2b6b8 +.text 0x2b6ac 0x0 +_cmd_handlers 0x1b8 0x2b6ac +_zw_protocol_cmd_handlers 0x70 0x2b864 +_zw_protocol_cmd_handlers_lr 0x30 0x2b8d4 +.ARM.exidx 0x8 0x2b904 +.copy.table 0xc 0x2b90c +.zero.table 0x0 0x2b918 .stack 0x1000 0x20000000 .data 0x370 0x20001000 -.bss 0xa750 0x20001370 -.heap 0x4540 0x2000bac0 -.zwave_nvm 0x3000 0x2b6b8 -.nvm 0x9000 0x2e6b8 +.bss 0xa778 0x20001370 +.heap 0x4518 0x2000bae8 +.zwave_nvm 0x3000 0x2b918 +.nvm 0x9000 0x2e918 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6064 0x0 -.debug_info 0xad589 0x0 -.debug_abbrev 0xbdff 0x0 -.debug_loc 0x20d06 0x0 -.debug_aranges 0x21d8 0x0 -.debug_ranges 0x4018 0x0 -.debug_line 0x225c8 0x0 -.debug_str 0x69dea 0x0 -Total 0x1b9dc3 +.debug_frame 0x60c0 0x0 +.debug_info 0xadc11 0x0 +.debug_abbrev 0xbe56 0x0 +.debug_loc 0x20ead 0x0 +.debug_aranges 0x21f8 0x0 +.debug_ranges 0x4098 0x0 +.debug_line 0x227bd 0x0 +.debug_str 0x6a071 0x0 +Total 0x1bae21 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 178728 + 179336 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 49856 + 49896 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4207A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4207A_REGION_US_LR_size.txt index 35bfd65d2a..d476c5c570 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4207A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4207A_REGION_US_LR_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x2b44c 0x0 -_cmd_handlers 0x1b8 0x2b44c -_zw_protocol_cmd_handlers 0x70 0x2b604 -_zw_protocol_cmd_handlers_lr 0x30 0x2b674 -.ARM.exidx 0x8 0x2b6a4 -.copy.table 0xc 0x2b6ac -.zero.table 0x0 0x2b6b8 +.text 0x2b6ac 0x0 +_cmd_handlers 0x1b8 0x2b6ac +_zw_protocol_cmd_handlers 0x70 0x2b864 +_zw_protocol_cmd_handlers_lr 0x30 0x2b8d4 +.ARM.exidx 0x8 0x2b904 +.copy.table 0xc 0x2b90c +.zero.table 0x0 0x2b918 .stack 0x1000 0x20000000 .data 0x370 0x20001000 -.bss 0xa750 0x20001370 -.heap 0x4540 0x2000bac0 -.zwave_nvm 0x3000 0x2b6b8 -.nvm 0x9000 0x2e6b8 +.bss 0xa778 0x20001370 +.heap 0x4518 0x2000bae8 +.zwave_nvm 0x3000 0x2b918 +.nvm 0x9000 0x2e918 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6064 0x0 -.debug_info 0xad589 0x0 -.debug_abbrev 0xbdff 0x0 -.debug_loc 0x20d06 0x0 -.debug_aranges 0x21d8 0x0 -.debug_ranges 0x4018 0x0 -.debug_line 0x225c8 0x0 -.debug_str 0x69dea 0x0 -Total 0x1b9dc3 +.debug_frame 0x60c0 0x0 +.debug_info 0xadc11 0x0 +.debug_abbrev 0xbe56 0x0 +.debug_loc 0x20ead 0x0 +.debug_aranges 0x21f8 0x0 +.debug_ranges 0x4098 0x0 +.debug_line 0x227bd 0x0 +.debug_str 0x6a071 0x0 +Total 0x1bae21 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 178728 + 179336 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 49856 + 49896 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4207A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4207A_REGION_US_size.txt index ca9f49067d..42a3af1ea7 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4207A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4207A_REGION_US_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x2b45c 0x0 -_cmd_handlers 0x1b8 0x2b45c -_zw_protocol_cmd_handlers 0x70 0x2b614 -_zw_protocol_cmd_handlers_lr 0x30 0x2b684 -.ARM.exidx 0x8 0x2b6b4 -.copy.table 0xc 0x2b6bc -.zero.table 0x0 0x2b6c8 +.text 0x2b6bc 0x0 +_cmd_handlers 0x1b8 0x2b6bc +_zw_protocol_cmd_handlers 0x70 0x2b874 +_zw_protocol_cmd_handlers_lr 0x30 0x2b8e4 +.ARM.exidx 0x8 0x2b914 +.copy.table 0xc 0x2b91c +.zero.table 0x0 0x2b928 .stack 0x1000 0x20000000 .data 0x370 0x20001000 -.bss 0xa750 0x20001370 -.heap 0x4540 0x2000bac0 -.zwave_nvm 0x3000 0x2b6c8 -.nvm 0x9000 0x2e6c8 +.bss 0xa778 0x20001370 +.heap 0x4518 0x2000bae8 +.zwave_nvm 0x3000 0x2b928 +.nvm 0x9000 0x2e928 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6064 0x0 -.debug_info 0xad58a 0x0 -.debug_abbrev 0xbdff 0x0 -.debug_loc 0x20d06 0x0 -.debug_aranges 0x21d8 0x0 -.debug_ranges 0x4018 0x0 -.debug_line 0x225c8 0x0 -.debug_str 0x69dea 0x0 -Total 0x1b9dd4 +.debug_frame 0x60c0 0x0 +.debug_info 0xadc12 0x0 +.debug_abbrev 0xbe56 0x0 +.debug_loc 0x20ead 0x0 +.debug_aranges 0x21f8 0x0 +.debug_ranges 0x4098 0x0 +.debug_line 0x227bd 0x0 +.debug_str 0x6a071 0x0 +Total 0x1bae32 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 178744 + 179352 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 49856 + 49896 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4209A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4209A_REGION_US_LR_size.txt index 9c1d281e6c..3bf13064fa 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4209A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4209A_REGION_US_LR_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x2b3c8 0x0 -_cmd_handlers 0x1b8 0x2b3c8 -_zw_protocol_cmd_handlers 0x70 0x2b580 -_zw_protocol_cmd_handlers_lr 0x30 0x2b5f0 -.ARM.exidx 0x8 0x2b620 -.copy.table 0xc 0x2b628 -.zero.table 0x0 0x2b634 +.text 0x2b5e8 0x0 +_cmd_handlers 0x1b8 0x2b5e8 +_zw_protocol_cmd_handlers 0x70 0x2b7a0 +_zw_protocol_cmd_handlers_lr 0x30 0x2b810 +.ARM.exidx 0x8 0x2b840 +.copy.table 0xc 0x2b848 +.zero.table 0x0 0x2b854 .stack 0x1000 0x20000000 .data 0x36c 0x20001000 -.bss 0xa734 0x2000136c -.heap 0x4560 0x2000baa0 -.zwave_nvm 0x3000 0x2b634 -.nvm 0x9000 0x2e634 +.bss 0xa764 0x2000136c +.heap 0x4530 0x2000bad0 +.zwave_nvm 0x3000 0x2b854 +.nvm 0x9000 0x2e854 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x60cc 0x0 -.debug_info 0xadc33 0x0 -.debug_abbrev 0xc0a0 0x0 -.debug_loc 0x2104c 0x0 -.debug_aranges 0x2200 0x0 -.debug_ranges 0x4158 0x0 -.debug_line 0x22c8d 0x0 -.debug_str 0x6997a 0x0 -Total 0x1badf5 +.debug_frame 0x6128 0x0 +.debug_info 0xae2bb 0x0 +.debug_abbrev 0xc0f7 0x0 +.debug_loc 0x211f3 0x0 +.debug_aranges 0x2220 0x0 +.debug_ranges 0x41d8 0x0 +.debug_line 0x22e82 0x0 +.debug_str 0x69c02 0x0 +Total 0x1bbe14 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 178592 + 179136 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 49824 + 49872 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4210A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4210A_REGION_US_LR_size.txt index f2c3e3d37f..e5b9e09855 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4210A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_serial_api_end_device_BRD4210A_REGION_US_LR_size.txt @@ -5,37 +5,37 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_serial_api_end_device.out : section size addr -.text 0x333bc 0x8006000 -_cmd_handlers 0x1b8 0x80393bc -_zw_protocol_cmd_handlers 0x70 0x8039574 -_zw_protocol_cmd_handlers_lr 0x30 0x80395e4 -.ARM.exidx 0x8 0x8039614 -.copy.table 0xc 0x803961c -.zero.table 0x0 0x8039628 +.text 0x3294c 0x8006000 +_cmd_handlers 0x1b8 0x803894c +_zw_protocol_cmd_handlers 0x70 0x8038b04 +_zw_protocol_cmd_handlers_lr 0x30 0x8038b74 +.ARM.exidx 0x8 0x8038ba4 +.copy.table 0xc 0x8038bac +.zero.table 0x0 0x8038bb8 .stack 0x1000 0x20000000 .data 0x4cc 0x20001000 -.bss 0xb654 0x200014cc -.heap 0x34e0 0x2000cb20 -.zwave_nvm 0x6000 0x8039628 -.nvm 0xa000 0x803f628 +.bss 0xb67c 0x200014cc +.heap 0x34b8 0x2000cb48 +.zwave_nvm 0x6000 0x8038bb8 +.nvm 0x8000 0x803ebb8 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9cac 0x0 -.debug_info 0xfd820 0x0 -.debug_abbrev 0x12174 0x0 -.debug_loc 0x41cd8 0x0 -.debug_aranges 0x3390 0x0 -.debug_ranges 0x6620 0x0 -.debug_line 0x3a8af 0x0 -.debug_str 0x769c9 0x0 -Total 0x2695e7 +.debug_frame 0x9c70 0x0 +.debug_info 0xfd4ca 0x0 +.debug_abbrev 0x11f42 0x0 +.debug_loc 0x419d1 0x0 +.debug_aranges 0x3370 0x0 +.debug_ranges 0x6558 0x0 +.debug_line 0x3a50f 0x0 +.debug_str 0x76b5b 0x0 +Total 0x265fb6 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 211700 + 209028 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 54048 + 54088 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4202A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4202A_REGION_EU_size.txt index 586bb51a70..3e092a0f10 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4202A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4202A_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x2b580 0x0 -_cc_handlers_v3 0x1b0 0x2b580 -_zw_protocol_cmd_handlers 0x70 0x2b730 -_zw_protocol_cmd_handlers_lr 0x30 0x2b7a0 -.ARM.exidx 0x8 0x2b7d0 -.copy.table 0xc 0x2b7d8 -.zero.table 0x0 0x2b7e4 +.text 0x2b6dc 0x0 +_cc_handlers_v3 0x1b0 0x2b6dc +_zw_protocol_cmd_handlers 0x70 0x2b88c +_zw_protocol_cmd_handlers_lr 0x30 0x2b8fc +.ARM.exidx 0x8 0x2b92c +.copy.table 0xc 0x2b934 +.zero.table 0x0 0x2b940 .stack 0x1000 0x20000000 -.data 0x3e8 0x20001000 -.bss 0x996c 0x200013e8 -.heap 0x52a8 0x2000ad58 -.internal_storage 0x3a000 0x2b7e4 -.zwave_nvm 0x3000 0x657e4 -.nvm 0x9000 0x687e4 +.data 0x3f4 0x20001000 +.bss 0x99f4 0x200013f4 +.heap 0x5218 0x2000ade8 +.internal_storage 0x3a000 0x2b940 +.zwave_nvm 0x3000 0x65940 +.nvm 0x9000 0x68940 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x673c 0x0 -.debug_info 0x89b829 0x0 -.debug_abbrev 0xf41c 0x0 -.debug_loc 0x24f71 0x0 +.debug_frame 0x6748 0x0 +.debug_info 0x89bd20 0x0 +.debug_abbrev 0xf499 0x0 +.debug_loc 0x24f96 0x0 .debug_aranges 0x26c0 0x0 -.debug_ranges 0x4ac0 0x0 -.debug_line 0x29597 0x0 -.debug_str 0x6bfce 0x0 -Total 0x9f422e +.debug_ranges 0x4aa8 0x0 +.debug_line 0x295bb 0x0 +.debug_str 0x6c100 0x0 +Total 0x9f4a71 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 179148 + 179508 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 46420 + 46568 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4202A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4202A_REGION_US_LR_size.txt index 586bb51a70..3e092a0f10 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4202A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4202A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x2b580 0x0 -_cc_handlers_v3 0x1b0 0x2b580 -_zw_protocol_cmd_handlers 0x70 0x2b730 -_zw_protocol_cmd_handlers_lr 0x30 0x2b7a0 -.ARM.exidx 0x8 0x2b7d0 -.copy.table 0xc 0x2b7d8 -.zero.table 0x0 0x2b7e4 +.text 0x2b6dc 0x0 +_cc_handlers_v3 0x1b0 0x2b6dc +_zw_protocol_cmd_handlers 0x70 0x2b88c +_zw_protocol_cmd_handlers_lr 0x30 0x2b8fc +.ARM.exidx 0x8 0x2b92c +.copy.table 0xc 0x2b934 +.zero.table 0x0 0x2b940 .stack 0x1000 0x20000000 -.data 0x3e8 0x20001000 -.bss 0x996c 0x200013e8 -.heap 0x52a8 0x2000ad58 -.internal_storage 0x3a000 0x2b7e4 -.zwave_nvm 0x3000 0x657e4 -.nvm 0x9000 0x687e4 +.data 0x3f4 0x20001000 +.bss 0x99f4 0x200013f4 +.heap 0x5218 0x2000ade8 +.internal_storage 0x3a000 0x2b940 +.zwave_nvm 0x3000 0x65940 +.nvm 0x9000 0x68940 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x673c 0x0 -.debug_info 0x89b829 0x0 -.debug_abbrev 0xf41c 0x0 -.debug_loc 0x24f71 0x0 +.debug_frame 0x6748 0x0 +.debug_info 0x89bd20 0x0 +.debug_abbrev 0xf499 0x0 +.debug_loc 0x24f96 0x0 .debug_aranges 0x26c0 0x0 -.debug_ranges 0x4ac0 0x0 -.debug_line 0x29597 0x0 -.debug_str 0x6bfce 0x0 -Total 0x9f422e +.debug_ranges 0x4aa8 0x0 +.debug_line 0x295bb 0x0 +.debug_str 0x6c100 0x0 +Total 0x9f4a71 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 179148 + 179508 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 46420 + 46568 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4202A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4202A_REGION_US_size.txt index 586bb51a70..3e092a0f10 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4202A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4202A_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x2b580 0x0 -_cc_handlers_v3 0x1b0 0x2b580 -_zw_protocol_cmd_handlers 0x70 0x2b730 -_zw_protocol_cmd_handlers_lr 0x30 0x2b7a0 -.ARM.exidx 0x8 0x2b7d0 -.copy.table 0xc 0x2b7d8 -.zero.table 0x0 0x2b7e4 +.text 0x2b6dc 0x0 +_cc_handlers_v3 0x1b0 0x2b6dc +_zw_protocol_cmd_handlers 0x70 0x2b88c +_zw_protocol_cmd_handlers_lr 0x30 0x2b8fc +.ARM.exidx 0x8 0x2b92c +.copy.table 0xc 0x2b934 +.zero.table 0x0 0x2b940 .stack 0x1000 0x20000000 -.data 0x3e8 0x20001000 -.bss 0x996c 0x200013e8 -.heap 0x52a8 0x2000ad58 -.internal_storage 0x3a000 0x2b7e4 -.zwave_nvm 0x3000 0x657e4 -.nvm 0x9000 0x687e4 +.data 0x3f4 0x20001000 +.bss 0x99f4 0x200013f4 +.heap 0x5218 0x2000ade8 +.internal_storage 0x3a000 0x2b940 +.zwave_nvm 0x3000 0x65940 +.nvm 0x9000 0x68940 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x673c 0x0 -.debug_info 0x89b829 0x0 -.debug_abbrev 0xf41c 0x0 -.debug_loc 0x24f71 0x0 +.debug_frame 0x6748 0x0 +.debug_info 0x89bd20 0x0 +.debug_abbrev 0xf499 0x0 +.debug_loc 0x24f96 0x0 .debug_aranges 0x26c0 0x0 -.debug_ranges 0x4ac0 0x0 -.debug_line 0x29597 0x0 -.debug_str 0x6bfce 0x0 -Total 0x9f422e +.debug_ranges 0x4aa8 0x0 +.debug_line 0x295bb 0x0 +.debug_str 0x6c100 0x0 +Total 0x9f4a71 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 179148 + 179508 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 46420 + 46568 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204C_REGION_EU_size.txt index 3ad8d58bb2..7dc5ce8a7e 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204C_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x33080 0x8006000 -_cc_handlers_v3 0x1b0 0x8039080 -_zw_protocol_cmd_handlers 0x70 0x8039230 -_zw_protocol_cmd_handlers_lr 0x30 0x80392a0 -.ARM.exidx 0x8 0x80392d0 -.copy.table 0xc 0x80392d8 -.zero.table 0x0 0x80392e4 +.text 0x3250c 0x8006000 +_cc_handlers_v3 0x1b0 0x803850c +_zw_protocol_cmd_handlers 0x70 0x80386bc +_zw_protocol_cmd_handlers_lr 0x30 0x803872c +.ARM.exidx 0x8 0x803875c +.copy.table 0xc 0x8038764 +.zero.table 0x0 0x8038770 .stack 0x1000 0x20000000 -.data 0x4e4 0x20001000 -.bss 0xa7f0 0x200014e4 -.heap 0x4328 0x2000bcd8 -.internal_storage 0x2a000 0x80392e4 -.zwave_nvm 0x6000 0x80632e4 -.nvm 0xa000 0x80692e4 +.data 0x4f0 0x20001000 +.bss 0xa878 0x200014f0 +.heap 0x4298 0x2000bd68 +.internal_storage 0x2c000 0x8038770 +.zwave_nvm 0x6000 0x8064770 +.nvm 0x8000 0x806a770 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9c70 0x0 -.debug_info 0x8e2889 0x0 -.debug_abbrev 0x14cd8 0x0 -.debug_loc 0x4375a 0x0 -.debug_aranges 0x3600 0x0 -.debug_ranges 0x6ad0 0x0 -.debug_line 0x3f572 0x0 -.debug_str 0x77b64 0x0 -Total 0xa82e30 +.debug_frame 0x9bfc 0x0 +.debug_info 0x8e23fd 0x0 +.debug_abbrev 0x14ad7 0x0 +.debug_loc 0x432e6 0x0 +.debug_aranges 0x35c8 0x0 +.debug_ranges 0x6988 0x0 +.debug_line 0x3f00e 0x0 +.debug_str 0x77bbb 0x0 +Total 0xa810be The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 210888 + 207968 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 50388 + 50536 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204C_REGION_US_LR_size.txt index 3ad8d58bb2..7dc5ce8a7e 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204C_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x33080 0x8006000 -_cc_handlers_v3 0x1b0 0x8039080 -_zw_protocol_cmd_handlers 0x70 0x8039230 -_zw_protocol_cmd_handlers_lr 0x30 0x80392a0 -.ARM.exidx 0x8 0x80392d0 -.copy.table 0xc 0x80392d8 -.zero.table 0x0 0x80392e4 +.text 0x3250c 0x8006000 +_cc_handlers_v3 0x1b0 0x803850c +_zw_protocol_cmd_handlers 0x70 0x80386bc +_zw_protocol_cmd_handlers_lr 0x30 0x803872c +.ARM.exidx 0x8 0x803875c +.copy.table 0xc 0x8038764 +.zero.table 0x0 0x8038770 .stack 0x1000 0x20000000 -.data 0x4e4 0x20001000 -.bss 0xa7f0 0x200014e4 -.heap 0x4328 0x2000bcd8 -.internal_storage 0x2a000 0x80392e4 -.zwave_nvm 0x6000 0x80632e4 -.nvm 0xa000 0x80692e4 +.data 0x4f0 0x20001000 +.bss 0xa878 0x200014f0 +.heap 0x4298 0x2000bd68 +.internal_storage 0x2c000 0x8038770 +.zwave_nvm 0x6000 0x8064770 +.nvm 0x8000 0x806a770 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9c70 0x0 -.debug_info 0x8e2889 0x0 -.debug_abbrev 0x14cd8 0x0 -.debug_loc 0x4375a 0x0 -.debug_aranges 0x3600 0x0 -.debug_ranges 0x6ad0 0x0 -.debug_line 0x3f572 0x0 -.debug_str 0x77b64 0x0 -Total 0xa82e30 +.debug_frame 0x9bfc 0x0 +.debug_info 0x8e23fd 0x0 +.debug_abbrev 0x14ad7 0x0 +.debug_loc 0x432e6 0x0 +.debug_aranges 0x35c8 0x0 +.debug_ranges 0x6988 0x0 +.debug_line 0x3f00e 0x0 +.debug_str 0x77bbb 0x0 +Total 0xa810be The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 210888 + 207968 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 50388 + 50536 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204C_REGION_US_size.txt index 3ad8d58bb2..7dc5ce8a7e 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204C_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x33080 0x8006000 -_cc_handlers_v3 0x1b0 0x8039080 -_zw_protocol_cmd_handlers 0x70 0x8039230 -_zw_protocol_cmd_handlers_lr 0x30 0x80392a0 -.ARM.exidx 0x8 0x80392d0 -.copy.table 0xc 0x80392d8 -.zero.table 0x0 0x80392e4 +.text 0x3250c 0x8006000 +_cc_handlers_v3 0x1b0 0x803850c +_zw_protocol_cmd_handlers 0x70 0x80386bc +_zw_protocol_cmd_handlers_lr 0x30 0x803872c +.ARM.exidx 0x8 0x803875c +.copy.table 0xc 0x8038764 +.zero.table 0x0 0x8038770 .stack 0x1000 0x20000000 -.data 0x4e4 0x20001000 -.bss 0xa7f0 0x200014e4 -.heap 0x4328 0x2000bcd8 -.internal_storage 0x2a000 0x80392e4 -.zwave_nvm 0x6000 0x80632e4 -.nvm 0xa000 0x80692e4 +.data 0x4f0 0x20001000 +.bss 0xa878 0x200014f0 +.heap 0x4298 0x2000bd68 +.internal_storage 0x2c000 0x8038770 +.zwave_nvm 0x6000 0x8064770 +.nvm 0x8000 0x806a770 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9c70 0x0 -.debug_info 0x8e2889 0x0 -.debug_abbrev 0x14cd8 0x0 -.debug_loc 0x4375a 0x0 -.debug_aranges 0x3600 0x0 -.debug_ranges 0x6ad0 0x0 -.debug_line 0x3f572 0x0 -.debug_str 0x77b64 0x0 -Total 0xa82e30 +.debug_frame 0x9bfc 0x0 +.debug_info 0x8e23fd 0x0 +.debug_abbrev 0x14ad7 0x0 +.debug_loc 0x432e6 0x0 +.debug_aranges 0x35c8 0x0 +.debug_ranges 0x6988 0x0 +.debug_line 0x3f00e 0x0 +.debug_str 0x77bbb 0x0 +Total 0xa810be The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 210888 + 207968 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 50388 + 50536 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204D_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204D_REGION_EU_size.txt index 3993b8a310..83895c4fc1 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204D_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204D_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x33154 0x8006000 -_cc_handlers_v3 0x1b0 0x8039154 -_zw_protocol_cmd_handlers 0x70 0x8039304 -_zw_protocol_cmd_handlers_lr 0x30 0x8039374 -.ARM.exidx 0x8 0x80393a4 -.copy.table 0xc 0x80393ac -.zero.table 0x0 0x80393b8 +.text 0x325e0 0x8006000 +_cc_handlers_v3 0x1b0 0x80385e0 +_zw_protocol_cmd_handlers 0x70 0x8038790 +_zw_protocol_cmd_handlers_lr 0x30 0x8038800 +.ARM.exidx 0x8 0x8038830 +.copy.table 0xc 0x8038838 +.zero.table 0x0 0x8038844 .stack 0x1000 0x20000000 -.data 0x4e8 0x20001000 -.bss 0xa7f4 0x200014e8 -.heap 0x4320 0x2000bce0 -.internal_storage 0x2a000 0x80393b8 -.zwave_nvm 0x6000 0x80633b8 -.nvm 0xa000 0x80693b8 +.data 0x4f4 0x20001000 +.bss 0xa874 0x200014f4 +.heap 0x4298 0x2000bd68 +.internal_storage 0x2c000 0x8038844 +.zwave_nvm 0x6000 0x8064844 +.nvm 0x8000 0x806a844 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9ca0 0x0 -.debug_info 0x8e2aec 0x0 -.debug_abbrev 0x14dc4 0x0 -.debug_loc 0x4375a 0x0 -.debug_aranges 0x3620 0x0 -.debug_ranges 0x6ae0 0x0 -.debug_line 0x3f758 0x0 -.debug_str 0x77d37 0x0 -Total 0xa8366c +.debug_frame 0x9c2c 0x0 +.debug_info 0x8e2660 0x0 +.debug_abbrev 0x14bc3 0x0 +.debug_loc 0x432e6 0x0 +.debug_aranges 0x35e8 0x0 +.debug_ranges 0x6998 0x0 +.debug_line 0x3f1f4 0x0 +.debug_str 0x77d8e 0x0 +Total 0xa818fa The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 211104 + 208184 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 50396 + 50536 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204D_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204D_REGION_US_LR_size.txt index 3993b8a310..83895c4fc1 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204D_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204D_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x33154 0x8006000 -_cc_handlers_v3 0x1b0 0x8039154 -_zw_protocol_cmd_handlers 0x70 0x8039304 -_zw_protocol_cmd_handlers_lr 0x30 0x8039374 -.ARM.exidx 0x8 0x80393a4 -.copy.table 0xc 0x80393ac -.zero.table 0x0 0x80393b8 +.text 0x325e0 0x8006000 +_cc_handlers_v3 0x1b0 0x80385e0 +_zw_protocol_cmd_handlers 0x70 0x8038790 +_zw_protocol_cmd_handlers_lr 0x30 0x8038800 +.ARM.exidx 0x8 0x8038830 +.copy.table 0xc 0x8038838 +.zero.table 0x0 0x8038844 .stack 0x1000 0x20000000 -.data 0x4e8 0x20001000 -.bss 0xa7f4 0x200014e8 -.heap 0x4320 0x2000bce0 -.internal_storage 0x2a000 0x80393b8 -.zwave_nvm 0x6000 0x80633b8 -.nvm 0xa000 0x80693b8 +.data 0x4f4 0x20001000 +.bss 0xa874 0x200014f4 +.heap 0x4298 0x2000bd68 +.internal_storage 0x2c000 0x8038844 +.zwave_nvm 0x6000 0x8064844 +.nvm 0x8000 0x806a844 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9ca0 0x0 -.debug_info 0x8e2aec 0x0 -.debug_abbrev 0x14dc4 0x0 -.debug_loc 0x4375a 0x0 -.debug_aranges 0x3620 0x0 -.debug_ranges 0x6ae0 0x0 -.debug_line 0x3f758 0x0 -.debug_str 0x77d37 0x0 -Total 0xa8366c +.debug_frame 0x9c2c 0x0 +.debug_info 0x8e2660 0x0 +.debug_abbrev 0x14bc3 0x0 +.debug_loc 0x432e6 0x0 +.debug_aranges 0x35e8 0x0 +.debug_ranges 0x6998 0x0 +.debug_line 0x3f1f4 0x0 +.debug_str 0x77d8e 0x0 +Total 0xa818fa The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 211104 + 208184 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 50396 + 50536 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204D_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204D_REGION_US_size.txt index 3993b8a310..83895c4fc1 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204D_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4204D_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x33154 0x8006000 -_cc_handlers_v3 0x1b0 0x8039154 -_zw_protocol_cmd_handlers 0x70 0x8039304 -_zw_protocol_cmd_handlers_lr 0x30 0x8039374 -.ARM.exidx 0x8 0x80393a4 -.copy.table 0xc 0x80393ac -.zero.table 0x0 0x80393b8 +.text 0x325e0 0x8006000 +_cc_handlers_v3 0x1b0 0x80385e0 +_zw_protocol_cmd_handlers 0x70 0x8038790 +_zw_protocol_cmd_handlers_lr 0x30 0x8038800 +.ARM.exidx 0x8 0x8038830 +.copy.table 0xc 0x8038838 +.zero.table 0x0 0x8038844 .stack 0x1000 0x20000000 -.data 0x4e8 0x20001000 -.bss 0xa7f4 0x200014e8 -.heap 0x4320 0x2000bce0 -.internal_storage 0x2a000 0x80393b8 -.zwave_nvm 0x6000 0x80633b8 -.nvm 0xa000 0x80693b8 +.data 0x4f4 0x20001000 +.bss 0xa874 0x200014f4 +.heap 0x4298 0x2000bd68 +.internal_storage 0x2c000 0x8038844 +.zwave_nvm 0x6000 0x8064844 +.nvm 0x8000 0x806a844 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9ca0 0x0 -.debug_info 0x8e2aec 0x0 -.debug_abbrev 0x14dc4 0x0 -.debug_loc 0x4375a 0x0 -.debug_aranges 0x3620 0x0 -.debug_ranges 0x6ae0 0x0 -.debug_line 0x3f758 0x0 -.debug_str 0x77d37 0x0 -Total 0xa8366c +.debug_frame 0x9c2c 0x0 +.debug_info 0x8e2660 0x0 +.debug_abbrev 0x14bc3 0x0 +.debug_loc 0x432e6 0x0 +.debug_aranges 0x35e8 0x0 +.debug_ranges 0x6998 0x0 +.debug_line 0x3f1f4 0x0 +.debug_str 0x77d8e 0x0 +Total 0xa818fa The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 211104 + 208184 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 50396 + 50536 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205A_REGION_EU_size.txt index 854f09667c..766c143b46 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205A_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x3328c 0x8006000 -_cc_handlers_v3 0x1b0 0x803928c -_zw_protocol_cmd_handlers 0x70 0x803943c -_zw_protocol_cmd_handlers_lr 0x30 0x80394ac -.ARM.exidx 0x8 0x80394dc -.copy.table 0xc 0x80394e4 -.zero.table 0x0 0x80394f0 +.text 0x32490 0x8006000 +_cc_handlers_v3 0x1b0 0x8038490 +_zw_protocol_cmd_handlers 0x70 0x8038640 +_zw_protocol_cmd_handlers_lr 0x30 0x80386b0 +.ARM.exidx 0x8 0x80386e0 +.copy.table 0xc 0x80386e8 +.zero.table 0x0 0x80386f4 .stack 0x1000 0x20000000 -.data 0x4e4 0x20001000 -.bss 0xa6e0 0x200014e4 -.heap 0x4438 0x2000bbc8 -.internal_storage 0x2a000 0x80394f0 -.zwave_nvm 0x6000 0x80634f0 -.nvm 0xa000 0x80694f0 +.data 0x4f0 0x20001000 +.bss 0xa768 0x200014f0 +.heap 0x43a8 0x2000bc58 +.internal_storage 0x2c000 0x80386f4 +.zwave_nvm 0x6000 0x80646f4 +.nvm 0x8000 0x806a6f4 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9a60 0x0 -.debug_info 0x8e10dc 0x0 -.debug_abbrev 0x150d4 0x0 -.debug_loc 0x41a1c 0x0 -.debug_aranges 0x3600 0x0 -.debug_ranges 0x69b0 0x0 -.debug_line 0x3e3f0 0x0 -.debug_str 0x780be 0x0 -Total 0xa7eff5 +.debug_frame 0x9664 0x0 +.debug_info 0x8de846 0x0 +.debug_abbrev 0x14847 0x0 +.debug_loc 0x3ec38 0x0 +.debug_aranges 0x34e8 0x0 +.debug_ranges 0x6758 0x0 +.debug_line 0x3ccbe 0x0 +.debug_str 0x77b69 0x0 +Total 0xa75f03 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 211412 + 207844 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 50116 + 50264 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205A_REGION_US_LR_size.txt index 854f09667c..766c143b46 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x3328c 0x8006000 -_cc_handlers_v3 0x1b0 0x803928c -_zw_protocol_cmd_handlers 0x70 0x803943c -_zw_protocol_cmd_handlers_lr 0x30 0x80394ac -.ARM.exidx 0x8 0x80394dc -.copy.table 0xc 0x80394e4 -.zero.table 0x0 0x80394f0 +.text 0x32490 0x8006000 +_cc_handlers_v3 0x1b0 0x8038490 +_zw_protocol_cmd_handlers 0x70 0x8038640 +_zw_protocol_cmd_handlers_lr 0x30 0x80386b0 +.ARM.exidx 0x8 0x80386e0 +.copy.table 0xc 0x80386e8 +.zero.table 0x0 0x80386f4 .stack 0x1000 0x20000000 -.data 0x4e4 0x20001000 -.bss 0xa6e0 0x200014e4 -.heap 0x4438 0x2000bbc8 -.internal_storage 0x2a000 0x80394f0 -.zwave_nvm 0x6000 0x80634f0 -.nvm 0xa000 0x80694f0 +.data 0x4f0 0x20001000 +.bss 0xa768 0x200014f0 +.heap 0x43a8 0x2000bc58 +.internal_storage 0x2c000 0x80386f4 +.zwave_nvm 0x6000 0x80646f4 +.nvm 0x8000 0x806a6f4 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9a60 0x0 -.debug_info 0x8e10dc 0x0 -.debug_abbrev 0x150d4 0x0 -.debug_loc 0x41a1c 0x0 -.debug_aranges 0x3600 0x0 -.debug_ranges 0x69b0 0x0 -.debug_line 0x3e3f0 0x0 -.debug_str 0x780be 0x0 -Total 0xa7eff5 +.debug_frame 0x9664 0x0 +.debug_info 0x8de846 0x0 +.debug_abbrev 0x14847 0x0 +.debug_loc 0x3ec38 0x0 +.debug_aranges 0x34e8 0x0 +.debug_ranges 0x6758 0x0 +.debug_line 0x3ccbe 0x0 +.debug_str 0x77b69 0x0 +Total 0xa75f03 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 211412 + 207844 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 50116 + 50264 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205A_REGION_US_size.txt index 854f09667c..766c143b46 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205A_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x3328c 0x8006000 -_cc_handlers_v3 0x1b0 0x803928c -_zw_protocol_cmd_handlers 0x70 0x803943c -_zw_protocol_cmd_handlers_lr 0x30 0x80394ac -.ARM.exidx 0x8 0x80394dc -.copy.table 0xc 0x80394e4 -.zero.table 0x0 0x80394f0 +.text 0x32490 0x8006000 +_cc_handlers_v3 0x1b0 0x8038490 +_zw_protocol_cmd_handlers 0x70 0x8038640 +_zw_protocol_cmd_handlers_lr 0x30 0x80386b0 +.ARM.exidx 0x8 0x80386e0 +.copy.table 0xc 0x80386e8 +.zero.table 0x0 0x80386f4 .stack 0x1000 0x20000000 -.data 0x4e4 0x20001000 -.bss 0xa6e0 0x200014e4 -.heap 0x4438 0x2000bbc8 -.internal_storage 0x2a000 0x80394f0 -.zwave_nvm 0x6000 0x80634f0 -.nvm 0xa000 0x80694f0 +.data 0x4f0 0x20001000 +.bss 0xa768 0x200014f0 +.heap 0x43a8 0x2000bc58 +.internal_storage 0x2c000 0x80386f4 +.zwave_nvm 0x6000 0x80646f4 +.nvm 0x8000 0x806a6f4 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9a60 0x0 -.debug_info 0x8e10dc 0x0 -.debug_abbrev 0x150d4 0x0 -.debug_loc 0x41a1c 0x0 -.debug_aranges 0x3600 0x0 -.debug_ranges 0x69b0 0x0 -.debug_line 0x3e3f0 0x0 -.debug_str 0x780be 0x0 -Total 0xa7eff5 +.debug_frame 0x9664 0x0 +.debug_info 0x8de846 0x0 +.debug_abbrev 0x14847 0x0 +.debug_loc 0x3ec38 0x0 +.debug_aranges 0x34e8 0x0 +.debug_ranges 0x6758 0x0 +.debug_line 0x3ccbe 0x0 +.debug_str 0x77b69 0x0 +Total 0xa75f03 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 211412 + 207844 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 50116 + 50264 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205B_REGION_EU_size.txt index f79bda2ac3..90feed4c9d 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205B_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x335dc 0x8006000 -_cc_handlers_v3 0x1b0 0x80395dc -_zw_protocol_cmd_handlers 0x70 0x803978c -_zw_protocol_cmd_handlers_lr 0x30 0x80397fc -.ARM.exidx 0x8 0x803982c -.copy.table 0xc 0x8039834 -.zero.table 0x0 0x8039840 +.text 0x32a68 0x8006000 +_cc_handlers_v3 0x1b0 0x8038a68 +_zw_protocol_cmd_handlers 0x70 0x8038c18 +_zw_protocol_cmd_handlers_lr 0x30 0x8038c88 +.ARM.exidx 0x8 0x8038cb8 +.copy.table 0xc 0x8038cc0 +.zero.table 0x0 0x8038ccc .stack 0x1000 0x20000000 -.data 0x4e4 0x20001000 -.bss 0xa810 0x200014e4 -.heap 0x4308 0x2000bcf8 -.internal_storage 0x2a000 0x8039840 -.zwave_nvm 0x6000 0x8063840 -.nvm 0xa000 0x8069840 +.data 0x4f0 0x20001000 +.bss 0xa898 0x200014f0 +.heap 0x4278 0x2000bd88 +.internal_storage 0x2c000 0x8038ccc +.zwave_nvm 0x6000 0x8064ccc +.nvm 0x8000 0x806accc .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9c70 0x0 -.debug_info 0x8e3304 0x0 -.debug_abbrev 0x14e1d 0x0 -.debug_loc 0x43747 0x0 -.debug_aranges 0x3630 0x0 -.debug_ranges 0x6ad0 0x0 -.debug_line 0x3f59c 0x0 -.debug_str 0x78411 0x0 -Total 0xa84840 +.debug_frame 0x9bfc 0x0 +.debug_info 0x8e2e78 0x0 +.debug_abbrev 0x14c1c 0x0 +.debug_loc 0x432d6 0x0 +.debug_aranges 0x35f8 0x0 +.debug_ranges 0x6988 0x0 +.debug_line 0x3f038 0x0 +.debug_str 0x78467 0x0 +Total 0xa82ad0 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 212260 + 209340 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 50420 + 50568 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205B_REGION_US_LR_size.txt index f79bda2ac3..90feed4c9d 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205B_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x335dc 0x8006000 -_cc_handlers_v3 0x1b0 0x80395dc -_zw_protocol_cmd_handlers 0x70 0x803978c -_zw_protocol_cmd_handlers_lr 0x30 0x80397fc -.ARM.exidx 0x8 0x803982c -.copy.table 0xc 0x8039834 -.zero.table 0x0 0x8039840 +.text 0x32a68 0x8006000 +_cc_handlers_v3 0x1b0 0x8038a68 +_zw_protocol_cmd_handlers 0x70 0x8038c18 +_zw_protocol_cmd_handlers_lr 0x30 0x8038c88 +.ARM.exidx 0x8 0x8038cb8 +.copy.table 0xc 0x8038cc0 +.zero.table 0x0 0x8038ccc .stack 0x1000 0x20000000 -.data 0x4e4 0x20001000 -.bss 0xa810 0x200014e4 -.heap 0x4308 0x2000bcf8 -.internal_storage 0x2a000 0x8039840 -.zwave_nvm 0x6000 0x8063840 -.nvm 0xa000 0x8069840 +.data 0x4f0 0x20001000 +.bss 0xa898 0x200014f0 +.heap 0x4278 0x2000bd88 +.internal_storage 0x2c000 0x8038ccc +.zwave_nvm 0x6000 0x8064ccc +.nvm 0x8000 0x806accc .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9c70 0x0 -.debug_info 0x8e3304 0x0 -.debug_abbrev 0x14e1d 0x0 -.debug_loc 0x43747 0x0 -.debug_aranges 0x3630 0x0 -.debug_ranges 0x6ad0 0x0 -.debug_line 0x3f59c 0x0 -.debug_str 0x78411 0x0 -Total 0xa84840 +.debug_frame 0x9bfc 0x0 +.debug_info 0x8e2e78 0x0 +.debug_abbrev 0x14c1c 0x0 +.debug_loc 0x432d6 0x0 +.debug_aranges 0x35f8 0x0 +.debug_ranges 0x6988 0x0 +.debug_line 0x3f038 0x0 +.debug_str 0x78467 0x0 +Total 0xa82ad0 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 212260 + 209340 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 50420 + 50568 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205B_REGION_US_size.txt index f79bda2ac3..90feed4c9d 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4205B_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x335dc 0x8006000 -_cc_handlers_v3 0x1b0 0x80395dc -_zw_protocol_cmd_handlers 0x70 0x803978c -_zw_protocol_cmd_handlers_lr 0x30 0x80397fc -.ARM.exidx 0x8 0x803982c -.copy.table 0xc 0x8039834 -.zero.table 0x0 0x8039840 +.text 0x32a68 0x8006000 +_cc_handlers_v3 0x1b0 0x8038a68 +_zw_protocol_cmd_handlers 0x70 0x8038c18 +_zw_protocol_cmd_handlers_lr 0x30 0x8038c88 +.ARM.exidx 0x8 0x8038cb8 +.copy.table 0xc 0x8038cc0 +.zero.table 0x0 0x8038ccc .stack 0x1000 0x20000000 -.data 0x4e4 0x20001000 -.bss 0xa810 0x200014e4 -.heap 0x4308 0x2000bcf8 -.internal_storage 0x2a000 0x8039840 -.zwave_nvm 0x6000 0x8063840 -.nvm 0xa000 0x8069840 +.data 0x4f0 0x20001000 +.bss 0xa898 0x200014f0 +.heap 0x4278 0x2000bd88 +.internal_storage 0x2c000 0x8038ccc +.zwave_nvm 0x6000 0x8064ccc +.nvm 0x8000 0x806accc .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9c70 0x0 -.debug_info 0x8e3304 0x0 -.debug_abbrev 0x14e1d 0x0 -.debug_loc 0x43747 0x0 -.debug_aranges 0x3630 0x0 -.debug_ranges 0x6ad0 0x0 -.debug_line 0x3f59c 0x0 -.debug_str 0x78411 0x0 -Total 0xa84840 +.debug_frame 0x9bfc 0x0 +.debug_info 0x8e2e78 0x0 +.debug_abbrev 0x14c1c 0x0 +.debug_loc 0x432d6 0x0 +.debug_aranges 0x35f8 0x0 +.debug_ranges 0x6988 0x0 +.debug_line 0x3f038 0x0 +.debug_str 0x78467 0x0 +Total 0xa82ad0 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 212260 + 209340 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 50420 + 50568 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4207A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4207A_REGION_EU_size.txt index 586bb51a70..3e092a0f10 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4207A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4207A_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x2b580 0x0 -_cc_handlers_v3 0x1b0 0x2b580 -_zw_protocol_cmd_handlers 0x70 0x2b730 -_zw_protocol_cmd_handlers_lr 0x30 0x2b7a0 -.ARM.exidx 0x8 0x2b7d0 -.copy.table 0xc 0x2b7d8 -.zero.table 0x0 0x2b7e4 +.text 0x2b6dc 0x0 +_cc_handlers_v3 0x1b0 0x2b6dc +_zw_protocol_cmd_handlers 0x70 0x2b88c +_zw_protocol_cmd_handlers_lr 0x30 0x2b8fc +.ARM.exidx 0x8 0x2b92c +.copy.table 0xc 0x2b934 +.zero.table 0x0 0x2b940 .stack 0x1000 0x20000000 -.data 0x3e8 0x20001000 -.bss 0x996c 0x200013e8 -.heap 0x52a8 0x2000ad58 -.internal_storage 0x3a000 0x2b7e4 -.zwave_nvm 0x3000 0x657e4 -.nvm 0x9000 0x687e4 +.data 0x3f4 0x20001000 +.bss 0x99f4 0x200013f4 +.heap 0x5218 0x2000ade8 +.internal_storage 0x3a000 0x2b940 +.zwave_nvm 0x3000 0x65940 +.nvm 0x9000 0x68940 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x673c 0x0 -.debug_info 0x89b829 0x0 -.debug_abbrev 0xf41c 0x0 -.debug_loc 0x24f71 0x0 +.debug_frame 0x6748 0x0 +.debug_info 0x89bd20 0x0 +.debug_abbrev 0xf499 0x0 +.debug_loc 0x24f96 0x0 .debug_aranges 0x26c0 0x0 -.debug_ranges 0x4ac0 0x0 -.debug_line 0x29597 0x0 -.debug_str 0x6bfce 0x0 -Total 0x9f422e +.debug_ranges 0x4aa8 0x0 +.debug_line 0x295bb 0x0 +.debug_str 0x6c100 0x0 +Total 0x9f4a71 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 179148 + 179508 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 46420 + 46568 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4207A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4207A_REGION_US_LR_size.txt index 586bb51a70..3e092a0f10 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4207A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4207A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x2b580 0x0 -_cc_handlers_v3 0x1b0 0x2b580 -_zw_protocol_cmd_handlers 0x70 0x2b730 -_zw_protocol_cmd_handlers_lr 0x30 0x2b7a0 -.ARM.exidx 0x8 0x2b7d0 -.copy.table 0xc 0x2b7d8 -.zero.table 0x0 0x2b7e4 +.text 0x2b6dc 0x0 +_cc_handlers_v3 0x1b0 0x2b6dc +_zw_protocol_cmd_handlers 0x70 0x2b88c +_zw_protocol_cmd_handlers_lr 0x30 0x2b8fc +.ARM.exidx 0x8 0x2b92c +.copy.table 0xc 0x2b934 +.zero.table 0x0 0x2b940 .stack 0x1000 0x20000000 -.data 0x3e8 0x20001000 -.bss 0x996c 0x200013e8 -.heap 0x52a8 0x2000ad58 -.internal_storage 0x3a000 0x2b7e4 -.zwave_nvm 0x3000 0x657e4 -.nvm 0x9000 0x687e4 +.data 0x3f4 0x20001000 +.bss 0x99f4 0x200013f4 +.heap 0x5218 0x2000ade8 +.internal_storage 0x3a000 0x2b940 +.zwave_nvm 0x3000 0x65940 +.nvm 0x9000 0x68940 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x673c 0x0 -.debug_info 0x89b829 0x0 -.debug_abbrev 0xf41c 0x0 -.debug_loc 0x24f71 0x0 +.debug_frame 0x6748 0x0 +.debug_info 0x89bd20 0x0 +.debug_abbrev 0xf499 0x0 +.debug_loc 0x24f96 0x0 .debug_aranges 0x26c0 0x0 -.debug_ranges 0x4ac0 0x0 -.debug_line 0x29597 0x0 -.debug_str 0x6bfce 0x0 -Total 0x9f422e +.debug_ranges 0x4aa8 0x0 +.debug_line 0x295bb 0x0 +.debug_str 0x6c100 0x0 +Total 0x9f4a71 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 179148 + 179508 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 46420 + 46568 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4207A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4207A_REGION_US_size.txt index 586bb51a70..3e092a0f10 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4207A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4207A_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x2b580 0x0 -_cc_handlers_v3 0x1b0 0x2b580 -_zw_protocol_cmd_handlers 0x70 0x2b730 -_zw_protocol_cmd_handlers_lr 0x30 0x2b7a0 -.ARM.exidx 0x8 0x2b7d0 -.copy.table 0xc 0x2b7d8 -.zero.table 0x0 0x2b7e4 +.text 0x2b6dc 0x0 +_cc_handlers_v3 0x1b0 0x2b6dc +_zw_protocol_cmd_handlers 0x70 0x2b88c +_zw_protocol_cmd_handlers_lr 0x30 0x2b8fc +.ARM.exidx 0x8 0x2b92c +.copy.table 0xc 0x2b934 +.zero.table 0x0 0x2b940 .stack 0x1000 0x20000000 -.data 0x3e8 0x20001000 -.bss 0x996c 0x200013e8 -.heap 0x52a8 0x2000ad58 -.internal_storage 0x3a000 0x2b7e4 -.zwave_nvm 0x3000 0x657e4 -.nvm 0x9000 0x687e4 +.data 0x3f4 0x20001000 +.bss 0x99f4 0x200013f4 +.heap 0x5218 0x2000ade8 +.internal_storage 0x3a000 0x2b940 +.zwave_nvm 0x3000 0x65940 +.nvm 0x9000 0x68940 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x673c 0x0 -.debug_info 0x89b829 0x0 -.debug_abbrev 0xf41c 0x0 -.debug_loc 0x24f71 0x0 +.debug_frame 0x6748 0x0 +.debug_info 0x89bd20 0x0 +.debug_abbrev 0xf499 0x0 +.debug_loc 0x24f96 0x0 .debug_aranges 0x26c0 0x0 -.debug_ranges 0x4ac0 0x0 -.debug_line 0x29597 0x0 -.debug_str 0x6bfce 0x0 -Total 0x9f422e +.debug_ranges 0x4aa8 0x0 +.debug_line 0x295bb 0x0 +.debug_str 0x6c100 0x0 +Total 0x9f4a71 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 179148 + 179508 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 46420 + 46568 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4209A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4209A_REGION_US_LR_size.txt index 3ca3efc76e..391e8e1128 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4209A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4209A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x2b544 0x0 -_cc_handlers_v3 0x1b0 0x2b544 -_zw_protocol_cmd_handlers 0x70 0x2b6f4 -_zw_protocol_cmd_handlers_lr 0x30 0x2b764 -.ARM.exidx 0x8 0x2b794 -.copy.table 0xc 0x2b79c -.zero.table 0x0 0x2b7a8 +.text 0x2b660 0x0 +_cc_handlers_v3 0x1b0 0x2b660 +_zw_protocol_cmd_handlers 0x70 0x2b810 +_zw_protocol_cmd_handlers_lr 0x30 0x2b880 +.ARM.exidx 0x8 0x2b8b0 +.copy.table 0xc 0x2b8b8 +.zero.table 0x0 0x2b8c4 .stack 0x1000 0x20000000 -.data 0x3e4 0x20001000 -.bss 0x9958 0x200013e4 -.heap 0x52c0 0x2000ad40 -.internal_storage 0x3a000 0x2b7a8 -.zwave_nvm 0x3000 0x657a8 -.nvm 0x9000 0x687a8 +.data 0x3f0 0x20001000 +.bss 0x99d0 0x200013f0 +.heap 0x5240 0x2000adc0 +.internal_storage 0x3a000 0x2b8c4 +.zwave_nvm 0x3000 0x658c4 +.nvm 0x9000 0x688c4 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x696c 0x0 -.debug_info 0x89d0fc 0x0 -.debug_abbrev 0xf986 0x0 -.debug_loc 0x25a80 0x0 +.debug_frame 0x6978 0x0 +.debug_info 0x89d5f3 0x0 +.debug_abbrev 0xfa03 0x0 +.debug_loc 0x25aa5 0x0 .debug_aranges 0x27a0 0x0 -.debug_ranges 0x4ca8 0x0 -.debug_line 0x2a5d8 0x0 -.debug_str 0x6c3c4 0x0 -Total 0x9f846d +.debug_ranges 0x4c90 0x0 +.debug_line 0x2a5fc 0x0 +.debug_str 0x6c4f7 0x0 +Total 0x9f8c71 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 179084 + 179380 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 46396 + 46528 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4210A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4210A_REGION_US_LR_size.txt index 3993b8a310..83895c4fc1 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4210A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_ncp_zniffer_pti_BRD4210A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_ncp_zniffer_pti.out : section size addr -.text 0x33154 0x8006000 -_cc_handlers_v3 0x1b0 0x8039154 -_zw_protocol_cmd_handlers 0x70 0x8039304 -_zw_protocol_cmd_handlers_lr 0x30 0x8039374 -.ARM.exidx 0x8 0x80393a4 -.copy.table 0xc 0x80393ac -.zero.table 0x0 0x80393b8 +.text 0x325e0 0x8006000 +_cc_handlers_v3 0x1b0 0x80385e0 +_zw_protocol_cmd_handlers 0x70 0x8038790 +_zw_protocol_cmd_handlers_lr 0x30 0x8038800 +.ARM.exidx 0x8 0x8038830 +.copy.table 0xc 0x8038838 +.zero.table 0x0 0x8038844 .stack 0x1000 0x20000000 -.data 0x4e8 0x20001000 -.bss 0xa7f4 0x200014e8 -.heap 0x4320 0x2000bce0 -.internal_storage 0x2a000 0x80393b8 -.zwave_nvm 0x6000 0x80633b8 -.nvm 0xa000 0x80693b8 +.data 0x4f4 0x20001000 +.bss 0xa874 0x200014f4 +.heap 0x4298 0x2000bd68 +.internal_storage 0x2c000 0x8038844 +.zwave_nvm 0x6000 0x8064844 +.nvm 0x8000 0x806a844 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9ca0 0x0 -.debug_info 0x8e2aec 0x0 -.debug_abbrev 0x14dc4 0x0 -.debug_loc 0x4375a 0x0 -.debug_aranges 0x3620 0x0 -.debug_ranges 0x6ae0 0x0 -.debug_line 0x3f758 0x0 -.debug_str 0x77d37 0x0 -Total 0xa8366c +.debug_frame 0x9c2c 0x0 +.debug_info 0x8e2660 0x0 +.debug_abbrev 0x14bc3 0x0 +.debug_loc 0x432e6 0x0 +.debug_aranges 0x35e8 0x0 +.debug_ranges 0x6998 0x0 +.debug_line 0x3f1f4 0x0 +.debug_str 0x77d8e 0x0 +Total 0xa818fa The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 211104 + 208184 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 50396 + 50536 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4202A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4202A_REGION_EU_size.txt index 5c7226ac02..ff0d20139b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4202A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4202A_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x2e4dc 0x0 -_cc_handlers_v3 0x240 0x2e4dc -_zw_protocol_cmd_handlers 0x70 0x2e71c -_zw_protocol_cmd_handlers_lr 0x30 0x2e78c -.ARM.exidx 0x8 0x2e7bc -.copy.table 0xc 0x2e7c4 -.zero.table 0x0 0x2e7d0 +.text 0x2e638 0x0 +_cc_handlers_v3 0x240 0x2e638 +_zw_protocol_cmd_handlers 0x70 0x2e878 +_zw_protocol_cmd_handlers_lr 0x30 0x2e8e8 +.ARM.exidx 0x8 0x2e918 +.copy.table 0xc 0x2e920 +.zero.table 0x0 0x2e92c .stack 0x1000 0x20000000 -.data 0x3f4 0x20001000 -.bss 0x9e40 0x200013f4 -.heap 0x4dc8 0x2000b238 -.internal_storage 0x3a000 0x2e7d0 -.zwave_nvm 0x3000 0x687d0 -.nvm 0x9000 0x6b7d0 +.data 0x3fc 0x20001000 +.bss 0x9ec8 0x200013fc +.heap 0x4d38 0x2000b2c8 +.internal_storage 0x3a000 0x2e92c +.zwave_nvm 0x3000 0x6892c +.nvm 0x9000 0x6b92c .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6ec0 0x0 -.debug_info 0xa3af8c 0x0 -.debug_abbrev 0x10eac 0x0 -.debug_loc 0x276f4 0x0 +.debug_frame 0x6ecc 0x0 +.debug_info 0xa3b5aa 0x0 +.debug_abbrev 0x10f0f 0x0 +.debug_loc 0x2771c 0x0 .debug_aranges 0x29b0 0x0 -.debug_ranges 0x5060 0x0 -.debug_line 0x2d347 0x0 -.debug_str 0x6f96c 0x0 -Total 0xba32f2 +.debug_ranges 0x5048 0x0 +.debug_line 0x2d3a1 0x0 +.debug_str 0x6fa9e 0x0 +Total 0xba3c77 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 191428 + 191784 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47668 + 47812 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4202A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4202A_REGION_US_LR_size.txt index 5c7226ac02..ff0d20139b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4202A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4202A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x2e4dc 0x0 -_cc_handlers_v3 0x240 0x2e4dc -_zw_protocol_cmd_handlers 0x70 0x2e71c -_zw_protocol_cmd_handlers_lr 0x30 0x2e78c -.ARM.exidx 0x8 0x2e7bc -.copy.table 0xc 0x2e7c4 -.zero.table 0x0 0x2e7d0 +.text 0x2e638 0x0 +_cc_handlers_v3 0x240 0x2e638 +_zw_protocol_cmd_handlers 0x70 0x2e878 +_zw_protocol_cmd_handlers_lr 0x30 0x2e8e8 +.ARM.exidx 0x8 0x2e918 +.copy.table 0xc 0x2e920 +.zero.table 0x0 0x2e92c .stack 0x1000 0x20000000 -.data 0x3f4 0x20001000 -.bss 0x9e40 0x200013f4 -.heap 0x4dc8 0x2000b238 -.internal_storage 0x3a000 0x2e7d0 -.zwave_nvm 0x3000 0x687d0 -.nvm 0x9000 0x6b7d0 +.data 0x3fc 0x20001000 +.bss 0x9ec8 0x200013fc +.heap 0x4d38 0x2000b2c8 +.internal_storage 0x3a000 0x2e92c +.zwave_nvm 0x3000 0x6892c +.nvm 0x9000 0x6b92c .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6ec0 0x0 -.debug_info 0xa3af8c 0x0 -.debug_abbrev 0x10eac 0x0 -.debug_loc 0x276f4 0x0 +.debug_frame 0x6ecc 0x0 +.debug_info 0xa3b5aa 0x0 +.debug_abbrev 0x10f0f 0x0 +.debug_loc 0x2771c 0x0 .debug_aranges 0x29b0 0x0 -.debug_ranges 0x5060 0x0 -.debug_line 0x2d347 0x0 -.debug_str 0x6f96c 0x0 -Total 0xba32f2 +.debug_ranges 0x5048 0x0 +.debug_line 0x2d3a1 0x0 +.debug_str 0x6fa9e 0x0 +Total 0xba3c77 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 191428 + 191784 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47668 + 47812 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4202A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4202A_REGION_US_size.txt index 5c7226ac02..ff0d20139b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4202A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4202A_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x2e4dc 0x0 -_cc_handlers_v3 0x240 0x2e4dc -_zw_protocol_cmd_handlers 0x70 0x2e71c -_zw_protocol_cmd_handlers_lr 0x30 0x2e78c -.ARM.exidx 0x8 0x2e7bc -.copy.table 0xc 0x2e7c4 -.zero.table 0x0 0x2e7d0 +.text 0x2e638 0x0 +_cc_handlers_v3 0x240 0x2e638 +_zw_protocol_cmd_handlers 0x70 0x2e878 +_zw_protocol_cmd_handlers_lr 0x30 0x2e8e8 +.ARM.exidx 0x8 0x2e918 +.copy.table 0xc 0x2e920 +.zero.table 0x0 0x2e92c .stack 0x1000 0x20000000 -.data 0x3f4 0x20001000 -.bss 0x9e40 0x200013f4 -.heap 0x4dc8 0x2000b238 -.internal_storage 0x3a000 0x2e7d0 -.zwave_nvm 0x3000 0x687d0 -.nvm 0x9000 0x6b7d0 +.data 0x3fc 0x20001000 +.bss 0x9ec8 0x200013fc +.heap 0x4d38 0x2000b2c8 +.internal_storage 0x3a000 0x2e92c +.zwave_nvm 0x3000 0x6892c +.nvm 0x9000 0x6b92c .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6ec0 0x0 -.debug_info 0xa3af8c 0x0 -.debug_abbrev 0x10eac 0x0 -.debug_loc 0x276f4 0x0 +.debug_frame 0x6ecc 0x0 +.debug_info 0xa3b5aa 0x0 +.debug_abbrev 0x10f0f 0x0 +.debug_loc 0x2771c 0x0 .debug_aranges 0x29b0 0x0 -.debug_ranges 0x5060 0x0 -.debug_line 0x2d347 0x0 -.debug_str 0x6f96c 0x0 -Total 0xba32f2 +.debug_ranges 0x5048 0x0 +.debug_line 0x2d3a1 0x0 +.debug_str 0x6fa9e 0x0 +Total 0xba3c77 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 191428 + 191784 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47668 + 47812 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204C_REGION_EU_size.txt index c0a0a57674..439cc42ffe 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204C_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x36294 0x8006000 -_cc_handlers_v3 0x240 0x803c294 -_zw_protocol_cmd_handlers 0x70 0x803c4d4 -_zw_protocol_cmd_handlers_lr 0x30 0x803c544 -.ARM.exidx 0x8 0x803c574 -.copy.table 0xc 0x803c57c -.zero.table 0x0 0x803c588 +.text 0x35720 0x8006000 +_cc_handlers_v3 0x240 0x803b720 +_zw_protocol_cmd_handlers 0x70 0x803b960 +_zw_protocol_cmd_handlers_lr 0x30 0x803b9d0 +.ARM.exidx 0x8 0x803ba00 +.copy.table 0xc 0x803ba08 +.zero.table 0x0 0x803ba14 .stack 0x1000 0x20000000 -.data 0x54c 0x20001000 -.bss 0xad60 0x2000154c -.heap 0x3d50 0x2000c2b0 -.internal_storage 0x2a000 0x803c588 -.zwave_nvm 0x6000 0x8066588 -.nvm 0xa000 0x806c588 +.data 0x554 0x20001000 +.bss 0xade8 0x20001554 +.heap 0x3cc0 0x2000c340 +.internal_storage 0x2c000 0x803ba14 +.zwave_nvm 0x6000 0x8067a14 +.nvm 0x8000 0x806da14 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa4dc 0x0 -.debug_info 0xa829d4 0x0 -.debug_abbrev 0x16835 0x0 -.debug_loc 0x4637c 0x0 -.debug_aranges 0x3920 0x0 -.debug_ranges 0x7170 0x0 -.debug_line 0x43893 0x0 -.debug_str 0x7a976 0x0 -Total 0xc32cfd +.debug_frame 0xa468 0x0 +.debug_info 0xa82675 0x0 +.debug_abbrev 0x16625 0x0 +.debug_loc 0x45e8c 0x0 +.debug_aranges 0x38e8 0x0 +.debug_ranges 0x7008 0x0 +.debug_line 0x43369 0x0 +.debug_str 0x7a9cd 0x0 +Total 0xc31043 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 223956 + 221032 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51884 + 52028 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204C_REGION_US_LR_size.txt index c0a0a57674..439cc42ffe 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204C_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x36294 0x8006000 -_cc_handlers_v3 0x240 0x803c294 -_zw_protocol_cmd_handlers 0x70 0x803c4d4 -_zw_protocol_cmd_handlers_lr 0x30 0x803c544 -.ARM.exidx 0x8 0x803c574 -.copy.table 0xc 0x803c57c -.zero.table 0x0 0x803c588 +.text 0x35720 0x8006000 +_cc_handlers_v3 0x240 0x803b720 +_zw_protocol_cmd_handlers 0x70 0x803b960 +_zw_protocol_cmd_handlers_lr 0x30 0x803b9d0 +.ARM.exidx 0x8 0x803ba00 +.copy.table 0xc 0x803ba08 +.zero.table 0x0 0x803ba14 .stack 0x1000 0x20000000 -.data 0x54c 0x20001000 -.bss 0xad60 0x2000154c -.heap 0x3d50 0x2000c2b0 -.internal_storage 0x2a000 0x803c588 -.zwave_nvm 0x6000 0x8066588 -.nvm 0xa000 0x806c588 +.data 0x554 0x20001000 +.bss 0xade8 0x20001554 +.heap 0x3cc0 0x2000c340 +.internal_storage 0x2c000 0x803ba14 +.zwave_nvm 0x6000 0x8067a14 +.nvm 0x8000 0x806da14 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa4dc 0x0 -.debug_info 0xa829d4 0x0 -.debug_abbrev 0x16835 0x0 -.debug_loc 0x4637c 0x0 -.debug_aranges 0x3920 0x0 -.debug_ranges 0x7170 0x0 -.debug_line 0x43893 0x0 -.debug_str 0x7a976 0x0 -Total 0xc32cfd +.debug_frame 0xa468 0x0 +.debug_info 0xa82675 0x0 +.debug_abbrev 0x16625 0x0 +.debug_loc 0x45e8c 0x0 +.debug_aranges 0x38e8 0x0 +.debug_ranges 0x7008 0x0 +.debug_line 0x43369 0x0 +.debug_str 0x7a9cd 0x0 +Total 0xc31043 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 223956 + 221032 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51884 + 52028 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204C_REGION_US_size.txt index c0a0a57674..439cc42ffe 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204C_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x36294 0x8006000 -_cc_handlers_v3 0x240 0x803c294 -_zw_protocol_cmd_handlers 0x70 0x803c4d4 -_zw_protocol_cmd_handlers_lr 0x30 0x803c544 -.ARM.exidx 0x8 0x803c574 -.copy.table 0xc 0x803c57c -.zero.table 0x0 0x803c588 +.text 0x35720 0x8006000 +_cc_handlers_v3 0x240 0x803b720 +_zw_protocol_cmd_handlers 0x70 0x803b960 +_zw_protocol_cmd_handlers_lr 0x30 0x803b9d0 +.ARM.exidx 0x8 0x803ba00 +.copy.table 0xc 0x803ba08 +.zero.table 0x0 0x803ba14 .stack 0x1000 0x20000000 -.data 0x54c 0x20001000 -.bss 0xad60 0x2000154c -.heap 0x3d50 0x2000c2b0 -.internal_storage 0x2a000 0x803c588 -.zwave_nvm 0x6000 0x8066588 -.nvm 0xa000 0x806c588 +.data 0x554 0x20001000 +.bss 0xade8 0x20001554 +.heap 0x3cc0 0x2000c340 +.internal_storage 0x2c000 0x803ba14 +.zwave_nvm 0x6000 0x8067a14 +.nvm 0x8000 0x806da14 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa4dc 0x0 -.debug_info 0xa829d4 0x0 -.debug_abbrev 0x16835 0x0 -.debug_loc 0x4637c 0x0 -.debug_aranges 0x3920 0x0 -.debug_ranges 0x7170 0x0 -.debug_line 0x43893 0x0 -.debug_str 0x7a976 0x0 -Total 0xc32cfd +.debug_frame 0xa468 0x0 +.debug_info 0xa82675 0x0 +.debug_abbrev 0x16625 0x0 +.debug_loc 0x45e8c 0x0 +.debug_aranges 0x38e8 0x0 +.debug_ranges 0x7008 0x0 +.debug_line 0x43369 0x0 +.debug_str 0x7a9cd 0x0 +Total 0xc31043 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 223956 + 221032 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51884 + 52028 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204D_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204D_REGION_EU_size.txt index 717217ff06..5d2a7e5803 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204D_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204D_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x36360 0x8006000 -_cc_handlers_v3 0x240 0x803c360 -_zw_protocol_cmd_handlers 0x70 0x803c5a0 -_zw_protocol_cmd_handlers_lr 0x30 0x803c610 -.ARM.exidx 0x8 0x803c640 -.copy.table 0xc 0x803c648 -.zero.table 0x0 0x803c654 +.text 0x357e4 0x8006000 +_cc_handlers_v3 0x240 0x803b7e4 +_zw_protocol_cmd_handlers 0x70 0x803ba24 +_zw_protocol_cmd_handlers_lr 0x30 0x803ba94 +.ARM.exidx 0x8 0x803bac4 +.copy.table 0xc 0x803bacc +.zero.table 0x0 0x803bad8 .stack 0x1000 0x20000000 -.data 0x550 0x20001000 -.bss 0xad64 0x20001550 -.heap 0x3d48 0x2000c2b8 -.internal_storage 0x2a000 0x803c654 -.zwave_nvm 0x6000 0x8066654 -.nvm 0xa000 0x806c654 +.data 0x558 0x20001000 +.bss 0xadec 0x20001558 +.heap 0x3cb8 0x2000c348 +.internal_storage 0x2c000 0x803bad8 +.zwave_nvm 0x6000 0x8067ad8 +.nvm 0x8000 0x806dad8 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa50c 0x0 -.debug_info 0xa82c37 0x0 -.debug_abbrev 0x16921 0x0 -.debug_loc 0x4637c 0x0 -.debug_aranges 0x3940 0x0 -.debug_ranges 0x7180 0x0 -.debug_line 0x43a79 0x0 -.debug_str 0x7ab49 0x0 -Total 0xc33531 +.debug_frame 0xa498 0x0 +.debug_info 0xa828d8 0x0 +.debug_abbrev 0x16711 0x0 +.debug_loc 0x45e8c 0x0 +.debug_aranges 0x3908 0x0 +.debug_ranges 0x7018 0x0 +.debug_line 0x4354f 0x0 +.debug_str 0x7aba0 0x0 +Total 0xc3186f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 224164 + 221232 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51892 + 52036 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204D_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204D_REGION_US_LR_size.txt index 717217ff06..5d2a7e5803 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204D_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204D_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x36360 0x8006000 -_cc_handlers_v3 0x240 0x803c360 -_zw_protocol_cmd_handlers 0x70 0x803c5a0 -_zw_protocol_cmd_handlers_lr 0x30 0x803c610 -.ARM.exidx 0x8 0x803c640 -.copy.table 0xc 0x803c648 -.zero.table 0x0 0x803c654 +.text 0x357e4 0x8006000 +_cc_handlers_v3 0x240 0x803b7e4 +_zw_protocol_cmd_handlers 0x70 0x803ba24 +_zw_protocol_cmd_handlers_lr 0x30 0x803ba94 +.ARM.exidx 0x8 0x803bac4 +.copy.table 0xc 0x803bacc +.zero.table 0x0 0x803bad8 .stack 0x1000 0x20000000 -.data 0x550 0x20001000 -.bss 0xad64 0x20001550 -.heap 0x3d48 0x2000c2b8 -.internal_storage 0x2a000 0x803c654 -.zwave_nvm 0x6000 0x8066654 -.nvm 0xa000 0x806c654 +.data 0x558 0x20001000 +.bss 0xadec 0x20001558 +.heap 0x3cb8 0x2000c348 +.internal_storage 0x2c000 0x803bad8 +.zwave_nvm 0x6000 0x8067ad8 +.nvm 0x8000 0x806dad8 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa50c 0x0 -.debug_info 0xa82c37 0x0 -.debug_abbrev 0x16921 0x0 -.debug_loc 0x4637c 0x0 -.debug_aranges 0x3940 0x0 -.debug_ranges 0x7180 0x0 -.debug_line 0x43a79 0x0 -.debug_str 0x7ab49 0x0 -Total 0xc33531 +.debug_frame 0xa498 0x0 +.debug_info 0xa828d8 0x0 +.debug_abbrev 0x16711 0x0 +.debug_loc 0x45e8c 0x0 +.debug_aranges 0x3908 0x0 +.debug_ranges 0x7018 0x0 +.debug_line 0x4354f 0x0 +.debug_str 0x7aba0 0x0 +Total 0xc3186f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 224164 + 221232 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51892 + 52036 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204D_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204D_REGION_US_size.txt index 717217ff06..5d2a7e5803 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204D_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4204D_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x36360 0x8006000 -_cc_handlers_v3 0x240 0x803c360 -_zw_protocol_cmd_handlers 0x70 0x803c5a0 -_zw_protocol_cmd_handlers_lr 0x30 0x803c610 -.ARM.exidx 0x8 0x803c640 -.copy.table 0xc 0x803c648 -.zero.table 0x0 0x803c654 +.text 0x357e4 0x8006000 +_cc_handlers_v3 0x240 0x803b7e4 +_zw_protocol_cmd_handlers 0x70 0x803ba24 +_zw_protocol_cmd_handlers_lr 0x30 0x803ba94 +.ARM.exidx 0x8 0x803bac4 +.copy.table 0xc 0x803bacc +.zero.table 0x0 0x803bad8 .stack 0x1000 0x20000000 -.data 0x550 0x20001000 -.bss 0xad64 0x20001550 -.heap 0x3d48 0x2000c2b8 -.internal_storage 0x2a000 0x803c654 -.zwave_nvm 0x6000 0x8066654 -.nvm 0xa000 0x806c654 +.data 0x558 0x20001000 +.bss 0xadec 0x20001558 +.heap 0x3cb8 0x2000c348 +.internal_storage 0x2c000 0x803bad8 +.zwave_nvm 0x6000 0x8067ad8 +.nvm 0x8000 0x806dad8 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa50c 0x0 -.debug_info 0xa82c37 0x0 -.debug_abbrev 0x16921 0x0 -.debug_loc 0x4637c 0x0 -.debug_aranges 0x3940 0x0 -.debug_ranges 0x7180 0x0 -.debug_line 0x43a79 0x0 -.debug_str 0x7ab49 0x0 -Total 0xc33531 +.debug_frame 0xa498 0x0 +.debug_info 0xa828d8 0x0 +.debug_abbrev 0x16711 0x0 +.debug_loc 0x45e8c 0x0 +.debug_aranges 0x3908 0x0 +.debug_ranges 0x7018 0x0 +.debug_line 0x4354f 0x0 +.debug_str 0x7aba0 0x0 +Total 0xc3186f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 224164 + 221232 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51892 + 52036 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205A_REGION_EU_size.txt index 419a4c73e3..f589516799 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205A_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x364a0 0x8006000 -_cc_handlers_v3 0x240 0x803c4a0 -_zw_protocol_cmd_handlers 0x70 0x803c6e0 -_zw_protocol_cmd_handlers_lr 0x30 0x803c750 -.ARM.exidx 0x8 0x803c780 -.copy.table 0xc 0x803c788 -.zero.table 0x0 0x803c794 +.text 0x356b4 0x8006000 +_cc_handlers_v3 0x240 0x803b6b4 +_zw_protocol_cmd_handlers 0x70 0x803b8f4 +_zw_protocol_cmd_handlers_lr 0x30 0x803b964 +.ARM.exidx 0x8 0x803b994 +.copy.table 0xc 0x803b99c +.zero.table 0x0 0x803b9a8 .stack 0x1000 0x20000000 -.data 0x54c 0x20001000 -.bss 0xac50 0x2000154c -.heap 0x3e60 0x2000c1a0 -.internal_storage 0x2a000 0x803c794 -.zwave_nvm 0x6000 0x8066794 -.nvm 0xa000 0x806c794 +.data 0x554 0x20001000 +.bss 0xacd0 0x20001554 +.heap 0x3dd8 0x2000c228 +.internal_storage 0x2c000 0x803b9a8 +.zwave_nvm 0x6000 0x80679a8 +.nvm 0x8000 0x806d9a8 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa2cc 0x0 -.debug_info 0xa81227 0x0 -.debug_abbrev 0x16c31 0x0 -.debug_loc 0x4463e 0x0 -.debug_aranges 0x3920 0x0 -.debug_ranges 0x7050 0x0 -.debug_line 0x426fd 0x0 -.debug_str 0x7aec8 0x0 -Total 0xc2eea6 +.debug_frame 0x9ed0 0x0 +.debug_info 0xa7eabe 0x0 +.debug_abbrev 0x16395 0x0 +.debug_loc 0x417de 0x0 +.debug_aranges 0x3808 0x0 +.debug_ranges 0x6dd8 0x0 +.debug_line 0x41005 0x0 +.debug_str 0x7a973 0x0 +Total 0xc25e7c The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 224480 + 220924 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51612 + 51748 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205A_REGION_US_LR_size.txt index 419a4c73e3..f589516799 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x364a0 0x8006000 -_cc_handlers_v3 0x240 0x803c4a0 -_zw_protocol_cmd_handlers 0x70 0x803c6e0 -_zw_protocol_cmd_handlers_lr 0x30 0x803c750 -.ARM.exidx 0x8 0x803c780 -.copy.table 0xc 0x803c788 -.zero.table 0x0 0x803c794 +.text 0x356b4 0x8006000 +_cc_handlers_v3 0x240 0x803b6b4 +_zw_protocol_cmd_handlers 0x70 0x803b8f4 +_zw_protocol_cmd_handlers_lr 0x30 0x803b964 +.ARM.exidx 0x8 0x803b994 +.copy.table 0xc 0x803b99c +.zero.table 0x0 0x803b9a8 .stack 0x1000 0x20000000 -.data 0x54c 0x20001000 -.bss 0xac50 0x2000154c -.heap 0x3e60 0x2000c1a0 -.internal_storage 0x2a000 0x803c794 -.zwave_nvm 0x6000 0x8066794 -.nvm 0xa000 0x806c794 +.data 0x554 0x20001000 +.bss 0xacd0 0x20001554 +.heap 0x3dd8 0x2000c228 +.internal_storage 0x2c000 0x803b9a8 +.zwave_nvm 0x6000 0x80679a8 +.nvm 0x8000 0x806d9a8 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa2cc 0x0 -.debug_info 0xa81227 0x0 -.debug_abbrev 0x16c31 0x0 -.debug_loc 0x4463e 0x0 -.debug_aranges 0x3920 0x0 -.debug_ranges 0x7050 0x0 -.debug_line 0x426fd 0x0 -.debug_str 0x7aec8 0x0 -Total 0xc2eea6 +.debug_frame 0x9ed0 0x0 +.debug_info 0xa7eabe 0x0 +.debug_abbrev 0x16395 0x0 +.debug_loc 0x417de 0x0 +.debug_aranges 0x3808 0x0 +.debug_ranges 0x6dd8 0x0 +.debug_line 0x41005 0x0 +.debug_str 0x7a973 0x0 +Total 0xc25e7c The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 224480 + 220924 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51612 + 51748 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205A_REGION_US_size.txt index 419a4c73e3..f589516799 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205A_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x364a0 0x8006000 -_cc_handlers_v3 0x240 0x803c4a0 -_zw_protocol_cmd_handlers 0x70 0x803c6e0 -_zw_protocol_cmd_handlers_lr 0x30 0x803c750 -.ARM.exidx 0x8 0x803c780 -.copy.table 0xc 0x803c788 -.zero.table 0x0 0x803c794 +.text 0x356b4 0x8006000 +_cc_handlers_v3 0x240 0x803b6b4 +_zw_protocol_cmd_handlers 0x70 0x803b8f4 +_zw_protocol_cmd_handlers_lr 0x30 0x803b964 +.ARM.exidx 0x8 0x803b994 +.copy.table 0xc 0x803b99c +.zero.table 0x0 0x803b9a8 .stack 0x1000 0x20000000 -.data 0x54c 0x20001000 -.bss 0xac50 0x2000154c -.heap 0x3e60 0x2000c1a0 -.internal_storage 0x2a000 0x803c794 -.zwave_nvm 0x6000 0x8066794 -.nvm 0xa000 0x806c794 +.data 0x554 0x20001000 +.bss 0xacd0 0x20001554 +.heap 0x3dd8 0x2000c228 +.internal_storage 0x2c000 0x803b9a8 +.zwave_nvm 0x6000 0x80679a8 +.nvm 0x8000 0x806d9a8 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa2cc 0x0 -.debug_info 0xa81227 0x0 -.debug_abbrev 0x16c31 0x0 -.debug_loc 0x4463e 0x0 -.debug_aranges 0x3920 0x0 -.debug_ranges 0x7050 0x0 -.debug_line 0x426fd 0x0 -.debug_str 0x7aec8 0x0 -Total 0xc2eea6 +.debug_frame 0x9ed0 0x0 +.debug_info 0xa7eabe 0x0 +.debug_abbrev 0x16395 0x0 +.debug_loc 0x417de 0x0 +.debug_aranges 0x3808 0x0 +.debug_ranges 0x6dd8 0x0 +.debug_line 0x41005 0x0 +.debug_str 0x7a973 0x0 +Total 0xc25e7c The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 224480 + 220924 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51612 + 51748 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205B_REGION_EU_size.txt index 49385b9ca4..8f3dd7711c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205B_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x367f0 0x8006000 -_cc_handlers_v3 0x240 0x803c7f0 -_zw_protocol_cmd_handlers 0x70 0x803ca30 -_zw_protocol_cmd_handlers_lr 0x30 0x803caa0 -.ARM.exidx 0x8 0x803cad0 -.copy.table 0xc 0x803cad8 -.zero.table 0x0 0x803cae4 +.text 0x35c7c 0x8006000 +_cc_handlers_v3 0x240 0x803bc7c +_zw_protocol_cmd_handlers 0x70 0x803bebc +_zw_protocol_cmd_handlers_lr 0x30 0x803bf2c +.ARM.exidx 0x8 0x803bf5c +.copy.table 0xc 0x803bf64 +.zero.table 0x0 0x803bf70 .stack 0x1000 0x20000000 -.data 0x54c 0x20001000 -.bss 0xad80 0x2000154c -.heap 0x3d30 0x2000c2d0 -.internal_storage 0x2a000 0x803cae4 -.zwave_nvm 0x6000 0x8066ae4 -.nvm 0xa000 0x806cae4 +.data 0x554 0x20001000 +.bss 0xae08 0x20001554 +.heap 0x3ca0 0x2000c360 +.internal_storage 0x2c000 0x803bf70 +.zwave_nvm 0x6000 0x8067f70 +.nvm 0x8000 0x806df70 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa4dc 0x0 -.debug_info 0xa8344f 0x0 -.debug_abbrev 0x1697a 0x0 -.debug_loc 0x46369 0x0 -.debug_aranges 0x3950 0x0 -.debug_ranges 0x7170 0x0 -.debug_line 0x438a9 0x0 -.debug_str 0x7b21b 0x0 -Total 0xc346f1 +.debug_frame 0xa468 0x0 +.debug_info 0xa830f0 0x0 +.debug_abbrev 0x1676a 0x0 +.debug_loc 0x45e7c 0x0 +.debug_aranges 0x3918 0x0 +.debug_ranges 0x7008 0x0 +.debug_line 0x4337f 0x0 +.debug_str 0x7b271 0x0 +Total 0xc32a39 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225328 + 222404 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51916 + 52060 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205B_REGION_US_LR_size.txt index 49385b9ca4..8f3dd7711c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205B_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x367f0 0x8006000 -_cc_handlers_v3 0x240 0x803c7f0 -_zw_protocol_cmd_handlers 0x70 0x803ca30 -_zw_protocol_cmd_handlers_lr 0x30 0x803caa0 -.ARM.exidx 0x8 0x803cad0 -.copy.table 0xc 0x803cad8 -.zero.table 0x0 0x803cae4 +.text 0x35c7c 0x8006000 +_cc_handlers_v3 0x240 0x803bc7c +_zw_protocol_cmd_handlers 0x70 0x803bebc +_zw_protocol_cmd_handlers_lr 0x30 0x803bf2c +.ARM.exidx 0x8 0x803bf5c +.copy.table 0xc 0x803bf64 +.zero.table 0x0 0x803bf70 .stack 0x1000 0x20000000 -.data 0x54c 0x20001000 -.bss 0xad80 0x2000154c -.heap 0x3d30 0x2000c2d0 -.internal_storage 0x2a000 0x803cae4 -.zwave_nvm 0x6000 0x8066ae4 -.nvm 0xa000 0x806cae4 +.data 0x554 0x20001000 +.bss 0xae08 0x20001554 +.heap 0x3ca0 0x2000c360 +.internal_storage 0x2c000 0x803bf70 +.zwave_nvm 0x6000 0x8067f70 +.nvm 0x8000 0x806df70 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa4dc 0x0 -.debug_info 0xa8344f 0x0 -.debug_abbrev 0x1697a 0x0 -.debug_loc 0x46369 0x0 -.debug_aranges 0x3950 0x0 -.debug_ranges 0x7170 0x0 -.debug_line 0x438a9 0x0 -.debug_str 0x7b21b 0x0 -Total 0xc346f1 +.debug_frame 0xa468 0x0 +.debug_info 0xa830f0 0x0 +.debug_abbrev 0x1676a 0x0 +.debug_loc 0x45e7c 0x0 +.debug_aranges 0x3918 0x0 +.debug_ranges 0x7008 0x0 +.debug_line 0x4337f 0x0 +.debug_str 0x7b271 0x0 +Total 0xc32a39 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225328 + 222404 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51916 + 52060 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205B_REGION_US_size.txt index 49385b9ca4..8f3dd7711c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4205B_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x367f0 0x8006000 -_cc_handlers_v3 0x240 0x803c7f0 -_zw_protocol_cmd_handlers 0x70 0x803ca30 -_zw_protocol_cmd_handlers_lr 0x30 0x803caa0 -.ARM.exidx 0x8 0x803cad0 -.copy.table 0xc 0x803cad8 -.zero.table 0x0 0x803cae4 +.text 0x35c7c 0x8006000 +_cc_handlers_v3 0x240 0x803bc7c +_zw_protocol_cmd_handlers 0x70 0x803bebc +_zw_protocol_cmd_handlers_lr 0x30 0x803bf2c +.ARM.exidx 0x8 0x803bf5c +.copy.table 0xc 0x803bf64 +.zero.table 0x0 0x803bf70 .stack 0x1000 0x20000000 -.data 0x54c 0x20001000 -.bss 0xad80 0x2000154c -.heap 0x3d30 0x2000c2d0 -.internal_storage 0x2a000 0x803cae4 -.zwave_nvm 0x6000 0x8066ae4 -.nvm 0xa000 0x806cae4 +.data 0x554 0x20001000 +.bss 0xae08 0x20001554 +.heap 0x3ca0 0x2000c360 +.internal_storage 0x2c000 0x803bf70 +.zwave_nvm 0x6000 0x8067f70 +.nvm 0x8000 0x806df70 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa4dc 0x0 -.debug_info 0xa8344f 0x0 -.debug_abbrev 0x1697a 0x0 -.debug_loc 0x46369 0x0 -.debug_aranges 0x3950 0x0 -.debug_ranges 0x7170 0x0 -.debug_line 0x438a9 0x0 -.debug_str 0x7b21b 0x0 -Total 0xc346f1 +.debug_frame 0xa468 0x0 +.debug_info 0xa830f0 0x0 +.debug_abbrev 0x1676a 0x0 +.debug_loc 0x45e7c 0x0 +.debug_aranges 0x3918 0x0 +.debug_ranges 0x7008 0x0 +.debug_line 0x4337f 0x0 +.debug_str 0x7b271 0x0 +Total 0xc32a39 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225328 + 222404 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51916 + 52060 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4207A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4207A_REGION_EU_size.txt index 5c7226ac02..ff0d20139b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4207A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4207A_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x2e4dc 0x0 -_cc_handlers_v3 0x240 0x2e4dc -_zw_protocol_cmd_handlers 0x70 0x2e71c -_zw_protocol_cmd_handlers_lr 0x30 0x2e78c -.ARM.exidx 0x8 0x2e7bc -.copy.table 0xc 0x2e7c4 -.zero.table 0x0 0x2e7d0 +.text 0x2e638 0x0 +_cc_handlers_v3 0x240 0x2e638 +_zw_protocol_cmd_handlers 0x70 0x2e878 +_zw_protocol_cmd_handlers_lr 0x30 0x2e8e8 +.ARM.exidx 0x8 0x2e918 +.copy.table 0xc 0x2e920 +.zero.table 0x0 0x2e92c .stack 0x1000 0x20000000 -.data 0x3f4 0x20001000 -.bss 0x9e40 0x200013f4 -.heap 0x4dc8 0x2000b238 -.internal_storage 0x3a000 0x2e7d0 -.zwave_nvm 0x3000 0x687d0 -.nvm 0x9000 0x6b7d0 +.data 0x3fc 0x20001000 +.bss 0x9ec8 0x200013fc +.heap 0x4d38 0x2000b2c8 +.internal_storage 0x3a000 0x2e92c +.zwave_nvm 0x3000 0x6892c +.nvm 0x9000 0x6b92c .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6ec0 0x0 -.debug_info 0xa3af8c 0x0 -.debug_abbrev 0x10eac 0x0 -.debug_loc 0x276f4 0x0 +.debug_frame 0x6ecc 0x0 +.debug_info 0xa3b5aa 0x0 +.debug_abbrev 0x10f0f 0x0 +.debug_loc 0x2771c 0x0 .debug_aranges 0x29b0 0x0 -.debug_ranges 0x5060 0x0 -.debug_line 0x2d347 0x0 -.debug_str 0x6f96c 0x0 -Total 0xba32f2 +.debug_ranges 0x5048 0x0 +.debug_line 0x2d3a1 0x0 +.debug_str 0x6fa9e 0x0 +Total 0xba3c77 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 191428 + 191784 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47668 + 47812 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4207A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4207A_REGION_US_LR_size.txt index 5c7226ac02..ff0d20139b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4207A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4207A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x2e4dc 0x0 -_cc_handlers_v3 0x240 0x2e4dc -_zw_protocol_cmd_handlers 0x70 0x2e71c -_zw_protocol_cmd_handlers_lr 0x30 0x2e78c -.ARM.exidx 0x8 0x2e7bc -.copy.table 0xc 0x2e7c4 -.zero.table 0x0 0x2e7d0 +.text 0x2e638 0x0 +_cc_handlers_v3 0x240 0x2e638 +_zw_protocol_cmd_handlers 0x70 0x2e878 +_zw_protocol_cmd_handlers_lr 0x30 0x2e8e8 +.ARM.exidx 0x8 0x2e918 +.copy.table 0xc 0x2e920 +.zero.table 0x0 0x2e92c .stack 0x1000 0x20000000 -.data 0x3f4 0x20001000 -.bss 0x9e40 0x200013f4 -.heap 0x4dc8 0x2000b238 -.internal_storage 0x3a000 0x2e7d0 -.zwave_nvm 0x3000 0x687d0 -.nvm 0x9000 0x6b7d0 +.data 0x3fc 0x20001000 +.bss 0x9ec8 0x200013fc +.heap 0x4d38 0x2000b2c8 +.internal_storage 0x3a000 0x2e92c +.zwave_nvm 0x3000 0x6892c +.nvm 0x9000 0x6b92c .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6ec0 0x0 -.debug_info 0xa3af8c 0x0 -.debug_abbrev 0x10eac 0x0 -.debug_loc 0x276f4 0x0 +.debug_frame 0x6ecc 0x0 +.debug_info 0xa3b5aa 0x0 +.debug_abbrev 0x10f0f 0x0 +.debug_loc 0x2771c 0x0 .debug_aranges 0x29b0 0x0 -.debug_ranges 0x5060 0x0 -.debug_line 0x2d347 0x0 -.debug_str 0x6f96c 0x0 -Total 0xba32f2 +.debug_ranges 0x5048 0x0 +.debug_line 0x2d3a1 0x0 +.debug_str 0x6fa9e 0x0 +Total 0xba3c77 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 191428 + 191784 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47668 + 47812 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4207A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4207A_REGION_US_size.txt index 5c7226ac02..ff0d20139b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4207A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4207A_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x2e4dc 0x0 -_cc_handlers_v3 0x240 0x2e4dc -_zw_protocol_cmd_handlers 0x70 0x2e71c -_zw_protocol_cmd_handlers_lr 0x30 0x2e78c -.ARM.exidx 0x8 0x2e7bc -.copy.table 0xc 0x2e7c4 -.zero.table 0x0 0x2e7d0 +.text 0x2e638 0x0 +_cc_handlers_v3 0x240 0x2e638 +_zw_protocol_cmd_handlers 0x70 0x2e878 +_zw_protocol_cmd_handlers_lr 0x30 0x2e8e8 +.ARM.exidx 0x8 0x2e918 +.copy.table 0xc 0x2e920 +.zero.table 0x0 0x2e92c .stack 0x1000 0x20000000 -.data 0x3f4 0x20001000 -.bss 0x9e40 0x200013f4 -.heap 0x4dc8 0x2000b238 -.internal_storage 0x3a000 0x2e7d0 -.zwave_nvm 0x3000 0x687d0 -.nvm 0x9000 0x6b7d0 +.data 0x3fc 0x20001000 +.bss 0x9ec8 0x200013fc +.heap 0x4d38 0x2000b2c8 +.internal_storage 0x3a000 0x2e92c +.zwave_nvm 0x3000 0x6892c +.nvm 0x9000 0x6b92c .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6ec0 0x0 -.debug_info 0xa3af8c 0x0 -.debug_abbrev 0x10eac 0x0 -.debug_loc 0x276f4 0x0 +.debug_frame 0x6ecc 0x0 +.debug_info 0xa3b5aa 0x0 +.debug_abbrev 0x10f0f 0x0 +.debug_loc 0x2771c 0x0 .debug_aranges 0x29b0 0x0 -.debug_ranges 0x5060 0x0 -.debug_line 0x2d347 0x0 -.debug_str 0x6f96c 0x0 -Total 0xba32f2 +.debug_ranges 0x5048 0x0 +.debug_line 0x2d3a1 0x0 +.debug_str 0x6fa9e 0x0 +Total 0xba3c77 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 191428 + 191784 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47668 + 47812 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4209A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4209A_REGION_US_LR_size.txt index 9d159dc65f..11a29eff84 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4209A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4209A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x2e4a8 0x0 -_cc_handlers_v3 0x240 0x2e4a8 -_zw_protocol_cmd_handlers 0x70 0x2e6e8 -_zw_protocol_cmd_handlers_lr 0x30 0x2e758 -.ARM.exidx 0x8 0x2e788 -.copy.table 0xc 0x2e790 -.zero.table 0x0 0x2e79c +.text 0x2e5c4 0x0 +_cc_handlers_v3 0x240 0x2e5c4 +_zw_protocol_cmd_handlers 0x70 0x2e804 +_zw_protocol_cmd_handlers_lr 0x30 0x2e874 +.ARM.exidx 0x8 0x2e8a4 +.copy.table 0xc 0x2e8ac +.zero.table 0x0 0x2e8b8 .stack 0x1000 0x20000000 -.data 0x3f0 0x20001000 -.bss 0x9e1c 0x200013f0 -.heap 0x4df0 0x2000b210 -.internal_storage 0x3a000 0x2e79c -.zwave_nvm 0x3000 0x6879c -.nvm 0x9000 0x6b79c +.data 0x3f8 0x20001000 +.bss 0x9ea4 0x200013f8 +.heap 0x4d60 0x2000b2a0 +.internal_storage 0x3a000 0x2e8b8 +.zwave_nvm 0x3000 0x688b8 +.nvm 0x9000 0x6b8b8 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x70f0 0x0 -.debug_info 0xa3c85f 0x0 -.debug_abbrev 0x11416 0x0 -.debug_loc 0x28203 0x0 +.debug_frame 0x70fc 0x0 +.debug_info 0xa3ce7d 0x0 +.debug_abbrev 0x11479 0x0 +.debug_loc 0x2822b 0x0 .debug_aranges 0x2a90 0x0 -.debug_ranges 0x5248 0x0 -.debug_line 0x2e3a1 0x0 -.debug_str 0x6fd5c 0x0 -Total 0xba754c +.debug_ranges 0x5230 0x0 +.debug_line 0x2e3fb 0x0 +.debug_str 0x6fe8f 0x0 +Total 0xba7e92 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 191372 + 191664 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47628 + 47772 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4210A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4210A_REGION_US_LR_size.txt index 717217ff06..5d2a7e5803 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4210A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_door_lock_keypad_BRD4210A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_door_lock_keypad.out : section size addr -.text 0x36360 0x8006000 -_cc_handlers_v3 0x240 0x803c360 -_zw_protocol_cmd_handlers 0x70 0x803c5a0 -_zw_protocol_cmd_handlers_lr 0x30 0x803c610 -.ARM.exidx 0x8 0x803c640 -.copy.table 0xc 0x803c648 -.zero.table 0x0 0x803c654 +.text 0x357e4 0x8006000 +_cc_handlers_v3 0x240 0x803b7e4 +_zw_protocol_cmd_handlers 0x70 0x803ba24 +_zw_protocol_cmd_handlers_lr 0x30 0x803ba94 +.ARM.exidx 0x8 0x803bac4 +.copy.table 0xc 0x803bacc +.zero.table 0x0 0x803bad8 .stack 0x1000 0x20000000 -.data 0x550 0x20001000 -.bss 0xad64 0x20001550 -.heap 0x3d48 0x2000c2b8 -.internal_storage 0x2a000 0x803c654 -.zwave_nvm 0x6000 0x8066654 -.nvm 0xa000 0x806c654 +.data 0x558 0x20001000 +.bss 0xadec 0x20001558 +.heap 0x3cb8 0x2000c348 +.internal_storage 0x2c000 0x803bad8 +.zwave_nvm 0x6000 0x8067ad8 +.nvm 0x8000 0x806dad8 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa50c 0x0 -.debug_info 0xa82c37 0x0 -.debug_abbrev 0x16921 0x0 -.debug_loc 0x4637c 0x0 -.debug_aranges 0x3940 0x0 -.debug_ranges 0x7180 0x0 -.debug_line 0x43a79 0x0 -.debug_str 0x7ab49 0x0 -Total 0xc33531 +.debug_frame 0xa498 0x0 +.debug_info 0xa828d8 0x0 +.debug_abbrev 0x16711 0x0 +.debug_loc 0x45e8c 0x0 +.debug_aranges 0x3908 0x0 +.debug_ranges 0x7018 0x0 +.debug_line 0x4354f 0x0 +.debug_str 0x7aba0 0x0 +Total 0xc3186f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 224164 + 221232 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51892 + 52036 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4202A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4202A_REGION_EU_size.txt index 04799aa338..02250db23f 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4202A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4202A_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_key_fob.out : section size addr -.text 0x37e28 0x0 -_cc_handlers_v3 0x168 0x37e28 -_zw_protocol_cmd_handlers 0xb0 0x37f90 -_zw_protocol_cmd_handlers_lr 0x48 0x38040 -.ARM.exidx 0x8 0x38088 -.copy.table 0xc 0x38090 -.zero.table 0x0 0x3809c +.text 0x38bb0 0x0 +_cc_handlers_v3 0x168 0x38bb0 +_zw_protocol_cmd_handlers 0xb0 0x38d18 +_zw_protocol_cmd_handlers_lr 0x48 0x38dc8 +.ARM.exidx 0x8 0x38e10 +.copy.table 0xc 0x38e18 +.zero.table 0x0 0x38e24 .stack 0x400 0x20000000 -.data 0x468 0x20000400 -.bss 0xd224 0x20000868 -.heap 0x2570 0x2000da90 -.zwave_nvm 0x3000 0x3809c -.nvm 0x9000 0x3b09c +.data 0x474 0x20000400 +.bss 0xd2f0 0x20000874 +.heap 0x2498 0x2000db68 +.zwave_nvm 0x3000 0x38e24 +.nvm 0x9000 0x3be24 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0xb998 0x0 -.debug_info 0x88f3ea 0x0 -.debug_abbrev 0x1c8a9 0x0 -.debug_loc 0x41ac3 0x0 -.debug_aranges 0x3f78 0x0 -.debug_ranges 0x7e58 0x0 -.debug_line 0x4c1f2 0x0 -.debug_str 0x8dd42 0x0 +.debug_frame 0xba08 0x0 +.debug_info 0x88f7c3 0x0 +.debug_abbrev 0x1c928 0x0 +.debug_loc 0x41b96 0x0 +.debug_aranges 0x3f88 0x0 +.debug_ranges 0x7db8 0x0 +.debug_line 0x4c176 0x0 +.debug_str 0x8debc 0x0 .stab 0xcc 0x0 .stabstr 0x1b9 0x0 -Total 0xa33186 +Total 0xa34517 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 230660 + 234136 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 57996 + 58212 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4202A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4202A_REGION_US_LR_size.txt index e9c2b68795..da60b67f83 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4202A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4202A_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_key_fob.out : section size addr -.text 0x37e28 0x0 -_cc_handlers_v3 0x168 0x37e28 -_zw_protocol_cmd_handlers 0xb0 0x37f90 -_zw_protocol_cmd_handlers_lr 0x48 0x38040 -.ARM.exidx 0x8 0x38088 -.copy.table 0xc 0x38090 -.zero.table 0x0 0x3809c +.text 0x38bb0 0x0 +_cc_handlers_v3 0x168 0x38bb0 +_zw_protocol_cmd_handlers 0xb0 0x38d18 +_zw_protocol_cmd_handlers_lr 0x48 0x38dc8 +.ARM.exidx 0x8 0x38e10 +.copy.table 0xc 0x38e18 +.zero.table 0x0 0x38e24 .stack 0x400 0x20000000 -.data 0x468 0x20000400 -.bss 0xd224 0x20000868 -.heap 0x2570 0x2000da90 -.zwave_nvm 0x3000 0x3809c -.nvm 0x9000 0x3b09c +.data 0x474 0x20000400 +.bss 0xd2f0 0x20000874 +.heap 0x2498 0x2000db68 +.zwave_nvm 0x3000 0x38e24 +.nvm 0x9000 0x3be24 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0xb998 0x0 -.debug_info 0x88f3ea 0x0 -.debug_abbrev 0x1c8a9 0x0 -.debug_loc 0x41ac3 0x0 -.debug_aranges 0x3f78 0x0 -.debug_ranges 0x7e58 0x0 -.debug_line 0x4c1f2 0x0 -.debug_str 0x8dd45 0x0 +.debug_frame 0xba08 0x0 +.debug_info 0x88f7c3 0x0 +.debug_abbrev 0x1c928 0x0 +.debug_loc 0x41b96 0x0 +.debug_aranges 0x3f88 0x0 +.debug_ranges 0x7db8 0x0 +.debug_line 0x4c176 0x0 +.debug_str 0x8debf 0x0 .stab 0xcc 0x0 .stabstr 0x1b9 0x0 -Total 0xa33189 +Total 0xa3451a The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 230660 + 234136 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 57996 + 58212 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4202A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4202A_REGION_US_size.txt index 04799aa338..02250db23f 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4202A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4202A_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_key_fob.out : section size addr -.text 0x37e28 0x0 -_cc_handlers_v3 0x168 0x37e28 -_zw_protocol_cmd_handlers 0xb0 0x37f90 -_zw_protocol_cmd_handlers_lr 0x48 0x38040 -.ARM.exidx 0x8 0x38088 -.copy.table 0xc 0x38090 -.zero.table 0x0 0x3809c +.text 0x38bb0 0x0 +_cc_handlers_v3 0x168 0x38bb0 +_zw_protocol_cmd_handlers 0xb0 0x38d18 +_zw_protocol_cmd_handlers_lr 0x48 0x38dc8 +.ARM.exidx 0x8 0x38e10 +.copy.table 0xc 0x38e18 +.zero.table 0x0 0x38e24 .stack 0x400 0x20000000 -.data 0x468 0x20000400 -.bss 0xd224 0x20000868 -.heap 0x2570 0x2000da90 -.zwave_nvm 0x3000 0x3809c -.nvm 0x9000 0x3b09c +.data 0x474 0x20000400 +.bss 0xd2f0 0x20000874 +.heap 0x2498 0x2000db68 +.zwave_nvm 0x3000 0x38e24 +.nvm 0x9000 0x3be24 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0xb998 0x0 -.debug_info 0x88f3ea 0x0 -.debug_abbrev 0x1c8a9 0x0 -.debug_loc 0x41ac3 0x0 -.debug_aranges 0x3f78 0x0 -.debug_ranges 0x7e58 0x0 -.debug_line 0x4c1f2 0x0 -.debug_str 0x8dd42 0x0 +.debug_frame 0xba08 0x0 +.debug_info 0x88f7c3 0x0 +.debug_abbrev 0x1c928 0x0 +.debug_loc 0x41b96 0x0 +.debug_aranges 0x3f88 0x0 +.debug_ranges 0x7db8 0x0 +.debug_line 0x4c176 0x0 +.debug_str 0x8debc 0x0 .stab 0xcc 0x0 .stabstr 0x1b9 0x0 -Total 0xa33186 +Total 0xa34517 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 230660 + 234136 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 57996 + 58212 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4205A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4205A_REGION_EU_size.txt index 205eb5575b..f739ae8a2d 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4205A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4205A_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_key_fob.out : section size addr -.text 0x40000 0x8006000 -_cc_handlers_v3 0x168 0x8046000 -_zw_protocol_cmd_handlers 0xb0 0x8046168 -_zw_protocol_cmd_handlers_lr 0x48 0x8046218 -.ARM.exidx 0x8 0x8046260 -.copy.table 0xc 0x8046268 -.zero.table 0x0 0x8046274 +.text 0x3fe14 0x8006000 +_cc_handlers_v3 0x168 0x8045e14 +_zw_protocol_cmd_handlers 0xb0 0x8045f7c +_zw_protocol_cmd_handlers_lr 0x48 0x804602c +.ARM.exidx 0x8 0x8046074 +.copy.table 0xc 0x804607c +.zero.table 0x0 0x8046088 .stack 0x400 0x20000000 -.data 0x5c8 0x20000400 -.bss 0xe034 0x200009c8 -.heap 0x1600 0x2000ea00 -.zwave_nvm 0x6000 0x8046274 -.nvm 0xa000 0x804c274 +.data 0x5d4 0x20000400 +.bss 0xe108 0x200009d4 +.heap 0x1520 0x2000eae0 +.zwave_nvm 0x6000 0x8046088 +.nvm 0xa000 0x804c088 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xeb9c 0x0 -.debug_info 0x8d6808 0x0 -.debug_abbrev 0x221c9 0x0 -.debug_loc 0x5dc6c 0x0 -.debug_aranges 0x4e20 0x0 -.debug_ranges 0x9f18 0x0 -.debug_line 0x60e11 0x0 -.debug_str 0x98b28 0x0 +.debug_frame 0xe804 0x0 +.debug_info 0x8d3e5e 0x0 +.debug_abbrev 0x21949 0x0 +.debug_loc 0x5aec9 0x0 +.debug_aranges 0x4d18 0x0 +.debug_ranges 0x9bf8 0x0 +.debug_line 0x5f61f 0x0 +.debug_str 0x9861e 0x0 .stab 0xcc 0x0 .stabstr 0x1b9 0x0 -Total 0xacddbe +Total 0xac5749 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 264252 + 263772 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 65536 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 61948 + 62172 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4205A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4205A_REGION_US_LR_size.txt index b3cca8dd3b..8906fb053b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4205A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4205A_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_key_fob.out : section size addr -.text 0x40000 0x8006000 -_cc_handlers_v3 0x168 0x8046000 -_zw_protocol_cmd_handlers 0xb0 0x8046168 -_zw_protocol_cmd_handlers_lr 0x48 0x8046218 -.ARM.exidx 0x8 0x8046260 -.copy.table 0xc 0x8046268 -.zero.table 0x0 0x8046274 +.text 0x3fe14 0x8006000 +_cc_handlers_v3 0x168 0x8045e14 +_zw_protocol_cmd_handlers 0xb0 0x8045f7c +_zw_protocol_cmd_handlers_lr 0x48 0x804602c +.ARM.exidx 0x8 0x8046074 +.copy.table 0xc 0x804607c +.zero.table 0x0 0x8046088 .stack 0x400 0x20000000 -.data 0x5c8 0x20000400 -.bss 0xe034 0x200009c8 -.heap 0x1600 0x2000ea00 -.zwave_nvm 0x6000 0x8046274 -.nvm 0xa000 0x804c274 +.data 0x5d4 0x20000400 +.bss 0xe108 0x200009d4 +.heap 0x1520 0x2000eae0 +.zwave_nvm 0x6000 0x8046088 +.nvm 0xa000 0x804c088 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xeb9c 0x0 -.debug_info 0x8d6808 0x0 -.debug_abbrev 0x221c9 0x0 -.debug_loc 0x5dc6c 0x0 -.debug_aranges 0x4e20 0x0 -.debug_ranges 0x9f18 0x0 -.debug_line 0x60e11 0x0 -.debug_str 0x98b2b 0x0 +.debug_frame 0xe804 0x0 +.debug_info 0x8d3e5e 0x0 +.debug_abbrev 0x21949 0x0 +.debug_loc 0x5aec9 0x0 +.debug_aranges 0x4d18 0x0 +.debug_ranges 0x9bf8 0x0 +.debug_line 0x5f61f 0x0 +.debug_str 0x98621 0x0 .stab 0xcc 0x0 .stabstr 0x1b9 0x0 -Total 0xacddc1 +Total 0xac574c The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 264252 + 263772 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 65536 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 61948 + 62172 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4205A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4205A_REGION_US_size.txt index 205eb5575b..f739ae8a2d 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4205A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4205A_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_key_fob.out : section size addr -.text 0x40000 0x8006000 -_cc_handlers_v3 0x168 0x8046000 -_zw_protocol_cmd_handlers 0xb0 0x8046168 -_zw_protocol_cmd_handlers_lr 0x48 0x8046218 -.ARM.exidx 0x8 0x8046260 -.copy.table 0xc 0x8046268 -.zero.table 0x0 0x8046274 +.text 0x3fe14 0x8006000 +_cc_handlers_v3 0x168 0x8045e14 +_zw_protocol_cmd_handlers 0xb0 0x8045f7c +_zw_protocol_cmd_handlers_lr 0x48 0x804602c +.ARM.exidx 0x8 0x8046074 +.copy.table 0xc 0x804607c +.zero.table 0x0 0x8046088 .stack 0x400 0x20000000 -.data 0x5c8 0x20000400 -.bss 0xe034 0x200009c8 -.heap 0x1600 0x2000ea00 -.zwave_nvm 0x6000 0x8046274 -.nvm 0xa000 0x804c274 +.data 0x5d4 0x20000400 +.bss 0xe108 0x200009d4 +.heap 0x1520 0x2000eae0 +.zwave_nvm 0x6000 0x8046088 +.nvm 0xa000 0x804c088 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xeb9c 0x0 -.debug_info 0x8d6808 0x0 -.debug_abbrev 0x221c9 0x0 -.debug_loc 0x5dc6c 0x0 -.debug_aranges 0x4e20 0x0 -.debug_ranges 0x9f18 0x0 -.debug_line 0x60e11 0x0 -.debug_str 0x98b28 0x0 +.debug_frame 0xe804 0x0 +.debug_info 0x8d3e5e 0x0 +.debug_abbrev 0x21949 0x0 +.debug_loc 0x5aec9 0x0 +.debug_aranges 0x4d18 0x0 +.debug_ranges 0x9bf8 0x0 +.debug_line 0x5f61f 0x0 +.debug_str 0x9861e 0x0 .stab 0xcc 0x0 .stabstr 0x1b9 0x0 -Total 0xacddbe +Total 0xac5749 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 264252 + 263772 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 65536 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 61948 + 62172 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4205B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4205B_REGION_EU_size.txt index 2a6789238b..009ed86508 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4205B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4205B_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_key_fob.out : section size addr -.text 0x40500 0x8006000 -_cc_handlers_v3 0x168 0x8046500 -_zw_protocol_cmd_handlers 0xb0 0x8046668 -_zw_protocol_cmd_handlers_lr 0x48 0x8046718 -.ARM.exidx 0x8 0x8046760 -.copy.table 0xc 0x8046768 -.zero.table 0x0 0x8046774 +.text 0x40598 0x8006000 +_cc_handlers_v3 0x168 0x8046598 +_zw_protocol_cmd_handlers 0xb0 0x8046700 +_zw_protocol_cmd_handlers_lr 0x48 0x80467b0 +.ARM.exidx 0x8 0x80467f8 +.copy.table 0xc 0x8046800 +.zero.table 0x0 0x804680c .stack 0x400 0x20000000 -.data 0x5c8 0x20000400 -.bss 0xe16c 0x200009c8 -.heap 0x14c8 0x2000eb38 -.zwave_nvm 0x6000 0x8046774 -.nvm 0xa000 0x804c774 +.data 0x5d4 0x20000400 +.bss 0xe238 0x200009d4 +.heap 0x13f0 0x2000ec10 +.zwave_nvm 0x6000 0x804680c +.nvm 0xa000 0x804c80c .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xedac 0x0 -.debug_info 0x8d8a42 0x0 -.debug_abbrev 0x21f12 0x0 -.debug_loc 0x5f986 0x0 -.debug_aranges 0x4e50 0x0 -.debug_ranges 0xa038 0x0 -.debug_line 0x61fbd 0x0 -.debug_str 0x98e80 0x0 +.debug_frame 0xed9c 0x0 +.debug_info 0x8d84a2 0x0 +.debug_abbrev 0x21d1e 0x0 +.debug_loc 0x5f556 0x0 +.debug_aranges 0x4e28 0x0 +.debug_ranges 0x9e28 0x0 +.debug_line 0x61999 0x0 +.debug_str 0x98f21 0x0 .stab 0xcc 0x0 .stabstr 0x1b9 0x0 -Total 0xad37bf +Total 0xad24c8 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 265532 + 265696 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 65536 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 62260 + 62476 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4205B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4205B_REGION_US_LR_size.txt index a2baea2739..9b1b24859b 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4205B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4205B_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_key_fob.out : section size addr -.text 0x40500 0x8006000 -_cc_handlers_v3 0x168 0x8046500 -_zw_protocol_cmd_handlers 0xb0 0x8046668 -_zw_protocol_cmd_handlers_lr 0x48 0x8046718 -.ARM.exidx 0x8 0x8046760 -.copy.table 0xc 0x8046768 -.zero.table 0x0 0x8046774 +.text 0x40598 0x8006000 +_cc_handlers_v3 0x168 0x8046598 +_zw_protocol_cmd_handlers 0xb0 0x8046700 +_zw_protocol_cmd_handlers_lr 0x48 0x80467b0 +.ARM.exidx 0x8 0x80467f8 +.copy.table 0xc 0x8046800 +.zero.table 0x0 0x804680c .stack 0x400 0x20000000 -.data 0x5c8 0x20000400 -.bss 0xe16c 0x200009c8 -.heap 0x14c8 0x2000eb38 -.zwave_nvm 0x6000 0x8046774 -.nvm 0xa000 0x804c774 +.data 0x5d4 0x20000400 +.bss 0xe238 0x200009d4 +.heap 0x13f0 0x2000ec10 +.zwave_nvm 0x6000 0x804680c +.nvm 0xa000 0x804c80c .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xedac 0x0 -.debug_info 0x8d8a42 0x0 -.debug_abbrev 0x21f12 0x0 -.debug_loc 0x5f986 0x0 -.debug_aranges 0x4e50 0x0 -.debug_ranges 0xa038 0x0 -.debug_line 0x61fbd 0x0 -.debug_str 0x98e83 0x0 +.debug_frame 0xed9c 0x0 +.debug_info 0x8d84a2 0x0 +.debug_abbrev 0x21d1e 0x0 +.debug_loc 0x5f556 0x0 +.debug_aranges 0x4e28 0x0 +.debug_ranges 0x9e28 0x0 +.debug_line 0x61999 0x0 +.debug_str 0x98f24 0x0 .stab 0xcc 0x0 .stabstr 0x1b9 0x0 -Total 0xad37c2 +Total 0xad24cb The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 265532 + 265696 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 65536 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 62260 + 62476 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4205B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4205B_REGION_US_size.txt index 2a6789238b..009ed86508 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4205B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4205B_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_key_fob.out : section size addr -.text 0x40500 0x8006000 -_cc_handlers_v3 0x168 0x8046500 -_zw_protocol_cmd_handlers 0xb0 0x8046668 -_zw_protocol_cmd_handlers_lr 0x48 0x8046718 -.ARM.exidx 0x8 0x8046760 -.copy.table 0xc 0x8046768 -.zero.table 0x0 0x8046774 +.text 0x40598 0x8006000 +_cc_handlers_v3 0x168 0x8046598 +_zw_protocol_cmd_handlers 0xb0 0x8046700 +_zw_protocol_cmd_handlers_lr 0x48 0x80467b0 +.ARM.exidx 0x8 0x80467f8 +.copy.table 0xc 0x8046800 +.zero.table 0x0 0x804680c .stack 0x400 0x20000000 -.data 0x5c8 0x20000400 -.bss 0xe16c 0x200009c8 -.heap 0x14c8 0x2000eb38 -.zwave_nvm 0x6000 0x8046774 -.nvm 0xa000 0x804c774 +.data 0x5d4 0x20000400 +.bss 0xe238 0x200009d4 +.heap 0x13f0 0x2000ec10 +.zwave_nvm 0x6000 0x804680c +.nvm 0xa000 0x804c80c .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xedac 0x0 -.debug_info 0x8d8a42 0x0 -.debug_abbrev 0x21f12 0x0 -.debug_loc 0x5f986 0x0 -.debug_aranges 0x4e50 0x0 -.debug_ranges 0xa038 0x0 -.debug_line 0x61fbd 0x0 -.debug_str 0x98e80 0x0 +.debug_frame 0xed9c 0x0 +.debug_info 0x8d84a2 0x0 +.debug_abbrev 0x21d1e 0x0 +.debug_loc 0x5f556 0x0 +.debug_aranges 0x4e28 0x0 +.debug_ranges 0x9e28 0x0 +.debug_line 0x61999 0x0 +.debug_str 0x98f21 0x0 .stab 0xcc 0x0 .stabstr 0x1b9 0x0 -Total 0xad37bf +Total 0xad24c8 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 265532 + 265696 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 65536 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 62260 + 62476 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4207A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4207A_REGION_EU_size.txt index 04799aa338..02250db23f 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4207A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4207A_REGION_EU_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_key_fob.out : section size addr -.text 0x37e28 0x0 -_cc_handlers_v3 0x168 0x37e28 -_zw_protocol_cmd_handlers 0xb0 0x37f90 -_zw_protocol_cmd_handlers_lr 0x48 0x38040 -.ARM.exidx 0x8 0x38088 -.copy.table 0xc 0x38090 -.zero.table 0x0 0x3809c +.text 0x38bb0 0x0 +_cc_handlers_v3 0x168 0x38bb0 +_zw_protocol_cmd_handlers 0xb0 0x38d18 +_zw_protocol_cmd_handlers_lr 0x48 0x38dc8 +.ARM.exidx 0x8 0x38e10 +.copy.table 0xc 0x38e18 +.zero.table 0x0 0x38e24 .stack 0x400 0x20000000 -.data 0x468 0x20000400 -.bss 0xd224 0x20000868 -.heap 0x2570 0x2000da90 -.zwave_nvm 0x3000 0x3809c -.nvm 0x9000 0x3b09c +.data 0x474 0x20000400 +.bss 0xd2f0 0x20000874 +.heap 0x2498 0x2000db68 +.zwave_nvm 0x3000 0x38e24 +.nvm 0x9000 0x3be24 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0xb998 0x0 -.debug_info 0x88f3ea 0x0 -.debug_abbrev 0x1c8a9 0x0 -.debug_loc 0x41ac3 0x0 -.debug_aranges 0x3f78 0x0 -.debug_ranges 0x7e58 0x0 -.debug_line 0x4c1f2 0x0 -.debug_str 0x8dd42 0x0 +.debug_frame 0xba08 0x0 +.debug_info 0x88f7c3 0x0 +.debug_abbrev 0x1c928 0x0 +.debug_loc 0x41b96 0x0 +.debug_aranges 0x3f88 0x0 +.debug_ranges 0x7db8 0x0 +.debug_line 0x4c176 0x0 +.debug_str 0x8debc 0x0 .stab 0xcc 0x0 .stabstr 0x1b9 0x0 -Total 0xa33186 +Total 0xa34517 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 230660 + 234136 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 57996 + 58212 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4207A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4207A_REGION_US_LR_size.txt index e9c2b68795..da60b67f83 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4207A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4207A_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_key_fob.out : section size addr -.text 0x37e28 0x0 -_cc_handlers_v3 0x168 0x37e28 -_zw_protocol_cmd_handlers 0xb0 0x37f90 -_zw_protocol_cmd_handlers_lr 0x48 0x38040 -.ARM.exidx 0x8 0x38088 -.copy.table 0xc 0x38090 -.zero.table 0x0 0x3809c +.text 0x38bb0 0x0 +_cc_handlers_v3 0x168 0x38bb0 +_zw_protocol_cmd_handlers 0xb0 0x38d18 +_zw_protocol_cmd_handlers_lr 0x48 0x38dc8 +.ARM.exidx 0x8 0x38e10 +.copy.table 0xc 0x38e18 +.zero.table 0x0 0x38e24 .stack 0x400 0x20000000 -.data 0x468 0x20000400 -.bss 0xd224 0x20000868 -.heap 0x2570 0x2000da90 -.zwave_nvm 0x3000 0x3809c -.nvm 0x9000 0x3b09c +.data 0x474 0x20000400 +.bss 0xd2f0 0x20000874 +.heap 0x2498 0x2000db68 +.zwave_nvm 0x3000 0x38e24 +.nvm 0x9000 0x3be24 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0xb998 0x0 -.debug_info 0x88f3ea 0x0 -.debug_abbrev 0x1c8a9 0x0 -.debug_loc 0x41ac3 0x0 -.debug_aranges 0x3f78 0x0 -.debug_ranges 0x7e58 0x0 -.debug_line 0x4c1f2 0x0 -.debug_str 0x8dd45 0x0 +.debug_frame 0xba08 0x0 +.debug_info 0x88f7c3 0x0 +.debug_abbrev 0x1c928 0x0 +.debug_loc 0x41b96 0x0 +.debug_aranges 0x3f88 0x0 +.debug_ranges 0x7db8 0x0 +.debug_line 0x4c176 0x0 +.debug_str 0x8debf 0x0 .stab 0xcc 0x0 .stabstr 0x1b9 0x0 -Total 0xa33189 +Total 0xa3451a The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 230660 + 234136 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 57996 + 58212 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4207A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4207A_REGION_US_size.txt index 04799aa338..02250db23f 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4207A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4207A_REGION_US_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_key_fob.out : section size addr -.text 0x37e28 0x0 -_cc_handlers_v3 0x168 0x37e28 -_zw_protocol_cmd_handlers 0xb0 0x37f90 -_zw_protocol_cmd_handlers_lr 0x48 0x38040 -.ARM.exidx 0x8 0x38088 -.copy.table 0xc 0x38090 -.zero.table 0x0 0x3809c +.text 0x38bb0 0x0 +_cc_handlers_v3 0x168 0x38bb0 +_zw_protocol_cmd_handlers 0xb0 0x38d18 +_zw_protocol_cmd_handlers_lr 0x48 0x38dc8 +.ARM.exidx 0x8 0x38e10 +.copy.table 0xc 0x38e18 +.zero.table 0x0 0x38e24 .stack 0x400 0x20000000 -.data 0x468 0x20000400 -.bss 0xd224 0x20000868 -.heap 0x2570 0x2000da90 -.zwave_nvm 0x3000 0x3809c -.nvm 0x9000 0x3b09c +.data 0x474 0x20000400 +.bss 0xd2f0 0x20000874 +.heap 0x2498 0x2000db68 +.zwave_nvm 0x3000 0x38e24 +.nvm 0x9000 0x3be24 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0xb998 0x0 -.debug_info 0x88f3ea 0x0 -.debug_abbrev 0x1c8a9 0x0 -.debug_loc 0x41ac3 0x0 -.debug_aranges 0x3f78 0x0 -.debug_ranges 0x7e58 0x0 -.debug_line 0x4c1f2 0x0 -.debug_str 0x8dd42 0x0 +.debug_frame 0xba08 0x0 +.debug_info 0x88f7c3 0x0 +.debug_abbrev 0x1c928 0x0 +.debug_loc 0x41b96 0x0 +.debug_aranges 0x3f88 0x0 +.debug_ranges 0x7db8 0x0 +.debug_line 0x4c176 0x0 +.debug_str 0x8debc 0x0 .stab 0xcc 0x0 .stabstr 0x1b9 0x0 -Total 0xa33186 +Total 0xa34517 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 230660 + 234136 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 57996 + 58212 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4210A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4210A_REGION_US_LR_size.txt index f6aa4f1e7d..d365cf8554 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4210A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_key_fob_BRD4210A_REGION_US_LR_size.txt @@ -5,39 +5,39 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_key_fob.out : section size addr -.text 0x40080 0x8006000 -_cc_handlers_v3 0x168 0x8046080 -_zw_protocol_cmd_handlers 0xb0 0x80461e8 -_zw_protocol_cmd_handlers_lr 0x48 0x8046298 -.ARM.exidx 0x8 0x80462e0 -.copy.table 0xc 0x80462e8 -.zero.table 0x0 0x80462f4 +.text 0x40110 0x8006000 +_cc_handlers_v3 0x168 0x8046110 +_zw_protocol_cmd_handlers 0xb0 0x8046278 +_zw_protocol_cmd_handlers_lr 0x48 0x8046328 +.ARM.exidx 0x8 0x8046370 +.copy.table 0xc 0x8046378 +.zero.table 0x0 0x8046384 .stack 0x400 0x20000000 -.data 0x5cc 0x20000400 -.bss 0xe150 0x200009cc -.heap 0x14e0 0x2000eb20 -.zwave_nvm 0x6000 0x80462f4 -.nvm 0xa000 0x804c2f4 +.data 0x5d8 0x20000400 +.bss 0xe214 0x200009d8 +.heap 0x1410 0x2000ebf0 +.zwave_nvm 0x6000 0x8046384 +.nvm 0xa000 0x804c384 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xeddc 0x0 -.debug_info 0x8d822a 0x0 -.debug_abbrev 0x21eb9 0x0 -.debug_loc 0x5f988 0x0 -.debug_aranges 0x4e40 0x0 -.debug_ranges 0xa048 0x0 -.debug_line 0x621c1 0x0 -.debug_str 0x987a9 0x0 +.debug_frame 0xedcc 0x0 +.debug_info 0x8d7c8a 0x0 +.debug_abbrev 0x21cc5 0x0 +.debug_loc 0x5f555 0x0 +.debug_aranges 0x4e18 0x0 +.debug_ranges 0x9e38 0x0 +.debug_line 0x61b9d 0x0 +.debug_str 0x9884b 0x0 .stab 0xcc 0x0 .stabstr 0x1b9 0x0 -Total 0xad262d +Total 0xad132c The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 264384 + 264540 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 65536 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 62236 + 62444 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4202A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4202A_REGION_EU_size.txt index 6bce56f79c..c411edbd4c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4202A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4202A_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x2e3fc 0x0 -_cc_handlers_v3 0x21c 0x2e3fc -_zw_protocol_cmd_handlers 0x70 0x2e618 -_zw_protocol_cmd_handlers_lr 0x30 0x2e688 -.ARM.exidx 0x8 0x2e6b8 -.copy.table 0xc 0x2e6c0 -.zero.table 0x0 0x2e6cc +.text 0x2e558 0x0 +_cc_handlers_v3 0x21c 0x2e558 +_zw_protocol_cmd_handlers 0x70 0x2e774 +_zw_protocol_cmd_handlers_lr 0x30 0x2e7e4 +.ARM.exidx 0x8 0x2e814 +.copy.table 0xc 0x2e81c +.zero.table 0x0 0x2e828 .stack 0x1000 0x20000000 -.data 0x5bc 0x20001000 -.bss 0x9dc8 0x200015bc -.heap 0x4c78 0x2000b388 -.internal_storage 0x3a000 0x2e6cc -.zwave_nvm 0x3000 0x686cc -.nvm 0x9000 0x6b6cc +.data 0x5c8 0x20001000 +.bss 0x9e4c 0x200015c8 +.heap 0x4be8 0x2000b418 +.internal_storage 0x3a000 0x2e828 +.zwave_nvm 0x3000 0x68828 +.nvm 0x9000 0x6b828 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6fdc 0x0 -.debug_info 0x9d555a 0x0 -.debug_abbrev 0x11473 0x0 -.debug_loc 0x2823a 0x0 +.debug_frame 0x6fe8 0x0 +.debug_info 0x9d5b52 0x0 +.debug_abbrev 0x114d6 0x0 +.debug_loc 0x2825f 0x0 .debug_aranges 0x2a38 0x0 -.debug_ranges 0x52d0 0x0 -.debug_line 0x2dd1a 0x0 -.debug_str 0x6d5fb 0x0 -Total 0xb3d33f +.debug_ranges 0x52b8 0x0 +.debug_line 0x2dd6d 0x0 +.debug_str 0x6d740 0x0 +Total 0xb3dca7 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 191624 + 191984 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48004 + 48148 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4202A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4202A_REGION_US_LR_size.txt index 6bce56f79c..c411edbd4c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4202A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4202A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x2e3fc 0x0 -_cc_handlers_v3 0x21c 0x2e3fc -_zw_protocol_cmd_handlers 0x70 0x2e618 -_zw_protocol_cmd_handlers_lr 0x30 0x2e688 -.ARM.exidx 0x8 0x2e6b8 -.copy.table 0xc 0x2e6c0 -.zero.table 0x0 0x2e6cc +.text 0x2e558 0x0 +_cc_handlers_v3 0x21c 0x2e558 +_zw_protocol_cmd_handlers 0x70 0x2e774 +_zw_protocol_cmd_handlers_lr 0x30 0x2e7e4 +.ARM.exidx 0x8 0x2e814 +.copy.table 0xc 0x2e81c +.zero.table 0x0 0x2e828 .stack 0x1000 0x20000000 -.data 0x5bc 0x20001000 -.bss 0x9dc8 0x200015bc -.heap 0x4c78 0x2000b388 -.internal_storage 0x3a000 0x2e6cc -.zwave_nvm 0x3000 0x686cc -.nvm 0x9000 0x6b6cc +.data 0x5c8 0x20001000 +.bss 0x9e4c 0x200015c8 +.heap 0x4be8 0x2000b418 +.internal_storage 0x3a000 0x2e828 +.zwave_nvm 0x3000 0x68828 +.nvm 0x9000 0x6b828 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6fdc 0x0 -.debug_info 0x9d555a 0x0 -.debug_abbrev 0x11473 0x0 -.debug_loc 0x2823a 0x0 +.debug_frame 0x6fe8 0x0 +.debug_info 0x9d5b52 0x0 +.debug_abbrev 0x114d6 0x0 +.debug_loc 0x2825f 0x0 .debug_aranges 0x2a38 0x0 -.debug_ranges 0x52d0 0x0 -.debug_line 0x2dd1a 0x0 -.debug_str 0x6d5fb 0x0 -Total 0xb3d33f +.debug_ranges 0x52b8 0x0 +.debug_line 0x2dd6d 0x0 +.debug_str 0x6d740 0x0 +Total 0xb3dca7 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 191624 + 191984 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48004 + 48148 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4202A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4202A_REGION_US_size.txt index 6bce56f79c..c411edbd4c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4202A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4202A_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x2e3fc 0x0 -_cc_handlers_v3 0x21c 0x2e3fc -_zw_protocol_cmd_handlers 0x70 0x2e618 -_zw_protocol_cmd_handlers_lr 0x30 0x2e688 -.ARM.exidx 0x8 0x2e6b8 -.copy.table 0xc 0x2e6c0 -.zero.table 0x0 0x2e6cc +.text 0x2e558 0x0 +_cc_handlers_v3 0x21c 0x2e558 +_zw_protocol_cmd_handlers 0x70 0x2e774 +_zw_protocol_cmd_handlers_lr 0x30 0x2e7e4 +.ARM.exidx 0x8 0x2e814 +.copy.table 0xc 0x2e81c +.zero.table 0x0 0x2e828 .stack 0x1000 0x20000000 -.data 0x5bc 0x20001000 -.bss 0x9dc8 0x200015bc -.heap 0x4c78 0x2000b388 -.internal_storage 0x3a000 0x2e6cc -.zwave_nvm 0x3000 0x686cc -.nvm 0x9000 0x6b6cc +.data 0x5c8 0x20001000 +.bss 0x9e4c 0x200015c8 +.heap 0x4be8 0x2000b418 +.internal_storage 0x3a000 0x2e828 +.zwave_nvm 0x3000 0x68828 +.nvm 0x9000 0x6b828 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6fdc 0x0 -.debug_info 0x9d555a 0x0 -.debug_abbrev 0x11473 0x0 -.debug_loc 0x2823a 0x0 +.debug_frame 0x6fe8 0x0 +.debug_info 0x9d5b52 0x0 +.debug_abbrev 0x114d6 0x0 +.debug_loc 0x2825f 0x0 .debug_aranges 0x2a38 0x0 -.debug_ranges 0x52d0 0x0 -.debug_line 0x2dd1a 0x0 -.debug_str 0x6d5fb 0x0 -Total 0xb3d33f +.debug_ranges 0x52b8 0x0 +.debug_line 0x2dd6d 0x0 +.debug_str 0x6d740 0x0 +Total 0xb3dca7 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 191624 + 191984 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48004 + 48148 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205A_REGION_EU_size.txt index f2c42e718b..5e54590a3d 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205A_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x36308 0x8006000 -_cc_handlers_v3 0x21c 0x803c308 -_zw_protocol_cmd_handlers 0x70 0x803c524 -_zw_protocol_cmd_handlers_lr 0x30 0x803c594 -.ARM.exidx 0x8 0x803c5c4 -.copy.table 0xc 0x803c5cc -.zero.table 0x0 0x803c5d8 +.text 0x3551c 0x8006000 +_cc_handlers_v3 0x21c 0x803b51c +_zw_protocol_cmd_handlers 0x70 0x803b738 +_zw_protocol_cmd_handlers_lr 0x30 0x803b7a8 +.ARM.exidx 0x8 0x803b7d8 +.copy.table 0xc 0x803b7e0 +.zero.table 0x0 0x803b7ec .stack 0x1000 0x20000000 -.data 0x714 0x20001000 -.bss 0xabd0 0x20001714 -.heap 0x3d18 0x2000c2e8 -.internal_storage 0x2a000 0x803c5d8 -.zwave_nvm 0x6000 0x80665d8 -.nvm 0xa000 0x806c5d8 +.data 0x720 0x20001000 +.bss 0xac64 0x20001720 +.heap 0x3c78 0x2000c388 +.internal_storage 0x2c000 0x803b7ec +.zwave_nvm 0x6000 0x80677ec +.nvm 0x8000 0x806d7ec .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa32c 0x0 -.debug_info 0xa1ed68 0x0 -.debug_abbrev 0x17235 0x0 -.debug_loc 0x44f7e 0x0 -.debug_aranges 0x3988 0x0 -.debug_ranges 0x71e0 0x0 -.debug_line 0x42ec8 0x0 -.debug_str 0x79df8 0x0 -Total 0xbcd0c2 +.debug_frame 0x9f30 0x0 +.debug_info 0xa1c5d3 0x0 +.debug_abbrev 0x1698e 0x0 +.debug_loc 0x4219a 0x0 +.debug_aranges 0x3870 0x0 +.debug_ranges 0x6f88 0x0 +.debug_line 0x417c6 0x0 +.debug_str 0x798b6 0x0 +Total 0xbc4106 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 224492 + 220940 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51940 + 52100 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205A_REGION_US_LR_size.txt index f2c42e718b..5e54590a3d 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x36308 0x8006000 -_cc_handlers_v3 0x21c 0x803c308 -_zw_protocol_cmd_handlers 0x70 0x803c524 -_zw_protocol_cmd_handlers_lr 0x30 0x803c594 -.ARM.exidx 0x8 0x803c5c4 -.copy.table 0xc 0x803c5cc -.zero.table 0x0 0x803c5d8 +.text 0x3551c 0x8006000 +_cc_handlers_v3 0x21c 0x803b51c +_zw_protocol_cmd_handlers 0x70 0x803b738 +_zw_protocol_cmd_handlers_lr 0x30 0x803b7a8 +.ARM.exidx 0x8 0x803b7d8 +.copy.table 0xc 0x803b7e0 +.zero.table 0x0 0x803b7ec .stack 0x1000 0x20000000 -.data 0x714 0x20001000 -.bss 0xabd0 0x20001714 -.heap 0x3d18 0x2000c2e8 -.internal_storage 0x2a000 0x803c5d8 -.zwave_nvm 0x6000 0x80665d8 -.nvm 0xa000 0x806c5d8 +.data 0x720 0x20001000 +.bss 0xac64 0x20001720 +.heap 0x3c78 0x2000c388 +.internal_storage 0x2c000 0x803b7ec +.zwave_nvm 0x6000 0x80677ec +.nvm 0x8000 0x806d7ec .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa32c 0x0 -.debug_info 0xa1ed68 0x0 -.debug_abbrev 0x17235 0x0 -.debug_loc 0x44f7e 0x0 -.debug_aranges 0x3988 0x0 -.debug_ranges 0x71e0 0x0 -.debug_line 0x42ec8 0x0 -.debug_str 0x79df8 0x0 -Total 0xbcd0c2 +.debug_frame 0x9f30 0x0 +.debug_info 0xa1c5d3 0x0 +.debug_abbrev 0x1698e 0x0 +.debug_loc 0x4219a 0x0 +.debug_aranges 0x3870 0x0 +.debug_ranges 0x6f88 0x0 +.debug_line 0x417c6 0x0 +.debug_str 0x798b6 0x0 +Total 0xbc4106 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 224492 + 220940 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51940 + 52100 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205A_REGION_US_size.txt index f2c42e718b..5e54590a3d 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205A_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x36308 0x8006000 -_cc_handlers_v3 0x21c 0x803c308 -_zw_protocol_cmd_handlers 0x70 0x803c524 -_zw_protocol_cmd_handlers_lr 0x30 0x803c594 -.ARM.exidx 0x8 0x803c5c4 -.copy.table 0xc 0x803c5cc -.zero.table 0x0 0x803c5d8 +.text 0x3551c 0x8006000 +_cc_handlers_v3 0x21c 0x803b51c +_zw_protocol_cmd_handlers 0x70 0x803b738 +_zw_protocol_cmd_handlers_lr 0x30 0x803b7a8 +.ARM.exidx 0x8 0x803b7d8 +.copy.table 0xc 0x803b7e0 +.zero.table 0x0 0x803b7ec .stack 0x1000 0x20000000 -.data 0x714 0x20001000 -.bss 0xabd0 0x20001714 -.heap 0x3d18 0x2000c2e8 -.internal_storage 0x2a000 0x803c5d8 -.zwave_nvm 0x6000 0x80665d8 -.nvm 0xa000 0x806c5d8 +.data 0x720 0x20001000 +.bss 0xac64 0x20001720 +.heap 0x3c78 0x2000c388 +.internal_storage 0x2c000 0x803b7ec +.zwave_nvm 0x6000 0x80677ec +.nvm 0x8000 0x806d7ec .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa32c 0x0 -.debug_info 0xa1ed68 0x0 -.debug_abbrev 0x17235 0x0 -.debug_loc 0x44f7e 0x0 -.debug_aranges 0x3988 0x0 -.debug_ranges 0x71e0 0x0 -.debug_line 0x42ec8 0x0 -.debug_str 0x79df8 0x0 -Total 0xbcd0c2 +.debug_frame 0x9f30 0x0 +.debug_info 0xa1c5d3 0x0 +.debug_abbrev 0x1698e 0x0 +.debug_loc 0x4219a 0x0 +.debug_aranges 0x3870 0x0 +.debug_ranges 0x6f88 0x0 +.debug_line 0x417c6 0x0 +.debug_str 0x798b6 0x0 +Total 0xbc4106 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 224492 + 220940 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51940 + 52100 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205B_REGION_EU_size.txt index 847cb94c75..ba5194032e 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205B_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x36658 0x8006000 -_cc_handlers_v3 0x21c 0x803c658 -_zw_protocol_cmd_handlers 0x70 0x803c874 -_zw_protocol_cmd_handlers_lr 0x30 0x803c8e4 -.ARM.exidx 0x8 0x803c914 -.copy.table 0xc 0x803c91c -.zero.table 0x0 0x803c928 +.text 0x35ae4 0x8006000 +_cc_handlers_v3 0x21c 0x803bae4 +_zw_protocol_cmd_handlers 0x70 0x803bd00 +_zw_protocol_cmd_handlers_lr 0x30 0x803bd70 +.ARM.exidx 0x8 0x803bda0 +.copy.table 0xc 0x803bda8 +.zero.table 0x0 0x803bdb4 .stack 0x1000 0x20000000 -.data 0x714 0x20001000 -.bss 0xad08 0x20001714 -.heap 0x3be0 0x2000c420 -.internal_storage 0x2a000 0x803c928 -.zwave_nvm 0x6000 0x8066928 -.nvm 0xa000 0x806c928 +.data 0x720 0x20001000 +.bss 0xad94 0x20001720 +.heap 0x3b48 0x2000c4b8 +.internal_storage 0x2c000 0x803bdb4 +.zwave_nvm 0x6000 0x8067db4 +.nvm 0x8000 0x806ddb4 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa53c 0x0 -.debug_info 0xa20f90 0x0 -.debug_abbrev 0x16f7e 0x0 -.debug_loc 0x46ca9 0x0 -.debug_aranges 0x39b8 0x0 -.debug_ranges 0x7300 0x0 -.debug_line 0x44074 0x0 -.debug_str 0x7a14b 0x0 -Total 0xbd290d +.debug_frame 0xa4c8 0x0 +.debug_info 0xa20c05 0x0 +.debug_abbrev 0x16d63 0x0 +.debug_loc 0x46838 0x0 +.debug_aranges 0x3980 0x0 +.debug_ranges 0x71b8 0x0 +.debug_line 0x43b40 0x0 +.debug_str 0x7a1b4 0x0 +Total 0xbd0cc3 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225340 + 222420 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52252 + 52404 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205B_REGION_US_LR_size.txt index 847cb94c75..ba5194032e 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205B_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x36658 0x8006000 -_cc_handlers_v3 0x21c 0x803c658 -_zw_protocol_cmd_handlers 0x70 0x803c874 -_zw_protocol_cmd_handlers_lr 0x30 0x803c8e4 -.ARM.exidx 0x8 0x803c914 -.copy.table 0xc 0x803c91c -.zero.table 0x0 0x803c928 +.text 0x35ae4 0x8006000 +_cc_handlers_v3 0x21c 0x803bae4 +_zw_protocol_cmd_handlers 0x70 0x803bd00 +_zw_protocol_cmd_handlers_lr 0x30 0x803bd70 +.ARM.exidx 0x8 0x803bda0 +.copy.table 0xc 0x803bda8 +.zero.table 0x0 0x803bdb4 .stack 0x1000 0x20000000 -.data 0x714 0x20001000 -.bss 0xad08 0x20001714 -.heap 0x3be0 0x2000c420 -.internal_storage 0x2a000 0x803c928 -.zwave_nvm 0x6000 0x8066928 -.nvm 0xa000 0x806c928 +.data 0x720 0x20001000 +.bss 0xad94 0x20001720 +.heap 0x3b48 0x2000c4b8 +.internal_storage 0x2c000 0x803bdb4 +.zwave_nvm 0x6000 0x8067db4 +.nvm 0x8000 0x806ddb4 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa53c 0x0 -.debug_info 0xa20f90 0x0 -.debug_abbrev 0x16f7e 0x0 -.debug_loc 0x46ca9 0x0 -.debug_aranges 0x39b8 0x0 -.debug_ranges 0x7300 0x0 -.debug_line 0x44074 0x0 -.debug_str 0x7a14b 0x0 -Total 0xbd290d +.debug_frame 0xa4c8 0x0 +.debug_info 0xa20c05 0x0 +.debug_abbrev 0x16d63 0x0 +.debug_loc 0x46838 0x0 +.debug_aranges 0x3980 0x0 +.debug_ranges 0x71b8 0x0 +.debug_line 0x43b40 0x0 +.debug_str 0x7a1b4 0x0 +Total 0xbd0cc3 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225340 + 222420 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52252 + 52404 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205B_REGION_US_size.txt index 847cb94c75..ba5194032e 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4205B_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x36658 0x8006000 -_cc_handlers_v3 0x21c 0x803c658 -_zw_protocol_cmd_handlers 0x70 0x803c874 -_zw_protocol_cmd_handlers_lr 0x30 0x803c8e4 -.ARM.exidx 0x8 0x803c914 -.copy.table 0xc 0x803c91c -.zero.table 0x0 0x803c928 +.text 0x35ae4 0x8006000 +_cc_handlers_v3 0x21c 0x803bae4 +_zw_protocol_cmd_handlers 0x70 0x803bd00 +_zw_protocol_cmd_handlers_lr 0x30 0x803bd70 +.ARM.exidx 0x8 0x803bda0 +.copy.table 0xc 0x803bda8 +.zero.table 0x0 0x803bdb4 .stack 0x1000 0x20000000 -.data 0x714 0x20001000 -.bss 0xad08 0x20001714 -.heap 0x3be0 0x2000c420 -.internal_storage 0x2a000 0x803c928 -.zwave_nvm 0x6000 0x8066928 -.nvm 0xa000 0x806c928 +.data 0x720 0x20001000 +.bss 0xad94 0x20001720 +.heap 0x3b48 0x2000c4b8 +.internal_storage 0x2c000 0x803bdb4 +.zwave_nvm 0x6000 0x8067db4 +.nvm 0x8000 0x806ddb4 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa53c 0x0 -.debug_info 0xa20f90 0x0 -.debug_abbrev 0x16f7e 0x0 -.debug_loc 0x46ca9 0x0 -.debug_aranges 0x39b8 0x0 -.debug_ranges 0x7300 0x0 -.debug_line 0x44074 0x0 -.debug_str 0x7a14b 0x0 -Total 0xbd290d +.debug_frame 0xa4c8 0x0 +.debug_info 0xa20c05 0x0 +.debug_abbrev 0x16d63 0x0 +.debug_loc 0x46838 0x0 +.debug_aranges 0x3980 0x0 +.debug_ranges 0x71b8 0x0 +.debug_line 0x43b40 0x0 +.debug_str 0x7a1b4 0x0 +Total 0xbd0cc3 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225340 + 222420 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52252 + 52404 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4207A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4207A_REGION_EU_size.txt index 6bce56f79c..c411edbd4c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4207A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4207A_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x2e3fc 0x0 -_cc_handlers_v3 0x21c 0x2e3fc -_zw_protocol_cmd_handlers 0x70 0x2e618 -_zw_protocol_cmd_handlers_lr 0x30 0x2e688 -.ARM.exidx 0x8 0x2e6b8 -.copy.table 0xc 0x2e6c0 -.zero.table 0x0 0x2e6cc +.text 0x2e558 0x0 +_cc_handlers_v3 0x21c 0x2e558 +_zw_protocol_cmd_handlers 0x70 0x2e774 +_zw_protocol_cmd_handlers_lr 0x30 0x2e7e4 +.ARM.exidx 0x8 0x2e814 +.copy.table 0xc 0x2e81c +.zero.table 0x0 0x2e828 .stack 0x1000 0x20000000 -.data 0x5bc 0x20001000 -.bss 0x9dc8 0x200015bc -.heap 0x4c78 0x2000b388 -.internal_storage 0x3a000 0x2e6cc -.zwave_nvm 0x3000 0x686cc -.nvm 0x9000 0x6b6cc +.data 0x5c8 0x20001000 +.bss 0x9e4c 0x200015c8 +.heap 0x4be8 0x2000b418 +.internal_storage 0x3a000 0x2e828 +.zwave_nvm 0x3000 0x68828 +.nvm 0x9000 0x6b828 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6fdc 0x0 -.debug_info 0x9d555a 0x0 -.debug_abbrev 0x11473 0x0 -.debug_loc 0x2823a 0x0 +.debug_frame 0x6fe8 0x0 +.debug_info 0x9d5b52 0x0 +.debug_abbrev 0x114d6 0x0 +.debug_loc 0x2825f 0x0 .debug_aranges 0x2a38 0x0 -.debug_ranges 0x52d0 0x0 -.debug_line 0x2dd1a 0x0 -.debug_str 0x6d5fb 0x0 -Total 0xb3d33f +.debug_ranges 0x52b8 0x0 +.debug_line 0x2dd6d 0x0 +.debug_str 0x6d740 0x0 +Total 0xb3dca7 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 191624 + 191984 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48004 + 48148 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4207A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4207A_REGION_US_LR_size.txt index 6bce56f79c..c411edbd4c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4207A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4207A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x2e3fc 0x0 -_cc_handlers_v3 0x21c 0x2e3fc -_zw_protocol_cmd_handlers 0x70 0x2e618 -_zw_protocol_cmd_handlers_lr 0x30 0x2e688 -.ARM.exidx 0x8 0x2e6b8 -.copy.table 0xc 0x2e6c0 -.zero.table 0x0 0x2e6cc +.text 0x2e558 0x0 +_cc_handlers_v3 0x21c 0x2e558 +_zw_protocol_cmd_handlers 0x70 0x2e774 +_zw_protocol_cmd_handlers_lr 0x30 0x2e7e4 +.ARM.exidx 0x8 0x2e814 +.copy.table 0xc 0x2e81c +.zero.table 0x0 0x2e828 .stack 0x1000 0x20000000 -.data 0x5bc 0x20001000 -.bss 0x9dc8 0x200015bc -.heap 0x4c78 0x2000b388 -.internal_storage 0x3a000 0x2e6cc -.zwave_nvm 0x3000 0x686cc -.nvm 0x9000 0x6b6cc +.data 0x5c8 0x20001000 +.bss 0x9e4c 0x200015c8 +.heap 0x4be8 0x2000b418 +.internal_storage 0x3a000 0x2e828 +.zwave_nvm 0x3000 0x68828 +.nvm 0x9000 0x6b828 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6fdc 0x0 -.debug_info 0x9d555a 0x0 -.debug_abbrev 0x11473 0x0 -.debug_loc 0x2823a 0x0 +.debug_frame 0x6fe8 0x0 +.debug_info 0x9d5b52 0x0 +.debug_abbrev 0x114d6 0x0 +.debug_loc 0x2825f 0x0 .debug_aranges 0x2a38 0x0 -.debug_ranges 0x52d0 0x0 -.debug_line 0x2dd1a 0x0 -.debug_str 0x6d5fb 0x0 -Total 0xb3d33f +.debug_ranges 0x52b8 0x0 +.debug_line 0x2dd6d 0x0 +.debug_str 0x6d740 0x0 +Total 0xb3dca7 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 191624 + 191984 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48004 + 48148 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4207A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4207A_REGION_US_size.txt index 6bce56f79c..c411edbd4c 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4207A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4207A_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x2e3fc 0x0 -_cc_handlers_v3 0x21c 0x2e3fc -_zw_protocol_cmd_handlers 0x70 0x2e618 -_zw_protocol_cmd_handlers_lr 0x30 0x2e688 -.ARM.exidx 0x8 0x2e6b8 -.copy.table 0xc 0x2e6c0 -.zero.table 0x0 0x2e6cc +.text 0x2e558 0x0 +_cc_handlers_v3 0x21c 0x2e558 +_zw_protocol_cmd_handlers 0x70 0x2e774 +_zw_protocol_cmd_handlers_lr 0x30 0x2e7e4 +.ARM.exidx 0x8 0x2e814 +.copy.table 0xc 0x2e81c +.zero.table 0x0 0x2e828 .stack 0x1000 0x20000000 -.data 0x5bc 0x20001000 -.bss 0x9dc8 0x200015bc -.heap 0x4c78 0x2000b388 -.internal_storage 0x3a000 0x2e6cc -.zwave_nvm 0x3000 0x686cc -.nvm 0x9000 0x6b6cc +.data 0x5c8 0x20001000 +.bss 0x9e4c 0x200015c8 +.heap 0x4be8 0x2000b418 +.internal_storage 0x3a000 0x2e828 +.zwave_nvm 0x3000 0x68828 +.nvm 0x9000 0x6b828 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6fdc 0x0 -.debug_info 0x9d555a 0x0 -.debug_abbrev 0x11473 0x0 -.debug_loc 0x2823a 0x0 +.debug_frame 0x6fe8 0x0 +.debug_info 0x9d5b52 0x0 +.debug_abbrev 0x114d6 0x0 +.debug_loc 0x2825f 0x0 .debug_aranges 0x2a38 0x0 -.debug_ranges 0x52d0 0x0 -.debug_line 0x2dd1a 0x0 -.debug_str 0x6d5fb 0x0 -Total 0xb3d33f +.debug_ranges 0x52b8 0x0 +.debug_line 0x2dd6d 0x0 +.debug_str 0x6d740 0x0 +Total 0xb3dca7 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 191624 + 191984 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48004 + 48148 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4209A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4209A_REGION_US_LR_size.txt index 273ed85c4c..1c84ce4da2 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4209A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_led_bulb_BRD4209A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_led_bulb.out : section size addr -.text 0x2e3b8 0x0 -_cc_handlers_v3 0x21c 0x2e3b8 -_zw_protocol_cmd_handlers 0x70 0x2e5d4 -_zw_protocol_cmd_handlers_lr 0x30 0x2e644 -.ARM.exidx 0x8 0x2e674 -.copy.table 0xc 0x2e67c -.zero.table 0x0 0x2e688 +.text 0x2e4d4 0x0 +_cc_handlers_v3 0x21c 0x2e4d4 +_zw_protocol_cmd_handlers 0x70 0x2e6f0 +_zw_protocol_cmd_handlers_lr 0x30 0x2e760 +.ARM.exidx 0x8 0x2e790 +.copy.table 0xc 0x2e798 +.zero.table 0x0 0x2e7a4 .stack 0x1000 0x20000000 -.data 0x5b8 0x20001000 -.bss 0x9da4 0x200015b8 -.heap 0x4ca0 0x2000b360 -.internal_storage 0x3a000 0x2e688 -.zwave_nvm 0x3000 0x68688 -.nvm 0x9000 0x6b688 +.data 0x5c4 0x20001000 +.bss 0x9e30 0x200015c4 +.heap 0x4c08 0x2000b3f8 +.internal_storage 0x3a000 0x2e7a4 +.zwave_nvm 0x3000 0x687a4 +.nvm 0x9000 0x6b7a4 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x720c 0x0 -.debug_info 0x9d6e2d 0x0 -.debug_abbrev 0x119dd 0x0 -.debug_loc 0x28d49 0x0 +.debug_frame 0x7218 0x0 +.debug_info 0x9d7425 0x0 +.debug_abbrev 0x11a40 0x0 +.debug_loc 0x28d6e 0x0 .debug_aranges 0x2b18 0x0 -.debug_ranges 0x54b8 0x0 -.debug_line 0x2ed97 0x0 -.debug_str 0x6d9f1 0x0 -Total 0xb415b2 +.debug_ranges 0x54a0 0x0 +.debug_line 0x2edea 0x0 +.debug_str 0x6db37 0x0 +Total 0xb41edb The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 191552 + 191848 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47964 + 48116 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2603A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2603A_REGION_EU_size.txt index 1c6a5aa473..785750bb32 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2603A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2603A_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x3824c 0x8006000 -_cc_handlers_v3 0x264 0x803e24c -_zw_protocol_cmd_handlers 0x70 0x803e4b0 -_zw_protocol_cmd_handlers_lr 0x30 0x803e520 -.ARM.exidx 0x8 0x803e550 -.copy.table 0xc 0x803e558 -.zero.table 0x0 0x803e564 +.text 0x371e8 0x8006000 +_cc_handlers_v3 0x240 0x803d1e8 +_zw_protocol_cmd_handlers 0x70 0x803d428 +_zw_protocol_cmd_handlers_lr 0x30 0x803d498 +.ARM.exidx 0x8 0x803d4c8 +.copy.table 0xc 0x803d4d0 +.zero.table 0x0 0x803d4dc .stack 0x1000 0x20000000 -.data 0x5ac 0x20001000 -.bss 0xae70 0x200015ac -.heap 0x3be0 0x2000c420 -.internal_storage 0x2a000 0x803e564 -.zwave_nvm 0x6000 0x8068564 -.nvm 0xa000 0x806e564 +.data 0x5b8 0x20001000 +.bss 0xaec4 0x200015b8 +.heap 0x3b80 0x2000c480 +.internal_storage 0x2c000 0x803d4dc +.zwave_nvm 0x6000 0x80694dc +.nvm 0x8000 0x806f4dc .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xac74 0x0 -.debug_info 0xaf4209 0x0 -.debug_abbrev 0x18820 0x0 -.debug_aranges 0x3c10 0x0 -.debug_ranges 0x7b38 0x0 -.debug_line 0x482b9 0x0 -.debug_str 0x7d4af 0x0 -.debug_loc 0x4b7b6 0x0 -Total 0xcb62e2 +.debug_frame 0xa9d0 0x0 +.debug_info 0xa8d012 0x0 +.debug_abbrev 0x17f3a 0x0 +.debug_aranges 0x3b20 0x0 +.debug_ranges 0x7850 0x0 +.debug_line 0x46b6b 0x0 +.debug_str 0x7cdc6 0x0 +.debug_loc 0x4a349 0x0 +Total 0xc49e5d The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 232208 + 227988 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52252 + 52348 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2603A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2603A_REGION_US_LR_size.txt index 1c6a5aa473..785750bb32 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2603A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2603A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x3824c 0x8006000 -_cc_handlers_v3 0x264 0x803e24c -_zw_protocol_cmd_handlers 0x70 0x803e4b0 -_zw_protocol_cmd_handlers_lr 0x30 0x803e520 -.ARM.exidx 0x8 0x803e550 -.copy.table 0xc 0x803e558 -.zero.table 0x0 0x803e564 +.text 0x371e8 0x8006000 +_cc_handlers_v3 0x240 0x803d1e8 +_zw_protocol_cmd_handlers 0x70 0x803d428 +_zw_protocol_cmd_handlers_lr 0x30 0x803d498 +.ARM.exidx 0x8 0x803d4c8 +.copy.table 0xc 0x803d4d0 +.zero.table 0x0 0x803d4dc .stack 0x1000 0x20000000 -.data 0x5ac 0x20001000 -.bss 0xae70 0x200015ac -.heap 0x3be0 0x2000c420 -.internal_storage 0x2a000 0x803e564 -.zwave_nvm 0x6000 0x8068564 -.nvm 0xa000 0x806e564 +.data 0x5b8 0x20001000 +.bss 0xaec4 0x200015b8 +.heap 0x3b80 0x2000c480 +.internal_storage 0x2c000 0x803d4dc +.zwave_nvm 0x6000 0x80694dc +.nvm 0x8000 0x806f4dc .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xac74 0x0 -.debug_info 0xaf4209 0x0 -.debug_abbrev 0x18820 0x0 -.debug_aranges 0x3c10 0x0 -.debug_ranges 0x7b38 0x0 -.debug_line 0x482b9 0x0 -.debug_str 0x7d4af 0x0 -.debug_loc 0x4b7b6 0x0 -Total 0xcb62e2 +.debug_frame 0xa9d0 0x0 +.debug_info 0xa8d012 0x0 +.debug_abbrev 0x17f3a 0x0 +.debug_aranges 0x3b20 0x0 +.debug_ranges 0x7850 0x0 +.debug_line 0x46b6b 0x0 +.debug_str 0x7cdc6 0x0 +.debug_loc 0x4a349 0x0 +Total 0xc49e5d The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 232208 + 227988 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52252 + 52348 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2603A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2603A_REGION_US_size.txt index 1c6a5aa473..785750bb32 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2603A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD2603A_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x3824c 0x8006000 -_cc_handlers_v3 0x264 0x803e24c -_zw_protocol_cmd_handlers 0x70 0x803e4b0 -_zw_protocol_cmd_handlers_lr 0x30 0x803e520 -.ARM.exidx 0x8 0x803e550 -.copy.table 0xc 0x803e558 -.zero.table 0x0 0x803e564 +.text 0x371e8 0x8006000 +_cc_handlers_v3 0x240 0x803d1e8 +_zw_protocol_cmd_handlers 0x70 0x803d428 +_zw_protocol_cmd_handlers_lr 0x30 0x803d498 +.ARM.exidx 0x8 0x803d4c8 +.copy.table 0xc 0x803d4d0 +.zero.table 0x0 0x803d4dc .stack 0x1000 0x20000000 -.data 0x5ac 0x20001000 -.bss 0xae70 0x200015ac -.heap 0x3be0 0x2000c420 -.internal_storage 0x2a000 0x803e564 -.zwave_nvm 0x6000 0x8068564 -.nvm 0xa000 0x806e564 +.data 0x5b8 0x20001000 +.bss 0xaec4 0x200015b8 +.heap 0x3b80 0x2000c480 +.internal_storage 0x2c000 0x803d4dc +.zwave_nvm 0x6000 0x80694dc +.nvm 0x8000 0x806f4dc .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xac74 0x0 -.debug_info 0xaf4209 0x0 -.debug_abbrev 0x18820 0x0 -.debug_aranges 0x3c10 0x0 -.debug_ranges 0x7b38 0x0 -.debug_line 0x482b9 0x0 -.debug_str 0x7d4af 0x0 -.debug_loc 0x4b7b6 0x0 -Total 0xcb62e2 +.debug_frame 0xa9d0 0x0 +.debug_info 0xa8d012 0x0 +.debug_abbrev 0x17f3a 0x0 +.debug_aranges 0x3b20 0x0 +.debug_ranges 0x7850 0x0 +.debug_line 0x46b6b 0x0 +.debug_str 0x7cdc6 0x0 +.debug_loc 0x4a349 0x0 +Total 0xc49e5d The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 232208 + 227988 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52252 + 52348 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4202A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4202A_REGION_EU_size.txt index 5e004bf705..de91d1ea0e 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4202A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4202A_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x2ff44 0x0 -_cc_handlers_v3 0x264 0x2ff44 -_zw_protocol_cmd_handlers 0x70 0x301a8 -_zw_protocol_cmd_handlers_lr 0x30 0x30218 -.ARM.exidx 0x8 0x30248 -.copy.table 0xc 0x30250 -.zero.table 0x0 0x3025c +.text 0x2fbb0 0x0 +_cc_handlers_v3 0x240 0x2fbb0 +_zw_protocol_cmd_handlers 0x70 0x2fdf0 +_zw_protocol_cmd_handlers_lr 0x30 0x2fe60 +.ARM.exidx 0x8 0x2fe90 +.copy.table 0xc 0x2fe98 +.zero.table 0x0 0x2fea4 .stack 0x1000 0x20000000 -.data 0x454 0x20001000 -.bss 0x9f30 0x20001454 -.heap 0x4c78 0x2000b388 -.internal_storage 0x3a000 0x3025c -.zwave_nvm 0x3000 0x6a25c -.nvm 0x9000 0x6d25c +.data 0x460 0x20001000 +.bss 0x9f7c 0x20001460 +.heap 0x4c20 0x2000b3e0 +.internal_storage 0x3a000 0x2fea4 +.zwave_nvm 0x3000 0x69ea4 +.nvm 0x9000 0x6cea4 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x7774 0x0 -.debug_info 0xaabd50 0x0 -.debug_abbrev 0x13149 0x0 -.debug_aranges 0x2d08 0x0 -.debug_ranges 0x5a20 0x0 -.debug_line 0x324ff 0x0 -.debug_str 0x71f36 0x0 -.debug_loc 0x2cfb3 0x0 -Total 0xc263ec +.debug_frame 0x7550 0x0 +.debug_info 0xa454d6 0x0 +.debug_abbrev 0x12ad6 0x0 +.debug_aranges 0x2c50 0x0 +.debug_ranges 0x5888 0x0 +.debug_line 0x3138b 0x0 +.debug_str 0x71929 0x0 +.debug_loc 0x2c026 0x0 +Total 0xbbc5c5 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 198320 + 197380 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48004 + 48092 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4202A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4202A_REGION_US_LR_size.txt index 5e004bf705..de91d1ea0e 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4202A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4202A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x2ff44 0x0 -_cc_handlers_v3 0x264 0x2ff44 -_zw_protocol_cmd_handlers 0x70 0x301a8 -_zw_protocol_cmd_handlers_lr 0x30 0x30218 -.ARM.exidx 0x8 0x30248 -.copy.table 0xc 0x30250 -.zero.table 0x0 0x3025c +.text 0x2fbb0 0x0 +_cc_handlers_v3 0x240 0x2fbb0 +_zw_protocol_cmd_handlers 0x70 0x2fdf0 +_zw_protocol_cmd_handlers_lr 0x30 0x2fe60 +.ARM.exidx 0x8 0x2fe90 +.copy.table 0xc 0x2fe98 +.zero.table 0x0 0x2fea4 .stack 0x1000 0x20000000 -.data 0x454 0x20001000 -.bss 0x9f30 0x20001454 -.heap 0x4c78 0x2000b388 -.internal_storage 0x3a000 0x3025c -.zwave_nvm 0x3000 0x6a25c -.nvm 0x9000 0x6d25c +.data 0x460 0x20001000 +.bss 0x9f7c 0x20001460 +.heap 0x4c20 0x2000b3e0 +.internal_storage 0x3a000 0x2fea4 +.zwave_nvm 0x3000 0x69ea4 +.nvm 0x9000 0x6cea4 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x7774 0x0 -.debug_info 0xaabd50 0x0 -.debug_abbrev 0x13149 0x0 -.debug_aranges 0x2d08 0x0 -.debug_ranges 0x5a20 0x0 -.debug_line 0x324ff 0x0 -.debug_str 0x71f36 0x0 -.debug_loc 0x2cfb3 0x0 -Total 0xc263ec +.debug_frame 0x7550 0x0 +.debug_info 0xa454d6 0x0 +.debug_abbrev 0x12ad6 0x0 +.debug_aranges 0x2c50 0x0 +.debug_ranges 0x5888 0x0 +.debug_line 0x3138b 0x0 +.debug_str 0x71929 0x0 +.debug_loc 0x2c026 0x0 +Total 0xbbc5c5 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 198320 + 197380 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48004 + 48092 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4202A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4202A_REGION_US_size.txt index 5e004bf705..de91d1ea0e 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4202A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4202A_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x2ff44 0x0 -_cc_handlers_v3 0x264 0x2ff44 -_zw_protocol_cmd_handlers 0x70 0x301a8 -_zw_protocol_cmd_handlers_lr 0x30 0x30218 -.ARM.exidx 0x8 0x30248 -.copy.table 0xc 0x30250 -.zero.table 0x0 0x3025c +.text 0x2fbb0 0x0 +_cc_handlers_v3 0x240 0x2fbb0 +_zw_protocol_cmd_handlers 0x70 0x2fdf0 +_zw_protocol_cmd_handlers_lr 0x30 0x2fe60 +.ARM.exidx 0x8 0x2fe90 +.copy.table 0xc 0x2fe98 +.zero.table 0x0 0x2fea4 .stack 0x1000 0x20000000 -.data 0x454 0x20001000 -.bss 0x9f30 0x20001454 -.heap 0x4c78 0x2000b388 -.internal_storage 0x3a000 0x3025c -.zwave_nvm 0x3000 0x6a25c -.nvm 0x9000 0x6d25c +.data 0x460 0x20001000 +.bss 0x9f7c 0x20001460 +.heap 0x4c20 0x2000b3e0 +.internal_storage 0x3a000 0x2fea4 +.zwave_nvm 0x3000 0x69ea4 +.nvm 0x9000 0x6cea4 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x7774 0x0 -.debug_info 0xaabd50 0x0 -.debug_abbrev 0x13149 0x0 -.debug_aranges 0x2d08 0x0 -.debug_ranges 0x5a20 0x0 -.debug_line 0x324ff 0x0 -.debug_str 0x71f36 0x0 -.debug_loc 0x2cfb3 0x0 -Total 0xc263ec +.debug_frame 0x7550 0x0 +.debug_info 0xa454d6 0x0 +.debug_abbrev 0x12ad6 0x0 +.debug_aranges 0x2c50 0x0 +.debug_ranges 0x5888 0x0 +.debug_line 0x3138b 0x0 +.debug_str 0x71929 0x0 +.debug_loc 0x2c026 0x0 +Total 0xbbc5c5 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 198320 + 197380 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48004 + 48092 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204C_REGION_EU_size.txt index a7de7321b8..ea4ac1b00d 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204C_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x37d1c 0x8006000 -_cc_handlers_v3 0x264 0x803dd1c -_zw_protocol_cmd_handlers 0x70 0x803df80 -_zw_protocol_cmd_handlers_lr 0x30 0x803dff0 -.ARM.exidx 0x8 0x803e020 -.copy.table 0xc 0x803e028 -.zero.table 0x0 0x803e034 +.text 0x36c98 0x8006000 +_cc_handlers_v3 0x240 0x803cc98 +_zw_protocol_cmd_handlers 0x70 0x803ced8 +_zw_protocol_cmd_handlers_lr 0x30 0x803cf48 +.ARM.exidx 0x8 0x803cf78 +.copy.table 0xc 0x803cf80 +.zero.table 0x0 0x803cf8c .stack 0x1000 0x20000000 -.data 0x5a8 0x20001000 -.bss 0xae54 0x200015a8 -.heap 0x3c00 0x2000c400 -.internal_storage 0x2a000 0x803e034 -.zwave_nvm 0x6000 0x8068034 -.nvm 0xa000 0x806e034 +.data 0x5b4 0x20001000 +.bss 0xaea0 0x200015b4 +.heap 0x3ba8 0x2000c458 +.internal_storage 0x2c000 0x803cf8c +.zwave_nvm 0x6000 0x8068f8c +.nvm 0x8000 0x806ef8c .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xad6c 0x0 -.debug_info 0xaf5d59 0x0 -.debug_abbrev 0x18aa3 0x0 -.debug_aranges 0x3c58 0x0 -.debug_ranges 0x7bd0 0x0 -.debug_line 0x48a7b 0x0 -.debug_str 0x7cea9 0x0 -.debug_loc 0x4bb99 0x0 -Total 0xcb82fc +.debug_frame 0xaac8 0x0 +.debug_info 0xa8eb62 0x0 +.debug_abbrev 0x181bd 0x0 +.debug_aranges 0x3b68 0x0 +.debug_ranges 0x78e8 0x0 +.debug_line 0x4732d 0x0 +.debug_str 0x7c7c1 0x0 +.debug_loc 0x4a729 0x0 +Total 0xc4be55 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 230876 + 226624 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52220 + 52308 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204C_REGION_US_LR_size.txt index a7de7321b8..ea4ac1b00d 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204C_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x37d1c 0x8006000 -_cc_handlers_v3 0x264 0x803dd1c -_zw_protocol_cmd_handlers 0x70 0x803df80 -_zw_protocol_cmd_handlers_lr 0x30 0x803dff0 -.ARM.exidx 0x8 0x803e020 -.copy.table 0xc 0x803e028 -.zero.table 0x0 0x803e034 +.text 0x36c98 0x8006000 +_cc_handlers_v3 0x240 0x803cc98 +_zw_protocol_cmd_handlers 0x70 0x803ced8 +_zw_protocol_cmd_handlers_lr 0x30 0x803cf48 +.ARM.exidx 0x8 0x803cf78 +.copy.table 0xc 0x803cf80 +.zero.table 0x0 0x803cf8c .stack 0x1000 0x20000000 -.data 0x5a8 0x20001000 -.bss 0xae54 0x200015a8 -.heap 0x3c00 0x2000c400 -.internal_storage 0x2a000 0x803e034 -.zwave_nvm 0x6000 0x8068034 -.nvm 0xa000 0x806e034 +.data 0x5b4 0x20001000 +.bss 0xaea0 0x200015b4 +.heap 0x3ba8 0x2000c458 +.internal_storage 0x2c000 0x803cf8c +.zwave_nvm 0x6000 0x8068f8c +.nvm 0x8000 0x806ef8c .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xad6c 0x0 -.debug_info 0xaf5d59 0x0 -.debug_abbrev 0x18aa3 0x0 -.debug_aranges 0x3c58 0x0 -.debug_ranges 0x7bd0 0x0 -.debug_line 0x48a7b 0x0 -.debug_str 0x7cea9 0x0 -.debug_loc 0x4bb99 0x0 -Total 0xcb82fc +.debug_frame 0xaac8 0x0 +.debug_info 0xa8eb62 0x0 +.debug_abbrev 0x181bd 0x0 +.debug_aranges 0x3b68 0x0 +.debug_ranges 0x78e8 0x0 +.debug_line 0x4732d 0x0 +.debug_str 0x7c7c1 0x0 +.debug_loc 0x4a729 0x0 +Total 0xc4be55 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 230876 + 226624 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52220 + 52308 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204C_REGION_US_size.txt index a7de7321b8..ea4ac1b00d 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204C_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x37d1c 0x8006000 -_cc_handlers_v3 0x264 0x803dd1c -_zw_protocol_cmd_handlers 0x70 0x803df80 -_zw_protocol_cmd_handlers_lr 0x30 0x803dff0 -.ARM.exidx 0x8 0x803e020 -.copy.table 0xc 0x803e028 -.zero.table 0x0 0x803e034 +.text 0x36c98 0x8006000 +_cc_handlers_v3 0x240 0x803cc98 +_zw_protocol_cmd_handlers 0x70 0x803ced8 +_zw_protocol_cmd_handlers_lr 0x30 0x803cf48 +.ARM.exidx 0x8 0x803cf78 +.copy.table 0xc 0x803cf80 +.zero.table 0x0 0x803cf8c .stack 0x1000 0x20000000 -.data 0x5a8 0x20001000 -.bss 0xae54 0x200015a8 -.heap 0x3c00 0x2000c400 -.internal_storage 0x2a000 0x803e034 -.zwave_nvm 0x6000 0x8068034 -.nvm 0xa000 0x806e034 +.data 0x5b4 0x20001000 +.bss 0xaea0 0x200015b4 +.heap 0x3ba8 0x2000c458 +.internal_storage 0x2c000 0x803cf8c +.zwave_nvm 0x6000 0x8068f8c +.nvm 0x8000 0x806ef8c .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xad6c 0x0 -.debug_info 0xaf5d59 0x0 -.debug_abbrev 0x18aa3 0x0 -.debug_aranges 0x3c58 0x0 -.debug_ranges 0x7bd0 0x0 -.debug_line 0x48a7b 0x0 -.debug_str 0x7cea9 0x0 -.debug_loc 0x4bb99 0x0 -Total 0xcb82fc +.debug_frame 0xaac8 0x0 +.debug_info 0xa8eb62 0x0 +.debug_abbrev 0x181bd 0x0 +.debug_aranges 0x3b68 0x0 +.debug_ranges 0x78e8 0x0 +.debug_line 0x4732d 0x0 +.debug_str 0x7c7c1 0x0 +.debug_loc 0x4a729 0x0 +Total 0xc4be55 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 230876 + 226624 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52220 + 52308 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204D_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204D_REGION_EU_size.txt index 7256986794..36885e0407 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204D_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204D_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x37de8 0x8006000 -_cc_handlers_v3 0x264 0x803dde8 -_zw_protocol_cmd_handlers 0x70 0x803e04c -_zw_protocol_cmd_handlers_lr 0x30 0x803e0bc -.ARM.exidx 0x8 0x803e0ec -.copy.table 0xc 0x803e0f4 -.zero.table 0x0 0x803e100 +.text 0x36d74 0x8006000 +_cc_handlers_v3 0x240 0x803cd74 +_zw_protocol_cmd_handlers 0x70 0x803cfb4 +_zw_protocol_cmd_handlers_lr 0x30 0x803d024 +.ARM.exidx 0x8 0x803d054 +.copy.table 0xc 0x803d05c +.zero.table 0x0 0x803d068 .stack 0x1000 0x20000000 -.data 0x5ac 0x20001000 -.bss 0xae50 0x200015ac -.heap 0x3c00 0x2000c400 -.internal_storage 0x2a000 0x803e100 -.zwave_nvm 0x6000 0x8068100 -.nvm 0xa000 0x806e100 +.data 0x5b8 0x20001000 +.bss 0xaea4 0x200015b8 +.heap 0x3ba0 0x2000c460 +.internal_storage 0x2c000 0x803d068 +.zwave_nvm 0x6000 0x8069068 +.nvm 0x8000 0x806f068 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xad9c 0x0 -.debug_info 0xaf5fbc 0x0 -.debug_abbrev 0x18b8f 0x0 -.debug_aranges 0x3c78 0x0 -.debug_ranges 0x7be0 0x0 -.debug_line 0x48c61 0x0 -.debug_str 0x7d07c 0x0 -.debug_loc 0x4bb99 0x0 -Total 0xcb8b30 +.debug_frame 0xaaf8 0x0 +.debug_info 0xa8edc5 0x0 +.debug_abbrev 0x182a9 0x0 +.debug_aranges 0x3b88 0x0 +.debug_ranges 0x78f8 0x0 +.debug_line 0x47513 0x0 +.debug_str 0x7c994 0x0 +.debug_loc 0x4a729 0x0 +Total 0xc4c699 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 231084 + 226848 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52220 + 52316 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204D_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204D_REGION_US_LR_size.txt index 7256986794..36885e0407 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204D_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204D_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x37de8 0x8006000 -_cc_handlers_v3 0x264 0x803dde8 -_zw_protocol_cmd_handlers 0x70 0x803e04c -_zw_protocol_cmd_handlers_lr 0x30 0x803e0bc -.ARM.exidx 0x8 0x803e0ec -.copy.table 0xc 0x803e0f4 -.zero.table 0x0 0x803e100 +.text 0x36d74 0x8006000 +_cc_handlers_v3 0x240 0x803cd74 +_zw_protocol_cmd_handlers 0x70 0x803cfb4 +_zw_protocol_cmd_handlers_lr 0x30 0x803d024 +.ARM.exidx 0x8 0x803d054 +.copy.table 0xc 0x803d05c +.zero.table 0x0 0x803d068 .stack 0x1000 0x20000000 -.data 0x5ac 0x20001000 -.bss 0xae50 0x200015ac -.heap 0x3c00 0x2000c400 -.internal_storage 0x2a000 0x803e100 -.zwave_nvm 0x6000 0x8068100 -.nvm 0xa000 0x806e100 +.data 0x5b8 0x20001000 +.bss 0xaea4 0x200015b8 +.heap 0x3ba0 0x2000c460 +.internal_storage 0x2c000 0x803d068 +.zwave_nvm 0x6000 0x8069068 +.nvm 0x8000 0x806f068 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xad9c 0x0 -.debug_info 0xaf5fbc 0x0 -.debug_abbrev 0x18b8f 0x0 -.debug_aranges 0x3c78 0x0 -.debug_ranges 0x7be0 0x0 -.debug_line 0x48c61 0x0 -.debug_str 0x7d07c 0x0 -.debug_loc 0x4bb99 0x0 -Total 0xcb8b30 +.debug_frame 0xaaf8 0x0 +.debug_info 0xa8edc5 0x0 +.debug_abbrev 0x182a9 0x0 +.debug_aranges 0x3b88 0x0 +.debug_ranges 0x78f8 0x0 +.debug_line 0x47513 0x0 +.debug_str 0x7c994 0x0 +.debug_loc 0x4a729 0x0 +Total 0xc4c699 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 231084 + 226848 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52220 + 52316 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204D_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204D_REGION_US_size.txt index 7256986794..36885e0407 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204D_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4204D_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x37de8 0x8006000 -_cc_handlers_v3 0x264 0x803dde8 -_zw_protocol_cmd_handlers 0x70 0x803e04c -_zw_protocol_cmd_handlers_lr 0x30 0x803e0bc -.ARM.exidx 0x8 0x803e0ec -.copy.table 0xc 0x803e0f4 -.zero.table 0x0 0x803e100 +.text 0x36d74 0x8006000 +_cc_handlers_v3 0x240 0x803cd74 +_zw_protocol_cmd_handlers 0x70 0x803cfb4 +_zw_protocol_cmd_handlers_lr 0x30 0x803d024 +.ARM.exidx 0x8 0x803d054 +.copy.table 0xc 0x803d05c +.zero.table 0x0 0x803d068 .stack 0x1000 0x20000000 -.data 0x5ac 0x20001000 -.bss 0xae50 0x200015ac -.heap 0x3c00 0x2000c400 -.internal_storage 0x2a000 0x803e100 -.zwave_nvm 0x6000 0x8068100 -.nvm 0xa000 0x806e100 +.data 0x5b8 0x20001000 +.bss 0xaea4 0x200015b8 +.heap 0x3ba0 0x2000c460 +.internal_storage 0x2c000 0x803d068 +.zwave_nvm 0x6000 0x8069068 +.nvm 0x8000 0x806f068 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xad9c 0x0 -.debug_info 0xaf5fbc 0x0 -.debug_abbrev 0x18b8f 0x0 -.debug_aranges 0x3c78 0x0 -.debug_ranges 0x7be0 0x0 -.debug_line 0x48c61 0x0 -.debug_str 0x7d07c 0x0 -.debug_loc 0x4bb99 0x0 -Total 0xcb8b30 +.debug_frame 0xaaf8 0x0 +.debug_info 0xa8edc5 0x0 +.debug_abbrev 0x182a9 0x0 +.debug_aranges 0x3b88 0x0 +.debug_ranges 0x78f8 0x0 +.debug_line 0x47513 0x0 +.debug_str 0x7c994 0x0 +.debug_loc 0x4a729 0x0 +Total 0xc4c699 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 231084 + 226848 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52220 + 52316 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205A_REGION_EU_size.txt index d8afb04329..09f2f75961 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205A_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x37f28 0x8006000 -_cc_handlers_v3 0x264 0x803df28 -_zw_protocol_cmd_handlers 0x70 0x803e18c -_zw_protocol_cmd_handlers_lr 0x30 0x803e1fc -.ARM.exidx 0x8 0x803e22c -.copy.table 0xc 0x803e234 -.zero.table 0x0 0x803e240 +.text 0x36c2c 0x8006000 +_cc_handlers_v3 0x240 0x803cc2c +_zw_protocol_cmd_handlers 0x70 0x803ce6c +_zw_protocol_cmd_handlers_lr 0x30 0x803cedc +.ARM.exidx 0x8 0x803cf0c +.copy.table 0xc 0x803cf14 +.zero.table 0x0 0x803cf20 .stack 0x1000 0x20000000 -.data 0x5a8 0x20001000 -.bss 0xad3c 0x200015a8 -.heap 0x3d18 0x2000c2e8 -.internal_storage 0x2a000 0x803e240 -.zwave_nvm 0x6000 0x8068240 -.nvm 0xa000 0x806e240 +.data 0x5b4 0x20001000 +.bss 0xad90 0x200015b4 +.heap 0x3cb8 0x2000c348 +.internal_storage 0x2c000 0x803cf20 +.zwave_nvm 0x6000 0x8068f20 +.nvm 0x8000 0x806ef20 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xab5c 0x0 -.debug_info 0xaf45ac 0x0 -.debug_abbrev 0x18e9f 0x0 -.debug_aranges 0x3c58 0x0 -.debug_ranges 0x7ab0 0x0 -.debug_line 0x478ad 0x0 -.debug_str 0x7d403 0x0 -.debug_loc 0x49e5b 0x0 -Total 0xcb4475 +.debug_frame 0xa530 0x0 +.debug_info 0xa8afab 0x0 +.debug_abbrev 0x17f2d 0x0 +.debug_aranges 0x3a88 0x0 +.debug_ranges 0x76b8 0x0 +.debug_line 0x44f91 0x0 +.debug_str 0x7c76f 0x0 +.debug_loc 0x4607b 0x0 +Total 0xc40c5e The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 231400 + 226516 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51940 + 52036 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205A_REGION_US_LR_size.txt index d8afb04329..09f2f75961 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x37f28 0x8006000 -_cc_handlers_v3 0x264 0x803df28 -_zw_protocol_cmd_handlers 0x70 0x803e18c -_zw_protocol_cmd_handlers_lr 0x30 0x803e1fc -.ARM.exidx 0x8 0x803e22c -.copy.table 0xc 0x803e234 -.zero.table 0x0 0x803e240 +.text 0x36c2c 0x8006000 +_cc_handlers_v3 0x240 0x803cc2c +_zw_protocol_cmd_handlers 0x70 0x803ce6c +_zw_protocol_cmd_handlers_lr 0x30 0x803cedc +.ARM.exidx 0x8 0x803cf0c +.copy.table 0xc 0x803cf14 +.zero.table 0x0 0x803cf20 .stack 0x1000 0x20000000 -.data 0x5a8 0x20001000 -.bss 0xad3c 0x200015a8 -.heap 0x3d18 0x2000c2e8 -.internal_storage 0x2a000 0x803e240 -.zwave_nvm 0x6000 0x8068240 -.nvm 0xa000 0x806e240 +.data 0x5b4 0x20001000 +.bss 0xad90 0x200015b4 +.heap 0x3cb8 0x2000c348 +.internal_storage 0x2c000 0x803cf20 +.zwave_nvm 0x6000 0x8068f20 +.nvm 0x8000 0x806ef20 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xab5c 0x0 -.debug_info 0xaf45ac 0x0 -.debug_abbrev 0x18e9f 0x0 -.debug_aranges 0x3c58 0x0 -.debug_ranges 0x7ab0 0x0 -.debug_line 0x478ad 0x0 -.debug_str 0x7d403 0x0 -.debug_loc 0x49e5b 0x0 -Total 0xcb4475 +.debug_frame 0xa530 0x0 +.debug_info 0xa8afab 0x0 +.debug_abbrev 0x17f2d 0x0 +.debug_aranges 0x3a88 0x0 +.debug_ranges 0x76b8 0x0 +.debug_line 0x44f91 0x0 +.debug_str 0x7c76f 0x0 +.debug_loc 0x4607b 0x0 +Total 0xc40c5e The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 231400 + 226516 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51940 + 52036 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205A_REGION_US_size.txt index d8afb04329..09f2f75961 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205A_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x37f28 0x8006000 -_cc_handlers_v3 0x264 0x803df28 -_zw_protocol_cmd_handlers 0x70 0x803e18c -_zw_protocol_cmd_handlers_lr 0x30 0x803e1fc -.ARM.exidx 0x8 0x803e22c -.copy.table 0xc 0x803e234 -.zero.table 0x0 0x803e240 +.text 0x36c2c 0x8006000 +_cc_handlers_v3 0x240 0x803cc2c +_zw_protocol_cmd_handlers 0x70 0x803ce6c +_zw_protocol_cmd_handlers_lr 0x30 0x803cedc +.ARM.exidx 0x8 0x803cf0c +.copy.table 0xc 0x803cf14 +.zero.table 0x0 0x803cf20 .stack 0x1000 0x20000000 -.data 0x5a8 0x20001000 -.bss 0xad3c 0x200015a8 -.heap 0x3d18 0x2000c2e8 -.internal_storage 0x2a000 0x803e240 -.zwave_nvm 0x6000 0x8068240 -.nvm 0xa000 0x806e240 +.data 0x5b4 0x20001000 +.bss 0xad90 0x200015b4 +.heap 0x3cb8 0x2000c348 +.internal_storage 0x2c000 0x803cf20 +.zwave_nvm 0x6000 0x8068f20 +.nvm 0x8000 0x806ef20 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xab5c 0x0 -.debug_info 0xaf45ac 0x0 -.debug_abbrev 0x18e9f 0x0 -.debug_aranges 0x3c58 0x0 -.debug_ranges 0x7ab0 0x0 -.debug_line 0x478ad 0x0 -.debug_str 0x7d403 0x0 -.debug_loc 0x49e5b 0x0 -Total 0xcb4475 +.debug_frame 0xa530 0x0 +.debug_info 0xa8afab 0x0 +.debug_abbrev 0x17f2d 0x0 +.debug_aranges 0x3a88 0x0 +.debug_ranges 0x76b8 0x0 +.debug_line 0x44f91 0x0 +.debug_str 0x7c76f 0x0 +.debug_loc 0x4607b 0x0 +Total 0xc40c5e The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 231400 + 226516 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51940 + 52036 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205B_REGION_EU_size.txt index 3f9986615e..96b44e7d65 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205B_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x38278 0x8006000 -_cc_handlers_v3 0x264 0x803e278 -_zw_protocol_cmd_handlers 0x70 0x803e4dc -_zw_protocol_cmd_handlers_lr 0x30 0x803e54c -.ARM.exidx 0x8 0x803e57c -.copy.table 0xc 0x803e584 -.zero.table 0x0 0x803e590 +.text 0x371f4 0x8006000 +_cc_handlers_v3 0x240 0x803d1f4 +_zw_protocol_cmd_handlers 0x70 0x803d434 +_zw_protocol_cmd_handlers_lr 0x30 0x803d4a4 +.ARM.exidx 0x8 0x803d4d4 +.copy.table 0xc 0x803d4dc +.zero.table 0x0 0x803d4e8 .stack 0x1000 0x20000000 -.data 0x5a8 0x20001000 -.bss 0xae74 0x200015a8 -.heap 0x3be0 0x2000c420 -.internal_storage 0x2a000 0x803e590 -.zwave_nvm 0x6000 0x8068590 -.nvm 0xa000 0x806e590 +.data 0x5b4 0x20001000 +.bss 0xaec0 0x200015b4 +.heap 0x3b88 0x2000c478 +.internal_storage 0x2c000 0x803d4e8 +.zwave_nvm 0x6000 0x80694e8 +.nvm 0x8000 0x806f4e8 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xad6c 0x0 -.debug_info 0xaf67d4 0x0 -.debug_abbrev 0x18be8 0x0 -.debug_aranges 0x3c88 0x0 -.debug_ranges 0x7bd0 0x0 -.debug_line 0x48a59 0x0 -.debug_str 0x7d756 0x0 -.debug_loc 0x4bb86 0x0 -Total 0xcb9cc0 +.debug_frame 0xaac8 0x0 +.debug_info 0xa8f5dd 0x0 +.debug_abbrev 0x18302 0x0 +.debug_aranges 0x3b98 0x0 +.debug_ranges 0x78e8 0x0 +.debug_line 0x4730b 0x0 +.debug_str 0x7d06d 0x0 +.debug_loc 0x4a719 0x0 +Total 0xc4d81b The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 232248 + 227996 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52252 + 52340 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205B_REGION_US_LR_size.txt index 3f9986615e..96b44e7d65 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205B_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x38278 0x8006000 -_cc_handlers_v3 0x264 0x803e278 -_zw_protocol_cmd_handlers 0x70 0x803e4dc -_zw_protocol_cmd_handlers_lr 0x30 0x803e54c -.ARM.exidx 0x8 0x803e57c -.copy.table 0xc 0x803e584 -.zero.table 0x0 0x803e590 +.text 0x371f4 0x8006000 +_cc_handlers_v3 0x240 0x803d1f4 +_zw_protocol_cmd_handlers 0x70 0x803d434 +_zw_protocol_cmd_handlers_lr 0x30 0x803d4a4 +.ARM.exidx 0x8 0x803d4d4 +.copy.table 0xc 0x803d4dc +.zero.table 0x0 0x803d4e8 .stack 0x1000 0x20000000 -.data 0x5a8 0x20001000 -.bss 0xae74 0x200015a8 -.heap 0x3be0 0x2000c420 -.internal_storage 0x2a000 0x803e590 -.zwave_nvm 0x6000 0x8068590 -.nvm 0xa000 0x806e590 +.data 0x5b4 0x20001000 +.bss 0xaec0 0x200015b4 +.heap 0x3b88 0x2000c478 +.internal_storage 0x2c000 0x803d4e8 +.zwave_nvm 0x6000 0x80694e8 +.nvm 0x8000 0x806f4e8 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xad6c 0x0 -.debug_info 0xaf67d4 0x0 -.debug_abbrev 0x18be8 0x0 -.debug_aranges 0x3c88 0x0 -.debug_ranges 0x7bd0 0x0 -.debug_line 0x48a59 0x0 -.debug_str 0x7d756 0x0 -.debug_loc 0x4bb86 0x0 -Total 0xcb9cc0 +.debug_frame 0xaac8 0x0 +.debug_info 0xa8f5dd 0x0 +.debug_abbrev 0x18302 0x0 +.debug_aranges 0x3b98 0x0 +.debug_ranges 0x78e8 0x0 +.debug_line 0x4730b 0x0 +.debug_str 0x7d06d 0x0 +.debug_loc 0x4a719 0x0 +Total 0xc4d81b The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 232248 + 227996 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52252 + 52340 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205B_REGION_US_size.txt index 3f9986615e..96b44e7d65 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4205B_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x38278 0x8006000 -_cc_handlers_v3 0x264 0x803e278 -_zw_protocol_cmd_handlers 0x70 0x803e4dc -_zw_protocol_cmd_handlers_lr 0x30 0x803e54c -.ARM.exidx 0x8 0x803e57c -.copy.table 0xc 0x803e584 -.zero.table 0x0 0x803e590 +.text 0x371f4 0x8006000 +_cc_handlers_v3 0x240 0x803d1f4 +_zw_protocol_cmd_handlers 0x70 0x803d434 +_zw_protocol_cmd_handlers_lr 0x30 0x803d4a4 +.ARM.exidx 0x8 0x803d4d4 +.copy.table 0xc 0x803d4dc +.zero.table 0x0 0x803d4e8 .stack 0x1000 0x20000000 -.data 0x5a8 0x20001000 -.bss 0xae74 0x200015a8 -.heap 0x3be0 0x2000c420 -.internal_storage 0x2a000 0x803e590 -.zwave_nvm 0x6000 0x8068590 -.nvm 0xa000 0x806e590 +.data 0x5b4 0x20001000 +.bss 0xaec0 0x200015b4 +.heap 0x3b88 0x2000c478 +.internal_storage 0x2c000 0x803d4e8 +.zwave_nvm 0x6000 0x80694e8 +.nvm 0x8000 0x806f4e8 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xad6c 0x0 -.debug_info 0xaf67d4 0x0 -.debug_abbrev 0x18be8 0x0 -.debug_aranges 0x3c88 0x0 -.debug_ranges 0x7bd0 0x0 -.debug_line 0x48a59 0x0 -.debug_str 0x7d756 0x0 -.debug_loc 0x4bb86 0x0 -Total 0xcb9cc0 +.debug_frame 0xaac8 0x0 +.debug_info 0xa8f5dd 0x0 +.debug_abbrev 0x18302 0x0 +.debug_aranges 0x3b98 0x0 +.debug_ranges 0x78e8 0x0 +.debug_line 0x4730b 0x0 +.debug_str 0x7d06d 0x0 +.debug_loc 0x4a719 0x0 +Total 0xc4d81b The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 232248 + 227996 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52252 + 52340 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4207A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4207A_REGION_EU_size.txt index 5e004bf705..de91d1ea0e 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4207A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4207A_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x2ff44 0x0 -_cc_handlers_v3 0x264 0x2ff44 -_zw_protocol_cmd_handlers 0x70 0x301a8 -_zw_protocol_cmd_handlers_lr 0x30 0x30218 -.ARM.exidx 0x8 0x30248 -.copy.table 0xc 0x30250 -.zero.table 0x0 0x3025c +.text 0x2fbb0 0x0 +_cc_handlers_v3 0x240 0x2fbb0 +_zw_protocol_cmd_handlers 0x70 0x2fdf0 +_zw_protocol_cmd_handlers_lr 0x30 0x2fe60 +.ARM.exidx 0x8 0x2fe90 +.copy.table 0xc 0x2fe98 +.zero.table 0x0 0x2fea4 .stack 0x1000 0x20000000 -.data 0x454 0x20001000 -.bss 0x9f30 0x20001454 -.heap 0x4c78 0x2000b388 -.internal_storage 0x3a000 0x3025c -.zwave_nvm 0x3000 0x6a25c -.nvm 0x9000 0x6d25c +.data 0x460 0x20001000 +.bss 0x9f7c 0x20001460 +.heap 0x4c20 0x2000b3e0 +.internal_storage 0x3a000 0x2fea4 +.zwave_nvm 0x3000 0x69ea4 +.nvm 0x9000 0x6cea4 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x7774 0x0 -.debug_info 0xaabd50 0x0 -.debug_abbrev 0x13149 0x0 -.debug_aranges 0x2d08 0x0 -.debug_ranges 0x5a20 0x0 -.debug_line 0x324ff 0x0 -.debug_str 0x71f36 0x0 -.debug_loc 0x2cfb3 0x0 -Total 0xc263ec +.debug_frame 0x7550 0x0 +.debug_info 0xa454d6 0x0 +.debug_abbrev 0x12ad6 0x0 +.debug_aranges 0x2c50 0x0 +.debug_ranges 0x5888 0x0 +.debug_line 0x3138b 0x0 +.debug_str 0x71929 0x0 +.debug_loc 0x2c026 0x0 +Total 0xbbc5c5 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 198320 + 197380 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48004 + 48092 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4207A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4207A_REGION_US_LR_size.txt index 5e004bf705..de91d1ea0e 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4207A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4207A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x2ff44 0x0 -_cc_handlers_v3 0x264 0x2ff44 -_zw_protocol_cmd_handlers 0x70 0x301a8 -_zw_protocol_cmd_handlers_lr 0x30 0x30218 -.ARM.exidx 0x8 0x30248 -.copy.table 0xc 0x30250 -.zero.table 0x0 0x3025c +.text 0x2fbb0 0x0 +_cc_handlers_v3 0x240 0x2fbb0 +_zw_protocol_cmd_handlers 0x70 0x2fdf0 +_zw_protocol_cmd_handlers_lr 0x30 0x2fe60 +.ARM.exidx 0x8 0x2fe90 +.copy.table 0xc 0x2fe98 +.zero.table 0x0 0x2fea4 .stack 0x1000 0x20000000 -.data 0x454 0x20001000 -.bss 0x9f30 0x20001454 -.heap 0x4c78 0x2000b388 -.internal_storage 0x3a000 0x3025c -.zwave_nvm 0x3000 0x6a25c -.nvm 0x9000 0x6d25c +.data 0x460 0x20001000 +.bss 0x9f7c 0x20001460 +.heap 0x4c20 0x2000b3e0 +.internal_storage 0x3a000 0x2fea4 +.zwave_nvm 0x3000 0x69ea4 +.nvm 0x9000 0x6cea4 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x7774 0x0 -.debug_info 0xaabd50 0x0 -.debug_abbrev 0x13149 0x0 -.debug_aranges 0x2d08 0x0 -.debug_ranges 0x5a20 0x0 -.debug_line 0x324ff 0x0 -.debug_str 0x71f36 0x0 -.debug_loc 0x2cfb3 0x0 -Total 0xc263ec +.debug_frame 0x7550 0x0 +.debug_info 0xa454d6 0x0 +.debug_abbrev 0x12ad6 0x0 +.debug_aranges 0x2c50 0x0 +.debug_ranges 0x5888 0x0 +.debug_line 0x3138b 0x0 +.debug_str 0x71929 0x0 +.debug_loc 0x2c026 0x0 +Total 0xbbc5c5 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 198320 + 197380 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48004 + 48092 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4207A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4207A_REGION_US_size.txt index 5e004bf705..de91d1ea0e 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4207A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4207A_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x2ff44 0x0 -_cc_handlers_v3 0x264 0x2ff44 -_zw_protocol_cmd_handlers 0x70 0x301a8 -_zw_protocol_cmd_handlers_lr 0x30 0x30218 -.ARM.exidx 0x8 0x30248 -.copy.table 0xc 0x30250 -.zero.table 0x0 0x3025c +.text 0x2fbb0 0x0 +_cc_handlers_v3 0x240 0x2fbb0 +_zw_protocol_cmd_handlers 0x70 0x2fdf0 +_zw_protocol_cmd_handlers_lr 0x30 0x2fe60 +.ARM.exidx 0x8 0x2fe90 +.copy.table 0xc 0x2fe98 +.zero.table 0x0 0x2fea4 .stack 0x1000 0x20000000 -.data 0x454 0x20001000 -.bss 0x9f30 0x20001454 -.heap 0x4c78 0x2000b388 -.internal_storage 0x3a000 0x3025c -.zwave_nvm 0x3000 0x6a25c -.nvm 0x9000 0x6d25c +.data 0x460 0x20001000 +.bss 0x9f7c 0x20001460 +.heap 0x4c20 0x2000b3e0 +.internal_storage 0x3a000 0x2fea4 +.zwave_nvm 0x3000 0x69ea4 +.nvm 0x9000 0x6cea4 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x7774 0x0 -.debug_info 0xaabd50 0x0 -.debug_abbrev 0x13149 0x0 -.debug_aranges 0x2d08 0x0 -.debug_ranges 0x5a20 0x0 -.debug_line 0x324ff 0x0 -.debug_str 0x71f36 0x0 -.debug_loc 0x2cfb3 0x0 -Total 0xc263ec +.debug_frame 0x7550 0x0 +.debug_info 0xa454d6 0x0 +.debug_abbrev 0x12ad6 0x0 +.debug_aranges 0x2c50 0x0 +.debug_ranges 0x5888 0x0 +.debug_line 0x3138b 0x0 +.debug_str 0x71929 0x0 +.debug_loc 0x2c026 0x0 +Total 0xbbc5c5 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 198320 + 197380 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48004 + 48092 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4209A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4209A_REGION_US_LR_size.txt index 62caff6a8b..bb68d1d04a 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4209A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4209A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x2fec0 0x0 -_cc_handlers_v3 0x264 0x2fec0 -_zw_protocol_cmd_handlers 0x70 0x30124 -_zw_protocol_cmd_handlers_lr 0x30 0x30194 -.ARM.exidx 0x8 0x301c4 -.copy.table 0xc 0x301cc -.zero.table 0x0 0x301d8 +.text 0x2faec 0x0 +_cc_handlers_v3 0x240 0x2faec +_zw_protocol_cmd_handlers 0x70 0x2fd2c +_zw_protocol_cmd_handlers_lr 0x30 0x2fd9c +.ARM.exidx 0x8 0x2fdcc +.copy.table 0xc 0x2fdd4 +.zero.table 0x0 0x2fde0 .stack 0x1000 0x20000000 -.data 0x450 0x20001000 -.bss 0x9f0c 0x20001450 -.heap 0x4ca0 0x2000b360 -.internal_storage 0x3a000 0x301d8 -.zwave_nvm 0x3000 0x6a1d8 -.nvm 0x9000 0x6d1d8 +.data 0x45c 0x20001000 +.bss 0x9f60 0x2000145c +.heap 0x4c40 0x2000b3c0 +.internal_storage 0x3a000 0x2fde0 +.zwave_nvm 0x3000 0x69de0 +.nvm 0x9000 0x6cde0 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x7974 0x0 -.debug_info 0xaad4ff 0x0 -.debug_abbrev 0x1360d 0x0 -.debug_aranges 0x2dc8 0x0 -.debug_ranges 0x5bf8 0x0 -.debug_line 0x333e1 0x0 -.debug_str 0x7227a 0x0 -.debug_loc 0x2d954 0x0 -Total 0xc2a03a +.debug_frame 0x7750 0x0 +.debug_info 0xa46c85 0x0 +.debug_abbrev 0x12f9a 0x0 +.debug_aranges 0x2d10 0x0 +.debug_ranges 0x5a60 0x0 +.debug_line 0x3226d 0x0 +.debug_str 0x71c6e 0x0 +.debug_loc 0x2c9c7 0x0 +Total 0xbc01d4 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 198184 + 197180 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47964 + 48060 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4210A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4210A_REGION_US_LR_size.txt index 7256986794..36885e0407 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4210A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_multilevel_sensor_BRD4210A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_multilevel_sensor.out : section size addr -.text 0x37de8 0x8006000 -_cc_handlers_v3 0x264 0x803dde8 -_zw_protocol_cmd_handlers 0x70 0x803e04c -_zw_protocol_cmd_handlers_lr 0x30 0x803e0bc -.ARM.exidx 0x8 0x803e0ec -.copy.table 0xc 0x803e0f4 -.zero.table 0x0 0x803e100 +.text 0x36d74 0x8006000 +_cc_handlers_v3 0x240 0x803cd74 +_zw_protocol_cmd_handlers 0x70 0x803cfb4 +_zw_protocol_cmd_handlers_lr 0x30 0x803d024 +.ARM.exidx 0x8 0x803d054 +.copy.table 0xc 0x803d05c +.zero.table 0x0 0x803d068 .stack 0x1000 0x20000000 -.data 0x5ac 0x20001000 -.bss 0xae50 0x200015ac -.heap 0x3c00 0x2000c400 -.internal_storage 0x2a000 0x803e100 -.zwave_nvm 0x6000 0x8068100 -.nvm 0xa000 0x806e100 +.data 0x5b8 0x20001000 +.bss 0xaea4 0x200015b8 +.heap 0x3ba0 0x2000c460 +.internal_storage 0x2c000 0x803d068 +.zwave_nvm 0x6000 0x8069068 +.nvm 0x8000 0x806f068 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xad9c 0x0 -.debug_info 0xaf5fbc 0x0 -.debug_abbrev 0x18b8f 0x0 -.debug_aranges 0x3c78 0x0 -.debug_ranges 0x7be0 0x0 -.debug_line 0x48c61 0x0 -.debug_str 0x7d07c 0x0 -.debug_loc 0x4bb99 0x0 -Total 0xcb8b30 +.debug_frame 0xaaf8 0x0 +.debug_info 0xa8edc5 0x0 +.debug_abbrev 0x182a9 0x0 +.debug_aranges 0x3b88 0x0 +.debug_ranges 0x78f8 0x0 +.debug_line 0x47513 0x0 +.debug_str 0x7c994 0x0 +.debug_loc 0x4a729 0x0 +Total 0xc4c699 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 231084 + 226848 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52220 + 52316 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4202A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4202A_REGION_EU_size.txt index 05a600614a..ac5c33bf1f 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4202A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4202A_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x2f3c0 0x0 -_cc_handlers_v3 0x2ac 0x2f3c0 -_zw_protocol_cmd_handlers 0x70 0x2f66c -_zw_protocol_cmd_handlers_lr 0x30 0x2f6dc -.ARM.exidx 0x8 0x2f70c -.copy.table 0xc 0x2f714 -.zero.table 0x0 0x2f720 +.text 0x2f55c 0x0 +_cc_handlers_v3 0x2ac 0x2f55c +_zw_protocol_cmd_handlers 0x70 0x2f808 +_zw_protocol_cmd_handlers_lr 0x30 0x2f878 +.ARM.exidx 0x8 0x2f8a8 +.copy.table 0xc 0x2f8b0 +.zero.table 0x0 0x2f8bc .stack 0x1000 0x20000000 -.data 0x578 0x20001000 -.bss 0x9f3c 0x20001578 -.heap 0x4b48 0x2000b4b8 -.internal_storage 0x3a000 0x2f720 -.zwave_nvm 0x3000 0x69720 -.nvm 0x9000 0x6c720 +.data 0x580 0x20001000 +.bss 0x9fc4 0x20001580 +.heap 0x4ab8 0x2000b548 +.internal_storage 0x3a000 0x2f8bc +.zwave_nvm 0x3000 0x698bc +.nvm 0x9000 0x6c8bc .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x73e4 0x0 -.debug_info 0xb08b29 0x0 -.debug_abbrev 0x120e8 0x0 -.debug_loc 0x29963 0x0 +.debug_frame 0x7414 0x0 +.debug_info 0xb09317 0x0 +.debug_abbrev 0x121a5 0x0 +.debug_loc 0x29a9c 0x0 .debug_aranges 0x2b98 0x0 -.debug_ranges 0x5570 0x0 -.debug_line 0x2fbcc 0x0 -.debug_str 0x6e65a 0x0 -Total 0xc77419 +.debug_ranges 0x5548 0x0 +.debug_line 0x2fc7d 0x0 +.debug_str 0x6e7cc 0x0 +Total 0xc781c4 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 195736 + 196156 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48308 + 48452 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4202A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4202A_REGION_US_LR_size.txt index 05a600614a..ac5c33bf1f 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4202A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4202A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x2f3c0 0x0 -_cc_handlers_v3 0x2ac 0x2f3c0 -_zw_protocol_cmd_handlers 0x70 0x2f66c -_zw_protocol_cmd_handlers_lr 0x30 0x2f6dc -.ARM.exidx 0x8 0x2f70c -.copy.table 0xc 0x2f714 -.zero.table 0x0 0x2f720 +.text 0x2f55c 0x0 +_cc_handlers_v3 0x2ac 0x2f55c +_zw_protocol_cmd_handlers 0x70 0x2f808 +_zw_protocol_cmd_handlers_lr 0x30 0x2f878 +.ARM.exidx 0x8 0x2f8a8 +.copy.table 0xc 0x2f8b0 +.zero.table 0x0 0x2f8bc .stack 0x1000 0x20000000 -.data 0x578 0x20001000 -.bss 0x9f3c 0x20001578 -.heap 0x4b48 0x2000b4b8 -.internal_storage 0x3a000 0x2f720 -.zwave_nvm 0x3000 0x69720 -.nvm 0x9000 0x6c720 +.data 0x580 0x20001000 +.bss 0x9fc4 0x20001580 +.heap 0x4ab8 0x2000b548 +.internal_storage 0x3a000 0x2f8bc +.zwave_nvm 0x3000 0x698bc +.nvm 0x9000 0x6c8bc .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x73e4 0x0 -.debug_info 0xb08b29 0x0 -.debug_abbrev 0x120e8 0x0 -.debug_loc 0x29963 0x0 +.debug_frame 0x7414 0x0 +.debug_info 0xb09317 0x0 +.debug_abbrev 0x121a5 0x0 +.debug_loc 0x29a9c 0x0 .debug_aranges 0x2b98 0x0 -.debug_ranges 0x5570 0x0 -.debug_line 0x2fbcc 0x0 -.debug_str 0x6e65a 0x0 -Total 0xc77419 +.debug_ranges 0x5548 0x0 +.debug_line 0x2fc7d 0x0 +.debug_str 0x6e7cc 0x0 +Total 0xc781c4 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 195736 + 196156 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48308 + 48452 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4202A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4202A_REGION_US_size.txt index 05a600614a..ac5c33bf1f 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4202A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4202A_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x2f3c0 0x0 -_cc_handlers_v3 0x2ac 0x2f3c0 -_zw_protocol_cmd_handlers 0x70 0x2f66c -_zw_protocol_cmd_handlers_lr 0x30 0x2f6dc -.ARM.exidx 0x8 0x2f70c -.copy.table 0xc 0x2f714 -.zero.table 0x0 0x2f720 +.text 0x2f55c 0x0 +_cc_handlers_v3 0x2ac 0x2f55c +_zw_protocol_cmd_handlers 0x70 0x2f808 +_zw_protocol_cmd_handlers_lr 0x30 0x2f878 +.ARM.exidx 0x8 0x2f8a8 +.copy.table 0xc 0x2f8b0 +.zero.table 0x0 0x2f8bc .stack 0x1000 0x20000000 -.data 0x578 0x20001000 -.bss 0x9f3c 0x20001578 -.heap 0x4b48 0x2000b4b8 -.internal_storage 0x3a000 0x2f720 -.zwave_nvm 0x3000 0x69720 -.nvm 0x9000 0x6c720 +.data 0x580 0x20001000 +.bss 0x9fc4 0x20001580 +.heap 0x4ab8 0x2000b548 +.internal_storage 0x3a000 0x2f8bc +.zwave_nvm 0x3000 0x698bc +.nvm 0x9000 0x6c8bc .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x73e4 0x0 -.debug_info 0xb08b29 0x0 -.debug_abbrev 0x120e8 0x0 -.debug_loc 0x29963 0x0 +.debug_frame 0x7414 0x0 +.debug_info 0xb09317 0x0 +.debug_abbrev 0x121a5 0x0 +.debug_loc 0x29a9c 0x0 .debug_aranges 0x2b98 0x0 -.debug_ranges 0x5570 0x0 -.debug_line 0x2fbcc 0x0 -.debug_str 0x6e65a 0x0 -Total 0xc77419 +.debug_ranges 0x5548 0x0 +.debug_line 0x2fc7d 0x0 +.debug_str 0x6e7cc 0x0 +Total 0xc781c4 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 195736 + 196156 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48308 + 48452 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205A_REGION_EU_size.txt index 46758dbaba..ed42576367 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205A_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x372cc 0x8006000 -_cc_handlers_v3 0x2ac 0x803d2cc -_zw_protocol_cmd_handlers 0x70 0x803d578 -_zw_protocol_cmd_handlers_lr 0x30 0x803d5e8 -.ARM.exidx 0x8 0x803d618 -.copy.table 0xc 0x803d620 -.zero.table 0x0 0x803d62c +.text 0x36520 0x8006000 +_cc_handlers_v3 0x2ac 0x803c520 +_zw_protocol_cmd_handlers 0x70 0x803c7cc +_zw_protocol_cmd_handlers_lr 0x30 0x803c83c +.ARM.exidx 0x8 0x803c86c +.copy.table 0xc 0x803c874 +.zero.table 0x0 0x803c880 .stack 0x1000 0x20000000 -.data 0x6d0 0x20001000 -.bss 0xad54 0x200016d0 -.heap 0x3bd8 0x2000c428 -.internal_storage 0x2a000 0x803d62c -.zwave_nvm 0x6000 0x806762c -.nvm 0xa000 0x806d62c +.data 0x6d8 0x20001000 +.bss 0xaddc 0x200016d8 +.heap 0x3b48 0x2000c4b8 +.internal_storage 0x2c000 0x803c880 +.zwave_nvm 0x6000 0x8068880 +.nvm 0x8000 0x806e880 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa734 0x0 -.debug_info 0xb52337 0x0 -.debug_abbrev 0x17eaa 0x0 -.debug_loc 0x466b7 0x0 -.debug_aranges 0x3ae8 0x0 -.debug_ranges 0x7450 0x0 -.debug_line 0x44db6 0x0 -.debug_str 0x7ae5e 0x0 -Total 0xd071bf +.debug_frame 0xa35c 0x0 +.debug_info 0xb4fd9a 0x0 +.debug_abbrev 0x1765d 0x0 +.debug_loc 0x439e7 0x0 +.debug_aranges 0x39d0 0x0 +.debug_ranges 0x71e8 0x0 +.debug_line 0x43719 0x0 +.debug_str 0x7a949 0x0 +Total 0xcfe64f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228604 + 225112 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52260 + 52404 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205A_REGION_US_LR_size.txt index 46758dbaba..ed42576367 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x372cc 0x8006000 -_cc_handlers_v3 0x2ac 0x803d2cc -_zw_protocol_cmd_handlers 0x70 0x803d578 -_zw_protocol_cmd_handlers_lr 0x30 0x803d5e8 -.ARM.exidx 0x8 0x803d618 -.copy.table 0xc 0x803d620 -.zero.table 0x0 0x803d62c +.text 0x36520 0x8006000 +_cc_handlers_v3 0x2ac 0x803c520 +_zw_protocol_cmd_handlers 0x70 0x803c7cc +_zw_protocol_cmd_handlers_lr 0x30 0x803c83c +.ARM.exidx 0x8 0x803c86c +.copy.table 0xc 0x803c874 +.zero.table 0x0 0x803c880 .stack 0x1000 0x20000000 -.data 0x6d0 0x20001000 -.bss 0xad54 0x200016d0 -.heap 0x3bd8 0x2000c428 -.internal_storage 0x2a000 0x803d62c -.zwave_nvm 0x6000 0x806762c -.nvm 0xa000 0x806d62c +.data 0x6d8 0x20001000 +.bss 0xaddc 0x200016d8 +.heap 0x3b48 0x2000c4b8 +.internal_storage 0x2c000 0x803c880 +.zwave_nvm 0x6000 0x8068880 +.nvm 0x8000 0x806e880 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa734 0x0 -.debug_info 0xb52337 0x0 -.debug_abbrev 0x17eaa 0x0 -.debug_loc 0x466b7 0x0 -.debug_aranges 0x3ae8 0x0 -.debug_ranges 0x7450 0x0 -.debug_line 0x44db6 0x0 -.debug_str 0x7ae5e 0x0 -Total 0xd071bf +.debug_frame 0xa35c 0x0 +.debug_info 0xb4fd9a 0x0 +.debug_abbrev 0x1765d 0x0 +.debug_loc 0x439e7 0x0 +.debug_aranges 0x39d0 0x0 +.debug_ranges 0x71e8 0x0 +.debug_line 0x43719 0x0 +.debug_str 0x7a949 0x0 +Total 0xcfe64f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228604 + 225112 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52260 + 52404 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205A_REGION_US_size.txt index 46758dbaba..ed42576367 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205A_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x372cc 0x8006000 -_cc_handlers_v3 0x2ac 0x803d2cc -_zw_protocol_cmd_handlers 0x70 0x803d578 -_zw_protocol_cmd_handlers_lr 0x30 0x803d5e8 -.ARM.exidx 0x8 0x803d618 -.copy.table 0xc 0x803d620 -.zero.table 0x0 0x803d62c +.text 0x36520 0x8006000 +_cc_handlers_v3 0x2ac 0x803c520 +_zw_protocol_cmd_handlers 0x70 0x803c7cc +_zw_protocol_cmd_handlers_lr 0x30 0x803c83c +.ARM.exidx 0x8 0x803c86c +.copy.table 0xc 0x803c874 +.zero.table 0x0 0x803c880 .stack 0x1000 0x20000000 -.data 0x6d0 0x20001000 -.bss 0xad54 0x200016d0 -.heap 0x3bd8 0x2000c428 -.internal_storage 0x2a000 0x803d62c -.zwave_nvm 0x6000 0x806762c -.nvm 0xa000 0x806d62c +.data 0x6d8 0x20001000 +.bss 0xaddc 0x200016d8 +.heap 0x3b48 0x2000c4b8 +.internal_storage 0x2c000 0x803c880 +.zwave_nvm 0x6000 0x8068880 +.nvm 0x8000 0x806e880 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa734 0x0 -.debug_info 0xb52337 0x0 -.debug_abbrev 0x17eaa 0x0 -.debug_loc 0x466b7 0x0 -.debug_aranges 0x3ae8 0x0 -.debug_ranges 0x7450 0x0 -.debug_line 0x44db6 0x0 -.debug_str 0x7ae5e 0x0 -Total 0xd071bf +.debug_frame 0xa35c 0x0 +.debug_info 0xb4fd9a 0x0 +.debug_abbrev 0x1765d 0x0 +.debug_loc 0x439e7 0x0 +.debug_aranges 0x39d0 0x0 +.debug_ranges 0x71e8 0x0 +.debug_line 0x43719 0x0 +.debug_str 0x7a949 0x0 +Total 0xcfe64f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 228604 + 225112 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52260 + 52404 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205B_REGION_EU_size.txt index 9d9ea9c7a1..59a4e7da33 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205B_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x3761c 0x8006000 -_cc_handlers_v3 0x2ac 0x803d61c -_zw_protocol_cmd_handlers 0x70 0x803d8c8 -_zw_protocol_cmd_handlers_lr 0x30 0x803d938 -.ARM.exidx 0x8 0x803d968 -.copy.table 0xc 0x803d970 -.zero.table 0x0 0x803d97c +.text 0x36af8 0x8006000 +_cc_handlers_v3 0x2ac 0x803caf8 +_zw_protocol_cmd_handlers 0x70 0x803cda4 +_zw_protocol_cmd_handlers_lr 0x30 0x803ce14 +.ARM.exidx 0x8 0x803ce44 +.copy.table 0xc 0x803ce4c +.zero.table 0x0 0x803ce58 .stack 0x1000 0x20000000 -.data 0x6d0 0x20001000 -.bss 0xae84 0x200016d0 -.heap 0x3aa8 0x2000c558 -.internal_storage 0x2a000 0x803d97c -.zwave_nvm 0x6000 0x806797c -.nvm 0xa000 0x806d97c +.data 0x6d8 0x20001000 +.bss 0xaf14 0x200016d8 +.heap 0x3a10 0x2000c5f0 +.internal_storage 0x2c000 0x803ce58 +.zwave_nvm 0x6000 0x8068e58 +.nvm 0x8000 0x806ee58 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa944 0x0 -.debug_info 0xb5455f 0x0 -.debug_abbrev 0x17bf3 0x0 -.debug_loc 0x483e2 0x0 -.debug_aranges 0x3b18 0x0 -.debug_ranges 0x7570 0x0 -.debug_line 0x45f62 0x0 -.debug_str 0x7b1b1 0x0 -Total 0xd0ca0a +.debug_frame 0xa8f4 0x0 +.debug_info 0xb543cc 0x0 +.debug_abbrev 0x17a32 0x0 +.debug_loc 0x48085 0x0 +.debug_aranges 0x3ae0 0x0 +.debug_ranges 0x7418 0x0 +.debug_line 0x45a93 0x0 +.debug_str 0x7b247 0x0 +Total 0xd0b21c The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 229452 + 226608 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52564 + 52716 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205B_REGION_US_LR_size.txt index 9d9ea9c7a1..59a4e7da33 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205B_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x3761c 0x8006000 -_cc_handlers_v3 0x2ac 0x803d61c -_zw_protocol_cmd_handlers 0x70 0x803d8c8 -_zw_protocol_cmd_handlers_lr 0x30 0x803d938 -.ARM.exidx 0x8 0x803d968 -.copy.table 0xc 0x803d970 -.zero.table 0x0 0x803d97c +.text 0x36af8 0x8006000 +_cc_handlers_v3 0x2ac 0x803caf8 +_zw_protocol_cmd_handlers 0x70 0x803cda4 +_zw_protocol_cmd_handlers_lr 0x30 0x803ce14 +.ARM.exidx 0x8 0x803ce44 +.copy.table 0xc 0x803ce4c +.zero.table 0x0 0x803ce58 .stack 0x1000 0x20000000 -.data 0x6d0 0x20001000 -.bss 0xae84 0x200016d0 -.heap 0x3aa8 0x2000c558 -.internal_storage 0x2a000 0x803d97c -.zwave_nvm 0x6000 0x806797c -.nvm 0xa000 0x806d97c +.data 0x6d8 0x20001000 +.bss 0xaf14 0x200016d8 +.heap 0x3a10 0x2000c5f0 +.internal_storage 0x2c000 0x803ce58 +.zwave_nvm 0x6000 0x8068e58 +.nvm 0x8000 0x806ee58 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa944 0x0 -.debug_info 0xb5455f 0x0 -.debug_abbrev 0x17bf3 0x0 -.debug_loc 0x483e2 0x0 -.debug_aranges 0x3b18 0x0 -.debug_ranges 0x7570 0x0 -.debug_line 0x45f62 0x0 -.debug_str 0x7b1b1 0x0 -Total 0xd0ca0a +.debug_frame 0xa8f4 0x0 +.debug_info 0xb543cc 0x0 +.debug_abbrev 0x17a32 0x0 +.debug_loc 0x48085 0x0 +.debug_aranges 0x3ae0 0x0 +.debug_ranges 0x7418 0x0 +.debug_line 0x45a93 0x0 +.debug_str 0x7b247 0x0 +Total 0xd0b21c The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 229452 + 226608 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52564 + 52716 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205B_REGION_US_size.txt index 9d9ea9c7a1..59a4e7da33 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4205B_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x3761c 0x8006000 -_cc_handlers_v3 0x2ac 0x803d61c -_zw_protocol_cmd_handlers 0x70 0x803d8c8 -_zw_protocol_cmd_handlers_lr 0x30 0x803d938 -.ARM.exidx 0x8 0x803d968 -.copy.table 0xc 0x803d970 -.zero.table 0x0 0x803d97c +.text 0x36af8 0x8006000 +_cc_handlers_v3 0x2ac 0x803caf8 +_zw_protocol_cmd_handlers 0x70 0x803cda4 +_zw_protocol_cmd_handlers_lr 0x30 0x803ce14 +.ARM.exidx 0x8 0x803ce44 +.copy.table 0xc 0x803ce4c +.zero.table 0x0 0x803ce58 .stack 0x1000 0x20000000 -.data 0x6d0 0x20001000 -.bss 0xae84 0x200016d0 -.heap 0x3aa8 0x2000c558 -.internal_storage 0x2a000 0x803d97c -.zwave_nvm 0x6000 0x806797c -.nvm 0xa000 0x806d97c +.data 0x6d8 0x20001000 +.bss 0xaf14 0x200016d8 +.heap 0x3a10 0x2000c5f0 +.internal_storage 0x2c000 0x803ce58 +.zwave_nvm 0x6000 0x8068e58 +.nvm 0x8000 0x806ee58 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa944 0x0 -.debug_info 0xb5455f 0x0 -.debug_abbrev 0x17bf3 0x0 -.debug_loc 0x483e2 0x0 -.debug_aranges 0x3b18 0x0 -.debug_ranges 0x7570 0x0 -.debug_line 0x45f62 0x0 -.debug_str 0x7b1b1 0x0 -Total 0xd0ca0a +.debug_frame 0xa8f4 0x0 +.debug_info 0xb543cc 0x0 +.debug_abbrev 0x17a32 0x0 +.debug_loc 0x48085 0x0 +.debug_aranges 0x3ae0 0x0 +.debug_ranges 0x7418 0x0 +.debug_line 0x45a93 0x0 +.debug_str 0x7b247 0x0 +Total 0xd0b21c The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 229452 + 226608 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52564 + 52716 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4207A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4207A_REGION_EU_size.txt index 05a600614a..ac5c33bf1f 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4207A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4207A_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x2f3c0 0x0 -_cc_handlers_v3 0x2ac 0x2f3c0 -_zw_protocol_cmd_handlers 0x70 0x2f66c -_zw_protocol_cmd_handlers_lr 0x30 0x2f6dc -.ARM.exidx 0x8 0x2f70c -.copy.table 0xc 0x2f714 -.zero.table 0x0 0x2f720 +.text 0x2f55c 0x0 +_cc_handlers_v3 0x2ac 0x2f55c +_zw_protocol_cmd_handlers 0x70 0x2f808 +_zw_protocol_cmd_handlers_lr 0x30 0x2f878 +.ARM.exidx 0x8 0x2f8a8 +.copy.table 0xc 0x2f8b0 +.zero.table 0x0 0x2f8bc .stack 0x1000 0x20000000 -.data 0x578 0x20001000 -.bss 0x9f3c 0x20001578 -.heap 0x4b48 0x2000b4b8 -.internal_storage 0x3a000 0x2f720 -.zwave_nvm 0x3000 0x69720 -.nvm 0x9000 0x6c720 +.data 0x580 0x20001000 +.bss 0x9fc4 0x20001580 +.heap 0x4ab8 0x2000b548 +.internal_storage 0x3a000 0x2f8bc +.zwave_nvm 0x3000 0x698bc +.nvm 0x9000 0x6c8bc .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x73e4 0x0 -.debug_info 0xb08b29 0x0 -.debug_abbrev 0x120e8 0x0 -.debug_loc 0x29963 0x0 +.debug_frame 0x7414 0x0 +.debug_info 0xb09317 0x0 +.debug_abbrev 0x121a5 0x0 +.debug_loc 0x29a9c 0x0 .debug_aranges 0x2b98 0x0 -.debug_ranges 0x5570 0x0 -.debug_line 0x2fbcc 0x0 -.debug_str 0x6e65a 0x0 -Total 0xc77419 +.debug_ranges 0x5548 0x0 +.debug_line 0x2fc7d 0x0 +.debug_str 0x6e7cc 0x0 +Total 0xc781c4 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 195736 + 196156 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48308 + 48452 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4207A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4207A_REGION_US_LR_size.txt index 05a600614a..ac5c33bf1f 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4207A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4207A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x2f3c0 0x0 -_cc_handlers_v3 0x2ac 0x2f3c0 -_zw_protocol_cmd_handlers 0x70 0x2f66c -_zw_protocol_cmd_handlers_lr 0x30 0x2f6dc -.ARM.exidx 0x8 0x2f70c -.copy.table 0xc 0x2f714 -.zero.table 0x0 0x2f720 +.text 0x2f55c 0x0 +_cc_handlers_v3 0x2ac 0x2f55c +_zw_protocol_cmd_handlers 0x70 0x2f808 +_zw_protocol_cmd_handlers_lr 0x30 0x2f878 +.ARM.exidx 0x8 0x2f8a8 +.copy.table 0xc 0x2f8b0 +.zero.table 0x0 0x2f8bc .stack 0x1000 0x20000000 -.data 0x578 0x20001000 -.bss 0x9f3c 0x20001578 -.heap 0x4b48 0x2000b4b8 -.internal_storage 0x3a000 0x2f720 -.zwave_nvm 0x3000 0x69720 -.nvm 0x9000 0x6c720 +.data 0x580 0x20001000 +.bss 0x9fc4 0x20001580 +.heap 0x4ab8 0x2000b548 +.internal_storage 0x3a000 0x2f8bc +.zwave_nvm 0x3000 0x698bc +.nvm 0x9000 0x6c8bc .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x73e4 0x0 -.debug_info 0xb08b29 0x0 -.debug_abbrev 0x120e8 0x0 -.debug_loc 0x29963 0x0 +.debug_frame 0x7414 0x0 +.debug_info 0xb09317 0x0 +.debug_abbrev 0x121a5 0x0 +.debug_loc 0x29a9c 0x0 .debug_aranges 0x2b98 0x0 -.debug_ranges 0x5570 0x0 -.debug_line 0x2fbcc 0x0 -.debug_str 0x6e65a 0x0 -Total 0xc77419 +.debug_ranges 0x5548 0x0 +.debug_line 0x2fc7d 0x0 +.debug_str 0x6e7cc 0x0 +Total 0xc781c4 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 195736 + 196156 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48308 + 48452 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4207A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4207A_REGION_US_size.txt index 05a600614a..ac5c33bf1f 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4207A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4207A_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x2f3c0 0x0 -_cc_handlers_v3 0x2ac 0x2f3c0 -_zw_protocol_cmd_handlers 0x70 0x2f66c -_zw_protocol_cmd_handlers_lr 0x30 0x2f6dc -.ARM.exidx 0x8 0x2f70c -.copy.table 0xc 0x2f714 -.zero.table 0x0 0x2f720 +.text 0x2f55c 0x0 +_cc_handlers_v3 0x2ac 0x2f55c +_zw_protocol_cmd_handlers 0x70 0x2f808 +_zw_protocol_cmd_handlers_lr 0x30 0x2f878 +.ARM.exidx 0x8 0x2f8a8 +.copy.table 0xc 0x2f8b0 +.zero.table 0x0 0x2f8bc .stack 0x1000 0x20000000 -.data 0x578 0x20001000 -.bss 0x9f3c 0x20001578 -.heap 0x4b48 0x2000b4b8 -.internal_storage 0x3a000 0x2f720 -.zwave_nvm 0x3000 0x69720 -.nvm 0x9000 0x6c720 +.data 0x580 0x20001000 +.bss 0x9fc4 0x20001580 +.heap 0x4ab8 0x2000b548 +.internal_storage 0x3a000 0x2f8bc +.zwave_nvm 0x3000 0x698bc +.nvm 0x9000 0x6c8bc .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x73e4 0x0 -.debug_info 0xb08b29 0x0 -.debug_abbrev 0x120e8 0x0 -.debug_loc 0x29963 0x0 +.debug_frame 0x7414 0x0 +.debug_info 0xb09317 0x0 +.debug_abbrev 0x121a5 0x0 +.debug_loc 0x29a9c 0x0 .debug_aranges 0x2b98 0x0 -.debug_ranges 0x5570 0x0 -.debug_line 0x2fbcc 0x0 -.debug_str 0x6e65a 0x0 -Total 0xc77419 +.debug_ranges 0x5548 0x0 +.debug_line 0x2fc7d 0x0 +.debug_str 0x6e7cc 0x0 +Total 0xc781c4 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 195736 + 196156 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48308 + 48452 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4209A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4209A_REGION_US_LR_size.txt index 89cbbe6600..88808bf9fd 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4209A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_power_strip_BRD4209A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_power_strip.out : section size addr -.text 0x2f38c 0x0 -_cc_handlers_v3 0x2ac 0x2f38c -_zw_protocol_cmd_handlers 0x70 0x2f638 -_zw_protocol_cmd_handlers_lr 0x30 0x2f6a8 -.ARM.exidx 0x8 0x2f6d8 -.copy.table 0xc 0x2f6e0 -.zero.table 0x0 0x2f6ec +.text 0x2f4e8 0x0 +_cc_handlers_v3 0x2ac 0x2f4e8 +_zw_protocol_cmd_handlers 0x70 0x2f794 +_zw_protocol_cmd_handlers_lr 0x30 0x2f804 +.ARM.exidx 0x8 0x2f834 +.copy.table 0xc 0x2f83c +.zero.table 0x0 0x2f848 .stack 0x1000 0x20000000 -.data 0x574 0x20001000 -.bss 0x9f28 0x20001574 -.heap 0x4b60 0x2000b4a0 -.internal_storage 0x3a000 0x2f6ec -.zwave_nvm 0x3000 0x696ec -.nvm 0x9000 0x6c6ec +.data 0x57c 0x20001000 +.bss 0x9fb0 0x2000157c +.heap 0x4ad0 0x2000b530 +.internal_storage 0x3a000 0x2f848 +.zwave_nvm 0x3000 0x69848 +.nvm 0x9000 0x6c848 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x7614 0x0 -.debug_info 0xb0a3fc 0x0 -.debug_abbrev 0x12652 0x0 -.debug_loc 0x2a472 0x0 +.debug_frame 0x7644 0x0 +.debug_info 0xb0abea 0x0 +.debug_abbrev 0x1270f 0x0 +.debug_loc 0x2a5ab 0x0 .debug_aranges 0x2c78 0x0 -.debug_ranges 0x5758 0x0 -.debug_line 0x30c49 0x0 -.debug_str 0x6ea50 0x0 -Total 0xc7b69c +.debug_ranges 0x5730 0x0 +.debug_line 0x30cfa 0x0 +.debug_str 0x6ebc3 0x0 +Total 0xc7c408 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 195680 + 196036 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 48284 + 48428 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4202A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4202A_REGION_EU_size.txt index 7c5f7733af..f9beefd8b2 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4202A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4202A_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x2ea9c 0x0 -_cc_handlers_v3 0x21c 0x2ea9c -_zw_protocol_cmd_handlers 0x70 0x2ecb8 -_zw_protocol_cmd_handlers_lr 0x30 0x2ed28 -.ARM.exidx 0x8 0x2ed58 -.copy.table 0xc 0x2ed60 -.zero.table 0x0 0x2ed6c +.text 0x2ec18 0x0 +_cc_handlers_v3 0x21c 0x2ec18 +_zw_protocol_cmd_handlers 0x70 0x2ee34 +_zw_protocol_cmd_handlers_lr 0x30 0x2eea4 +.ARM.exidx 0x8 0x2eed4 +.copy.table 0xc 0x2eedc +.zero.table 0x0 0x2eee8 .stack 0x1000 0x20000000 -.data 0x434 0x20001000 -.bss 0x9e40 0x20001434 -.heap 0x4d88 0x2000b278 -.internal_storage 0x3a000 0x2ed6c -.zwave_nvm 0x3000 0x68d6c -.nvm 0x9000 0x6bd6c +.data 0x43c 0x20001000 +.bss 0x9ec0 0x2000143c +.heap 0x4d00 0x2000b300 +.internal_storage 0x3a000 0x2eee8 +.zwave_nvm 0x3000 0x68ee8 +.nvm 0x9000 0x6bee8 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6f9c 0x0 -.debug_info 0x9d94f1 0x0 -.debug_abbrev 0x11595 0x0 +.debug_frame 0x6fbc 0x0 +.debug_info 0x9d9d15 0x0 +.debug_abbrev 0x11649 0x0 .debug_aranges 0x2a10 0x0 -.debug_ranges 0x5010 0x0 -.debug_line 0x2e18a 0x0 -.debug_str 0x6fdde 0x0 -.debug_loc 0x27a2d 0x0 -Total 0xb43bb6 +.debug_ranges 0x4fe0 0x0 +.debug_line 0x2e21f 0x0 +.debug_str 0x6ff46 0x0 +.debug_loc 0x27b26 0x0 +Total 0xb448f0 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 192928 + 193316 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47732 + 47868 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4202A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4202A_REGION_US_LR_size.txt index 7c5f7733af..f9beefd8b2 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4202A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4202A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x2ea9c 0x0 -_cc_handlers_v3 0x21c 0x2ea9c -_zw_protocol_cmd_handlers 0x70 0x2ecb8 -_zw_protocol_cmd_handlers_lr 0x30 0x2ed28 -.ARM.exidx 0x8 0x2ed58 -.copy.table 0xc 0x2ed60 -.zero.table 0x0 0x2ed6c +.text 0x2ec18 0x0 +_cc_handlers_v3 0x21c 0x2ec18 +_zw_protocol_cmd_handlers 0x70 0x2ee34 +_zw_protocol_cmd_handlers_lr 0x30 0x2eea4 +.ARM.exidx 0x8 0x2eed4 +.copy.table 0xc 0x2eedc +.zero.table 0x0 0x2eee8 .stack 0x1000 0x20000000 -.data 0x434 0x20001000 -.bss 0x9e40 0x20001434 -.heap 0x4d88 0x2000b278 -.internal_storage 0x3a000 0x2ed6c -.zwave_nvm 0x3000 0x68d6c -.nvm 0x9000 0x6bd6c +.data 0x43c 0x20001000 +.bss 0x9ec0 0x2000143c +.heap 0x4d00 0x2000b300 +.internal_storage 0x3a000 0x2eee8 +.zwave_nvm 0x3000 0x68ee8 +.nvm 0x9000 0x6bee8 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6f9c 0x0 -.debug_info 0x9d94f1 0x0 -.debug_abbrev 0x11595 0x0 +.debug_frame 0x6fbc 0x0 +.debug_info 0x9d9d15 0x0 +.debug_abbrev 0x11649 0x0 .debug_aranges 0x2a10 0x0 -.debug_ranges 0x5010 0x0 -.debug_line 0x2e18a 0x0 -.debug_str 0x6fdde 0x0 -.debug_loc 0x27a2d 0x0 -Total 0xb43bb6 +.debug_ranges 0x4fe0 0x0 +.debug_line 0x2e21f 0x0 +.debug_str 0x6ff46 0x0 +.debug_loc 0x27b26 0x0 +Total 0xb448f0 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 192928 + 193316 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47732 + 47868 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4202A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4202A_REGION_US_size.txt index 7c5f7733af..f9beefd8b2 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4202A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4202A_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x2ea9c 0x0 -_cc_handlers_v3 0x21c 0x2ea9c -_zw_protocol_cmd_handlers 0x70 0x2ecb8 -_zw_protocol_cmd_handlers_lr 0x30 0x2ed28 -.ARM.exidx 0x8 0x2ed58 -.copy.table 0xc 0x2ed60 -.zero.table 0x0 0x2ed6c +.text 0x2ec18 0x0 +_cc_handlers_v3 0x21c 0x2ec18 +_zw_protocol_cmd_handlers 0x70 0x2ee34 +_zw_protocol_cmd_handlers_lr 0x30 0x2eea4 +.ARM.exidx 0x8 0x2eed4 +.copy.table 0xc 0x2eedc +.zero.table 0x0 0x2eee8 .stack 0x1000 0x20000000 -.data 0x434 0x20001000 -.bss 0x9e40 0x20001434 -.heap 0x4d88 0x2000b278 -.internal_storage 0x3a000 0x2ed6c -.zwave_nvm 0x3000 0x68d6c -.nvm 0x9000 0x6bd6c +.data 0x43c 0x20001000 +.bss 0x9ec0 0x2000143c +.heap 0x4d00 0x2000b300 +.internal_storage 0x3a000 0x2eee8 +.zwave_nvm 0x3000 0x68ee8 +.nvm 0x9000 0x6bee8 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6f9c 0x0 -.debug_info 0x9d94f1 0x0 -.debug_abbrev 0x11595 0x0 +.debug_frame 0x6fbc 0x0 +.debug_info 0x9d9d15 0x0 +.debug_abbrev 0x11649 0x0 .debug_aranges 0x2a10 0x0 -.debug_ranges 0x5010 0x0 -.debug_line 0x2e18a 0x0 -.debug_str 0x6fdde 0x0 -.debug_loc 0x27a2d 0x0 -Total 0xb43bb6 +.debug_ranges 0x4fe0 0x0 +.debug_line 0x2e21f 0x0 +.debug_str 0x6ff46 0x0 +.debug_loc 0x27b26 0x0 +Total 0xb448f0 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 192928 + 193316 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47732 + 47868 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204C_REGION_EU_size.txt index 340ee03d5d..bcc5108990 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204C_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x36854 0x8006000 -_cc_handlers_v3 0x21c 0x803c854 -_zw_protocol_cmd_handlers 0x70 0x803ca70 -_zw_protocol_cmd_handlers_lr 0x30 0x803cae0 -.ARM.exidx 0x8 0x803cb10 -.copy.table 0xc 0x803cb18 -.zero.table 0x0 0x803cb24 +.text 0x35d08 0x8006000 +_cc_handlers_v3 0x21c 0x803bd08 +_zw_protocol_cmd_handlers 0x70 0x803bf24 +_zw_protocol_cmd_handlers_lr 0x30 0x803bf94 +.ARM.exidx 0x8 0x803bfc4 +.copy.table 0xc 0x803bfcc +.zero.table 0x0 0x803bfd8 .stack 0x1000 0x20000000 -.data 0x58c 0x20001000 -.bss 0xad60 0x2000158c -.heap 0x3d10 0x2000c2f0 -.internal_storage 0x2a000 0x803cb24 -.zwave_nvm 0x6000 0x8066b24 -.nvm 0xa000 0x806cb24 +.data 0x594 0x20001000 +.bss 0xade8 0x20001594 +.heap 0x3c80 0x2000c380 +.internal_storage 0x2c000 0x803bfd8 +.zwave_nvm 0x6000 0x8067fd8 +.nvm 0x8000 0x806dfd8 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa5b8 0x0 -.debug_info 0xa214c2 0x0 -.debug_abbrev 0x16f46 0x0 -.debug_aranges 0x3980 0x0 -.debug_ranges 0x7158 0x0 -.debug_line 0x44748 0x0 -.debug_str 0x7adec 0x0 -.debug_loc 0x4668a 0x0 -Total 0xbd3bf5 +.debug_frame 0xa558 0x0 +.debug_info 0xa21367 0x0 +.debug_abbrev 0x16d87 0x0 +.debug_aranges 0x3948 0x0 +.debug_ranges 0x6fc8 0x0 +.debug_line 0x4424e 0x0 +.debug_str 0x7ae79 0x0 +.debug_loc 0x4626e 0x0 +Total 0xbd22de The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225456 + 222572 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51948 + 52092 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204C_REGION_US_LR_size.txt index 340ee03d5d..bcc5108990 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204C_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x36854 0x8006000 -_cc_handlers_v3 0x21c 0x803c854 -_zw_protocol_cmd_handlers 0x70 0x803ca70 -_zw_protocol_cmd_handlers_lr 0x30 0x803cae0 -.ARM.exidx 0x8 0x803cb10 -.copy.table 0xc 0x803cb18 -.zero.table 0x0 0x803cb24 +.text 0x35d08 0x8006000 +_cc_handlers_v3 0x21c 0x803bd08 +_zw_protocol_cmd_handlers 0x70 0x803bf24 +_zw_protocol_cmd_handlers_lr 0x30 0x803bf94 +.ARM.exidx 0x8 0x803bfc4 +.copy.table 0xc 0x803bfcc +.zero.table 0x0 0x803bfd8 .stack 0x1000 0x20000000 -.data 0x58c 0x20001000 -.bss 0xad60 0x2000158c -.heap 0x3d10 0x2000c2f0 -.internal_storage 0x2a000 0x803cb24 -.zwave_nvm 0x6000 0x8066b24 -.nvm 0xa000 0x806cb24 +.data 0x594 0x20001000 +.bss 0xade8 0x20001594 +.heap 0x3c80 0x2000c380 +.internal_storage 0x2c000 0x803bfd8 +.zwave_nvm 0x6000 0x8067fd8 +.nvm 0x8000 0x806dfd8 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa5b8 0x0 -.debug_info 0xa214c2 0x0 -.debug_abbrev 0x16f46 0x0 -.debug_aranges 0x3980 0x0 -.debug_ranges 0x7158 0x0 -.debug_line 0x44748 0x0 -.debug_str 0x7adec 0x0 -.debug_loc 0x4668a 0x0 -Total 0xbd3bf5 +.debug_frame 0xa558 0x0 +.debug_info 0xa21367 0x0 +.debug_abbrev 0x16d87 0x0 +.debug_aranges 0x3948 0x0 +.debug_ranges 0x6fc8 0x0 +.debug_line 0x4424e 0x0 +.debug_str 0x7ae79 0x0 +.debug_loc 0x4626e 0x0 +Total 0xbd22de The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225456 + 222572 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51948 + 52092 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204C_REGION_US_size.txt index 340ee03d5d..bcc5108990 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204C_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x36854 0x8006000 -_cc_handlers_v3 0x21c 0x803c854 -_zw_protocol_cmd_handlers 0x70 0x803ca70 -_zw_protocol_cmd_handlers_lr 0x30 0x803cae0 -.ARM.exidx 0x8 0x803cb10 -.copy.table 0xc 0x803cb18 -.zero.table 0x0 0x803cb24 +.text 0x35d08 0x8006000 +_cc_handlers_v3 0x21c 0x803bd08 +_zw_protocol_cmd_handlers 0x70 0x803bf24 +_zw_protocol_cmd_handlers_lr 0x30 0x803bf94 +.ARM.exidx 0x8 0x803bfc4 +.copy.table 0xc 0x803bfcc +.zero.table 0x0 0x803bfd8 .stack 0x1000 0x20000000 -.data 0x58c 0x20001000 -.bss 0xad60 0x2000158c -.heap 0x3d10 0x2000c2f0 -.internal_storage 0x2a000 0x803cb24 -.zwave_nvm 0x6000 0x8066b24 -.nvm 0xa000 0x806cb24 +.data 0x594 0x20001000 +.bss 0xade8 0x20001594 +.heap 0x3c80 0x2000c380 +.internal_storage 0x2c000 0x803bfd8 +.zwave_nvm 0x6000 0x8067fd8 +.nvm 0x8000 0x806dfd8 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa5b8 0x0 -.debug_info 0xa214c2 0x0 -.debug_abbrev 0x16f46 0x0 -.debug_aranges 0x3980 0x0 -.debug_ranges 0x7158 0x0 -.debug_line 0x44748 0x0 -.debug_str 0x7adec 0x0 -.debug_loc 0x4668a 0x0 -Total 0xbd3bf5 +.debug_frame 0xa558 0x0 +.debug_info 0xa21367 0x0 +.debug_abbrev 0x16d87 0x0 +.debug_aranges 0x3948 0x0 +.debug_ranges 0x6fc8 0x0 +.debug_line 0x4424e 0x0 +.debug_str 0x7ae79 0x0 +.debug_loc 0x4626e 0x0 +Total 0xbd22de The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225456 + 222572 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51948 + 52092 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204D_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204D_REGION_EU_size.txt index 6408e08114..8bdd8716ea 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204D_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204D_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x36930 0x8006000 -_cc_handlers_v3 0x21c 0x803c930 -_zw_protocol_cmd_handlers 0x70 0x803cb4c -_zw_protocol_cmd_handlers_lr 0x30 0x803cbbc -.ARM.exidx 0x8 0x803cbec -.copy.table 0xc 0x803cbf4 -.zero.table 0x0 0x803cc00 +.text 0x35dcc 0x8006000 +_cc_handlers_v3 0x21c 0x803bdcc +_zw_protocol_cmd_handlers 0x70 0x803bfe8 +_zw_protocol_cmd_handlers_lr 0x30 0x803c058 +.ARM.exidx 0x8 0x803c088 +.copy.table 0xc 0x803c090 +.zero.table 0x0 0x803c09c .stack 0x1000 0x20000000 -.data 0x590 0x20001000 -.bss 0xad64 0x20001590 -.heap 0x3d08 0x2000c2f8 -.internal_storage 0x2a000 0x803cc00 -.zwave_nvm 0x6000 0x8066c00 -.nvm 0xa000 0x806cc00 +.data 0x598 0x20001000 +.bss 0xadec 0x20001598 +.heap 0x3c78 0x2000c388 +.internal_storage 0x2c000 0x803c09c +.zwave_nvm 0x6000 0x806809c +.nvm 0x8000 0x806e09c .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa5e8 0x0 -.debug_info 0xa21725 0x0 -.debug_abbrev 0x17032 0x0 -.debug_aranges 0x39a0 0x0 -.debug_ranges 0x7168 0x0 -.debug_line 0x44937 0x0 -.debug_str 0x7afbf 0x0 -.debug_loc 0x4668a 0x0 -Total 0xbd4442 +.debug_frame 0xa588 0x0 +.debug_info 0xa215ca 0x0 +.debug_abbrev 0x16e73 0x0 +.debug_aranges 0x3968 0x0 +.debug_ranges 0x6fd8 0x0 +.debug_line 0x4443d 0x0 +.debug_str 0x7b04c 0x0 +.debug_loc 0x4626e 0x0 +Total 0xbd2b13 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225680 + 222772 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51956 + 52100 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204D_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204D_REGION_US_LR_size.txt index 6408e08114..8bdd8716ea 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204D_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204D_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x36930 0x8006000 -_cc_handlers_v3 0x21c 0x803c930 -_zw_protocol_cmd_handlers 0x70 0x803cb4c -_zw_protocol_cmd_handlers_lr 0x30 0x803cbbc -.ARM.exidx 0x8 0x803cbec -.copy.table 0xc 0x803cbf4 -.zero.table 0x0 0x803cc00 +.text 0x35dcc 0x8006000 +_cc_handlers_v3 0x21c 0x803bdcc +_zw_protocol_cmd_handlers 0x70 0x803bfe8 +_zw_protocol_cmd_handlers_lr 0x30 0x803c058 +.ARM.exidx 0x8 0x803c088 +.copy.table 0xc 0x803c090 +.zero.table 0x0 0x803c09c .stack 0x1000 0x20000000 -.data 0x590 0x20001000 -.bss 0xad64 0x20001590 -.heap 0x3d08 0x2000c2f8 -.internal_storage 0x2a000 0x803cc00 -.zwave_nvm 0x6000 0x8066c00 -.nvm 0xa000 0x806cc00 +.data 0x598 0x20001000 +.bss 0xadec 0x20001598 +.heap 0x3c78 0x2000c388 +.internal_storage 0x2c000 0x803c09c +.zwave_nvm 0x6000 0x806809c +.nvm 0x8000 0x806e09c .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa5e8 0x0 -.debug_info 0xa21725 0x0 -.debug_abbrev 0x17032 0x0 -.debug_aranges 0x39a0 0x0 -.debug_ranges 0x7168 0x0 -.debug_line 0x44937 0x0 -.debug_str 0x7afbf 0x0 -.debug_loc 0x4668a 0x0 -Total 0xbd4442 +.debug_frame 0xa588 0x0 +.debug_info 0xa215ca 0x0 +.debug_abbrev 0x16e73 0x0 +.debug_aranges 0x3968 0x0 +.debug_ranges 0x6fd8 0x0 +.debug_line 0x4443d 0x0 +.debug_str 0x7b04c 0x0 +.debug_loc 0x4626e 0x0 +Total 0xbd2b13 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225680 + 222772 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51956 + 52100 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204D_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204D_REGION_US_size.txt index 6408e08114..8bdd8716ea 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204D_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4204D_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x36930 0x8006000 -_cc_handlers_v3 0x21c 0x803c930 -_zw_protocol_cmd_handlers 0x70 0x803cb4c -_zw_protocol_cmd_handlers_lr 0x30 0x803cbbc -.ARM.exidx 0x8 0x803cbec -.copy.table 0xc 0x803cbf4 -.zero.table 0x0 0x803cc00 +.text 0x35dcc 0x8006000 +_cc_handlers_v3 0x21c 0x803bdcc +_zw_protocol_cmd_handlers 0x70 0x803bfe8 +_zw_protocol_cmd_handlers_lr 0x30 0x803c058 +.ARM.exidx 0x8 0x803c088 +.copy.table 0xc 0x803c090 +.zero.table 0x0 0x803c09c .stack 0x1000 0x20000000 -.data 0x590 0x20001000 -.bss 0xad64 0x20001590 -.heap 0x3d08 0x2000c2f8 -.internal_storage 0x2a000 0x803cc00 -.zwave_nvm 0x6000 0x8066c00 -.nvm 0xa000 0x806cc00 +.data 0x598 0x20001000 +.bss 0xadec 0x20001598 +.heap 0x3c78 0x2000c388 +.internal_storage 0x2c000 0x803c09c +.zwave_nvm 0x6000 0x806809c +.nvm 0x8000 0x806e09c .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa5e8 0x0 -.debug_info 0xa21725 0x0 -.debug_abbrev 0x17032 0x0 -.debug_aranges 0x39a0 0x0 -.debug_ranges 0x7168 0x0 -.debug_line 0x44937 0x0 -.debug_str 0x7afbf 0x0 -.debug_loc 0x4668a 0x0 -Total 0xbd4442 +.debug_frame 0xa588 0x0 +.debug_info 0xa215ca 0x0 +.debug_abbrev 0x16e73 0x0 +.debug_aranges 0x3968 0x0 +.debug_ranges 0x6fd8 0x0 +.debug_line 0x4443d 0x0 +.debug_str 0x7b04c 0x0 +.debug_loc 0x4626e 0x0 +Total 0xbd2b13 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225680 + 222772 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51956 + 52100 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205A_REGION_EU_size.txt index 4d45fd93c9..897bcdb69a 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205A_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x36a60 0x8006000 -_cc_handlers_v3 0x21c 0x803ca60 -_zw_protocol_cmd_handlers 0x70 0x803cc7c -_zw_protocol_cmd_handlers_lr 0x30 0x803ccec -.ARM.exidx 0x8 0x803cd1c -.copy.table 0xc 0x803cd24 -.zero.table 0x0 0x803cd30 +.text 0x35c9c 0x8006000 +_cc_handlers_v3 0x21c 0x803bc9c +_zw_protocol_cmd_handlers 0x70 0x803beb8 +_zw_protocol_cmd_handlers_lr 0x30 0x803bf28 +.ARM.exidx 0x8 0x803bf58 +.copy.table 0xc 0x803bf60 +.zero.table 0x0 0x803bf6c .stack 0x1000 0x20000000 -.data 0x58c 0x20001000 -.bss 0xac50 0x2000158c -.heap 0x3e20 0x2000c1e0 -.internal_storage 0x2a000 0x803cd30 -.zwave_nvm 0x6000 0x8066d30 -.nvm 0xa000 0x806cd30 +.data 0x594 0x20001000 +.bss 0xacd0 0x20001594 +.heap 0x3d98 0x2000c268 +.internal_storage 0x2c000 0x803bf6c +.zwave_nvm 0x6000 0x8067f6c +.nvm 0x8000 0x806df6c .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa3a8 0x0 -.debug_info 0xa1fd15 0x0 -.debug_abbrev 0x17342 0x0 -.debug_aranges 0x3980 0x0 -.debug_ranges 0x7038 0x0 -.debug_line 0x435aa 0x0 -.debug_str 0x7b33e 0x0 -.debug_loc 0x4494c 0x0 -Total 0xbcfd96 +.debug_frame 0x9fc0 0x0 +.debug_info 0xa1d7b0 0x0 +.debug_abbrev 0x16af7 0x0 +.debug_aranges 0x3868 0x0 +.debug_ranges 0x6d98 0x0 +.debug_line 0x41ee2 0x0 +.debug_str 0x7ae1f 0x0 +.debug_loc 0x41bc0 0x0 +Total 0xbc710f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225980 + 222464 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51676 + 51812 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205A_REGION_US_LR_size.txt index 4d45fd93c9..897bcdb69a 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x36a60 0x8006000 -_cc_handlers_v3 0x21c 0x803ca60 -_zw_protocol_cmd_handlers 0x70 0x803cc7c -_zw_protocol_cmd_handlers_lr 0x30 0x803ccec -.ARM.exidx 0x8 0x803cd1c -.copy.table 0xc 0x803cd24 -.zero.table 0x0 0x803cd30 +.text 0x35c9c 0x8006000 +_cc_handlers_v3 0x21c 0x803bc9c +_zw_protocol_cmd_handlers 0x70 0x803beb8 +_zw_protocol_cmd_handlers_lr 0x30 0x803bf28 +.ARM.exidx 0x8 0x803bf58 +.copy.table 0xc 0x803bf60 +.zero.table 0x0 0x803bf6c .stack 0x1000 0x20000000 -.data 0x58c 0x20001000 -.bss 0xac50 0x2000158c -.heap 0x3e20 0x2000c1e0 -.internal_storage 0x2a000 0x803cd30 -.zwave_nvm 0x6000 0x8066d30 -.nvm 0xa000 0x806cd30 +.data 0x594 0x20001000 +.bss 0xacd0 0x20001594 +.heap 0x3d98 0x2000c268 +.internal_storage 0x2c000 0x803bf6c +.zwave_nvm 0x6000 0x8067f6c +.nvm 0x8000 0x806df6c .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa3a8 0x0 -.debug_info 0xa1fd15 0x0 -.debug_abbrev 0x17342 0x0 -.debug_aranges 0x3980 0x0 -.debug_ranges 0x7038 0x0 -.debug_line 0x435aa 0x0 -.debug_str 0x7b33e 0x0 -.debug_loc 0x4494c 0x0 -Total 0xbcfd96 +.debug_frame 0x9fc0 0x0 +.debug_info 0xa1d7b0 0x0 +.debug_abbrev 0x16af7 0x0 +.debug_aranges 0x3868 0x0 +.debug_ranges 0x6d98 0x0 +.debug_line 0x41ee2 0x0 +.debug_str 0x7ae1f 0x0 +.debug_loc 0x41bc0 0x0 +Total 0xbc710f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225980 + 222464 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51676 + 51812 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205A_REGION_US_size.txt index 4d45fd93c9..897bcdb69a 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205A_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x36a60 0x8006000 -_cc_handlers_v3 0x21c 0x803ca60 -_zw_protocol_cmd_handlers 0x70 0x803cc7c -_zw_protocol_cmd_handlers_lr 0x30 0x803ccec -.ARM.exidx 0x8 0x803cd1c -.copy.table 0xc 0x803cd24 -.zero.table 0x0 0x803cd30 +.text 0x35c9c 0x8006000 +_cc_handlers_v3 0x21c 0x803bc9c +_zw_protocol_cmd_handlers 0x70 0x803beb8 +_zw_protocol_cmd_handlers_lr 0x30 0x803bf28 +.ARM.exidx 0x8 0x803bf58 +.copy.table 0xc 0x803bf60 +.zero.table 0x0 0x803bf6c .stack 0x1000 0x20000000 -.data 0x58c 0x20001000 -.bss 0xac50 0x2000158c -.heap 0x3e20 0x2000c1e0 -.internal_storage 0x2a000 0x803cd30 -.zwave_nvm 0x6000 0x8066d30 -.nvm 0xa000 0x806cd30 +.data 0x594 0x20001000 +.bss 0xacd0 0x20001594 +.heap 0x3d98 0x2000c268 +.internal_storage 0x2c000 0x803bf6c +.zwave_nvm 0x6000 0x8067f6c +.nvm 0x8000 0x806df6c .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa3a8 0x0 -.debug_info 0xa1fd15 0x0 -.debug_abbrev 0x17342 0x0 -.debug_aranges 0x3980 0x0 -.debug_ranges 0x7038 0x0 -.debug_line 0x435aa 0x0 -.debug_str 0x7b33e 0x0 -.debug_loc 0x4494c 0x0 -Total 0xbcfd96 +.debug_frame 0x9fc0 0x0 +.debug_info 0xa1d7b0 0x0 +.debug_abbrev 0x16af7 0x0 +.debug_aranges 0x3868 0x0 +.debug_ranges 0x6d98 0x0 +.debug_line 0x41ee2 0x0 +.debug_str 0x7ae1f 0x0 +.debug_loc 0x41bc0 0x0 +Total 0xbc710f The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225980 + 222464 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51676 + 51812 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205B_REGION_EU_size.txt index 7e0c958ca2..89f99a309d 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205B_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x36db0 0x8006000 -_cc_handlers_v3 0x21c 0x803cdb0 -_zw_protocol_cmd_handlers 0x70 0x803cfcc -_zw_protocol_cmd_handlers_lr 0x30 0x803d03c -.ARM.exidx 0x8 0x803d06c -.copy.table 0xc 0x803d074 -.zero.table 0x0 0x803d080 +.text 0x36264 0x8006000 +_cc_handlers_v3 0x21c 0x803c264 +_zw_protocol_cmd_handlers 0x70 0x803c480 +_zw_protocol_cmd_handlers_lr 0x30 0x803c4f0 +.ARM.exidx 0x8 0x803c520 +.copy.table 0xc 0x803c528 +.zero.table 0x0 0x803c534 .stack 0x1000 0x20000000 -.data 0x58c 0x20001000 -.bss 0xad80 0x2000158c -.heap 0x3cf0 0x2000c310 -.internal_storage 0x2a000 0x803d080 -.zwave_nvm 0x6000 0x8067080 -.nvm 0xa000 0x806d080 +.data 0x594 0x20001000 +.bss 0xae08 0x20001594 +.heap 0x3c60 0x2000c3a0 +.internal_storage 0x2c000 0x803c534 +.zwave_nvm 0x6000 0x8068534 +.nvm 0x8000 0x806e534 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa5b8 0x0 -.debug_info 0xa21f3d 0x0 -.debug_abbrev 0x1708b 0x0 -.debug_aranges 0x39b0 0x0 -.debug_ranges 0x7158 0x0 -.debug_line 0x44756 0x0 -.debug_str 0x7b691 0x0 -.debug_loc 0x46677 0x0 -Total 0xbd55e1 +.debug_frame 0xa558 0x0 +.debug_info 0xa21de2 0x0 +.debug_abbrev 0x16ecc 0x0 +.debug_aranges 0x3978 0x0 +.debug_ranges 0x6fc8 0x0 +.debug_line 0x4425c 0x0 +.debug_str 0x7b71d 0x0 +.debug_loc 0x4625e 0x0 +Total 0xbd3ccc The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 226828 + 223944 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51980 + 52124 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205B_REGION_US_LR_size.txt index 7e0c958ca2..89f99a309d 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205B_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x36db0 0x8006000 -_cc_handlers_v3 0x21c 0x803cdb0 -_zw_protocol_cmd_handlers 0x70 0x803cfcc -_zw_protocol_cmd_handlers_lr 0x30 0x803d03c -.ARM.exidx 0x8 0x803d06c -.copy.table 0xc 0x803d074 -.zero.table 0x0 0x803d080 +.text 0x36264 0x8006000 +_cc_handlers_v3 0x21c 0x803c264 +_zw_protocol_cmd_handlers 0x70 0x803c480 +_zw_protocol_cmd_handlers_lr 0x30 0x803c4f0 +.ARM.exidx 0x8 0x803c520 +.copy.table 0xc 0x803c528 +.zero.table 0x0 0x803c534 .stack 0x1000 0x20000000 -.data 0x58c 0x20001000 -.bss 0xad80 0x2000158c -.heap 0x3cf0 0x2000c310 -.internal_storage 0x2a000 0x803d080 -.zwave_nvm 0x6000 0x8067080 -.nvm 0xa000 0x806d080 +.data 0x594 0x20001000 +.bss 0xae08 0x20001594 +.heap 0x3c60 0x2000c3a0 +.internal_storage 0x2c000 0x803c534 +.zwave_nvm 0x6000 0x8068534 +.nvm 0x8000 0x806e534 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa5b8 0x0 -.debug_info 0xa21f3d 0x0 -.debug_abbrev 0x1708b 0x0 -.debug_aranges 0x39b0 0x0 -.debug_ranges 0x7158 0x0 -.debug_line 0x44756 0x0 -.debug_str 0x7b691 0x0 -.debug_loc 0x46677 0x0 -Total 0xbd55e1 +.debug_frame 0xa558 0x0 +.debug_info 0xa21de2 0x0 +.debug_abbrev 0x16ecc 0x0 +.debug_aranges 0x3978 0x0 +.debug_ranges 0x6fc8 0x0 +.debug_line 0x4425c 0x0 +.debug_str 0x7b71d 0x0 +.debug_loc 0x4625e 0x0 +Total 0xbd3ccc The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 226828 + 223944 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51980 + 52124 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205B_REGION_US_size.txt index 7e0c958ca2..89f99a309d 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4205B_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x36db0 0x8006000 -_cc_handlers_v3 0x21c 0x803cdb0 -_zw_protocol_cmd_handlers 0x70 0x803cfcc -_zw_protocol_cmd_handlers_lr 0x30 0x803d03c -.ARM.exidx 0x8 0x803d06c -.copy.table 0xc 0x803d074 -.zero.table 0x0 0x803d080 +.text 0x36264 0x8006000 +_cc_handlers_v3 0x21c 0x803c264 +_zw_protocol_cmd_handlers 0x70 0x803c480 +_zw_protocol_cmd_handlers_lr 0x30 0x803c4f0 +.ARM.exidx 0x8 0x803c520 +.copy.table 0xc 0x803c528 +.zero.table 0x0 0x803c534 .stack 0x1000 0x20000000 -.data 0x58c 0x20001000 -.bss 0xad80 0x2000158c -.heap 0x3cf0 0x2000c310 -.internal_storage 0x2a000 0x803d080 -.zwave_nvm 0x6000 0x8067080 -.nvm 0xa000 0x806d080 +.data 0x594 0x20001000 +.bss 0xae08 0x20001594 +.heap 0x3c60 0x2000c3a0 +.internal_storage 0x2c000 0x803c534 +.zwave_nvm 0x6000 0x8068534 +.nvm 0x8000 0x806e534 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa5b8 0x0 -.debug_info 0xa21f3d 0x0 -.debug_abbrev 0x1708b 0x0 -.debug_aranges 0x39b0 0x0 -.debug_ranges 0x7158 0x0 -.debug_line 0x44756 0x0 -.debug_str 0x7b691 0x0 -.debug_loc 0x46677 0x0 -Total 0xbd55e1 +.debug_frame 0xa558 0x0 +.debug_info 0xa21de2 0x0 +.debug_abbrev 0x16ecc 0x0 +.debug_aranges 0x3978 0x0 +.debug_ranges 0x6fc8 0x0 +.debug_line 0x4425c 0x0 +.debug_str 0x7b71d 0x0 +.debug_loc 0x4625e 0x0 +Total 0xbd3ccc The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 226828 + 223944 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51980 + 52124 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4207A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4207A_REGION_EU_size.txt index 7c5f7733af..f9beefd8b2 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4207A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4207A_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x2ea9c 0x0 -_cc_handlers_v3 0x21c 0x2ea9c -_zw_protocol_cmd_handlers 0x70 0x2ecb8 -_zw_protocol_cmd_handlers_lr 0x30 0x2ed28 -.ARM.exidx 0x8 0x2ed58 -.copy.table 0xc 0x2ed60 -.zero.table 0x0 0x2ed6c +.text 0x2ec18 0x0 +_cc_handlers_v3 0x21c 0x2ec18 +_zw_protocol_cmd_handlers 0x70 0x2ee34 +_zw_protocol_cmd_handlers_lr 0x30 0x2eea4 +.ARM.exidx 0x8 0x2eed4 +.copy.table 0xc 0x2eedc +.zero.table 0x0 0x2eee8 .stack 0x1000 0x20000000 -.data 0x434 0x20001000 -.bss 0x9e40 0x20001434 -.heap 0x4d88 0x2000b278 -.internal_storage 0x3a000 0x2ed6c -.zwave_nvm 0x3000 0x68d6c -.nvm 0x9000 0x6bd6c +.data 0x43c 0x20001000 +.bss 0x9ec0 0x2000143c +.heap 0x4d00 0x2000b300 +.internal_storage 0x3a000 0x2eee8 +.zwave_nvm 0x3000 0x68ee8 +.nvm 0x9000 0x6bee8 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6f9c 0x0 -.debug_info 0x9d94f1 0x0 -.debug_abbrev 0x11595 0x0 +.debug_frame 0x6fbc 0x0 +.debug_info 0x9d9d15 0x0 +.debug_abbrev 0x11649 0x0 .debug_aranges 0x2a10 0x0 -.debug_ranges 0x5010 0x0 -.debug_line 0x2e18a 0x0 -.debug_str 0x6fdde 0x0 -.debug_loc 0x27a2d 0x0 -Total 0xb43bb6 +.debug_ranges 0x4fe0 0x0 +.debug_line 0x2e21f 0x0 +.debug_str 0x6ff46 0x0 +.debug_loc 0x27b26 0x0 +Total 0xb448f0 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 192928 + 193316 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47732 + 47868 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4207A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4207A_REGION_US_LR_size.txt index 7c5f7733af..f9beefd8b2 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4207A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4207A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x2ea9c 0x0 -_cc_handlers_v3 0x21c 0x2ea9c -_zw_protocol_cmd_handlers 0x70 0x2ecb8 -_zw_protocol_cmd_handlers_lr 0x30 0x2ed28 -.ARM.exidx 0x8 0x2ed58 -.copy.table 0xc 0x2ed60 -.zero.table 0x0 0x2ed6c +.text 0x2ec18 0x0 +_cc_handlers_v3 0x21c 0x2ec18 +_zw_protocol_cmd_handlers 0x70 0x2ee34 +_zw_protocol_cmd_handlers_lr 0x30 0x2eea4 +.ARM.exidx 0x8 0x2eed4 +.copy.table 0xc 0x2eedc +.zero.table 0x0 0x2eee8 .stack 0x1000 0x20000000 -.data 0x434 0x20001000 -.bss 0x9e40 0x20001434 -.heap 0x4d88 0x2000b278 -.internal_storage 0x3a000 0x2ed6c -.zwave_nvm 0x3000 0x68d6c -.nvm 0x9000 0x6bd6c +.data 0x43c 0x20001000 +.bss 0x9ec0 0x2000143c +.heap 0x4d00 0x2000b300 +.internal_storage 0x3a000 0x2eee8 +.zwave_nvm 0x3000 0x68ee8 +.nvm 0x9000 0x6bee8 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6f9c 0x0 -.debug_info 0x9d94f1 0x0 -.debug_abbrev 0x11595 0x0 +.debug_frame 0x6fbc 0x0 +.debug_info 0x9d9d15 0x0 +.debug_abbrev 0x11649 0x0 .debug_aranges 0x2a10 0x0 -.debug_ranges 0x5010 0x0 -.debug_line 0x2e18a 0x0 -.debug_str 0x6fdde 0x0 -.debug_loc 0x27a2d 0x0 -Total 0xb43bb6 +.debug_ranges 0x4fe0 0x0 +.debug_line 0x2e21f 0x0 +.debug_str 0x6ff46 0x0 +.debug_loc 0x27b26 0x0 +Total 0xb448f0 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 192928 + 193316 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47732 + 47868 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4207A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4207A_REGION_US_size.txt index 7c5f7733af..f9beefd8b2 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4207A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4207A_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x2ea9c 0x0 -_cc_handlers_v3 0x21c 0x2ea9c -_zw_protocol_cmd_handlers 0x70 0x2ecb8 -_zw_protocol_cmd_handlers_lr 0x30 0x2ed28 -.ARM.exidx 0x8 0x2ed58 -.copy.table 0xc 0x2ed60 -.zero.table 0x0 0x2ed6c +.text 0x2ec18 0x0 +_cc_handlers_v3 0x21c 0x2ec18 +_zw_protocol_cmd_handlers 0x70 0x2ee34 +_zw_protocol_cmd_handlers_lr 0x30 0x2eea4 +.ARM.exidx 0x8 0x2eed4 +.copy.table 0xc 0x2eedc +.zero.table 0x0 0x2eee8 .stack 0x1000 0x20000000 -.data 0x434 0x20001000 -.bss 0x9e40 0x20001434 -.heap 0x4d88 0x2000b278 -.internal_storage 0x3a000 0x2ed6c -.zwave_nvm 0x3000 0x68d6c -.nvm 0x9000 0x6bd6c +.data 0x43c 0x20001000 +.bss 0x9ec0 0x2000143c +.heap 0x4d00 0x2000b300 +.internal_storage 0x3a000 0x2eee8 +.zwave_nvm 0x3000 0x68ee8 +.nvm 0x9000 0x6bee8 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6f9c 0x0 -.debug_info 0x9d94f1 0x0 -.debug_abbrev 0x11595 0x0 +.debug_frame 0x6fbc 0x0 +.debug_info 0x9d9d15 0x0 +.debug_abbrev 0x11649 0x0 .debug_aranges 0x2a10 0x0 -.debug_ranges 0x5010 0x0 -.debug_line 0x2e18a 0x0 -.debug_str 0x6fdde 0x0 -.debug_loc 0x27a2d 0x0 -Total 0xb43bb6 +.debug_ranges 0x4fe0 0x0 +.debug_line 0x2e21f 0x0 +.debug_str 0x6ff46 0x0 +.debug_loc 0x27b26 0x0 +Total 0xb448f0 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 192928 + 193316 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47732 + 47868 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4209A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4209A_REGION_US_LR_size.txt index a81b422581..bb4801d01a 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4209A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4209A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x2ea58 0x0 -_cc_handlers_v3 0x21c 0x2ea58 -_zw_protocol_cmd_handlers 0x70 0x2ec74 -_zw_protocol_cmd_handlers_lr 0x30 0x2ece4 -.ARM.exidx 0x8 0x2ed14 -.copy.table 0xc 0x2ed1c -.zero.table 0x0 0x2ed28 +.text 0x2eba4 0x0 +_cc_handlers_v3 0x21c 0x2eba4 +_zw_protocol_cmd_handlers 0x70 0x2edc0 +_zw_protocol_cmd_handlers_lr 0x30 0x2ee30 +.ARM.exidx 0x8 0x2ee60 +.copy.table 0xc 0x2ee68 +.zero.table 0x0 0x2ee74 .stack 0x1000 0x20000000 -.data 0x430 0x20001000 -.bss 0x9e24 0x20001430 -.heap 0x4da8 0x2000b258 -.internal_storage 0x3a000 0x2ed28 -.zwave_nvm 0x3000 0x68d28 -.nvm 0x9000 0x6bd28 +.data 0x438 0x20001000 +.bss 0x9ea4 0x20001438 +.heap 0x4d20 0x2000b2e0 +.internal_storage 0x3a000 0x2ee74 +.zwave_nvm 0x3000 0x68e74 +.nvm 0x9000 0x6be74 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x71cc 0x0 -.debug_info 0x9dadc4 0x0 -.debug_abbrev 0x11aff 0x0 +.debug_frame 0x71ec 0x0 +.debug_info 0x9db5e8 0x0 +.debug_abbrev 0x11bb3 0x0 .debug_aranges 0x2af0 0x0 -.debug_ranges 0x51f8 0x0 -.debug_line 0x2f1ee 0x0 -.debug_str 0x701ce 0x0 -.debug_loc 0x2853c 0x0 -Total 0xb47e0a +.debug_ranges 0x51c8 0x0 +.debug_line 0x2f283 0x0 +.debug_str 0x70337 0x0 +.debug_loc 0x28635 0x0 +Total 0xb48b15 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 192856 + 193196 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47700 + 47836 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4210A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4210A_REGION_US_LR_size.txt index 6408e08114..8bdd8716ea 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4210A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_sensor_pir_BRD4210A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_sensor_pir.out : section size addr -.text 0x36930 0x8006000 -_cc_handlers_v3 0x21c 0x803c930 -_zw_protocol_cmd_handlers 0x70 0x803cb4c -_zw_protocol_cmd_handlers_lr 0x30 0x803cbbc -.ARM.exidx 0x8 0x803cbec -.copy.table 0xc 0x803cbf4 -.zero.table 0x0 0x803cc00 +.text 0x35dcc 0x8006000 +_cc_handlers_v3 0x21c 0x803bdcc +_zw_protocol_cmd_handlers 0x70 0x803bfe8 +_zw_protocol_cmd_handlers_lr 0x30 0x803c058 +.ARM.exidx 0x8 0x803c088 +.copy.table 0xc 0x803c090 +.zero.table 0x0 0x803c09c .stack 0x1000 0x20000000 -.data 0x590 0x20001000 -.bss 0xad64 0x20001590 -.heap 0x3d08 0x2000c2f8 -.internal_storage 0x2a000 0x803cc00 -.zwave_nvm 0x6000 0x8066c00 -.nvm 0xa000 0x806cc00 +.data 0x598 0x20001000 +.bss 0xadec 0x20001598 +.heap 0x3c78 0x2000c388 +.internal_storage 0x2c000 0x803c09c +.zwave_nvm 0x6000 0x806809c +.nvm 0x8000 0x806e09c .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0xa5e8 0x0 -.debug_info 0xa21725 0x0 -.debug_abbrev 0x17032 0x0 -.debug_aranges 0x39a0 0x0 -.debug_ranges 0x7168 0x0 -.debug_line 0x44937 0x0 -.debug_str 0x7afbf 0x0 -.debug_loc 0x4668a 0x0 -Total 0xbd4442 +.debug_frame 0xa588 0x0 +.debug_info 0xa215ca 0x0 +.debug_abbrev 0x16e73 0x0 +.debug_aranges 0x3968 0x0 +.debug_ranges 0x6fd8 0x0 +.debug_line 0x4443d 0x0 +.debug_str 0x7b04c 0x0 +.debug_loc 0x4626e 0x0 +Total 0xbd2b13 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 225680 + 222772 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51956 + 52100 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2603A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2603A_REGION_EU_size.txt index 2e58b97d25..69ec3b6cde 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2603A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2603A_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x3572c 0x8006000 -_cc_handlers_v3 0x1f8 0x803b72c -_zw_protocol_cmd_handlers 0x70 0x803b924 -_zw_protocol_cmd_handlers_lr 0x30 0x803b994 -.ARM.exidx 0x8 0x803b9c4 -.copy.table 0xc 0x803b9cc -.zero.table 0x0 0x803b9d8 +.text 0x34bb8 0x8006000 +_cc_handlers_v3 0x1f8 0x803abb8 +_zw_protocol_cmd_handlers 0x70 0x803adb0 +_zw_protocol_cmd_handlers_lr 0x30 0x803ae20 +.ARM.exidx 0x8 0x803ae50 +.copy.table 0xc 0x803ae58 +.zero.table 0x0 0x803ae64 .stack 0x1000 0x20000000 -.data 0x558 0x20001000 -.bss 0xaca4 0x20001558 -.heap 0x3e00 0x2000c200 -.internal_storage 0x2a000 0x803b9d8 -.zwave_nvm 0x6000 0x80659d8 -.nvm 0xa000 0x806b9d8 +.data 0x560 0x20001000 +.bss 0xad24 0x20001560 +.heap 0x3d78 0x2000c288 +.internal_storage 0x2c000 0x803ae64 +.zwave_nvm 0x6000 0x8066e64 +.nvm 0x8000 0x806ce64 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9ea4 0x0 -.debug_info 0x9b1913 0x0 -.debug_abbrev 0x158e4 0x0 -.debug_loc 0x440d3 0x0 -.debug_aranges 0x3710 0x0 -.debug_ranges 0x6c68 0x0 -.debug_line 0x40c9c 0x0 -.debug_str 0x78b21 0x0 -Total 0xb586f6 +.debug_frame 0x9e30 0x0 +.debug_info 0x9b15dc 0x0 +.debug_abbrev 0x156c9 0x0 +.debug_loc 0x43c62 0x0 +.debug_aranges 0x36d8 0x0 +.debug_ranges 0x6b20 0x0 +.debug_line 0x4076e 0x0 +.debug_str 0x78b77 0x0 +Total 0xb56af3 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 220976 + 218052 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51708 + 51844 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2603A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2603A_REGION_US_LR_size.txt index 2e58b97d25..69ec3b6cde 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2603A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2603A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x3572c 0x8006000 -_cc_handlers_v3 0x1f8 0x803b72c -_zw_protocol_cmd_handlers 0x70 0x803b924 -_zw_protocol_cmd_handlers_lr 0x30 0x803b994 -.ARM.exidx 0x8 0x803b9c4 -.copy.table 0xc 0x803b9cc -.zero.table 0x0 0x803b9d8 +.text 0x34bb8 0x8006000 +_cc_handlers_v3 0x1f8 0x803abb8 +_zw_protocol_cmd_handlers 0x70 0x803adb0 +_zw_protocol_cmd_handlers_lr 0x30 0x803ae20 +.ARM.exidx 0x8 0x803ae50 +.copy.table 0xc 0x803ae58 +.zero.table 0x0 0x803ae64 .stack 0x1000 0x20000000 -.data 0x558 0x20001000 -.bss 0xaca4 0x20001558 -.heap 0x3e00 0x2000c200 -.internal_storage 0x2a000 0x803b9d8 -.zwave_nvm 0x6000 0x80659d8 -.nvm 0xa000 0x806b9d8 +.data 0x560 0x20001000 +.bss 0xad24 0x20001560 +.heap 0x3d78 0x2000c288 +.internal_storage 0x2c000 0x803ae64 +.zwave_nvm 0x6000 0x8066e64 +.nvm 0x8000 0x806ce64 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9ea4 0x0 -.debug_info 0x9b1913 0x0 -.debug_abbrev 0x158e4 0x0 -.debug_loc 0x440d3 0x0 -.debug_aranges 0x3710 0x0 -.debug_ranges 0x6c68 0x0 -.debug_line 0x40c9c 0x0 -.debug_str 0x78b21 0x0 -Total 0xb586f6 +.debug_frame 0x9e30 0x0 +.debug_info 0x9b15dc 0x0 +.debug_abbrev 0x156c9 0x0 +.debug_loc 0x43c62 0x0 +.debug_aranges 0x36d8 0x0 +.debug_ranges 0x6b20 0x0 +.debug_line 0x4076e 0x0 +.debug_str 0x78b77 0x0 +Total 0xb56af3 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 220976 + 218052 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51708 + 51844 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2603A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2603A_REGION_US_size.txt index 2e58b97d25..69ec3b6cde 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2603A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD2603A_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x3572c 0x8006000 -_cc_handlers_v3 0x1f8 0x803b72c -_zw_protocol_cmd_handlers 0x70 0x803b924 -_zw_protocol_cmd_handlers_lr 0x30 0x803b994 -.ARM.exidx 0x8 0x803b9c4 -.copy.table 0xc 0x803b9cc -.zero.table 0x0 0x803b9d8 +.text 0x34bb8 0x8006000 +_cc_handlers_v3 0x1f8 0x803abb8 +_zw_protocol_cmd_handlers 0x70 0x803adb0 +_zw_protocol_cmd_handlers_lr 0x30 0x803ae20 +.ARM.exidx 0x8 0x803ae50 +.copy.table 0xc 0x803ae58 +.zero.table 0x0 0x803ae64 .stack 0x1000 0x20000000 -.data 0x558 0x20001000 -.bss 0xaca4 0x20001558 -.heap 0x3e00 0x2000c200 -.internal_storage 0x2a000 0x803b9d8 -.zwave_nvm 0x6000 0x80659d8 -.nvm 0xa000 0x806b9d8 +.data 0x560 0x20001000 +.bss 0xad24 0x20001560 +.heap 0x3d78 0x2000c288 +.internal_storage 0x2c000 0x803ae64 +.zwave_nvm 0x6000 0x8066e64 +.nvm 0x8000 0x806ce64 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9ea4 0x0 -.debug_info 0x9b1913 0x0 -.debug_abbrev 0x158e4 0x0 -.debug_loc 0x440d3 0x0 -.debug_aranges 0x3710 0x0 -.debug_ranges 0x6c68 0x0 -.debug_line 0x40c9c 0x0 -.debug_str 0x78b21 0x0 -Total 0xb586f6 +.debug_frame 0x9e30 0x0 +.debug_info 0x9b15dc 0x0 +.debug_abbrev 0x156c9 0x0 +.debug_loc 0x43c62 0x0 +.debug_aranges 0x36d8 0x0 +.debug_ranges 0x6b20 0x0 +.debug_line 0x4076e 0x0 +.debug_str 0x78b77 0x0 +Total 0xb56af3 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 220976 + 218052 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51708 + 51844 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4202A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4202A_REGION_EU_size.txt index 6ebf2f6292..11c2276631 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4202A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4202A_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x2d69c 0x0 -_cc_handlers_v3 0x1f8 0x2d69c -_zw_protocol_cmd_handlers 0x70 0x2d894 -_zw_protocol_cmd_handlers_lr 0x30 0x2d904 -.ARM.exidx 0x8 0x2d934 -.copy.table 0xc 0x2d93c -.zero.table 0x0 0x2d948 +.text 0x2d7f8 0x0 +_cc_handlers_v3 0x1f8 0x2d7f8 +_zw_protocol_cmd_handlers 0x70 0x2d9f0 +_zw_protocol_cmd_handlers_lr 0x30 0x2da60 +.ARM.exidx 0x8 0x2da90 +.copy.table 0xc 0x2da98 +.zero.table 0x0 0x2daa4 .stack 0x1000 0x20000000 -.data 0x3fc 0x20001000 -.bss 0x9d58 0x200013fc -.heap 0x4ea8 0x2000b158 -.internal_storage 0x3a000 0x2d948 -.zwave_nvm 0x3000 0x67948 -.nvm 0x9000 0x6a948 +.data 0x404 0x20001000 +.bss 0x9de0 0x20001404 +.heap 0x4e18 0x2000b1e8 +.internal_storage 0x3a000 0x2daa4 +.zwave_nvm 0x3000 0x67aa4 +.nvm 0x9000 0x6aaa4 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6a74 0x0 -.debug_info 0x96c402 0x0 -.debug_abbrev 0x102ab 0x0 -.debug_loc 0x25ce0 0x0 +.debug_frame 0x6a80 0x0 +.debug_info 0x96ca4e 0x0 +.debug_abbrev 0x1030e 0x0 +.debug_loc 0x25d05 0x0 .debug_aranges 0x2818 0x0 -.debug_ranges 0x4cf8 0x0 -.debug_line 0x2b3e6 0x0 -.debug_str 0x6c98f 0x0 -Total 0xacba41 +.debug_ranges 0x4ce0 0x0 +.debug_line 0x2b43f 0x0 +.debug_str 0x6cac1 0x0 +Total 0xacc3f0 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 187716 + 188072 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47444 + 47588 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4202A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4202A_REGION_US_LR_size.txt index 6ebf2f6292..11c2276631 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4202A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4202A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x2d69c 0x0 -_cc_handlers_v3 0x1f8 0x2d69c -_zw_protocol_cmd_handlers 0x70 0x2d894 -_zw_protocol_cmd_handlers_lr 0x30 0x2d904 -.ARM.exidx 0x8 0x2d934 -.copy.table 0xc 0x2d93c -.zero.table 0x0 0x2d948 +.text 0x2d7f8 0x0 +_cc_handlers_v3 0x1f8 0x2d7f8 +_zw_protocol_cmd_handlers 0x70 0x2d9f0 +_zw_protocol_cmd_handlers_lr 0x30 0x2da60 +.ARM.exidx 0x8 0x2da90 +.copy.table 0xc 0x2da98 +.zero.table 0x0 0x2daa4 .stack 0x1000 0x20000000 -.data 0x3fc 0x20001000 -.bss 0x9d58 0x200013fc -.heap 0x4ea8 0x2000b158 -.internal_storage 0x3a000 0x2d948 -.zwave_nvm 0x3000 0x67948 -.nvm 0x9000 0x6a948 +.data 0x404 0x20001000 +.bss 0x9de0 0x20001404 +.heap 0x4e18 0x2000b1e8 +.internal_storage 0x3a000 0x2daa4 +.zwave_nvm 0x3000 0x67aa4 +.nvm 0x9000 0x6aaa4 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6a74 0x0 -.debug_info 0x96c402 0x0 -.debug_abbrev 0x102ab 0x0 -.debug_loc 0x25ce0 0x0 +.debug_frame 0x6a80 0x0 +.debug_info 0x96ca4e 0x0 +.debug_abbrev 0x1030e 0x0 +.debug_loc 0x25d05 0x0 .debug_aranges 0x2818 0x0 -.debug_ranges 0x4cf8 0x0 -.debug_line 0x2b3e6 0x0 -.debug_str 0x6c98f 0x0 -Total 0xacba41 +.debug_ranges 0x4ce0 0x0 +.debug_line 0x2b43f 0x0 +.debug_str 0x6cac1 0x0 +Total 0xacc3f0 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 187716 + 188072 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47444 + 47588 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4202A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4202A_REGION_US_size.txt index 6ebf2f6292..11c2276631 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4202A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4202A_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x2d69c 0x0 -_cc_handlers_v3 0x1f8 0x2d69c -_zw_protocol_cmd_handlers 0x70 0x2d894 -_zw_protocol_cmd_handlers_lr 0x30 0x2d904 -.ARM.exidx 0x8 0x2d934 -.copy.table 0xc 0x2d93c -.zero.table 0x0 0x2d948 +.text 0x2d7f8 0x0 +_cc_handlers_v3 0x1f8 0x2d7f8 +_zw_protocol_cmd_handlers 0x70 0x2d9f0 +_zw_protocol_cmd_handlers_lr 0x30 0x2da60 +.ARM.exidx 0x8 0x2da90 +.copy.table 0xc 0x2da98 +.zero.table 0x0 0x2daa4 .stack 0x1000 0x20000000 -.data 0x3fc 0x20001000 -.bss 0x9d58 0x200013fc -.heap 0x4ea8 0x2000b158 -.internal_storage 0x3a000 0x2d948 -.zwave_nvm 0x3000 0x67948 -.nvm 0x9000 0x6a948 +.data 0x404 0x20001000 +.bss 0x9de0 0x20001404 +.heap 0x4e18 0x2000b1e8 +.internal_storage 0x3a000 0x2daa4 +.zwave_nvm 0x3000 0x67aa4 +.nvm 0x9000 0x6aaa4 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6a74 0x0 -.debug_info 0x96c402 0x0 -.debug_abbrev 0x102ab 0x0 -.debug_loc 0x25ce0 0x0 +.debug_frame 0x6a80 0x0 +.debug_info 0x96ca4e 0x0 +.debug_abbrev 0x1030e 0x0 +.debug_loc 0x25d05 0x0 .debug_aranges 0x2818 0x0 -.debug_ranges 0x4cf8 0x0 -.debug_line 0x2b3e6 0x0 -.debug_str 0x6c98f 0x0 -Total 0xacba41 +.debug_ranges 0x4ce0 0x0 +.debug_line 0x2b43f 0x0 +.debug_str 0x6cac1 0x0 +Total 0xacc3f0 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 187716 + 188072 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47444 + 47588 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204C_REGION_EU_size.txt index 5c4df857d4..ec11b38f56 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204C_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x35204 0x8006000 -_cc_handlers_v3 0x1f8 0x803b204 -_zw_protocol_cmd_handlers 0x70 0x803b3fc -_zw_protocol_cmd_handlers_lr 0x30 0x803b46c -.ARM.exidx 0x8 0x803b49c -.copy.table 0xc 0x803b4a4 -.zero.table 0x0 0x803b4b0 +.text 0x34690 0x8006000 +_cc_handlers_v3 0x1f8 0x803a690 +_zw_protocol_cmd_handlers 0x70 0x803a888 +_zw_protocol_cmd_handlers_lr 0x30 0x803a8f8 +.ARM.exidx 0x8 0x803a928 +.copy.table 0xc 0x803a930 +.zero.table 0x0 0x803a93c .stack 0x1000 0x20000000 -.data 0x554 0x20001000 -.bss 0xac80 0x20001554 -.heap 0x3e28 0x2000c1d8 -.internal_storage 0x2a000 0x803b4b0 -.zwave_nvm 0x6000 0x80654b0 -.nvm 0xa000 0x806b4b0 +.data 0x55c 0x20001000 +.bss 0xad00 0x2000155c +.heap 0x3da0 0x2000c260 +.internal_storage 0x2c000 0x803a93c +.zwave_nvm 0x6000 0x806693c +.nvm 0x8000 0x806c93c .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9fa8 0x0 -.debug_info 0x9b3463 0x0 -.debug_abbrev 0x15b67 0x0 -.debug_loc 0x444b6 0x0 -.debug_aranges 0x3758 0x0 -.debug_ranges 0x6d00 0x0 -.debug_line 0x41421 0x0 -.debug_str 0x78525 0x0 -Total 0xb5a6f1 +.debug_frame 0x9f34 0x0 +.debug_info 0x9b312c 0x0 +.debug_abbrev 0x1594c 0x0 +.debug_loc 0x44042 0x0 +.debug_aranges 0x3720 0x0 +.debug_ranges 0x6bb8 0x0 +.debug_line 0x40ef3 0x0 +.debug_str 0x7857c 0x0 +Total 0xb58aec The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 219652 + 216728 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51668 + 51804 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204C_REGION_US_LR_size.txt index 5c4df857d4..ec11b38f56 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204C_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x35204 0x8006000 -_cc_handlers_v3 0x1f8 0x803b204 -_zw_protocol_cmd_handlers 0x70 0x803b3fc -_zw_protocol_cmd_handlers_lr 0x30 0x803b46c -.ARM.exidx 0x8 0x803b49c -.copy.table 0xc 0x803b4a4 -.zero.table 0x0 0x803b4b0 +.text 0x34690 0x8006000 +_cc_handlers_v3 0x1f8 0x803a690 +_zw_protocol_cmd_handlers 0x70 0x803a888 +_zw_protocol_cmd_handlers_lr 0x30 0x803a8f8 +.ARM.exidx 0x8 0x803a928 +.copy.table 0xc 0x803a930 +.zero.table 0x0 0x803a93c .stack 0x1000 0x20000000 -.data 0x554 0x20001000 -.bss 0xac80 0x20001554 -.heap 0x3e28 0x2000c1d8 -.internal_storage 0x2a000 0x803b4b0 -.zwave_nvm 0x6000 0x80654b0 -.nvm 0xa000 0x806b4b0 +.data 0x55c 0x20001000 +.bss 0xad00 0x2000155c +.heap 0x3da0 0x2000c260 +.internal_storage 0x2c000 0x803a93c +.zwave_nvm 0x6000 0x806693c +.nvm 0x8000 0x806c93c .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9fa8 0x0 -.debug_info 0x9b3463 0x0 -.debug_abbrev 0x15b67 0x0 -.debug_loc 0x444b6 0x0 -.debug_aranges 0x3758 0x0 -.debug_ranges 0x6d00 0x0 -.debug_line 0x41421 0x0 -.debug_str 0x78525 0x0 -Total 0xb5a6f1 +.debug_frame 0x9f34 0x0 +.debug_info 0x9b312c 0x0 +.debug_abbrev 0x1594c 0x0 +.debug_loc 0x44042 0x0 +.debug_aranges 0x3720 0x0 +.debug_ranges 0x6bb8 0x0 +.debug_line 0x40ef3 0x0 +.debug_str 0x7857c 0x0 +Total 0xb58aec The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 219652 + 216728 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51668 + 51804 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204C_REGION_US_size.txt index 5c4df857d4..ec11b38f56 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204C_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x35204 0x8006000 -_cc_handlers_v3 0x1f8 0x803b204 -_zw_protocol_cmd_handlers 0x70 0x803b3fc -_zw_protocol_cmd_handlers_lr 0x30 0x803b46c -.ARM.exidx 0x8 0x803b49c -.copy.table 0xc 0x803b4a4 -.zero.table 0x0 0x803b4b0 +.text 0x34690 0x8006000 +_cc_handlers_v3 0x1f8 0x803a690 +_zw_protocol_cmd_handlers 0x70 0x803a888 +_zw_protocol_cmd_handlers_lr 0x30 0x803a8f8 +.ARM.exidx 0x8 0x803a928 +.copy.table 0xc 0x803a930 +.zero.table 0x0 0x803a93c .stack 0x1000 0x20000000 -.data 0x554 0x20001000 -.bss 0xac80 0x20001554 -.heap 0x3e28 0x2000c1d8 -.internal_storage 0x2a000 0x803b4b0 -.zwave_nvm 0x6000 0x80654b0 -.nvm 0xa000 0x806b4b0 +.data 0x55c 0x20001000 +.bss 0xad00 0x2000155c +.heap 0x3da0 0x2000c260 +.internal_storage 0x2c000 0x803a93c +.zwave_nvm 0x6000 0x806693c +.nvm 0x8000 0x806c93c .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9fa8 0x0 -.debug_info 0x9b3463 0x0 -.debug_abbrev 0x15b67 0x0 -.debug_loc 0x444b6 0x0 -.debug_aranges 0x3758 0x0 -.debug_ranges 0x6d00 0x0 -.debug_line 0x41421 0x0 -.debug_str 0x78525 0x0 -Total 0xb5a6f1 +.debug_frame 0x9f34 0x0 +.debug_info 0x9b312c 0x0 +.debug_abbrev 0x1594c 0x0 +.debug_loc 0x44042 0x0 +.debug_aranges 0x3720 0x0 +.debug_ranges 0x6bb8 0x0 +.debug_line 0x40ef3 0x0 +.debug_str 0x7857c 0x0 +Total 0xb58aec The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 219652 + 216728 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51668 + 51804 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204D_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204D_REGION_EU_size.txt index 8939a157d6..80e6741796 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204D_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204D_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x352d0 0x8006000 -_cc_handlers_v3 0x1f8 0x803b2d0 -_zw_protocol_cmd_handlers 0x70 0x803b4c8 -_zw_protocol_cmd_handlers_lr 0x30 0x803b538 -.ARM.exidx 0x8 0x803b568 -.copy.table 0xc 0x803b570 -.zero.table 0x0 0x803b57c +.text 0x3475c 0x8006000 +_cc_handlers_v3 0x1f8 0x803a75c +_zw_protocol_cmd_handlers 0x70 0x803a954 +_zw_protocol_cmd_handlers_lr 0x30 0x803a9c4 +.ARM.exidx 0x8 0x803a9f4 +.copy.table 0xc 0x803a9fc +.zero.table 0x0 0x803aa08 .stack 0x1000 0x20000000 -.data 0x558 0x20001000 -.bss 0xac84 0x20001558 -.heap 0x3e20 0x2000c1e0 -.internal_storage 0x2a000 0x803b57c -.zwave_nvm 0x6000 0x806557c -.nvm 0xa000 0x806b57c +.data 0x560 0x20001000 +.bss 0xad04 0x20001560 +.heap 0x3d98 0x2000c268 +.internal_storage 0x2c000 0x803aa08 +.zwave_nvm 0x6000 0x8066a08 +.nvm 0x8000 0x806ca08 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9fd8 0x0 -.debug_info 0x9b36c6 0x0 -.debug_abbrev 0x15c53 0x0 -.debug_loc 0x444b6 0x0 -.debug_aranges 0x3778 0x0 -.debug_ranges 0x6d10 0x0 -.debug_line 0x41607 0x0 -.debug_str 0x786f8 0x0 -Total 0xb5af25 +.debug_frame 0x9f64 0x0 +.debug_info 0x9b338f 0x0 +.debug_abbrev 0x15a38 0x0 +.debug_loc 0x44042 0x0 +.debug_aranges 0x3740 0x0 +.debug_ranges 0x6bc8 0x0 +.debug_line 0x410d9 0x0 +.debug_str 0x7874f 0x0 +Total 0xb59320 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 219860 + 216936 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51676 + 51812 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204D_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204D_REGION_US_LR_size.txt index 8939a157d6..80e6741796 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204D_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204D_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x352d0 0x8006000 -_cc_handlers_v3 0x1f8 0x803b2d0 -_zw_protocol_cmd_handlers 0x70 0x803b4c8 -_zw_protocol_cmd_handlers_lr 0x30 0x803b538 -.ARM.exidx 0x8 0x803b568 -.copy.table 0xc 0x803b570 -.zero.table 0x0 0x803b57c +.text 0x3475c 0x8006000 +_cc_handlers_v3 0x1f8 0x803a75c +_zw_protocol_cmd_handlers 0x70 0x803a954 +_zw_protocol_cmd_handlers_lr 0x30 0x803a9c4 +.ARM.exidx 0x8 0x803a9f4 +.copy.table 0xc 0x803a9fc +.zero.table 0x0 0x803aa08 .stack 0x1000 0x20000000 -.data 0x558 0x20001000 -.bss 0xac84 0x20001558 -.heap 0x3e20 0x2000c1e0 -.internal_storage 0x2a000 0x803b57c -.zwave_nvm 0x6000 0x806557c -.nvm 0xa000 0x806b57c +.data 0x560 0x20001000 +.bss 0xad04 0x20001560 +.heap 0x3d98 0x2000c268 +.internal_storage 0x2c000 0x803aa08 +.zwave_nvm 0x6000 0x8066a08 +.nvm 0x8000 0x806ca08 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9fd8 0x0 -.debug_info 0x9b36c6 0x0 -.debug_abbrev 0x15c53 0x0 -.debug_loc 0x444b6 0x0 -.debug_aranges 0x3778 0x0 -.debug_ranges 0x6d10 0x0 -.debug_line 0x41607 0x0 -.debug_str 0x786f8 0x0 -Total 0xb5af25 +.debug_frame 0x9f64 0x0 +.debug_info 0x9b338f 0x0 +.debug_abbrev 0x15a38 0x0 +.debug_loc 0x44042 0x0 +.debug_aranges 0x3740 0x0 +.debug_ranges 0x6bc8 0x0 +.debug_line 0x410d9 0x0 +.debug_str 0x7874f 0x0 +Total 0xb59320 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 219860 + 216936 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51676 + 51812 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204D_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204D_REGION_US_size.txt index 8939a157d6..80e6741796 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204D_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4204D_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x352d0 0x8006000 -_cc_handlers_v3 0x1f8 0x803b2d0 -_zw_protocol_cmd_handlers 0x70 0x803b4c8 -_zw_protocol_cmd_handlers_lr 0x30 0x803b538 -.ARM.exidx 0x8 0x803b568 -.copy.table 0xc 0x803b570 -.zero.table 0x0 0x803b57c +.text 0x3475c 0x8006000 +_cc_handlers_v3 0x1f8 0x803a75c +_zw_protocol_cmd_handlers 0x70 0x803a954 +_zw_protocol_cmd_handlers_lr 0x30 0x803a9c4 +.ARM.exidx 0x8 0x803a9f4 +.copy.table 0xc 0x803a9fc +.zero.table 0x0 0x803aa08 .stack 0x1000 0x20000000 -.data 0x558 0x20001000 -.bss 0xac84 0x20001558 -.heap 0x3e20 0x2000c1e0 -.internal_storage 0x2a000 0x803b57c -.zwave_nvm 0x6000 0x806557c -.nvm 0xa000 0x806b57c +.data 0x560 0x20001000 +.bss 0xad04 0x20001560 +.heap 0x3d98 0x2000c268 +.internal_storage 0x2c000 0x803aa08 +.zwave_nvm 0x6000 0x8066a08 +.nvm 0x8000 0x806ca08 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9fd8 0x0 -.debug_info 0x9b36c6 0x0 -.debug_abbrev 0x15c53 0x0 -.debug_loc 0x444b6 0x0 -.debug_aranges 0x3778 0x0 -.debug_ranges 0x6d10 0x0 -.debug_line 0x41607 0x0 -.debug_str 0x786f8 0x0 -Total 0xb5af25 +.debug_frame 0x9f64 0x0 +.debug_info 0x9b338f 0x0 +.debug_abbrev 0x15a38 0x0 +.debug_loc 0x44042 0x0 +.debug_aranges 0x3740 0x0 +.debug_ranges 0x6bc8 0x0 +.debug_line 0x410d9 0x0 +.debug_str 0x7874f 0x0 +Total 0xb59320 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 219860 + 216936 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51676 + 51812 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205A_REGION_EU_size.txt index f1e660c9be..a12a689212 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205A_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x35410 0x8006000 -_cc_handlers_v3 0x1f8 0x803b410 -_zw_protocol_cmd_handlers 0x70 0x803b608 -_zw_protocol_cmd_handlers_lr 0x30 0x803b678 -.ARM.exidx 0x8 0x803b6a8 -.copy.table 0xc 0x803b6b0 -.zero.table 0x0 0x803b6bc +.text 0x34624 0x8006000 +_cc_handlers_v3 0x1f8 0x803a624 +_zw_protocol_cmd_handlers 0x70 0x803a81c +_zw_protocol_cmd_handlers_lr 0x30 0x803a88c +.ARM.exidx 0x8 0x803a8bc +.copy.table 0xc 0x803a8c4 +.zero.table 0x0 0x803a8d0 .stack 0x1000 0x20000000 -.data 0x554 0x20001000 -.bss 0xab68 0x20001554 -.heap 0x3f40 0x2000c0c0 -.internal_storage 0x2a000 0x803b6bc -.zwave_nvm 0x6000 0x80656bc -.nvm 0xa000 0x806b6bc +.data 0x55c 0x20001000 +.bss 0xabf0 0x2000155c +.heap 0x3eb0 0x2000c150 +.internal_storage 0x2c000 0x803a8d0 +.zwave_nvm 0x6000 0x80668d0 +.nvm 0x8000 0x806c8d0 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9d98 0x0 -.debug_info 0x9b1cb6 0x0 -.debug_abbrev 0x15f63 0x0 -.debug_loc 0x42778 0x0 -.debug_aranges 0x3758 0x0 -.debug_ranges 0x6be0 0x0 -.debug_line 0x4029f 0x0 -.debug_str 0x78a7f 0x0 -Total 0xb568b6 +.debug_frame 0x999c 0x0 +.debug_info 0x9af575 0x0 +.debug_abbrev 0x156bc 0x0 +.debug_loc 0x3f994 0x0 +.debug_aranges 0x3640 0x0 +.debug_ranges 0x6988 0x0 +.debug_line 0x3eba3 0x0 +.debug_str 0x7852a 0x0 +Total 0xb4d941 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 220176 + 216620 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51388 + 51532 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205A_REGION_US_LR_size.txt index f1e660c9be..a12a689212 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x35410 0x8006000 -_cc_handlers_v3 0x1f8 0x803b410 -_zw_protocol_cmd_handlers 0x70 0x803b608 -_zw_protocol_cmd_handlers_lr 0x30 0x803b678 -.ARM.exidx 0x8 0x803b6a8 -.copy.table 0xc 0x803b6b0 -.zero.table 0x0 0x803b6bc +.text 0x34624 0x8006000 +_cc_handlers_v3 0x1f8 0x803a624 +_zw_protocol_cmd_handlers 0x70 0x803a81c +_zw_protocol_cmd_handlers_lr 0x30 0x803a88c +.ARM.exidx 0x8 0x803a8bc +.copy.table 0xc 0x803a8c4 +.zero.table 0x0 0x803a8d0 .stack 0x1000 0x20000000 -.data 0x554 0x20001000 -.bss 0xab68 0x20001554 -.heap 0x3f40 0x2000c0c0 -.internal_storage 0x2a000 0x803b6bc -.zwave_nvm 0x6000 0x80656bc -.nvm 0xa000 0x806b6bc +.data 0x55c 0x20001000 +.bss 0xabf0 0x2000155c +.heap 0x3eb0 0x2000c150 +.internal_storage 0x2c000 0x803a8d0 +.zwave_nvm 0x6000 0x80668d0 +.nvm 0x8000 0x806c8d0 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9d98 0x0 -.debug_info 0x9b1cb6 0x0 -.debug_abbrev 0x15f63 0x0 -.debug_loc 0x42778 0x0 -.debug_aranges 0x3758 0x0 -.debug_ranges 0x6be0 0x0 -.debug_line 0x4029f 0x0 -.debug_str 0x78a7f 0x0 -Total 0xb568b6 +.debug_frame 0x999c 0x0 +.debug_info 0x9af575 0x0 +.debug_abbrev 0x156bc 0x0 +.debug_loc 0x3f994 0x0 +.debug_aranges 0x3640 0x0 +.debug_ranges 0x6988 0x0 +.debug_line 0x3eba3 0x0 +.debug_str 0x7852a 0x0 +Total 0xb4d941 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 220176 + 216620 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51388 + 51532 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205A_REGION_US_size.txt index f1e660c9be..a12a689212 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205A_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x35410 0x8006000 -_cc_handlers_v3 0x1f8 0x803b410 -_zw_protocol_cmd_handlers 0x70 0x803b608 -_zw_protocol_cmd_handlers_lr 0x30 0x803b678 -.ARM.exidx 0x8 0x803b6a8 -.copy.table 0xc 0x803b6b0 -.zero.table 0x0 0x803b6bc +.text 0x34624 0x8006000 +_cc_handlers_v3 0x1f8 0x803a624 +_zw_protocol_cmd_handlers 0x70 0x803a81c +_zw_protocol_cmd_handlers_lr 0x30 0x803a88c +.ARM.exidx 0x8 0x803a8bc +.copy.table 0xc 0x803a8c4 +.zero.table 0x0 0x803a8d0 .stack 0x1000 0x20000000 -.data 0x554 0x20001000 -.bss 0xab68 0x20001554 -.heap 0x3f40 0x2000c0c0 -.internal_storage 0x2a000 0x803b6bc -.zwave_nvm 0x6000 0x80656bc -.nvm 0xa000 0x806b6bc +.data 0x55c 0x20001000 +.bss 0xabf0 0x2000155c +.heap 0x3eb0 0x2000c150 +.internal_storage 0x2c000 0x803a8d0 +.zwave_nvm 0x6000 0x80668d0 +.nvm 0x8000 0x806c8d0 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9d98 0x0 -.debug_info 0x9b1cb6 0x0 -.debug_abbrev 0x15f63 0x0 -.debug_loc 0x42778 0x0 -.debug_aranges 0x3758 0x0 -.debug_ranges 0x6be0 0x0 -.debug_line 0x4029f 0x0 -.debug_str 0x78a7f 0x0 -Total 0xb568b6 +.debug_frame 0x999c 0x0 +.debug_info 0x9af575 0x0 +.debug_abbrev 0x156bc 0x0 +.debug_loc 0x3f994 0x0 +.debug_aranges 0x3640 0x0 +.debug_ranges 0x6988 0x0 +.debug_line 0x3eba3 0x0 +.debug_str 0x7852a 0x0 +Total 0xb4d941 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 220176 + 216620 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51388 + 51532 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205B_REGION_EU_size.txt index 9c8a400c35..a6f1ff7552 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205B_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x35760 0x8006000 -_cc_handlers_v3 0x1f8 0x803b760 -_zw_protocol_cmd_handlers 0x70 0x803b958 -_zw_protocol_cmd_handlers_lr 0x30 0x803b9c8 -.ARM.exidx 0x8 0x803b9f8 -.copy.table 0xc 0x803ba00 -.zero.table 0x0 0x803ba0c +.text 0x34bec 0x8006000 +_cc_handlers_v3 0x1f8 0x803abec +_zw_protocol_cmd_handlers 0x70 0x803ade4 +_zw_protocol_cmd_handlers_lr 0x30 0x803ae54 +.ARM.exidx 0x8 0x803ae84 +.copy.table 0xc 0x803ae8c +.zero.table 0x0 0x803ae98 .stack 0x1000 0x20000000 -.data 0x554 0x20001000 -.bss 0xaca0 0x20001554 -.heap 0x3e08 0x2000c1f8 -.internal_storage 0x2a000 0x803ba0c -.zwave_nvm 0x6000 0x8065a0c -.nvm 0xa000 0x806ba0c +.data 0x55c 0x20001000 +.bss 0xad20 0x2000155c +.heap 0x3d80 0x2000c280 +.internal_storage 0x2c000 0x803ae98 +.zwave_nvm 0x6000 0x8066e98 +.nvm 0x8000 0x806ce98 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9fa8 0x0 -.debug_info 0x9b3ede 0x0 -.debug_abbrev 0x15cac 0x0 -.debug_loc 0x444a3 0x0 -.debug_aranges 0x3788 0x0 -.debug_ranges 0x6d00 0x0 -.debug_line 0x4144b 0x0 -.debug_str 0x78dd2 0x0 -Total 0xb5c101 +.debug_frame 0x9f34 0x0 +.debug_info 0x9b3ba7 0x0 +.debug_abbrev 0x15a91 0x0 +.debug_loc 0x44032 0x0 +.debug_aranges 0x3750 0x0 +.debug_ranges 0x6bb8 0x0 +.debug_line 0x40f1d 0x0 +.debug_str 0x78e28 0x0 +Total 0xb5a4fe The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 221024 + 218100 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51700 + 51836 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205B_REGION_US_LR_size.txt index 9c8a400c35..a6f1ff7552 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205B_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x35760 0x8006000 -_cc_handlers_v3 0x1f8 0x803b760 -_zw_protocol_cmd_handlers 0x70 0x803b958 -_zw_protocol_cmd_handlers_lr 0x30 0x803b9c8 -.ARM.exidx 0x8 0x803b9f8 -.copy.table 0xc 0x803ba00 -.zero.table 0x0 0x803ba0c +.text 0x34bec 0x8006000 +_cc_handlers_v3 0x1f8 0x803abec +_zw_protocol_cmd_handlers 0x70 0x803ade4 +_zw_protocol_cmd_handlers_lr 0x30 0x803ae54 +.ARM.exidx 0x8 0x803ae84 +.copy.table 0xc 0x803ae8c +.zero.table 0x0 0x803ae98 .stack 0x1000 0x20000000 -.data 0x554 0x20001000 -.bss 0xaca0 0x20001554 -.heap 0x3e08 0x2000c1f8 -.internal_storage 0x2a000 0x803ba0c -.zwave_nvm 0x6000 0x8065a0c -.nvm 0xa000 0x806ba0c +.data 0x55c 0x20001000 +.bss 0xad20 0x2000155c +.heap 0x3d80 0x2000c280 +.internal_storage 0x2c000 0x803ae98 +.zwave_nvm 0x6000 0x8066e98 +.nvm 0x8000 0x806ce98 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9fa8 0x0 -.debug_info 0x9b3ede 0x0 -.debug_abbrev 0x15cac 0x0 -.debug_loc 0x444a3 0x0 -.debug_aranges 0x3788 0x0 -.debug_ranges 0x6d00 0x0 -.debug_line 0x4144b 0x0 -.debug_str 0x78dd2 0x0 -Total 0xb5c101 +.debug_frame 0x9f34 0x0 +.debug_info 0x9b3ba7 0x0 +.debug_abbrev 0x15a91 0x0 +.debug_loc 0x44032 0x0 +.debug_aranges 0x3750 0x0 +.debug_ranges 0x6bb8 0x0 +.debug_line 0x40f1d 0x0 +.debug_str 0x78e28 0x0 +Total 0xb5a4fe The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 221024 + 218100 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51700 + 51836 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205B_REGION_US_size.txt index 9c8a400c35..a6f1ff7552 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4205B_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x35760 0x8006000 -_cc_handlers_v3 0x1f8 0x803b760 -_zw_protocol_cmd_handlers 0x70 0x803b958 -_zw_protocol_cmd_handlers_lr 0x30 0x803b9c8 -.ARM.exidx 0x8 0x803b9f8 -.copy.table 0xc 0x803ba00 -.zero.table 0x0 0x803ba0c +.text 0x34bec 0x8006000 +_cc_handlers_v3 0x1f8 0x803abec +_zw_protocol_cmd_handlers 0x70 0x803ade4 +_zw_protocol_cmd_handlers_lr 0x30 0x803ae54 +.ARM.exidx 0x8 0x803ae84 +.copy.table 0xc 0x803ae8c +.zero.table 0x0 0x803ae98 .stack 0x1000 0x20000000 -.data 0x554 0x20001000 -.bss 0xaca0 0x20001554 -.heap 0x3e08 0x2000c1f8 -.internal_storage 0x2a000 0x803ba0c -.zwave_nvm 0x6000 0x8065a0c -.nvm 0xa000 0x806ba0c +.data 0x55c 0x20001000 +.bss 0xad20 0x2000155c +.heap 0x3d80 0x2000c280 +.internal_storage 0x2c000 0x803ae98 +.zwave_nvm 0x6000 0x8066e98 +.nvm 0x8000 0x806ce98 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9fa8 0x0 -.debug_info 0x9b3ede 0x0 -.debug_abbrev 0x15cac 0x0 -.debug_loc 0x444a3 0x0 -.debug_aranges 0x3788 0x0 -.debug_ranges 0x6d00 0x0 -.debug_line 0x4144b 0x0 -.debug_str 0x78dd2 0x0 -Total 0xb5c101 +.debug_frame 0x9f34 0x0 +.debug_info 0x9b3ba7 0x0 +.debug_abbrev 0x15a91 0x0 +.debug_loc 0x44032 0x0 +.debug_aranges 0x3750 0x0 +.debug_ranges 0x6bb8 0x0 +.debug_line 0x40f1d 0x0 +.debug_str 0x78e28 0x0 +Total 0xb5a4fe The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 221024 + 218100 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51700 + 51836 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4207A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4207A_REGION_EU_size.txt index 6ebf2f6292..11c2276631 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4207A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4207A_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x2d69c 0x0 -_cc_handlers_v3 0x1f8 0x2d69c -_zw_protocol_cmd_handlers 0x70 0x2d894 -_zw_protocol_cmd_handlers_lr 0x30 0x2d904 -.ARM.exidx 0x8 0x2d934 -.copy.table 0xc 0x2d93c -.zero.table 0x0 0x2d948 +.text 0x2d7f8 0x0 +_cc_handlers_v3 0x1f8 0x2d7f8 +_zw_protocol_cmd_handlers 0x70 0x2d9f0 +_zw_protocol_cmd_handlers_lr 0x30 0x2da60 +.ARM.exidx 0x8 0x2da90 +.copy.table 0xc 0x2da98 +.zero.table 0x0 0x2daa4 .stack 0x1000 0x20000000 -.data 0x3fc 0x20001000 -.bss 0x9d58 0x200013fc -.heap 0x4ea8 0x2000b158 -.internal_storage 0x3a000 0x2d948 -.zwave_nvm 0x3000 0x67948 -.nvm 0x9000 0x6a948 +.data 0x404 0x20001000 +.bss 0x9de0 0x20001404 +.heap 0x4e18 0x2000b1e8 +.internal_storage 0x3a000 0x2daa4 +.zwave_nvm 0x3000 0x67aa4 +.nvm 0x9000 0x6aaa4 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6a74 0x0 -.debug_info 0x96c402 0x0 -.debug_abbrev 0x102ab 0x0 -.debug_loc 0x25ce0 0x0 +.debug_frame 0x6a80 0x0 +.debug_info 0x96ca4e 0x0 +.debug_abbrev 0x1030e 0x0 +.debug_loc 0x25d05 0x0 .debug_aranges 0x2818 0x0 -.debug_ranges 0x4cf8 0x0 -.debug_line 0x2b3e6 0x0 -.debug_str 0x6c98f 0x0 -Total 0xacba41 +.debug_ranges 0x4ce0 0x0 +.debug_line 0x2b43f 0x0 +.debug_str 0x6cac1 0x0 +Total 0xacc3f0 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 187716 + 188072 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47444 + 47588 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4207A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4207A_REGION_US_LR_size.txt index 6ebf2f6292..11c2276631 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4207A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4207A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x2d69c 0x0 -_cc_handlers_v3 0x1f8 0x2d69c -_zw_protocol_cmd_handlers 0x70 0x2d894 -_zw_protocol_cmd_handlers_lr 0x30 0x2d904 -.ARM.exidx 0x8 0x2d934 -.copy.table 0xc 0x2d93c -.zero.table 0x0 0x2d948 +.text 0x2d7f8 0x0 +_cc_handlers_v3 0x1f8 0x2d7f8 +_zw_protocol_cmd_handlers 0x70 0x2d9f0 +_zw_protocol_cmd_handlers_lr 0x30 0x2da60 +.ARM.exidx 0x8 0x2da90 +.copy.table 0xc 0x2da98 +.zero.table 0x0 0x2daa4 .stack 0x1000 0x20000000 -.data 0x3fc 0x20001000 -.bss 0x9d58 0x200013fc -.heap 0x4ea8 0x2000b158 -.internal_storage 0x3a000 0x2d948 -.zwave_nvm 0x3000 0x67948 -.nvm 0x9000 0x6a948 +.data 0x404 0x20001000 +.bss 0x9de0 0x20001404 +.heap 0x4e18 0x2000b1e8 +.internal_storage 0x3a000 0x2daa4 +.zwave_nvm 0x3000 0x67aa4 +.nvm 0x9000 0x6aaa4 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6a74 0x0 -.debug_info 0x96c402 0x0 -.debug_abbrev 0x102ab 0x0 -.debug_loc 0x25ce0 0x0 +.debug_frame 0x6a80 0x0 +.debug_info 0x96ca4e 0x0 +.debug_abbrev 0x1030e 0x0 +.debug_loc 0x25d05 0x0 .debug_aranges 0x2818 0x0 -.debug_ranges 0x4cf8 0x0 -.debug_line 0x2b3e6 0x0 -.debug_str 0x6c98f 0x0 -Total 0xacba41 +.debug_ranges 0x4ce0 0x0 +.debug_line 0x2b43f 0x0 +.debug_str 0x6cac1 0x0 +Total 0xacc3f0 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 187716 + 188072 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47444 + 47588 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4207A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4207A_REGION_US_size.txt index 6ebf2f6292..11c2276631 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4207A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4207A_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x2d69c 0x0 -_cc_handlers_v3 0x1f8 0x2d69c -_zw_protocol_cmd_handlers 0x70 0x2d894 -_zw_protocol_cmd_handlers_lr 0x30 0x2d904 -.ARM.exidx 0x8 0x2d934 -.copy.table 0xc 0x2d93c -.zero.table 0x0 0x2d948 +.text 0x2d7f8 0x0 +_cc_handlers_v3 0x1f8 0x2d7f8 +_zw_protocol_cmd_handlers 0x70 0x2d9f0 +_zw_protocol_cmd_handlers_lr 0x30 0x2da60 +.ARM.exidx 0x8 0x2da90 +.copy.table 0xc 0x2da98 +.zero.table 0x0 0x2daa4 .stack 0x1000 0x20000000 -.data 0x3fc 0x20001000 -.bss 0x9d58 0x200013fc -.heap 0x4ea8 0x2000b158 -.internal_storage 0x3a000 0x2d948 -.zwave_nvm 0x3000 0x67948 -.nvm 0x9000 0x6a948 +.data 0x404 0x20001000 +.bss 0x9de0 0x20001404 +.heap 0x4e18 0x2000b1e8 +.internal_storage 0x3a000 0x2daa4 +.zwave_nvm 0x3000 0x67aa4 +.nvm 0x9000 0x6aaa4 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6a74 0x0 -.debug_info 0x96c402 0x0 -.debug_abbrev 0x102ab 0x0 -.debug_loc 0x25ce0 0x0 +.debug_frame 0x6a80 0x0 +.debug_info 0x96ca4e 0x0 +.debug_abbrev 0x1030e 0x0 +.debug_loc 0x25d05 0x0 .debug_aranges 0x2818 0x0 -.debug_ranges 0x4cf8 0x0 -.debug_line 0x2b3e6 0x0 -.debug_str 0x6c98f 0x0 -Total 0xacba41 +.debug_ranges 0x4ce0 0x0 +.debug_line 0x2b43f 0x0 +.debug_str 0x6cac1 0x0 +Total 0xacc3f0 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 187716 + 188072 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47444 + 47588 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4209A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4209A_REGION_US_LR_size.txt index f121c971eb..63d437ee96 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4209A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4209A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x2d668 0x0 -_cc_handlers_v3 0x1f8 0x2d668 -_zw_protocol_cmd_handlers 0x70 0x2d860 -_zw_protocol_cmd_handlers_lr 0x30 0x2d8d0 -.ARM.exidx 0x8 0x2d900 -.copy.table 0xc 0x2d908 -.zero.table 0x0 0x2d914 +.text 0x2d784 0x0 +_cc_handlers_v3 0x1f8 0x2d784 +_zw_protocol_cmd_handlers 0x70 0x2d97c +_zw_protocol_cmd_handlers_lr 0x30 0x2d9ec +.ARM.exidx 0x8 0x2da1c +.copy.table 0xc 0x2da24 +.zero.table 0x0 0x2da30 .stack 0x1000 0x20000000 -.data 0x3f8 0x20001000 -.bss 0x9d3c 0x200013f8 -.heap 0x4ec8 0x2000b138 -.internal_storage 0x3a000 0x2d914 -.zwave_nvm 0x3000 0x67914 -.nvm 0x9000 0x6a914 +.data 0x400 0x20001000 +.bss 0x9dc4 0x20001400 +.heap 0x4e38 0x2000b1c8 +.internal_storage 0x3a000 0x2da30 +.zwave_nvm 0x3000 0x67a30 +.nvm 0x9000 0x6aa30 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6ca4 0x0 -.debug_info 0x96dcd5 0x0 -.debug_abbrev 0x10815 0x0 -.debug_loc 0x267ef 0x0 +.debug_frame 0x6cb0 0x0 +.debug_info 0x96e321 0x0 +.debug_abbrev 0x10878 0x0 +.debug_loc 0x26814 0x0 .debug_aranges 0x28f8 0x0 -.debug_ranges 0x4ee0 0x0 -.debug_line 0x2c427 0x0 -.debug_str 0x6cd85 0x0 -Total 0xacfc88 +.debug_ranges 0x4ec8 0x0 +.debug_line 0x2c480 0x0 +.debug_str 0x6ceb8 0x0 +Total 0xad05f8 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 187660 + 187952 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47412 + 47556 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4210A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4210A_REGION_US_LR_size.txt index 8939a157d6..80e6741796 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4210A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_switch_on_off_BRD4210A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_switch_on_off.out : section size addr -.text 0x352d0 0x8006000 -_cc_handlers_v3 0x1f8 0x803b2d0 -_zw_protocol_cmd_handlers 0x70 0x803b4c8 -_zw_protocol_cmd_handlers_lr 0x30 0x803b538 -.ARM.exidx 0x8 0x803b568 -.copy.table 0xc 0x803b570 -.zero.table 0x0 0x803b57c +.text 0x3475c 0x8006000 +_cc_handlers_v3 0x1f8 0x803a75c +_zw_protocol_cmd_handlers 0x70 0x803a954 +_zw_protocol_cmd_handlers_lr 0x30 0x803a9c4 +.ARM.exidx 0x8 0x803a9f4 +.copy.table 0xc 0x803a9fc +.zero.table 0x0 0x803aa08 .stack 0x1000 0x20000000 -.data 0x558 0x20001000 -.bss 0xac84 0x20001558 -.heap 0x3e20 0x2000c1e0 -.internal_storage 0x2a000 0x803b57c -.zwave_nvm 0x6000 0x806557c -.nvm 0xa000 0x806b57c +.data 0x560 0x20001000 +.bss 0xad04 0x20001560 +.heap 0x3d98 0x2000c268 +.internal_storage 0x2c000 0x803aa08 +.zwave_nvm 0x6000 0x8066a08 +.nvm 0x8000 0x806ca08 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9fd8 0x0 -.debug_info 0x9b36c6 0x0 -.debug_abbrev 0x15c53 0x0 -.debug_loc 0x444b6 0x0 -.debug_aranges 0x3778 0x0 -.debug_ranges 0x6d10 0x0 -.debug_line 0x41607 0x0 -.debug_str 0x786f8 0x0 -Total 0xb5af25 +.debug_frame 0x9f64 0x0 +.debug_info 0x9b338f 0x0 +.debug_abbrev 0x15a38 0x0 +.debug_loc 0x44042 0x0 +.debug_aranges 0x3740 0x0 +.debug_ranges 0x6bc8 0x0 +.debug_line 0x410d9 0x0 +.debug_str 0x7874f 0x0 +Total 0xb59320 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 219860 + 216936 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51676 + 51812 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4202A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4202A_REGION_EU_size.txt index 7d575f2eeb..118ed3f495 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4202A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4202A_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x2daec 0x0 -_cc_handlers_v3 0x1d4 0x2daec -_zw_protocol_cmd_handlers 0x70 0x2dcc0 -_zw_protocol_cmd_handlers_lr 0x30 0x2dd30 -.ARM.exidx 0x8 0x2dd60 -.copy.table 0xc 0x2dd68 -.zero.table 0x0 0x2dd74 +.text 0x2dc48 0x0 +_cc_handlers_v3 0x1d4 0x2dc48 +_zw_protocol_cmd_handlers 0x70 0x2de1c +_zw_protocol_cmd_handlers_lr 0x30 0x2de8c +.ARM.exidx 0x8 0x2debc +.copy.table 0xc 0x2dec4 +.zero.table 0x0 0x2ded0 .stack 0x1000 0x20000000 -.data 0x52c 0x20001000 -.bss 0x9e50 0x2000152c -.heap 0x4c80 0x2000b380 -.internal_storage 0x3a000 0x2dd74 -.zwave_nvm 0x3000 0x67d74 -.nvm 0x9000 0x6ad74 +.data 0x534 0x20001000 +.bss 0x9ed8 0x20001534 +.heap 0x4bf0 0x2000b410 +.internal_storage 0x3a000 0x2ded0 +.zwave_nvm 0x3000 0x67ed0 +.nvm 0x9000 0x6aed0 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x69e0 0x0 -.debug_info 0x96b345 0x0 -.debug_abbrev 0x100b9 0x0 -.debug_loc 0x25e12 0x0 +.debug_frame 0x69ec 0x0 +.debug_info 0x96b920 0x0 +.debug_abbrev 0x1012e 0x0 +.debug_loc 0x25e37 0x0 .debug_aranges 0x27e0 0x0 -.debug_ranges 0x4d58 0x0 -.debug_line 0x2b6a3 0x0 -.debug_str 0x6cdd8 0x0 -Total 0xacb38a +.debug_ranges 0x4d40 0x0 +.debug_line 0x2b6f3 0x0 +.debug_str 0x6cf0a 0x0 +Total 0xacbcd1 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 189088 + 189444 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47996 + 48140 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4202A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4202A_REGION_US_LR_size.txt index 7d575f2eeb..118ed3f495 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4202A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4202A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x2daec 0x0 -_cc_handlers_v3 0x1d4 0x2daec -_zw_protocol_cmd_handlers 0x70 0x2dcc0 -_zw_protocol_cmd_handlers_lr 0x30 0x2dd30 -.ARM.exidx 0x8 0x2dd60 -.copy.table 0xc 0x2dd68 -.zero.table 0x0 0x2dd74 +.text 0x2dc48 0x0 +_cc_handlers_v3 0x1d4 0x2dc48 +_zw_protocol_cmd_handlers 0x70 0x2de1c +_zw_protocol_cmd_handlers_lr 0x30 0x2de8c +.ARM.exidx 0x8 0x2debc +.copy.table 0xc 0x2dec4 +.zero.table 0x0 0x2ded0 .stack 0x1000 0x20000000 -.data 0x52c 0x20001000 -.bss 0x9e50 0x2000152c -.heap 0x4c80 0x2000b380 -.internal_storage 0x3a000 0x2dd74 -.zwave_nvm 0x3000 0x67d74 -.nvm 0x9000 0x6ad74 +.data 0x534 0x20001000 +.bss 0x9ed8 0x20001534 +.heap 0x4bf0 0x2000b410 +.internal_storage 0x3a000 0x2ded0 +.zwave_nvm 0x3000 0x67ed0 +.nvm 0x9000 0x6aed0 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x69e0 0x0 -.debug_info 0x96b345 0x0 -.debug_abbrev 0x100b9 0x0 -.debug_loc 0x25e12 0x0 +.debug_frame 0x69ec 0x0 +.debug_info 0x96b920 0x0 +.debug_abbrev 0x1012e 0x0 +.debug_loc 0x25e37 0x0 .debug_aranges 0x27e0 0x0 -.debug_ranges 0x4d58 0x0 -.debug_line 0x2b6a3 0x0 -.debug_str 0x6cdd8 0x0 -Total 0xacb38a +.debug_ranges 0x4d40 0x0 +.debug_line 0x2b6f3 0x0 +.debug_str 0x6cf0a 0x0 +Total 0xacbcd1 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 189088 + 189444 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47996 + 48140 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4202A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4202A_REGION_US_size.txt index 7d575f2eeb..118ed3f495 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4202A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4202A_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x2daec 0x0 -_cc_handlers_v3 0x1d4 0x2daec -_zw_protocol_cmd_handlers 0x70 0x2dcc0 -_zw_protocol_cmd_handlers_lr 0x30 0x2dd30 -.ARM.exidx 0x8 0x2dd60 -.copy.table 0xc 0x2dd68 -.zero.table 0x0 0x2dd74 +.text 0x2dc48 0x0 +_cc_handlers_v3 0x1d4 0x2dc48 +_zw_protocol_cmd_handlers 0x70 0x2de1c +_zw_protocol_cmd_handlers_lr 0x30 0x2de8c +.ARM.exidx 0x8 0x2debc +.copy.table 0xc 0x2dec4 +.zero.table 0x0 0x2ded0 .stack 0x1000 0x20000000 -.data 0x52c 0x20001000 -.bss 0x9e50 0x2000152c -.heap 0x4c80 0x2000b380 -.internal_storage 0x3a000 0x2dd74 -.zwave_nvm 0x3000 0x67d74 -.nvm 0x9000 0x6ad74 +.data 0x534 0x20001000 +.bss 0x9ed8 0x20001534 +.heap 0x4bf0 0x2000b410 +.internal_storage 0x3a000 0x2ded0 +.zwave_nvm 0x3000 0x67ed0 +.nvm 0x9000 0x6aed0 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x69e0 0x0 -.debug_info 0x96b345 0x0 -.debug_abbrev 0x100b9 0x0 -.debug_loc 0x25e12 0x0 +.debug_frame 0x69ec 0x0 +.debug_info 0x96b920 0x0 +.debug_abbrev 0x1012e 0x0 +.debug_loc 0x25e37 0x0 .debug_aranges 0x27e0 0x0 -.debug_ranges 0x4d58 0x0 -.debug_line 0x2b6a3 0x0 -.debug_str 0x6cdd8 0x0 -Total 0xacb38a +.debug_ranges 0x4d40 0x0 +.debug_line 0x2b6f3 0x0 +.debug_str 0x6cf0a 0x0 +Total 0xacbcd1 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 189088 + 189444 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47996 + 48140 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204C_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204C_REGION_EU_size.txt index 4de0562c76..d643f723b4 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204C_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204C_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x35654 0x8006000 -_cc_handlers_v3 0x1d4 0x803b654 -_zw_protocol_cmd_handlers 0x70 0x803b828 -_zw_protocol_cmd_handlers_lr 0x30 0x803b898 -.ARM.exidx 0x8 0x803b8c8 -.copy.table 0xc 0x803b8d0 -.zero.table 0x0 0x803b8dc +.text 0x34af0 0x8006000 +_cc_handlers_v3 0x1d4 0x803aaf0 +_zw_protocol_cmd_handlers 0x70 0x803acc4 +_zw_protocol_cmd_handlers_lr 0x30 0x803ad34 +.ARM.exidx 0x8 0x803ad64 +.copy.table 0xc 0x803ad6c +.zero.table 0x0 0x803ad78 .stack 0x1000 0x20000000 -.data 0x684 0x20001000 -.bss 0xad70 0x20001684 -.heap 0x3c08 0x2000c3f8 -.internal_storage 0x2a000 0x803b8dc -.zwave_nvm 0x6000 0x80658dc -.nvm 0xa000 0x806b8dc +.data 0x68c 0x20001000 +.bss 0xae00 0x2000168c +.heap 0x3b70 0x2000c490 +.internal_storage 0x2c000 0x803ad78 +.zwave_nvm 0x6000 0x8066d78 +.nvm 0x8000 0x806cd78 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9f14 0x0 -.debug_info 0x9b23a4 0x0 -.debug_abbrev 0x15975 0x0 -.debug_loc 0x445c5 0x0 -.debug_aranges 0x3720 0x0 -.debug_ranges 0x6d58 0x0 -.debug_line 0x4170d 0x0 -.debug_str 0x7895e 0x0 -Total 0xb5a02c +.debug_frame 0x9ea0 0x0 +.debug_info 0x9b1ffe 0x0 +.debug_abbrev 0x1576c 0x0 +.debug_loc 0x44151 0x0 +.debug_aranges 0x36e8 0x0 +.debug_ranges 0x6c10 0x0 +.debug_line 0x411dc 0x0 +.debug_str 0x789b5 0x0 +Total 0xb583d7 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 221024 + 218116 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52212 + 52364 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204C_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204C_REGION_US_LR_size.txt index 4de0562c76..d643f723b4 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204C_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204C_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x35654 0x8006000 -_cc_handlers_v3 0x1d4 0x803b654 -_zw_protocol_cmd_handlers 0x70 0x803b828 -_zw_protocol_cmd_handlers_lr 0x30 0x803b898 -.ARM.exidx 0x8 0x803b8c8 -.copy.table 0xc 0x803b8d0 -.zero.table 0x0 0x803b8dc +.text 0x34af0 0x8006000 +_cc_handlers_v3 0x1d4 0x803aaf0 +_zw_protocol_cmd_handlers 0x70 0x803acc4 +_zw_protocol_cmd_handlers_lr 0x30 0x803ad34 +.ARM.exidx 0x8 0x803ad64 +.copy.table 0xc 0x803ad6c +.zero.table 0x0 0x803ad78 .stack 0x1000 0x20000000 -.data 0x684 0x20001000 -.bss 0xad70 0x20001684 -.heap 0x3c08 0x2000c3f8 -.internal_storage 0x2a000 0x803b8dc -.zwave_nvm 0x6000 0x80658dc -.nvm 0xa000 0x806b8dc +.data 0x68c 0x20001000 +.bss 0xae00 0x2000168c +.heap 0x3b70 0x2000c490 +.internal_storage 0x2c000 0x803ad78 +.zwave_nvm 0x6000 0x8066d78 +.nvm 0x8000 0x806cd78 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9f14 0x0 -.debug_info 0x9b23a4 0x0 -.debug_abbrev 0x15975 0x0 -.debug_loc 0x445c5 0x0 -.debug_aranges 0x3720 0x0 -.debug_ranges 0x6d58 0x0 -.debug_line 0x4170d 0x0 -.debug_str 0x7895e 0x0 -Total 0xb5a02c +.debug_frame 0x9ea0 0x0 +.debug_info 0x9b1ffe 0x0 +.debug_abbrev 0x1576c 0x0 +.debug_loc 0x44151 0x0 +.debug_aranges 0x36e8 0x0 +.debug_ranges 0x6c10 0x0 +.debug_line 0x411dc 0x0 +.debug_str 0x789b5 0x0 +Total 0xb583d7 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 221024 + 218116 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52212 + 52364 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204C_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204C_REGION_US_size.txt index 4de0562c76..d643f723b4 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204C_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204C_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x35654 0x8006000 -_cc_handlers_v3 0x1d4 0x803b654 -_zw_protocol_cmd_handlers 0x70 0x803b828 -_zw_protocol_cmd_handlers_lr 0x30 0x803b898 -.ARM.exidx 0x8 0x803b8c8 -.copy.table 0xc 0x803b8d0 -.zero.table 0x0 0x803b8dc +.text 0x34af0 0x8006000 +_cc_handlers_v3 0x1d4 0x803aaf0 +_zw_protocol_cmd_handlers 0x70 0x803acc4 +_zw_protocol_cmd_handlers_lr 0x30 0x803ad34 +.ARM.exidx 0x8 0x803ad64 +.copy.table 0xc 0x803ad6c +.zero.table 0x0 0x803ad78 .stack 0x1000 0x20000000 -.data 0x684 0x20001000 -.bss 0xad70 0x20001684 -.heap 0x3c08 0x2000c3f8 -.internal_storage 0x2a000 0x803b8dc -.zwave_nvm 0x6000 0x80658dc -.nvm 0xa000 0x806b8dc +.data 0x68c 0x20001000 +.bss 0xae00 0x2000168c +.heap 0x3b70 0x2000c490 +.internal_storage 0x2c000 0x803ad78 +.zwave_nvm 0x6000 0x8066d78 +.nvm 0x8000 0x806cd78 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9f14 0x0 -.debug_info 0x9b23a4 0x0 -.debug_abbrev 0x15975 0x0 -.debug_loc 0x445c5 0x0 -.debug_aranges 0x3720 0x0 -.debug_ranges 0x6d58 0x0 -.debug_line 0x4170d 0x0 -.debug_str 0x7895e 0x0 -Total 0xb5a02c +.debug_frame 0x9ea0 0x0 +.debug_info 0x9b1ffe 0x0 +.debug_abbrev 0x1576c 0x0 +.debug_loc 0x44151 0x0 +.debug_aranges 0x36e8 0x0 +.debug_ranges 0x6c10 0x0 +.debug_line 0x411dc 0x0 +.debug_str 0x789b5 0x0 +Total 0xb583d7 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 221024 + 218116 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52212 + 52364 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204D_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204D_REGION_EU_size.txt index f92a5772e5..1d4e0a7f19 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204D_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204D_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x35720 0x8006000 -_cc_handlers_v3 0x1d4 0x803b720 -_zw_protocol_cmd_handlers 0x70 0x803b8f4 -_zw_protocol_cmd_handlers_lr 0x30 0x803b964 -.ARM.exidx 0x8 0x803b994 -.copy.table 0xc 0x803b99c -.zero.table 0x0 0x803b9a8 +.text 0x34bbc 0x8006000 +_cc_handlers_v3 0x1d4 0x803abbc +_zw_protocol_cmd_handlers 0x70 0x803ad90 +_zw_protocol_cmd_handlers_lr 0x30 0x803ae00 +.ARM.exidx 0x8 0x803ae30 +.copy.table 0xc 0x803ae38 +.zero.table 0x0 0x803ae44 .stack 0x1000 0x20000000 -.data 0x688 0x20001000 -.bss 0xad74 0x20001688 -.heap 0x3c00 0x2000c400 -.internal_storage 0x2a000 0x803b9a8 -.zwave_nvm 0x6000 0x80659a8 -.nvm 0xa000 0x806b9a8 +.data 0x690 0x20001000 +.bss 0xae04 0x20001690 +.heap 0x3b68 0x2000c498 +.internal_storage 0x2c000 0x803ae44 +.zwave_nvm 0x6000 0x8066e44 +.nvm 0x8000 0x806ce44 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9f44 0x0 -.debug_info 0x9b2607 0x0 -.debug_abbrev 0x15a61 0x0 -.debug_loc 0x445c5 0x0 -.debug_aranges 0x3740 0x0 -.debug_ranges 0x6d68 0x0 -.debug_line 0x418f3 0x0 -.debug_str 0x78b31 0x0 -Total 0xb5a860 +.debug_frame 0x9ed0 0x0 +.debug_info 0x9b2261 0x0 +.debug_abbrev 0x15858 0x0 +.debug_loc 0x44151 0x0 +.debug_aranges 0x3708 0x0 +.debug_ranges 0x6c20 0x0 +.debug_line 0x413c2 0x0 +.debug_str 0x78b88 0x0 +Total 0xb58c0b The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 221232 + 218324 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52220 + 52372 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204D_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204D_REGION_US_LR_size.txt index f92a5772e5..1d4e0a7f19 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204D_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204D_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x35720 0x8006000 -_cc_handlers_v3 0x1d4 0x803b720 -_zw_protocol_cmd_handlers 0x70 0x803b8f4 -_zw_protocol_cmd_handlers_lr 0x30 0x803b964 -.ARM.exidx 0x8 0x803b994 -.copy.table 0xc 0x803b99c -.zero.table 0x0 0x803b9a8 +.text 0x34bbc 0x8006000 +_cc_handlers_v3 0x1d4 0x803abbc +_zw_protocol_cmd_handlers 0x70 0x803ad90 +_zw_protocol_cmd_handlers_lr 0x30 0x803ae00 +.ARM.exidx 0x8 0x803ae30 +.copy.table 0xc 0x803ae38 +.zero.table 0x0 0x803ae44 .stack 0x1000 0x20000000 -.data 0x688 0x20001000 -.bss 0xad74 0x20001688 -.heap 0x3c00 0x2000c400 -.internal_storage 0x2a000 0x803b9a8 -.zwave_nvm 0x6000 0x80659a8 -.nvm 0xa000 0x806b9a8 +.data 0x690 0x20001000 +.bss 0xae04 0x20001690 +.heap 0x3b68 0x2000c498 +.internal_storage 0x2c000 0x803ae44 +.zwave_nvm 0x6000 0x8066e44 +.nvm 0x8000 0x806ce44 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9f44 0x0 -.debug_info 0x9b2607 0x0 -.debug_abbrev 0x15a61 0x0 -.debug_loc 0x445c5 0x0 -.debug_aranges 0x3740 0x0 -.debug_ranges 0x6d68 0x0 -.debug_line 0x418f3 0x0 -.debug_str 0x78b31 0x0 -Total 0xb5a860 +.debug_frame 0x9ed0 0x0 +.debug_info 0x9b2261 0x0 +.debug_abbrev 0x15858 0x0 +.debug_loc 0x44151 0x0 +.debug_aranges 0x3708 0x0 +.debug_ranges 0x6c20 0x0 +.debug_line 0x413c2 0x0 +.debug_str 0x78b88 0x0 +Total 0xb58c0b The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 221232 + 218324 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52220 + 52372 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204D_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204D_REGION_US_size.txt index f92a5772e5..1d4e0a7f19 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204D_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4204D_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x35720 0x8006000 -_cc_handlers_v3 0x1d4 0x803b720 -_zw_protocol_cmd_handlers 0x70 0x803b8f4 -_zw_protocol_cmd_handlers_lr 0x30 0x803b964 -.ARM.exidx 0x8 0x803b994 -.copy.table 0xc 0x803b99c -.zero.table 0x0 0x803b9a8 +.text 0x34bbc 0x8006000 +_cc_handlers_v3 0x1d4 0x803abbc +_zw_protocol_cmd_handlers 0x70 0x803ad90 +_zw_protocol_cmd_handlers_lr 0x30 0x803ae00 +.ARM.exidx 0x8 0x803ae30 +.copy.table 0xc 0x803ae38 +.zero.table 0x0 0x803ae44 .stack 0x1000 0x20000000 -.data 0x688 0x20001000 -.bss 0xad74 0x20001688 -.heap 0x3c00 0x2000c400 -.internal_storage 0x2a000 0x803b9a8 -.zwave_nvm 0x6000 0x80659a8 -.nvm 0xa000 0x806b9a8 +.data 0x690 0x20001000 +.bss 0xae04 0x20001690 +.heap 0x3b68 0x2000c498 +.internal_storage 0x2c000 0x803ae44 +.zwave_nvm 0x6000 0x8066e44 +.nvm 0x8000 0x806ce44 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9f44 0x0 -.debug_info 0x9b2607 0x0 -.debug_abbrev 0x15a61 0x0 -.debug_loc 0x445c5 0x0 -.debug_aranges 0x3740 0x0 -.debug_ranges 0x6d68 0x0 -.debug_line 0x418f3 0x0 -.debug_str 0x78b31 0x0 -Total 0xb5a860 +.debug_frame 0x9ed0 0x0 +.debug_info 0x9b2261 0x0 +.debug_abbrev 0x15858 0x0 +.debug_loc 0x44151 0x0 +.debug_aranges 0x3708 0x0 +.debug_ranges 0x6c20 0x0 +.debug_line 0x413c2 0x0 +.debug_str 0x78b88 0x0 +Total 0xb58c0b The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 221232 + 218324 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52220 + 52372 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205A_REGION_EU_size.txt index 1bebbe7056..a987a1c3b9 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205A_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x35860 0x8006000 -_cc_handlers_v3 0x1d4 0x803b860 -_zw_protocol_cmd_handlers 0x70 0x803ba34 -_zw_protocol_cmd_handlers_lr 0x30 0x803baa4 -.ARM.exidx 0x8 0x803bad4 -.copy.table 0xc 0x803badc -.zero.table 0x0 0x803bae8 +.text 0x34a74 0x8006000 +_cc_handlers_v3 0x1d4 0x803aa74 +_zw_protocol_cmd_handlers 0x70 0x803ac48 +_zw_protocol_cmd_handlers_lr 0x30 0x803acb8 +.ARM.exidx 0x8 0x803ace8 +.copy.table 0xc 0x803acf0 +.zero.table 0x0 0x803acfc .stack 0x1000 0x20000000 -.data 0x684 0x20001000 -.bss 0xac60 0x20001684 -.heap 0x3d18 0x2000c2e8 -.internal_storage 0x2a000 0x803bae8 -.zwave_nvm 0x6000 0x8065ae8 -.nvm 0xa000 0x806bae8 +.data 0x68c 0x20001000 +.bss 0xace8 0x2000168c +.heap 0x3c88 0x2000c378 +.internal_storage 0x2c000 0x803acfc +.zwave_nvm 0x6000 0x8066cfc +.nvm 0x8000 0x806ccfc .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9d04 0x0 -.debug_info 0x9b0bf7 0x0 -.debug_abbrev 0x15d71 0x0 -.debug_loc 0x42887 0x0 -.debug_aranges 0x3720 0x0 -.debug_ranges 0x6c38 0x0 -.debug_line 0x4058b 0x0 -.debug_str 0x78eb8 0x0 -Total 0xb561f1 +.debug_frame 0x9908 0x0 +.debug_info 0x9ae447 0x0 +.debug_abbrev 0x154dc 0x0 +.debug_loc 0x3faa3 0x0 +.debug_aranges 0x3608 0x0 +.debug_ranges 0x69e0 0x0 +.debug_line 0x3ee8c 0x0 +.debug_str 0x78963 0x0 +Total 0xb4d21c The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 221548 + 217992 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51940 + 52084 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205A_REGION_US_LR_size.txt index 1bebbe7056..a987a1c3b9 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x35860 0x8006000 -_cc_handlers_v3 0x1d4 0x803b860 -_zw_protocol_cmd_handlers 0x70 0x803ba34 -_zw_protocol_cmd_handlers_lr 0x30 0x803baa4 -.ARM.exidx 0x8 0x803bad4 -.copy.table 0xc 0x803badc -.zero.table 0x0 0x803bae8 +.text 0x34a74 0x8006000 +_cc_handlers_v3 0x1d4 0x803aa74 +_zw_protocol_cmd_handlers 0x70 0x803ac48 +_zw_protocol_cmd_handlers_lr 0x30 0x803acb8 +.ARM.exidx 0x8 0x803ace8 +.copy.table 0xc 0x803acf0 +.zero.table 0x0 0x803acfc .stack 0x1000 0x20000000 -.data 0x684 0x20001000 -.bss 0xac60 0x20001684 -.heap 0x3d18 0x2000c2e8 -.internal_storage 0x2a000 0x803bae8 -.zwave_nvm 0x6000 0x8065ae8 -.nvm 0xa000 0x806bae8 +.data 0x68c 0x20001000 +.bss 0xace8 0x2000168c +.heap 0x3c88 0x2000c378 +.internal_storage 0x2c000 0x803acfc +.zwave_nvm 0x6000 0x8066cfc +.nvm 0x8000 0x806ccfc .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9d04 0x0 -.debug_info 0x9b0bf7 0x0 -.debug_abbrev 0x15d71 0x0 -.debug_loc 0x42887 0x0 -.debug_aranges 0x3720 0x0 -.debug_ranges 0x6c38 0x0 -.debug_line 0x4058b 0x0 -.debug_str 0x78eb8 0x0 -Total 0xb561f1 +.debug_frame 0x9908 0x0 +.debug_info 0x9ae447 0x0 +.debug_abbrev 0x154dc 0x0 +.debug_loc 0x3faa3 0x0 +.debug_aranges 0x3608 0x0 +.debug_ranges 0x69e0 0x0 +.debug_line 0x3ee8c 0x0 +.debug_str 0x78963 0x0 +Total 0xb4d21c The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 221548 + 217992 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51940 + 52084 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205A_REGION_US_size.txt index 1bebbe7056..a987a1c3b9 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205A_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x35860 0x8006000 -_cc_handlers_v3 0x1d4 0x803b860 -_zw_protocol_cmd_handlers 0x70 0x803ba34 -_zw_protocol_cmd_handlers_lr 0x30 0x803baa4 -.ARM.exidx 0x8 0x803bad4 -.copy.table 0xc 0x803badc -.zero.table 0x0 0x803bae8 +.text 0x34a74 0x8006000 +_cc_handlers_v3 0x1d4 0x803aa74 +_zw_protocol_cmd_handlers 0x70 0x803ac48 +_zw_protocol_cmd_handlers_lr 0x30 0x803acb8 +.ARM.exidx 0x8 0x803ace8 +.copy.table 0xc 0x803acf0 +.zero.table 0x0 0x803acfc .stack 0x1000 0x20000000 -.data 0x684 0x20001000 -.bss 0xac60 0x20001684 -.heap 0x3d18 0x2000c2e8 -.internal_storage 0x2a000 0x803bae8 -.zwave_nvm 0x6000 0x8065ae8 -.nvm 0xa000 0x806bae8 +.data 0x68c 0x20001000 +.bss 0xace8 0x2000168c +.heap 0x3c88 0x2000c378 +.internal_storage 0x2c000 0x803acfc +.zwave_nvm 0x6000 0x8066cfc +.nvm 0x8000 0x806ccfc .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9d04 0x0 -.debug_info 0x9b0bf7 0x0 -.debug_abbrev 0x15d71 0x0 -.debug_loc 0x42887 0x0 -.debug_aranges 0x3720 0x0 -.debug_ranges 0x6c38 0x0 -.debug_line 0x4058b 0x0 -.debug_str 0x78eb8 0x0 -Total 0xb561f1 +.debug_frame 0x9908 0x0 +.debug_info 0x9ae447 0x0 +.debug_abbrev 0x154dc 0x0 +.debug_loc 0x3faa3 0x0 +.debug_aranges 0x3608 0x0 +.debug_ranges 0x69e0 0x0 +.debug_line 0x3ee8c 0x0 +.debug_str 0x78963 0x0 +Total 0xb4d21c The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 221548 + 217992 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 51940 + 52084 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205B_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205B_REGION_EU_size.txt index 16f91bf1ea..4d110a37e0 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205B_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205B_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x35bb0 0x8006000 -_cc_handlers_v3 0x1d4 0x803bbb0 -_zw_protocol_cmd_handlers 0x70 0x803bd84 -_zw_protocol_cmd_handlers_lr 0x30 0x803bdf4 -.ARM.exidx 0x8 0x803be24 -.copy.table 0xc 0x803be2c -.zero.table 0x0 0x803be38 +.text 0x3504c 0x8006000 +_cc_handlers_v3 0x1d4 0x803b04c +_zw_protocol_cmd_handlers 0x70 0x803b220 +_zw_protocol_cmd_handlers_lr 0x30 0x803b290 +.ARM.exidx 0x8 0x803b2c0 +.copy.table 0xc 0x803b2c8 +.zero.table 0x0 0x803b2d4 .stack 0x1000 0x20000000 -.data 0x684 0x20001000 -.bss 0xad90 0x20001684 -.heap 0x3be8 0x2000c418 -.internal_storage 0x2a000 0x803be38 -.zwave_nvm 0x6000 0x8065e38 -.nvm 0xa000 0x806be38 +.data 0x68c 0x20001000 +.bss 0xae20 0x2000168c +.heap 0x3b50 0x2000c4b0 +.internal_storage 0x2c000 0x803b2d4 +.zwave_nvm 0x6000 0x80672d4 +.nvm 0x8000 0x806d2d4 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9f14 0x0 -.debug_info 0x9b2e1f 0x0 -.debug_abbrev 0x15aba 0x0 -.debug_loc 0x445b2 0x0 -.debug_aranges 0x3750 0x0 -.debug_ranges 0x6d58 0x0 -.debug_line 0x41737 0x0 -.debug_str 0x7920b 0x0 -Total 0xb5ba3c +.debug_frame 0x9ea0 0x0 +.debug_info 0x9b2a79 0x0 +.debug_abbrev 0x158b1 0x0 +.debug_loc 0x44141 0x0 +.debug_aranges 0x3718 0x0 +.debug_ranges 0x6c10 0x0 +.debug_line 0x41206 0x0 +.debug_str 0x79261 0x0 +Total 0xb59de9 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 222396 + 219488 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52244 + 52396 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205B_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205B_REGION_US_LR_size.txt index 16f91bf1ea..4d110a37e0 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205B_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205B_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x35bb0 0x8006000 -_cc_handlers_v3 0x1d4 0x803bbb0 -_zw_protocol_cmd_handlers 0x70 0x803bd84 -_zw_protocol_cmd_handlers_lr 0x30 0x803bdf4 -.ARM.exidx 0x8 0x803be24 -.copy.table 0xc 0x803be2c -.zero.table 0x0 0x803be38 +.text 0x3504c 0x8006000 +_cc_handlers_v3 0x1d4 0x803b04c +_zw_protocol_cmd_handlers 0x70 0x803b220 +_zw_protocol_cmd_handlers_lr 0x30 0x803b290 +.ARM.exidx 0x8 0x803b2c0 +.copy.table 0xc 0x803b2c8 +.zero.table 0x0 0x803b2d4 .stack 0x1000 0x20000000 -.data 0x684 0x20001000 -.bss 0xad90 0x20001684 -.heap 0x3be8 0x2000c418 -.internal_storage 0x2a000 0x803be38 -.zwave_nvm 0x6000 0x8065e38 -.nvm 0xa000 0x806be38 +.data 0x68c 0x20001000 +.bss 0xae20 0x2000168c +.heap 0x3b50 0x2000c4b0 +.internal_storage 0x2c000 0x803b2d4 +.zwave_nvm 0x6000 0x80672d4 +.nvm 0x8000 0x806d2d4 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9f14 0x0 -.debug_info 0x9b2e1f 0x0 -.debug_abbrev 0x15aba 0x0 -.debug_loc 0x445b2 0x0 -.debug_aranges 0x3750 0x0 -.debug_ranges 0x6d58 0x0 -.debug_line 0x41737 0x0 -.debug_str 0x7920b 0x0 -Total 0xb5ba3c +.debug_frame 0x9ea0 0x0 +.debug_info 0x9b2a79 0x0 +.debug_abbrev 0x158b1 0x0 +.debug_loc 0x44141 0x0 +.debug_aranges 0x3718 0x0 +.debug_ranges 0x6c10 0x0 +.debug_line 0x41206 0x0 +.debug_str 0x79261 0x0 +Total 0xb59de9 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 222396 + 219488 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52244 + 52396 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205B_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205B_REGION_US_size.txt index 16f91bf1ea..4d110a37e0 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205B_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4205B_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x35bb0 0x8006000 -_cc_handlers_v3 0x1d4 0x803bbb0 -_zw_protocol_cmd_handlers 0x70 0x803bd84 -_zw_protocol_cmd_handlers_lr 0x30 0x803bdf4 -.ARM.exidx 0x8 0x803be24 -.copy.table 0xc 0x803be2c -.zero.table 0x0 0x803be38 +.text 0x3504c 0x8006000 +_cc_handlers_v3 0x1d4 0x803b04c +_zw_protocol_cmd_handlers 0x70 0x803b220 +_zw_protocol_cmd_handlers_lr 0x30 0x803b290 +.ARM.exidx 0x8 0x803b2c0 +.copy.table 0xc 0x803b2c8 +.zero.table 0x0 0x803b2d4 .stack 0x1000 0x20000000 -.data 0x684 0x20001000 -.bss 0xad90 0x20001684 -.heap 0x3be8 0x2000c418 -.internal_storage 0x2a000 0x803be38 -.zwave_nvm 0x6000 0x8065e38 -.nvm 0xa000 0x806be38 +.data 0x68c 0x20001000 +.bss 0xae20 0x2000168c +.heap 0x3b50 0x2000c4b0 +.internal_storage 0x2c000 0x803b2d4 +.zwave_nvm 0x6000 0x80672d4 +.nvm 0x8000 0x806d2d4 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9f14 0x0 -.debug_info 0x9b2e1f 0x0 -.debug_abbrev 0x15aba 0x0 -.debug_loc 0x445b2 0x0 -.debug_aranges 0x3750 0x0 -.debug_ranges 0x6d58 0x0 -.debug_line 0x41737 0x0 -.debug_str 0x7920b 0x0 -Total 0xb5ba3c +.debug_frame 0x9ea0 0x0 +.debug_info 0x9b2a79 0x0 +.debug_abbrev 0x158b1 0x0 +.debug_loc 0x44141 0x0 +.debug_aranges 0x3718 0x0 +.debug_ranges 0x6c10 0x0 +.debug_line 0x41206 0x0 +.debug_str 0x79261 0x0 +Total 0xb59de9 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 222396 + 219488 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52244 + 52396 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4207A_REGION_EU_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4207A_REGION_EU_size.txt index 7d575f2eeb..118ed3f495 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4207A_REGION_EU_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4207A_REGION_EU_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x2daec 0x0 -_cc_handlers_v3 0x1d4 0x2daec -_zw_protocol_cmd_handlers 0x70 0x2dcc0 -_zw_protocol_cmd_handlers_lr 0x30 0x2dd30 -.ARM.exidx 0x8 0x2dd60 -.copy.table 0xc 0x2dd68 -.zero.table 0x0 0x2dd74 +.text 0x2dc48 0x0 +_cc_handlers_v3 0x1d4 0x2dc48 +_zw_protocol_cmd_handlers 0x70 0x2de1c +_zw_protocol_cmd_handlers_lr 0x30 0x2de8c +.ARM.exidx 0x8 0x2debc +.copy.table 0xc 0x2dec4 +.zero.table 0x0 0x2ded0 .stack 0x1000 0x20000000 -.data 0x52c 0x20001000 -.bss 0x9e50 0x2000152c -.heap 0x4c80 0x2000b380 -.internal_storage 0x3a000 0x2dd74 -.zwave_nvm 0x3000 0x67d74 -.nvm 0x9000 0x6ad74 +.data 0x534 0x20001000 +.bss 0x9ed8 0x20001534 +.heap 0x4bf0 0x2000b410 +.internal_storage 0x3a000 0x2ded0 +.zwave_nvm 0x3000 0x67ed0 +.nvm 0x9000 0x6aed0 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x69e0 0x0 -.debug_info 0x96b345 0x0 -.debug_abbrev 0x100b9 0x0 -.debug_loc 0x25e12 0x0 +.debug_frame 0x69ec 0x0 +.debug_info 0x96b920 0x0 +.debug_abbrev 0x1012e 0x0 +.debug_loc 0x25e37 0x0 .debug_aranges 0x27e0 0x0 -.debug_ranges 0x4d58 0x0 -.debug_line 0x2b6a3 0x0 -.debug_str 0x6cdd8 0x0 -Total 0xacb38a +.debug_ranges 0x4d40 0x0 +.debug_line 0x2b6f3 0x0 +.debug_str 0x6cf0a 0x0 +Total 0xacbcd1 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 189088 + 189444 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47996 + 48140 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4207A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4207A_REGION_US_LR_size.txt index 7d575f2eeb..118ed3f495 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4207A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4207A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x2daec 0x0 -_cc_handlers_v3 0x1d4 0x2daec -_zw_protocol_cmd_handlers 0x70 0x2dcc0 -_zw_protocol_cmd_handlers_lr 0x30 0x2dd30 -.ARM.exidx 0x8 0x2dd60 -.copy.table 0xc 0x2dd68 -.zero.table 0x0 0x2dd74 +.text 0x2dc48 0x0 +_cc_handlers_v3 0x1d4 0x2dc48 +_zw_protocol_cmd_handlers 0x70 0x2de1c +_zw_protocol_cmd_handlers_lr 0x30 0x2de8c +.ARM.exidx 0x8 0x2debc +.copy.table 0xc 0x2dec4 +.zero.table 0x0 0x2ded0 .stack 0x1000 0x20000000 -.data 0x52c 0x20001000 -.bss 0x9e50 0x2000152c -.heap 0x4c80 0x2000b380 -.internal_storage 0x3a000 0x2dd74 -.zwave_nvm 0x3000 0x67d74 -.nvm 0x9000 0x6ad74 +.data 0x534 0x20001000 +.bss 0x9ed8 0x20001534 +.heap 0x4bf0 0x2000b410 +.internal_storage 0x3a000 0x2ded0 +.zwave_nvm 0x3000 0x67ed0 +.nvm 0x9000 0x6aed0 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x69e0 0x0 -.debug_info 0x96b345 0x0 -.debug_abbrev 0x100b9 0x0 -.debug_loc 0x25e12 0x0 +.debug_frame 0x69ec 0x0 +.debug_info 0x96b920 0x0 +.debug_abbrev 0x1012e 0x0 +.debug_loc 0x25e37 0x0 .debug_aranges 0x27e0 0x0 -.debug_ranges 0x4d58 0x0 -.debug_line 0x2b6a3 0x0 -.debug_str 0x6cdd8 0x0 -Total 0xacb38a +.debug_ranges 0x4d40 0x0 +.debug_line 0x2b6f3 0x0 +.debug_str 0x6cf0a 0x0 +Total 0xacbcd1 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 189088 + 189444 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47996 + 48140 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4207A_REGION_US_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4207A_REGION_US_size.txt index 7d575f2eeb..118ed3f495 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4207A_REGION_US_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4207A_REGION_US_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x2daec 0x0 -_cc_handlers_v3 0x1d4 0x2daec -_zw_protocol_cmd_handlers 0x70 0x2dcc0 -_zw_protocol_cmd_handlers_lr 0x30 0x2dd30 -.ARM.exidx 0x8 0x2dd60 -.copy.table 0xc 0x2dd68 -.zero.table 0x0 0x2dd74 +.text 0x2dc48 0x0 +_cc_handlers_v3 0x1d4 0x2dc48 +_zw_protocol_cmd_handlers 0x70 0x2de1c +_zw_protocol_cmd_handlers_lr 0x30 0x2de8c +.ARM.exidx 0x8 0x2debc +.copy.table 0xc 0x2dec4 +.zero.table 0x0 0x2ded0 .stack 0x1000 0x20000000 -.data 0x52c 0x20001000 -.bss 0x9e50 0x2000152c -.heap 0x4c80 0x2000b380 -.internal_storage 0x3a000 0x2dd74 -.zwave_nvm 0x3000 0x67d74 -.nvm 0x9000 0x6ad74 +.data 0x534 0x20001000 +.bss 0x9ed8 0x20001534 +.heap 0x4bf0 0x2000b410 +.internal_storage 0x3a000 0x2ded0 +.zwave_nvm 0x3000 0x67ed0 +.nvm 0x9000 0x6aed0 .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x69e0 0x0 -.debug_info 0x96b345 0x0 -.debug_abbrev 0x100b9 0x0 -.debug_loc 0x25e12 0x0 +.debug_frame 0x69ec 0x0 +.debug_info 0x96b920 0x0 +.debug_abbrev 0x1012e 0x0 +.debug_loc 0x25e37 0x0 .debug_aranges 0x27e0 0x0 -.debug_ranges 0x4d58 0x0 -.debug_line 0x2b6a3 0x0 -.debug_str 0x6cdd8 0x0 -Total 0xacb38a +.debug_ranges 0x4d40 0x0 +.debug_line 0x2b6f3 0x0 +.debug_str 0x6cf0a 0x0 +Total 0xacbcd1 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 189088 + 189444 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47996 + 48140 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4209A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4209A_REGION_US_LR_size.txt index 24c2363c25..85c60ab3e7 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4209A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4209A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x2daa8 0x0 -_cc_handlers_v3 0x1d4 0x2daa8 -_zw_protocol_cmd_handlers 0x70 0x2dc7c -_zw_protocol_cmd_handlers_lr 0x30 0x2dcec -.ARM.exidx 0x8 0x2dd1c -.copy.table 0xc 0x2dd24 -.zero.table 0x0 0x2dd30 +.text 0x2dbc4 0x0 +_cc_handlers_v3 0x1d4 0x2dbc4 +_zw_protocol_cmd_handlers 0x70 0x2dd98 +_zw_protocol_cmd_handlers_lr 0x30 0x2de08 +.ARM.exidx 0x8 0x2de38 +.copy.table 0xc 0x2de40 +.zero.table 0x0 0x2de4c .stack 0x1000 0x20000000 -.data 0x528 0x20001000 -.bss 0x9e34 0x20001528 -.heap 0x4ca0 0x2000b360 -.internal_storage 0x3a000 0x2dd30 -.zwave_nvm 0x3000 0x67d30 -.nvm 0x9000 0x6ad30 +.data 0x530 0x20001000 +.bss 0x9ebc 0x20001530 +.heap 0x4c10 0x2000b3f0 +.internal_storage 0x3a000 0x2de4c +.zwave_nvm 0x3000 0x67e4c +.nvm 0x9000 0x6ae4c .ARM.attributes 0x2e 0x0 .comment 0x49 0x0 -.debug_frame 0x6c10 0x0 -.debug_info 0x96cc18 0x0 -.debug_abbrev 0x10623 0x0 -.debug_loc 0x26921 0x0 +.debug_frame 0x6c1c 0x0 +.debug_info 0x96d1f3 0x0 +.debug_abbrev 0x10698 0x0 +.debug_loc 0x26946 0x0 .debug_aranges 0x28c0 0x0 -.debug_ranges 0x4f40 0x0 -.debug_line 0x2c6e4 0x0 -.debug_str 0x6d1ce 0x0 -Total 0xacf5c1 +.debug_ranges 0x4f28 0x0 +.debug_line 0x2c734 0x0 +.debug_str 0x6d301 0x0 +Total 0xacfec9 The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 189016 + 189308 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) 49152 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 47964 + 48108 diff --git a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4210A_REGION_US_LR_size.txt b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4210A_REGION_US_LR_size.txt index f92a5772e5..1d4e0a7f19 100644 --- a/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4210A_REGION_US_LR_size.txt +++ b/protocol/z-wave/Apps/bin/codesize/zwave_soc_wall_controller_BRD4210A_REGION_US_LR_size.txt @@ -5,38 +5,38 @@ The output of the size tool: (e.g. arm-none-ambi-size.exe) zwave_soc_wall_controller.out : section size addr -.text 0x35720 0x8006000 -_cc_handlers_v3 0x1d4 0x803b720 -_zw_protocol_cmd_handlers 0x70 0x803b8f4 -_zw_protocol_cmd_handlers_lr 0x30 0x803b964 -.ARM.exidx 0x8 0x803b994 -.copy.table 0xc 0x803b99c -.zero.table 0x0 0x803b9a8 +.text 0x34bbc 0x8006000 +_cc_handlers_v3 0x1d4 0x803abbc +_zw_protocol_cmd_handlers 0x70 0x803ad90 +_zw_protocol_cmd_handlers_lr 0x30 0x803ae00 +.ARM.exidx 0x8 0x803ae30 +.copy.table 0xc 0x803ae38 +.zero.table 0x0 0x803ae44 .stack 0x1000 0x20000000 -.data 0x688 0x20001000 -.bss 0xad74 0x20001688 -.heap 0x3c00 0x2000c400 -.internal_storage 0x2a000 0x803b9a8 -.zwave_nvm 0x6000 0x80659a8 -.nvm 0xa000 0x806b9a8 +.data 0x690 0x20001000 +.bss 0xae04 0x20001690 +.heap 0x3b68 0x2000c498 +.internal_storage 0x2c000 0x803ae44 +.zwave_nvm 0x6000 0x8066e44 +.nvm 0x8000 0x806ce44 .ARM.attributes 0x36 0x0 .comment 0x49 0x0 -.debug_frame 0x9f44 0x0 -.debug_info 0x9b2607 0x0 -.debug_abbrev 0x15a61 0x0 -.debug_loc 0x445c5 0x0 -.debug_aranges 0x3740 0x0 -.debug_ranges 0x6d68 0x0 -.debug_line 0x418f3 0x0 -.debug_str 0x78b31 0x0 -Total 0xb5a860 +.debug_frame 0x9ed0 0x0 +.debug_info 0x9b2261 0x0 +.debug_abbrev 0x15858 0x0 +.debug_loc 0x44151 0x0 +.debug_aranges 0x3708 0x0 +.debug_ranges 0x6c20 0x0 +.debug_line 0x413c2 0x0 +.debug_str 0x78b88 0x0 +Total 0xb58c0b The calculated FLASH and SRAM usage summary: ============================================ FLASH used as program memory: (Including only the sections: .text, .ARM.exidx, .data, _cc_handlers_v3) - 221232 + 218324 FLASH used for storage: (Including only the sections: .zwavenvm, .simee, .nvm, .zwave_nvm) - 65536 + 57344 SRAM usage: (Including only the sections: .data, .bss, .heap (limited to 2048 per sl_memory_config.h), .stack_dummy, .reset_info) - 52220 + 52372 diff --git a/protocol/z-wave/Apps/bin/demos.xml b/protocol/z-wave/Apps/bin/demos.xml index c7563a2660..878bbc78ab 100644 --- a/protocol/z-wave/Apps/bin/demos.xml +++ b/protocol/z-wave/Apps/bin/demos.xml @@ -1,235 +1,264 @@ - - - - - - + ota Bootloader for BRD2603A board + + + + + + - - - - - ota Bootloader for BRD4200A board + + + + + + - - - - - ota Bootloader for BRD4201C board + + + + + + - - - - - ota Bootloader for BRD4201D board + + + + + + - - - - - ota Bootloader for BRD4202A board + + + + + + - - - - - ota Bootloader for BRD4204A board + + + + + + - - - - - ota Bootloader for BRD4204B board + + + + + + - - - - - ota Bootloader for BRD4204C board + + + + + + - - - - - ota Bootloader for BRD4204D board + + + + + + - - - - - - + ota Bootloader for BRD4205A board + + + + + + - - - - - - + ota Bootloader for BRD4205B board + + + + + + - - - - - ota Bootloader for BRD4207A board + + + + + + - - - - - ota Bootloader for BRD4209A board + + + + + + - - - - - ota Bootloader for BRD4210A board + + + + + + - - - - - - + otw Bootloader for BRD2603A board + + + + + + - - - - - otw Bootloader for BRD4200A board + + + + + + - - - - - otw Bootloader for BRD4201A board + + + + + + - - - - - otw Bootloader for BRD4202A board + + + + + + - - - - - otw Bootloader for BRD4204A board + + + + + + - - - - - otw Bootloader for BRD4204B board + + + + + + - - - - - otw Bootloader for BRD4204C board + + + + + + - - - - - otw Bootloader for BRD4204D board + + + + + + - - - - - - + otw Bootloader for BRD4205A board + + + + + + - - - - - - + otw Bootloader for BRD4205B board + + + + + + - - - - - otw Bootloader for BRD4206A board + + + + + + - - - - - otw Bootloader for BRD4207A board + + + + + + - - - - - otw Bootloader for BRD4208A board + + + + + + - - - - - otw Bootloader for BRD4209A board + + + + + + - - - - - otw Bootloader for BRD4210A board + + + + + + diff --git a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD2603A.gbl b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD2603A.gbl index bc93d0b07b..8fc9f2ecd1 100644 --- a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD2603A.gbl +++ b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD2603A.gbl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d69c04d3f02592bbc010c6e8ad6a89a4eaf3ccdb0f0eee8a704a730eedf25650 -size 132780 +oid sha256:1690ba71ef895652149ee21cf95c9d18caa56f2d5f8e4f512ffb8cf28b921b04 +size 133576 diff --git a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD2603A_v255.gbl b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD2603A_v255.gbl index ee30ea18ef..b37138d4f9 100644 --- a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD2603A_v255.gbl +++ b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD2603A_v255.gbl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c248676c12dff6c4410b9b05c9f0bdde7940fddc75afe046318bf22214f6881f -size 132784 +oid sha256:9cbda9704f3238679a1916bee2a12e77d0ed7104810327525d620dbb15ac389e +size 133568 diff --git a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4201A.gbl b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4201A.gbl index b9e64fb77c..1ca7b62637 100644 --- a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4201A.gbl +++ b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4201A.gbl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2cbd2a4bbc8ad0f505525bfc832a94d59c2f91549b7b2e88e8e1c80388a4f038 -size 166224 +oid sha256:4a8e0d2114d768ee142a181497cc7f5032d0ad85efd5dc2e892d2309aecdf05b +size 166756 diff --git a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4201A_v255.gbl b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4201A_v255.gbl index 162c7d9be1..a2b7cbce45 100644 --- a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4201A_v255.gbl +++ b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4201A_v255.gbl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:dadda4b77eb1baa82017fbc2a051f662b087a74f64c20dd139ac5576f653635e -size 166220 +oid sha256:48ef53b8db5363691893d0e8b79920284276aaac194c969f5e350b75ef0148c2 +size 166752 diff --git a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4202A.gbl b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4202A.gbl index facf6cf0fc..564cc11bb2 100644 --- a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4202A.gbl +++ b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4202A.gbl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2cf14c3f379e05349bde5b9f6bb4d2e9c942d8b3f405d3ef1efd8596e7a95f31 -size 168192 +oid sha256:92b74ea4738911bdd67414101926cfe832f987978db1c42fa57c08b5d5356ffa +size 168636 diff --git a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4202A_v255.gbl b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4202A_v255.gbl index 3506acdd5f..23f27242fa 100644 --- a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4202A_v255.gbl +++ b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4202A_v255.gbl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:452b8fbd6ef415dc3c25248eec5ca5a0bf7024cdad35977601cd9cd50a36c605 -size 168192 +oid sha256:d1e8e024fd14aaa3e5166baf26feee57d1d849a419a705bfb1e7207b42062d8f +size 168632 diff --git a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204C.gbl b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204C.gbl index 839b025308..7c6a85e045 100644 --- a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204C.gbl +++ b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204C.gbl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:efc93aa26d03518f826aa353e5ffcd4f11b8391d3f61f691bc652418d2ce41cb -size 131988 +oid sha256:906a1fd5ff2ba14c4b501b21f40c8c7bf95d07c01ea263d26bbcf58ed305632c +size 132784 diff --git a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204C_v255.gbl b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204C_v255.gbl index 009d052c5e..488228e1a5 100644 --- a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204C_v255.gbl +++ b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204C_v255.gbl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0c8632dbe0574e250b7a4888cf01b94472d2fa3ff8eede80b447af83a1a0693b -size 131980 +oid sha256:38bc0ffe6de9a710afb1ff0b3ade1d979e9ac88605c194fbfad3752f84f17229 +size 132784 diff --git a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204D.gbl b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204D.gbl index 876bab71dd..3f64903f91 100644 --- a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204D.gbl +++ b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204D.gbl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:165b1e965187faff5e9c42f8810c920d726953dd0d244b3fb5d6d467b6b331f4 -size 132116 +oid sha256:a512e2caea77a622c311a0446a86d6328edbb4218f64d3cc68529612ea88e0ff +size 132984 diff --git a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204D_v255.gbl b/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204D_v255.gbl index 0b1d66958b..8cc53f7957 100644 --- a/protocol/z-wave/Apps/bin/gbl/zwave_ncp_serial_api_controller_BRD4204D_v255.gbl +++ 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a/protocol/z-wave/Apps/bin/gbl/zwave_soc_wall_controller_BRD4207A.gbl b/protocol/z-wave/Apps/bin/gbl/zwave_soc_wall_controller_BRD4207A.gbl index 649f1705ac..e4ef02023a 100644 --- a/protocol/z-wave/Apps/bin/gbl/zwave_soc_wall_controller_BRD4207A.gbl +++ b/protocol/z-wave/Apps/bin/gbl/zwave_soc_wall_controller_BRD4207A.gbl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e1da58adfaab38638d972858479b0571942416b0493df5170971a94ab8b753a8 -size 169060 +oid sha256:1bda89cd29bee7ef99f0a1e93be2b7b038023fb3799d342046671b08a42e70c9 +size 169356 diff --git a/protocol/z-wave/Apps/bin/gbl/zwave_soc_wall_controller_BRD4207A_v255.gbl b/protocol/z-wave/Apps/bin/gbl/zwave_soc_wall_controller_BRD4207A_v255.gbl index 32e922cd74..bb8a1d7c8f 100644 --- a/protocol/z-wave/Apps/bin/gbl/zwave_soc_wall_controller_BRD4207A_v255.gbl +++ b/protocol/z-wave/Apps/bin/gbl/zwave_soc_wall_controller_BRD4207A_v255.gbl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:17a2e09e636b8389796dc8f97709c369029574ff68e402832b7648fa5f2e6423 -size 169060 +oid sha256:9af3dd8905c8593be3c463346ccfdc704bf69bf3a97aa53f6634247dc68470b2 +size 169360 diff --git a/protocol/z-wave/Components/MfgTokens/MfgTokens.h b/protocol/z-wave/Components/MfgTokens/MfgTokens.h index df697e509d..e664632935 100644 --- a/protocol/z-wave/Components/MfgTokens/MfgTokens.h +++ b/protocol/z-wave/Components/MfgTokens/MfgTokens.h @@ -41,14 +41,12 @@ extern "C" { #define TOKEN_MFG_ZW_PUK_ID 0x0003 #define TOKEN_MFG_ZW_INITIALIZED_ID 0x0004 #define TOKEN_MFG_ZW_QR_CODE_ID 0x0005 -#define TOKEN_MFG_ZW_QR_CODE_EXT_ID 0x0006 #define TOKEN_MFG_ZWAVE_COUNTRY_FREQ_SIZE 1 // bytes #define TOKEN_MFG_ZW_PRK_SIZE 32 // bytes #define TOKEN_MFG_ZW_PUK_SIZE 32 // bytes #define TOKEN_MFG_ZW_INITIALIZED_SIZE 1 // bytes -#define TOKEN_MFG_ZW_QR_CODE_SIZE 90 // bytes -#define TOKEN_MFG_ZW_QR_CODE_EXT_SIZE 16 // bytes +#define TOKEN_MFG_ZW_QR_CODE_SIZE 106 // bytes /** * Function for initializing manufacturing module diff --git a/protocol/z-wave/NonCertifiableApps/KeyFob/events.h b/protocol/z-wave/NonCertifiableApps/KeyFob/events.h index eade102c87..989c13368e 100644 --- a/protocol/z-wave/NonCertifiableApps/KeyFob/events.h +++ b/protocol/z-wave/NonCertifiableApps/KeyFob/events.h @@ -25,6 +25,7 @@ typedef enum EVENT_APP_SWITCH_ON_OFF EVENT_EMPTY = DEFINE_EVENT_APP_NBR, EVENT_APP_INIT, EVENT_APP_REFRESH_MMI, + EVENT_APP_FLUSHMEM_READY, EVENT_APP_IS_POWERING_DOWN, EVENT_APP_NEXT_EVENT_JOB, EVENT_APP_FINISH_EVENT_JOB, diff --git a/protocol/z-wave/NonCertifiableApps/KeyFob/key_fob.c b/protocol/z-wave/NonCertifiableApps/KeyFob/key_fob.c index 85f2692c7f..47061478af 100644 --- a/protocol/z-wave/NonCertifiableApps/KeyFob/key_fob.c +++ b/protocol/z-wave/NonCertifiableApps/KeyFob/key_fob.c @@ -48,7 +48,11 @@ #include "events.h" // Command Classes +#include +#include + #include + #include #include @@ -60,10 +64,8 @@ #include "sl_status.h" #include "zw_region_config.h" #include "zw_build_no.h" - #include "zpal_nvm.h" #include "ZAF_nvm_app.h" -#include #include /****************************************************************************/ @@ -81,6 +83,8 @@ #define PM_STAY_AWAKE_DURATION_REBOOT (1000 * 4) // [ms] #define PM_STAY_AWAKE_DURATION_BTN (1000 * 15) // [ms] #define PM_STAY_AWAKE_DURATION_LEARN_MODE (1000 * 10) // [ms] +#define PM_STAY_AWAKE_DURATION_3_SEC (1000 * 3) +#define PM_STAY_AWAKE_DURATION_REPORT_WAIT (1000 * 10) // [ms] /** * Application states. Function AppStateManager(..) includes the state @@ -94,13 +98,10 @@ typedef enum _STATE_APP_ STATE_APP_ASSOCIATION, /**< STATE_APP_ASSOCIATION */ STATE_APP_TRANSMIT_DATA, /**< STATE_APP_TRANSMIT_DATA */ STATE_APP_NETWORK_LEARNMODE, /**< STATE_APP_NETWORK_LEARNMODE */ + STATE_APP_RESET /**< STATE_APP_RESET */ } STATE_APP; -#define BASIC_SET_TRIGGER_VALUE 0xFF -#define BASIC_CLEAR_TRIGGER_VALUE 0x00 - /** - * * Note: enum order is important, should be in sync with g_aEventHandlerTable elements */ typedef enum EApplicationEvent @@ -116,14 +117,6 @@ typedef enum EApplicationEvent /* STATIC FUNCTION DECLARATION */ /****************************************************************************/ -/** - * Handler for Configuration CC get info command - * @param[in] pRxOpt Receive options. - * @param[in] pCmd Payload including command class. - * @param[in] cmdLength Length of the received command. - * @return Result of command parsing. -*/ - /** * Task for initialize * @param[in] pAppHandles Application handle @@ -167,7 +160,9 @@ static void EventHandlerApp(void); static void EventQueueInit(); -SBatteryData readBatteryData(void); +static void SendBasicSetDone(void); + +static void SupervisionReport(void *pSubscriberContext, void* pRxPackage); /** * Handler for application related tasks, called from button push @@ -178,8 +173,6 @@ static void AppStateManager(EVENT_APP event); static void handle_network_management_states(node_id_t current_node_id); -void SendDeviceResetLocally(void); - /****************************************************************************/ /* Application specific button and LED definitions */ /****************************************************************************/ @@ -190,7 +183,7 @@ static const EventDistributorEventHandler g_aEventHandlerTable[] = EventHandlerZwRx, // EAPPLICATIONEVENT_ZWRX = 1 EventHandlerZwCommandStatus, // EAPPLICATIONEVENT_ZWCOMMANDSTATUS = 2 EventHandlerApp, // EAPPLICATIONEVENT_APP = 3 - KeyFobStateHandler // EAPPLICATIONEVENT_STATECHANGE = 4 + KeyFobStateHandler // EAPPLICATIONEVENT_STATECHANGE = 4 }; static zpal_pm_handle_t m_RadioPowerLock; @@ -222,6 +215,9 @@ static SRadioConfig_t RadioConfig = { static uint8_t cmdClassListNonSecureNotIncluded[] = { COMMAND_CLASS_ZWAVEPLUS_INFO, + COMMAND_CLASS_ASSOCIATION, + COMMAND_CLASS_MULTI_CHANNEL_ASSOCIATION_V2, + COMMAND_CLASS_ASSOCIATION_GRP_INFO, COMMAND_CLASS_TRANSPORT_SERVICE_V2, COMMAND_CLASS_BATTERY, COMMAND_CLASS_MANUFACTURER_SPECIFIC, @@ -241,7 +237,7 @@ static uint8_t cmdClassListNonSecureIncludedSecure[] = COMMAND_CLASS_TRANSPORT_SERVICE_V2, COMMAND_CLASS_SECURITY, COMMAND_CLASS_SECURITY_2, - COMMAND_CLASS_SUPERVISION, + COMMAND_CLASS_SUPERVISION }; /** @@ -249,6 +245,9 @@ static uint8_t cmdClassListNonSecureIncludedSecure[] = */ static uint8_t cmdClassListSecure[] = { + COMMAND_CLASS_ASSOCIATION, + COMMAND_CLASS_MULTI_CHANNEL_ASSOCIATION_V2, + COMMAND_CLASS_ASSOCIATION_GRP_INFO, COMMAND_CLASS_BATTERY, COMMAND_CLASS_VERSION, COMMAND_CLASS_MANUFACTURER_SPECIFIC, @@ -297,7 +296,6 @@ static STATE_APP currentState = STATE_APP_IDLE; */ static EResetReason_t g_eResetReason; -//static SSwTimer EventJobsTimer; static SSwTimer JobTimer; #define APP_EVENT_QUEUE_SIZE 5 @@ -334,14 +332,6 @@ static zpal_nvm_handle_t pFileSystemApplication; /****************************************************************************/ /* Static Functions */ /****************************************************************************/ -#if defined(DEBUGPRINT) && defined(BUILDING_WITH_UC) -#include "sl_iostream.h" -static void DebugPrinter(const uint8_t * buffer, uint32_t len) -{ - sl_iostream_write(SL_IOSTREAM_STDOUT, buffer, len); -} -#endif - ZW_APPLICATION_STATUS ApplicationInit(EResetReason_t eResetReason) { @@ -351,12 +341,8 @@ ApplicationInit(EResetReason_t eResetReason) Board_Init(); #ifdef DEBUGPRINT -#if BUILDING_WITH_UC - DebugPrintConfig(m_aDebugPrintBuffer, sizeof(m_aDebugPrintBuffer), DebugPrinter); -#else zpal_debug_init(); DebugPrintConfig(m_aDebugPrintBuffer, sizeof(m_aDebugPrintBuffer), zpal_debug_output); -#endif // BUILDING_WITH_UC #endif // DEBUGPRINT DPRINT("\n\n===ApplicationInit===\n"); @@ -383,6 +369,14 @@ ApplicationInit(EResetReason_t eResetReason) // Init file system ApplicationFileSystemInit(&pFileSystemApplication); + // Read Rf region from MFG_ZWAVE_COUNTRY_FREQ + zpal_radio_region_t regionMfg; + ZW_GetMfgTokenDataCountryFreq((void*) ®ionMfg); + if (isRfRegionValid(regionMfg)) { + RadioConfig.eRegion = regionMfg; + } else { + ZW_SetMfgTokenDataCountryRegion((void*) &RadioConfig.eRegion); + } /************************************************************************************* * CREATE USER TASKS - ZW_ApplicationRegisterTask() and ZW_UserTask_CreateTask() @@ -410,22 +404,170 @@ ApplicationInit(EResetReason_t eResetReason) } /** - * The callback functions that will be called as the last step just before the - * chip enters EM4 hibernate. - * - * NB: When the function is called the OS tick has been disabled and the FreeRTOS - * scheduler is no longer running. OS features like events, queues and timers - * are therefore unavailable and must not be called from the callback function. - * - * The callback functions can be used to set pins and write to retention RAM. - * Do NOT try to write to the NVM file system. - * - * The maximum number of functions that can be registered is given by the macro - * MAX_POWERDOWN_CALLBACKS in ZW_PowerManager_api.h +* Aquire a list of included nodes IDS in the network from protocol +* +* Method requires CommandStatus queue from protocol to be empty. +* Method requires CommandQueue to protocol to be empty. +* Method will cause assert on failure. +* +* @param[out] node_id_list Pointer to bitmask list where aquired included nodes IDs saved +*/ +static void Get_included_nodes(uint8_t* node_id_list) +{ + const SApplicationHandles *m_pAppHandles = ZAF_getAppHandle(); + SZwaveCommandPackage GetIncludedNodesCommand = { + .eCommandType = EZWAVECOMMANDTYPE_ZW_GET_INCLUDED_NODES}; + + // Put the Command on queue (and dont wait for it, queue must be empty) + EQueueNotifyingStatus QueueStatus = QueueNotifyingSendToBack(m_pAppHandles->pZwCommandQueue, (uint8_t *)&GetIncludedNodesCommand, 0); + ASSERT(EQUEUENOTIFYING_STATUS_SUCCESS == QueueStatus); + // Wait for protocol to handle command (it shouldnt take long) + SZwaveCommandStatusPackage includedNodes; + if (GetCommandResponse(&includedNodes, EZWAVECOMMANDSTATUS_ZW_GET_INCLUDED_NODES)) + { + memcpy(node_id_list, (uint8_t*)includedNodes.Content.GetIncludedNodes.node_id_list, sizeof(NODE_MASK_TYPE)); + return; + } + ASSERT(false); +} + +static uint8_t sv_session_id = 0x30; +/* build a supervision get command + * + * @param[out] getFrame Buffer to store the built supervision get command + * @param[out] getLen The lenght of the built supervision get command + * @param[in] cmdFrame The command to be encapsulated into the supervision get command + * @param[in] cmdLen The lenght of the command to be encapsulated into the supervision get command */ -static void powerDownCB(void) +static void BuildSupervisionGet(uint8_t *getFrame, + uint16_t *getLen, + uint8_t *cmdFrame, + uint8_t cmdLen) { - DPRINT("powerDownCB() - Powering down\n"); + *getLen = 0; + if (0 == sv_session_id) + sv_session_id = 1; + getFrame[(*getLen)++] = COMMAND_CLASS_SUPERVISION; + getFrame[(*getLen)++] = SUPERVISION_GET; + getFrame[(*getLen)++] = sv_session_id++ & SUPERVISION_GET_PROPERTIES1_SESSION_ID_MASK; + getFrame[(*getLen)++] = cmdLen; + memcpy(&getFrame[*getLen], cmdFrame, cmdLen); + *getLen += cmdLen; +} + +static uint8_t SendSecureFrame(node_id_t node_id, + zwave_keyset_t tx_key, + uint8_t number_of_responses, + bool isMultiCast, + uint8_t *pData, + size_t data_length, + void (*pCallback)(uint8_t, const TX_STATUS_TYPE*)) +{ + SZwaveTransmitPackage TransmitPackage; + memset(&TransmitPackage, 0, sizeof(TransmitPackage)); + TransmitPackage.eTransmitType = EZWAVETRANSMITTYPE_SECURE; + SSecureSendData *params = &TransmitPackage.uTransmitParams.SendDataParams; + if (isMultiCast) { + node_storage_group_member_nodemask_get((uint8_t*)params->connection.remote.address.nodeList.nodeMask, + sizeof(params->connection.remote.address.nodeList.nodeMask)); + params->connection.remote.is_multicast = isMultiCast; + } else { + params->connection.remote.address.node_id = node_id; + } + params->tx_options.number_of_responses = number_of_responses; + params->tx_keys = tx_key; + params->ptxCompleteCallback = pCallback; + memcpy(params->data, pData, data_length); + params->data_length = data_length; + + // Put the package on queue (and don't wait for it) + return EQUEUENOTIFYING_STATUS_SUCCESS == QueueNotifyingSendToBack(g_pAppHandles->pZwTxQueue, (uint8_t*)&TransmitPackage, 0); +} + + +/** + * @brief keyfob is working as secondary then we need to know if the slave node is included with + * security or not + * + * First we send basic get cmd using s2_unautnticated + * If we received basic report then we update the security information for the node + * if not then we try with s0 if we succeeded then we update the security information for the node + */ +static bool SendBasicGet(node_id_t node_id, zwave_keyset_t tx_key) +{ + DPRINT("\nbasic_get"); + uint8_t basic_get[] = {COMMAND_CLASS_BASIC, BASIC_GET}; + TimerStart(&JobTimer, PM_STAY_AWAKE_DURATION_REPORT_WAIT); + // Put the package on queue (and don't wait for it) + return (true == SendSecureFrame(node_id, tx_key, 0, false, basic_get, sizeof(basic_get), NULL)); +} + +static NODE_MASK_TYPE nodeid_list; +static node_id_t probed_nodeid = 0; +static void NodeSecurityProbe(bool init); + +static void BasicReprotReceived (void *pSubscriberContext, void* pRxPackage) { + (void)pSubscriberContext; + (void)pRxPackage; + TimerStop(&JobTimer); + + SZwaveCommandPackage CommandPackage; + CommandPackage.eCommandType = EZWAVECOMMANDTYPE_SECURE_NETWORK_MANAGEMENT_SET_SECURITY_FLAGS; + CommandPackage.uCommandParams.SetSecurityFlags.nodeID = probed_nodeid; + + if (NETWORK_MANAGEMENT_STATE_S2_PROBE == get_current_network_management_state()) + { + CommandPackage.uCommandParams.SetSecurityFlags.nodeS2Capable = true; + CommandPackage.uCommandParams.SetSecurityFlags.nodeS2Included = true; + CommandPackage.uCommandParams.SetSecurityFlags.nodeSecureIncluded = true; + QueueNotifyingSendToBack(g_pAppHandles->pZwCommandQueue, (uint8_t*) &CommandPackage, 500); + + ZW_NODE_MASK_CLEAR_BIT(nodeid_list, probed_nodeid ); + NodeSecurityProbe(false); + } + else if (NETWORK_MANAGEMENT_STATE_S0_PROBE == get_current_network_management_state()) + { + CommandPackage.uCommandParams.SetSecurityFlags.nodeS2Capable = false; + CommandPackage.uCommandParams.SetSecurityFlags.nodeS2Included = false; + CommandPackage.uCommandParams.SetSecurityFlags.nodeSecureIncluded = true; + QueueNotifyingSendToBack(g_pAppHandles->pZwCommandQueue, (uint8_t*) &CommandPackage, 500); + + set_new_network_management_state(NETWORK_MANAGEMENT_STATE_S2_PROBE); + ZW_NODE_MASK_CLEAR_BIT(nodeid_list, probed_nodeid ); + NodeSecurityProbe(false); + } +} + +static void NodeSecurityProbe(bool init) +{ + if (true == init) { + Get_included_nodes(nodeid_list); + set_new_network_management_state(NETWORK_MANAGEMENT_STATE_S2_PROBE); + ZAF_CP_SubscribeToCmd(ZAF_getCPHandle(), NULL, BasicReprotReceived, COMMAND_CLASS_BASIC, BASIC_REPORT); + probed_nodeid = 2; + } + + while((0 == ZW_NODE_MASK_NODE_IN(nodeid_list, probed_nodeid)) || + (probed_nodeid == g_pAppHandles->pNetworkInfo->NodeId)) + { + probed_nodeid++; + } + + if (probed_nodeid < ZW_MAX_NODES) { + zpal_pm_stay_awake(m_RadioPowerLock, PM_STAY_AWAKE_DURATION_3_SEC); + if (NETWORK_MANAGEMENT_STATE_S2_PROBE == get_current_network_management_state()) { + SendBasicGet(probed_nodeid, SECURITY_KEY_S2_UNAUTHENTICATED_BIT); + } else { + SendBasicGet(probed_nodeid, SECURITY_KEY_S0_BIT); + } + } else { + ZAF_CP_UnsubscribeToCmd(ZAF_getCPHandle(), NULL, BasicReprotReceived, COMMAND_CLASS_BASIC, BASIC_REPORT); + zpal_pm_cancel(m_RadioPowerLock); + KeyFob_network_learnmode_led_handler(false); + ChangeState(STATE_APP_IDLE); + ZAF_EventHelperEventEnqueue(EVENT_APP_FINISH_EVENT_JOB); + } + } static void @@ -454,8 +596,31 @@ ZCB_JobTimeout(SSwTimer *pTimer) DPRINT("ZCB: Network LearnMode timeout\n"); handle_network_management_states(0); } + else if (NETWORK_MANAGEMENT_STATE_SECURITY_PROBE == get_current_network_management_state()) + { + /*We start probing slave nodes for granted security keys*/ + NodeSecurityProbe(true); + } + else if (NETWORK_MANAGEMENT_STATE_S2_PROBE == get_current_network_management_state()) + { + /*probing the current node for s2 failed then try s0*/ + set_new_network_management_state(NETWORK_MANAGEMENT_STATE_S0_PROBE); + NodeSecurityProbe(false); + } + else if (NETWORK_MANAGEMENT_STATE_S0_PROBE == get_current_network_management_state()) + { + set_new_network_management_state(NETWORK_MANAGEMENT_STATE_S2_PROBE); + /*probing the current node for s0 (and s2) failed then removed with from the list*/ + ZW_NODE_MASK_CLEAR_BIT(nodeid_list, probed_nodeid ); + NodeSecurityProbe(false); + } + else if ((NETWORK_MANAGEMENT_STATE_IDLE == get_current_network_management_state()) && + STATE_APP_TRANSMIT_DATA== currentState) { + SendBasicSetDone(); + } } + static __attribute__((noreturn)) void ApplicationTask(SApplicationHandles* pAppHandles) { @@ -469,26 +634,25 @@ ApplicationTask(SApplicationHandles* pAppHandles) ZAF_Init(g_AppTaskHandle, pAppHandles, &ProtocolConfig, NULL); ZAF_setApplicationData(g_AppTaskHandle, pAppHandles, &ProtocolConfig); - - EventQueueInit(); // Initialize the slew of modules made for event management. - + EventQueueInit(); // Initialize the slew of modules made for event management. // Init AppTimer with an app handle AppTimerInit(EAPPLICATIONEVENT_TIMER, g_AppTaskHandle); AppTimerRegister(&JobTimer, false, ZCB_JobTimeout); + ZAF_CP_SubscribeToCmd(ZAF_getCPHandle(), NULL, SupervisionReport, COMMAND_CLASS_SUPERVISION, SUPERVISION_REPORT); + // Setup power management. m_RadioPowerLock = zpal_pm_register(ZPAL_PM_TYPE_USE_RADIO); if ((ERESETREASON_DEEP_SLEEP_WUT != g_eResetReason) && (ERESETREASON_DEEP_SLEEP_EXT_INT != g_eResetReason)) { - zpal_pm_stay_awake(m_RadioPowerLock, PM_STAY_AWAKE_DURATION_REBOOT); // Allowing time for choosing learnmode after reset. + zpal_pm_stay_awake(m_RadioPowerLock, PM_STAY_AWAKE_DURATION_REBOOT); // Allowing time for choosing learnmode after reset. } - ZAF_PM_SetPowerDownCallback(powerDownCB); // Generate event that says the APP needs additional initialization. - ZAF_EventHelperEventEnqueue(EVENT_APP_INIT); // The state is already set to STATE_APP_STARTUP. + ZAF_EventHelperEventEnqueue(EVENT_APP_INIT); // The state is already set to STATE_APP_STARTUP. //Initialize buttons @@ -568,9 +732,13 @@ SetDefaultConfiguration(void) { zpal_status_t errCode; + AssociationInit(true, pFileSystemApplication); + + ZAF_Reset(); + uint32_t appVersion = zpal_get_app_version(); errCode = zpal_nvm_write(pFileSystemApplication, ZAF_FILE_ID_APP_VERSION, &appVersion, ZAF_FILE_SIZE_APP_VERSION); - ASSERT(ZPAL_STATUS_OK == errCode); //Assert has been kept for debugging , can be removed from production code if this error can only be caused by some internal flash HW failure + ASSERT(ZPAL_STATUS_OK == errCode); // Assert has been kept for debugging , can be removed from production code if this error can only be caused by some internal flash HW failure // Set default Basic Set Group - no members node_storage_init_group(); @@ -610,6 +778,9 @@ LoadConfiguration(void) // Add code for migration of file system to higher version here. } + /* Initialize association module */ + AssociationInit(false, pFileSystemApplication); + // End Device node IDs in Basic Set Association group will be stored in non volatile memory node_storage_init_group(); @@ -641,14 +812,8 @@ static void doRemainingInitialization() bool filesExist = LoadConfiguration(); UNUSED(filesExist); - /* Re-load and process EM4 persistent application timers. - * NB: Before calling AppTimerEm4PersistentLoadAll here, all - * application timers must have been registered with - * AppTimerRegister() or AppTimerEm4PersistentRegister(). - * Essentially it means that all CC handlers must be - * initialized first. - */ -// AppTimerEm4PersistentLoadAll(g_eResetReason); + // Setup AGI group lists + AGI_Init(); /* * Initialize Event Scheduler. @@ -685,6 +850,21 @@ static void doRemainingInitialization() } } +uint8_t IsPrimaryController(void) +{ + const SApplicationHandles *m_pAppHandles = ZAF_getAppHandle(); + SZwaveCommandPackage cmdPackage = { + .eCommandType = EZWAVECOMMANDTYPE_IS_PRIMARY_CTRL}; + EQueueNotifyingStatus QueueStatus = QueueNotifyingSendToBack(m_pAppHandles->pZwCommandQueue, (uint8_t *)&cmdPackage, 500); + ASSERT(EQUEUENOTIFYING_STATUS_SUCCESS == QueueStatus); + SZwaveCommandStatusPackage cmdStatus; + if (GetCommandResponse(&cmdStatus, EZWAVECOMMANDSTATUS_IS_PRIMARY_CTRL)) + { + return cmdStatus.Content.IsPrimaryCtrlStatus.result; + } + ASSERT(false); + return 0; +} static void EventHandlerZwRx(void) { @@ -705,7 +885,8 @@ static void EventHandlerZwRx(void) DPRINT("-->EZWAVERECEIVETYPE_SINGLE\n"); break; case EZWAVERECEIVETYPE_SECURE_FRAME_RECEIVED: - ApplicationCommandHandler(NULL, &RxPackage); + ZAF_CP_CommandPublish(ZAF_getCPHandle(), (void *) &RxPackage); + TimerStart(&JobTimer, PM_STAY_AWAKE_DURATION_3_SEC); break; case EZWAVERECEIVETYPE_NODE_UPDATE: @@ -832,7 +1013,7 @@ static void EventHandlerZwCommandStatus(void) case EZWAVECOMMANDSTATUS_SECURE_ON_NETWORK_MANAGEMENT_STATE_UPDATE: ///< Secure network management changed state - DPRINTF("-->EZWAVECOMMANDSTATUS_SECURE_ON_NETWORK_MANAGEMENT_STATE_UPDATE %u\n", Status.Content.USecureAppNotification); + DPRINTF("-->EZWAVECOMMANDSTATUS_SECURE_ON_NETWORK_MANAGEMENT_STATE_UPDATE %u\n", Status.Content.USecureAppNotification.nodeNetworkManagement.state); if (0 == Status.Content.USecureAppNotification.nodeNetworkManagement.state) { handle_network_management_states(0); @@ -847,11 +1028,17 @@ static void EventHandlerZwCommandStatus(void) case EZWAVECOMMANDSTATUS_SECURE_ON_FRAME_TRANSMISSION: ///< Frame transmission result DPRINT("-->EZWAVECOMMANDSTATUS_SECURE_ON_FRAME_TRANSMISSION\n"); + if ( NETWORK_MANAGEMENT_STATE_SECURITY_PROBE== get_current_network_management_state()) { + TimerStart(&JobTimer, 2 * 1000); + } break; case EZWAVECOMMANDSTATUS_SECURE_ON_RX_FRAME_RECEIVED_INDICATOR: ///< Frame received from NodeID indicator DPRINT("-->EZWAVECOMMANDSTATUS_SECURE_ON_RX_FRAME_RECEIVED_INDICATOR\n"); + if ( NETWORK_MANAGEMENT_STATE_SECURITY_PROBE== get_current_network_management_state()) { + TimerStart(&JobTimer, 2 * 1000); + } break; case EZWAVECOMMANDSTATUS_LEARN_MODE_STATUS: @@ -859,10 +1046,12 @@ static void EventHandlerZwCommandStatus(void) break; case EZWAVECOMMANDSTATUS_SET_DEFAULT: + { DPRINT("-->EZWAVECOMMANDSTATUS_SET_DEFAULT\n"); - DPRINT("Portable Controller reset to Default\n"); - Board_ResetHandler(); + DPRINT("Protocol Ready for reset\r\n"); + ZAF_EventHelperEventEnqueue(EVENT_APP_FLUSHMEM_READY); break; + } case EZWAVECOMMANDSTATUS_REPLACE_FAILED_NODE_ID: DPRINT("-->EZWAVECOMMANDSTATUS_REPLACE_FAILED_NODE_ID\n"); @@ -906,51 +1095,37 @@ static void ChangeState(STATE_APP newState) } } +static uint8_t nodesInGroup = 0; static void -SendBasicSetToGroupCallback( - uint8_t txStatus, - const TX_STATUS_TYPE *txStatusType) -{ - UNUSED(txStatus); - UNUSED(txStatusType); - DPRINT("\nBasicSetDone\n"); +SendBasicSetDone(void) { ZAF_EventHelperEventEnqueue(EVENT_APP_NEXT_EVENT_JOB); KeyFob_basic_off_Led_handler(false); - KeyFob_basic_on_Led_handler(false); + KeyFob_basic_on_Led_handler(false); } - -/* build a supervision get command - * - * @param[out] getFrame Buffer to store the built supervision get command - * @param[out] getLen The lenght of the built supervision get command - * @param[in] cmdFrame The command to be encapsulated into the supervision get command - * @param[in] cmdLen The lenght of the command to be encapsulated into the supervision get command - */ -static void BuildSupervisionGet(uint8_t *getFrame, - uint16_t *getLen, - uint8_t *cmdFrame, - uint8_t cmdLen) -{ - static uint8_t sv_session_id = 0; - *getLen = 0; - getFrame[(*getLen)++] = COMMAND_CLASS_SUPERVISION; - getFrame[(*getLen)++] = SUPERVISION_GET; - getFrame[(*getLen)++] = sv_session_id++ & SUPERVISION_GET_PROPERTIES1_SESSION_ID_MASK; - getFrame[(*getLen)++] = cmdLen; - for (int8_t i = 0; i < cmdLen; i++) { - getFrame[(*getLen)++] = cmdFrame[i]; +static void SupervisionReport (void *pSubscriberContext, void* pRxPackage) { + (void)pSubscriberContext; + SZwaveReceivePackage* myPackage = (SZwaveReceivePackage *)pRxPackage; + ZW_SUPERVISION_REPORT_FRAME* pReport = (ZW_SUPERVISION_REPORT_FRAME *)&myPackage->uReceiveParams.Rx.Payload.padding; + if ((SUPERVISION_REPORT == pReport->cmd) && + ((pReport->properties1 & SUPERVISION_GET_PROPERTIES1_SESSION_ID_MASK) + == ((sv_session_id - 1) & SUPERVISION_GET_PROPERTIES1_SESSION_ID_MASK))) + { + if (!--nodesInGroup) + { + SendBasicSetDone(); + } } } static uint8_t SendBasicSetToGroup(uint8_t value, void (*pCallback)(uint8_t, const TX_STATUS_TYPE*)) { - - uint8_t nodesInGroup = node_storage_group_member_count(); + nodesInGroup = node_storage_group_member_count(); if (0 < nodesInGroup) { DPRINTF("\nBasicToGroup (%u nodes) value %u\n", nodesInGroup, value); - + zpal_pm_stay_awake(m_RadioPowerLock, 0); + TimerStart(&JobTimer, PM_STAY_AWAKE_DURATION_3_SEC); /** * @attention * We will be sending a multicast to a list of nodes on our local group @@ -958,26 +1133,12 @@ static uint8_t SendBasicSetToGroup(uint8_t value, void (*pCallback)(uint8_t, co * * This group is persistently stored on NVM. */ - - SZwaveTransmitPackage TransmitPackage; - memset(&TransmitPackage, 0, sizeof(TransmitPackage)); - TransmitPackage.eTransmitType = EZWAVETRANSMITTYPE_SECURE; - SSecureSendData *params = &TransmitPackage.uTransmitParams.SendDataParams; - - /* Set the destination node mask bits */ - node_storage_group_member_nodemask_get((uint8_t*)params->connection.remote.address.nodeList.nodeMask, - sizeof(params->connection.remote.address.nodeList.nodeMask)); - - params->connection.remote.is_multicast = true; - params->tx_options.number_of_responses = 0; // 0 for SET command. - params->ptxCompleteCallback = pCallback; uint8_t basic_set_cmd[] = {COMMAND_CLASS_BASIC, BASIC_SET, value}; + uint8_t supervision_get[4 + sizeof(basic_set_cmd)]; + uint16_t frame_length; // encapsulates basic set command into supervision get command - BuildSupervisionGet(params->data, ¶ms->data_length, basic_set_cmd, sizeof(basic_set_cmd)); - - // Put the package on queue (and don't wait for it) - EQueueNotifyingStatus QueueStatus = QueueNotifyingSendToBack(g_pAppHandles->pZwTxQueue, (uint8_t*)&TransmitPackage, 0); - if (EQUEUENOTIFYING_STATUS_SUCCESS == QueueStatus) + BuildSupervisionGet(supervision_get, &frame_length, basic_set_cmd, sizeof(basic_set_cmd)); + if (SendSecureFrame(0, 0, 1, true, supervision_get, frame_length, pCallback)) { if (0 == value) { @@ -994,72 +1155,36 @@ static uint8_t SendBasicSetToGroup(uint8_t value, void (*pCallback)(uint8_t, co else { DPRINTF("Group Empty - Basic Set %s\n", value ? "ON" : "OFF"); - SendBasicSetToGroupCallback(0, NULL); + SendBasicSetDone(); return true; } } -uint8_t IsPrimaryController(void) -{ - const SApplicationHandles *m_pAppHandles = ZAF_getAppHandle(); - SZwaveCommandPackage cmdPackage = { - .eCommandType = EZWAVECOMMANDTYPE_IS_PRIMARY_CTRL}; - EQueueNotifyingStatus QueueStatus = QueueNotifyingSendToBack(m_pAppHandles->pZwCommandQueue, (uint8_t *)&cmdPackage, 500); - ASSERT(EQUEUENOTIFYING_STATUS_SUCCESS == QueueStatus); - SZwaveCommandStatusPackage cmdStatus; - if (GetCommandResponse(&cmdStatus, EZWAVECOMMANDSTATUS_IS_PRIMARY_CTRL)) - { - return cmdStatus.Content.IsPrimaryCtrlStatus.result; - } - ASSERT(false); - return 0; -} - /** - * Sends Device Reset Locally Notification - * @details Should only send notification if: - * 1. Not a primary controller - * 2. Has lifeline associations. + * @brief Transmission callback for Device Reset Locally call. + * @param pTransmissionResult Result of each transmission. */ void -SendDeviceResetLocally(void) +CC_DeviceResetLocally_done(TRANSMISSION_RESULT * pTransmissionResult) { - if (IsPrimaryController()) + if (TRANSMISSION_RESULT_FINISHED == pTransmissionResult->isFinished) { - DPRINTF("Primary controller. Skip Device Reset Locally Notification.\n"); - SetProtocolDefault(TRANSMIT_COMPLETE_OK, NULL); - return; - } - - uint8_t frame[] = {COMMAND_CLASS_DEVICE_RESET_LOCALLY, DEVICE_RESET_LOCALLY_NOTIFICATION}; - SZwaveTransmitPackage TransmitPackage; - memset(&TransmitPackage, 0, sizeof(TransmitPackage)); - TransmitPackage.eTransmitType = EZWAVETRANSMITTYPE_SECURE; - SSecureSendData *params = &TransmitPackage.uTransmitParams.SendDataParams; - - if (0 == node_storage_group_member_nodemask_get( - (uint8_t*)params->connection.remote.address.nodeList.nodeMask, - sizeof(params->connection.remote.address.nodeList.nodeMask))) - { - DPRINTF("No associations. Skip Device Reset Locally Notification.\n"); - SetProtocolDefault(TRANSMIT_COMPLETE_OK, NULL); - return; - } + /* Reset protocol */ + // Set default command to protocol + SZwaveCommandPackage CommandPackage; + CommandPackage.eCommandType = EZWAVECOMMANDTYPE_SET_DEFAULT; - DPRINT("Send Device Reset Locally Notification\r\n"); - params->connection.remote.is_multicast = true; - memcpy(params->data, frame, sizeof(frame)); - params->data_length = sizeof(frame); - params->tx_options.number_of_responses = 0; - params->ptxCompleteCallback = &SetProtocolDefault; + DPRINT("\nDisabling watchdog during reset\n"); + zpal_enable_watchdog(false); - if(EQUEUENOTIFYING_STATUS_SUCCESS != QueueNotifyingSendToBack(g_pAppHandles->pZwTxQueue, (uint8_t*)&TransmitPackage, 0)) - { - DPRINT("Fail DEVICE_RESET_LOCALLY_NOTIFICATION\r\n"); - SetProtocolDefault(TRANSMIT_COMPLETE_FAIL, NULL); + EQueueNotifyingStatus Status = QueueNotifyingSendToBack(g_pAppHandles->pZwCommandQueue, + (uint8_t*)&CommandPackage, + 500); + ASSERT(EQUEUENOTIFYING_STATUS_SUCCESS == Status); } } + static uint8_t SetRFReceiveMode(uint8_t mode) { DPRINTF("SetRFReceiveMode(%u)\n", mode); @@ -1199,19 +1324,16 @@ static void AppState_StartUp(EVENT_APP event) */ doRemainingInitialization(); } + else if(EVENT_APP_FLUSHMEM_READY == event) + { + AppResetNvm(); + } else { ChangeState(STATE_APP_IDLE); } } -static void ResetToDefault(void) -{ - DPRINT("\n===Reset to Default===\n"); - SendDeviceResetLocally(); - AppResetNvm(); -} - static void AppState_Idle(EVENT_APP event) { /************************************* @@ -1225,7 +1347,7 @@ static void AppState_Idle(EVENT_APP event) { DPRINT("\n===Inclusion process started===\n"); - bool ret = portable_controller_start_inclusion(); // This sets state to NETWORK_MANAGEMENT_STATE_START_INCLUSION + bool ret = key_fob_start_inclusion(); // This sets state to NETWORK_MANAGEMENT_STATE_START_INCLUSION if (ret == false) { DPRINT("Error, queue is full\n"); @@ -1251,7 +1373,7 @@ static void AppState_Idle(EVENT_APP event) { DPRINT("\n===Exclusion process started===\n"); - bool ret = portable_controller_start_exclusion(); // This sets state to NETWORK_MANAGEMENT_STATE_START_EXCLUSION + bool ret = key_fob_start_exclusion(); // This sets state to NETWORK_MANAGEMENT_STATE_START_EXCLUSION if (ret == false) { DPRINT("Error, queue is full\n"); @@ -1270,9 +1392,10 @@ static void AppState_Idle(EVENT_APP event) } } - if (EVENT_APP_BUTTON_RESET == event) + if(EVENT_APP_FLUSHMEM_READY == event) { - ResetToDefault(); + AppResetNvm(); + LoadConfiguration(); } if (EVENT_APP_BUTTON_ASSOCIATION_GROUP_ADD == event) @@ -1327,19 +1450,26 @@ static void AppState_Idle(EVENT_APP event) if (EVENT_APP_BUTTON_NETWORK_LEARNMODE_NWI == event) { - DPRINT("\nSet LearnMode NWI\n"); - if (false == portable_controller_start_learnmode_include()) + if (SetRFReceiveMode(true)) { - DPRINT("Error, queue is full\n"); + DPRINT("\nSet LearnMode NWI\n"); + if (false == key_fob_start_learnmode_include()) + { + DPRINT("Error, queue is full\n"); + } + else + { + KeyFob_network_learnmode_led_handler(true); + ChangeState(STATE_APP_NETWORK_LEARNMODE); + zpal_pm_stay_awake(m_RadioPowerLock, PM_STAY_AWAKE_DURATION_TEN_MINUTES); + TimerStart(&JobTimer, 61 * 1000); + } } else { - KeyFob_network_learnmode_led_handler(true); - ChangeState(STATE_APP_NETWORK_LEARNMODE); - zpal_pm_stay_awake(m_RadioPowerLock, PM_STAY_AWAKE_DURATION_TEN_MINUTES); - TimerStart(&JobTimer, 61 * 1000); + DPRINT("Error, couldn't start radio\n"); } - } +} if (EVENT_APP_BUTTON_NETWORK_LEARNMODE_NWE == event) { @@ -1348,7 +1478,7 @@ static void AppState_Idle(EVENT_APP event) if (SetRFReceiveMode(true)) { DPRINT("\nSet LearnMode NWE\n"); - if (false == portable_controller_start_learnmode_exclude()) + if (false == key_fob_start_learnmode_exclude()) { DPRINT("Error, queue is full\n"); } @@ -1386,12 +1516,10 @@ static void AppState_IncludeExclude(EVENT_APP event) return; } - if (EVENT_APP_BUTTON_RESET == event) + if(EVENT_APP_FLUSHMEM_READY == event) { - // First stop any active exclusion - portable_controller_stop_exclusion(); - STOP_LEARNMODE(); - ResetToDefault(); + AppResetNvm(); + LoadConfiguration(); } } @@ -1403,12 +1531,10 @@ static void AppState_NetworkLearnMode(EVENT_APP event) return; } - if (EVENT_APP_BUTTON_RESET == event) + if(EVENT_APP_FLUSHMEM_READY == event) { - KeyFob_network_learnmode_led_handler(false); - zwave_network_management_abort(); - STOP_LEARNMODE(); - ResetToDefault(); + AppResetNvm(); + LoadConfiguration(); } } @@ -1432,11 +1558,6 @@ static void AppState_Association(EVENT_APP event) } } - if (EVENT_APP_BUTTON_RESET == event) - { - ResetToDefault(); - } - if (EVENT_APP_BUTTON_UP_ASSOCIATION_GROUP_ADD == event) { DPRINT("\nAdd Device to Group - Activate Device Nodeinformation\n"); @@ -1499,14 +1620,15 @@ static void AppState_TransmitData(EVENT_APP event) } } - if (EVENT_APP_BUTTON_RESET == event) + if(EVENT_APP_FLUSHMEM_READY == event) { - ResetToDefault(); + AppResetNvm(); + LoadConfiguration(); } if (EVENT_APP_SEND_BASIC_ON_JOB == event) { - if (true != SendBasicSetToGroup(0xFF, &SendBasicSetToGroupCallback)) + if (true != SendBasicSetToGroup(0xFF, NULL)) { DPRINT("\n*SendBasicSetToGroup ON TX FAILED\n"); ZAF_EventHelperEventEnqueue(EVENT_APP_NEXT_EVENT_JOB); @@ -1516,7 +1638,7 @@ static void AppState_TransmitData(EVENT_APP event) if (EVENT_APP_SEND_BASIC_OFF_JOB == event) { - if (true != SendBasicSetToGroup(0x00, &SendBasicSetToGroupCallback)) + if (true != SendBasicSetToGroup(0x00, NULL)) { DPRINT("\n*SendBasicSetToGroup OFF TX FAILED\n"); ZAF_EventHelperEventEnqueue(EVENT_APP_NEXT_EVENT_JOB); @@ -1542,6 +1664,20 @@ static void AppStateManager(EVENT_APP event) */ notAppStateDependentActivity(event); + if (EVENT_APP_BUTTON_RESET == event) + { + if (IsPrimaryController()) + { + DPRINTF("Primary controller. Skip Device Reset Locally Notification.\n"); + SetProtocolDefault(TRANSMIT_COMPLETE_OK, NULL); + } else { + /* Send reset notification*/ + CC_DeviceResetLocally_notification_tx(); + } + /*Force state change to activate system-reset without taking care of current state.*/ + ChangeState(STATE_APP_RESET); + } + switch(currentState) { case STATE_APP_STARTUP: @@ -1568,6 +1704,15 @@ static void AppStateManager(EVENT_APP event) AppState_NetworkLearnMode(event); break; + case STATE_APP_RESET: + if(EVENT_APP_FLUSHMEM_READY == event) + { + AppResetNvm(); + /* Soft reset */ + zpal_reboot(); + } + break; + default: // Do nothing. DPRINT("\nAppStateHandler(): Case is not handled\n"); @@ -1592,7 +1737,7 @@ static void handle_network_management_states(node_id_t current_node_id) { DPRINTF("incl, node %d not in group\n", current_node_id); } - portable_controller_stop_inclusion(); + key_fob_stop_inclusion(); STOP_LEARNMODE(); break; @@ -1603,15 +1748,15 @@ static void handle_network_management_states(node_id_t current_node_id) DPRINTF("excl, remove node %d from group\n", current_node_id); node_storage_remove_group_member_nodeid(current_node_id); } - portable_controller_stop_exclusion(); + key_fob_stop_exclusion(); STOP_LEARNMODE(); break; case NETWORK_MANAGEMENT_STATE_LEARNMODE: DPRINTF("-->NETWORK_MANAGEMENT_STATE_LEARNMODE %u\n", current_node_id); - KeyFob_network_learnmode_led_handler(false); zwave_network_management_abort(); - ChangeState(STATE_APP_IDLE); + set_new_network_management_state(NETWORK_MANAGEMENT_STATE_SECURITY_PROBE); + TimerStart(&JobTimer, 2 * 1000); zpal_pm_stay_awake(m_RadioPowerLock, 1000 * 10); break; @@ -1639,178 +1784,12 @@ CC_Battery_BatteryGet_handler(uint8_t endpoint) return KeyFob_hw_get_battery_level(); } -/*************************************************************************** - * The below material should be moved into a separate file. - **************************************************************************/ - -#include -#include "Min2Max2.h" - -#define FILE_ID_APPLICATIONSETTINGS 102 -#define FILE_ID_APPLICATIONCMDINFO 103 - -#define FILE_SIZE_APPLICATIONSETTINGS (sizeof(SApplicationSettings)) -#define FILE_SIZE_APPLICATIONCMDINFO (sizeof(SApplicationCmdClassInfo)) - -typedef struct SApplicationSettings -{ - uint8_t listening; - uint8_t generic; - uint8_t specific; -} SApplicationSettings; - -typedef struct SApplicationCmdClassInfo -{ - uint8_t UnSecureIncludedCCLen; - uint8_t UnSecureIncludedCC[APPL_NODEPARM_MAX]; - uint8_t SecureIncludedUnSecureCCLen; - uint8_t SecureIncludedUnSecureCC[APPL_NODEPARM_MAX]; - uint8_t SecureIncludedSecureCCLen; - uint8_t SecureIncludedSecureCC[APPL_NODEPARM_MAX]; - -} SApplicationCmdClassInfo; - -static uint8_t -SaveApplicationSettings(uint8_t bListening, - uint8_t bGeneric, - uint8_t bSpecific - ) -{ - SApplicationSettings tApplicationSettings; - uint8_t dataIsWritten = false; - zpal_status_t tReturnVal; - tReturnVal = zpal_nvm_read(pFileSystemApplication, FILE_ID_APPLICATIONSETTINGS, &tApplicationSettings, FILE_SIZE_APPLICATIONSETTINGS); - if (ZPAL_STATUS_OK == tReturnVal) - { - tApplicationSettings.listening = bListening; - tApplicationSettings.generic = bGeneric; - tApplicationSettings.specific = bSpecific; - tReturnVal = zpal_nvm_write(pFileSystemApplication, FILE_ID_APPLICATIONSETTINGS, &tApplicationSettings, FILE_SIZE_APPLICATIONSETTINGS); - if (ZPAL_STATUS_OK == tReturnVal) - { - dataIsWritten = true; - } - } - return dataIsWritten; -} - - -uint8_t -SaveApplicationCCInfo (uint8_t bUnSecureIncludedCCLen, - const uint8_t* pUnSecureIncludedCC, - uint8_t bSecureIncludedUnSecureCCLen, - uint8_t* pSecureIncludedUnSecureCC, - uint8_t bSecureIncludedSecureCCLen, - uint8_t* pSecureIncludedSecureCC) -{ - SApplicationCmdClassInfo tApplicationCmdClassInfo; - uint8_t dataIsWritten = false; - zpal_status_t tReturnVal; - - tReturnVal = zpal_nvm_read(pFileSystemApplication, FILE_ID_APPLICATIONCMDINFO, &tApplicationCmdClassInfo, FILE_SIZE_APPLICATIONCMDINFO); - if (ZPAL_STATUS_OK == tReturnVal) - { - - tApplicationCmdClassInfo.UnSecureIncludedCCLen = bUnSecureIncludedCCLen; - tApplicationCmdClassInfo.SecureIncludedUnSecureCCLen = bSecureIncludedUnSecureCCLen; - tApplicationCmdClassInfo.SecureIncludedSecureCCLen = bSecureIncludedSecureCCLen; - - for (uint8_t i = 0; i < APPL_NODEPARM_MAX; i++) - { - if (i < bUnSecureIncludedCCLen) - { - tApplicationCmdClassInfo.UnSecureIncludedCC[i] = pUnSecureIncludedCC[i]; - } - else - { - tApplicationCmdClassInfo.UnSecureIncludedCC[i] = 0; - } - - if (i < bSecureIncludedUnSecureCCLen) - { - tApplicationCmdClassInfo.SecureIncludedUnSecureCC[i] = pSecureIncludedUnSecureCC[i]; - } - else - { - tApplicationCmdClassInfo.SecureIncludedUnSecureCC[i] = 0; - } - - if (i < bSecureIncludedSecureCCLen) - { - tApplicationCmdClassInfo.SecureIncludedSecureCC[i] = pSecureIncludedSecureCC[i]; - } - else - { - tApplicationCmdClassInfo.SecureIncludedSecureCC[i] = 0; - } - - } - tReturnVal = zpal_nvm_write(pFileSystemApplication, FILE_ID_APPLICATIONCMDINFO, &tApplicationCmdClassInfo, FILE_SIZE_APPLICATIONCMDINFO); - if (ZPAL_STATUS_OK == tReturnVal) - { - dataIsWritten = true; - } - } - return dataIsWritten; - -} - -uint32_t portable_setApplicationNodeInformation(uint8_t listening, - NODE_TYPE node_type, - const uint8_t *nodeParm, - uint8_t parmLength) +uint32_t portable_setApplicationNodeInformation() { - /* listening | generic | specific | parmLength | nodeParms[] */ - - AppNodeInfo.DeviceOptionsMask = listening; - AppNodeInfo.NodeType.generic = node_type.generic; - AppNodeInfo.NodeType.specific = node_type.specific; - - // As this serial API command only supports one set of command classes, - // we use the same list for the entire CC set - - // Data for loopifying CC list writes - SCommandClassList_t *const apCCLists[3] = - { - &AppNodeInfo.CommandClasses.UnSecureIncludedCC, - &AppNodeInfo.CommandClasses.SecureIncludedUnSecureCC, - &AppNodeInfo.CommandClasses.SecureIncludedSecureCC - }; - - const uint8_t aCCListSizes[3] = - { - sizeof(cmdClassListNonSecureNotIncluded), - sizeof(cmdClassListNonSecureIncludedSecure), - sizeof(cmdClassListSecure) - }; - - uint32_t iListLength = parmLength; - for (uint32_t i = 0; i < 3; i++) - { - // NOTE: These are not really supposed to be edited run time. - // So set list lengths to 0 at first to reduce chaos if protocol - // accesses them while we edit them. - apCCLists[i]->iListLength = 0; - - memset((uint8_t *)(apCCLists[i]->pCommandClasses), 0, aCCListSizes[i]); // Clear CCList - memcpy((uint8_t *)(apCCLists[i]->pCommandClasses), nodeParm, Minimum2(iListLength, aCCListSizes[i])); - - // Set new list length after finishing CCList - apCCLists[i]->iListLength = (uint8_t)Minimum2(iListLength, aCCListSizes[i]); - } - - AppNodeInfo.DeviceOptionsMask = listening; - AppNodeInfo.NodeType.generic = node_type.generic; - AppNodeInfo.NodeType.specific = node_type.specific; - - bool bStatus = SaveApplicationSettings(listening, node_type.generic, - node_type.specific); - bStatus &= SaveApplicationCCInfo(apCCLists[0]->iListLength, (const uint8_t*)apCCLists[0]->pCommandClasses, // See comment at the beginning of the case. - 0, NULL, 0, NULL); #if defined(ZW_CONTROLLER) - ZW_UpdateCtrlNodeInformation_API_IF(true); + ZW_UpdateCtrlNodeInformation_API_IF(); #endif - return bStatus; + return true; } /*********************************************************************** @@ -1831,7 +1810,7 @@ typedef struct SApplicationConfiguration uint8_t -SaveApplicationTxPowerlevel(int8_t ipower, int8_t power0dbmMeasured) +SaveApplicationTxPowerlevel(zpal_tx_power_t ipower, zpal_tx_power_t power0dbmMeasured) { SApplicationConfiguration tApplicationConfiguration; uint8_t dataIsWritten = false; @@ -1854,16 +1833,8 @@ SaveApplicationTxPowerlevel(int8_t ipower, int8_t power0dbmMeasured) static bool ObjectExist(zpal_nvm_object_key_t key) { - zpal_status_t tReturnVal; - size_t tDataLen; - - - tReturnVal = zpal_nvm_get_object_size(pFileSystemApplication, key, &tDataLen); - if (ZPAL_STATUS_OK != tReturnVal) - { - return false; - } - return true; + size_t tDataLen; + return ZPAL_STATUS_OK == zpal_nvm_get_object_size(pFileSystemApplication, key, &tDataLen); } uint8_t diff --git a/protocol/z-wave/NonCertifiableApps/KeyFob/network_management.c b/protocol/z-wave/NonCertifiableApps/KeyFob/network_management.c index 70f6fc5426..6b944b25fd 100644 --- a/protocol/z-wave/NonCertifiableApps/KeyFob/network_management.c +++ b/protocol/z-wave/NonCertifiableApps/KeyFob/network_management.c @@ -61,7 +61,7 @@ static sl_network_management_states_t network_management_state = NETWORK_MANAGEM // ----------------------------------------------------------------------------- // Public Function Definitions // ----------------------------------------------------------------------------- -bool portable_controller_start_inclusion() +bool key_fob_start_inclusion() { const SApplicationHandles* pAppHandle = ZAF_getAppHandle(); EQueueNotifyingStatus status; @@ -78,7 +78,7 @@ bool portable_controller_start_inclusion() return false; } -bool portable_controller_stop_inclusion() +bool key_fob_stop_inclusion() { const SApplicationHandles* pAppHandle = ZAF_getAppHandle(); EQueueNotifyingStatus status; @@ -95,7 +95,7 @@ bool portable_controller_stop_inclusion() return false; } -bool portable_controller_start_exclusion() +bool key_fob_start_exclusion() { const SApplicationHandles* pAppHandle = ZAF_getAppHandle(); EQueueNotifyingStatus status; @@ -112,7 +112,7 @@ bool portable_controller_start_exclusion() return false; } -bool portable_controller_stop_exclusion() +bool key_fob_stop_exclusion() { const SApplicationHandles* pAppHandle = ZAF_getAppHandle(); EQueueNotifyingStatus status; @@ -129,7 +129,7 @@ bool portable_controller_stop_exclusion() return false; } -bool portable_controller_start_learnmode_include() +bool key_fob_start_learnmode_include() { const SApplicationHandles* pAppHandle = ZAF_getAppHandle(); EQueueNotifyingStatus status; @@ -146,7 +146,7 @@ bool portable_controller_start_learnmode_include() return false; } -bool portable_controller_start_learnmode_exclude() +bool key_fob_start_learnmode_exclude() { const SApplicationHandles* pAppHandle = ZAF_getAppHandle(); EQueueNotifyingStatus status; diff --git a/protocol/z-wave/NonCertifiableApps/KeyFob/network_management.h b/protocol/z-wave/NonCertifiableApps/KeyFob/network_management.h index f56252fcd4..a419289d52 100644 --- a/protocol/z-wave/NonCertifiableApps/KeyFob/network_management.h +++ b/protocol/z-wave/NonCertifiableApps/KeyFob/network_management.h @@ -31,7 +31,10 @@ typedef enum NETWORK_MANAGEMENT_STATE_START_EXCLUSION, NETWORK_MANAGEMENT_STATE_ADD_GROUP, NETWORK_MANAGEMENT_STATE_REMOVE_GROUP, - NETWORK_MANAGEMENT_STATE_LEARNMODE + NETWORK_MANAGEMENT_STATE_LEARNMODE, + NETWORK_MANAGEMENT_STATE_SECURITY_PROBE, + NETWORK_MANAGEMENT_STATE_S2_PROBE, + NETWORK_MANAGEMENT_STATE_S0_PROBE } sl_network_management_states_t; // ----------------------------------------------------------------------------- // Global Variables @@ -41,17 +44,17 @@ typedef enum // Public Function Declarations // ----------------------------------------------------------------------------- -bool portable_controller_start_inclusion(); +bool key_fob_start_inclusion(); -bool portable_controller_start_exclusion(); +bool key_fob_start_exclusion(); -bool portable_controller_stop_exclusion(); +bool key_fob_stop_exclusion(); -bool portable_controller_stop_inclusion(); +bool key_fob_stop_inclusion(); -bool portable_controller_start_network_learnmode(); +bool key_fob_start_network_learnmode(); -bool portable_controller_stop_network_learnmode(); +bool key_fob_stop_network_learnmode(); bool set_new_network_management_state( sl_network_management_states_t new_state); diff --git a/protocol/z-wave/NonCertifiableApps/MultilevelSensor/MultilevelSensor.c b/protocol/z-wave/NonCertifiableApps/MultilevelSensor/MultilevelSensor.c index 1b9effdf5a..a74309672e 100644 --- a/protocol/z-wave/NonCertifiableApps/MultilevelSensor/MultilevelSensor.c +++ b/protocol/z-wave/NonCertifiableApps/MultilevelSensor/MultilevelSensor.c @@ -14,6 +14,7 @@ #include "SizeOf.h" #include "Assert.h" +#include #include "DebugPrintConfig.h" //#define DEBUGPRINT @@ -196,7 +197,7 @@ static const SAppNodeInfo_t AppNodeInfo = .CommandClasses.SecureIncludedSecureCC.pCommandClasses = cmdClassListSecure }; -static const SRadioConfig_t RadioConfig = +static SRadioConfig_t RadioConfig = { .iListenBeforeTalkThreshold = ELISTENBEFORETALKTRESHOLD_DEFAULT, .iTxPowerLevelMax = APP_MAX_TX_POWER, @@ -659,6 +660,15 @@ ApplicationInit(EResetReason_t eResetReason) // Init file system ApplicationFileSystemInit(&pFileSystemApplication); + // Read Rf region from MFG_ZWAVE_COUNTRY_FREQ + zpal_radio_region_t regionMfg; + ZW_GetMfgTokenDataCountryFreq((void*) ®ionMfg); + if (isRfRegionValid(regionMfg)) { + RadioConfig.eRegion = regionMfg; + } else { + ZW_SetMfgTokenDataCountryRegion((void*) &RadioConfig.eRegion); + } + /* Register task function */ /************************************************************************************* * CREATE USER TASKS - ZW_ApplicationRegisterTask() and ZW_UserTask_CreateTask() @@ -985,7 +995,7 @@ AppStateManager(EVENT_APP event) ZAF_JobHelperJobEnqueue(EVENT_APP_START_TIMER_EVENTJOB_STOP); } - if (EVENT_APP_BUTTON_BATTERY_REPORT == event) + if (EVENT_APP_BUTTON_BATTERY_AND_SENSOR_REPORT == event) { /* BATTERY REPORT EVENT received. Send a battery level report */ DPRINT("\r\nBattery Level report transmit (keypress trig)\r\n"); @@ -997,8 +1007,23 @@ AppStateManager(EVENT_APP event) } /*Add event's on job-queue*/ - ZAF_JobHelperJobEnqueue(EVENT_APP_SEND_BATTERY_LEVEL_REPORT); + ZAF_JobHelperJobEnqueue(EVENT_APP_SEND_BATTERY_LEVEL_AND_SENSOR_REPORT); } + + if (EVENT_APP_BUTTON_BASIC_SET_REPORT == event) + { + /* BASIC SET EVENT received */ + DPRINT("\r\nBasic set transmit (keypress trig)\r\n"); + ChangeState(STATE_APP_TRANSMIT_DATA); + + if (false == ZAF_EventHelperEventEnqueue(EVENT_APP_NEXT_EVENT_JOB)) + { + DPRINT("\r\n** EVENT_APP_NEXT_EVENT_JOB fail\r\n"); + } + + /*Add event's on job-queue*/ + ZAF_JobHelperJobEnqueue(EVENT_APP_SEND_BASIC_SET_REPORT); + } break; case STATE_APP_LEARN_MODE: @@ -1126,9 +1151,19 @@ AppStateManager(EVENT_APP event) AppTimerDeepSleepPersistentStart(&EventJobsTimer, BASIC_SET_TIMEOUT); } - if (EVENT_APP_SEND_BATTERY_LEVEL_REPORT == event) + if (EVENT_APP_SEND_BATTERY_LEVEL_AND_SENSOR_REPORT == event) { ReportBatteryLevel(); + cc_multilevel_sensor_send_sensor_data(); + } + + if (EVENT_APP_SEND_BASIC_SET_REPORT == event) + { + if (JOB_STATUS_SUCCESS != CC_Basic_Set_tx( &agiTableRootDeviceGroups[0].profile, ENDPOINT_ROOT, BASIC_SET_TRIGGER_VALUE, ZCB_JobStatus)) + { + /*Kick next job*/ + ZAF_EventHelperEventEnqueue(EVENT_APP_NEXT_EVENT_JOB); + } } if (EVENT_APP_FINISH_EVENT_JOB == event) diff --git a/protocol/z-wave/NonCertifiableApps/MultilevelSensor/MultilevelSensor.slcp b/protocol/z-wave/NonCertifiableApps/MultilevelSensor/MultilevelSensor.slcp index a43970bb6b..0db3dd57b6 100644 --- a/protocol/z-wave/NonCertifiableApps/MultilevelSensor/MultilevelSensor.slcp +++ b/protocol/z-wave/NonCertifiableApps/MultilevelSensor/MultilevelSensor.slcp @@ -28,7 +28,6 @@ component: - id: zw_cc_powerlevel - id: zw_cc_zwaveplusinfo - id: zw_cc_battery - - id: zw_cc_notification - id: zw_cc_wakeup - id: zw_cc_configuration - id: zw_cc_multilevelsensor diff --git a/protocol/z-wave/NonCertifiableApps/MultilevelSensor/config_app.h b/protocol/z-wave/NonCertifiableApps/MultilevelSensor/config_app.h index 56c62ac3d6..17de5e3963 100644 --- a/protocol/z-wave/NonCertifiableApps/MultilevelSensor/config_app.h +++ b/protocol/z-wave/NonCertifiableApps/MultilevelSensor/config_app.h @@ -91,11 +91,6 @@ {{ASSOCIATION_GROUP_INFO_REPORT_PROFILE_NOTIFICATION, NOTIFICATION_REPORT_HOME_SECURITY_V4}, 1, {{COMMAND_CLASS_BASIC, BASIC_SET}}, "Basic set"} //@ [AGI_TABLE_ID] -/** - * Max notifications types - */ -#define MAX_NOTIFICATIONS 2 - /** * Heat event notification handler period in ms */ diff --git a/protocol/z-wave/NonCertifiableApps/MultilevelSensor/events.h b/protocol/z-wave/NonCertifiableApps/MultilevelSensor/events.h index c4a8c45a0c..5f06ace785 100644 --- a/protocol/z-wave/NonCertifiableApps/MultilevelSensor/events.h +++ b/protocol/z-wave/NonCertifiableApps/MultilevelSensor/events.h @@ -27,7 +27,8 @@ typedef enum EVENT_APP_MULTILEVELSENSOR EVENT_APP_FLUSHMEM_READY, EVENT_APP_NEXT_EVENT_JOB, EVENT_APP_FINISH_EVENT_JOB, - EVENT_APP_SEND_BATTERY_LEVEL_REPORT, + EVENT_APP_SEND_BATTERY_LEVEL_AND_SENSOR_REPORT, + EVENT_APP_SEND_BASIC_SET_REPORT, EVENT_APP_BASIC_STOP_JOB, EVENT_APP_BASIC_START_JOB, EVENT_APP_NOTIFICATION_START_JOB, @@ -36,7 +37,8 @@ typedef enum EVENT_APP_MULTILEVELSENSOR EVENT_APP_SMARTSTART_IN_PROGRESS, EVENT_APP_BUTTON_LEARN_RESET_SHORT_PRESS, EVENT_APP_BUTTON_LEARN_RESET_LONG_PRESS, - EVENT_APP_BUTTON_BATTERY_REPORT, + EVENT_APP_BUTTON_BATTERY_AND_SENSOR_REPORT, + EVENT_APP_BUTTON_BASIC_SET_REPORT, EVENT_APP_TRANSITION_TO_ACTIVE, EVENT_APP_TRANSITION_TO_DEACTIVE, /* diff --git a/protocol/z-wave/PAL/inc/ZW_classcmd.h b/protocol/z-wave/PAL/inc/ZW_classcmd.h index 4345eb9e75..5c6e048188 100644 --- a/protocol/z-wave/PAL/inc/ZW_classcmd.h +++ b/protocol/z-wave/PAL/inc/ZW_classcmd.h @@ -1,10 +1,11 @@ -// Generated on: 5/6/2022 2:34:49 PM +// This file is auto generated. Do not edit it manually! +// Generated on: 7/1/2022 10:08:05 AM /** * @file * @version 2.10.0 * Device and command class types and definitions. * - * @copyright 2018 Silicon Laboratories Inc. + * @copyright 2022 Silicon Laboratories Inc. */ #ifndef _ZW_CLASSCMD_H_ #define _ZW_CLASSCMD_H_ @@ -14081,6 +14082,9 @@ /* Max. frame size to allow routing over 4 hops */ #define META_DATA_MAX_DATA_SIZE 48 +/* Max frame that can be transmitted */ +#define TX_DATA_MAX_DATA_SIZE 170 + /************************************************************/ /* Structs and unions that can be used by the application */ /* to construct the frames to be sent */ @@ -52540,6 +52544,7 @@ ZW_FRAME_COLLECTION_MACRO4 ZW_FRAME_COLLECTION_MACRO5 ZW_FRAME_COLLECTION_MACRO6 ZW_FRAME_COLLECTION_MACRO7 + uint8_t bPadding[TX_DATA_MAX_DATA_SIZE]; } ZW_APPLICATION_TX_BUFFER; /************************************************************/ @@ -52561,7 +52566,7 @@ ZW_FRAME_COLLECTION_MACRO4 ZW_FRAME_COLLECTION_MACRO5 ZW_FRAME_COLLECTION_MACRO6 ZW_FRAME_COLLECTION_MACRO7 - uint8_t bPadding[META_DATA_MAX_DATA_SIZE]; + uint8_t bPadding[META_DATA_MAX_DATA_SIZE]; } ZW_APPLICATION_META_TX_BUFFER; diff --git a/protocol/z-wave/PAL/inc/zpal_radio.h b/protocol/z-wave/PAL/inc/zpal_radio.h index 7b3bb68c81..77d359b9a6 100644 --- a/protocol/z-wave/PAL/inc/zpal_radio.h +++ b/protocol/z-wave/PAL/inc/zpal_radio.h @@ -190,11 +190,21 @@ extern "C" { #define ZPAL_RADIO_INVALID_RSSI_DBM (-128) #define ZPAL_RADIO_RSSI_NOT_AVAILABLE (127) +//deci-dBm values +#define ZW_TX_POWER_10DBM 100 +#define ZW_TX_POWER_14DBM 140 +#define ZW_TX_POWER_20DBM 200 + /** * @brief Node ID type. */ typedef uint16_t node_id_t; +/** + * @brief Parameter type to store deci dBm values. + */ +typedef int16_t zpal_tx_power_t; + typedef enum { ZPAL_RADIO_MODE_NON_LISTENING, ///< The radio is not listening unless configured to for a period. @@ -431,9 +441,9 @@ typedef struct zpal_radio_wakeup_t wakeup; ///< Wakeup interval for the radio. uint8_t primary_lr_channel; ///< Primary Long Range Channel. int8_t listen_before_talk_threshold; ///< LBT Threshold for Transmit backoff in dBm. - int8_t tx_power_max; ///< Z-Wave Transmit Power in deci dBm. - int8_t tx_power_adjust; ///< Adjustment for antenna gain in deci dBm. - int16_t tx_power_max_lr; ///< Max transmit power for Z-Wave LR in deci dBm. + zpal_tx_power_t tx_power_max; ///< Z-Wave Transmit Power in deci dBm. + zpal_tx_power_t tx_power_adjust; ///< Adjustment for antenna gain in deci dBm. + zpal_tx_power_t tx_power_max_lr; ///< Max transmit power for Z-Wave LR in deci dBm. uint8_t *home_id; ///< Pointer to current HomeID(uint8_t homeID[4]). zpal_radio_callback_t rx_cb; ///< Pointer to function called by RF on Rx Completion. zpal_radio_callback_t tx_cb; ///< Pointer to function called by RF on Tx Completion. @@ -591,9 +601,9 @@ zpal_status_t zpal_radio_get_background_rssi(uint8_t channel, bool force_rx, int /** * @brief Function for getting the current reduce RF tx power compared to the default normal power in dBm. * - * @return The current reduced RF TX power in dBm. + * @return The current reduce RF TX power in dBm. */ -uint8_t zpal_radio_get_reduced_tx_power(void); +uint8_t zpal_radio_get_reduce_tx_power(void); /** * @brief Allows the radio to go into FLiRS receive mode. @@ -663,14 +673,14 @@ node_id_t zpal_radio_get_beam_node_id(void); * * @return Minimum TX power in dBm. */ -int8_t zpal_radio_get_minimum_lr_tx_power(void); +zpal_tx_power_t zpal_radio_get_minimum_lr_tx_power(void); /** * @brief Returns the maximum transmit power for Z-Wave Long Range. * * @return Maximum TX power in dBm. */ -int8_t zpal_radio_get_maximum_lr_tx_power(void); +zpal_tx_power_t zpal_radio_get_maximum_lr_tx_power(void); /** * @brief Returns whether debug is enabled or disabled. diff --git a/protocol/z-wave/PAL/inc/zpal_uart.h b/protocol/z-wave/PAL/inc/zpal_uart.h index a08e7169c3..6c2bdc5c41 100644 --- a/protocol/z-wave/PAL/inc/zpal_uart.h +++ b/protocol/z-wave/PAL/inc/zpal_uart.h @@ -100,6 +100,12 @@ typedef void (*zpal_uart_transmit_done_t)(zpal_uart_handle_t handle); */ typedef struct { zpal_uart_id_t id; ///pDestNode->nodeInfo.BitMultiChannelEncap) { @@ -330,6 +352,20 @@ Transport_SendRequestEP( return ZAF_ENQUEUE_STATUS_BUFFER_OVERRUN; } +#ifdef HOST_SECURITY_INCLUDED + UNUSED(pCallback); + SZwaveTransmitPackage TransmitPackage; + memset(&TransmitPackage, 0, sizeof(TransmitPackage)); + TransmitPackage.eTransmitType = EZWAVETRANSMITTYPE_SECURE; + SSecureSendData *params = &TransmitPackage.uTransmitParams.SendDataParams; + params->connection.remote.is_multicast = false; + params->data_length = dataLength; + memcpy(params->data, pData, params->data_length); + params->tx_options.number_of_responses = 0; + params->ptxCompleteCallback = (void *)ZCB_RequestCompleted; + params->connection.remote.address.node_id = pTxOptionsEx->pDestNode->node.nodeId; + result = (EZAF_EnqueueStatus_t)QueueNotifyingSendToBack(m_pTxQueueNotifying, (uint8_t *)&TransmitPackage, 0); +#else CmdClassMultiChannelEncapsulate(&pData, &dataLength, pTxOptionsEx); @@ -349,7 +385,8 @@ Transport_SendRequestEP( FramePackage.eTransmitType = EZWAVETRANSMITTYPE_EX; // Put the package on queue (and don't wait for it) - result = (EZAF_EnqueueStatus_t)QueueNotifyingSendToBack(m_pTxQueueNotifying, (uint8_t*)&FramePackage, 0); + result = (EZAF_EnqueueStatus_t)QueueNotifyingSendToBack(m_pTxQueueNotifying, (uint8_t*)&FramePackage, QUEUE_NOTIFYING_SEND_MAX_WAIT); +#endif if (ZAF_ENQUEUE_STATUS_SUCCESS == result) { // Success. Advance the callback function queue counters @@ -373,7 +410,7 @@ Transport_SendResponseEP( UNUSED(pCallback); SZwaveTransmitPackage TransmitPackage; memset(&TransmitPackage, 0, sizeof(TransmitPackage)); - TransmitPackage.eTransmitType = EZWAVETRANSMITTYPE_SECURE; + TransmitPackage.eTransmitType = pTxOptionsEx->pDestNode->nodeInfo.security == SECURITY_KEY_NONE ? EZWAVETRANSMITTYPE_NON_SECURE : EZWAVETRANSMITTYPE_SECURE; SSecureSendData *params = &TransmitPackage.uTransmitParams.SendDataParams; params->connection.remote.is_multicast = false; params->data_length = dataLength; @@ -426,7 +463,7 @@ Transport_SendResponseEP( FramePackage.eTransmitType = EZWAVETRANSMITTYPE_EX; // Put the package on queue (and dont wait for it) - result = (EZAF_EnqueueStatus_t)QueueNotifyingSendToBack(m_pTxQueueNotifying, (uint8_t*)&FramePackage, 0); + result = (EZAF_EnqueueStatus_t)QueueNotifyingSendToBack(m_pTxQueueNotifying, (uint8_t*)&FramePackage, QUEUE_NOTIFYING_SEND_MAX_WAIT); if (ZAF_ENQUEUE_STATUS_SUCCESS == result) { // Success. Advance the callback function queue counters diff --git a/protocol/z-wave/ZAF/ApplicationUtilities/_commonIF/ZAF_Common_interface.c b/protocol/z-wave/ZAF/ApplicationUtilities/_commonIF/ZAF_Common_interface.c index c453264f45..d00f0fa194 100644 --- a/protocol/z-wave/ZAF/ApplicationUtilities/_commonIF/ZAF_Common_interface.c +++ b/protocol/z-wave/ZAF/ApplicationUtilities/_commonIF/ZAF_Common_interface.c @@ -131,3 +131,15 @@ EInclusionMode_t ZAF_GetInclusionMode(void) ASSERT(false); // Crash in debug return EINCLUSIONMODE_NOT_SET; } + +bool isRfRegionValid(zpal_radio_region_t region) +{ + if (REGION_US_LR >= region || + REGION_US_LR_END_DEVICE == region || + REGION_JP == region || + REGION_KR == region) { + return true; + } else { + return false; + } +} diff --git a/protocol/z-wave/ZAF/ApplicationUtilities/_commonIF/ZAF_Common_interface.h b/protocol/z-wave/ZAF/ApplicationUtilities/_commonIF/ZAF_Common_interface.h index eaae6a1b96..0cc4e22d4c 100644 --- a/protocol/z-wave/ZAF/ApplicationUtilities/_commonIF/ZAF_Common_interface.h +++ b/protocol/z-wave/ZAF/ApplicationUtilities/_commonIF/ZAF_Common_interface.h @@ -152,4 +152,11 @@ node_id_t ZAF_GetNodeID(void); */ EInclusionMode_t ZAF_GetInclusionMode(void); +/** + * Checks if region is valid Z-Wave radio region + * @param region Region to check + * @return True if region is valid, false if it isn't. + */ +bool isRfRegionValid(zpal_radio_region_t region); + #endif /*_ZAF_COMMON_IF_H_ */ diff --git a/protocol/z-wave/ZAF/CommandClasses/MultilevelSensor/CC_MultilevelSensor_Support.c b/protocol/z-wave/ZAF/CommandClasses/MultilevelSensor/CC_MultilevelSensor_Support.c index ab43f09fc7..6c27c56824 100644 --- a/protocol/z-wave/ZAF/CommandClasses/MultilevelSensor/CC_MultilevelSensor_Support.c +++ b/protocol/z-wave/ZAF/CommandClasses/MultilevelSensor/CC_MultilevelSensor_Support.c @@ -120,22 +120,7 @@ static tse_data_t tse_data[MULTILEVEL_SENSOR_REGISTERED_SENSOR_NUMBER_LIMIT] = { static void cc_multilevel_sensor_autoreport_callback(SSwTimer *pTimer) { UNUSED(pTimer); - /** - * TSE simulated RX option for local change addressed to the Root Device - * All applications can use this variable when triggering the TSE after - * a local / non Z-Wave initiated change - */ - sensor_interface_iterator_t* sensor_interface_iterator; - cc_multilevel_sensor_init_iterator(&sensor_interface_iterator); - uint8_t i = 0; - while(sensor_interface_iterator) - { - - tse_data[i].sensor_interface = sensor_interface_iterator; - ZAF_TSE_Trigger(cc_multilevel_sensor_operation_report_stx, (void*)&tse_data[i], false); - cc_multilevel_sensor_next_iterator(&sensor_interface_iterator); - i++; - } + cc_multilevel_sensor_send_sensor_data(); AppTimerDeepSleepPersistentStart(&cc_multilevel_sensor_autoreport_timer, MULTILEVEL_SENSOR_DEFAULT_AUTOREPORT_PEDIOD_MS); } @@ -350,6 +335,25 @@ static uint8_t lifeline_reporting(ccc_pair_t * p_ccc_pair) return 1; } +void cc_multilevel_sensor_send_sensor_data() +{ + /** + * TSE simulated RX option for local change addressed to the Root Device + * All applications can use this variable when triggering the TSE after + * a local / non Z-Wave initiated change + */ + sensor_interface_iterator_t* sensor_interface_iterator; + cc_multilevel_sensor_init_iterator(&sensor_interface_iterator); + uint8_t i = 0; + while(sensor_interface_iterator) + { + tse_data[i].sensor_interface = sensor_interface_iterator; + ZAF_TSE_Trigger(cc_multilevel_sensor_operation_report_stx, (void*)&tse_data[i], false); + cc_multilevel_sensor_next_iterator(&sensor_interface_iterator); + i++; + } +} + REGISTER_CC_V3(COMMAND_CLASS_SENSOR_MULTILEVEL_V11, SENSOR_MULTILEVEL_VERSION_V11, CC_MultilevelSensor_handler, NULL, NULL, lifeline_reporting, 0); // ----------------------------------------------------------------------------- diff --git a/protocol/z-wave/ZAF/CommandClasses/MultilevelSensor/CC_MultilevelSensor_Support.h b/protocol/z-wave/ZAF/CommandClasses/MultilevelSensor/CC_MultilevelSensor_Support.h index c2628beb16..cae4a7d8bd 100644 --- a/protocol/z-wave/ZAF/CommandClasses/MultilevelSensor/CC_MultilevelSensor_Support.h +++ b/protocol/z-wave/ZAF/CommandClasses/MultilevelSensor/CC_MultilevelSensor_Support.h @@ -40,4 +40,10 @@ */ void cc_multilevel_sensor_init(void); +/** + * This function will report the registered sensor's measured datas + * to the Lifeline group. + */ +void cc_multilevel_sensor_send_sensor_data(); + #endif // CC_MULTILEVELSENSOR_SUPPORT_H diff --git a/protocol/z-wave/ZAF/CommandClasses/Notification/CC_Notification.c b/protocol/z-wave/ZAF/CommandClasses/Notification/CC_Notification.c index c9d2cba817..6e4d744f2b 100644 --- a/protocol/z-wave/ZAF/CommandClasses/Notification/CC_Notification.c +++ b/protocol/z-wave/ZAF/CommandClasses/Notification/CC_Notification.c @@ -141,7 +141,7 @@ CC_Notification_handler( a pending notification from its internal list (Pull mode). We also do it for Push mode.*/ notification_type_t notificationType = (notification_type_t)pTxBuf->ZW_NotificationReport1byteV4Frame.notificationType; - uint8_t grp = GetGroupNotificationType(¬ificationType,tempEndpoint); + uint8_t grp = GetGroupIndex(¬ificationType,tempEndpoint); pTxBuf->ZW_NotificationReport1byteV4Frame.notificationType = (uint8_t)notificationType; if(0xff == grp) diff --git a/protocol/z-wave/ZAF/CommandClasses/Notification/CC_Notification.h b/protocol/z-wave/ZAF/CommandClasses/Notification/CC_Notification.h index ec85087969..b3fdb8f7c4 100644 --- a/protocol/z-wave/ZAF/CommandClasses/Notification/CC_Notification.h +++ b/protocol/z-wave/ZAF/CommandClasses/Notification/CC_Notification.h @@ -292,13 +292,13 @@ JOB_STATUS CmdClassNotificationReport( VOID_CALLBACKFUNC(pCallback)(TRANSMISSION_RESULT * pTransmissionResult)); /** - * @brief GetGroupNotificationType + * @brief GetGroupIndex * Read last active notification type * @param[in,out] pNotificationType * @param[in] endpoint is the destination endpoint * @return Success: group number, else: 0xFF */ -extern uint8_t GetGroupNotificationType(notification_type_t * pNotificationType, uint8_t endpoint); +extern uint8_t GetGroupIndex(notification_type_t * pNotificationType, uint8_t endpoint); /** * Validates or finds a combination of notification type and endpoint. diff --git a/protocol/z-wave/ZAF/CommandClasses/Notification/notification.c b/protocol/z-wave/ZAF/CommandClasses/Notification/notification.c index 3de1d823ae..6ccd6e4d9e 100644 --- a/protocol/z-wave/ZAF/CommandClasses/Notification/notification.c +++ b/protocol/z-wave/ZAF/CommandClasses/Notification/notification.c @@ -40,7 +40,7 @@ typedef struct _NOTIFICATION_ typedef struct _MY_NOTIFICATION_ { uint8_t lastActionGrp; - NOTIFICATION grp[MAX_NOTIFICATIONS]; + NOTIFICATION grp[MAX_NUM_OF_NOTIFICATION_GROUPS]; } MY_NOTIFICATION; @@ -80,7 +80,7 @@ static void SaveNotificationStatus( status = zpal_nvm_read(pFileSystem, ZAF_FILE_ID_NOTIFICATIONDATA, &tSource, sizeof(SNotificationData)); ASSERT(ZPAL_STATUS_OK == status); - uint8_t tGroupNumber = GetGroupNotificationType(¬ificationType, endpoint); + uint8_t tGroupNumber = GetGroupIndex(¬ificationType, endpoint); if(0xFF != tGroupNumber) { @@ -94,6 +94,32 @@ static void SaveNotificationStatus( } } +//Saves notificationStatus to persistent memory +static void SaveNotificationStatusForType( + notification_type_t notificationType, + NOTIFICATION_STATUS notificationStatus) +{ + zpal_status_t status; + + ASSERT(pFileSystem != 0); + + for (uint8_t i = 0; i < MAX_NUM_OF_NOTIFICATION_GROUPS; i++) { + if(myNotification.grp[i].type == notificationType) + { + SNotificationData tSource; + status = zpal_nvm_read(pFileSystem, ZAF_FILE_ID_NOTIFICATIONDATA, &tSource, sizeof(SNotificationData)); + ASSERT(ZPAL_STATUS_OK == status); + + if(tSource.AlarmStatus[i] != (uint8_t)notificationStatus) + { + tSource.AlarmStatus[i] = (uint8_t)notificationStatus; + status = zpal_nvm_write(pFileSystem, ZAF_FILE_ID_NOTIFICATIONDATA, &tSource, sizeof(SNotificationData)); + ASSERT(ZPAL_STATUS_OK == status); + } + } + } +} + void InitNotification(zpal_nvm_handle_t pFS) { ASSERT(pFS != NULL); @@ -101,7 +127,7 @@ void InitNotification(zpal_nvm_handle_t pFS) uint8_t i = 0; notificationBurglerUnknownEvent = false; - for(i = 0; i< MAX_NOTIFICATIONS; i++) + for(i = 0; i< MAX_NUM_OF_NOTIFICATION_GROUPS; i++) { myNotification.grp[i].agiProfile.profile_MS = 0; myNotification.grp[i].agiProfile.profile_LS = 0; @@ -129,6 +155,33 @@ void InitNotification(zpal_nvm_handle_t pFS) } } +/** + * @brief In case of multidevice type (0xff) replace the endpoint to the endpoint of the last action group, if the lastActionGrp is not valid than return endpoint of group 0 + * @param notificationType Notification type. + * @param pEndpoint Endpoint number to be updated + * @return bool + */ +static bool UpdateEndpointForRoot( + notification_type_t notificationType, + uint8_t *pEndpoint) +{ + if (0xFF == notificationType) + { + if (0xFF != myNotification.lastActionGrp) + { + *pEndpoint = myNotification.grp[myNotification.lastActionGrp].ep; + } + else + { + *pEndpoint = myNotification.grp[0].ep; + } + + return true; + } + + return false; +} + void DefaultNotificationStatus(NOTIFICATION_STATUS status) { ASSERT(pFileSystem != 0); @@ -168,7 +221,7 @@ bool AddNotification( { uint8_t i; /*Find free slot*/ - for(i = 0; i< MAX_NOTIFICATIONS; i++) + for(i = 0; i< MAX_NUM_OF_NOTIFICATION_GROUPS; i++) { if( 0 == myNotification.grp[i].type) { @@ -199,11 +252,17 @@ bool AddNotification( return false; } -uint8_t GetGroupNotificationType(notification_type_t* pNotificationType, uint8_t endpoint) +/** + * @brief Search the index of group. + * @param notificationType Notification type. + * @param endpoint Endpoint number + * @return If the given endpoint is 0 (root) it return the firs groupnumber where the notification type is the same. Otherwise return the group number where the endpoint and type is matched. + */ +uint8_t GetGroupIndex(notification_type_t* pNotificationType, uint8_t endpoint) { uint8_t i = 0; - DPRINTF("\r\nGetGroupNotificationType %d", *pNotificationType); + DPRINTF("\r\nGetGroupIndex %d", *pNotificationType); if(0xFF == *pNotificationType) { @@ -226,7 +285,7 @@ uint8_t GetGroupNotificationType(notification_type_t* pNotificationType, uint8_t } else{ /*find notification out from end-point*/ - for(i = 0; i< MAX_NOTIFICATIONS; i++) + for(i = 0; i< MAX_NUM_OF_NOTIFICATION_GROUPS; i++) { if(myNotification.grp[i].ep == endpoint) { @@ -237,69 +296,49 @@ uint8_t GetGroupNotificationType(notification_type_t* pNotificationType, uint8_t } } - for(i = 0; i< MAX_NOTIFICATIONS; i++) + for(i = 0; i< MAX_NUM_OF_NOTIFICATION_GROUPS; i++) { DPRINTF("%d %d ", myNotification.grp[i].type, *myNotification.grp[i].pSupportedEvents); - if((myNotification.grp[i].type == *pNotificationType) && (myNotification.grp[i].ep == endpoint)) + + if( (myNotification.grp[i].type == *pNotificationType) && (ENDPOINT_ROOT == endpoint) ) { DPRINTF("ID %d", i); return i; } - } - return 0xff; -} - -/* - Find the endpoint that assigned to a certian notification type from myNotification structure -*/ -static bool ExtractEndpoint( - notification_type_t notificationType, - uint8_t *pEndpoint) { - if (0xFF == notificationType) - { - if (0xFF != myNotification.lastActionGrp) - { - *pEndpoint = myNotification.grp[myNotification.lastActionGrp].ep; - } else { - *pEndpoint = myNotification.grp[0].ep; - } - return true; - } - else - { - if ((0xFF != myNotification.lastActionGrp) && - (myNotification.grp[myNotification.lastActionGrp].type == notificationType)) { - *pEndpoint = myNotification.grp[myNotification.lastActionGrp].ep; - return true; - } - for (uint8_t i = 0; i < MAX_NOTIFICATIONS; i++) { - if ((myNotification.grp[i].type == notificationType) && - (0xff != myNotification.grp[i].ep)) { - *pEndpoint = myNotification.grp[i].ep; - return true; - } + if((myNotification.grp[i].type == *pNotificationType) && (myNotification.grp[i].ep == endpoint)) + { + DPRINTF("ID %d", i); + return i; + } + } } - return false; + return 0xff; } +/** + * @brief Validates the given notificationType - endpoint pairs, and updates the endpoint in a special case. + * @param notificationType Notification type. + * @param endpoint Endpoint number + * @return False if the given endpoint not suppert the given notification type, otherwise is true. + */ bool FindNotificationEndpoint( notification_type_t notificationType, uint8_t * pEndpoint) { DPRINTF("\r\nFindNotificationEndpoint %d EP %d\r\n", notificationType, *pEndpoint); - if (false == ValidateNotificationType(notificationType , *pEndpoint ) || (0 == *pEndpoint)) + bool valid = ValidateNotificationType(notificationType , *pEndpoint ); + if (valid) { - if((0 == *pEndpoint) && ExtractEndpoint(notificationType, pEndpoint)) { - return true; - } else { - return false; - } - } else { - return true; + return true; } + else if ( (false == valid) && (ENDPOINT_ROOT == *pEndpoint) && (UpdateEndpointForRoot(notificationType, pEndpoint)) ) + { + return true; + } + return false; } e_cmd_handler_return_code_t handleAppNotificationSet( @@ -307,6 +346,7 @@ e_cmd_handler_return_code_t handleAppNotificationSet( NOTIFICATION_STATUS_SET notificationStatus, uint8_t endpoint) { + UNUSED(endpoint); NOTIFICATION_STATUS newStatus = NOTIFICATION_STATUS_NO_PENDING_NOTIFICATION; if(NOTIFICATION_STATUS_SET_UNSOLICIT_DEACTIVATED == notificationStatus) @@ -317,13 +357,22 @@ e_cmd_handler_return_code_t handleAppNotificationSet( { newStatus = NOTIFICATION_STATUS_UNSOLICIT_ACTIVATED; } + + if (endpoint == 0) { + // Enable/disable notification status for all EndPoints in case of root node is addressed + + SaveNotificationStatusForType( + notificationType, + newStatus); + } else { + // Enable/disable notification status for the requested EndPoint only + SaveNotificationStatus( + notificationType, + newStatus, + endpoint + ); + } - //Saves notificationStatus to persistent memory - SaveNotificationStatus( - notificationType, - newStatus, - endpoint - ); return E_CMD_HANDLER_RETURN_CODE_HANDLED; } @@ -333,10 +382,10 @@ void handleCmdClassNotificationEventSupportedReport( uint8_t * pBitMaskArray, uint8_t endpoint) { - if( true == FindNotificationEndpoint(notificationType, &endpoint) ) + if( true == (ValidateNotificationType(notificationType, endpoint)) ) { notification_type_t temp_notificationType = notificationType; - uint8_t grpNo = GetGroupNotificationType(&temp_notificationType, endpoint ); + uint8_t grpNo = GetGroupIndex(&temp_notificationType, endpoint ); uint8_t i; if(temp_notificationType != notificationType) @@ -361,7 +410,8 @@ void handleCmdClassNotificationEventSupportedReport( /*calc number of bitmask bytes*/ *pNbrBitMask = (*pNbrBitMask / 8) + 1; } - else{ + else + { /*Only support Unkown event why bit maks is 0*/ *pNbrBitMask = 0; } @@ -372,7 +422,7 @@ NOTIFICATION_STATUS CmdClassNotificationGetNotificationStatus( uint8_t endpoint) { NOTIFICATION_STATUS status = NOTIFICATION_STATUS_UNSOLICIT_DEACTIVATED; - uint8_t grp = GetGroupNotificationType( ¬ificationType, endpoint ); + uint8_t grp = GetGroupIndex( ¬ificationType, endpoint ); if(0xff != grp) { @@ -403,7 +453,7 @@ bool CmdClassNotificationGetNotificationEvent( uint8_t endpoint) { uint8_t i = 0; - uint8_t grpNo = GetGroupNotificationType(pNotificationType, endpoint ); + uint8_t grpNo = GetGroupIndex(pNotificationType, endpoint ); *pEventPar = 0; *pEvNbrs = 0; if(0xff == grpNo) @@ -413,7 +463,7 @@ bool CmdClassNotificationGetNotificationEvent( DPRINTF("GetNotificationEvent %d %d ", *pNotificationType, *pNotificationEvent); /*check valid type*/ - if(true == ValidateNotificationType(*pNotificationType, endpoint )) + if( true == (ValidateNotificationType(*pNotificationType, endpoint)) ) { DPRINTF("%d", myNotification.grp[grpNo].event); @@ -493,7 +543,7 @@ void NotificationEventTrigger( uint8_t sourceEndpoint) { uint8_t i; - for(i = 0; i< MAX_NOTIFICATIONS; i++) + for(i = 0; i< MAX_NUM_OF_NOTIFICATION_GROUPS; i++) { if( myNotification.grp[i].agiProfile.profile_MS == pAgiProfile->profile_MS && myNotification.grp[i].agiProfile.profile_LS == pAgiProfile->profile_LS && @@ -509,7 +559,7 @@ void NotificationEventTrigger( myNotification.grp[i].pEvPar = pEvPar; myNotification.grp[i].evParLen = evParLen; myNotification.grp[i].trigged = 1; - i = MAX_NOTIFICATIONS; + i = MAX_NUM_OF_NOTIFICATION_GROUPS; } } } @@ -519,7 +569,7 @@ JOB_STATUS UnsolicitedNotificationAction( uint8_t sourceEndpoint, VOID_CALLBACKFUNC(pCallback)(TRANSMISSION_RESULT * pTransmissionResult)) { - if (myNotification.lastActionGrp >= MAX_NOTIFICATIONS) + if (myNotification.lastActionGrp >= MAX_NUM_OF_NOTIFICATION_GROUPS) { return JOB_STATUS_BUSY; } @@ -549,7 +599,7 @@ JOB_STATUS UnsolicitedNotificationAction( void ClearLastNotificationAction(AGI_PROFILE const * const pAgiProfile, uint8_t sourceEndpoint) { - if (myNotification.lastActionGrp < MAX_NOTIFICATIONS) + if (myNotification.lastActionGrp < MAX_NUM_OF_NOTIFICATION_GROUPS) { if( myNotification.grp[myNotification.lastActionGrp].agiProfile.profile_MS == pAgiProfile->profile_MS && myNotification.grp[myNotification.lastActionGrp].agiProfile.profile_LS == pAgiProfile->profile_LS && @@ -595,7 +645,7 @@ void handleCmdClassNotificationSupportedReport( uint8_t endpoint) { *pNbrBitMask = 0; - for(uint8_t i = 0; i< MAX_NOTIFICATIONS; i++) { + for(uint8_t i = 0; i< MAX_NUM_OF_NOTIFICATION_GROUPS; i++) { if((0 == endpoint) || /* find all notification types for device*/ (myNotification.grp[i].ep == endpoint) ) { /* find all notification types for endpoint*/ SetNotificationBit(i, pNbrBitMask, pBitMaskArray, bBitMaskLen); @@ -615,7 +665,7 @@ static bool ValidateNotificationType(notification_type_t notificationType, uint8 if( 0xFF == notificationType) { - for(i = 0; i< MAX_NOTIFICATIONS; i++) + for(i = 0; i< MAX_NUM_OF_NOTIFICATION_GROUPS; i++) { if(myNotification.grp[i].ep == endpoint) { @@ -625,9 +675,9 @@ static bool ValidateNotificationType(notification_type_t notificationType, uint8 return false; } - for(i = 0; i< MAX_NOTIFICATIONS; i++) + for(i = 0; i< MAX_NUM_OF_NOTIFICATION_GROUPS; i++) { - if(myNotification.grp[i].type == notificationType && myNotification.grp[i].ep == endpoint) + if(myNotification.grp[i].type == notificationType) { return true; } diff --git a/protocol/z-wave/ZAF/CommandClasses/Notification/notification.h b/protocol/z-wave/ZAF/CommandClasses/Notification/notification.h index 5b2941cb84..4c416cb0d3 100644 --- a/protocol/z-wave/ZAF/CommandClasses/Notification/notification.h +++ b/protocol/z-wave/ZAF/CommandClasses/Notification/notification.h @@ -42,7 +42,7 @@ // Used by the application file system. typedef struct SNotificationData { - uint8_t AlarmStatus[MAX_NOTIFICATIONS]; + uint8_t AlarmStatus[MAX_NUM_OF_NOTIFICATION_GROUPS]; } SNotificationData; #define ZAF_FILE_SIZE_NOTIFICATIONDATA (sizeof(SNotificationData)) diff --git a/protocol/z-wave/ZAF/CommandClasses/Version/CC_Version.c b/protocol/z-wave/ZAF/CommandClasses/Version/CC_Version.c index ec84a16b12..d189ee277f 100644 --- a/protocol/z-wave/ZAF/CommandClasses/Version/CC_Version.c +++ b/protocol/z-wave/ZAF/CommandClasses/Version/CC_Version.c @@ -258,6 +258,8 @@ static received_frame_status_t CC_Version_handler( uint16_t zaf_build_no; zaf_build_no = zaf_config_get_build_no(); + uint16_t protocol_build_no; + protocol_build_no = ZW_GetProtocolBuildNumber(); pTxBuf->ZW_VersionZwaveSoftwareReportV3Frame.cmdClass = COMMAND_CLASS_VERSION_V3; pTxBuf->ZW_VersionZwaveSoftwareReportV3Frame.cmd = VERSION_ZWAVE_SOFTWARE_REPORT_V3; @@ -283,8 +285,8 @@ static received_frame_status_t CC_Version_handler( pTxBuf->ZW_VersionZwaveSoftwareReportV3Frame.zWaveProtocolVersion1 = pAppHandles->pProtocolInfo->ProtocolVersion.Major; pTxBuf->ZW_VersionZwaveSoftwareReportV3Frame.zWaveProtocolVersion2 = pAppHandles->pProtocolInfo->ProtocolVersion.Minor; pTxBuf->ZW_VersionZwaveSoftwareReportV3Frame.zWaveProtocolVersion3 = pAppHandles->pProtocolInfo->ProtocolVersion.Revision; - pTxBuf->ZW_VersionZwaveSoftwareReportV3Frame.zWaveProtocolBuildNumber1 = (uint8_t)(ZW_BUILD_NO >> 8); - pTxBuf->ZW_VersionZwaveSoftwareReportV3Frame.zWaveProtocolBuildNumber2 = (uint8_t)ZW_BUILD_NO; + pTxBuf->ZW_VersionZwaveSoftwareReportV3Frame.zWaveProtocolBuildNumber1 = (uint8_t)(protocol_build_no >> 8); + pTxBuf->ZW_VersionZwaveSoftwareReportV3Frame.zWaveProtocolBuildNumber2 = (uint8_t)protocol_build_no; pTxBuf->ZW_VersionZwaveSoftwareReportV3Frame.applicationVersion1 = zpal_get_app_version_major(); pTxBuf->ZW_VersionZwaveSoftwareReportV3Frame.applicationVersion2 = zpal_get_app_version_minor(); diff --git a/protocol/z-wave/ZWave/API/ZW_application_transport_interface.h b/protocol/z-wave/ZWave/API/ZW_application_transport_interface.h index fb86df55c3..1ac5ffecfb 100644 --- a/protocol/z-wave/ZWave/API/ZW_application_transport_interface.h +++ b/protocol/z-wave/ZWave/API/ZW_application_transport_interface.h @@ -204,6 +204,7 @@ typedef enum EZwaveTransmitType EZWAVETRANSMITTYPE_SEND_SLAVE_DATA, EZWAVETRANSMITTYPE_INCLUDEDNODEINFORMATION, EZWAVETRANSMITTYPE_SECURE, + EZWAVETRANSMITTYPE_NON_SECURE, NUM_EZWAVETRANSMITTYPE } EZwaveTransmitType; @@ -1055,7 +1056,7 @@ typedef enum EZwaveCommandType // TOOD: /** - * @brief + * @brief * * @param[in] NvmBackupRestore.offset * @param[in] NvmBackupRestore.length @@ -1203,16 +1204,66 @@ typedef enum EZwaveCommandType */ EZWAVECOMMANDTYPE_ZW_SET_TX_ATTENUATION, // 125 + /********************************************* * SECURE API interface functions used in apps. ********************************************/ + /** + * @brief Add a new node to the network + * + * @details Used by Portable Controller application to start the process of including a new node to its network. + * After successful inclusion the protocol will send an EZWAVECOMMANDSTATUS_SECURE_ON_NODE_ADDED event + * to the application. + */ + EZWAVECOMMANDTYPE_SECURE_NETWORK_MANAGEMENT_ADD_NODE, // 126 + + /** + * @brief Abort Inclusion or Exclusion of node. + * + * @details Used by Portable Controller application to abort an Inclusion or Exclusion process it has started. + */ + EZWAVECOMMANDTYPE_SECURE_NETWORK_MANAGEMENT_ABORT, // 127 + + /** + * @brief Remove a node from the network + * + * @details Used by Portable Controller application to start the process of excluding a node from its network. + * After successful exclusion the protocol will send an EZWAVECOMMANDSTATUS_SECURE_ON_NODE_DELETED event + * to the application. + */ + EZWAVECOMMANDTYPE_SECURE_NETWORK_MANAGEMENT_REMOVE_NODE, // 128 + + /** + * @brief Unused. Data frames to network nodes are placed directly on the Zwave TxQueue + */ + EZWAVECOMMANDTYPE_SECURE_SEND_DATA, // 129 + + /** + * @brief Put the application in Network Wide Inclusion mode so it can be included in a network. + * + * @details Used by Portable Controller application to get included by a different Controller. + * After successful inclusion the protocol will send an EZWAVECOMMANDSTATUS_SECURE_ON_NEW_NETWORK_ENTERED event + * to the application. + */ + EZWAVECOMMANDTYPE_SECURE_NETWORK_MANAGEMENT_LEARN_MODE_INCLUSION, // 130 + + /** + * @brief Put the application in Network Wide Exclusion mode so it can be excluded from a network. + * + * @details Used by Portable Controller application to get excluded from a network. + * After successful exclusion the protocol will send an EZWAVECOMMANDSTATUS_SECURE_ON_NETWORK_MANAGEMENT_STATE_UPDATE + * event to the application. + */ + EZWAVECOMMANDTYPE_SECURE_NETWORK_MANAGEMENT_LEARN_MODE_EXCLUSION, // 131 + + /** + * @brief Set security flags for a network node. + * + * @details Used by Portable Controller application to set security related flags for a node in its network. + * S2 capable flag, S2 included flag, Secure included flag. + */ + EZWAVECOMMANDTYPE_SECURE_NETWORK_MANAGEMENT_SET_SECURITY_FLAGS, // 132 - EZWAVECOMMANDTYPE_SECURE_NETWORK_MANAGEMENT_ADD_NODE, - EZWAVECOMMANDTYPE_SECURE_NETWORK_MANAGEMENT_ABORT, - EZWAVECOMMANDTYPE_SECURE_NETWORK_MANAGEMENT_REMOVE_NODE, - EZWAVECOMMANDTYPE_SECURE_SEND_DATA, - EZWAVECOMMANDTYPE_SECURE_NETWORK_MANAGEMENT_LEARN_MODE_INCLUSION, - EZWAVECOMMANDTYPE_SECURE_NETWORK_MANAGEMENT_LEARN_MODE_EXCLUSION, NUM_EZWAVECOMMANDTYPE } EZwaveCommandType; @@ -1421,6 +1472,7 @@ typedef struct SAssignReturnRoute node_id_t RouteDestinationNodeId; // Destination of route (if 0 destination will be self). Destination can be a SUC. uint8_t aPriorityRouteRepeaters[4]; // Route to be assigned as priority route - set to zeroes to NOT supply a priority route (recommended) uint8_t PriorityRouteSpeed; + uint8_t isSucRoute; } SAssignReturnRoute; typedef struct SCommandSetRfReceiveMode @@ -1620,8 +1672,8 @@ typedef struct SApplicationHandles typedef struct SRadioConfig_t { int8_t iListenBeforeTalkThreshold; /**< Db (negative) or EListenBeforeTalkThreshold_t */ - int8_t iTxPowerLevelMax; /**< Db (negative) or EtxPowerLevel_t */ - int8_t iTxPowerLevelAdjust; /**< Db (negative) or EtxPowerLevel_t */ + zpal_tx_power_t iTxPowerLevelMax; /**< Db (negative) or EtxPowerLevel_t */ + zpal_tx_power_t iTxPowerLevelAdjust;/**< Db (negative) or EtxPowerLevel_t */ int16_t iTxPowerLevelMaxLR; /**< Maximum transmission power for Z-Wave LR */ zpal_radio_region_t eRegion; /**< RF Region setting */ uint8_t radio_debug_enable; /**< Enable radio PTI */ @@ -1855,6 +1907,15 @@ typedef struct SCommandInitiateShutdown } SCommandInitiateShutdown; +typedef struct SCommandSetSecurityFlags +{ + node_id_t nodeID; + bool nodeS2Capable; + bool nodeS2Included; + bool nodeSecureIncluded; +} SCommandSetSecurityFlags; + + typedef struct SZWaveGetPriorityRouteStatus { uint8_t bAnyRouteFound; @@ -2173,6 +2234,7 @@ typedef struct { typedef struct { ZW_controller_connection_info_t connection; ZW_tx_options_t tx_options; + zwave_keyset_t tx_keys; uint16_t data_length; uint8_t data[TX_BUFFER_SIZE]; void (*ptxCompleteCallback)(uint8_t, const TX_STATUS_TYPE*); @@ -2311,6 +2373,7 @@ typedef union UCommandParameters SCommandGeniric8bParameter SetLRChannel; SCommandGeniric8bParameter SetLRVirtualNodeIDs; SCommandGeniric8bParameter SetTxAttenuation; + SCommandSetSecurityFlags SetSecurityFlags; } UCommandParameters; /************************************************************************** diff --git a/protocol/z-wave/ZWave/API/ZW_basis_api.h b/protocol/z-wave/ZWave/API/ZW_basis_api.h index a17c1d4408..5177f49cb5 100644 --- a/protocol/z-wave/ZWave/API/ZW_basis_api.h +++ b/protocol/z-wave/ZWave/API/ZW_basis_api.h @@ -217,5 +217,11 @@ void sl_zwave_protocol_startup(void); */ void sl_zwave_platform_startup(void); +/** + * Gets Z-Wave Protocol Build number + * @return Z-Wave Protocol Build number + */ +uint16_t ZW_GetProtocolBuildNumber(); + #endif /* _ZW_BASIS_API_H_ */ diff --git a/protocol/z-wave/ZWave/API/ZW_system_startup_api.h b/protocol/z-wave/ZWave/API/ZW_system_startup_api.h index 5e103955f5..a8f1f888b1 100644 --- a/protocol/z-wave/ZWave/API/ZW_system_startup_api.h +++ b/protocol/z-wave/ZWave/API/ZW_system_startup_api.h @@ -97,4 +97,10 @@ void ZW_system_startup_SetMainApplicationTaskHandle(TaskHandle_t xHandle); */ bool ZW_system_startup_IsSchedulerStarted(void); +/** + * Used to get a pointer to The Application node information @ref SAppNodeInfo_t structure. + * + * @return const SAppNodeInfo_t* + */ +const SAppNodeInfo_t* ZW_system_startup_getAppNodeInfo(void); #endif /* _ZW_SYSTEM_STARTUP_H_ */ diff --git a/protocol/z-wave/ZWave/lib/libZWaveControllerPortable_700s.a b/protocol/z-wave/ZWave/lib/libZWaveControllerPortable_700s.a index b4c42e0e1d..4bccfd7e29 100644 --- a/protocol/z-wave/ZWave/lib/libZWaveControllerPortable_700s.a +++ b/protocol/z-wave/ZWave/lib/libZWaveControllerPortable_700s.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8fd32025b55e1636e0e1d3f211aae5cabd6b991f3609f6b1643cf2f9f786d7ed -size 3116780 +oid sha256:ba05f926cbb207dae34df19ac794f3177ea5b083d47eced46fe604ad83768cae +size 3121418 diff --git a/protocol/z-wave/ZWave/lib/libZWaveControllerPortable_800s.a b/protocol/z-wave/ZWave/lib/libZWaveControllerPortable_800s.a index b10b1a91e4..49bab81950 100644 --- a/protocol/z-wave/ZWave/lib/libZWaveControllerPortable_800s.a +++ b/protocol/z-wave/ZWave/lib/libZWaveControllerPortable_800s.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c575ef79003ce9017d3c264aae3ef37217dabb99ad6efbf9293ea0534fa389a3 -size 3090624 +oid sha256:169a7769f190b514ef0c543b6c94cbeddf7b537eade8e0069a5cbd04117f1376 +size 3094866 diff --git a/protocol/z-wave/ZWave/lib/libZWaveController_700s.a b/protocol/z-wave/ZWave/lib/libZWaveController_700s.a index 6945b1693c..38cf654fba 100644 --- a/protocol/z-wave/ZWave/lib/libZWaveController_700s.a +++ b/protocol/z-wave/ZWave/lib/libZWaveController_700s.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4070e4c753c739d79936bf713e6d7f73e110085fa2194b88843623768319acb7 -size 436232 +oid sha256:4ddbba17c091684136372d912e9ddf05de7943190df0084457a9b501e958c320 +size 437364 diff --git a/protocol/z-wave/ZWave/lib/libZWaveController_800s.a b/protocol/z-wave/ZWave/lib/libZWaveController_800s.a index 04f654c74f..cf25d61f07 100644 --- a/protocol/z-wave/ZWave/lib/libZWaveController_800s.a +++ b/protocol/z-wave/ZWave/lib/libZWaveController_800s.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:10d45f3f4ee907d865474983ecf38e80a5b279e516a4248bbb7bff505198793d -size 435944 +oid sha256:029530beb9c8b5204c5f1f352c9a6984f830d9442c75a9a706939ccaf4caf3ce +size 437080 diff --git a/protocol/z-wave/ZWave/lib/libZWaveSlave_700s.a b/protocol/z-wave/ZWave/lib/libZWaveSlave_700s.a index c77080cf89..b570f303ed 100644 --- a/protocol/z-wave/ZWave/lib/libZWaveSlave_700s.a +++ b/protocol/z-wave/ZWave/lib/libZWaveSlave_700s.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:490f4a096e78903152d9bc19d11f9ad4d599fab25811fea7f76573b1b1f008ed -size 408382 +oid sha256:48d8f5f24fe04da474052b9a1b04bcbf53f0365159d798f5aa14e76e1ab0474b +size 408874 diff --git a/protocol/z-wave/ZWave/lib/libZWaveSlave_800s.a b/protocol/z-wave/ZWave/lib/libZWaveSlave_800s.a index 644b5a3c6c..dfd66f1623 100644 --- a/protocol/z-wave/ZWave/lib/libZWaveSlave_800s.a +++ b/protocol/z-wave/ZWave/lib/libZWaveSlave_800s.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4fb0a7b8ecc49766416fe27139285ac1689cc4e1953c0abc9946f8c762dac3e0 -size 408764 +oid sha256:7ce875c5172309a064e14fec19ba422b7596fcd13f658988d7512d3351bc58ae +size 408858 diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_association.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_association.slcc index 59f87992a1..e5018f11e9 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_association.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_association.slcc @@ -34,6 +34,3 @@ provides: requires: - name: zw_core -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/643" - \ No newline at end of file diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_basic.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_basic.slcc index a1deef8e52..3de663b53e 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_basic.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_basic.slcc @@ -21,5 +21,3 @@ provides: - name: zw_cc_basic requires: - name: zw_core -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/638" diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_basiccontroller.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_basiccontroller.slcc index 79e90e589c..7339109a6a 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_basiccontroller.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_basiccontroller.slcc @@ -19,5 +19,3 @@ include: - path: CC_Basic.h provides: - name: zw_cc_basiccontroller -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/638" diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_battery.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_battery.slcc index 308973b2f4..2b8916dd85 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_battery.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_battery.slcc @@ -16,5 +16,3 @@ provides: - name: zw_cc_battery requires: - name: zw_core -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/643" \ No newline at end of file diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_binaryswitch.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_binaryswitch.slcc index a063165b3d..7398f0b7ca 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_binaryswitch.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_binaryswitch.slcc @@ -11,5 +11,3 @@ include: - path: protocol/z-wave/ZAF/CommandClasses/BinarySwitch file_list: - path: CC_BinarySwitch.h -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/638" diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_centralscene.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_centralscene.slcc index 0188e99499..dc9c2cf862 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_centralscene.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_centralscene.slcc @@ -14,5 +14,3 @@ include: - path: CC_CentralScene.h provides: - name: zw_cc_centralscene -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/638" diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_colorswitch.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_colorswitch.slcc index 1902cf92ec..31e6d8cdaa 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_colorswitch.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_colorswitch.slcc @@ -16,5 +16,3 @@ include: - path: CC_ColorSwitch.h provides: - name: zw_cc_colorswitch -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/638" diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_configuration.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_configuration.slcc index 3a0fa8c9de..8a41261c5f 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_configuration.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_configuration.slcc @@ -15,5 +15,3 @@ include: - path: CC_Configuration_Configuration.h provides: - name: zw_cc_configuration -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/638" diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_deviceresetlocally.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_deviceresetlocally.slcc index 3f7d2981ac..c72b880ac7 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_deviceresetlocally.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_deviceresetlocally.slcc @@ -10,5 +10,3 @@ source: - path: protocol/z-wave/ZAF/CommandClasses/DeviceResetLocally/CC_DeviceResetLocally.c provides: - name: zw_cc_deviceresetlocally -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/643" diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_doorlock.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_doorlock.slcc index 66650b2274..e6a5c1a309 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_doorlock.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_doorlock.slcc @@ -15,5 +15,3 @@ provides: - name: zw_cc_doorlock requires: - name: zw_core -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/638" diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_firmwareupdate.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_firmwareupdate.slcc index 327d538a12..02a1b8fa3e 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_firmwareupdate.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_firmwareupdate.slcc @@ -16,5 +16,3 @@ include: - path: ota_util.h provides: - name: zw_cc_firmwareupdate -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/643" diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_indicator.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_indicator.slcc index d17b40364b..8e8abeb3c4 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_indicator.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_indicator.slcc @@ -16,5 +16,3 @@ provides: - name: zw_cc_indicator requires: - name: zw_core -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/643" diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_manufacturerspecific.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_manufacturerspecific.slcc index c43737032e..a9b5cc10b0 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_manufacturerspecific.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_manufacturerspecific.slcc @@ -18,5 +18,3 @@ include: - path: CC_ManufacturerSpecific_config.h provides: - name: zw_cc_manufacturerspecific -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/643" diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_multichannelcontrol.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_multichannelcontrol.slcc index 86f23215b9..ee7d1b690c 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_multichannelcontrol.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_multichannelcontrol.slcc @@ -16,5 +16,3 @@ include: - path: multichannel.h provides: - name: zw_cc_multichannelcontrol -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/652" diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_multichannelsupport.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_multichannelsupport.slcc index ab312ec8e1..2c7d12f1f2 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_multichannelsupport.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_multichannelsupport.slcc @@ -17,5 +17,3 @@ include: - path: CC_MultiChan.h provides: - name: zw_cc_multichannelsupport -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/652" diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_multilevelsensor.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_multilevelsensor.slcc index 6ab3c02df2..04c3ec724e 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_multilevelsensor.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_multilevelsensor.slcc @@ -18,5 +18,3 @@ include: - path: CC_MultilevelSensor_Configuration.h provides: - name: zw_cc_multilevelsensor -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/638" diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_multilevelswitchcontrol.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_multilevelswitchcontrol.slcc index 8fa6e9cb30..895a94ca4d 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_multilevelswitchcontrol.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_multilevelswitchcontrol.slcc @@ -15,5 +15,3 @@ include: - path: CC_MultilevelSwitch_Control.h provides: - name: zw_cc_multilevelswitchcontrol -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/638" diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_multilevelswitchsupport.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_multilevelswitchsupport.slcc index d073851581..e866cb64ef 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_multilevelswitchsupport.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_multilevelswitchsupport.slcc @@ -17,5 +17,3 @@ include: - path: CC_MultilevelSwitch_Support.h provides: - name: zw_cc_multilevelswitchsupport -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/638" diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_notification.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_notification.slcc index aaa4175e4f..816de5292b 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_notification.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_notification.slcc @@ -16,5 +16,3 @@ include: - path: notification.h provides: - name: zw_cc_notification -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/638" diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_powerlevel.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_powerlevel.slcc index 4e268a8aa5..f12bb8de35 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_powerlevel.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_powerlevel.slcc @@ -19,5 +19,3 @@ provides: - name: zw_cc_powerlevel requires: - name: zw_core -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/700" diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_security.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_security.slcc index 91863c4d5b..4494050605 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_security.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_security.slcc @@ -11,5 +11,3 @@ source: provides: - name: zw_cc_security -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/652" diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_simpleav.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_simpleav.slcc index 83fa5a494f..5069413046 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_simpleav.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_simpleav.slcc @@ -13,5 +13,3 @@ include: - path: CC_SimpleAv.h provides: - name: zw_cc_simpleav -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/638" diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_supervision.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_supervision.slcc index 27e4d06251..723467f493 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_supervision.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_supervision.slcc @@ -19,5 +19,3 @@ provides: - name: zw_cc_supervision requires: - name: zw_core -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/652" diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_usercode.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_usercode.slcc index fdb7ad54b1..842c6e3104 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_usercode.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_usercode.slcc @@ -15,5 +15,3 @@ provides: - name: zw_cc_usercode requires: - name: zw_core -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/638" diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_version.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_version.slcc index 4135754a79..3168c54c56 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_version.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_version.slcc @@ -15,5 +15,3 @@ provides: - name: zw_cc_version requires: - name: zw_core -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/643" diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_wakeup.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_wakeup.slcc index 5d684fb43a..10c7be097e 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_wakeup.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_wakeup.slcc @@ -15,5 +15,3 @@ include: - path: CC_WakeUp.h provides: - name: zw_cc_wakeup -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/643" diff --git a/protocol/z-wave/component/CommandClasses/zw_cc_zwaveplusinfo.slcc b/protocol/z-wave/component/CommandClasses/zw_cc_zwaveplusinfo.slcc index 3b58ee29f1..3f84c4534d 100644 --- a/protocol/z-wave/component/CommandClasses/zw_cc_zwaveplusinfo.slcc +++ b/protocol/z-wave/component/CommandClasses/zw_cc_zwaveplusinfo.slcc @@ -19,5 +19,3 @@ include: - path: ZW_plus_version.h provides: - name: zw_cc_zwaveplusinfo -documentation: - url: "https://sdomembers.z-wavealliance.org/document/dl/643" diff --git a/protocol/z-wave/component/zw_appshw_serialapi.slcc b/protocol/z-wave/component/zw_appshw_serialapi.slcc index 0f4f9f11be..68e12726c5 100644 --- a/protocol/z-wave/component/zw_appshw_serialapi.slcc +++ b/protocol/z-wave/component/zw_appshw_serialapi.slcc @@ -4,8 +4,15 @@ category: Z-Wave|AppsHw description: AppsHw for SerialAPI application package: Z-Wave quality: production -ui_hints: - visibility: never +config_file: + # For series 1 + - path: protocol/z-wave/platform/SiliconLabs/AppsHw/inc/SerialAPI/config/s1/serial_api_config.h + file_id: serial_api_config + condition: [device_series_1] + # For series 2 + - path: protocol/z-wave/platform/SiliconLabs/AppsHw/inc/SerialAPI/config/s2/serial_api_config.h + file_id: serial_api_config + condition: [device_series_2] source: - path: "protocol/z-wave/platform/SiliconLabs/AppsHw/src/SerialAPI/SerialAPI_hw.c" include: diff --git a/protocol/z-wave/component/zw_core.slcc b/protocol/z-wave/component/zw_core.slcc index 1f2784d176..d800f1f4d8 100644 --- a/protocol/z-wave/component/zw_core.slcc +++ b/protocol/z-wave/component/zw_core.slcc @@ -39,10 +39,6 @@ requires: - name: rail_util_pa - name: psa_its condition: [device_series_2] - - name: psa_crypto - condition: [device_series_2] - - name: psa_driver - condition: [device_series_2] - name: psa_crypto_ecdh condition: [device_series_2] - name: psa_crypto_cmac @@ -51,8 +47,6 @@ requires: condition: [device_series_2] - name: psa_crypto_ecc_curve25519 condition: [device_series_2] - - name: psa_builtin_key_support_se - condition: [device_series_2, device_has_semailbox] recommends: - id: zw_production - id: zw_release @@ -111,6 +105,9 @@ include: file_list: - path: "zaf_event_helper.h" - path: "zaf_job_helper.h" + - path: "protocol/z-wave/platform/SiliconLabs/PAL/inc" + file_list: + - path: "system_startup.h" - path: "protocol/z-wave/platform/SiliconLabs/PAL/inc/application_properties" file_list: - path: "application_properties_config.h" @@ -172,9 +169,6 @@ define: - name: SL_SE_ASSUME_FW_AT_LEAST_2_1_7 value: 1 condition: [device_sdid_210] -# BUILDING_WITH_UC is used to ensure that non-UC builds still work as intended in the transition phase. - - name: BUILDING_WITH_UC - value: 1 # TODO: Integration hooks needed in FreeRTOS wrapper to register functions for pre/post sleep hooks - name: configPRE_SLEEP_PROCESSING(ms) value: enterPowerDown(ms) diff --git a/protocol/z-wave/component/zw_debug.slcc b/protocol/z-wave/component/zw_debug.slcc index b8563ace49..28622ac5ae 100644 --- a/protocol/z-wave/component/zw_debug.slcc +++ b/protocol/z-wave/component/zw_debug.slcc @@ -8,5 +8,3 @@ provides: - name: zw_debug - name: zw_build_mode -requires: - - name: iostream_recommended_stream diff --git a/protocol/z-wave/component/zw_debug_print.slcc b/protocol/z-wave/component/zw_debug_print.slcc new file mode 100644 index 0000000000..c87db39432 --- /dev/null +++ b/protocol/z-wave/component/zw_debug_print.slcc @@ -0,0 +1,14 @@ +id: zw_debug_print +label: Z-Wave Debug Print +category: Z-Wave +description: Enables debug print. Install this component to get debug output. +package: Z-Wave +quality: production +provides: +- name: zw_debug_print + +requires: + - name: iostream_recommended_stream + - name: zw_debug + - name: iostream_swo + condition: [zw_api_serialapi] \ No newline at end of file diff --git a/protocol/z-wave/component/zw_end_device.slcc b/protocol/z-wave/component/zw_end_device.slcc index 29ca191377..2a322e0fdd 100644 --- a/protocol/z-wave/component/zw_end_device.slcc +++ b/protocol/z-wave/component/zw_end_device.slcc @@ -10,6 +10,13 @@ define: - name: ZW_SLAVE - name: ZW_SLAVE_ROUTING - name: ZW_SECURITY_PROTOCOL + - name: NVM3_DEFAULT_NVM_SIZE + value: 36864 + condition: [device_series_1] + - name: NVM3_DEFAULT_NVM_SIZE + value: 32768 + condition: [device_series_2] + requires: - name: mbedtls_sha1 condition: [device_series_1] diff --git a/protocol/z-wave/component/zw_versions.slcc b/protocol/z-wave/component/zw_versions.slcc index 693c4aeb25..2e7fc8929b 100644 --- a/protocol/z-wave/component/zw_versions.slcc +++ b/protocol/z-wave/component/zw_versions.slcc @@ -13,18 +13,18 @@ define: - name: ZW_VERSION_MINOR value: 18 - name: ZW_VERSION_PATCH - value: 0 + value: 1 # Z-Wave Plus Framework and Apps - name: ZAF_VERSION_MAJOR value: 10 - name: ZAF_VERSION_MINOR value: 18 - name: ZAF_VERSION_PATCH - value: 0 + value: 1 # SDK - name: SDK_VERSION_MAJOR value: 7 - name: SDK_VERSION_MINOR value: 18 - name: SDK_VERSION_PATCH - value: 0 + value: 1 diff --git a/protocol/z-wave/config/zw_build_no.h b/protocol/z-wave/config/zw_build_no.h index 4cb7840737..8dc36d69e6 100644 --- a/protocol/z-wave/config/zw_build_no.h +++ b/protocol/z-wave/config/zw_build_no.h @@ -6,14 +6,10 @@ #ifndef _ZW_BUILD_NO_H_ #define _ZW_BUILD_NO_H_ - -// Can be changed with command line argument. -#ifndef ZW_BUILD_NO -#define ZW_BUILD_NO 0xABCD -#endif - +// Application Framework Build number. +// If not otherwise specified, it is the same as Z-Wave Protocol Build number #ifndef ZAF_BUILD_NO -#define ZAF_BUILD_NO ZW_BUILD_NO +#define ZAF_BUILD_NO ZW_GetProtocolBuildNumber() #endif #endif /* _ZW_BUILD_NO_H_ */ diff --git a/protocol/z-wave/esf.properties b/protocol/z-wave/esf.properties index 4fe57c7c8d..c65ad9e245 100644 --- a/protocol/z-wave/esf.properties +++ b/protocol/z-wave/esf.properties @@ -3,7 +3,7 @@ id=com.silabs.sdk.stack.zwave label=Z-Wave SDK description=Silicon Labs Z-Wave SDK for the EFR32 family -version=7.18.0.0 +version=7.18.1.0 #Build Information @@ -12,7 +12,7 @@ buildNumber=0 # Note: this particular string must be escaped -prop.subLabel=Z-Wave\\ SDK\\ 7.18.0.0 +prop.subLabel=Z-Wave\\ SDK\\ 7.18.1.0 # Path to side-package properties file extendedProperties=efr32zg13l.properties efr32zg13p.properties efr32zg13s.properties @@ -27,4 +27,4 @@ prop.file.docsFile=studio-docs/docs.xml prop.file.demosFile=Apps/bin/demos.xml z-wave_production_demos.xml z-wave_alpha_demos.xml z-wave_beta_demos.xml z-wave_test_demos.xml z-wave_internal_demos.xml z-wave_development_demos.xml # ---- Compatibility ---- -prop.partCompatibility=.*zgm13.* .*efr32zg.* +prop.partCompatibility=.*zgm13.* .*efr32zg.* .*zgm23.* diff --git a/protocol/z-wave/platform/SiliconLabs/AppsHw/inc/SerialAPI/config/s1/serial_api_config.h b/protocol/z-wave/platform/SiliconLabs/AppsHw/inc/SerialAPI/config/s1/serial_api_config.h new file mode 100644 index 0000000000..6e8f3f9ae9 --- /dev/null +++ b/protocol/z-wave/platform/SiliconLabs/AppsHw/inc/SerialAPI/config/s1/serial_api_config.h @@ -0,0 +1,30 @@ +/** + * @file + * Serial API Configuration + * @copyright 2022 Silicon Laboratories Inc. + */ +#ifndef SERIAL_API_CONFIG_H +#define SERIAL_API_CONFIG_H + +#include + +// <<< sl:start pin_tool >>> + +// SERIAL_API + +// $[USART_SERIAL_API] +#define SERIAL_API_PERIPHERAL USART0 +#define SERIAL_API_PERIPHERAL_NO 0 + +#define SERIAL_API_TX_PORT gpioPortA +#define SERIAL_API_TX_PIN 0 +#define SERIAL_API_TX_LOC 0 + +#define SERIAL_API_RX_PORT gpioPortA +#define SERIAL_API_RX_PIN 1 +#define SERIAL_API_RX_LOC 0 +// [USART_SERIAL_API]$ + +// <<< sl:end pin_tool >>> + +#endif // SERIAL_API_CONFIG_H diff --git a/protocol/z-wave/platform/SiliconLabs/AppsHw/inc/SerialAPI/config/s2/serial_api_config.h b/protocol/z-wave/platform/SiliconLabs/AppsHw/inc/SerialAPI/config/s2/serial_api_config.h new file mode 100644 index 0000000000..22bdb679db --- /dev/null +++ b/protocol/z-wave/platform/SiliconLabs/AppsHw/inc/SerialAPI/config/s2/serial_api_config.h @@ -0,0 +1,28 @@ +/** + * @file + * Serial API Configuration + * @copyright 2022 Silicon Laboratories Inc. + */ +#ifndef SERIAL_API_CONFIG_H +#define SERIAL_API_CONFIG_H + +#include + +// <<< sl:start pin_tool >>> + +// SERIAL_API + +// $[USART_SERIAL_API] +#define SERIAL_API_PERIPHERAL USART0 +#define SERIAL_API_PERIPHERAL_NO 0 + +#define SERIAL_API_TX_PORT gpioPortA +#define SERIAL_API_TX_PIN 8 + +#define SERIAL_API_RX_PORT gpioPortA +#define SERIAL_API_RX_PIN 9 +// [USART_SERIAL_API]$ + +// <<< sl:end pin_tool >>> + +#endif // SERIAL_API_CONFIG_H diff --git a/protocol/z-wave/platform/SiliconLabs/AppsHw/inc/target_boards.h b/protocol/z-wave/platform/SiliconLabs/AppsHw/inc/target_boards.h index d3b960cab7..0a2e183bc8 100644 --- a/protocol/z-wave/platform/SiliconLabs/AppsHw/inc/target_boards.h +++ b/protocol/z-wave/platform/SiliconLabs/AppsHw/inc/target_boards.h @@ -50,9 +50,6 @@ #elif defined(RADIO_BOARD_BRD2603A) #include "radio_board_brd2603a.h" -#else -#error "Undefined board!" - #endif #endif /* TARGET_BOARDS_H */ diff --git a/protocol/z-wave/platform/SiliconLabs/AppsHw/src/KeyFob/KeyFob_hw.c b/protocol/z-wave/platform/SiliconLabs/AppsHw/src/KeyFob/KeyFob_hw.c index 097da4a18c..31c044f668 100644 --- a/protocol/z-wave/platform/SiliconLabs/AppsHw/src/KeyFob/KeyFob_hw.c +++ b/protocol/z-wave/platform/SiliconLabs/AppsHw/src/KeyFob/KeyFob_hw.c @@ -116,7 +116,7 @@ void KeyFob_hw_init(EResetReason_t reset_reason) DPRINT("-----------------------------\n"); -// DPRINT("Press RESET BTN to activate ADD/REMOVE End device BTN for 4sec\n"); //If deep sleep is enabled. + DPRINTF("%s: Press for ADD, HOLD for REMOVE End device\n", Board_GetButtonLabel(BUTTON_NETWORK_ADD_REMOVE)); DPRINTF("%s: Hold 5+ sec and release for Reset to Default\n", diff --git a/protocol/z-wave/platform/SiliconLabs/AppsHw/src/LEDBulb/LEDBulb_hw.c b/protocol/z-wave/platform/SiliconLabs/AppsHw/src/LEDBulb/LEDBulb_hw.c index 444889bb26..f147ca7915 100644 --- a/protocol/z-wave/platform/SiliconLabs/AppsHw/src/LEDBulb/LEDBulb_hw.c +++ b/protocol/z-wave/platform/SiliconLabs/AppsHw/src/LEDBulb/LEDBulb_hw.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -14,74 +15,6 @@ //#define DEBUGPRINT #include "DebugPrint.h" -#if defined(BUILDING_WITH_UC) -#include "sl_simple_rgb_pwm_led_instances.h" -#else - -#include "sl_simple_rgb_pwm_led_led_config.h" - -sl_led_pwm_t red_led = { - .port = SL_SIMPLE_RGB_PWM_LED_LED_RED_PORT, - .pin = SL_SIMPLE_RGB_PWM_LED_LED_RED_PIN, - .polarity = SL_SIMPLE_RGB_PWM_LED_LED_RED_POLARITY, - .channel = SL_SIMPLE_RGB_PWM_LED_LED_RED_CHANNEL, -#if defined(SL_SIMPLE_RGB_PWM_LED_LED_RED_LOC) - .location = SL_SIMPLE_RGB_PWM_LED_LED_RED_LOC, -#endif - .timer = SL_SIMPLE_RGB_PWM_LED_LED_PERIPHERAL, - .frequency = SL_SIMPLE_RGB_PWM_LED_LED_FREQUENCY, - .resolution = SL_SIMPLE_RGB_PWM_LED_LED_RESOLUTION, -}; - -sl_led_pwm_t green_led = { - .port = SL_SIMPLE_RGB_PWM_LED_LED_GREEN_PORT, - .pin = SL_SIMPLE_RGB_PWM_LED_LED_GREEN_PIN, - .polarity = SL_SIMPLE_RGB_PWM_LED_LED_GREEN_POLARITY, - .channel = SL_SIMPLE_RGB_PWM_LED_LED_GREEN_CHANNEL, -#if defined(SL_SIMPLE_RGB_PWM_LED_LED_GREEN_LOC) - .location = SL_SIMPLE_RGB_PWM_LED_LED_GREEN_LOC, -#endif - .timer = SL_SIMPLE_RGB_PWM_LED_LED_PERIPHERAL, - .frequency = SL_SIMPLE_RGB_PWM_LED_LED_FREQUENCY, - .resolution = SL_SIMPLE_RGB_PWM_LED_LED_RESOLUTION, -}; - -sl_led_pwm_t blue_led = { - .port = SL_SIMPLE_RGB_PWM_LED_LED_BLUE_PORT, - .pin = SL_SIMPLE_RGB_PWM_LED_LED_BLUE_PIN, - .polarity = SL_SIMPLE_RGB_PWM_LED_LED_BLUE_POLARITY, - .channel = SL_SIMPLE_RGB_PWM_LED_LED_BLUE_CHANNEL, -#if defined(SL_SIMPLE_RGB_PWM_LED_LED_BLUE_LOC) - .location = SL_SIMPLE_RGB_PWM_LED_LED_BLUE_LOC, -#endif - .timer = SL_SIMPLE_RGB_PWM_LED_LED_PERIPHERAL, - .frequency = SL_SIMPLE_RGB_PWM_LED_LED_FREQUENCY, - .resolution = SL_SIMPLE_RGB_PWM_LED_LED_RESOLUTION, -}; - -sl_simple_rgb_pwm_led_context_t simple_rgb_pwm_led_context = { - .red = &red_led, - .green = &green_led, - .blue = &blue_led, - - .timer = SL_SIMPLE_RGB_PWM_LED_LED_PERIPHERAL, - .frequency = SL_SIMPLE_RGB_PWM_LED_LED_FREQUENCY, - .resolution = SL_SIMPLE_RGB_PWM_LED_LED_RESOLUTION, -}; - -const sl_led_rgb_pwm_t sl_led = { - .led_common.context = &simple_rgb_pwm_led_context, - .led_common.init = sl_simple_rgb_pwm_led_init, - .led_common.turn_on = sl_simple_rgb_pwm_led_turn_on, - .led_common.turn_off = sl_simple_rgb_pwm_led_turn_off, - .led_common.toggle = sl_simple_rgb_pwm_led_toggle, - .led_common.get_state = sl_simple_rgb_pwm_led_get_state, - .set_rgb_color = sl_simple_rgb_pwm_led_set_color, - .get_rgb_color = sl_simple_rgb_pwm_led_get_color, -}; - -#endif // BUILDING_WITH_UC - static uint8_t multilevel_switch_max; static uint8_t multilevel_switch_value; static uint8_t color_switch_max; @@ -95,7 +28,7 @@ static void update_rgbw_led(void) (color_switch_red_value * multilevel_switch_value) / multilevel_switch_max, (color_switch_green_value * multilevel_switch_value) / multilevel_switch_max, (color_switch_blue_value * multilevel_switch_value) / multilevel_switch_max); - sl_led_set_rgb_color(&sl_led, + sl_led_set_rgb_color(&sl_simple_rgb_pwm_led_led, (uint16_t)((color_switch_red_value * multilevel_switch_value) / multilevel_switch_max), (uint16_t)((color_switch_green_value * multilevel_switch_value) / multilevel_switch_max), (uint16_t)((color_switch_blue_value * multilevel_switch_value) / multilevel_switch_max)); @@ -140,10 +73,6 @@ void LEDBulb_hw_init(uint8_t multilevel_switch_max_, uint8_t color_switch_max_) multilevel_switch_max = multilevel_switch_max_; color_switch_max = color_switch_max_; - -#if !defined(BUILDING_WITH_UC) - sl_led_init((sl_led_t *)&sl_led); -#endif /* !defined(BUILDING_WITH_UC) */ } void LEDBulb_hw_callback_RED(s_colorComponent * colorComponent) diff --git a/protocol/z-wave/platform/SiliconLabs/AppsHw/src/MultilevelSensor/MultilevelSensor_hw.c b/protocol/z-wave/platform/SiliconLabs/AppsHw/src/MultilevelSensor/MultilevelSensor_hw.c index 96d8d2eeae..6cfab2e2db 100644 --- a/protocol/z-wave/platform/SiliconLabs/AppsHw/src/MultilevelSensor/MultilevelSensor_hw.c +++ b/protocol/z-wave/platform/SiliconLabs/AppsHw/src/MultilevelSensor/MultilevelSensor_hw.c @@ -15,14 +15,19 @@ #include #include +#include + #define MY_BATTERY_SPEC_LEVEL_FULL 3000 // My battery's 100% level (millivolts) #define MY_BATTERY_SPEC_LEVEL_EMPTY 2400 // My battery's 0% level (millivolts) // Only use BTN PB1 and PB2 on Multilevel Sensor // PB3 and PB4 from the extension board use the same // Ports and Pins that the I2C uses -#define EVENT_BTN APP_BUTTON_LEARN_RESET -#define BATTERY_REPORT_BTN APP_BUTTON_A // This button cannot wake up the device from EM4 +#define EVENT_BTN APP_BUTTON_LEARN_RESET +#define REPORT_BTN APP_BUTTON_A // This button cannot wake up the device from EM4 +#define BASIC_SET_BTN APP_BUTTON_A + +#define APP_LED_POWER_ON APP_LED_A // Define the button events used to signify sensor state transitions: // @@ -35,7 +40,7 @@ #define EVENT_TRANSITION_TO_DEACTIVE(event) (BTN_EVENT_UP(EVENT_BTN) == (BUTTON_EVENT)event) /* Ensure we did not allocate the same physical button to more than one function */ -STATIC_ASSERT((APP_BUTTON_LEARN_RESET != BATTERY_REPORT_BTN), +STATIC_ASSERT((APP_BUTTON_LEARN_RESET != REPORT_BTN), STATIC_ASSERT_FAILED_button_overlap); static void button_handler(BUTTON_EVENT event, bool is_called_from_isr) @@ -50,9 +55,9 @@ static void button_handler(BUTTON_EVENT event, bool is_called_from_isr) { app_event = EVENT_APP_BUTTON_LEARN_RESET_SHORT_PRESS; } - else if (BTN_EVENT_SHORT_PRESS(BATTERY_REPORT_BTN) == event) + else if (BTN_EVENT_SHORT_PRESS(REPORT_BTN) == event) { - app_event = EVENT_APP_BUTTON_BATTERY_REPORT; + app_event = EVENT_APP_BUTTON_BATTERY_AND_SENSOR_REPORT; } else if (EVENT_TRANSITION_TO_ACTIVE(event)) { @@ -62,6 +67,10 @@ static void button_handler(BUTTON_EVENT event, bool is_called_from_isr) { app_event = EVENT_APP_TRANSITION_TO_DEACTIVE; } + else if (BTN_EVENT_HOLD(BASIC_SET_BTN) == event) + { + app_event = EVENT_APP_BUTTON_BASIC_SET_REPORT; + } if (app_event != EVENT_EMPTY) { @@ -78,14 +87,17 @@ static void button_handler(BUTTON_EVENT event, bool is_called_from_isr) void MultilevelSensor_hw_init(void) { + /* Init indicator LED */ + Board_SetLed(APP_LED_POWER_ON, LED_ON); + /* hardware initialization */ Board_SetButtonCallback(button_handler); Board_EnableButton(APP_BUTTON_LEARN_RESET); - Board_EnableButton(BATTERY_REPORT_BTN); + Board_EnableButton(REPORT_BTN); // BASIC_SET_BTN mapped to the same button Board_EnableButton(EVENT_BTN); DPRINT("-----------------------------\n"); - DPRINTF("%s: Send battery report\n", Board_GetButtonLabel(BATTERY_REPORT_BTN)); + DPRINTF("%s: Send battery and temperature report\n", Board_GetButtonLabel(REPORT_BTN)); DPRINTF("%s: Toggle learn mode\n", Board_GetButtonLabel(APP_BUTTON_LEARN_RESET)); DPRINT(" Hold 5 sec: Reset\n"); DPRINTF("%s: Activate event\n", Board_GetButtonLabel(EVENT_BTN)); @@ -153,3 +165,8 @@ uint8_t MultilevelSensor_hw_get_battery_level(void) } return roundedLevel; } + +void EMU_EM4PresleepHook(void) +{ + Board_SetLed(APP_LED_POWER_ON, LED_OFF); +} diff --git a/protocol/z-wave/platform/SiliconLabs/AppsHw/src/PowerStrip/PowerStrip_hw.c b/protocol/z-wave/platform/SiliconLabs/AppsHw/src/PowerStrip/PowerStrip_hw.c index 98b92db73f..a59a996bc4 100644 --- a/protocol/z-wave/platform/SiliconLabs/AppsHw/src/PowerStrip/PowerStrip_hw.c +++ b/protocol/z-wave/platform/SiliconLabs/AppsHw/src/PowerStrip/PowerStrip_hw.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -16,7 +17,6 @@ #include "DebugPrint.h" #include - #define OUTLET1_TOGGLE_BTN APP_BUTTON_A #define OUTLET2_DIMMER_BTN APP_BUTTON_B #define NOTIFICATION_TOGGLE_BTN APP_BUTTON_C @@ -35,74 +35,6 @@ STATIC_ASSERT((APP_LED_INDICATOR != OUTLET1_STATUS_LED), STATIC_ASSERT_FAILED_led_overlap); -#if defined(BUILDING_WITH_UC) -#include "sl_simple_rgb_pwm_led_instances.h" -#else - -#include "sl_simple_rgb_pwm_led_led_config.h" - -sl_led_pwm_t red_led = { - .port = SL_SIMPLE_RGB_PWM_LED_LED_RED_PORT, - .pin = SL_SIMPLE_RGB_PWM_LED_LED_RED_PIN, - .polarity = SL_SIMPLE_RGB_PWM_LED_LED_RED_POLARITY, - .channel = SL_SIMPLE_RGB_PWM_LED_LED_RED_CHANNEL, -#if defined(SL_SIMPLE_RGB_PWM_LED_LED_RED_LOC) - .location = SL_SIMPLE_RGB_PWM_LED_LED_RED_LOC, -#endif - .timer = SL_SIMPLE_RGB_PWM_LED_LED_PERIPHERAL, - .frequency = SL_SIMPLE_RGB_PWM_LED_LED_FREQUENCY, - .resolution = SL_SIMPLE_RGB_PWM_LED_LED_RESOLUTION, -}; - -sl_led_pwm_t green_led = { - .port = SL_SIMPLE_RGB_PWM_LED_LED_GREEN_PORT, - .pin = SL_SIMPLE_RGB_PWM_LED_LED_GREEN_PIN, - .polarity = SL_SIMPLE_RGB_PWM_LED_LED_GREEN_POLARITY, - .channel = SL_SIMPLE_RGB_PWM_LED_LED_GREEN_CHANNEL, -#if defined(SL_SIMPLE_RGB_PWM_LED_LED_GREEN_LOC) - .location = SL_SIMPLE_RGB_PWM_LED_LED_GREEN_LOC, -#endif - .timer = SL_SIMPLE_RGB_PWM_LED_LED_PERIPHERAL, - .frequency = SL_SIMPLE_RGB_PWM_LED_LED_FREQUENCY, - .resolution = SL_SIMPLE_RGB_PWM_LED_LED_RESOLUTION, -}; - -sl_led_pwm_t blue_led = { - .port = SL_SIMPLE_RGB_PWM_LED_LED_BLUE_PORT, - .pin = SL_SIMPLE_RGB_PWM_LED_LED_BLUE_PIN, - .polarity = SL_SIMPLE_RGB_PWM_LED_LED_BLUE_POLARITY, - .channel = SL_SIMPLE_RGB_PWM_LED_LED_BLUE_CHANNEL, -#if defined(SL_SIMPLE_RGB_PWM_LED_LED_BLUE_LOC) - .location = SL_SIMPLE_RGB_PWM_LED_LED_BLUE_LOC, -#endif - .timer = SL_SIMPLE_RGB_PWM_LED_LED_PERIPHERAL, - .frequency = SL_SIMPLE_RGB_PWM_LED_LED_FREQUENCY, - .resolution = SL_SIMPLE_RGB_PWM_LED_LED_RESOLUTION, -}; - -sl_simple_rgb_pwm_led_context_t simple_rgb_pwm_led_context = { - .red = &red_led, - .green = &green_led, - .blue = &blue_led, - - .timer = SL_SIMPLE_RGB_PWM_LED_LED_PERIPHERAL, - .frequency = SL_SIMPLE_RGB_PWM_LED_LED_FREQUENCY, - .resolution = SL_SIMPLE_RGB_PWM_LED_LED_RESOLUTION, -}; - -const sl_led_rgb_pwm_t sl_led = { - .led_common.context = &simple_rgb_pwm_led_context, - .led_common.init = sl_simple_rgb_pwm_led_init, - .led_common.turn_on = sl_simple_rgb_pwm_led_turn_on, - .led_common.turn_off = sl_simple_rgb_pwm_led_turn_off, - .led_common.toggle = sl_simple_rgb_pwm_led_toggle, - .led_common.get_state = sl_simple_rgb_pwm_led_get_state, - .set_rgb_color = sl_simple_rgb_pwm_led_set_color, - .get_rgb_color = sl_simple_rgb_pwm_led_get_color, -}; - -#endif // BUILDING_WITH_UC - static void button_handler(BUTTON_EVENT event, bool is_called_from_isr) { EVENT_APP app_event = EVENT_EMPTY; @@ -170,10 +102,6 @@ void PowerStrip_hw_init(void) Board_EnableButton(OUTLET1_TOGGLE_BTN); Board_EnableButton(OUTLET2_DIMMER_BTN); Board_EnableButton(NOTIFICATION_TOGGLE_BTN); - -#if !defined(BUILDING_WITH_UC) - sl_led_init((sl_led_t *)&sl_led); -#endif /* !defined(BUILDING_WITH_UC) */ } void PowerStrip_hw_binary_switch_handler(bool on) @@ -184,5 +112,5 @@ void PowerStrip_hw_binary_switch_handler(bool on) void PowerStrip_hw_multilevel_switch_handler(cc_multilevel_switch_t * p_switch) { const uint8_t level = ZAF_Actuator_GetCurrentValue(&p_switch->actuator); - sl_led_set_rgb_color(&sl_led, (uint16_t)level, (uint16_t)level, (uint16_t)level); + sl_led_set_rgb_color(&sl_simple_rgb_pwm_led_led, (uint16_t)level, (uint16_t)level, (uint16_t)level); } diff --git a/protocol/z-wave/platform/SiliconLabs/AppsHw/src/common/board.c b/protocol/z-wave/platform/SiliconLabs/AppsHw/src/common/board.c index ed1f4a4de9..5b2d49434c 100644 --- a/protocol/z-wave/platform/SiliconLabs/AppsHw/src/common/board.c +++ b/protocol/z-wave/platform/SiliconLabs/AppsHw/src/common/board.c @@ -25,6 +25,8 @@ #include "SizeOf.h" #include +#include + /****************************************************************************/ /* PRIVATE TYPES and DEFINITIONS */ /****************************************************************************/ @@ -1256,14 +1258,6 @@ void Board_GPIO_PinOutSet(GPIO_Port_TypeDef port, unsigned int pin) GPIO_PinOutSet(port, pin); } -void on_pre_unlatch_pin_retention(void) -{ - CMU_ClockEnable(cmuClock_GPIO, true); - - g_gpioEm4Flags = GPIO_IntGet() & _GPIO_IF_EM4WU_MASK; - GPIO_IntClear(g_gpioEm4Flags); -} - /* ------------------------------ BOARD INIT ------------------------------ */ uint32_t Board_Initialize() @@ -1271,30 +1265,13 @@ uint32_t Board_Initialize() CMU_ClockEnable(cmuClock_GPIO, true); m_button_timer_value = 0; -#if !defined(BUILDING_WITH_UC) - /* Unlatch EM4 GPIO pin states after wakeup (OK to call even if not EM4 wakeup) */ - EMU_UnlatchPinRetention(); - - /* Save the EM4 GPIO wakeup flags */ - g_gpioEm4Flags = GPIO_IntGet() & _GPIO_IF_EM4WU_MASK; - GPIO_IntClear(g_gpioEm4Flags); -#endif /* !defined(BUILDING_WITH_UC) */ + g_gpioEm4Flags = getWakeUpFlags(); for (uint32_t led = 0; led < BOARD_LED_COUNT; led++) { Board_ConfigLed(led, true); } -#if !defined(BUILDING_WITH_UC) -// UART init is handled by iostream_recommended_stream automatically -#if defined(HAL_VCOM_ENABLE) && defined(BSP_VCOM_ENABLE_PORT) - GPIO_PinModeSet(BSP_VCOM_ENABLE_PORT, //VCOM_ENABLE_PORT, - BSP_VCOM_ENABLE_PIN, //VCOM_ENABLE_PIN, - gpioModePushPull, - 1); -#endif -#endif // BUILDING_WITH_UC - Assert_SetCb(&Board_DefaultHandler); return 0; diff --git a/protocol/z-wave/platform/SiliconLabs/PAL/config/zw_ota/s2/sl_storage_config.h b/protocol/z-wave/platform/SiliconLabs/PAL/config/zw_ota/s2/sl_storage_config.h index 09e660ffda..6a402f82f6 100644 --- a/protocol/z-wave/platform/SiliconLabs/PAL/config/zw_ota/s2/sl_storage_config.h +++ b/protocol/z-wave/platform/SiliconLabs/PAL/config/zw_ota/s2/sl_storage_config.h @@ -21,9 +21,9 @@ // is set to false. This value will control how much of the flash memory // is reserved for bootloader storage. #if defined(NDEBUG) -#define SL_BOOTLOADER_STORAGE_SIZE 0x0002A000 +#define SL_BOOTLOADER_STORAGE_SIZE 0x0002C000 #else /* defined(NDEBUG) */ -#define SL_BOOTLOADER_STORAGE_SIZE 0x00025000 +#define SL_BOOTLOADER_STORAGE_SIZE 0x00027000 #endif /* defined(NDEBUG) */ // diff --git a/protocol/z-wave/platform/SiliconLabs/PAL/inc/hal-config/hal-config-board-700.h b/protocol/z-wave/platform/SiliconLabs/PAL/inc/hal-config/hal-config-board-700.h index e236899904..19f119a411 100644 --- a/protocol/z-wave/platform/SiliconLabs/PAL/inc/hal-config/hal-config-board-700.h +++ b/protocol/z-wave/platform/SiliconLabs/PAL/inc/hal-config/hal-config-board-700.h @@ -78,37 +78,6 @@ #define HAL_PA_CURVE_HEADER "pa_curves_efr32.h" // [PA]$ -// $[SERIAL] -#define HAL_SERIAL_USART0_ENABLE (0) -#define BSP_SERIAL_APP_PORT (HAL_SERIAL_PORT_USART0) -#define HAL_SERIAL_LEUART0_ENABLE (0) -#define HAL_SERIAL_USART1_ENABLE (0) -#define HAL_SERIAL_RXWAKE_ENABLE (0) -#define BSP_SERIAL_APP_CTS_PIN (2U) -#define BSP_SERIAL_APP_CTS_PORT (gpioPortA) -#define BSP_SERIAL_APP_CTS_LOC (30U) - -#define BSP_SERIAL_APP_RX_PIN (1U) -#define BSP_SERIAL_APP_RX_PORT (gpioPortA) -#define BSP_SERIAL_APP_RX_LOC (0U) - -#define BSP_SERIAL_APP_TX_PIN (0U) -#define BSP_SERIAL_APP_TX_PORT (gpioPortA) -#define BSP_SERIAL_APP_TX_LOC (0U) - -#define BSP_SERIAL_APP_RTS_PIN (3U) - -#define BSP_SERIAL_APP_RTS_PORT (gpioPortA) -#define BSP_SERIAL_APP_RTS_LOC (30U) - -#define HAL_SERIAL_APP_RX_QUEUE_SIZE (128UL) -#define HAL_SERIAL_APP_BAUD_RATE (115200UL) -#define HAL_SERIAL_APP_RXSTOP (16UL) -#define HAL_SERIAL_APP_RXSTART (16UL) -#define HAL_SERIAL_APP_TX_QUEUE_SIZE (128UL) -#define HAL_SERIAL_APP_FLOW_CONTROL (HAL_USART_FLOW_CONTROL_NONE) -// [SERIAL]$ - // $[USART0] #define PORTIO_USART0_CTS_PIN (2U) #define PORTIO_USART0_CTS_PORT (gpioPortA) @@ -192,22 +161,6 @@ // [USART1]$ -// $[VCOM] -#define HAL_VCOM_ENABLE (1) - -#if defined(EFR32ZG13L231F512GM32) || defined(EFR32ZG13L231F512IM32) || \ - defined(EFR32ZG13P231F512GM64) || defined(EFR32ZG13P531F512GM32) || \ - defined(EFR32ZG13P531F512GM48) || defined(EFR32ZG13S231F512GM32) || \ - defined(EFR32ZG14P231F256GM32) || defined(EFR32ZG14P731F256GM32) -#define BSP_VCOM_ENABLE_PIN (14U) -#define BSP_VCOM_ENABLE_PORT (gpioPortD) -#else -#define BSP_VCOM_ENABLE_PIN (5U) -#define BSP_VCOM_ENABLE_PORT (gpioPortA) -#endif -// [VCOM]$ - - #define BSP_ETM_TRACE /* This board supports ETM trace. */ #define BSP_TRACE_ETM_CLKLOC 3 /* ETM_TCLK = PC6 */ #define BSP_TRACE_ETM_TD0LOC 3 /* ETM_TD0 = PC7 */ diff --git a/protocol/z-wave/platform/SiliconLabs/PAL/inc/hal-config/hal-config-board-800.h b/protocol/z-wave/platform/SiliconLabs/PAL/inc/hal-config/hal-config-board-800.h index 7fcccf1090..5a513c8963 100644 --- a/protocol/z-wave/platform/SiliconLabs/PAL/inc/hal-config/hal-config-board-800.h +++ b/protocol/z-wave/platform/SiliconLabs/PAL/inc/hal-config/hal-config-board-800.h @@ -179,53 +179,6 @@ // [PTI]$ -// $[SERIAL] -#define HAL_SERIAL_USART0_ENABLE (0) -#define BSP_SERIAL_APP_PORT (HAL_SERIAL_PORT_USART0) -#define HAL_SERIAL_LEUART0_ENABLE (0) -#define HAL_SERIAL_USART1_ENABLE (0) -#define HAL_SERIAL_RXWAKE_ENABLE (0) - -#define HAL_SERIAL_APP_RX_QUEUE_SIZE (128UL) -#define HAL_SERIAL_APP_BAUD_RATE (115200UL) -#define HAL_SERIAL_APP_RXSTOP (16UL) -#define HAL_SERIAL_APP_RXSTART (16UL) -#define HAL_SERIAL_APP_TX_QUEUE_SIZE (128UL) -#define HAL_SERIAL_APP_FLOW_CONTROL (HAL_USART_FLOW_CONTROL_NONE) - -#ifndef BSP_SERIAL_APP_TX_PIN -#define BSP_SERIAL_APP_TX_PIN (8U) -#endif -#ifndef BSP_SERIAL_APP_TX_PORT -#define BSP_SERIAL_APP_TX_PORT (gpioPortA) -#endif -#ifndef BSP_SERIAL_APP_RX_PIN -#define BSP_SERIAL_APP_RX_PIN (9U) -#else -#endif -#ifndef BSP_SERIAL_APP_RX_PORT -#define BSP_SERIAL_APP_RX_PORT (gpioPortA) -#endif -#ifndef BSP_SERIAL_APP_CTS_PIN -#define BSP_SERIAL_APP_CTS_PIN (10U) -#endif -#ifndef BSP_SERIAL_APP_CTS_PORT -#define BSP_SERIAL_APP_CTS_PORT (gpioPortA) -#endif -#ifndef BSP_SERIAL_APP_CTS_LOC -#define BSP_SERIAL_APP_CTS_LOC (30U) -#endif -#ifndef BSP_SERIAL_APP_RTS_PIN -#define BSP_SERIAL_APP_RTS_PIN (0U) -#endif -#ifndef BSP_SERIAL_APP_RTS_PORT -#define BSP_SERIAL_APP_RTS_PORT (gpioPortA) -#endif -#ifndef BSP_SERIAL_APP_RTS_LOC -#define BSP_SERIAL_APP_RTS_LOC (30U) -#endif -// [SERIAL]$ - // $[SPIDISPLAY] #define BSP_SPIDISPLAY_CS_PIN (8U) @@ -300,13 +253,6 @@ #define HAL_USART0_FLOW_CONTROL (HAL_USART_FLOW_CONTROL_NONE) // [USART0]$ -// $[VCOM] -#define HAL_VCOM_ENABLE (1) - -#define BSP_VCOM_ENABLE_PIN (0U) // in platform file this needs to be updated -#define BSP_VCOM_ENABLE_PORT (gpioPortB) -// [VCOM]$ - #if defined(_SILICON_LABS_MODULE) // Currently there is no support for ZGM23 (22q2) in sl_module.h #if !defined(_SILICON_LABS_32B_SERIES_2) diff --git a/protocol/z-wave/platform/SiliconLabs/PAL/inc/system_startup.h b/protocol/z-wave/platform/SiliconLabs/PAL/inc/system_startup.h new file mode 100644 index 0000000000..758da28a31 --- /dev/null +++ b/protocol/z-wave/platform/SiliconLabs/PAL/inc/system_startup.h @@ -0,0 +1,17 @@ +/** + * @file + * Export of data collected during system startup + * @copyright 2022 Silicon Laboratories Inc. + */ + +#ifndef __SYSTEM_STARTUP_H__ +#define __SYSTEM_STARTUP_H__ + +/** + * @brief Get the wake-up pins activated that led to a wake-up + * + * @return uint32_t GPIO bitmask + */ +uint32_t getWakeUpFlags(void); + +#endif /* __SYSTEM_STARTUP_H__ */ diff --git a/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg14p231f256gm32.a b/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg14p231f256gm32.a index 51d0617229..906dca4595 100644 --- a/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg14p231f256gm32.a +++ b/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg14p231f256gm32.a @@ -1,3 +1,3 @@ version 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104fe5abe9..822ac9863a 100644 --- a/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg23a010f512gm40.a +++ b/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg23a010f512gm40.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5c7372ec62f9eed3c619ce7547d25a740ce55dc6a307b5e703464b45fb4d5825 -size 116424 +oid sha256:c1bd3dc47c1c509eb3260be8d7ae59943cf7daeea46d1887246b84609757ea17 +size 117604 diff --git a/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg23a010f512gm48.a b/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg23a010f512gm48.a index 104fe5abe9..4b9a6213e8 100644 --- a/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg23a010f512gm48.a +++ b/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg23a010f512gm48.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:5c7372ec62f9eed3c619ce7547d25a740ce55dc6a307b5e703464b45fb4d5825 -size 116424 +oid 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b/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg23a020f512gm48.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:305216fc11eb6e7bf1f02b9e7bcc7e33bee1db7191bdef341dce1bc035948f92 -size 116424 +oid sha256:9cb8ae58a0f4652e74b0e096f32f20d4f33fb3d9517ab817a7af3d3cb969c491 +size 117604 diff --git a/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg23b010f512im40.a b/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg23b010f512im40.a index 2086572fa7..6b26fa0800 100644 --- a/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg23b010f512im40.a +++ b/protocol/z-wave/platform/SiliconLabs/PAL/lib/libzpal_efr32zg23b010f512im40.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:96cf63004a661d0715cc7513a62e04dbc1744fda85e22fabccc3762e80153b7c -size 116424 +oid sha256:9cb8ae58a0f4652e74b0e096f32f20d4f33fb3d9517ab817a7af3d3cb969c491 +size 117604 diff --git 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-/***************************************************************************//** - * @file gcc_EFR32ZG23.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.2.0 - * @date 16. December 2020 - * Linker script for Silicon Labs EFR32ZG23 devices - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000280; -__HEAP_SIZE = 0x00000180; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* -FLASH layout -* -------- 0x08000000 BOOTLOADER size = 24K ------ -* -------- 0x08006000 Z-Wave image size = 240K ------ -* ------- 0x08042000 OTA image size = 168K ------ -* ------- 0x0806C000 GAP size = 8K ------ -* ------- 0x0806E000 FS (NVM + NVM3_BASE) size = 64K ------ -* ------- 0x0807E000 TOKENS size = 8K ------ -*/ - -MEMORY -{ - BTL (rx) : ORIGIN = 0x08000000, LENGTH = 24K - FLASH (rx) : ORIGIN = 0x08006000, LENGTH = 240K - OTA (rx) : ORIGIN = 0x08042000, LENGTH = 168K - NVM (rx) : ORIGIN = 0x0806E000, LENGTH = 24K - NVM3_BASE (rx) : ORIGIN = 0x08074000, LENGTH = 40K - TOKENS (rx) : ORIGIN = 0x0807E000, LENGTH = 8K - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapBase - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ - -ENTRY(Reset_Handler) - -SECTIONS -{ - - .zwavenvm (NOLOAD): - { - . = ALIGN(2048); - _zwavenvm = . ; - KEEP(*(.zwavenvm)) - _ezwavenvm = . ; - } >NVM - - .simee (NOLOAD): - { - . = ALIGN(2048); - _simee = . ; - KEEP(*(.simee)) - _esimee = . ; - } >NVM3_BASE - - - - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - - /*We need to calculate the size of the cc_handlers to calculate the total FLASH space used*/ - /*This is useful to make an assert if the total FLASH space used is bigger than the FLASH max size*/ - __start__cc_handlers_v3 = .; - KEEP(*(_cc_handlers_v3*)) - __stop__cc_handlers_v3 = .; - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ - - .gnu.sgstubs : ALIGN(32) - { - . = ALIGN(32); - linker_sg_begin = .; - KEEP(*(.gnu.sgstubs*)) - . = ALIGN(32); - } > FLASH - linker_sg_end = linker_sg_begin + SIZEOF(.gnu.sgstubs); - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - __etext = ALIGN(4); - } > FLASH - - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - . = ALIGN (4); - PROVIDE (__ram_func_section_start = .); - *(.ram) - PROVIDE (__ram_func_section_end = .); - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __HeapBase = .; - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - /* Check if FLASH usage exceeds FLASH size */ - ASSERT( LENGTH(FLASH) >= ((__etext - ORIGIN(FLASH) ) + SIZEOF(.data)), "FLASH memory overflowed !") -} diff --git a/protocol/z-wave/platform/SiliconLabs/PAL/linkerscripts/zgm13-zw700.ld b/protocol/z-wave/platform/SiliconLabs/PAL/linkerscripts/zgm13-zw700.ld deleted file mode 100644 index 901782a48f..0000000000 --- a/protocol/z-wave/platform/SiliconLabs/PAL/linkerscripts/zgm13-zw700.ld +++ /dev/null @@ -1,308 +0,0 @@ -/***************************************************************************//** - * Linker script for Silicon Labs ZGM13 devices - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - - -__STACK_SIZE = 0x00000280; -__HEAP_SIZE = 0x00000180; - -MEMORY -{ - /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 524288 */ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 232K - NVM (rx) : ORIGIN = 0x00074000, LENGTH = 12K - NVM3_BASE (rx) : ORIGIN = 0x00077000, LENGTH = 36K - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 65536 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapBase - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - - .zwavenvm (NOLOAD): - { - . = ALIGN(2048); - _zwavenvm = . ; - KEEP(*(.zwavenvm)) - _ezwavenvm = . ; - } >NVM - - .simee (NOLOAD): - { - . = ALIGN(2048); - _simee = . ; - KEEP(*(.simee)) - _esimee = . ; - } >NVM3_BASE - - - .text : - { - KEEP(*(.vectors)) - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - - /*We need to calculate the size of the cc_handlers to calculate the total FLASH space used*/ - /*This is useful to make an assert if the total FLASH space used is bigger than the FLASH max size*/ - __start__cc_handlers_v3 = .; - KEEP(*(_cc_handlers_v3*)) - __stop__cc_handlers_v3 = .; - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /* - * - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - . = ALIGN (4); - PROVIDE (__ram_func_section_start = .); - *(.ram) - PROVIDE (__ram_func_section_end = .); - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __HeapBase = .; - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - /* Check if FLASH usage exceeds FLASH size */ - ASSERT( LENGTH(FLASH) >= ((__etext - ORIGIN(FLASH) ) + SIZEOF(.data)), "FLASH memory overflowed !") -} diff --git a/protocol/z-wave/platform/SiliconLabs/PAL/linkerscripts/zgm23-zw800.ld b/protocol/z-wave/platform/SiliconLabs/PAL/linkerscripts/zgm23-zw800.ld deleted file mode 100644 index 66433bf002..0000000000 --- a/protocol/z-wave/platform/SiliconLabs/PAL/linkerscripts/zgm23-zw800.ld +++ /dev/null @@ -1,334 +0,0 @@ -/***************************************************************************//** - * @file gcc_ZGM23.ld - * @brief GNU Linker Script for Cortex-M based device - * @version V2.2.0 - * @date 16. December 2020 - * Linker script for Silicon Labs ZGM23 devices - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/* - *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ -/*--------------------- Stack / Heap Configuration ---------------------------- - Stack / Heap Configuration - Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000280; -__HEAP_SIZE = 0x00000180; - -/* - *-------------------- <<< end of configuration section >>> ------------------- - */ - -/* -*FLASH layout -* -------- 0x08000000 BOOTLOADER size = 24K ------ -* -------- 0x08006000 Z-Wave image size = 240K ------ -* ------- 0x08042000 OTA image size = 168K ------ -* ------- 0x0806C000 GAP size = 8K ------ -* ------- 0x0806E000 FS (NVM + NVM3_BASE) size = 64K ------ -* ------- 0x0807E000 TOKENS size = 8K ------ -*/ - -MEMORY -{ - BTL (rx) : ORIGIN = 0x08000000, LENGTH = 24K - FLASH (rx) : ORIGIN = 0x08006000, LENGTH = 240K - OTA (rx) : ORIGIN = 0x08042000, LENGTH = 168K - NVM (rx) : ORIGIN = 0x0806E000, LENGTH = 24K - NVM3_BASE (rx) : ORIGIN = 0x08074000, LENGTH = 40K - TOKENS (rx) : ORIGIN = 0x0807E000, LENGTH = 8K - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapBase - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ - -ENTRY(Reset_Handler) - -SECTIONS -{ - - .zwavenvm (NOLOAD): - { - . = ALIGN(2048); - _zwavenvm = . ; - KEEP(*(.zwavenvm)) - _ezwavenvm = . ; - } >NVM - - .simee (NOLOAD): - { - . = ALIGN(2048); - _simee = . ; - KEEP(*(.simee)) - _esimee = . ; - } >NVM3_BASE - - - - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - - /*We need to calculate the size of the cc_handlers to calculate the total FLASH space used*/ - /*This is useful to make an assert if the total FLASH space used is bigger than the FLASH max size*/ - __start__cc_handlers_v3 = .; - KEEP(*(_cc_handlers_v3*)) - __stop__cc_handlers_v3 = .; - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ - - .gnu.sgstubs : ALIGN(32) - { - . = ALIGN(32); - linker_sg_begin = .; - KEEP(*(.gnu.sgstubs*)) - . = ALIGN(32); - } > FLASH - linker_sg_end = linker_sg_begin + SIZEOF(.gnu.sgstubs); - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - __etext = ALIGN(4); - } > FLASH - - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - . = ALIGN (4); - PROVIDE (__ram_func_section_start = .); - *(.ram) - PROVIDE (__ram_func_section_end = .); - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __HeapBase = .; - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - /* Check if FLASH usage exceeds FLASH size */ - ASSERT( LENGTH(FLASH) >= ((__etext - ORIGIN(FLASH) ) + SIZEOF(.data)), "FLASH memory overflowed !") -} diff --git a/protocol/z-wave/studio-docs/docs.xml b/protocol/z-wave/studio-docs/docs.xml index 73fb33fb29..d0b873a1b8 100644 --- a/protocol/z-wave/studio-docs/docs.xml +++ b/protocol/z-wave/studio-docs/docs.xml @@ -1,318 +1,256 @@ - - + + + Gives guidelines for the Z Wave application developer, when porting software applications based on Z-Wave Framework from 500 to 700. - Gives guidelines for the Z Wave application developer, when porting software applications based on Z-Wave Framework from 500 to 700. - + + Gives guidelines for the Z Wave application developer, when porting software applications based on Z-Wave Framework from 700 to 800. - Gives guidelines for the Z Wave application developer, when porting software applications based on Z-Wave Framework from 700 to 800. - + + Describes how to use the RailTest software to perform RF bring-up tests and validate a design based on the Z-Wave 700 devices, the ZGM130S for end-devices, and the EFR32ZG14 for gateway devices. - Describes how to use the RailTest software to perform RF bring-up tests and validate a design based on the Z-Wave 700 devices, the ZGM130S for end-devices, and the EFR32ZG14 for gateway devices. - + + Provides an implementation guide for integrating Z-Wave 700 devices into product designs. It is intended for product design engineers who aim for a fast integration of Z-Wave 700 devices. - Provides an implementation guide for integrating Z-Wave 700 devices into product designs. It is intended for product design engineers who aim for a fast integration of Z-Wave 700 devices. - + + ZGM130S SIP Module Datasheet - ZGM130S SIP Module Datasheet - + + EFR32ZG14 Z-Wave 700 Modem SoC Data Sheet - EFR32ZG14 Z-Wave 700 Modem SoC Data Sheet - + + ZGM130S Long Range Wireless Starter Kit User's Guide - ZGM130S Long Range Wireless Starter Kit User's Guide - + + Schematic for the BRD4207A Z-Wave 700 Long Range radio board with ZGM130S. - Schematic for the BRD4207A Z-Wave 700 Long Range radio board with ZGM130S. - + + Defines the Z-Wave extensions to the Lock Bits and User Data Page in the Zen Gecko SoCs. - Defines the Z-Wave extensions to the Lock Bits and User Data Page in the Zen Gecko SoCs. - + + Describes the Test Observations (TO) that exists on the development and test tool Z-Wave Zniffer. - Describes the Test Observations (TO) that exists on the development and test tool Z-Wave Zniffer. + Z-Wave Alliance, Z-Wave Plus Role Type Specification - - - - + - - - - - Z-Wave Alliance, Z-Wave Plus Role Type Specification + Z-Wave Alliance, Z-Wave Application Command Class Specification - - - - + - - - - - Z-Wave Alliance, Z-Wave Application Command Class Specification + Z-Wave Alliance, Z-Wave Management Command Class Specification - - - - + - - - - - Z-Wave Alliance, Z-Wave Management Command Class Specification + Z-Wave Alliance, Z-Wave Transport-Encapsulation Command Class Specification - - - - + - - - - - Z-Wave Alliance, Z-Wave Transport-Encapsulation Command Class Specification + Z-Wave Alliance, Z-Wave Network-Protocol Command Class Specification - - - - + - - - - - Z-Wave Alliance, Z-Wave Network-Protocol Command Class Specification + Z-Wave Alliance, Z-Wave Plus v2 Device Type Specification - - - - + - - - - - Z-Wave Alliance, Z-Wave Plus v2 Device Type Specification + Z-Wave Command Class Control Specification - - - - + - - - - - Z-Wave Command Class Control Specification + Z-Wave Alliance, List of defined Z-Wave Command Classes - - - - + - - - - - Z-Wave Alliance, List of defined Z-Wave Command Classes - + + Development Material for UZB-7. - + - Development Material for UZB-7. - + + PCB documentation for UZB-7 PCB. - + - PCB documentation for UZB-7 PCB. - + + EFR32ZG14 Zen Gecko Z-Wave 700 USB Stick Bridge Module UZB-7 Data Sheet + - EFR32ZG14 Zen Gecko Z-Wave 700 USB Stick Bridge Module UZB-7 Data Sheet - + + EFR32ZG14 Long Range Wireless Starter Kit User's Guide - EFR32ZG14 Long Range Wireless Starter Kit User's Guide - + + Guideline for developing serial API based host applications. - + - Guideline for developing serial API based host applications. - + + Instruction for mandatory crystal adjustment for EFR32ZG14 based products. - Instruction for mandatory crystal adjustment for EFR32ZG14 based products. - + + Schematic for the BRD4206A Z-Wave 700 Long Range radio board with EFR32ZG14. - Schematic for the BRD4206A Z-Wave 700 Long Range radio board with EFR32ZG14. + Z-Wave Alliance, Host API Specification. - - - - + - - - - - Z-Wave Alliance, Host API Specification. - + + Describes the Z-Wave Certification process for the Z-Wave 700 products and serves as a guide on where to find additional information. - + - Describes the Z-Wave Certification process for the Z-Wave 700 products and serves as a guide on where to find additional information. - + + Describes the manufacturing test flow for Z-Wave 700 SoC-based products. - + - Describes the manufacturing test flow for Z-Wave 700 SoC-based products. - + + Lists compatibility requirements and sources for all software components in the development environment. Discusses the latest changes to the Silicon Labs Z-Wave SDK and associated utilities, including added/deleted/deprecated features/API, and lists fixed and known issues. - Lists compatibility requirements and sources for all software components in the development environment. Discusses the latest changes to the Silicon Labs Z-Wave SDK and associated utilities, including added/deleted/deprecated features/API, and lists fixed and known issues. - + + Discusses the latest changes to the PC-based Zniffer tool and lists new features. - Discusses the latest changes to the PC-based Zniffer tool and lists new features. - + + Discusses the latest changes to the PC-based Controller code and lists new features. - Discusses the latest changes to the PC-based Controller code and lists new features. - + + Describes the Z-Wave Zniffer development tool used during SW application development for debugging, etc. - Describes the Z-Wave Zniffer development tool used during SW application development for debugging, etc. - + + Z-Wave PC based Controller v5 User Guide. The Z-Wave PC-based Controller application is an example on how Static/Bridge Controller Serial API functionality can be used to implement a Z-Wave-enabled PC application. - Z-Wave PC based Controller v5 User Guide. The Z-Wave PC-based Controller application is an example on how Static/Bridge Controller Serial API functionality can be used to implement a Z-Wave-enabled PC application. - + + Instruction to the Z-Wave XML Editor used to create a C header file and XML file containing the Z-Wave devices and command classes, which can be used by ZWave applications and used for interpretation in Zniffer. - Instruction to the Z-Wave XML Editor used to create a C header file and XML file containing the Z-Wave devices and command classes, which can be used by ZWave applications and used for interpretation in Zniffer. - + + Describes the Z-Wave Plus V2 Application Framework (ZAF) versions distributed on Z-Wave 700 SDKs. The purpose of the ZAF is to facilitate the implementation of robust Z-Wave Plus V2 compliant products. - Describes the Z-Wave Plus V2 Application Framework (ZAF) versions distributed on Z-Wave 700 SDKs. The purpose of the ZAF is to facilitate the implementation of robust Z-Wave Plus V2 compliant products. - + + Describes how to use the Z-Wave certified applications, which come as part of the Z-Wave SDK. - Describes how to use the Z-Wave certified applications, which come as part of the Z-Wave SDK. - + + Describes how to get started with Z-Wave development for end devices using Simplicity Studio. - Describes how to get started with Z-Wave development for end devices using Simplicity Studio. - + + This MS Excel file describes how to measure the Tx power of a Z-Wave frame and use this to calibrate the Tx Power of your final Z-Wave product. - This MS Excel file describes how to measure the Tx power of a Z-Wave frame and use this to calibrate the Tx Power of your final Z-Wave product. - + + Describes how to use the Z-Wave pre-certified applications, which come as part of the Z-Wave SDK. - Describes how to use the Z-Wave pre-certified applications, which come as part of the Z-Wave SDK. - + + Describes how to use the Tiny App for upgrading Secure Element firmware. - Describes how to use the Tiny App for upgrading Secure Element firmware. - + + Describes the functionality available in the RAIL Test application - Describes the functionality available in the RAIL Test application - + + Describes how to get started with Z-Wave 700 development for Controller devices. - + - Describes how to get started with Z-Wave 700 development for Controller devices. - + + Z-Wave gbl files - Z-Wave gbl files diff --git a/protocol/z-wave/z-wave_production_demos.xml b/protocol/z-wave/z-wave_production_demos.xml index 42dd836e66..44f536151f 100644 --- a/protocol/z-wave/z-wave_production_demos.xml +++ b/protocol/z-wave/z-wave_production_demos.xml @@ -1,1963 +1,1963 @@ - - - - - - - Prebuilt Z-Wave - NCP Serial API Controller binary for EU Region. The Z-Wave SerialAPI Controller application. + + + + + + + - - - - - - - Prebuilt Z-Wave - NCP Serial API Controller binary for EU Region. The Z-Wave SerialAPI Controller application. + + + + + + + - - - - - - - Prebuilt Z-Wave - NCP Serial API Controller binary for EU Region. The Z-Wave SerialAPI Controller application. + + + + + + + - - - - - - - Prebuilt Z-Wave - NCP Serial API Controller binary for EU Region. The Z-Wave SerialAPI Controller application. + + + + + + + - - - - - - - Prebuilt Z-Wave - NCP Serial API Controller binary for EU Region. The Z-Wave SerialAPI Controller application. + + + + + + + - - - - - - - Prebuilt Z-Wave - NCP Serial API Controller binary for EU Region. The Z-Wave SerialAPI Controller application. + + + + + + + - - - - - - - Prebuilt Z-Wave - NCP Serial API Controller binary for EU Region. The Z-Wave SerialAPI Controller application. + + + + + + + - - - - - - - Prebuilt Z-Wave - NCP Serial API Controller binary for EU Region. The Z-Wave SerialAPI Controller application. + + + + + + + - - - - - - - Prebuilt Z-Wave - NCP Serial API Controller binary for EU Region. The Z-Wave SerialAPI Controller application. + + + + + + + - - - - - - - Prebuilt Z-Wave - NCP Serial API Controller binary for EU Region. The Z-Wave SerialAPI Controller application. + + + + + + + - - - - - - - Prebuilt Z-Wave - NCP Serial API Controller binary for US Region. The Z-Wave SerialAPI Controller application. + + + + + + + - - - - - - - Prebuilt Z-Wave - NCP Serial API Controller binary for US Region. The Z-Wave SerialAPI Controller application. + + + + + + + - - - - - - - Prebuilt Z-Wave - NCP Serial API Controller binary for US Region. The Z-Wave SerialAPI Controller application. + + + + + + + - - - - - - - Prebuilt Z-Wave - NCP Serial API Controller binary for US Region. The Z-Wave SerialAPI Controller application. + + + + + + + - - - - - - - Prebuilt Z-Wave - NCP Serial API Controller binary for US Region. The Z-Wave SerialAPI Controller application. + + + + + + + - - - - - - - Prebuilt Z-Wave - NCP Serial API Controller binary for US Region. The Z-Wave SerialAPI Controller application. + + + + + + + - - - - - - - Prebuilt Z-Wave - NCP Serial API Controller binary for US Region. The Z-Wave SerialAPI Controller application. + + + + + + + - - - - - - - Prebuilt Z-Wave - NCP Serial API Controller binary for US Region. The Z-Wave SerialAPI Controller application. + + + + + + + - - - - - - - Prebuilt Z-Wave - NCP Serial API Controller binary for US Region. The Z-Wave SerialAPI Controller application. + + + + + + + - - - - - - - Prebuilt Z-Wave - NCP Serial API Controller binary for US Region. The Z-Wave SerialAPI Controller application. + + + + + + + - - - - - - - Prebuilt Z-Wave - NCP Serial API Controller binary for US_LR Region. The Z-Wave SerialAPI Controller application. + + + + + + + - - - - - - - Prebuilt Z-Wave - NCP Serial API Controller binary for US_LR Region. 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It is possible to both lock and unlock the door remotely through the Z-Wave protocol. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Door Lock Keypad binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Door Lock application shows a lock implementation. It will support user codes to open a door and thereby eliminate the need for traditional keys. It is possible to both lock and unlock the door remotely through the Z-Wave protocol. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Door Lock Keypad binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Door Lock application shows a lock implementation. It will support user codes to open a door and thereby eliminate the need for traditional keys. It is possible to both lock and unlock the door remotely through the Z-Wave protocol. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Door Lock Keypad binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Door Lock application shows a lock implementation. It will support user codes to open a door and thereby eliminate the need for traditional keys. It is possible to both lock and unlock the door remotely through the Z-Wave protocol. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Door Lock Keypad binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Door Lock application shows a lock implementation. It will support user codes to open a door and thereby eliminate the need for traditional keys. It is possible to both lock and unlock the door remotely through the Z-Wave protocol. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Door Lock Keypad binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Door Lock application shows a lock implementation. It will support user codes to open a door and thereby eliminate the need for traditional keys. It is possible to both lock and unlock the door remotely through the Z-Wave protocol. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Door Lock Keypad binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Door Lock application shows a lock implementation. It will support user codes to open a door and thereby eliminate the need for traditional keys. It is possible to both lock and unlock the door remotely through the Z-Wave protocol. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Door Lock Keypad binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Door Lock application shows a lock implementation. It will support user codes to open a door and thereby eliminate the need for traditional keys. It is possible to both lock and unlock the door remotely through the Z-Wave protocol. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Door Lock Keypad binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Door Lock application shows a lock implementation. It will support user codes to open a door and thereby eliminate the need for traditional keys. It is possible to both lock and unlock the door remotely through the Z-Wave protocol. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Door Lock Keypad binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Door Lock application shows a lock implementation. It will support user codes to open a door and thereby eliminate the need for traditional keys. It is possible to both lock and unlock the door remotely through the Z-Wave protocol. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Door Lock Keypad binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Door Lock application shows a lock implementation. It will support user codes to open a door and thereby eliminate the need for traditional keys. It is possible to both lock and unlock the door remotely through the Z-Wave protocol. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Door Lock Keypad binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Door Lock application shows a lock implementation. It will support user codes to open a door and thereby eliminate the need for traditional keys. It is possible to both lock and unlock the door remotely through the Z-Wave protocol. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Door Lock Keypad binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Door Lock application shows a lock implementation. It will support user codes to open a door and thereby eliminate the need for traditional keys. It is possible to both lock and unlock the door remotely through the Z-Wave protocol. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Door Lock Keypad binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Door Lock application shows a lock implementation. It will support user codes to open a door and thereby eliminate the need for traditional keys. It is possible to both lock and unlock the door remotely through the Z-Wave protocol. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Door Lock Keypad binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Door Lock application shows a lock implementation. It will support user codes to open a door and thereby eliminate the need for traditional keys. It is possible to both lock and unlock the door remotely through the Z-Wave protocol. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Door Lock Keypad binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Door Lock application shows a lock implementation. It will support user codes to open a door and thereby eliminate the need for traditional keys. It is possible to both lock and unlock the door remotely through the Z-Wave protocol. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Door Lock Keypad binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Door Lock application shows a lock implementation. It will support user codes to open a door and thereby eliminate the need for traditional keys. It is possible to both lock and unlock the door remotely through the Z-Wave protocol. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Door Lock Keypad binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Door Lock application shows a lock implementation. It will support user codes to open a door and thereby eliminate the need for traditional keys. It is possible to both lock and unlock the door remotely through the Z-Wave protocol. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Door Lock Keypad binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Door Lock application shows a lock implementation. It will support user codes to open a door and thereby eliminate the need for traditional keys. It is possible to both lock and unlock the door remotely through the Z-Wave protocol. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Key Fob binary for EU Region. The Key Fob application capable of including/excluding and controlling the included end devices through the BASIC Command Class When ever a functionality is done the Key Fob will go into EM4 power mode and can only wakeup from EM4 either through a reset or a button press on either BTN1 or BTN2 + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Key Fob binary for EU Region. The Key Fob application capable of including/excluding and controlling the included end devices through the BASIC Command Class When ever a functionality is done the Key Fob will go into EM4 power mode and can only wakeup from EM4 either through a reset or a button press on either BTN1 or BTN2 + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Key Fob binary for EU Region. The Key Fob application capable of including/excluding and controlling the included end devices through the BASIC Command Class When ever a functionality is done the Key Fob will go into EM4 power mode and can only wakeup from EM4 either through a reset or a button press on either BTN1 or BTN2 + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Key Fob binary for EU Region. The Key Fob application capable of including/excluding and controlling the included end devices through the BASIC Command Class When ever a functionality is done the Key Fob will go into EM4 power mode and can only wakeup from EM4 either through a reset or a button press on either BTN1 or BTN2 + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Key Fob binary for US Region. The Key Fob application capable of including/excluding and controlling the included end devices through the BASIC Command Class When ever a functionality is done the Key Fob will go into EM4 power mode and can only wakeup from EM4 either through a reset or a button press on either BTN1 or BTN2 + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Key Fob binary for US Region. The Key Fob application capable of including/excluding and controlling the included end devices through the BASIC Command Class When ever a functionality is done the Key Fob will go into EM4 power mode and can only wakeup from EM4 either through a reset or a button press on either BTN1 or BTN2 + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Key Fob binary for US Region. The Key Fob application capable of including/excluding and controlling the included end devices through the BASIC Command Class When ever a functionality is done the Key Fob will go into EM4 power mode and can only wakeup from EM4 either through a reset or a button press on either BTN1 or BTN2 + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Key Fob binary for US Region. The Key Fob application capable of including/excluding and controlling the included end devices through the BASIC Command Class When ever a functionality is done the Key Fob will go into EM4 power mode and can only wakeup from EM4 either through a reset or a button press on either BTN1 or BTN2 + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Portable Controller binary for US_LR Region. The Key Fob application capable of including/excluding and controlling the included end devices through the BASIC Command Class When ever a functionality is done the Key Fob will go into EM4 power mode and can only wakeup from EM4 either through a reset or a button press on either BTN1 or BTN2 + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Portable Controller binary for US_LR Region. The Key Fob application capable of including/excluding and controlling the included end devices through the BASIC Command Class When ever a functionality is done the Key Fob will go into EM4 power mode and can only wakeup from EM4 either through a reset or a button press on either BTN1 or BTN2 + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Portable Controller binary for US_LR Region. The Key Fob application capable of including/excluding and controlling the included end devices through the BASIC Command Class When ever a functionality is done the Key Fob will go into EM4 power mode and can only wakeup from EM4 either through a reset or a button press on either BTN1 or BTN2 + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Portable Controller binary for US_LR Region. The Key Fob application capable of including/excluding and controlling the included end devices through the BASIC Command Class When ever a functionality is done the Key Fob will go into EM4 power mode and can only wakeup from EM4 either through a reset or a button press on either BTN1 or BTN2 + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Portable Controller binary for US_LR Region. The Key Fob application capable of including/excluding and controlling the included end devices through the BASIC Command Class When ever a functionality is done the Key Fob will go into EM4 power mode and can only wakeup from EM4 either through a reset or a button press on either BTN1 or BTN2 + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC LED Bulb binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified LED Bulb application shows an implementation of a remotely controlled color switch. An example is a LED bulb or any other color capable device. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC LED Bulb binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified LED Bulb application shows an implementation of a remotely controlled color switch. An example is a LED bulb or any other color capable device. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC LED Bulb binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified LED Bulb application shows an implementation of a remotely controlled color switch. An example is a LED bulb or any other color capable device. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC LED Bulb binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified LED Bulb application shows an implementation of a remotely controlled color switch. An example is a LED bulb or any other color capable device. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC LED Bulb binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified LED Bulb application shows an implementation of a remotely controlled color switch. An example is a LED bulb or any other color capable device. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC LED Bulb binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified LED Bulb application shows an implementation of a remotely controlled color switch. An example is a LED bulb or any other color capable device. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC LED Bulb binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified LED Bulb application shows an implementation of a remotely controlled color switch. An example is a LED bulb or any other color capable device. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC LED Bulb binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified LED Bulb application shows an implementation of a remotely controlled color switch. An example is a LED bulb or any other color capable device. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC LED Bulb binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified LED Bulb application shows an implementation of a remotely controlled color switch. An example is a LED bulb or any other color capable device. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC LED Bulb binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified LED Bulb application shows an implementation of a remotely controlled color switch. An example is a LED bulb or any other color capable device. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC LED Bulb binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified LED Bulb application shows an implementation of a remotely controlled color switch. An example is a LED bulb or any other color capable device. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC LED Bulb binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified LED Bulb application shows an implementation of a remotely controlled color switch. An example is a LED bulb or any other color capable device. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC LED Bulb binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified LED Bulb application shows an implementation of a remotely controlled color switch. An example is a LED bulb or any other color capable device. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Multilevel Sensor binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Switch Multilevel Sensor application shows the ability to advertise numerical sensor readings, such as temperature, and humidity. Multiple parameters can be set for the minimum and maximum values, and a notification will be send if the measured temperature value is out of the range. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Multilevel Sensor binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Switch Multilevel Sensor application shows the ability to advertise numerical sensor readings, such as temperature, and humidity. Multiple parameters can be set for the minimum and maximum values, and a notification will be send if the measured temperature value is out of the range. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Multilevel Sensor binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Switch Multilevel Sensor application shows the ability to advertise numerical sensor readings, such as temperature, and humidity. Multiple parameters can be set for the minimum and maximum values, and a notification will be send if the measured temperature value is out of the range. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Multilevel Sensor binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Switch Multilevel Sensor application shows the ability to advertise numerical sensor readings, such as temperature, and humidity. Multiple parameters can be set for the minimum and maximum values, and a notification will be send if the measured temperature value is out of the range. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Multilevel Sensor binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Switch Multilevel Sensor application shows the ability to advertise numerical sensor readings, such as temperature, and humidity. Multiple parameters can be set for the minimum and maximum values, and a notification will be send if the measured temperature value is out of the range. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Multilevel Sensor binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Switch Multilevel Sensor application shows the ability to advertise numerical sensor readings, such as temperature, and humidity. Multiple parameters can be set for the minimum and maximum values, and a notification will be send if the measured temperature value is out of the range. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Multilevel Sensor binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Switch Multilevel Sensor application shows the ability to advertise numerical sensor readings, such as temperature, and humidity. Multiple parameters can be set for the minimum and maximum values, and a notification will be send if the measured temperature value is out of the range. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Multilevel Sensor binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Switch Multilevel Sensor application shows the ability to advertise numerical sensor readings, such as temperature, and humidity. Multiple parameters can be set for the minimum and maximum values, and a notification will be send if the measured temperature value is out of the range. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Multilevel Sensor binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Switch Multilevel Sensor application shows the ability to advertise numerical sensor readings, such as temperature, and humidity. Multiple parameters can be set for the minimum and maximum values, and a notification will be send if the measured temperature value is out of the range. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Multilevel Sensor binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Switch Multilevel Sensor application shows the ability to advertise numerical sensor readings, such as temperature, and humidity. Multiple parameters can be set for the minimum and maximum values, and a notification will be send if the measured temperature value is out of the range. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Multilevel Sensor binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Switch Multilevel Sensor application shows the ability to advertise numerical sensor readings, such as temperature, and humidity. Multiple parameters can be set for the minimum and maximum values, and a notification will be send if the measured temperature value is out of the range. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Multilevel Sensor binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Switch Multilevel Sensor application shows the ability to advertise numerical sensor readings, such as temperature, and humidity. Multiple parameters can be set for the minimum and maximum values, and a notification will be send if the measured temperature value is out of the range. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Multilevel Sensor binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Switch Multilevel Sensor application shows the ability to advertise numerical sensor readings, such as temperature, and humidity. Multiple parameters can be set for the minimum and maximum values, and a notification will be send if the measured temperature value is out of the range. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Multilevel Sensor binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Switch Multilevel Sensor application shows the ability to advertise numerical sensor readings, such as temperature, and humidity. Multiple parameters can be set for the minimum and maximum values, and a notification will be send if the measured temperature value is out of the range. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Multilevel Sensor binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Switch Multilevel Sensor application shows the ability to advertise numerical sensor readings, such as temperature, and humidity. Multiple parameters can be set for the minimum and maximum values, and a notification will be send if the measured temperature value is out of the range. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Multilevel Sensor binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Switch Multilevel Sensor application shows the ability to advertise numerical sensor readings, such as temperature, and humidity. Multiple parameters can be set for the minimum and maximum values, and a notification will be send if the measured temperature value is out of the range. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Multilevel Sensor binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Switch Multilevel Sensor application shows the ability to advertise numerical sensor readings, such as temperature, and humidity. Multiple parameters can be set for the minimum and maximum values, and a notification will be send if the measured temperature value is out of the range. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Multilevel Sensor binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Switch Multilevel Sensor application shows the ability to advertise numerical sensor readings, such as temperature, and humidity. Multiple parameters can be set for the minimum and maximum values, and a notification will be send if the measured temperature value is out of the range. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Multilevel Sensor binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Switch Multilevel Sensor application shows the ability to advertise numerical sensor readings, such as temperature, and humidity. Multiple parameters can be set for the minimum and maximum values, and a notification will be send if the measured temperature value is out of the range. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Multilevel Sensor binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Switch Multilevel Sensor application shows the ability to advertise numerical sensor readings, such as temperature, and humidity. Multiple parameters can be set for the minimum and maximum values, and a notification will be send if the measured temperature value is out of the range. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Multilevel Sensor binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Switch Multilevel Sensor application shows the ability to advertise numerical sensor readings, such as temperature, and humidity. Multiple parameters can be set for the minimum and maximum values, and a notification will be send if the measured temperature value is out of the range. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Multilevel Sensor binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Switch Multilevel Sensor application shows the ability to advertise numerical sensor readings, such as temperature, and humidity. Multiple parameters can be set for the minimum and maximum values, and a notification will be send if the measured temperature value is out of the range. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Multilevel Sensor binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Switch Multilevel Sensor application shows the ability to advertise numerical sensor readings, such as temperature, and humidity. Multiple parameters can be set for the minimum and maximum values, and a notification will be send if the measured temperature value is out of the range. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Power Strip binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Power Strip application shows an extension block implementation used to turn on several devices that are connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Power Strip binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Power Strip application shows an extension block implementation used to turn on several devices that are connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Power Strip binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Power Strip application shows an extension block implementation used to turn on several devices that are connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Power Strip binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Power Strip application shows an extension block implementation used to turn on several devices that are connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Power Strip binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Power Strip application shows an extension block implementation used to turn on several devices that are connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Power Strip binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Power Strip application shows an extension block implementation used to turn on several devices that are connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Power Strip binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Power Strip application shows an extension block implementation used to turn on several devices that are connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Power Strip binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Power Strip application shows an extension block implementation used to turn on several devices that are connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Power Strip binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Power Strip application shows an extension block implementation used to turn on several devices that are connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Power Strip binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Power Strip application shows an extension block implementation used to turn on several devices that are connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Power Strip binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Power Strip application shows an extension block implementation used to turn on several devices that are connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Power Strip binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Power Strip application shows an extension block implementation used to turn on several devices that are connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Power Strip binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Power Strip application shows an extension block implementation used to turn on several devices that are connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Sensor PIR binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Sensor PIR application shows a presence/movement detector implementation for controlling other devices and for sending notifications. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Sensor PIR binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Sensor PIR application shows a presence/movement detector implementation for controlling other devices and for sending notifications. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Sensor PIR binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Sensor PIR application shows a presence/movement detector implementation for controlling other devices and for sending notifications. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Sensor PIR binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Sensor PIR application shows a presence/movement detector implementation for controlling other devices and for sending notifications. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Sensor PIR binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Sensor PIR application shows a presence/movement detector implementation for controlling other devices and for sending notifications. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Sensor PIR binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Sensor PIR application shows a presence/movement detector implementation for controlling other devices and for sending notifications. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Sensor PIR binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Sensor PIR application shows a presence/movement detector implementation for controlling other devices and for sending notifications. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Sensor PIR binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Sensor PIR application shows a presence/movement detector implementation for controlling other devices and for sending notifications. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Sensor PIR binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Sensor PIR application shows a presence/movement detector implementation for controlling other devices and for sending notifications. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Sensor PIR binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Sensor PIR application shows a presence/movement detector implementation for controlling other devices and for sending notifications. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Sensor PIR binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Sensor PIR application shows a presence/movement detector implementation for controlling other devices and for sending notifications. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Sensor PIR binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Sensor PIR application shows a presence/movement detector implementation for controlling other devices and for sending notifications. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Sensor PIR binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Sensor PIR application shows a presence/movement detector implementation for controlling other devices and for sending notifications. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Sensor PIR binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Sensor PIR application shows a presence/movement detector implementation for controlling other devices and for sending notifications. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Sensor PIR binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Sensor PIR application shows a presence/movement detector implementation for controlling other devices and for sending notifications. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Sensor PIR binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Sensor PIR application shows a presence/movement detector implementation for controlling other devices and for sending notifications. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Sensor PIR binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Sensor PIR application shows a presence/movement detector implementation for controlling other devices and for sending notifications. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Sensor PIR binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Sensor PIR application shows a presence/movement detector implementation for controlling other devices and for sending notifications. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Sensor PIR binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Sensor PIR application shows a presence/movement detector implementation for controlling other devices and for sending notifications. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Sensor PIR binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Sensor PIR application shows a presence/movement detector implementation for controlling other devices and for sending notifications. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Switch On/Off binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Switch On/Off application shows a switch implementation that turns on any device that is connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Switch On/Off binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Switch On/Off application shows a switch implementation that turns on any device that is connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Switch On/Off binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Switch On/Off application shows a switch implementation that turns on any device that is connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Switch On/Off binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Switch On/Off application shows a switch implementation that turns on any device that is connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Switch On/Off binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Switch On/Off application shows a switch implementation that turns on any device that is connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Switch On/Off binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Switch On/Off application shows a switch implementation that turns on any device that is connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Switch On/Off binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Switch On/Off application shows a switch implementation that turns on any device that is connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Switch On/Off binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Switch On/Off application shows a switch implementation that turns on any device that is connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Switch On/Off binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Switch On/Off application shows a switch implementation that turns on any device that is connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Switch On/Off binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Switch On/Off application shows a switch implementation that turns on any device that is connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Switch On/Off binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Switch On/Off application shows a switch implementation that turns on any device that is connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Switch On/Off binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Switch On/Off application shows a switch implementation that turns on any device that is connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Switch On/Off binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Switch On/Off application shows a switch implementation that turns on any device that is connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Switch On/Off binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Switch On/Off application shows a switch implementation that turns on any device that is connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Switch On/Off binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Switch On/Off application shows a switch implementation that turns on any device that is connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Switch On/Off binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Switch On/Off application shows a switch implementation that turns on any device that is connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Switch On/Off binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Switch On/Off application shows a switch implementation that turns on any device that is connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Switch On/Off binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Switch On/Off application shows a switch implementation that turns on any device that is connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Switch On/Off binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Switch On/Off application shows a switch implementation that turns on any device that is connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Switch On/Off binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Switch On/Off application shows a switch implementation that turns on any device that is connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Switch On/Off binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Switch On/Off application shows a switch implementation that turns on any device that is connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Switch On/Off binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Switch On/Off application shows a switch implementation that turns on any device that is connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Switch On/Off binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Switch On/Off application shows a switch implementation that turns on any device that is connected to power. Examples include lights, appliances, etc. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Wall Controller binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Wall Controller application shows a push-button switch panel implementation to control devices in the Z-Wave network from push buttons (physical or virtual) on a device that is meant to be mounted on a wall. Examples include scene and zone controller and wall-mounted AV controllers. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Wall Controller binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Wall Controller application shows a push-button switch panel implementation to control devices in the Z-Wave network from push buttons (physical or virtual) on a device that is meant to be mounted on a wall. Examples include scene and zone controller and wall-mounted AV controllers. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Wall Controller binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Wall Controller application shows a push-button switch panel implementation to control devices in the Z-Wave network from push buttons (physical or virtual) on a device that is meant to be mounted on a wall. Examples include scene and zone controller and wall-mounted AV controllers. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Wall Controller binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Wall Controller application shows a push-button switch panel implementation to control devices in the Z-Wave network from push buttons (physical or virtual) on a device that is meant to be mounted on a wall. Examples include scene and zone controller and wall-mounted AV controllers. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Wall Controller binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Wall Controller application shows a push-button switch panel implementation to control devices in the Z-Wave network from push buttons (physical or virtual) on a device that is meant to be mounted on a wall. Examples include scene and zone controller and wall-mounted AV controllers. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Wall Controller binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Wall Controller application shows a push-button switch panel implementation to control devices in the Z-Wave network from push buttons (physical or virtual) on a device that is meant to be mounted on a wall. Examples include scene and zone controller and wall-mounted AV controllers. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Wall Controller binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Wall Controller application shows a push-button switch panel implementation to control devices in the Z-Wave network from push buttons (physical or virtual) on a device that is meant to be mounted on a wall. Examples include scene and zone controller and wall-mounted AV controllers. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Wall Controller binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Wall Controller application shows a push-button switch panel implementation to control devices in the Z-Wave network from push buttons (physical or virtual) on a device that is meant to be mounted on a wall. Examples include scene and zone controller and wall-mounted AV controllers. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Wall Controller binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Wall Controller application shows a push-button switch panel implementation to control devices in the Z-Wave network from push buttons (physical or virtual) on a device that is meant to be mounted on a wall. Examples include scene and zone controller and wall-mounted AV controllers. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Wall Controller binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Wall Controller application shows a push-button switch panel implementation to control devices in the Z-Wave network from push buttons (physical or virtual) on a device that is meant to be mounted on a wall. Examples include scene and zone controller and wall-mounted AV controllers. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Wall Controller binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Wall Controller application shows a push-button switch panel implementation to control devices in the Z-Wave network from push buttons (physical or virtual) on a device that is meant to be mounted on a wall. Examples include scene and zone controller and wall-mounted AV controllers. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Wall Controller binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Wall Controller application shows a push-button switch panel implementation to control devices in the Z-Wave network from push buttons (physical or virtual) on a device that is meant to be mounted on a wall. Examples include scene and zone controller and wall-mounted AV controllers. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Wall Controller binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Wall Controller application shows a push-button switch panel implementation to control devices in the Z-Wave network from push buttons (physical or virtual) on a device that is meant to be mounted on a wall. Examples include scene and zone controller and wall-mounted AV controllers. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Wall Controller binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Wall Controller application shows a push-button switch panel implementation to control devices in the Z-Wave network from push buttons (physical or virtual) on a device that is meant to be mounted on a wall. Examples include scene and zone controller and wall-mounted AV controllers. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Wall Controller binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Wall Controller application shows a push-button switch panel implementation to control devices in the Z-Wave network from push buttons (physical or virtual) on a device that is meant to be mounted on a wall. Examples include scene and zone controller and wall-mounted AV controllers. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Wall Controller binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Wall Controller application shows a push-button switch panel implementation to control devices in the Z-Wave network from push buttons (physical or virtual) on a device that is meant to be mounted on a wall. Examples include scene and zone controller and wall-mounted AV controllers. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Wall Controller binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Wall Controller application shows a push-button switch panel implementation to control devices in the Z-Wave network from push buttons (physical or virtual) on a device that is meant to be mounted on a wall. Examples include scene and zone controller and wall-mounted AV controllers. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Wall Controller binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Wall Controller application shows a push-button switch panel implementation to control devices in the Z-Wave network from push buttons (physical or virtual) on a device that is meant to be mounted on a wall. Examples include scene and zone controller and wall-mounted AV controllers. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Wall Controller binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Wall Controller application shows a push-button switch panel implementation to control devices in the Z-Wave network from push buttons (physical or virtual) on a device that is meant to be mounted on a wall. Examples include scene and zone controller and wall-mounted AV controllers. + + + + + + + - - - - - - - Prebuilt Z-Wave - SoC Wall Controller binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave certified Wall Controller application shows a push-button switch panel implementation to control devices in the Z-Wave network from push buttons (physical or virtual) on a device that is meant to be mounted on a wall. Examples include scene and zone controller and wall-mounted AV controllers. + + + + + + + diff --git a/protocol/z-wave/z-wave_production_templates.xml b/protocol/z-wave/z-wave_production_templates.xml index 76af666907..1d90008c41 100644 --- a/protocol/z-wave/z-wave_production_templates.xml +++ b/protocol/z-wave/z-wave_production_templates.xml @@ -8,7 +8,7 @@ - + @@ -23,7 +23,7 @@ - + @@ -38,7 +38,7 @@ - + @@ -53,7 +53,7 @@ - + @@ -68,7 +68,7 @@ - + @@ -83,7 +83,7 @@ - + @@ -98,7 +98,7 @@ - + @@ -113,7 +113,7 @@ - + @@ -128,7 +128,7 @@ - + @@ -143,7 +143,7 @@ - + diff --git a/protocol/z-wave/z-wave_test_demos.xml b/protocol/z-wave/z-wave_test_demos.xml new file mode 100644 index 0000000000..02d9de770e --- /dev/null +++ b/protocol/z-wave/z-wave_test_demos.xml @@ -0,0 +1,203 @@ + + + + Prebuilt ZnifferPTI binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Zniffer PTI application. + + + + + + + + + + Prebuilt ZnifferPTI binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Zniffer PTI application. + + + + + + + + + + Prebuilt ZnifferPTI binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Zniffer PTI application. + + + + + + + + + + Prebuilt ZnifferPTI binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Zniffer PTI application. + + + + + + + + + + Prebuilt ZnifferPTI binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Zniffer PTI application. + + + + + + + + + + Prebuilt ZnifferPTI binary for EU Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Zniffer PTI application. + + + + + + + + + + Prebuilt ZnifferPTI binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Zniffer PTI application. + + + + + + + + + + Prebuilt ZnifferPTI binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Zniffer PTI application. + + + + + + + + + + Prebuilt ZnifferPTI binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Zniffer PTI application. + + + + + + + + + + Prebuilt ZnifferPTI binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Zniffer PTI application. + + + + + + + + + + Prebuilt ZnifferPTI binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Zniffer PTI application. + + + + + + + + + + Prebuilt ZnifferPTI binary for US Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Zniffer PTI application. + + + + + + + + + + Prebuilt ZnifferPTI binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Zniffer PTI application. + + + + + + + + + + Prebuilt ZnifferPTI binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Zniffer PTI application. + + + + + + + + + + Prebuilt ZnifferPTI binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Zniffer PTI application. + + + + + + + + + + Prebuilt ZnifferPTI binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Zniffer PTI application. + + + + + + + + + + Prebuilt ZnifferPTI binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Zniffer PTI application. + + + + + + + + + + Prebuilt ZnifferPTI binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Zniffer PTI application. + + + + + + + + + + Prebuilt ZnifferPTI binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Zniffer PTI application. + + + + + + + + + + Prebuilt ZnifferPTI binary for US_LR Region. NOTE that this region is only used if MFG_ZWAVE_COUNTRY_FREQ is not set. The Z-Wave Zniffer PTI application. + + + + + + + + + diff --git a/protocol/zigbee/app/em260/command-handlers-binding-generated.c b/protocol/zigbee/app/em260/command-handlers-binding-generated.c index 1b54519ef4..a3d1be0622 100644 --- a/protocol/zigbee/app/em260/command-handlers-binding-generated.c +++ b/protocol/zigbee/app/em260/command-handlers-binding-generated.c @@ -17,6 +17,7 @@ #include "stack/include/cbke-crypto-engine.h" #include "stack/include/mfglib.h" #include "stack/include/binding-table.h" +#include "stack/include/message.h" #include "app/util/ezsp/ezsp-frame-utilities.h" #include "app/em260/command-handlers-cbke.h" #include "app/em260/command-handlers-binding.h" diff --git a/protocol/zigbee/app/em260/command-handlers-certificate-based-key-exchange-cbke-generated.c b/protocol/zigbee/app/em260/command-handlers-certificate-based-key-exchange-cbke-generated.c index 54de3fb10a..ccc7071daf 100644 --- a/protocol/zigbee/app/em260/command-handlers-certificate-based-key-exchange-cbke-generated.c +++ b/protocol/zigbee/app/em260/command-handlers-certificate-based-key-exchange-cbke-generated.c @@ -17,6 +17,7 @@ #include "stack/include/cbke-crypto-engine.h" #include "stack/include/mfglib.h" #include "stack/include/binding-table.h" +#include "stack/include/message.h" #include "app/util/ezsp/ezsp-frame-utilities.h" #include "app/em260/command-handlers-cbke.h" #include "app/em260/command-handlers-binding.h" diff --git a/protocol/zigbee/app/em260/command-handlers-green-power-generated.c b/protocol/zigbee/app/em260/command-handlers-green-power-generated.c index 740f79f133..3bb6c5ca69 100644 --- a/protocol/zigbee/app/em260/command-handlers-green-power-generated.c +++ b/protocol/zigbee/app/em260/command-handlers-green-power-generated.c @@ -17,6 +17,7 @@ #include "stack/include/cbke-crypto-engine.h" #include "stack/include/mfglib.h" #include "stack/include/binding-table.h" +#include "stack/include/message.h" #include "app/util/ezsp/ezsp-frame-utilities.h" #include "app/em260/command-handlers-cbke.h" #include "app/em260/command-handlers-binding.h" diff --git a/protocol/zigbee/app/em260/command-handlers-mfglib-generated.c b/protocol/zigbee/app/em260/command-handlers-mfglib-generated.c index 41e445575e..7aa47a56a3 100644 --- a/protocol/zigbee/app/em260/command-handlers-mfglib-generated.c +++ b/protocol/zigbee/app/em260/command-handlers-mfglib-generated.c @@ -17,6 +17,7 @@ #include "stack/include/cbke-crypto-engine.h" #include "stack/include/mfglib.h" #include "stack/include/binding-table.h" +#include "stack/include/message.h" #include "app/util/ezsp/ezsp-frame-utilities.h" #include "app/em260/command-handlers-cbke.h" #include "app/em260/command-handlers-binding.h" diff --git a/protocol/zigbee/app/em260/command-handlers-networking-generated.c b/protocol/zigbee/app/em260/command-handlers-networking-generated.c index 66a59e94b8..ae20d7bc02 100644 --- a/protocol/zigbee/app/em260/command-handlers-networking-generated.c +++ b/protocol/zigbee/app/em260/command-handlers-networking-generated.c @@ -17,6 +17,7 @@ #include "stack/include/cbke-crypto-engine.h" #include "stack/include/mfglib.h" #include "stack/include/binding-table.h" +#include "stack/include/message.h" #include "app/util/ezsp/ezsp-frame-utilities.h" #include "app/em260/command-handlers-cbke.h" #include "app/em260/command-handlers-binding.h" diff --git a/protocol/zigbee/app/em260/command-handlers-security-generated.c b/protocol/zigbee/app/em260/command-handlers-security-generated.c index 86c354aaca..2757810374 100644 --- a/protocol/zigbee/app/em260/command-handlers-security-generated.c +++ b/protocol/zigbee/app/em260/command-handlers-security-generated.c @@ -17,6 +17,7 @@ #include "stack/include/cbke-crypto-engine.h" #include "stack/include/mfglib.h" #include "stack/include/binding-table.h" +#include "stack/include/message.h" #include "app/util/ezsp/ezsp-frame-utilities.h" #include "app/em260/command-handlers-cbke.h" #include "app/em260/command-handlers-binding.h" diff --git a/protocol/zigbee/app/em260/command-handlers-token-interface-generated.c b/protocol/zigbee/app/em260/command-handlers-token-interface-generated.c index 5fcf770ca0..1d40a7129f 100644 --- a/protocol/zigbee/app/em260/command-handlers-token-interface-generated.c +++ b/protocol/zigbee/app/em260/command-handlers-token-interface-generated.c @@ -17,6 +17,7 @@ #include "stack/include/cbke-crypto-engine.h" #include "stack/include/mfglib.h" #include "stack/include/binding-table.h" +#include "stack/include/message.h" #include "app/util/ezsp/ezsp-frame-utilities.h" #include "app/em260/command-handlers-cbke.h" #include "app/em260/command-handlers-binding.h" diff --git a/protocol/zigbee/app/em260/command-handlers-trust-center-generated.c b/protocol/zigbee/app/em260/command-handlers-trust-center-generated.c index d1c1f425f1..39ef94afd6 100644 --- a/protocol/zigbee/app/em260/command-handlers-trust-center-generated.c +++ b/protocol/zigbee/app/em260/command-handlers-trust-center-generated.c @@ -17,6 +17,7 @@ #include "stack/include/cbke-crypto-engine.h" #include "stack/include/mfglib.h" #include "stack/include/binding-table.h" +#include "stack/include/message.h" #include "app/util/ezsp/ezsp-frame-utilities.h" #include "app/em260/command-handlers-cbke.h" #include "app/em260/command-handlers-binding.h" diff --git a/protocol/zigbee/app/em260/command-handlers-zll-generated.c b/protocol/zigbee/app/em260/command-handlers-zll-generated.c index 6a5da50cd8..cc76515404 100644 --- a/protocol/zigbee/app/em260/command-handlers-zll-generated.c +++ b/protocol/zigbee/app/em260/command-handlers-zll-generated.c @@ -17,6 +17,7 @@ #include "stack/include/cbke-crypto-engine.h" #include "stack/include/mfglib.h" #include "stack/include/binding-table.h" +#include "stack/include/message.h" #include "app/util/ezsp/ezsp-frame-utilities.h" #include "app/em260/command-handlers-cbke.h" #include "app/em260/command-handlers-binding.h" diff --git a/protocol/zigbee/app/em260/serial-interface-uart.c b/protocol/zigbee/app/em260/serial-interface-uart.c index ef9cb2c0b1..a7af58db82 100644 --- a/protocol/zigbee/app/em260/serial-interface-uart.c +++ b/protocol/zigbee/app/em260/serial-interface-uart.c @@ -168,6 +168,12 @@ uint8_t serialGetCommandLength(void) void serialSetResponseLength(uint8_t data) { emberSetMessageBufferLength(ezspBuffer, data); + + // emberSetMessageBufferLength has the potential effect of setting ezspBuffer + // to a brand new buffer. This can happen if ezspBuffer is being extended. + // As a result of that, we'll need to refresh ezspFrameContents, which is + // supposed to track the buffer contents of ezspBuffer + ezspFrameContents = emberMessageBufferContents(ezspBuffer); } bool serialCallbackResponse(void) diff --git a/protocol/zigbee/app/framework/cli/core-cli.c b/protocol/zigbee/app/framework/cli/core-cli.c index 3459a87188..b5dc0e73ab 100644 --- a/protocol/zigbee/app/framework/cli/core-cli.c +++ b/protocol/zigbee/app/framework/cli/core-cli.c @@ -58,29 +58,27 @@ void sli_zigbee_cli_config_cca_mode_command(sl_cli_command_arg_t *arguments) void sli_cli_pre_cmd_hook(sl_cli_command_arg_t* arguments) { (void)arguments; - emberAfPushNetworkIndex(emAfCliNetworkIndex); -#if defined(SL_CATALOG_KERNEL_PRESENT) - #if defined(SL_CATALOG_BLUETOOTH_PRESENT) +#if defined(SL_CATALOG_BLUETOOTH_PRESENT) //Do not lock/unlock kernel for BLE commands uint8_t cmd_count = sl_cli_get_command_count(arguments); - - if ( cmd_count >= 2) { + if (cmd_count >= 2) { char *cmd1_ptr = sl_cli_get_command_string(arguments, 0); char *cmd2_ptr = sl_cli_get_command_string(arguments, 1); + // condition below should be true for any cli that starts with plug ble + // strncmp returns 0 when the comparison results in a match + if ( (strncmp(cmd1_ptr, "plug", 4) == 0) && (strncmp(cmd2_ptr, "ble", 3) == 0) ) { + return; + } + } +#endif //#if defined(SL_CATALOG_BLUETOOTH_PRESENT) - if ( (strncmp(cmd1_ptr, "plug", 4) || strcmp(cmd2_ptr, "ble")) - && (strcmp(cmd1_ptr, "dmp_test"))) { - #endif //#if defined(SL_CATALOG_BLUETOOTH_PRESENT) - + // Lock OS kernel to prevent CLI task from calling ember functions + // CLI task is lower priority than zigbee and can be preempted + #if defined(SL_CATALOG_KERNEL_PRESENT) (void)osKernelLock(); - - #if defined(SL_CATALOG_BLUETOOTH_PRESENT) -} -} - #endif // #if defined(SL_CATALOG_BLUETOOTH_PRESENT) -#endif //#if defined(SL_CATALOG_KERNEL_PRESENT) + #endif //#if defined(SL_CATALOG_KERNEL_PRESENT) } void sli_cli_post_cmd_hook(sl_cli_command_arg_t* arguments) diff --git a/protocol/zigbee/app/framework/cli/network-cli.c b/protocol/zigbee/app/framework/cli/network-cli.c index ee86aba147..72c33388f5 100644 --- a/protocol/zigbee/app/framework/cli/network-cli.c +++ b/protocol/zigbee/app/framework/cli/network-cli.c @@ -22,6 +22,9 @@ // TODO: this is to bring in emAfPermitJoin() and emberAfGetBindingTableSize() // prototypes. #include "app/framework/util/af-main.h" +#ifdef SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT +#include "test-harness-config.h" +#endif uint8_t emAfCliNetworkIndex = EMBER_AF_DEFAULT_NETWORK_INDEX; extern uint8_t emAfExtendedPanId[]; @@ -88,11 +91,11 @@ void networkLeaveCommand(sl_cli_command_arg_t *arguments) sl_zigbee_core_debug_print("%s 0x%02X\n", "leave", status); } -// network rejoin +// network rejoin void networkRejoinCommand(sl_cli_command_arg_t *arguments) { bool haveCurrentNetworkKey = (bool)sl_cli_get_argument_uint8(arguments, 0); - uint32_t channelMask = sl_cli_get_argument_uint32(arguments, 0); + uint32_t channelMask = sl_cli_get_argument_uint32(arguments, 1); if (channelMask == 0) { channelMask = EMBER_ALL_802_15_4_CHANNELS_MASK; } @@ -154,8 +157,9 @@ void networkChangeChannelCommand(sl_cli_command_arg_t *arguments) channel, status); } - -#ifdef EMBER_AF_TC_SWAP_OUT_TEST +// This block of code is under UC_BUILD, so the EMBER_AF_TC_SWAP_OUT_TEST +// is defined to either 1 or 0 as a UC configuration. +#if (EMBER_AF_TC_SWAP_OUT_TEST == 1) void networkInitCommand(sl_cli_command_arg_t *arguments) { EmberNetworkInitStruct networkInitStruct = { @@ -425,7 +429,7 @@ void networkJoinCommand(void) emberAfAppPrintln("%p 0x%x", "join", status); } -// network rejoin +// network rejoin void networkRejoinCommand(void) { bool haveCurrentNetworkKey = (bool)emberUnsignedCommandArgument(0); diff --git a/protocol/zigbee/app/framework/cli/zcl-cli.c b/protocol/zigbee/app/framework/cli/zcl-cli.c index 48909ab533..a188f6f0e0 100644 --- a/protocol/zigbee/app/framework/cli/zcl-cli.c +++ b/protocol/zigbee/app/framework/cli/zcl-cli.c @@ -23,6 +23,7 @@ #include "app/framework/util/af-main.h" #include "app/framework/util/util.h" #include "zap-config.h" +#include "zcl-cli.h" //------------------------------------------------------------------------------ // Globals @@ -93,6 +94,13 @@ void eraseKeyTableEntry(uint8_t index) } } +// Key Delete command +void keysDeleteCommand(sl_cli_command_arg_t *arguments) +{ + uint8_t index = sl_cli_get_argument_uint8(arguments, 0); + eraseKeyTableEntry(index); +} + // keys clear void keysClearCommand(void) { @@ -442,6 +450,39 @@ void sli_zigbee_zcl_buffer_add_length_and_string(sl_cli_command_arg_t *arguments appZclBufferLen += length + prefixSize; } +/** + * @brief + * Given a 32-bit value and a specified number of bits fewer than 32, check that + * the value does not exceed the range of the specified number of bits. + * @param val + * @param bits + * @return true if value in range else return false + */ +static bool is_zcl_data_type_in_range(uint32_t val, uint8_t bits) +{ + if (bits == 0 || bits > 31) { + return false; + } + // Construct mask of the container's unused higher order bits. + uint32_t unusedBitsMask = ~((1u << bits) - 1u); + // Return true if the unused higher order bits are all zero. + return (unusedBitsMask & val) == 0; +} + +/** + * @brief + * Given a value then add n number of bytes into the zcl buffer from that value + * @param val + * @param noOfBytes + */ +static void add_bytes_to_zcl_buffer(uint32_t val, uint8_t noOfBytes) +{ + for (uint8_t i = 0; i < noOfBytes; i++) { + uint8_t byteN = (uint8_t)(val >> (8u * i)); + sli_zigbee_zcl_buffer_add_byte(byteN); + } +} + // Handles any zcl command where the argument list of the // command is simply appended to the zcl buffer. Handles argument types // mentioned in the switch case below. String arguments are written with @@ -456,56 +497,88 @@ void sli_zigbee_zcl_simple_command(uint8_t frameControl, uint8_t count = sl_cli_get_argument_count(arguments); uint8_t type; uint8_t typeIndex = 0; + uint8_t *hex_value = 0; + size_t hex_length = 0; zclBufferSetup(frameControl, clusterId, commandId); for (argumentIndex = 0; argumentIndex < count; argumentIndex++) { type = argumentTypes[typeIndex]; // For zcl cli array arguments are referenced as optional arguments. // Therefore the type of the arguments should remain the same for them. - if (type != SL_CLI_ARG_UINT8OPT - && type != SL_CLI_ARG_UINT16OPT - && type != SL_CLI_ARG_UINT32OPT - && type != SL_CLI_ARG_INT8OPT - && type != SL_CLI_ARG_INT16OPT - && type != SL_CLI_ARG_INT32OPT - && type != SL_CLI_ARG_STRINGOPT - && type != SL_CLI_ARG_HEXOPT) { + if (type != SL_ZCL_CLI_ARG_UINT8OPT + && type != SL_ZCL_CLI_ARG_UINT16OPT + && type != SL_ZCL_CLI_ARG_UINT24OPT + && type != SL_ZCL_CLI_ARG_UINT32OPT + && type != SL_ZCL_CLI_ARG_UINT40OPT + && type != SL_ZCL_CLI_ARG_UINT48OPT + && type != SL_ZCL_CLI_ARG_UINT56OPT + && type != SL_ZCL_CLI_ARG_UINT64OPT + && type != SL_ZCL_CLI_ARG_INT8OPT + && type != SL_ZCL_CLI_ARG_INT16OPT + && type != SL_ZCL_CLI_ARG_INT24OPT + && type != SL_ZCL_CLI_ARG_INT32OPT + && type != SL_ZCL_CLI_ARG_INT40OPT + && type != SL_ZCL_CLI_ARG_INT48OPT + && type != SL_ZCL_CLI_ARG_INT56OPT + && type != SL_ZCL_CLI_ARG_INT64OPT + && type != SL_ZCL_CLI_ARG_STRINGOPT + && type != SL_ZCL_CLI_ARG_HEXOPT) { typeIndex++; } switch (type) { - case SL_CLI_ARG_UINT8: - case SL_CLI_ARG_UINT8OPT: + case SL_ZCL_CLI_ARG_UINT8: + case SL_ZCL_CLI_ARG_UINT8OPT: sli_zigbee_zcl_buffer_add_byte((uint8_t)sl_cli_get_argument_uint8(arguments, argumentIndex)); break; - case SL_CLI_ARG_UINT16: - case SL_CLI_ARG_UINT16OPT: + case SL_ZCL_CLI_ARG_UINT16: + case SL_ZCL_CLI_ARG_UINT16OPT: sli_zigbee_zcl_buffer_add_word(sl_cli_get_argument_uint16(arguments, argumentIndex)); break; - case SL_CLI_ARG_UINT32: - case SL_CLI_ARG_UINT32OPT: + case SL_ZCL_CLI_ARG_UINT24: + case SL_ZCL_CLI_ARG_UINT24OPT: + if (is_zcl_data_type_in_range(sl_cli_get_argument_uint32(arguments, argumentIndex), 24u)) { + add_bytes_to_zcl_buffer(sl_cli_get_argument_uint32(arguments, argumentIndex), 3); + } else { + emberAfAppPrintln("Argument at index: %d is out of range", argumentIndex); + goto kickout; + } + break; + case SL_ZCL_CLI_ARG_UINT32: + case SL_ZCL_CLI_ARG_UINT32OPT: sli_zigbee_zcl_buffer_add_int32(sl_cli_get_argument_uint32(arguments, argumentIndex)); break; - case SL_CLI_ARG_INT8: - case SL_CLI_ARG_INT8OPT: + case SL_ZCL_CLI_ARG_INT8: + case SL_ZCL_CLI_ARG_INT8OPT: sli_zigbee_zcl_buffer_add_byte((uint8_t)sl_cli_get_argument_int8(arguments, argumentIndex)); break; - case SL_CLI_ARG_INT16: - case SL_CLI_ARG_INT16OPT: + case SL_ZCL_CLI_ARG_INT16: + case SL_ZCL_CLI_ARG_INT16OPT: sli_zigbee_zcl_buffer_add_word(sl_cli_get_argument_int16(arguments, argumentIndex)); break; - case SL_CLI_ARG_INT32: - case SL_CLI_ARG_INT32OPT: + case SL_ZCL_CLI_ARG_INT24: + case SL_ZCL_CLI_ARG_INT24OPT: + if (is_zcl_data_type_in_range(sl_cli_get_argument_int32(arguments, argumentIndex), 24u)) { + add_bytes_to_zcl_buffer(sl_cli_get_argument_int32(arguments, argumentIndex), 3); + } else { + emberAfAppPrintln("Argument at index: %d is out of range", argumentIndex); + goto kickout; + } + break; + case SL_ZCL_CLI_ARG_INT32: + case SL_ZCL_CLI_ARG_INT32OPT: sli_zigbee_zcl_buffer_add_int32(sl_cli_get_argument_int32(arguments, argumentIndex)); break; - case SL_CLI_ARG_STRING: - case SL_CLI_ARG_HEX: - case SL_CLI_ARG_STRINGOPT: - case SL_CLI_ARG_HEXOPT: - sli_zigbee_zcl_buffer_add_length_and_string(arguments, argumentIndex, false); + case SL_ZCL_CLI_ARG_HEX: + case SL_ZCL_CLI_ARG_HEXOPT: + hex_value = sl_cli_get_argument_hex(arguments, argumentIndex, &hex_length); + for (uint8_t i = 0; i < hex_length; i++) { + appZclBuffer[appZclBufferLen + i] = hex_value[i]; + } + appZclBufferLen += hex_length; break; - case SL_CLI_ARG_ADDITIONAL: - case SL_CLI_ARG_WILDCARD: - case SL_CLI_ARG_GROUP: + case SL_ZCL_CLI_ARG_STRING: + case SL_ZCL_CLI_ARG_STRINGOPT: + sli_zigbee_zcl_buffer_add_length_and_string(arguments, argumentIndex, false); break; default: goto kickout; diff --git a/protocol/zigbee/app/framework/cli/zcl-cli.h b/protocol/zigbee/app/framework/cli/zcl-cli.h new file mode 100644 index 0000000000..dabed7e923 --- /dev/null +++ b/protocol/zigbee/app/framework/cli/zcl-cli.h @@ -0,0 +1,90 @@ +/***************************************************************************//** + * @file + * @brief CLI commands for sending various messages. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SILABS_ZCL_CLI_H +#define SILABS_ZCL_CLI_H + +#ifndef UC_BUILD // In UC we only support generated CLI, no legacy +#if !defined(EMBER_AF_GENERATE_CLI) +void emAfCliSendCommand(void); +void emAfCliSendUsingMulticastBindingCommand(void); +void emAfCliBsendCommand(void); +void emAfCliReadCommand(void); +void emAfCliWriteCommand(void); +void emAfCliTimesyncCommand(void); +void emAfCliRawCommand(void); +void emAfCliAddReportEntryCommand(void); +#endif +extern EmberCommandEntry keysCommands[]; +extern EmberCommandEntry interpanCommands[]; +extern EmberCommandEntry printCommands[]; +extern EmberCommandEntry zclCommands[]; +extern EmberCommandEntry certificationCommands[]; +#else +#define SL_ZCL_CLI_ARG_UINT8 0x01u +#define SL_ZCL_CLI_ARG_UINT16 0x02u +#define SL_ZCL_CLI_ARG_UINT24 0x03u +#define SL_ZCL_CLI_ARG_UINT32 0x04u +#define SL_ZCL_CLI_ARG_UINT40 0x05u +#define SL_ZCL_CLI_ARG_UINT48 0x06u +#define SL_ZCL_CLI_ARG_UINT56 0x07u +#define SL_ZCL_CLI_ARG_UINT64 0x08u +#define SL_ZCL_CLI_ARG_INT8 0x11u +#define SL_ZCL_CLI_ARG_INT16 0x12u +#define SL_ZCL_CLI_ARG_INT24 0x13u +#define SL_ZCL_CLI_ARG_INT32 0x14u +#define SL_ZCL_CLI_ARG_INT40 0x15u +#define SL_ZCL_CLI_ARG_INT48 0x16u +#define SL_ZCL_CLI_ARG_INT56 0x17u +#define SL_ZCL_CLI_ARG_INT64 0x18u +#define SL_ZCL_CLI_ARG_UINT8OPT 0x21u +#define SL_ZCL_CLI_ARG_UINT16OPT 0x22u +#define SL_ZCL_CLI_ARG_UINT24OPT 0x23u +#define SL_ZCL_CLI_ARG_UINT32OPT 0x24u +#define SL_ZCL_CLI_ARG_UINT40OPT 0x25u +#define SL_ZCL_CLI_ARG_UINT48OPT 0x26u +#define SL_ZCL_CLI_ARG_UINT56OPT 0x27u +#define SL_ZCL_CLI_ARG_UINT64OPT 0x28u +#define SL_ZCL_CLI_ARG_INT8OPT 0x31u +#define SL_ZCL_CLI_ARG_INT16OPT 0x32u +#define SL_ZCL_CLI_ARG_INT24OPT 0x33u +#define SL_ZCL_CLI_ARG_INT32OPT 0x34u +#define SL_ZCL_CLI_ARG_INT40OPT 0x35u +#define SL_ZCL_CLI_ARG_INT48OPT 0x36u +#define SL_ZCL_CLI_ARG_INT56OPT 0x37u +#define SL_ZCL_CLI_ARG_INT64OPT 0x38u +#define SL_ZCL_CLI_ARG_STRING 0x41u +#define SL_ZCL_CLI_ARG_HEX 0x42u +#define SL_ZCL_CLI_ARG_STRINGOPT 0x43u +#define SL_ZCL_CLI_ARG_HEXOPT 0x44u +#endif //UC_BUILD + +void zclSimpleCommand(uint8_t frameControl, + uint16_t clusterId, + uint8_t commandId); + +#define zclSimpleClientCommand(clusterId, commandId) \ + zclSimpleCommand(ZCL_CLUSTER_SPECIFIC_COMMAND | ZCL_FRAME_CONTROL_CLIENT_TO_SERVER, \ + (clusterId), \ + (commandId)) + +#define zclSimpleServerCommand(clusterId, commandId) \ + zclSimpleCommand(ZCL_CLUSTER_SPECIFIC_COMMAND | ZCL_FRAME_CONTROL_SERVER_TO_CLIENT, \ + (clusterId), \ + (commandId)) + +#endif // SILABS_ZCL_CLI_H diff --git a/protocol/zigbee/app/framework/common/zigbee_app_framework_common_rtos.c b/protocol/zigbee/app/framework/common/zigbee_app_framework_common_rtos.c index 0a181af2bc..a3a626189e 100644 --- a/protocol/zigbee/app/framework/common/zigbee_app_framework_common_rtos.c +++ b/protocol/zigbee/app/framework/common/zigbee_app_framework_common_rtos.c @@ -34,6 +34,8 @@ #define ZIGBEE_STACK_TASK_PRIORITY SL_ZIGBEE_OS_STACK_TASK_PRIORITY #define ZIGBEE_TASK_YIELD 0x0001U +#define ZIGBEE_TASK_SEMAPHORE_MAX_COUNT 255 +#define ZIGBEE_TASK_SEMAPHORE_INITIAL_COUNT 0 //Zigbee stack size is specified in "word-increments". Multiply by size of void pointer static osThreadId_t zigbee_task_id; @@ -41,12 +43,12 @@ __ALIGNED(8) static uint8_t zigbee_task_stack[SL_ZIGBEE_OS_STACK_TASK_SIZE * siz __ALIGNED(4) static uint8_t zigbee_task_cb[osThreadCbSize]; static osThreadAttr_t zigbee_task_attr; -static osEventFlagsId_t zigbee_task_event_flags_id; -__ALIGNED(4) static uint8_t zigbee_task_event_flags_cb[osEventFlagsCbSize]; -static osEventFlagsAttr_t zigbee_task_event_flags_attr = { - .name = "Zigbee event flags", - .cb_mem = zigbee_task_event_flags_cb, - .cb_size = osEventFlagsCbSize, +static osSemaphoreId_t zigbee_task_semaphore_id; +__ALIGNED(4) static uint8_t zigbee_task_semaphore_cb[osSemaphoreCbSize]; +static osSemaphoreAttr_t zigbee_task_semaphore_attr = { + .name = "Zigbee task semphore", + .cb_mem = zigbee_task_semaphore_cb, + .cb_size = osSemaphoreCbSize, .attr_bits = 0 }; @@ -63,8 +65,8 @@ static void zigbee_stack_task_yield(void); void sl_zigbee_common_rtos_wakeup_stack_task(void) { - uint32_t flags = osEventFlagsSet(zigbee_task_event_flags_id, ZIGBEE_TASK_YIELD); - assert((flags & osFlagsError) == 0); + osStatus_t retVal = osSemaphoreRelease(zigbee_task_semaphore_id); + assert(retVal != osErrorParameter); } void sli_zigbee_common_rtos_init_callback(void) @@ -84,8 +86,10 @@ void sli_zigbee_common_rtos_init_callback(void) &zigbee_task_attr); assert(zigbee_task_id != NULL); - zigbee_task_event_flags_id = osEventFlagsNew(&zigbee_task_event_flags_attr); - assert(zigbee_task_event_flags_id != NULL); + zigbee_task_semaphore_id = osSemaphoreNew(ZIGBEE_TASK_SEMAPHORE_MAX_COUNT, + ZIGBEE_TASK_SEMAPHORE_INITIAL_COUNT, + &zigbee_task_semaphore_attr); + assert(zigbee_task_semaphore_id != NULL); } void sli_zigbee_common_rtos_wakeup_isr_callback(void) @@ -142,11 +146,7 @@ static void zigbee_stack_task_yield(void) } if (yield_time_ticks > 0) { - uint32_t flags = osEventFlagsWait(zigbee_task_event_flags_id, - ZIGBEE_TASK_YIELD, - osFlagsWaitAny, - yield_time_ticks); - - assert((flags != osFlagsErrorUnknown) && (flags != osFlagsErrorParameter) && (flags != osFlagsErrorResource)); + osStatus_t retVal = osSemaphoreAcquire(zigbee_task_semaphore_id, yield_time_ms); + assert((retVal != osErrorParameter) && (retVal != osErrorResource)); } } diff --git a/protocol/zigbee/app/framework/component/zigbee_comms_hub_function.slcc b/protocol/zigbee/app/framework/component/zigbee_comms_hub_function.slcc index 1968b27c03..a5a10d5f34 100644 --- a/protocol/zigbee/app/framework/component/zigbee_comms_hub_function.slcc +++ b/protocol/zigbee/app/framework/component/zigbee_comms_hub_function.slcc @@ -87,10 +87,19 @@ template_contribution: group: comms-hub-function name: send handler: emAfPluginCommsHubFunctionCliSend - help: Sends a message. + help: Sends a message with hex payload. argument: - type: hex - type: hex + - name: cli_command + value: + group: comms-hub-function + name: send_string + handler: emAfPluginCommsHubFunctionCliSend + help: Sends a message with string payload. + argument: + - type: hex + - type: string - name: cli_command value: group: comms-hub-function diff --git a/protocol/zigbee/app/framework/component/zigbee_file_descriptor_dispatch.slcc b/protocol/zigbee/app/framework/component/zigbee_file_descriptor_dispatch.slcc index ec96558634..92a41a6d7d 100644 --- a/protocol/zigbee/app/framework/component/zigbee_file_descriptor_dispatch.slcc +++ b/protocol/zigbee/app/framework/component/zigbee_file_descriptor_dispatch.slcc @@ -13,6 +13,7 @@ provides: - name: "zigbee_file_descriptor_dispatch" requires: - name: "device_host" + - name: "cli_threaded_host" include: - path: protocol/zigbee/app/framework/plugin-host/file-descriptor-dispatch file_list: diff --git a/protocol/zigbee/app/framework/component/zigbee_gas_proxy_function.slcc b/protocol/zigbee/app/framework/component/zigbee_gas_proxy_function.slcc index 0756e06c10..b61b9ebc01 100644 --- a/protocol/zigbee/app/framework/component/zigbee_gas_proxy_function.slcc +++ b/protocol/zigbee/app/framework/component/zigbee_gas_proxy_function.slcc @@ -50,34 +50,52 @@ template_contribution: function_name: emAfPluginGasProxyFunctionPreCommandReceivedCallback - name: cluster_service value: - cluster_id: "0x0708" - mfg_id: "NOT_MFG_SPECIFIC" - side: "CLIENT" - service_function: "emAfGasProxyFunctionDeviceManagementClusterClientCommandParse" + cluster_id: "0x0708" + mfg_id: "NOT_MFG_SPECIFIC" + side: "CLIENT" + service_function: "emAfGasProxyFunctionDeviceManagementClusterClientCommandParse" - name: cluster_service value: - cluster_id: "0x0707" - mfg_id: "NOT_MFG_SPECIFIC" - side: "CLIENT" - service_function: "emAfGasProxyFunctionCalendarClusterClientCommandParse" + cluster_id: "0x0707" + mfg_id: "NOT_MFG_SPECIFIC" + side: "CLIENT" + service_function: "emAfGasProxyFunctionCalendarClusterClientCommandParse" - name: cluster_service value: - cluster_id: "0x0700" - mfg_id: "NOT_MFG_SPECIFIC" - side: "CLIENT" - service_function: "emAfGasProxyFunctionPriceClusterClientCommandParse" + cluster_id: "0x0700" + mfg_id: "NOT_MFG_SPECIFIC" + side: "CLIENT" + service_function: "emAfGasProxyFunctionPriceClusterClientCommandParse" - name: cluster_service value: - cluster_id: "0x0703" - mfg_id: "NOT_MFG_SPECIFIC" - side: "CLIENT" - service_function: "emAfGasProxyFunctionMessagingClusterClientCommandParse" + cluster_id: "0x0703" + mfg_id: "NOT_MFG_SPECIFIC" + side: "CLIENT" + service_function: "emAfGasProxyFunctionMessagingClusterClientCommandParse" - name: cluster_service value: - cluster_id: "0x0702" - mfg_id: "NOT_MFG_SPECIFIC" - side: "CLIENT" - service_function: "emAfGasProxyFunctionSimpleMeteringClusterClientCommandParse" + cluster_id: "0x0702" + mfg_id: "NOT_MFG_SPECIFIC" + side: "CLIENT" + service_function: "emAfGasProxyFunctionSimpleMeteringClusterClientCommandParse" + - name: cluster_service + value: + cluster_id: "0x0702" + mfg_id: "NOT_MFG_SPECIFIC" + side: "SERVER" + service_function: "emAfGasProxyFunctionSimpleMeteringClusterServerCommandParse" + - name: cluster_service + value: + cluster_id: "0x0705" + mfg_id: "NOT_MFG_SPECIFIC" + side: "CLIENT" + service_function: "emAfGasProxyFunctionPrepaymentClusterClientCommandParse" + - name: cluster_service + value: + cluster_id: "0x0705" + mfg_id: "NOT_MFG_SPECIFIC" + side: "SERVER" + service_function: "emAfGasProxyFunctionPrepaymentClusterServerCommandParse" - name: cli_group value: group: plugin diff --git a/protocol/zigbee/app/framework/component/zigbee_gateway.slcc b/protocol/zigbee/app/framework/component/zigbee_gateway.slcc index 182d9409a8..4717f37ab9 100644 --- a/protocol/zigbee/app/framework/component/zigbee_gateway.slcc +++ b/protocol/zigbee/app/framework/component/zigbee_gateway.slcc @@ -32,14 +32,14 @@ source: template_contribution: - name: component_catalog value: zigbee_gateway - - name: zigbee_af_callback - value: - callback_type: event_init - function_name: emberAfPluginGatewayInitCallback - name: zigbee_af_callback value: callback_type: init_done function_name: emberAfPluginGatewayInitCallback + - name: zigbee_af_callback + value: + callback_type: tick + function_name: emberAfPluginGatewayTickCallback - name: cli_group value: group: plugin diff --git a/protocol/zigbee/app/framework/component/zigbee_gbcs_gas_meter.slcc b/protocol/zigbee/app/framework/component/zigbee_gbcs_gas_meter.slcc index ffd168a18e..8288d4cf9c 100644 --- a/protocol/zigbee/app/framework/component/zigbee_gbcs_gas_meter.slcc +++ b/protocol/zigbee/app/framework/component/zigbee_gbcs_gas_meter.slcc @@ -26,6 +26,12 @@ include: template_contribution: - name: component_catalog value: zigbee_gbcs_gas_meter + - name: cluster_service + value: + cluster_id: "0x0702" + mfg_id: "NOT_MFG_SPECIFIC" + side: "SERVER" + service_function: "emAfGbcsGasMeterSimpleMeteringClusterServerCommandParse" - name: zigbee_af_callback value: callback_type: event_init diff --git a/protocol/zigbee/app/framework/component/zigbee_meter_mirror.slcc b/protocol/zigbee/app/framework/component/zigbee_meter_mirror.slcc index 71651525f9..9daa1d4351 100644 --- a/protocol/zigbee/app/framework/component/zigbee_meter_mirror.slcc +++ b/protocol/zigbee/app/framework/component/zigbee_meter_mirror.slcc @@ -23,6 +23,12 @@ include: template_contribution: - name: component_catalog value: zigbee_meter_mirror + - name: cluster_service + value: + cluster_id: "0x0702" + mfg_id: "NOT_MFG_SPECIFIC" + side: "CLIENT" + service_function: "emAfMeterMirrorSimpleMeteringClusterClientCommandParse" - name: zigbee_af_callback value: callback_type: init_done diff --git a/protocol/zigbee/app/framework/component/zigbee_meter_snapshot_server.slcc b/protocol/zigbee/app/framework/component/zigbee_meter_snapshot_server.slcc index 4a3a3a913e..a2ab386e7c 100644 --- a/protocol/zigbee/app/framework/component/zigbee_meter_snapshot_server.slcc +++ b/protocol/zigbee/app/framework/component/zigbee_meter_snapshot_server.slcc @@ -51,6 +51,13 @@ template_contribution: - type: uint8 help: The destination endpoint - type: uint32 + help: The earliest time of a snapshot to be published + - type: uint32 + help: The latest time of a snapshot to be published + - type: uint8 + help: Identifies the snapshot to be published + - type: uint32 + help: Select only snapshots that were taken due to a specific cause documentation: docset: zigbee document: zigbee-af-api/meter-snapshot-server diff --git a/protocol/zigbee/app/framework/component/zigbee_price_client.slcc b/protocol/zigbee/app/framework/component/zigbee_price_client.slcc index e5ccc7dcfa..d4792dbe0a 100644 --- a/protocol/zigbee/app/framework/component/zigbee_price_client.slcc +++ b/protocol/zigbee/app/framework/component/zigbee_price_client.slcc @@ -175,7 +175,7 @@ template_contribution: - name: cli_command value: group: consol-bill - name: print + name: print-bill handler: emAfPriceClientCliConsolidatedBillTablePrint help: Prints the entry of the consolidated bill table. argument: @@ -220,7 +220,7 @@ template_contribution: - name: cli_command value: group: cpp-event - name: print + name: print-event handler: emAfPriceClientCliCppEventPrint help: Prints the entry of the CPP event table. argument: diff --git a/protocol/zigbee/app/framework/component/zigbee_sleepy_message_queue.slcc b/protocol/zigbee/app/framework/component/zigbee_sleepy_message_queue.slcc index 6929b900d5..0731096407 100644 --- a/protocol/zigbee/app/framework/component/zigbee_sleepy_message_queue.slcc +++ b/protocol/zigbee/app/framework/component/zigbee_sleepy_message_queue.slcc @@ -22,6 +22,14 @@ include: template_contribution: - name: component_catalog value: zigbee_sleepy_message_queue + - name: zigbee_af_callback + value: + callback_type: event_init + function_name: emberAfPluginSleepyMessageQueueInitCallback + - name: zigbee_af_callback + value: + callback_type: local_data_init + function_name: emberAfPluginSleepyMessageQueueInitCallback - name: cli_group value: group: plugin @@ -33,6 +41,9 @@ template_contribution: name: init handler: emberAfPluginSleepyMessageQueueInitCallback help: Initializes the sleepy message queue. + argument: + - type: uint8 + help: Initialize EVENT (0x00) or LOCAL_DATA (0x01) - name: cli_command value: group: sleepy-message-queue diff --git a/protocol/zigbee/app/framework/component/zigbee_smart_energy_registration.slcc b/protocol/zigbee/app/framework/component/zigbee_smart_energy_registration.slcc index 1c11e4c4dd..02318b455c 100644 --- a/protocol/zigbee/app/framework/component/zigbee_smart_energy_registration.slcc +++ b/protocol/zigbee/app/framework/component/zigbee_smart_energy_registration.slcc @@ -17,7 +17,6 @@ provides: - name: "zigbee_smart_energy_registration" requires: - name: "zigbee_address_table" - - name: "zigbee_test_harness" - name: "zigbee_esi_management" config_file: - path: protocol/zigbee/app/framework/plugin/smart-energy-registration/config/smart-energy-registration-config.h diff --git a/protocol/zigbee/app/framework/component/zigbee_zcl_framework_core.slcc b/protocol/zigbee/app/framework/component/zigbee_zcl_framework_core.slcc index da68c0a212..bdcf7388d5 100644 --- a/protocol/zigbee/app/framework/component/zigbee_zcl_framework_core.slcc +++ b/protocol/zigbee/app/framework/component/zigbee_zcl_framework_core.slcc @@ -102,6 +102,11 @@ include: - path: zcl-framework-core.h condition: - zigbee_ezsp + - path: protocol/zigbee/app/framework/cli + file_list: + - path: zcl-cli.h + condition: + - cli source: - path: protocol/zigbee/app/framework/cli/core-cli.c condition: @@ -421,6 +426,15 @@ template_contribution: group: keys handler: keysPrintCommand help: "Prints all security keys." + - name: cli_command + value: + name: delete + group: keys + handler: keysDeleteCommand + help: "Delete the specified link key index." + argument: + - type: uint8 + help: "index" - name: cli_command value: name: clear diff --git a/protocol/zigbee/app/framework/gen-template/gen-templates.json b/protocol/zigbee/app/framework/gen-template/gen-templates.json index c582a9eb34..bf4b57d03c 100644 --- a/protocol/zigbee/app/framework/gen-template/gen-templates.json +++ b/protocol/zigbee/app/framework/gen-template/gen-templates.json @@ -11,7 +11,7 @@ "shareClusterStatesAcrossEndpoints": "true" } }, - "requiredFeatureLevel": 70, + "requiredFeatureLevel": 74, "templates": [ { "path": "zap-id.zapt", @@ -100,4 +100,4 @@ } } } -} +} \ No newline at end of file diff --git a/protocol/zigbee/app/framework/gen-template/zap-cli.zapt b/protocol/zigbee/app/framework/gen-template/zap-cli.zapt index 45fdc25e2a..6fc945a374 100644 --- a/protocol/zigbee/app/framework/gen-template/zap-cli.zapt +++ b/protocol/zigbee/app/framework/gen-template/zap-cli.zapt @@ -23,6 +23,7 @@ #include "sl_cli_config.h" #include "sl_cli_command.h" #include "sl_cli.h" +#include "zcl-cli.h" #ifdef SL_CATALOG_ZIGBEE_DEBUG_PRINT_PRESENT #include "sl_zigbee_debug_print.h" #endif // SL_CATALOG_ZIGBEE_DEBUG_PRINT_PRESENT @@ -80,7 +81,7 @@ SL_CLI_COMMAND(sli_zigbee_cli_zcl_{{cleanse_label ../clusterName}}_{{cleanse_lab {{/template_options}} "{{trim_string description}}", {{#zcl_command_arguments}}"{{as_spaced_lowercase label}}" SL_CLI_UNIT_SEPARATOR {{#last}},{{/last}}{{/zcl_command_arguments}} - {{~#if_command_args_exist id}}{{else}}"",{{/if_command_args_exist}} + {{~#if (is_number_greater_than commandArgCount 0)}}{{else}}"",{{/if}} { {{#zcl_command_arguments}} {{zcl_command_argument_type_to_cli_data_type type struct="SL_CLI_ARG_HEX"}}, @@ -176,7 +177,7 @@ WEAK(void sli_zigbee_cli_zcl_{{cleanse_label ../clusterName}}_{{cleanse_label (a {{/template_options}} {{~#zcl_command_arguments~}} {{~#first~}}{{~indent 1}}uint8_t argumentTypes[{{zcl_command_arguments_count parent.id}}] = { {{new_line 1}}{{/first}} - {{~indent 2}}{{zcl_command_argument_type_to_cli_data_type type struct="SL_CLI_ARG_HEX"}}{{~#not_last~}},{{/not_last}} + {{~indent 2}}{{zcl_command_argument_type_to_zcl_cli_data_type type}}{{~#not_last~}},{{/not_last}} {{~#last~}}{{new_line 1}} }; {{/last}} {{/zcl_command_arguments}} {{~indent 1}}sli_zigbee_zcl_simple_command( @@ -184,7 +185,7 @@ WEAK(void sli_zigbee_cli_zcl_{{cleanse_label ../clusterName}}_{{cleanse_label (a ZCL_{{clusterDefine}}_ID, \ {{code}}, \ arguments, \ - {{#if_command_args_exist this.id}}argumentTypes{{else}}NULL{{/if_command_args_exist}}); + {{#if (is_number_greater_than commandArgCount 0)}}argumentTypes{{else}}NULL{{/if}}); } {{/all_cli_commands_for_user_enabled_clusters}} diff --git a/protocol/zigbee/app/framework/gen-template/zap-command.zapt b/protocol/zigbee/app/framework/gen-template/zap-command.zapt index 1d99422301..b45e99b385 100644 --- a/protocol/zigbee/app/framework/gen-template/zap-command.zapt +++ b/protocol/zigbee/app/framework/gen-template/zap-command.zapt @@ -56,7 +56,7 @@ emberAfFillExternalBuffer((ZCL_GLOBAL_COMMAND \ | ZCL_FRAME_CONTROL_SERVER_TO_CLIENT {{#is_command_default_response_disabled .}} | ZCL_DISABLE_DEFAULT_RESPONSE_MASK{{/is_command_default_response_disabled}}), \ clusterId, \ ZCL_{{as_delimited_macro label}}_COMMAND_ID, \ - "{{#zcl_command_arguments}}{{as_underlying_zcl_type type array="b" one_byte="u" two_byte="v" three_byte="x" four_byte="w" short_string="s" long_string="l" ten_byte="A" eleven_byte="B" twelve_byte="C" thirten_byte="D" fourteen_byte="E" fifteen_byte="F" sixteen_byte="G" struct="b" defaul="b" zclCharFormatter="true"}}{{/zcl_command_arguments}}"{{#if_command_args_exist this.id}},{{/if_command_args_exist}} \ + "{{#zcl_command_arguments}}{{as_underlying_zcl_type type array="b" one_byte="u" two_byte="v" three_byte="x" four_byte="w" short_string="s" long_string="l" ten_byte="A" eleven_byte="B" twelve_byte="C" thirten_byte="D" fourteen_byte="E" fifteen_byte="F" sixteen_byte="G" struct="b" defaul="b" zclCharFormatter="true"}}{{/zcl_command_arguments}}"{{#if (is_number_greater_than commandArgCount 0)}},{{/if}} \ {{#zcl_command_arguments}} {{#if isArray}} {{name}}, {{name}}Len{{#not_last}},{{/not_last~}} @@ -85,7 +85,7 @@ emberAfFillExternalBuffer((ZCL_GLOBAL_COMMAND \ | ZCL_FRAME_CONTROL_CLIENT_TO_SERVER{{#is_command_default_response_disabled .}} | ZCL_DISABLE_DEFAULT_RESPONSE_MASK{{/is_command_default_response_disabled}}), \ clusterId, \ ZCL_{{as_delimited_macro label}}_COMMAND_ID, \ - "{{#zcl_command_arguments}}{{as_underlying_zcl_type type array="b" one_byte="u" two_byte="v" three_byte="x" four_byte="w" short_string="s" long_string="l" ten_byte="A" eleven_byte="B" twelve_byte="C" thirten_byte="D" fourteen_byte="E" fifteen_byte="F" sixteen_byte="G" struct="b" defaul="b" zclCharFormatter="true"}}{{/zcl_command_arguments}}"{{#if_command_args_exist this.id}},{{/if_command_args_exist}} \ + "{{#zcl_command_arguments}}{{as_underlying_zcl_type type array="b" one_byte="u" two_byte="v" three_byte="x" four_byte="w" short_string="s" long_string="l" ten_byte="A" eleven_byte="B" twelve_byte="C" thirten_byte="D" fourteen_byte="E" fifteen_byte="F" sixteen_byte="G" struct="b" defaul="b" zclCharFormatter="true"}}{{/zcl_command_arguments}}"{{#if (is_number_greater_than commandArgCount 0)}},{{/if}} \ {{#zcl_command_arguments}} {{#if isArray}} {{name}}, {{name}}Len{{#not_last}},{{/not_last~}} @@ -116,7 +116,7 @@ emberAfFillExternalBuffer((ZCL_GLOBAL_COMMAND \ | ZCL_FRAME_CONTROL_CLIENT_TO_SERVER{{#is_command_default_response_disabled .}} | ZCL_DISABLE_DEFAULT_RESPONSE_MASK{{/is_command_default_response_disabled}}), \ clusterId, \ ZCL_{{as_delimited_macro label}}_COMMAND_ID, \ - "{{#zcl_command_arguments}}{{as_underlying_zcl_type type array="b" one_byte="u" two_byte="v" three_byte="x" four_byte="w" short_string="s" long_string="l" ten_byte="A" eleven_byte="B" twelve_byte="C" thirten_byte="D" fourteen_byte="E" fifteen_byte="F" sixteen_byte="G" struct="b" defaul="b" zclCharFormatter="true"}}{{/zcl_command_arguments}}"{{#if_command_args_exist this.id}},{{/if_command_args_exist}} \ + "{{#zcl_command_arguments}}{{as_underlying_zcl_type type array="b" one_byte="u" two_byte="v" three_byte="x" four_byte="w" short_string="s" long_string="l" ten_byte="A" eleven_byte="B" twelve_byte="C" thirten_byte="D" fourteen_byte="E" fifteen_byte="F" sixteen_byte="G" struct="b" defaul="b" zclCharFormatter="true"}}{{/zcl_command_arguments}}"{{#if (is_number_greater_than commandArgCount 0)}},{{/if}} \ {{#zcl_command_arguments}} {{#if isArray}} {{name}}, {{name}}Len{{#not_last}},{{/not_last~}} @@ -138,7 +138,7 @@ emberAfFillExternalBuffer((ZCL_GLOBAL_COMMAND \ | ZCL_FRAME_CONTROL_SERVER_TO_CLIENT{{#is_command_default_response_disabled .}} | ZCL_DISABLE_DEFAULT_RESPONSE_MASK{{/is_command_default_response_disabled}}), \ clusterId, \ ZCL_{{as_delimited_macro label}}_COMMAND_ID, \ - "{{#zcl_command_arguments}}{{as_underlying_zcl_type type array="b" one_byte="u" two_byte="v" three_byte="x" four_byte="w" short_string="s" long_string="l" ten_byte="A" eleven_byte="B" twelve_byte="C" thirten_byte="D" fourteen_byte="E" fifteen_byte="F" sixteen_byte="G" struct="b" defaul="b" zclCharFormatter="true"}}{{/zcl_command_arguments}}"{{#if_command_args_exist this.id}},{{/if_command_args_exist}} \ + "{{#zcl_command_arguments}}{{as_underlying_zcl_type type array="b" one_byte="u" two_byte="v" three_byte="x" four_byte="w" short_string="s" long_string="l" ten_byte="A" eleven_byte="B" twelve_byte="C" thirten_byte="D" fourteen_byte="E" fifteen_byte="F" sixteen_byte="G" struct="b" defaul="b" zclCharFormatter="true"}}{{/zcl_command_arguments}}"{{#if (is_number_greater_than commandArgCount 0)}},{{/if}} \ {{#zcl_command_arguments}} {{#if isArray}} {{name}}, {{name}}Len{{#not_last}},{{/not_last~}} @@ -174,14 +174,14 @@ emberAfFillExternalBuffer((ZCL_GLOBAL_COMMAND \ {{name}}{{#not_last}},{{/not_last~}} {{/if~}} {{/zcl_command_arguments}}) \ -emberAfFillExternal{{#if_mfg_specific_cluster ../id}}ManufacturerSpecific{{/if_mfg_specific_cluster}}Buffer((ZCL_CLUSTER_SPECIFIC_COMMAND{{#if_mfg_specific_cluster ../id}} | ZCL_MANUFACTURER_SPECIFIC_MASK{{/if_mfg_specific_cluster}} \ +emberAfFillExternal{{#if ../manufacturerCode}}ManufacturerSpecific{{/if}}Buffer((ZCL_CLUSTER_SPECIFIC_COMMAND{{#if ../manufacturerCode}} | ZCL_MANUFACTURER_SPECIFIC_MASK{{/if}} \ | ZCL_FRAME_CONTROL_SERVER_TO_CLIENT{{#is_command_default_response_disabled .}} | ZCL_DISABLE_DEFAULT_RESPONSE_MASK{{/is_command_default_response_disabled}}), \ ZCL_{{as_delimited_macro ../define}}_ID, {{backslash}}{{new_line 1}} - {{~#if_mfg_specific_cluster ../id~}} + {{~#if ../manufacturerCode~}} {{../manufacturerCode}}, \ - {{/if_mfg_specific_cluster}} + {{/if}} ZCL_{{as_delimited_macro name}}_COMMAND_ID, \ - "{{#zcl_command_arguments}}{{as_underlying_zcl_type type array="b" one_byte="u" two_byte="v" three_byte="x" four_byte="w" short_string="s" long_string="l" ten_byte="A" eleven_byte="B" twelve_byte="C" thirten_byte="D" fourteen_byte="E" fifteen_byte="F" sixteen_byte="G" struct="b" defaul="b" zclCharFormatter="true"}}{{/zcl_command_arguments}}"{{#if_command_args_exist this.id}},{{/if_command_args_exist}} \ + "{{#zcl_command_arguments}}{{as_underlying_zcl_type type array="b" one_byte="u" two_byte="v" three_byte="x" four_byte="w" short_string="s" long_string="l" ten_byte="A" eleven_byte="B" twelve_byte="C" thirten_byte="D" fourteen_byte="E" fifteen_byte="F" sixteen_byte="G" struct="b" defaul="b" zclCharFormatter="true"}}{{/zcl_command_arguments}}"{{#if (is_number_greater_than commandArgCount 0)}},{{/if}} \ {{#zcl_command_arguments}} {{#if isArray}} {{name}}, {{name}}Len{{#not_last}},{{/not_last~}} @@ -205,14 +205,14 @@ emberAfFillExternal{{#if_mfg_specific_cluster ../id}}ManufacturerSpecific{{/if_m {{name}}{{#not_last}},{{/not_last~}} {{/if~}} {{/zcl_command_arguments}}) \ -emberAfFillExternal{{#if_mfg_specific_cluster ../id}}ManufacturerSpecific{{/if_mfg_specific_cluster}}Buffer((ZCL_CLUSTER_SPECIFIC_COMMAND{{#if_mfg_specific_cluster ../id}} | ZCL_MANUFACTURER_SPECIFIC_MASK{{/if_mfg_specific_cluster}} \ +emberAfFillExternal{{#if ../manufacturerCode}}ManufacturerSpecific{{/if}}Buffer((ZCL_CLUSTER_SPECIFIC_COMMAND{{#if ../manufacturerCode}} | ZCL_MANUFACTURER_SPECIFIC_MASK{{/if}} \ | ZCL_FRAME_CONTROL_CLIENT_TO_SERVER{{#is_command_default_response_disabled .}} | ZCL_DISABLE_DEFAULT_RESPONSE_MASK{{/is_command_default_response_disabled}}), \ ZCL_{{as_delimited_macro ../define}}_ID, {{backslash}}{{new_line 1}} - {{~#if_mfg_specific_cluster ../id~}} + {{~#if ../manufacturerCode~}} {{../manufacturerCode}}, \ - {{/if_mfg_specific_cluster}} + {{/if}} ZCL_{{as_delimited_macro name}}_COMMAND_ID, \ - "{{#zcl_command_arguments}}{{as_underlying_zcl_type type array="b" one_byte="u" two_byte="v" three_byte="x" four_byte="w" short_string="s" long_string="l" ten_byte="A" eleven_byte="B" twelve_byte="C" thirten_byte="D" fourteen_byte="E" fifteen_byte="F" sixteen_byte="G" struct="b" defaul="b" zclCharFormatter="true"}}{{/zcl_command_arguments}}"{{#if_command_args_exist this.id}},{{/if_command_args_exist}} \ + "{{#zcl_command_arguments}}{{as_underlying_zcl_type type array="b" one_byte="u" two_byte="v" three_byte="x" four_byte="w" short_string="s" long_string="l" ten_byte="A" eleven_byte="B" twelve_byte="C" thirten_byte="D" fourteen_byte="E" fifteen_byte="F" sixteen_byte="G" struct="b" defaul="b" zclCharFormatter="true"}}{{/zcl_command_arguments}}"{{#if (is_number_greater_than commandArgCount 0)}},{{/if}} \ {{#zcl_command_arguments}} {{#if isArray}} {{name}}, {{name}}Len{{#not_last}},{{/not_last~}} @@ -238,14 +238,14 @@ emberAfFillExternal{{#if_mfg_specific_cluster ../id}}ManufacturerSpecific{{/if_m {{name}}{{#not_last}},{{/not_last~}} {{/if~}} {{/zcl_command_arguments}}) \ -emberAfFillExternal{{#if_mfg_specific_cluster ../id}}ManufacturerSpecific{{/if_mfg_specific_cluster}}Buffer((ZCL_CLUSTER_SPECIFIC_COMMAND{{#if_mfg_specific_cluster ../id}} | ZCL_MANUFACTURER_SPECIFIC_MASK{{/if_mfg_specific_cluster}} \ +emberAfFillExternal{{#if ../manufacturerCode}}ManufacturerSpecific{{/if}}Buffer((ZCL_CLUSTER_SPECIFIC_COMMAND{{#if ../manufacturerCode}} | ZCL_MANUFACTURER_SPECIFIC_MASK{{/if}} \ | ZCL_FRAME_CONTROL_CLIENT_TO_SERVER{{#is_command_default_response_disabled .}} | ZCL_DISABLE_DEFAULT_RESPONSE_MASK{{/is_command_default_response_disabled}}), \ ZCL_{{as_delimited_macro ../define}}_ID, {{backslash}}{{new_line 1}} - {{~#if_mfg_specific_cluster ../id~}} + {{~#if ../manufacturerCode~}} {{../manufacturerCode}}, \ - {{/if_mfg_specific_cluster}} + {{/if}} ZCL_{{as_delimited_macro name}}_COMMAND_ID, \ - "{{#zcl_command_arguments}}{{as_underlying_zcl_type type array="b" one_byte="u" two_byte="v" three_byte="x" four_byte="w" short_string="s" long_string="l" ten_byte="A" eleven_byte="B" twelve_byte="C" thirten_byte="D" fourteen_byte="E" fifteen_byte="F" sixteen_byte="G" struct="b" defaul="b" zclCharFormatter="true"}}{{/zcl_command_arguments}}"{{#if_command_args_exist this.id}},{{/if_command_args_exist}} \ + "{{#zcl_command_arguments}}{{as_underlying_zcl_type type array="b" one_byte="u" two_byte="v" three_byte="x" four_byte="w" short_string="s" long_string="l" ten_byte="A" eleven_byte="B" twelve_byte="C" thirten_byte="D" fourteen_byte="E" fifteen_byte="F" sixteen_byte="G" struct="b" defaul="b" zclCharFormatter="true"}}{{/zcl_command_arguments}}"{{#if (is_number_greater_than commandArgCount 0)}},{{/if}} \ {{#zcl_command_arguments}} {{#if isArray}} {{name}}, {{name}}Len{{#not_last}},{{/not_last~}} @@ -263,14 +263,14 @@ emberAfFillExternal{{#if_mfg_specific_cluster ../id}}ManufacturerSpecific{{/if_m {{name}}{{#not_last}},{{/not_last~}} {{/if~}} {{/zcl_command_arguments}}) \ -emberAfFillExternal{{#if_mfg_specific_cluster ../id}}ManufacturerSpecific{{/if_mfg_specific_cluster}}Buffer((ZCL_CLUSTER_SPECIFIC_COMMAND{{#if_mfg_specific_cluster ../id}} | ZCL_MANUFACTURER_SPECIFIC_MASK{{/if_mfg_specific_cluster}} \ +emberAfFillExternal{{#if ../manufacturerCode}}ManufacturerSpecific{{/if}}Buffer((ZCL_CLUSTER_SPECIFIC_COMMAND{{#if ../manufacturerCode}} | ZCL_MANUFACTURER_SPECIFIC_MASK{{/if}} \ | ZCL_FRAME_CONTROL_SERVER_TO_CLIENT{{#is_command_default_response_disabled .}} | ZCL_DISABLE_DEFAULT_RESPONSE_MASK{{/is_command_default_response_disabled}}), \ ZCL_{{as_delimited_macro ../define}}_ID, {{backslash}}{{new_line 1}} - {{~#if_mfg_specific_cluster ../id~}} + {{~#if ../manufacturerCode~}} {{../manufacturerCode}}, \ - {{/if_mfg_specific_cluster}} + {{/if}} ZCL_{{as_delimited_macro name}}_COMMAND_ID, \ - "{{#zcl_command_arguments}}{{as_underlying_zcl_type type array="b" one_byte="u" two_byte="v" three_byte="x" four_byte="w" short_string="s" long_string="l" ten_byte="A" eleven_byte="B" twelve_byte="C" thirten_byte="D" fourteen_byte="E" fifteen_byte="F" sixteen_byte="G" struct="b" defaul="b" zclCharFormatter="true"}}{{/zcl_command_arguments}}"{{#if_command_args_exist this.id}},{{/if_command_args_exist}} \ + "{{#zcl_command_arguments}}{{as_underlying_zcl_type type array="b" one_byte="u" two_byte="v" three_byte="x" four_byte="w" short_string="s" long_string="l" ten_byte="A" eleven_byte="B" twelve_byte="C" thirten_byte="D" fourteen_byte="E" fifteen_byte="F" sixteen_byte="G" struct="b" defaul="b" zclCharFormatter="true"}}{{/zcl_command_arguments}}"{{#if (is_number_greater_than commandArgCount 0)}},{{/if}} \ {{#zcl_command_arguments}} {{#if isArray}} {{name}}, {{name}}Len{{#not_last}},{{/not_last~}} diff --git a/protocol/zigbee/app/framework/gen-template/zap-config.zapt b/protocol/zigbee/app/framework/gen-template/zap-config.zapt index dfd397943c..8552804715 100644 --- a/protocol/zigbee/app/framework/gen-template/zap-config.zapt +++ b/protocol/zigbee/app/framework/gen-template/zap-config.zapt @@ -11,58 +11,65 @@ // binary blob. All attribute values with size greater than 2 bytes. Excluding 0 // values and externally saved values. Separate block is generated for // big-endian and little-endian cases.{{new_line 1}} -{{~#all_user_cluster_attributes_for_generated_defaults~}} -{{#first}}#define GENERATED_DEFAULTS_COUNT ({{count}}){{new_line 1}}{{/first}} -{{~else}} -#define GENERATED_DEFAULTS_COUNT (0) -{{/all_user_cluster_attributes_for_generated_defaults}} +{{#all_user_cluster_attributes_for_generated_defaults}} +{{#first}} +#define GENERATED_DEFAULTS_COUNT ({{count}}){{new_line 1}} #if BIGENDIAN_CPU #define GENERATED_DEFAULTS { {{backslash}} -{{#all_user_cluster_attributes_for_generated_defaults}} +{{/first}} {{#if isString}} {{~indent 1}}{{format_zcl_string_as_characters_for_generated_defaults defaultValue attributeSize}}/* {{arrayIndex}}{{#first}}0{{/first}},{{attributeValueType}} value for cluster: {{clusterName}}, attribute: {{name}}, side: {{side}} */ {{backslash}} {{else}} {{~indent 1}}{{as_generated_default_macro defaultValue attributeSize endian="big"}} /* {{arrayIndex}}{{#first}}0{{/first}},{{attributeValueType}} value for cluster: {{clusterName}}, attribute: {{name}}, side: {{side}} */ {{backslash}} {{/if}} -{{/all_user_cluster_attributes_for_generated_defaults}} +{{#last}} } +{{/last}} +{{/all_user_cluster_attributes_for_generated_defaults}} +{{#all_user_cluster_attributes_for_generated_defaults}} +{{#first}} #else //!BIGENDIAN_CPU #define GENERATED_DEFAULTS { {{backslash}} -{{#all_user_cluster_attributes_for_generated_defaults}} +{{/first}} {{#if isString}} {{~indent 1}}{{format_zcl_string_as_characters_for_generated_defaults defaultValue attributeSize}}/* {{arrayIndex}}{{#first}}0{{/first}},{{attributeValueType}} value for cluster: {{clusterName}}, attribute: {{name}}, side: {{side}} */ {{backslash}} {{else}} {{~indent 1}}{{as_generated_default_macro defaultValue attributeSize endian="little"}} /* {{arrayIndex}}{{#first}}0{{/first}},{{attributeValueType}} value for cluster: {{clusterName}}, attribute: {{name}}, side: {{side}} */ {{backslash}} {{/if}} -{{/all_user_cluster_attributes_for_generated_defaults}} +{{#last}} } #endif +{{/last}} +{{~else}} +#define GENERATED_DEFAULTS_COUNT (0) +#define GENERATED_DEFAULTS { } +{{/all_user_cluster_attributes_for_generated_defaults}} // This is an array of EmberAfAttributeMinMaxValue structures.{{new_line 1}} -{{~#all_user_cluster_attributes_min_max_defaults~}} - {{~#first~}}#define GENERATED_MIN_MAX_DEFAULT_COUNT ({{count}}){{new_line 1}}{{/first}} -{{~else~}} - #define GENERATED_MIN_MAX_DEFAULT_COUNT (0) -{{/all_user_cluster_attributes_min_max_defaults}} -#define GENERATED_MIN_MAX_DEFAULTS { {{backslash}} {{#all_user_cluster_attributes_min_max_defaults}} + {{#first}} +#define GENERATED_MIN_MAX_DEFAULT_COUNT ({{count}}){{new_line 1}} +#define GENERATED_MIN_MAX_DEFAULTS { {{backslash}} + {{/first}} {{~indent 1}}{ {{backslash}}{{new_line 1}} {{~indent 2}}{{generated_default_index ./clusterName ./name ./side 'DEFAULT' ./defaultValue '(uint8_t*)&(generatedDefaults[' '])'}}, /* Cluster: {{clusterName}}, Attribute Default Value: {{name}} interval */ {{backslash}}{{new_line 1}} {{~indent 2}}{{generated_default_index ./clusterName ./name ./side 'MINIMUM' ./attributeMinValue '(uint8_t*)&(generatedDefaults[' '])'}}, /* Cluster: {{clusterName}}, Attribute Minimum Value: {{name}} interval */ {{backslash}}{{new_line 1}} {{~indent 2}}{{generated_default_index ./clusterName ./name ./side 'MAXIMUM' ./attributeMaxValue '(uint8_t*)&(generatedDefaults[' '])'}} /* Cluster: {{clusterName}}, Attribute Maximum Value: {{name}} interval */ {{backslash}}{{new_line 1}} {{~indent 1}} }{{~#not_last~}}, {{/not_last}}{{backslash}} + {{#last}} }{{new_line 2}} {{/last}} + {{~else~}} + #define GENERATED_MIN_MAX_DEFAULT_COUNT (0) + #define GENERATED_MIN_MAX_DEFAULTS { } {{/all_user_cluster_attributes_min_max_defaults}} -}{{new_line 2}} -{{~#all_user_cluster_generated_attributes~}} - {{~#first~}}#define GENERATED_ATTRIBUTE_COUNT ({{count}}){{new_line 1}}{{/first}} - {{~else}} - #define GENERATED_ATTRIBUTE_COUNT (0) -{{/all_user_cluster_generated_attributes}} + +{{#all_user_cluster_generated_attributes}} + {{#first}} +#define GENERATED_ATTRIBUTE_COUNT ({{count}}){{new_line 1}} // This is an array of EmberAfAttributeMetadata structures. #define GENERATED_ATTRIBUTES { {{backslash}} -{{#all_user_cluster_generated_attributes}} + {{/first}} {{#if isAttributeBounded}} {{~indent 1}}{ {{as_hex code 4}}, ZCL_{{as_delimited_macro type}}_ATTRIBUTE_TYPE, {{attributeSize}}, ({{attribute_mask isWritable storageOption isAttributeBounded mfgCode clusterCode side isSingleton 'ATTRIBUTE_MASK_' ''}}), { (uint8_t*)&(minMaxDefaults[{{generated_attribute_min_max_index clusterName name side}}]) } }{{#not_last}},{{/not_last}} /* {{index}} Cluster: {{clusterName}}, Attribute: {{name}}, Side: {{side}}*/ {{backslash}} {{else if (is_number_greater_than attributeSize 2)}} @@ -70,69 +77,69 @@ {{else}} {{~indent 1}}{ {{as_hex code 4}}, ZCL_{{as_delimited_macro type}}_ATTRIBUTE_TYPE, {{attributeSize}}, ({{attribute_mask isWritable storageOption isAttributeBounded mfgCode clusterCode side isSingleton 'ATTRIBUTE_MASK_' ''}}), { (uint8_t*){{#if defaultValue}}{{defaultValue}}{{else}}0x00{{/if}} } }{{#not_last}},{{/not_last}} /* {{index}} Cluster: {{clusterName}}, Attribute: {{name}}, Side: {{side}}*/ {{backslash}} {{/if}} + {{#last}} }{{new_line 2}} {{/last}} + {{~else}} + #define GENERATED_ATTRIBUTE_COUNT (0) + #define GENERATED_ATTRIBUTES { } {{/all_user_cluster_generated_attributes}} -}{{new_line 2}} -{{~#generated_clustes_details~}} -{{~#first~}}#define GENERATED_CLUSTER_COUNT ({{count}}){{new_line 1}}{{/first}} -{{~else~}} -#define GENERATED_CLUSTER_COUNT (0) -{{/generated_clustes_details}} +{{#generated_clustes_details}} + {{#first}} +#define GENERATED_CLUSTER_COUNT ({{count}}){{new_line 1}} // This is an array of EmberAfCluster structures. #define GENERATED_CLUSTERS { {{backslash}} -{{#generated_clustes_details}} + {{/first}} {{~indent 1}}{ {{as_hex clusterCode 4}}, (EmberAfAttributeMetadata*)&(generatedAttributes[{{#all_user_cluster_generated_attributes}}{{#if (is_lowercase_equal ./clusterName ../clusterName)}}{{#if (is_num_equal ./clusterIndex 1)}}{{#if (is_lowercase_equal ./clusterSide ../clusterSide)}}{{index}}{{/if}}{{/if}}{{/if}}{{/all_user_cluster_generated_attributes}}]), {{attributeCount}}, {{attributesSize}}, CLUSTER_MASK_{{as_delimited_macro side}}, NULL }{{#not_last}},{{/not_last}} /* {{index}}, Endpoint Id: {{endpointIdentifier}}, Cluster: {{clusterName}}, Side: {{side}}*/ {{backslash}} + {{#last}} }{{new_line 2}} {{/last}} + {{~else~}} +#define GENERATED_CLUSTER_COUNT (0) +#define GENERATED_CLUSTERS { } {{/generated_clustes_details}} -}{{new_line 2}} -{{~#generated_endpoint_type_details~}} - {{~#first~}} +{{#generated_endpoint_type_details}} + {{#first}} #define GENERATED_ENDPOINT_TYPE_COUNT ({{count}}) - {{/first}} - {{~else~}} -#define GENERATED_ENDPOINT_TYPE_COUNT (0) -{{/generated_endpoint_type_details}} + // This is an array of EmberAfEndpointType structures. #define GENERATED_ENDPOINT_TYPES { {{backslash}} -{{#generated_endpoint_type_details}} + {{/first}} {{~indent 1}}{ ((EmberAfCluster*)&(generatedClusters[{{#generated_clustes_details}}{{#if (is_num_equal ./endpointIdentifier ../endpointIdentifier)}}{{#if (is_num_equal ./endpointIndex 1)}}{{#if (is_num_equal ./endpointTypeId ../endpointTypeId)}}{{./index}}{{/if}}{{/if}}{{/if}}{{/generated_clustes_details}}])), {{clusterCount}}, {{attributesSize}} }, {{backslash}} + {{#last}} } {{/last}} + {{~else~}} +#define GENERATED_ENDPOINT_TYPE_COUNT (0) +#define GENERATED_ENDPOINT_TYPES { } {{/generated_endpoint_type_details}} -} -// Largest attribute size is needed for various buffers {{#all_user_cluster_generated_attributes}} - {{#first}} +{{~#first}} +// Largest attribute size is needed for various buffers #define ATTRIBUTE_LARGEST ({{maxAttributeSize}}) - {{/first}} - {{~else}} -#define ATTRIBUTE_LARGEST (1) -{{/all_user_cluster_generated_attributes}} // Total size of singleton attributes -{{#all_user_cluster_generated_attributes}} -{{~#first}} #define ATTRIBUTE_SINGLETONS_SIZE ({{singletonAttributeSize}}) {{/first}} {{~else}} +// Largest attribute size is needed for various buffers +#define ATTRIBUTE_LARGEST (1) + +// Total size of singleton attributes #define ATTRIBUTE_SINGLETONS_SIZE (0) {{/all_user_cluster_generated_attributes}} -// Total size of attribute storage {{#generated_endpoint_type_details}} {{#first}} +// Total size of attribute storage #define ATTRIBUTE_MAX_SIZE ({{totalAttributeSizeAcrossEndpoints}}) - {{/first}} - {{~else}} -#define ATTRIBUTE_MAX_SIZE (0) -{{/generated_endpoint_type_details}} -// Number of fixed endpoints -{{#generated_endpoint_type_details}} - {{#first}} +// Number of fixed endpoints #define FIXED_ENDPOINT_COUNT ({{count}}) {{/first}} {{~else}} +// Total size of attribute storage +#define ATTRIBUTE_MAX_SIZE (0) + +// Number of fixed endpoints #define FIXED_ENDPOINT_COUNT (0) {{/generated_endpoint_type_details}} @@ -183,33 +190,30 @@ // Array of EmberAfCommandMetadata structs. #define ZAP_COMMAND_MASK(mask) COMMAND_MASK_ ## mask {{#all_user_cluster_generated_commands}} - {{~#first~}}#define EMBER_AF_GENERATED_COMMAND_COUNT ({{count}}){{/first}} - {{~else}} - #define EMBER_AF_GENERATED_COMMAND_COUNT (0) -{{/all_user_cluster_generated_commands}} - + {{~#first~}} +#define EMBER_AF_GENERATED_COMMAND_COUNT ({{count}}) #define GENERATED_COMMANDS { {{backslash}} -{{#all_user_cluster_generated_commands}} + {{/first}} + {{~#if (is_num_equal 2 numberOfClusterSidesEnabled)}} {{~indent 1}}{ {{as_hex clusterCode 4}}, {{as_hex commandCode 2}}, {{command_mask commandSource "either" 1 1 commandMfgCode "COMMAND_MASK_"}} }, /* {{index}}, Cluster: {{clusterName}}, Command: {{commandName}}*/ {{backslash}} {{else}} {{~indent 1}}{ {{as_hex clusterCode 4}}, {{as_hex commandCode 2}}, {{command_mask commandSource clusterSide incoming outgoing commandMfgCode "COMMAND_MASK_"}} }, /* {{index}}, Cluster: {{clusterName}}, Command: {{commandName}}*/ {{backslash}} {{/if}} + {{#last}} } {{/last}} + {{~else}} + #define EMBER_AF_GENERATED_COMMAND_COUNT (0) + #define GENERATED_COMMANDS { } {{/all_user_cluster_generated_commands}} -} {{/if_command_discovery_enabled}} {{#if_command_discovery_enabled}} // Array of EmberAfManufacturerCodeEntry structures for commands. {{#all_user_cluster_generated_commands}} {{~#first~}} - #define GENERATED_COMMAND_MANUFACTURER_CODE_COUNT ({{mfgCommandCount}}) - {{/first}} - {{~else}} -#define GENERATED_COMMAND_MANUFACTURER_CODE_COUNT (0) -{{/all_user_cluster_generated_commands}} +#define GENERATED_COMMAND_MANUFACTURER_CODE_COUNT ({{mfgCommandCount}}) #define GENERATED_COMMAND_MANUFACTURER_CODES { {{backslash}} -{{#all_user_cluster_generated_commands}} + {{/first}} {{#unless mfgCommandCount}} {{#first}} {{~indent 1}}{ 0x00, 0x00 } {{backslash}} @@ -218,20 +222,19 @@ {{#if (is_defined commandMfgCode)}} {{~indent 1}}{ {{index}}, {{as_hex commandMfgCode}} }, {{backslash}} {{/if}} + {{#last}} } {{/last}} + {{~else}} +#define GENERATED_COMMAND_MANUFACTURER_CODE_COUNT (0) +#define GENERATED_COMMAND_MANUFACTURER_CODES { } {{/all_user_cluster_generated_commands}} -} {{/if_command_discovery_enabled}} // This is an array of EmberAfManufacturerCodeEntry structures for clusters. {{#generated_clustes_details}} {{#first}} #define GENERATED_CLUSTER_MANUFACTURER_CODE_COUNT ({{mfgClusterCount}}) - {{/first}} - {{~else}} -#define GENERATED_CLUSTER_MANUFACTURER_CODE_COUNT (0) -{{/generated_clustes_details}} #define GENERATED_CLUSTER_MANUFACTURER_CODES { {{backslash}} -{{#generated_clustes_details}} + {{/first}} {{#unless mfgClusterCount}} {{#first}} {{~indent 1}}{ 0x00, 0x00 } {{backslash}} @@ -240,19 +243,18 @@ {{#if (is_defined mfgCode)}} {{~indent 1}}{ {{index}}, {{as_hex mfgCode}} }, {{backslash}} {{/if}} + {{#last}} } {{/last}} + {{~else}} +#define GENERATED_CLUSTER_MANUFACTURER_CODE_COUNT (0) +#define GENERATED_CLUSTER_MANUFACTURER_CODES { } {{/generated_clustes_details}} -} // This is an array of EmberAfManufacturerCodeEntry structures for attributes. {{#all_user_cluster_generated_attributes}} {{#first}} #define GENERATED_ATTRIBUTE_MANUFACTURER_CODE_COUNT ({{mfgAttributeCount}}) - {{/first}} - {{~else}} -#define GENERATED_ATTRIBUTE_MANUFACTURER_CODE_COUNT (0) -{{/all_user_cluster_generated_attributes}} #define GENERATED_ATTRIBUTE_MANUFACTURER_CODES { {{backslash}} -{{#all_user_cluster_generated_attributes}} + {{/first}} {{#unless mfgAttributeCount}} {{#first}} {{~indent 1}}{ 0x00, 0x00 } {{backslash}} @@ -261,22 +263,25 @@ {{#if (is_defined mfgCode)}} {{~indent 1}}{ {{index}}, {{as_hex mfgCode}} }, {{backslash}} {{/if}} + {{#last}} } {{/last}} + {{~else}} +#define GENERATED_ATTRIBUTE_MANUFACTURER_CODE_COUNT (0) +#define GENERATED_ATTRIBUTE_MANUFACTURER_CODES { } {{/all_user_cluster_generated_attributes}} -} // Array of EmberAfPluginReportingEntry structures. {{#all_user_reportable_attributes}} {{#first}} #define EMBER_AF_GENERATED_REPORTING_CONFIG_DEFAULTS_TABLE_SIZE ({{count}}) - {{/first}} - {{~else}} -#define EMBER_AF_GENERATED_REPORTING_CONFIG_DEFAULTS_TABLE_SIZE (0) -{{/all_user_reportable_attributes}} #define EMBER_AF_GENERATED_REPORTING_CONFIG_DEFAULTS { {{backslash}} -{{#all_user_reportable_attributes}} + {{/first}} {{~indent 1}}{ EMBER_ZCL_REPORTING_DIRECTION_REPORTED, {{as_hex endpointIdentifier 4}}, {{as_hex clusterCode 4}}, {{as_hex code 4}}, CLUSTER_MASK_{{as_delimited_macro side}}, {{as_hex mfgCode 4}}, {{attributeReportableMinValue}}, {{attributeReportableMaxValue}}, {{attributeReportableChange}} }, /* Endpoint Id: {{endpointIdentifier}}, Cluster: {{clusterName}}, Attribute: {{name}} */ {{backslash}} + {{#last}} } {{/last}} + {{~else}} +#define EMBER_AF_GENERATED_REPORTING_CONFIG_DEFAULTS_TABLE_SIZE (0) +#define EMBER_AF_GENERATED_REPORTING_CONFIG_DEFAULTS { } {{/all_user_reportable_attributes}} -} + #define EMBER_AF_MANUFACTURER_CODE {{user_manufacturer_code}} #define EMBER_AF_DEFAULT_RESPONSE_POLICY_{{user_default_response_policy toupper="true"}} diff --git a/protocol/zigbee/app/framework/plugin-host/file-descriptor-dispatch/file-descriptor-dispatch.c b/protocol/zigbee/app/framework/plugin-host/file-descriptor-dispatch/file-descriptor-dispatch.c index 4c0d584abc..6304ef8aba 100644 --- a/protocol/zigbee/app/framework/plugin-host/file-descriptor-dispatch/file-descriptor-dispatch.c +++ b/protocol/zigbee/app/framework/plugin-host/file-descriptor-dispatch/file-descriptor-dispatch.c @@ -20,6 +20,7 @@ #include "app/framework/include/af.h" #include "file-descriptor-dispatch.h" +#include "platform/service/cli/inc/sl_cli_threaded_host.h" #include // for malloc() #include // for select() @@ -55,6 +56,13 @@ const char emAfFileDescriptorDispatchPluginName[] = "FD Dispatch"; #define debugPrint(...) #endif +#ifdef EMBER_TEST +// Simulation apps are still using platform/base +// instead of platform/service +#define sli_cli_get_pipe_read_fd() (-1) +#define sli_cli_is_input_handled() (false) +#endif // EMBER_TEST + //============================================================================= // Forward Declarations @@ -205,6 +213,14 @@ static void cleanupItemsMarkedForRemoval(void) } } +static void setCliInFd(int *maxFd, fd_set *readSet, fd_set *errorSet) +{ + int pipeReadFd = sli_cli_get_pipe_read_fd(); + FD_SET(pipeReadFd, readSet); + FD_SET(pipeReadFd, errorSet); + *maxFd = (*maxFd < pipeReadFd ? pipeReadFd : *maxFd); +} + EmberStatus emberAfPluginFileDescriptorDispatchWaitForEvents(uint32_t timeoutMs) { fd_set readSet; @@ -258,6 +274,11 @@ EmberStatus emberAfPluginFileDescriptorDispatchWaitForEvents(uint32_t timeoutMs) } iterator = iterator->next; } + + // Set CLI pipe read fd so that we can wake up the host + // by entering CLI commands. + setCliInFd(&highestFd, &readSet, &exceptSet); + struct timeval timeoutStruct = { timeoutMs / 1000, // seconds (timeoutMs % 1000) * 1000, // micro seconds @@ -274,6 +295,13 @@ EmberStatus emberAfPluginFileDescriptorDispatchWaitForEvents(uint32_t timeoutMs) (timeoutMs != MAX_INT32U_VALUE ? &timeoutStruct : NULL)); + + // If the command is handled by the CLI component, read the data + // to empty the pipe so that it is ready for the next command. + if (sli_cli_is_input_handled()) { + char buff[2]; + read(sli_cli_get_pipe_read_fd(), buff, 2); + } } if (status < 0) { emberAfCorePrintln("%p select() failed: %p", PLUGIN_NAME, strerror(errno)); diff --git a/protocol/zigbee/app/framework/plugin-host/gateway/gateway-support.c b/protocol/zigbee/app/framework/plugin-host/gateway/gateway-support.c index 4f587b52a0..1a7403ef39 100644 --- a/protocol/zigbee/app/framework/plugin-host/gateway/gateway-support.c +++ b/protocol/zigbee/app/framework/plugin-host/gateway/gateway-support.c @@ -42,19 +42,14 @@ //------------------------------------------------------------------------------ // Globals -#if !defined(EMBER_AF_PLUGIN_GATEWAY_SUPPORT_MAX_WAIT_FOR_EVENTS_TIMEOUT_MS) - #define EMBER_AF_PLUGIN_GATEWAY_SUPPORT_MAX_WAIT_FOR_EVENTS_TIMEOUT_MS MAX_INT32U_VALUE -#endif - // If the application wishes to limit how long the select() call will yield // for, they can do it by specifying a max timeout. This may be necessary // if the main() loop expects to be serviced at some regular interval. // Ideally the application code can use an event, but it is easier to // tune it this way. 0xFFFFFFFFUL = no read timeout, thus allowing the // select() call to yield forever if there are no events scheduled. -#define MAX_READ_TIMEOUT_MS EMBER_AF_PLUGIN_GATEWAY_SUPPORT_MAX_WAIT_FOR_EVENTS_TIMEOUT_MS +#define MAX_READ_TIMEOUT_MS EMBER_AF_PLUGIN_GATEWAY_MAX_WAIT_FOR_EVENT_TIMEOUT_MS #define MAX_FDS EMBER_AF_PLUGIN_GATEWAY_MAX_FDS -#define MIN_READ_TIMEOUT_MS 1000 #define INVALID_FD -1 static const char* debugLabel = "gateway-debug"; @@ -144,25 +139,6 @@ static void debugPrintYieldDuration(uint32_t msToNextEvent, uint8_t eventIndex) } #endif // UC_BUILD -#ifdef UC_BUILD -sl_zigbee_event_t emberAfPluginGatewayTickCallbackEvent; -void emberAfPluginGatewayTickCallbackEventHandler(SLXU_UC_EVENT) -{ - sl_zigbee_event_set_delay_ms(&emberAfPluginGatewayTickCallbackEvent, - MIN_READ_TIMEOUT_MS); - uint8_t index; - uint32_t msToNextEvent = emberAfMsToNextEventExtended(0xFFFFFFFFUL, &index); - - SL_IGNORE_TYPE_LIMIT_BEGIN; - msToNextEvent = (msToNextEvent > MAX_READ_TIMEOUT_MS - ? MAX_READ_TIMEOUT_MS - : msToNextEvent); - SL_IGNORE_TYPE_LIMIT_END; - emberAfPluginFileDescriptorDispatchWaitForEvents(msToNextEvent); -} - -#else - void emberAfPluginGatewayTickCallback(void) { // If the CLI process is waiting for the 'go-ahead' to prompt the user @@ -174,75 +150,69 @@ void emberAfPluginGatewayTickCallback(void) uint8_t index; uint32_t msToNextEvent = emberAfMsToNextEventExtended(0xFFFFFFFFUL, &index); +#ifndef UC_BUILD debugPrintYieldDuration(msToNextEvent, index); +#endif msToNextEvent = (msToNextEvent > MAX_READ_TIMEOUT_MS ? MAX_READ_TIMEOUT_MS : msToNextEvent); emberAfPluginFileDescriptorDispatchWaitForEvents(msToNextEvent); } -#endif //#!UC_BUILD void emberAfPluginGatewayInitCallback(SLXU_INIT_ARG) { - #ifdef UC_BUILD - if (init_level == SL_ZIGBEE_INIT_LEVEL_EVENT) { - slxu_zigbee_event_init(&emberAfPluginGatewayTickCallbackEvent, - emberAfPluginGatewayTickCallbackEventHandler); - sl_zigbee_event_set_delay_ms(&emberAfPluginGatewayTickCallbackEvent, - MIN_READ_TIMEOUT_MS); - } else - #endif - { - int fdList[MAX_FDS]; - int count = 0; - int i; - - EmberAfFileDescriptorDispatchStruct dispatchStruct = { - NULL, // callback - NULL, // data passed to callback - EMBER_AF_FILE_DESCRIPTOR_OPERATION_READ, - -1, - }; - dispatchStruct.fileDescriptor = emberSerialGetInputFd(0); - if (dispatchStruct.fileDescriptor != -1 - && EMBER_SUCCESS != emberAfPluginFileDescriptorDispatchAdd(&dispatchStruct)) { - emberAfCorePrintln("Error: Gateway Plugin failed to register serial Port 0 FD"); - } - dispatchStruct.fileDescriptor = emberSerialGetInputFd(1); + int fdList[MAX_FDS]; + int count = 0; + int i; + + EmberAfFileDescriptorDispatchStruct dispatchStruct = { + NULL, // callback + NULL, // data passed to callback + EMBER_AF_FILE_DESCRIPTOR_OPERATION_READ, + -1, + }; + dispatchStruct.fileDescriptor = emberSerialGetInputFd(0); + if (dispatchStruct.fileDescriptor != -1 + && EMBER_SUCCESS != emberAfPluginFileDescriptorDispatchAdd(&dispatchStruct)) { + emberAfCorePrintln("Error: Gateway Plugin failed to register serial Port 0 FD"); + } + dispatchStruct.fileDescriptor = emberSerialGetInputFd(1); #if defined(ZA_CLI_FULL) - if (dispatchStruct.fileDescriptor != -1 - && EMBER_SUCCESS != emberAfPluginFileDescriptorDispatchAdd(&dispatchStruct)) { - emberAfCorePrintln("Error: Gateway Plugin failed to register serial Port 1 FD"); - } + if (dispatchStruct.fileDescriptor != -1 + && EMBER_SUCCESS != emberAfPluginFileDescriptorDispatchAdd(&dispatchStruct)) { + emberAfCorePrintln("Error: Gateway Plugin failed to register serial Port 1 FD"); + } #endif - // For SPI, we need the nHOST_INT line as well - EmberAfFileDescriptorDispatchStruct spiDispatchStruct = { - NULL, // callback - NULL, // data passed to callback - EMBER_AF_FILE_DESCRIPTOR_OPERATION_EXCEPT, - -1, - }; - spiDispatchStruct.fileDescriptor = serialGetSpiFd(); - if (spiDispatchStruct.fileDescriptor != -1 - && EMBER_SUCCESS != emberAfPluginFileDescriptorDispatchAdd(&spiDispatchStruct)) { - emberAfCorePrintln("Error: Gateway Plugin failed to register SPI FD"); - } - ezspSerialPortRegisterCallback(ezspSerialPortCallback); - if (ezspSerialGetFd() != NULL_FILE_DESCRIPTOR) { - ezspSerialPortCallback(EZSP_SERIAL_PORT_OPENED, ezspSerialGetFd()); - } +#ifdef EZSP_SPI + // For SPI, we need the nHOST_INT line as well + EmberAfFileDescriptorDispatchStruct spiDispatchStruct = { + NULL, // callback + NULL, // data passed to callback + EMBER_AF_FILE_DESCRIPTOR_OPERATION_EXCEPT, + -1, + }; + spiDispatchStruct.fileDescriptor = serialGetSpiFd(); + if (spiDispatchStruct.fileDescriptor != -1 + && EMBER_SUCCESS != emberAfPluginFileDescriptorDispatchAdd(&spiDispatchStruct)) { + emberAfCorePrintln("Error: Gateway Plugin failed to register SPI FD"); + } +#endif // EZSP_SPI - MEMSET(fdList, 0xFF, sizeof(int) * MAX_FDS); - count = emberAfPluginGatewaySelectFileDescriptorsCallback(fdList, MAX_FDS); - for (i = 0; i < count; i++) { - dispatchStruct.fileDescriptor = fdList[i]; - if (EMBER_SUCCESS != emberAfPluginFileDescriptorDispatchAdd(&dispatchStruct)) { - emberAfCorePrintln("Error: Gateway plugin failed to add FD %d for watching.", fdList[i]); - } + ezspSerialPortRegisterCallback(ezspSerialPortCallback); + if (ezspSerialGetFd() != NULL_FILE_DESCRIPTOR) { + ezspSerialPortCallback(EZSP_SERIAL_PORT_OPENED, ezspSerialGetFd()); + } + + MEMSET(fdList, 0xFF, sizeof(int) * MAX_FDS); + count = emberAfPluginGatewaySelectFileDescriptorsCallback(fdList, MAX_FDS); + for (i = 0; i < count; i++) { + dispatchStruct.fileDescriptor = fdList[i]; + if (EMBER_SUCCESS != emberAfPluginFileDescriptorDispatchAdd(&dispatchStruct)) { + emberAfCorePrintln("Error: Gateway plugin failed to add FD %d for watching.", fdList[i]); } - } // endof else SL_ZIGBEE_INIT_LEVEL_EVENT + } } static void debugPrint(const char* formatString, ...) diff --git a/protocol/zigbee/app/framework/plugin/address-table/address-table-cli.c b/protocol/zigbee/app/framework/plugin/address-table/address-table-cli.c index f429941ee7..6069c6ae55 100644 --- a/protocol/zigbee/app/framework/plugin/address-table/address-table-cli.c +++ b/protocol/zigbee/app/framework/plugin/address-table/address-table-cli.c @@ -74,7 +74,7 @@ void emberAfPluginAddressTablePrintCommand(sl_cli_command_arg_t *arguments) { uint8_t i; uint8_t used = 0; - sl_zigbee_core_debug_print("# node eui"); + sl_zigbee_core_debug_print("# node eui\n"); for (i = 0; i < emberAfGetAddressTableSize(); i++) { EmberNodeId nodeId = emberGetAddressTableRemoteNodeId(i); if (nodeId != EMBER_TABLE_ENTRY_UNUSED_NODE_ID) { @@ -87,7 +87,7 @@ void emberAfPluginAddressTablePrintCommand(sl_cli_command_arg_t *arguments) emberAfAppFlush(); } } - sl_zigbee_core_debug_print("%d of %d entries used.", + sl_zigbee_core_debug_print("%d of %d entries used.\n", used, emberAfGetAddressTableSize()); } diff --git a/protocol/zigbee/app/framework/plugin/address-table/address-table.c b/protocol/zigbee/app/framework/plugin/address-table/address-table.c index 09a6d93c2b..6f6d42b2a5 100644 --- a/protocol/zigbee/app/framework/plugin/address-table/address-table.c +++ b/protocol/zigbee/app/framework/plugin/address-table/address-table.c @@ -148,7 +148,6 @@ uint8_t emberAfAddAddressTableEntry(EmberEUI64 longId, EmberNodeId shortId) } } else if (index == EMBER_NULL_ADDRESS_TABLE_INDEX) { index = i; - break; } else { // MISRA requires ..else if.. to have terminating else. } diff --git a/protocol/zigbee/app/framework/plugin/basic/basic.c b/protocol/zigbee/app/framework/plugin/basic/basic.c index 657832539b..54f46c928e 100644 --- a/protocol/zigbee/app/framework/plugin/basic/basic.c +++ b/protocol/zigbee/app/framework/plugin/basic/basic.c @@ -17,14 +17,27 @@ #include "af.h" #include "basic.h" - #include "app/framework/util/attribute-storage.h" +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#ifdef SL_CATALOG_ZIGBEE_REPORTING_PRESENT +#include "reporting.h" +#endif // SL_CATALOG_ZIGBEE_REPORTING_PRESENT +#else // !SL_COMPONENT_CATALOG_PRESENT +#ifdef EMBER_AF_PLUGIN_REPORTING +#include "app/framework/plugin/reporting/reporting.h" +#define SL_CATALOG_ZIGBEE_REPORTING_PRESENT +#endif // EMBER_AF_PLUGIN_REPORTING +#endif // SL_COMPONENT_CATALOG_PRESENT bool emberAfBasicClusterResetToFactoryDefaultsCallback(void) { emberAfBasicClusterPrintln("RX: ResetToFactoryDefaultsCallback"); emberAfResetAttributes(emberAfCurrentEndpoint()); emberAfPluginBasicResetToFactoryDefaultsCallback(emberAfCurrentEndpoint()); +#ifdef SL_CATALOG_ZIGBEE_REPORTING_PRESENT + emAfPluginReportingGetLastValueAll(); +#endif // SL_CATALOG_ZIGBEE_REPORTING_PRESENT emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_SUCCESS); return true; } diff --git a/protocol/zigbee/app/framework/plugin/comms-hub-function/comms-hub-function-cli.c b/protocol/zigbee/app/framework/plugin/comms-hub-function/comms-hub-function-cli.c index 29094c844b..702d1dfd01 100644 --- a/protocol/zigbee/app/framework/plugin/comms-hub-function/comms-hub-function-cli.c +++ b/protocol/zigbee/app/framework/plugin/comms-hub-function/comms-hub-function-cli.c @@ -502,11 +502,20 @@ void emAfPluginCommsHubFunctionCliSend(sl_cli_command_arg_t *arguments) EmberEUI64 deviceId; uint8_t length; uint8_t message[255]; + uint8_t* command = sl_zigbee_cli_get_argument_string_and_length(arguments, -1, &length); + sl_zigbee_copy_eui64_arg(arguments, 0, deviceId, true); - length = sl_zigbee_copy_hex_arg(arguments, - 1, - message, - 255, false); + if (command[5] == 's') { + length = sl_zigbee_copy_string_arg(arguments, + 1, + message, + 255, false); + } else { + length = sl_zigbee_copy_hex_arg(arguments, + 1, + message, + 255, false); + } sendMessage(deviceId, length, message, false, TEST_MESSAGE_CODE); } diff --git a/protocol/zigbee/app/framework/plugin/comms-hub-function/comms-hub-function.c b/protocol/zigbee/app/framework/plugin/comms-hub-function/comms-hub-function.c index 0618567274..3dec04fba3 100644 --- a/protocol/zigbee/app/framework/plugin/comms-hub-function/comms-hub-function.c +++ b/protocol/zigbee/app/framework/plugin/comms-hub-function/comms-hub-function.c @@ -782,10 +782,11 @@ static void checkForAnyDeviceThatNeedsTunnelCreated(void) void emberAfPluginCommsHubFunctionStackStatusCallback(EmberStatus status) { if (status != EMBER_NETWORK_UP) { - slxu_zigbee_event_set_inactive(tunnelCheckEventControl); - // Disable - // sToDo: this actually seems wrong, if this needs to be disabled, the following calls actually enable it - //emberAfEventControlSetDelay(&tunnelCheckEventControl, 0); + if (status == EMBER_NETWORK_DOWN) { + slxu_zigbee_event_set_inactive(tunnelCheckEventControl); + } else { + slxu_zigbee_event_set_delay_ms(tunnelCheckEventControl, 0); + } return; } diff --git a/protocol/zigbee/app/framework/plugin/dmp-ui-demo/sl_dmp_ui.c b/protocol/zigbee/app/framework/plugin/dmp-ui-demo/sl_dmp_ui.c index e59fdfd4f2..5323ceffad 100644 --- a/protocol/zigbee/app/framework/plugin/dmp-ui-demo/sl_dmp_ui.c +++ b/protocol/zigbee/app/framework/plugin/dmp-ui-demo/sl_dmp_ui.c @@ -83,6 +83,7 @@ static void dmpUiUpdateZigbeeStatus(DmpUiZigBeeNetworkState_t nwState, { int32_t xPosition = 2; char tempStr[TMP_STR_LEN] = { 0 }; + char *pTempStr = tempStr; if (!helpMenuDisplayed) { EmberPanId panId = emberAfGetPanId(); @@ -117,40 +118,40 @@ static void dmpUiUpdateZigbeeStatus(DmpUiZigBeeNetworkState_t nwState, switch (nwState) { case DMP_UI_NO_NETWORK: dmpUiDirectDisplayStartTime = 0; - strncpy(tempStr, "No Nwk", TMP_STR_LEN); + pTempStr = "No Nwk"; break; case DMP_UI_LOST_NETWORK: dmpUiDirectDisplayStartTime = 0; - strncpy(tempStr, "Lost Nwk", TMP_STR_LEN); // (== on Nwk but No Parent) + pTempStr = "Lost Nwk"; break; case DMP_UI_SCANNING: - strncpy(tempStr, "Scanning", TMP_STR_LEN); + pTempStr = "Scanning"; break; case DMP_UI_JOINING: - strncpy(tempStr, "Joining", TMP_STR_LEN); + pTempStr = "Joining"; break; case DMP_UI_FORMING: - strncpy(tempStr, "Forming", TMP_STR_LEN); + pTempStr = "Forming"; break; case DMP_UI_DISCOVERING: - strncpy(tempStr, "Discvrng", TMP_STR_LEN); + pTempStr = "Discvrng"; break; case DMP_UI_NETWORK_UP: - //Intentionally avoiding snprintf for codespace - strncpy(tempStr, "PAN:", TMP_STR_LEN); - + tempStr[0] = 'P'; + tempStr[1] = 'A'; + tempStr[2] = 'N'; + tempStr[3] = ':'; tempStr[4] = ascii_lut[(panId & 0xF000) >> 12]; tempStr[5] = ascii_lut[(panId & 0x0F00) >> 8]; tempStr[6] = ascii_lut[(panId & 0x00F0) >> 4]; tempStr[7] = ascii_lut[(panId & 0x000F)]; tempStr[8] = '\0'; - break; default: break; } - GLIB_drawString(&glibContext, tempStr, + GLIB_drawString(&glibContext, pTempStr, strlen(tempStr) + 1, xPosition, glibContext.pDisplayGeometry->ySize - 10, 0); if (withDisplayUpdate) { @@ -213,9 +214,7 @@ static void dmpUiDisplayBluetoothLogo(void) static void dmpUiDisplayAppName(const char *device) { - char appName[APP_NAME_LEN]; - - strncpy(appName, "DMP Demo ", APP_NAME_LEN); + char appName[APP_NAME_LEN] = "DMP Demo "; strncpy(&appName[9], device, APP_NAME_LEN - 9); GLIB_drawString(&glibContext, appName, diff --git a/protocol/zigbee/app/framework/plugin/drlc/load-control-event-table-host.c b/protocol/zigbee/app/framework/plugin/drlc/load-control-event-table-host.c index cce6dc7622..11c005e2ac 100644 --- a/protocol/zigbee/app/framework/plugin/drlc/load-control-event-table-host.c +++ b/protocol/zigbee/app/framework/plugin/drlc/load-control-event-table-host.c @@ -19,7 +19,11 @@ #include "load-control-event-table.h" #include "app/framework/security/crypto-state.h" +#ifdef UC_BUILD +void emAfDemandResponseLoadControlClusterDsaSignCallback(EmberStatus status, EmberMessageBuffer message) +#else // !UC_BUILD void ezspDsaSignHandler(EmberStatus status, uint8_t messageLength, uint8_t* message) +#endif // UC_BUILD { // Message has been queued by the stack for sending. Nothing more to do. emAfCryptoOperationComplete(); diff --git a/protocol/zigbee/app/framework/plugin/fragmentation/fragmentation.c b/protocol/zigbee/app/framework/plugin/fragmentation/fragmentation.c index 68e147af0c..d3752944e0 100644 --- a/protocol/zigbee/app/framework/plugin/fragmentation/fragmentation.c +++ b/protocol/zigbee/app/framework/plugin/fragmentation/fragmentation.c @@ -82,8 +82,7 @@ uint8_t emAfPluginFragmentationArtificiallyDropBlockNumber = NO_BLOCK_TO_DROP; #endif -#define messageTag(txPacket) ((txPacket)->sequence) - +#define messageTag(txPacket) ((txPacket)->apsFrame.sequence) //------------------------------------------------------------------------------ // Functions diff --git a/protocol/zigbee/app/framework/plugin/gas-proxy-function/gas-proxy-function.c b/protocol/zigbee/app/framework/plugin/gas-proxy-function/gas-proxy-function.c index f349f63d12..4cb636f4b0 100644 --- a/protocol/zigbee/app/framework/plugin/gas-proxy-function/gas-proxy-function.c +++ b/protocol/zigbee/app/framework/plugin/gas-proxy-function/gas-proxy-function.c @@ -30,7 +30,20 @@ #ifdef UC_BUILD #include "zap-cluster-command-parser.h" -#endif + +extern bool emberAfSimpleMeteringClusterGetNotifiedMessageCallback(EmberAfClusterCommand *cmd); +extern bool emberAfSimpleMeteringClusterGetSampledDataCallback(EmberAfClusterCommand *cmd); +extern bool emberAfSimpleMeteringClusterPublishSnapshotCallback(EmberAfClusterCommand *cmd); +extern bool emberAfSimpleMeteringClusterGetSnapshotCallback(EmberAfClusterCommand *cmd); +extern bool emberAfSimpleMeteringClusterGetSampledDataResponseCallback(EmberAfClusterCommand *cmd); +extern bool emberAfSimpleMeteringClusterGetSampledDataResponseCallback(EmberAfClusterCommand *cmd); +extern bool emberAfPrepaymentClusterPublishPrepaySnapshotCallback(EmberAfClusterCommand *cmd); +extern bool emberAfPrepaymentClusterGetPrepaySnapshotCallback(EmberAfClusterCommand *cmd); +extern bool emberAfPrepaymentClusterPublishTopUpLogCallback(EmberAfClusterCommand *cmd); +extern bool emberAfPrepaymentClusterGetTopUpLogCallback(EmberAfClusterCommand *cmd); +extern bool emberAfPrepaymentClusterPublishDebtLogCallback(EmberAfClusterCommand *cmd); +extern bool emberAfPrepaymentClusterGetDebtRepaymentLogCallback(EmberAfClusterCommand *cmd); +#endif // UC_BUILD // default configurations #define DEFAULT_TABLE_SET_INDEX (0) @@ -59,6 +72,7 @@ static void hideEndpoint(uint8_t endpoint) sl_zigbee_event_t emberAfPluginGasProxyFunctionGsmeSyncEndpointEvents[FIXED_ENDPOINT_COUNT]; sl_zigbee_event_t emberAfPluginGasProxyFunctionCatchupEvent; +extern void emberAfPluginGasProxyFunctionGsmeSyncEndpointEventHandler(uint8_t endpoint); extern void emberAfPluginGasProxyFunctionCatchupEventHandler(sl_zigbee_event_t * event); void emberAfPluginGasProxyFunctionInitCallback(uint8_t init_level) @@ -71,7 +85,7 @@ void emberAfPluginGasProxyFunctionInitCallback(uint8_t init_level) for (i = 0; i < FIXED_ENDPOINT_COUNT; i++) { sl_zigbee_endpoint_event_init(&emberAfPluginGasProxyFunctionGsmeSyncEndpointEvents[i], - emberAfPluginGasProxyFunctionCatchupEventHandler, + emberAfPluginGasProxyFunctionGsmeSyncEndpointEventHandler, endpoint_array[i]); } @@ -2182,6 +2196,49 @@ uint32_t emAfGasProxyFunctionSimpleMeteringClusterClientCommandParse(sl_service_ wasHandled = emberAfSimpleMeteringClusterRemoveMirrorCallback(); break; } + case ZCL_GET_NOTIFIED_MESSAGE_COMMAND_ID: + { + wasHandled = emberAfSimpleMeteringClusterGetNotifiedMessageCallback(cmd); + break; + } + case ZCL_PUBLISH_SNAPSHOT_COMMAND_ID: + { + wasHandled = emberAfSimpleMeteringClusterPublishSnapshotCallback(cmd); + break; + } + case ZCL_GET_SAMPLED_DATA_RESPONSE_COMMAND_ID: + { + wasHandled = emberAfSimpleMeteringClusterGetSampledDataResponseCallback(cmd); + break; + } + } + } + + return ((wasHandled) + ? EMBER_ZCL_STATUS_SUCCESS + : EMBER_ZCL_STATUS_UNSUP_COMMAND); +} + +uint32_t emAfGasProxyFunctionSimpleMeteringClusterServerCommandParse(sl_service_opcode_t opcode, + sl_service_function_context_t *context) +{ + (void)opcode; + + EmberAfClusterCommand *cmd = (EmberAfClusterCommand *)context->data; + bool wasHandled = false; + + if (!cmd->mfgSpecific) { + switch (cmd->commandId) { + case ZCL_GET_SAMPLED_DATA_COMMAND_ID: + { + wasHandled = emberAfSimpleMeteringClusterGetSampledDataCallback(cmd); + break; + } + case ZCL_GET_SNAPSHOT_COMMAND_ID: + { + wasHandled = emberAfSimpleMeteringClusterGetSnapshotCallback(cmd); + break; + } } } @@ -2190,4 +2247,69 @@ uint32_t emAfGasProxyFunctionSimpleMeteringClusterClientCommandParse(sl_service_ : EMBER_ZCL_STATUS_UNSUP_COMMAND); } +uint32_t emAfGasProxyFunctionPrepaymentClusterClientCommandParse(sl_service_opcode_t opcode, + sl_service_function_context_t *context) +{ + (void)opcode; + + EmberAfClusterCommand *cmd = (EmberAfClusterCommand *)context->data; + bool wasHandled = false; + + if (!cmd->mfgSpecific) { + switch (cmd->commandId) { + case ZCL_PUBLISH_PREPAY_SNAPSHOT_COMMAND_ID: + { + wasHandled = emberAfPrepaymentClusterPublishPrepaySnapshotCallback(cmd); + break; + } + case ZCL_PUBLISH_TOP_UP_LOG_COMMAND_ID: + { + wasHandled = emberAfPrepaymentClusterPublishTopUpLogCallback(cmd); + break; + } + case ZCL_PUBLISH_DEBT_LOG_COMMAND_ID: + { + wasHandled = emberAfPrepaymentClusterPublishDebtLogCallback(cmd); + break; + } + } + } + + return ((wasHandled) + ? EMBER_ZCL_STATUS_SUCCESS + : EMBER_ZCL_STATUS_UNSUP_COMMAND); +} + +uint32_t emAfGasProxyFunctionPrepaymentClusterServerCommandParse(sl_service_opcode_t opcode, + sl_service_function_context_t *context) +{ + (void)opcode; + + EmberAfClusterCommand *cmd = (EmberAfClusterCommand *)context->data; + bool wasHandled = false; + + if (!cmd->mfgSpecific) { + switch (cmd->commandId) { + case ZCL_GET_PREPAY_SNAPSHOT_COMMAND_ID: + { + wasHandled = emberAfPrepaymentClusterGetPrepaySnapshotCallback(cmd); + break; + } + case ZCL_GET_TOP_UP_LOG_COMMAND_ID: + { + wasHandled = emberAfPrepaymentClusterGetTopUpLogCallback(cmd); + break; + } + case ZCL_GET_DEBT_REPAYMENT_LOG_COMMAND_ID: + { + wasHandled = emberAfPrepaymentClusterGetDebtRepaymentLogCallback(cmd); + break; + } + } + } + + return ((wasHandled) + ? EMBER_ZCL_STATUS_SUCCESS + : EMBER_ZCL_STATUS_UNSUP_COMMAND); +} #endif // UC_BUILD diff --git a/protocol/zigbee/app/framework/plugin/gas-proxy-function/gpf-structured-data.c b/protocol/zigbee/app/framework/plugin/gas-proxy-function/gpf-structured-data.c index 28aad565eb..f242178b5c 100644 --- a/protocol/zigbee/app/framework/plugin/gas-proxy-function/gpf-structured-data.c +++ b/protocol/zigbee/app/framework/plugin/gas-proxy-function/gpf-structured-data.c @@ -23,10 +23,11 @@ #include "gpf-structured-data.h" #ifdef UC_BUILD +#include "sl_component_catalog.h" #include "gas-proxy-function-config.h" // Needed because we reference EMBER_AF_PLUGIN_METER_MIRROR_MAX_MIRRORS #include "meter-mirror-config.h" -#include "sl_component_catalog.h" +#include "zap-cluster-command-parser.h" #else // !UC_BUILD #ifdef EMBER_AF_PLUGIN_GBCS_COMPATIBILITY #define SL_CATALOG_ZIGBEE_GBCS_COMPATIBILITY_PRESENT @@ -284,7 +285,6 @@ void emberAfPluginGasProxyFunctionCatchupEventHandler(SLXU_UC_EVENT); // See EMAPPFWKV2-1333 and section 10.4.2.8 in v0.8.1. extern sl_zigbee_event_t emberAfPluginGasProxyFunctionGsmeSyncEndpointEvents[]; #define endpointEvent emberAfPluginGasProxyFunctionGsmeSyncEndpointEvents - #else // !UC_BUILD // Event used to handle work when GetNotifiedMessage is received in response @@ -2358,6 +2358,134 @@ void emberAfPluginMeterMirrorReportingCompleteCallback(uint8_t endpoint) * @param numberOfSamples Ver.: always * @param samples Ver.: always */ +#ifdef UC_BUILD +bool emberAfSimpleMeteringClusterGetSampledDataResponseCallback(EmberAfClusterCommand *cmd) +{ + sl_zcl_simple_metering_cluster_get_sampled_data_response_command_t cmd_data; + + if (zcl_decode_simple_metering_cluster_get_sampled_data_response_command(cmd, &cmd_data) + != EMBER_ZCL_STATUS_SUCCESS) { + return false; + } + + uint16_t sampleId = cmd_data.sampleId; + uint32_t sampleStartTime = cmd_data.sampleStartTime; + uint8_t sampleType = cmd_data.sampleType; + uint16_t sampleRequestInterval = cmd_data.sampleRequestInterval; + uint16_t numberOfSamples = cmd_data.numberOfSamples; + uint8_t* samples = cmd_data.samples; + uint8_t endpoint = emberAfCurrentEndpoint(); + uint8_t i = findStructuredData(endpoint); + GpfSampleLog *sampleLog; + GpfSampleLog *otherSampleLog; + uint16_t samplesLength = fieldLength(samples); + uint16_t samplesIndex = 0; + uint32_t sample; + uint32_t sampleTime = sampleStartTime; + EmberAfStatus status; + uint8_t currentSummationDelivered[] = { 0, 0, 0, 0, 0, 0 }; + uint32_t currentSummation; + + emberAfPluginGasProxyFunctionPrintln("GPF: GetSampledDataResponse 0x%2x 0x%4x 0x%x 0x%2x 0x%2x 0x%2x", + sampleId, + sampleStartTime, + sampleType, + sampleRequestInterval, + numberOfSamples, + samplesLength); + + if (i == GPF_INVALID_LOG_INDEX) { + return false; + } + + if (sampleType != EMBER_ZCL_SAMPLE_TYPE_CONSUMPTION_DELIVERED) { + emberAfPluginGasProxyFunctionPrintln("GPF: WARN: GetSampledDataResponse command received with invalid sampleType: 0x%x", sampleType); + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_INVALID_FIELD); + return true; + } + + if (sampleId == GPF_DAILY_CONSUMPTION_LOG_SAMPLE_ID) { + emberAfPluginGasProxyFunctionPrintln("GPF: Receive Daily Consumption Log"); + sampleLog = &structuredData[i].dailyConsumptionLog; + otherSampleLog = &structuredData[i].profileDataLog; + } else if (sampleId == GPF_PROFILE_DATA_LOG_SAMPLE_ID) { + emberAfPluginGasProxyFunctionPrintln("GPF: Receive Profile Data Log"); + sampleLog = &structuredData[i].profileDataLog; + otherSampleLog = &structuredData[i].dailyConsumptionLog; + } else { + emberAfPluginGasProxyFunctionPrintln("GPF: WARN: GetSampledDataResponse command received with invalid sampleId: 0x%2x", sampleId); + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_INVALID_FIELD); + return true; + } + + // The only times we should receive a GetSampledDataResponse are + // the following: + // 1) After a node restart where we send a GetSampledData request to obtain + // any data that may have been missed while this node was out of service. + // 2) After we know that we are missing GSME Profile Data Log entries, and + // we send a GetSampledData to retrieve those entries. + // These are both examples of a "catchup." + // As such we will ignore any commands that we were not expecting. + if (!sampleLog->catchup || emberAfCurrentCommand()->seqNum != sampleLog->catchupSequenceNumber) { + emberAfPluginGasProxyFunctionPrintln("GPF: WARN: ignoring unexpected GetSampledDataResponse command"); + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_SUCCESS); + return true; + } + + // Don't overwrite our start time if we have already been receiving samples + // from the GSME. + if (sampleLog->numberOfEntries == 0) { + sampleLog->startTime = sampleTime; + } + + sampleLog->sampleInterval = sampleRequestInterval; + while (samplesIndex < samplesLength) { + sample = emberAfGetInt24u(samples, samplesIndex, samplesLength); + samplesIndex += 3; + sampleTime = ((sampleId == GPF_PROFILE_DATA_LOG_SAMPLE_ID) + ? NEXT_HALF_HOUR(sampleTime) : NEXT_MIDNIGHT(sampleTime)); + receiveSampleData(sampleTime, sample, sampleLog); + } + + // now that we are caught up we need to set the prev summation value so that + // the next time the device reports consumption we can calculate the sample + // correctly. For the profile log it is easy, we just use the current + // summation attribute which represents the last time it was reported. For + // the daily consumption log it is a little more difficult. To set the prev + // summation we need to start with the current summation then using the profile + // log subtract the incremental values back to the beginning of the day. + status = emberAfReadServerAttribute(endpoint, + ZCL_SIMPLE_METERING_CLUSTER_ID, + ZCL_CURRENT_SUMMATION_DELIVERED_ATTRIBUTE_ID, + currentSummationDelivered, + 6); + if (status != EMBER_ZCL_STATUS_SUCCESS) { + emberAfPluginGasProxyFunctionPrintln("GPF: ERR: can't read CurrentSummationDelivered attribute: status 0x%x", status); + } + // We only care about the least significant 32 bits as the the summation delivered + // should not change by more than a 32 bit value between attribute reports. +#if (BIGENDIAN_CPU) + MEMCOPY((uint8_t *)¤tSummation, ¤tSummationDelivered[2], 4); +#else + MEMCOPY((uint8_t *)¤tSummation, ¤tSummationDelivered[0], 4); +#endif + if (sampleId == GPF_PROFILE_DATA_LOG_SAMPLE_ID) { + sampleLog->prevSummation = currentSummation; + // in this case sampleLog is the profile data log and otherSamleLog is + // the daily consumption log + setDailyConsumptionLogPrevSummation(sampleLog, otherSampleLog); + } else if (!otherSampleLog->catchup) { + // in this case sampleLog is the daily consumption log and otherSampleLog is + // the profile data log. + setDailyConsumptionLogPrevSummation(otherSampleLog, sampleLog); + } + + stopSampleLogCatchup(endpoint, sampleLog, otherSampleLog); + + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_SUCCESS); + return true; +} +#else // !UC_BUILD bool emberAfSimpleMeteringClusterGetSampledDataResponseCallback(uint16_t sampleId, uint32_t sampleStartTime, uint8_t sampleType, @@ -2476,6 +2604,7 @@ bool emberAfSimpleMeteringClusterGetSampledDataResponseCallback(uint16_t sampleI emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_SUCCESS); return true; } +#endif // UC_BUILD /** @brief Simple Metering Cluster Get Sampled Data * @@ -2484,6 +2613,59 @@ bool emberAfSimpleMeteringClusterGetSampledDataResponseCallback(uint16_t sampleI * @param sampleType Ver.: always * @param numberOfSamples Ver.: always */ +#ifdef UC_BUILD +bool emberAfSimpleMeteringClusterGetSampledDataCallback(EmberAfClusterCommand *cmd) +{ + sl_zcl_simple_metering_cluster_get_sampled_data_command_t cmd_data; + + if (zcl_decode_simple_metering_cluster_get_sampled_data_command(cmd, &cmd_data) + != EMBER_ZCL_STATUS_SUCCESS) { + return false; + } + + uint8_t endpoint = emberAfCurrentEndpoint(); + uint8_t i = findStructuredData(endpoint); + GpfSampleLog *sampleLog; + + emberAfPluginGasProxyFunctionPrintln("GPF: GetSampledData 0x%2x 0x%4x 0x%x 0x%2x", + cmd_data.sampleId, + cmd_data.earliestSampleTime, + cmd_data.sampleType, + cmd_data.numberOfSamples); + + if (i == GPF_INVALID_LOG_INDEX) { + return false; + } + + if (cmd_data.sampleType != EMBER_ZCL_SAMPLE_TYPE_CONSUMPTION_DELIVERED) { + emberAfPluginGasProxyFunctionPrintln("GPF: WARN: GetSampledData command received with invalid sampleType: 0x%x", cmd_data.sampleType); + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_NOT_FOUND); + return true; + } + + if (!emberAfPluginGasProxyFunctionDataLogAccessRequestCallback(emberAfPluginGasProxyFunctionGetCurrentMessage(), + emberAfCurrentCommand())) { + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_NOT_AUTHORIZED); + return true; + } + + if (cmd_data.sampleId == GPF_DAILY_CONSUMPTION_LOG_SAMPLE_ID) { + emberAfPluginGasProxyFunctionPrintln("GPF: Publish Daily Consumption Log"); + sampleLog = &structuredData[i].dailyConsumptionLog; + } else if (cmd_data.sampleId == GPF_PROFILE_DATA_LOG_SAMPLE_ID) { + emberAfPluginGasProxyFunctionPrintln("GPF: Publish Profile Data Log"); + sampleLog = &structuredData[i].profileDataLog; + } else { + emberAfPluginGasProxyFunctionPrintln("GPF: WARN: GetSampledData command received with invalid sampleId: 0x%2x", cmd_data.sampleId); + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_NOT_FOUND); + return true; + } + + sendSampleData(cmd_data.earliestSampleTime, cmd_data.numberOfSamples, sampleLog); + return true; +} + +#else // !UC_BUILD bool emberAfSimpleMeteringClusterGetSampledDataCallback(uint16_t sampleId, uint32_t earliestSampleTime, uint8_t sampleType, @@ -2530,6 +2712,7 @@ bool emberAfSimpleMeteringClusterGetSampledDataCallback(uint16_t sampleId, sendSampleData(earliestSampleTime, numberOfSamples, sampleLog); return true; } +#endif // UC_BUILD /** @brief Simple Metering Cluster Publish Snapshot * @@ -2542,6 +2725,122 @@ bool emberAfSimpleMeteringClusterGetSampledDataCallback(uint16_t sampleId, * @param snapshotPayloadType Ver.: always * @param snapshotPayload Ver.: always */ +#ifdef UC_BUILD +bool emberAfSimpleMeteringClusterPublishSnapshotCallback(EmberAfClusterCommand *cmd) +{ + sl_zcl_simple_metering_cluster_publish_snapshot_command_t cmd_data; + + if (zcl_decode_simple_metering_cluster_publish_snapshot_command(cmd, &cmd_data) + != EMBER_ZCL_STATUS_SUCCESS) { + return false; + } + + uint8_t endpoint = emberAfCurrentEndpoint(); + uint8_t i = findStructuredData(endpoint); + GpfSnapshotLog *snapshotLog; + GpfSnapshotLog *otherSnapshotLog; + uint32_t now = emberAfGetCurrentTime(); + + emberAfPluginGasProxyFunctionPrintln("GPF: PublishSnapshot 0x%4x 0x%4x 0x%x 0x%x 0x%x 0x%4x 0x%x", + cmd_data.snapshotId, + cmd_data.snapshotTime, + cmd_data.totalSnapshotsFound, + cmd_data.commandIndex, + cmd_data.totalCommands, + cmd_data.snapshotCause, + cmd_data.snapshotPayloadType); + + if (i == GPF_INVALID_LOG_INDEX) { + return false; + } + + // Both the Daily Read Log and Billing Data Log PublishSnapshot commands use + // the same snapshotPayloadTypes (referenced below). The types were obtained + // by looking at the response in the use case description for GCS16a then + // also looking at the description of the billing data log in GBCS v0.8.1 + // section 10.4.2.4 and comparing it to the description of the daily read log + // in the SMETS v1.58 section 4.4.94. + // GBCS IRP328 wants to add support for SnapshotPayloadType 4 and 6 i.e + // EMBER_ZCL_SNAPSHOT_PAYLOAD_TYPE_TOU_INFORMATION_SET_DELIVERED_REGISTERS_NO_BILLING + // and EMBER_ZCL_SNAPSHOT_PAYLOAD_TYPE_BLOCK_TIER_INFORMATION_SET_DELIVERED_NO_BILLING respectively. + if (cmd_data.snapshotPayloadType != EMBER_ZCL_SNAPSHOT_PAYLOAD_TYPE_TOU_INFORMATION_SET_DELIVERED_REGISTERS + && cmd_data.snapshotPayloadType != EMBER_ZCL_SNAPSHOT_PAYLOAD_TYPE_BLOCK_TIER_INFORMATION_SET_DELIVERED + && cmd_data.snapshotPayloadType != EMBER_ZCL_SNAPSHOT_PAYLOAD_TYPE_TOU_INFORMATION_SET_DELIVERED_REGISTERS_NO_BILLING + && cmd_data.snapshotPayloadType != EMBER_ZCL_SNAPSHOT_PAYLOAD_TYPE_BLOCK_TIER_INFORMATION_SET_DELIVERED_NO_BILLING) { + emberAfPluginGasProxyFunctionPrintln("GPF: WARN: PublishSnapshot command received with unsupported payloadType: 0x%x", cmd_data.snapshotPayloadType); + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_INVALID_FIELD); + return true; + } + + if (cmd_data.snapshotCause == GPF_SNAPSHOT_CAUSE_GENERAL) { + emberAfPluginGasProxyFunctionPrintln("GPF: Receive Daily Read Log"); + snapshotLog = &structuredData[i].dailyReadLog; + otherSnapshotLog = &structuredData[i].billingDataLog.snapshot; + } else if (cmd_data.snapshotCause + & (GPF_SNAPSHOT_CAUSE_END_OF_BILLING_PERIOD + | GPF_SNAPSHOT_CAUSE_CHANGE_OF_TARIFF + | GPF_SNAPSHOT_CAUSE_CHANGE_OF_SUPPLIER + | GPF_SNAPSHOT_CAUSE_CHANGE_OF_PAYMENT_MODE)) { + emberAfPluginGasProxyFunctionPrintln("GPF: Receive Billing Data Log - Tariff TOU Register Matrix, the Consumption Register and Tariff Block Counter Matrix"); + snapshotLog = &structuredData[i].billingDataLog.snapshot; + otherSnapshotLog = &structuredData[i].dailyReadLog; + } else { + emberAfPluginGasProxyFunctionPrintln("GPF: WARN: PublishSnapshot command received with unsupported cause: 0x%4x", cmd_data.snapshotCause); + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_INVALID_FIELD); + return true; + } + + // Ignore any commands that we were not expecting. + if (snapshotLog->catchup && emberAfCurrentCommand()->seqNum != snapshotLog->catchupSequenceNumber) { + emberAfPluginGasProxyFunctionPrintln("GPF: WARN: ignoring unexpected PublishSnapshot command"); + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_SUCCESS); + return true; + } + + receiveSnapshot(cmd_data.snapshotId, cmd_data.snapshotTime, cmd_data.snapshotCause, cmd_data.snapshotPayloadType, cmd_data.snapshotPayload, snapshotLog); + + if (snapshotLog->catchup) { + snapshotLog->catchupSnapshotOffset++; + if (snapshotLog->catchupSnapshotOffset >= cmd_data.totalSnapshotsFound) { + stopSnapshotLogCatchup(endpoint, snapshotLog, otherSnapshotLog); + } else { + EmberAfClusterCommand *cmd_current = emberAfCurrentCommand(); + getSnapshot(endpoint, cmd_current->apsFrame->sourceEndpoint, cmd_current->source, snapshotLog); + } + } else { + if (cmd_data.snapshotCause == GPF_SNAPSHOT_CAUSE_GENERAL) { + /* + * GBCS v0.8.1 Section 10.4.2.1 + * + * The GPF shall populate the relevant attributes upon receipt of the + * PublishSnapshot command, providing the command is received between + * midnight (UTC) and the next scheduled wake of the GSME. + */ + if (cmd_data.snapshotTime >= PREV_MIDNIGHT(now) + && structuredData[i].lastAttributeReportTime < PREV_MIDNIGHT(now)) { + updateSnapshotAttributes(endpoint, cmd_data.snapshotPayloadType, cmd_data.snapshotPayload); + } + } else { + /* + * CHTS v1.46 Section 4.5.2 + * + * Where changes have been made to the GSME Billing Data Log in accordance + * with the timetable set-out in the GSME Billing Calendar, the GPF shall be + * capable of generating and sending an Alert containing the most recent + * entries of the GSME Tariff TOU Register Matrix, the GSME Tariff Block + * Counter Matrix and the GSME Consumption Register in the GSME Billing Data + * Log. + */ + emAfGasProxyFunctionAlert(GBCS_ALERT_BILLING_DATA_LOG_UPDATED, + emberAfCurrentCommand(), + GCS53_MESSAGE_CODE); + } + } + + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_SUCCESS); + return true; +} +#else // !UC_BUILD bool emberAfSimpleMeteringClusterPublishSnapshotCallback(uint32_t snapshotId, uint32_t snapshotTime, uint8_t totalSnapshotsFound, @@ -2656,6 +2955,7 @@ bool emberAfSimpleMeteringClusterPublishSnapshotCallback(uint32_t snapshotId, emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_SUCCESS); return true; } +#endif // UC_BUILD /** @brief Simple Metering Cluster Get Snapshot * @@ -2664,14 +2964,70 @@ bool emberAfSimpleMeteringClusterPublishSnapshotCallback(uint32_t snapshotId, * @param snapshotOffset Ver.: always * @param snapshotCause Ver.: always */ -bool emberAfSimpleMeteringClusterGetSnapshotCallback(uint32_t earliestStartTime, - uint32_t latestEndTime, - uint8_t snapshotOffset, - uint32_t snapshotCause) +#ifdef UC_BUILD +bool emberAfSimpleMeteringClusterGetSnapshotCallback(EmberAfClusterCommand *cmd) { - uint8_t endpoint = emberAfCurrentEndpoint(); - uint8_t i = findStructuredData(endpoint); - GpfSnapshotLog *snapshotLog; + sl_zcl_simple_metering_cluster_get_snapshot_command_t cmd_data; + + if (zcl_decode_simple_metering_cluster_get_snapshot_command(cmd, &cmd_data) + != EMBER_ZCL_STATUS_SUCCESS) { + return false; + } + + uint8_t endpoint = emberAfCurrentEndpoint(); + uint8_t i = findStructuredData(endpoint); + GpfSnapshotLog *snapshotLog; + + emberAfPluginGasProxyFunctionPrintln("GPF: GetSnapshot 0x%4x 0x%4x 0x%x 0x%4x", + cmd_data.earliestStartTime, + cmd_data.latestEndTime, + cmd_data.snapshotOffset, + cmd_data.snapshotCause); + + if (i == GPF_INVALID_LOG_INDEX) { + return false; + } + + if (cmd_data.snapshotCause == GPF_SNAPSHOT_CAUSE_GENERAL) { + emberAfPluginGasProxyFunctionPrintln("GPF: Publish Daily Read Log"); + snapshotLog = &structuredData[i].dailyReadLog; + if (!emberAfPluginGasProxyFunctionDataLogAccessRequestCallback(emberAfPluginGasProxyFunctionGetCurrentMessage(), + emberAfCurrentCommand())) { + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_NOT_AUTHORIZED); + goto kickout; + } + } else if (cmd_data.snapshotCause + & (GPF_SNAPSHOT_CAUSE_END_OF_BILLING_PERIOD + | GPF_SNAPSHOT_CAUSE_CHANGE_OF_TARIFF + | GPF_SNAPSHOT_CAUSE_CHANGE_OF_SUPPLIER + | GPF_SNAPSHOT_CAUSE_CHANGE_OF_PAYMENT_MODE)) { + if (!emberAfPluginGasProxyFunctionDataLogAccessRequestCallback(emberAfPluginGasProxyFunctionGetCurrentMessage(), + emberAfCurrentCommand())) { + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_NOT_AUTHORIZED); + goto kickout; + } + + emberAfPluginGasProxyFunctionPrintln("GPF: Publish Billing Data Log - Tariff TOU Register Matrix, the Consumption Register and Tariff Block Counter Matrix"); + snapshotLog = &structuredData[i].billingDataLog.snapshot; + } else { + emberAfPluginGasProxyFunctionPrintln("GPF: WARN: GetSnapshot command received with unsupported cause: 0x%4x", cmd_data.snapshotCause); + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_NOT_FOUND); + return true; + } + + sendSnapshot(cmd_data.earliestStartTime, cmd_data.latestEndTime, cmd_data.snapshotOffset, cmd_data.snapshotCause, snapshotLog); + kickout: + return true; +} +#else // !UC_BUILD +bool emberAfSimpleMeteringClusterGetSnapshotCallback(uint32_t earliestStartTime, + uint32_t latestEndTime, + uint8_t snapshotOffset, + uint32_t snapshotCause) +{ + uint8_t endpoint = emberAfCurrentEndpoint(); + uint8_t i = findStructuredData(endpoint); + GpfSnapshotLog *snapshotLog; emberAfPluginGasProxyFunctionPrintln("GPF: GetSnapshot 0x%4x 0x%4x 0x%x 0x%4x", earliestStartTime, @@ -2714,6 +3070,7 @@ bool emberAfSimpleMeteringClusterGetSnapshotCallback(uint32_t earliestStartTime, kickout: return true; } +#endif // UC_BUILD /** @brief Prepayment Cluster Publish Prepay Snapshot * @@ -2726,6 +3083,121 @@ bool emberAfSimpleMeteringClusterGetSnapshotCallback(uint32_t earliestStartTime, * @param snapshotPayloadType Ver.: always * @param snapshotPayload Ver.: always */ +#ifdef UC_BUILD +bool emberAfPrepaymentClusterPublishPrepaySnapshotCallback(EmberAfClusterCommand *cmd) +{ + sl_zcl_prepayment_cluster_publish_prepay_snapshot_command_t cmd_data; + + if (zcl_decode_prepayment_cluster_publish_prepay_snapshot_command(cmd, &cmd_data) + != EMBER_ZCL_STATUS_SUCCESS) { + return false; + } + + uint32_t snapshotId = cmd_data.snapshotId; + uint32_t snapshotTime = cmd_data.snapshotTime; + uint8_t totalSnapshotsFound = cmd_data.totalSnapshotsFound; + uint8_t commandIndex = cmd_data.commandIndex; + uint8_t totalNumberOfCommands = cmd_data.totalNumberOfCommands; + uint32_t snapshotCause = cmd_data.snapshotCause; + uint8_t snapshotPayloadType = cmd_data.snapshotPayloadType; + uint8_t* snapshotPayload = cmd_data.snapshotPayload; + uint8_t endpoint = emberAfCurrentEndpoint(); + uint8_t i = findStructuredData(endpoint); + GpfPrepaySnapshotLog *prepaySnapshotLog; + GpfPrepaySnapshotLog *otherPrepaySnapshotLog; + uint32_t now = emberAfGetCurrentTime(); + + emberAfPluginGasProxyFunctionPrintln("GPF: RX: PublishPrepaySnapshot, 0x%4x, 0x%4x, 0x%x, 0x%x, 0x%x, 0x%4x, 0x%x", + snapshotId, + snapshotTime, + totalSnapshotsFound, + commandIndex, + totalNumberOfCommands, + snapshotCause, + snapshotPayloadType); + + if (i == GPF_INVALID_LOG_INDEX) { + return false; + } + + if (snapshotPayloadType != EMBER_ZCL_PREPAY_SNAPSHOT_PAYLOAD_TYPE_DEBT_CREDIT_STATUS) { + emberAfPluginGasProxyFunctionPrintln("GPF: WARN: PublishPrepaySnapshot command received with unsupported payloadType: 0x%x", snapshotPayloadType); + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_INVALID_FIELD); + return true; + } + + if (snapshotCause == GPF_SNAPSHOT_CAUSE_GENERAL) { + emberAfPluginGasProxyFunctionPrintln("GPF: Receive Prepay Daily Read Log"); + if (!emberAfPluginGasProxyFunctionDataLogAccessRequestCallback(emberAfPluginGasProxyFunctionGetCurrentMessage(), + emberAfCurrentCommand())) { + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_NOT_AUTHORIZED); + goto kickout; + } + + prepaySnapshotLog = &structuredData[i].prepayDailyReadLog; + otherPrepaySnapshotLog = &structuredData[i].billingDataLog.prepaySnapshot; + } else if (snapshotCause + & (GPF_SNAPSHOT_CAUSE_END_OF_BILLING_PERIOD + | GPF_SNAPSHOT_CAUSE_CHANGE_OF_TARIFF + | GPF_SNAPSHOT_CAUSE_CHANGE_OF_SUPPLIER + | GPF_SNAPSHOT_CAUSE_CHANGE_OF_PAYMENT_MODE)) { + emberAfPluginGasProxyFunctionPrintln("GPF: Receive Billing Data Log - Meter Balance, Emergency Credit Balance, Accumulated Debt Register, Payment Debt Register and Time Debt Registers"); + prepaySnapshotLog = &structuredData[i].billingDataLog.prepaySnapshot; + otherPrepaySnapshotLog = &structuredData[i].prepayDailyReadLog; + } else { + emberAfPluginGasProxyFunctionPrintln("GPF: WARN: PublishPrepaySnapshot command received with unsupported cause: 0x%4x", snapshotCause); + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_INVALID_FIELD); + return true; + } + + // Ignore any commands that we were not expecting. + if (prepaySnapshotLog->catchup && emberAfCurrentCommand()->seqNum != prepaySnapshotLog->catchupSequenceNumber) { + emberAfPluginGasProxyFunctionPrintln("GPF: WARN: ignoring unexpected PublishPrepaySnapshot command"); + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_SUCCESS); + return true; + } + + receivePrepaySnapshot(snapshotId, snapshotTime, snapshotCause, snapshotPayloadType, snapshotPayload, prepaySnapshotLog); + + if (prepaySnapshotLog->catchup) { + prepaySnapshotLog->catchupSnapshotOffset++; + if (prepaySnapshotLog->catchupSnapshotOffset >= totalSnapshotsFound) { + stopPrepaySnapshotLogCatchup(endpoint, prepaySnapshotLog, otherPrepaySnapshotLog); + } else { + EmberAfClusterCommand *cmd = emberAfCurrentCommand(); + getPrepaySnapshot(endpoint, cmd->apsFrame->sourceEndpoint, cmd->source, prepaySnapshotLog); + } + } else { + if (snapshotCause == GPF_SNAPSHOT_CAUSE_GENERAL) { + /* + * GBCS v0.8.1 Section 10.4.2.2 + * + * The GPF shall populate the relevant attributes upon receipt of the + * Publish Prepay Snapshot command, providing the command is received + * between midnight (UTC) and the next scheduled wake of the GSME. + */ + if (snapshotTime >= PREV_MIDNIGHT(now) + && structuredData[i].lastAttributeReportTime < PREV_MIDNIGHT(now)) { + updatePrepaySnapshotAttributes(endpoint, snapshotPayloadType, snapshotPayload); + } + } else { + /* + * GBCS IRP328: added missing element in the usecase GCS53. + * With this change, the GPF shall be capable of generating and sending an alert + * containing the most entries of GSME Meter Balance, Emergency Credit Balance, + * Accumulated Debt Register, Payment Debt Register and Time Debt Registers [1 ... 2] + */ + emAfGasProxyFunctionAlert(GBCS_ALERT_BILLING_DATA_LOG_UPDATED, + emberAfCurrentCommand(), + GCS53_MESSAGE_CODE); + } + } + + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_SUCCESS); + kickout: + return true; +} +#else // !UC_BUILD bool emberAfPrepaymentClusterPublishPrepaySnapshotCallback(uint32_t snapshotId, uint32_t snapshotTime, uint8_t totalSnapshotsFound, @@ -2831,6 +3303,7 @@ bool emberAfPrepaymentClusterPublishPrepaySnapshotCallback(uint32_t snapshotId, kickout: return true; } +#endif // UC_BUILD /** @brief Prepayment Cluster Get Prepay Snapshot * @@ -2839,6 +3312,50 @@ bool emberAfPrepaymentClusterPublishPrepaySnapshotCallback(uint32_t snapshotId, * @param snapshotOffset Ver.: always * @param snapshotCause Ver.: always */ +#ifdef UC_BUILD +bool emberAfPrepaymentClusterGetPrepaySnapshotCallback(EmberAfClusterCommand *cmd) +{ + sl_zcl_prepayment_cluster_get_prepay_snapshot_command_t cmd_data; + + if (zcl_decode_prepayment_cluster_get_prepay_snapshot_command(cmd, &cmd_data) + != EMBER_ZCL_STATUS_SUCCESS) { + return false; + } + + uint8_t endpoint = emberAfCurrentEndpoint(); + uint8_t i = findStructuredData(endpoint); + GpfPrepaySnapshotLog *prepaySnapshotLog; + + emberAfPluginGasProxyFunctionPrintln("GPF: RX: GetPrepaySnapshot 0x%4x 0x%4x 0x%x 0x%4x", + cmd_data.earliestStartTime, + cmd_data.latestEndTime, + cmd_data.snapshotOffset, + cmd_data.snapshotCause); + + if (i == GPF_INVALID_LOG_INDEX) { + return false; + } + + if (cmd_data.snapshotCause == GPF_SNAPSHOT_CAUSE_GENERAL) { + emberAfPluginGasProxyFunctionPrintln("GPF: Publish Prepay Daily Read Log"); + prepaySnapshotLog = &structuredData[i].prepayDailyReadLog; + } else if (cmd_data.snapshotCause + & (GPF_SNAPSHOT_CAUSE_END_OF_BILLING_PERIOD + | GPF_SNAPSHOT_CAUSE_CHANGE_OF_TARIFF + | GPF_SNAPSHOT_CAUSE_CHANGE_OF_SUPPLIER + | GPF_SNAPSHOT_CAUSE_CHANGE_OF_PAYMENT_MODE)) { + emberAfPluginGasProxyFunctionPrintln("GPF: Publish Billing Data Log - Meter Balance, Emergency Credit Balance, Accumulated Debt Register, Payment Debt Register and Time Debt Registers"); + prepaySnapshotLog = &structuredData[i].billingDataLog.prepaySnapshot; + } else { + emberAfPluginGasProxyFunctionPrintln("GPF: WARN: GetPrepaySnapshot command received with unsupported cause: 0x%4x", cmd_data.snapshotCause); + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_NOT_FOUND); + return true; + } + + sendPrepaySnapshot(cmd_data.earliestStartTime, cmd_data.latestEndTime, cmd_data.snapshotOffset, cmd_data.snapshotCause, prepaySnapshotLog); + return true; +} +#else // !UC_BUILD bool emberAfPrepaymentClusterGetPrepaySnapshotCallback(uint32_t earliestStartTime, uint32_t latestEndTime, uint8_t snapshotOffset, @@ -2877,6 +3394,7 @@ bool emberAfPrepaymentClusterGetPrepaySnapshotCallback(uint32_t earliestStartTim sendPrepaySnapshot(earliestStartTime, latestEndTime, snapshotOffset, snapshotCause, prepaySnapshotLog); return true; } +#endif // UC_BUILD /** @brief Prepayment Cluster Publish Top Up Log * @@ -2884,6 +3402,62 @@ bool emberAfPrepaymentClusterGetPrepaySnapshotCallback(uint32_t earliestStartTim * @param totalNumberOfCommands Ver.: always * @param topUpPayload Ver.: always */ +#ifdef UC_BUILD +bool emberAfPrepaymentClusterPublishTopUpLogCallback(EmberAfClusterCommand *cmd) +{ + sl_zcl_prepayment_cluster_publish_top_up_log_command_t cmd_data; + + if (zcl_decode_prepayment_cluster_publish_top_up_log_command(cmd, &cmd_data) + != EMBER_ZCL_STATUS_SUCCESS) { + return false; + } + + uint8_t endpoint = emberAfCurrentEndpoint(); + uint8_t i = findStructuredData(endpoint); + GpfTopUpLog *topUpLog; + uint16_t topUpPayloadLength = fieldLength(cmd_data.topUpPayload); + uint16_t topUpPayloadIndex = 0; + uint8_t *topUpPayloadCode; + uint32_t topUpPayloadAmount; + uint32_t topUpPayloadTime; + + emberAfPluginGasProxyFunctionPrintln("GPF: PublishTopUpLog 0x%x 0x%x 0x%2x", + cmd_data.commandIndex, + cmd_data.totalNumberOfCommands, + topUpPayloadLength); + + if (i == GPF_INVALID_LOG_INDEX) { + return false; + } + + emberAfPluginGasProxyFunctionPrintln("GPF: Receive Billing Data Log - value of prepayment credits"); + topUpLog = &structuredData[i].billingDataLog.topUp; + + // Ignore any commands that we were not expecting. + if (topUpLog->catchup && emberAfCurrentCommand()->seqNum != topUpLog->catchupSequenceNumber) { + emberAfPluginGasProxyFunctionPrintln("GPF: WARN: ignoring unexpected PublishTopUpLog command"); + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_SUCCESS); + return true; + } + + while (topUpPayloadIndex < topUpPayloadLength) { + topUpPayloadCode = emberAfGetString(cmd_data.topUpPayload, topUpPayloadIndex, topUpPayloadLength); + topUpPayloadIndex += emberAfStringLength(topUpPayloadCode) + 1; + topUpPayloadAmount = emberAfGetInt32u(cmd_data.topUpPayload, topUpPayloadIndex, topUpPayloadLength); + topUpPayloadIndex += 4; + topUpPayloadTime = emberAfGetInt32u(cmd_data.topUpPayload, topUpPayloadIndex, topUpPayloadLength); + topUpPayloadIndex += 4; + receiveTopUp(topUpPayloadCode, topUpPayloadAmount, topUpPayloadTime, topUpLog); + } + + if (topUpLog->catchup) { + stopTopUpLogCatchup(endpoint, topUpLog); + } + + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_SUCCESS); + return true; +} +#else // !UC_BUILD bool emberAfPrepaymentClusterPublishTopUpLogCallback(uint8_t commandIndex, uint8_t totalNumberOfCommands, uint8_t* topUpPayload) @@ -2933,12 +3507,48 @@ bool emberAfPrepaymentClusterPublishTopUpLogCallback(uint8_t commandIndex, emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_SUCCESS); return true; } +#endif // UC_BUILD /** @brief Prepayment Cluster Get Top Up Log * * @param latestEndTime Ver.: always * @param numberOfRecords Ver.: always */ +#ifdef UC_BUILD +bool emberAfPrepaymentClusterGetTopUpLogCallback(EmberAfClusterCommand *cmd) +{ + sl_zcl_prepayment_cluster_get_top_up_log_command_t cmd_data; + + if (zcl_decode_prepayment_cluster_get_top_up_log_command(cmd, &cmd_data) + != EMBER_ZCL_STATUS_SUCCESS) { + return false; + } + + uint8_t endpoint = emberAfCurrentEndpoint(); + uint8_t i = findStructuredData(endpoint); + GpfTopUpLog *topUpLog; + uint32_t earliestStartTime; + + emberAfPluginGasProxyFunctionPrintln("GPF: GetTopUpLog 0x%4x 0x%x", + cmd_data.latestEndTime, + cmd_data.numberOfRecords); + + if (i == GPF_INVALID_LOG_INDEX) { + return false; + } + + emberAfPluginGasProxyFunctionPrintln("GPF: Publish Billing Data Log - value of prepayment credits"); + topUpLog = &structuredData[i].billingDataLog.topUp; + + // GBCS adds an additional filter criteria so if this is use case GCS15e, + // indicated by this being a loopback command, then grab the start time + // from the GBZ parser. + earliestStartTime = (emberAfCurrentCommand()->source == emberAfGetNodeId()) + ? emAfGasProxyFunctionGetGbzStartTime() : 0; + sendTopUp(earliestStartTime, cmd_data.latestEndTime, cmd_data.numberOfRecords, topUpLog); + return true; +} +#else // !UC_BUILD bool emberAfPrepaymentClusterGetTopUpLogCallback(uint32_t latestEndTime, uint8_t numberOfRecords) { @@ -2966,6 +3576,7 @@ bool emberAfPrepaymentClusterGetTopUpLogCallback(uint32_t latestEndTime, sendTopUp(earliestStartTime, latestEndTime, numberOfRecords, topUpLog); return true; } +#endif // UC_BUILD /** @brief Prepayment Cluster Publish Debt Log * @@ -2973,6 +3584,65 @@ bool emberAfPrepaymentClusterGetTopUpLogCallback(uint32_t latestEndTime, * @param totalNumberOfCommands Ver.: always * @param debtPayload Ver.: always */ +#ifdef UC_BUILD +bool emberAfPrepaymentClusterPublishDebtLogCallback(EmberAfClusterCommand *cmd) +{ + sl_zcl_prepayment_cluster_publish_debt_log_command_t cmd_data; + + if (zcl_decode_prepayment_cluster_publish_debt_log_command(cmd, &cmd_data) + != EMBER_ZCL_STATUS_SUCCESS) { + return false; + } + + uint8_t endpoint = emberAfCurrentEndpoint(); + uint8_t i = findStructuredData(endpoint); + GpfDebtLog *debtLog; + uint16_t debtPayloadLength = fieldLength(cmd_data.debtPayload); + uint16_t debtPayloadIndex = 0; + uint32_t collectionTime; + uint32_t amountCollected; + uint32_t outstandingDebt; + uint8_t debtType; + + emberAfPluginGasProxyFunctionPrintln("GPF: PublishDebtLog 0x%x 0x%x 0x%2x", + cmd_data.commandIndex, + cmd_data.totalNumberOfCommands, + debtPayloadLength); + + if (i == GPF_INVALID_LOG_INDEX) { + return false; + } + + emberAfPluginGasProxyFunctionPrintln("GPF: Receive Billing Data Log - payment-based debt payments"); + debtLog = &structuredData[i].billingDataLog.debt; + + // Ignore any commands that we were not expecting. + if (debtLog->catchup && emberAfCurrentCommand()->seqNum != debtLog->catchupSequenceNumber) { + emberAfPluginGasProxyFunctionPrintln("GPF: WARN: ignoring unexpected PublishDebtLog command"); + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_SUCCESS); + return true; + } + + while (debtPayloadIndex < debtPayloadLength) { + collectionTime = emberAfGetInt32u(cmd_data.debtPayload, debtPayloadIndex, debtPayloadLength); + debtPayloadIndex += 4; + amountCollected = emberAfGetInt32u(cmd_data.debtPayload, debtPayloadIndex, debtPayloadLength); + debtPayloadIndex += 4; + debtType = emberAfGetInt8u(cmd_data.debtPayload, debtPayloadIndex, debtPayloadLength); + debtPayloadIndex += 1; + outstandingDebt = emberAfGetInt32u(cmd_data.debtPayload, debtPayloadIndex, debtPayloadLength); + debtPayloadIndex += 4; + receiveDebt(collectionTime, amountCollected, outstandingDebt, debtType, debtLog); + } + + if (debtLog->catchup) { + stopDebtLogCatchup(endpoint, debtLog); + } + + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_SUCCESS); + return true; +} +#else // !UC_BUILD bool emberAfPrepaymentClusterPublishDebtLogCallback(uint8_t commandIndex, uint8_t totalNumberOfCommands, uint8_t* debtPayload) @@ -3025,6 +3695,7 @@ bool emberAfPrepaymentClusterPublishDebtLogCallback(uint8_t commandIndex, emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_SUCCESS); return true; } +#endif // UC_BUILD /** @brief Prepayment Cluster Get Debt Repayment Log * @@ -3032,6 +3703,42 @@ bool emberAfPrepaymentClusterPublishDebtLogCallback(uint8_t commandIndex, * @param numberOfDebts Ver.: always * @param debtType Ver.: always */ +#ifdef UC_BUILD +bool emberAfPrepaymentClusterGetDebtRepaymentLogCallback(EmberAfClusterCommand *cmd) +{ + sl_zcl_prepayment_cluster_get_debt_repayment_log_command_t cmd_data; + + if (zcl_decode_prepayment_cluster_get_debt_repayment_log_command(cmd, &cmd_data) + != EMBER_ZCL_STATUS_SUCCESS) { + return false; + } + + uint8_t endpoint = emberAfCurrentEndpoint(); + uint8_t i = findStructuredData(endpoint); + GpfDebtLog *debtLog; + uint32_t earliestStartTime; + + emberAfPluginGasProxyFunctionPrintln("GPF: GetDebtRepaymentLog 0x%4x 0x%x 0x%x", + cmd_data.latestEndTime, + cmd_data.numberOfDebts, + cmd_data.debtType); + + if (i == GPF_INVALID_LOG_INDEX) { + return false; + } + + emberAfPluginGasProxyFunctionPrintln("GPF: Publish Billing Data Log - payment-based debt payments"); + debtLog = &structuredData[i].billingDataLog.debt; + + // GBCS adds an additional filter criteria so if this is use case GCS15d, + // indicated by this being a loopback command, then grab the start time + // from the GBZ parser. + earliestStartTime = (emberAfCurrentCommand()->source == emberAfGetNodeId()) + ? emAfGasProxyFunctionGetGbzStartTime() : 0; + sendDebt(earliestStartTime, cmd_data.latestEndTime, cmd_data.numberOfDebts, cmd_data.debtType, debtLog); + return true; +} +#else // !UC_BUILD bool emberAfPrepaymentClusterGetDebtRepaymentLogCallback(uint32_t latestEndTime, uint8_t numberOfDebts, uint8_t debtType) @@ -3061,6 +3768,7 @@ bool emberAfPrepaymentClusterGetDebtRepaymentLogCallback(uint32_t latestEndTime, sendDebt(earliestStartTime, latestEndTime, numberOfDebts, debtType, debtLog); return true; } +#endif // UC_BUILD // Catchup event handler used to retry previously attempted Get requests on // the various logs. @@ -3229,6 +3937,80 @@ void emberAfPluginGasProxyFunctionGsmeSyncEndpointEventHandler(uint8_t endpoint) * @param notificationFlagAttributeId Ver.: always * @param notificationFlagsN Ver.: always */ +#ifdef UC_BUILD +bool emberAfSimpleMeteringClusterGetNotifiedMessageCallback(EmberAfClusterCommand *cmd) +{ + sl_zcl_simple_metering_cluster_get_notified_message_command_t cmd_data; + + if (zcl_decode_simple_metering_cluster_get_notified_message_command(cmd, &cmd_data) + != EMBER_ZCL_STATUS_SUCCESS) { + return false; + } + + uint8_t notificationScheme = cmd_data.notificationScheme; + uint16_t notificationFlagAttributeId = cmd_data.notificationFlagAttributeId; + uint32_t notificationFlagsN = cmd_data.notificationFlagsN; + EmberAfClusterCommand *cmd_current = emberAfCurrentCommand(); + uint8_t endpoint = emberAfCurrentEndpoint(); + uint8_t i = findStructuredData(endpoint); + + /* + * From GBCS + * + * For clarity, the GSME: + * + * - shall not action ZSE / ZCL commands received from the GPF in relation + * to any of the flags within NotificationFlags2, NotificationFlags3 and + * NotificationFlags5; + * + * - for NotificationFlags4, shall only action ZSE / ZCL commands received + * from the GPF in relation to the flags specified below. + * + * Bit Number Waiting Command + * 6 Get Prepay Snapshot + * 7 Get Top Up Log + * 9 Get Debt Repayment Log + * + * - for FunctionalNotificationFlags, shall only action ZSE / ZCL commands + * received from the GPF in relation to the flags specified below + * + * Bit Number Waiting Command + * 0 New OTA Firmware + * 1 CBKE Update Request + * 4 Stay Awake Request HAN + * 5 Stay Awake Request WAN + * 6-8 Push Historical Metering Data Attribute Set + * 9-11 Push Historical Prepayment Data Attribute Set + * 12 Push All Static Data - Basic Cluster + * 13 Push All Static Data - Metering Cluster + * 14 Push All Static Data - Prepayment Cluster + * 15 NetworkKeyActive + * 21 Tunnel Message Pending + * 22 GetSnapshot + * 23 GetSampledData + */ + + if (i == GPF_INVALID_LOG_INDEX || notificationScheme != 0x02 + || (notificationFlagAttributeId != ZCL_FUNCTIONAL_NOTIFICATION_FLAGS_ATTRIBUTE_ID + && notificationFlagAttributeId != ZCL_NOTIFICATION_FLAGS_4_ATTRIBUTE_ID)) { + return false; + } + + // Since this request could result in many commands being sent back to the + // sleepy device we schedule the work for the catchup event handler which can + // deal with spacing out the commands. + structuredData[i].remoteEndpoint = cmd_current->apsFrame->sourceEndpoint; + structuredData[i].remoteNodeId = cmd_current->source; + structuredData[i].functionalNotificationFlags |= + (notificationFlagAttributeId == ZCL_FUNCTIONAL_NOTIFICATION_FLAGS_ATTRIBUTE_ID) ? notificationFlagsN : 0; + structuredData[i].notificationFlags4 |= + (notificationFlagAttributeId == ZCL_NOTIFICATION_FLAGS_4_ATTRIBUTE_ID) ? notificationFlagsN : 0; + slxu_zigbee_event_set_active(gasProxyFunctionCatchupEventControl); + + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_SUCCESS); + return true; +} +#else //! UC_BUILD bool emberAfSimpleMeteringClusterGetNotifiedMessageCallback(uint8_t notificationScheme, uint16_t notificationFlagAttributeId, uint32_t notificationFlagsN) @@ -3293,6 +4075,7 @@ bool emberAfSimpleMeteringClusterGetNotifiedMessageCallback(uint8_t notification emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_SUCCESS); return true; } +#endif // UC_BUILD /** @brief Simple Metering Cluster Client Default Response * diff --git a/protocol/zigbee/app/framework/plugin/gbcs-device-log/gbcs-device-log-cli.c b/protocol/zigbee/app/framework/plugin/gbcs-device-log/gbcs-device-log-cli.c index 20936f3493..42b3d8a092 100644 --- a/protocol/zigbee/app/framework/plugin/gbcs-device-log/gbcs-device-log-cli.c +++ b/protocol/zigbee/app/framework/plugin/gbcs-device-log/gbcs-device-log-cli.c @@ -99,7 +99,7 @@ void emAfPluginGbcsDeviceLogCliPrint(sl_cli_command_arg_t *arguments) // plugin gbcs-device-log is-sleepy void emAfPluginGbcsDeviceLogCliIsSleepy(sl_cli_command_arg_t *arguments) { - EmberAfGBCSDeviceType deviceType = (EmberAfGBCSDeviceType)sl_cli_get_argument_uint8(arguments, 1); + EmberAfGBCSDeviceType deviceType = (EmberAfGBCSDeviceType)sl_cli_get_argument_uint8(arguments, 0); if (emberAfPluginGbcsDeviceLogIsSleepyType(deviceType)) { emberAfPluginGbcsDeviceLogPrintln("Device type %d is a sleepy device type", deviceType); } else { diff --git a/protocol/zigbee/app/framework/plugin/gbcs-gas-meter/gbcs-gas-meter.c b/protocol/zigbee/app/framework/plugin/gbcs-gas-meter/gbcs-gas-meter.c index 1b69e037ef..e36e237997 100644 --- a/protocol/zigbee/app/framework/plugin/gbcs-gas-meter/gbcs-gas-meter.c +++ b/protocol/zigbee/app/framework/plugin/gbcs-gas-meter/gbcs-gas-meter.c @@ -24,6 +24,7 @@ #ifdef UC_BUILD #include "gbcs-gas-meter-config.h" +#include "zap-cluster-command-parser.h" #endif // UC_BUILD // Plugin configuration options @@ -691,6 +692,7 @@ void emberAfPluginSimpleMeteringServerProcessNotificationFlagsCallback(EmberAfAt } } +#ifndef UC_BUILD /** @brief Request Mirror Response * * @param endpointId Ver.: always @@ -742,7 +744,7 @@ bool emberAfSimpleMeteringClusterMirrorRemovedCallback(uint16_t endpointId) emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_SUCCESS); return true; } - +#endif // UC_BUILD /** @brief Registration * * This callback is called when the device joins a network and the process of @@ -1148,3 +1150,96 @@ static void serviceDiscoveryCallback(const EmberAfServiceDiscoveryResult* result emberAfAppPrintln("service discovery complete."); } } + +#ifdef UC_BUILD + +bool emberAfSimpleMeteringClusterRequestMirrorResponseCallback(EmberAfClusterCommand *cmd) +{ + sl_zcl_simple_metering_cluster_request_mirror_response_command_t cmd_data; + + if (zcl_decode_simple_metering_cluster_request_mirror_response_command(cmd, &cmd_data) + != EMBER_ZCL_STATUS_SUCCESS) { + return false; + } + + uint16_t endpointId = cmd_data.endpointId; + + if (endpointId == 0xffff) { + emberAfAppPrintln("Mirror add FAILED"); + } else { + if (state != MIRROR_READY) { + mirrorEndpoint = endpointId; + mirrorAddress = emberAfCurrentCommand()->source; + emberAfAppPrintln("Mirror ADDED on 0x%2x, 0x%x", mirrorAddress, endpointId); + + uint32_t issuerEventId = emberAfGetCurrentTime(); + emberAfFillCommandSimpleMeteringClusterConfigureMirror(issuerEventId, + MIRROR_UPDATE_INTERVAL_SECONDS, + true, + EMBER_ZCL_NOTIFICATION_SCHEME_PREDEFINED_NOTIFICATION_SCHEME_B); + emberAfSetCommandEndpoints(GSME_ENDPOINT, mirrorEndpoint); + emberAfSendCommandUnicast(EMBER_OUTGOING_DIRECT, mirrorAddress); + + setSleepyMeterState(MIRROR_READY); + } else { + emberAfAppPrintln("Mirror add for 0x%2x, 0x%x ignored, already mirrored on 0x%2x 0x%x.", + emberAfCurrentCommand()->source, endpointId, + mirrorAddress, mirrorEndpoint); + } + } + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_SUCCESS); + return true; +} + +bool emberAfSimpleMeteringClusterMirrorRemovedCallback(EmberAfClusterCommand *cmd) +{ + sl_zcl_simple_metering_cluster_mirror_removed_command_t cmd_data; + + if (zcl_decode_simple_metering_cluster_mirror_removed_command(cmd, &cmd_data) + != EMBER_ZCL_STATUS_SUCCESS) { + return false; + } + + uint16_t endpointId = cmd_data.endpointId; + + // * This callback simply prints out the endpoint from which + // * the mirror was removed, and sets our state back to looking for + // * a new mirror + if (endpointId == 0xffff) { + emberAfAppPrintln("Mirror remove FAILED"); + } else { + emberAfAppPrintln("Mirror REMOVED from %x", endpointId); + setSleepyMeterState(INITIAL_STATE); + } + emberAfSendImmediateDefaultResponse(EMBER_ZCL_STATUS_SUCCESS); + return true; +} + +uint32_t emAfGbcsGasMeterSimpleMeteringClusterServerCommandParse(sl_service_opcode_t opcode, + sl_service_function_context_t *context) +{ + (void)opcode; + + EmberAfClusterCommand *cmd = (EmberAfClusterCommand *)context->data; + bool wasHandled = false; + + if (!cmd->mfgSpecific) { + switch (cmd->commandId) { + case ZCL_REQUEST_MIRROR_RESPONSE_COMMAND_ID: + { + wasHandled = emberAfSimpleMeteringClusterRequestMirrorResponseCallback(cmd); + break; + } + case ZCL_MIRROR_REMOVED_COMMAND_ID: + { + wasHandled = emberAfSimpleMeteringClusterMirrorRemovedCallback(cmd); + break; + } + } + } + + return ((wasHandled) + ? EMBER_ZCL_STATUS_SUCCESS + : EMBER_ZCL_STATUS_UNSUP_COMMAND); +} +#endif //UC_BUILD diff --git a/protocol/zigbee/app/framework/plugin/key-establishment/key-establishment.c b/protocol/zigbee/app/framework/plugin/key-establishment/key-establishment.c index ffedceccf7..290f87b35b 100644 --- a/protocol/zigbee/app/framework/plugin/key-establishment/key-establishment.c +++ b/protocol/zigbee/app/framework/plugin/key-establishment/key-establishment.c @@ -22,11 +22,18 @@ #include "app/framework/util/af-main.h" #include "app/framework/util/common.h" #include "hal/hal.h" + #ifdef UC_BUILD +#include "sl_component_catalog.h" +#ifdef SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT #include "test-harness.h" -#else +#endif // SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT +#else // !UC_BUILD +#ifdef EMBER_AF_PLUGIN_TEST_HARNESS +#define SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT #include "app/framework/plugin/test-harness/test-harness.h" -#endif +#endif // EMBER_AF_PLUGIN_TEST_HARNESS +#endif // UC_BUILD #if !defined(EZSP_HOST) #include "stack/include/cbke-crypto-engine.h" @@ -35,7 +42,6 @@ #include "key-establishment-storage.h" #ifdef UC_BUILD -#include "sl_component_catalog.h" #include "zap-cluster-command-parser.h" #include "zigbee_af_cluster_functions.h" @@ -47,11 +53,6 @@ #error "ZCL TerminateKeyEstablishment Command ID not defined" #endif -#else // !UC_BUILD -#ifdef EMBER_AF_PLUGIN_TEST_HARNESS -#define SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT -#endif - WEAK(bool emberAfPluginKeyEstablishmentInterPanCallback(EmberAfKeyEstablishmentNotifyMessage status, bool amInitiator, EmberPanId panId, @@ -161,7 +162,9 @@ EmberEventControl emberAfPluginKeyEstablishmentApsDuplicateDetectionEventControl EmberAfCbkeKeyEstablishmentSuite emAfAvailableCbkeSuite = EMBER_AF_CBKE_KEY_ESTABLISHMENT_SUITE_163K1; EmberAfCbkeKeyEstablishmentSuite emAfCurrentCbkeSuite = EMBER_AF_CBKE_KEY_ESTABLISHMENT_SUITE_163K1; -EmberAfCbkeKeyEstablishmentSuite emUseTestHarnessSuite = EMBER_AF_INVALID_KEY_ESTABLISHMENT_SUITE; +#ifdef SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT +static EmberAfCbkeKeyEstablishmentSuite emUseTestHarnessSuite = EMBER_AF_INVALID_KEY_ESTABLISHMENT_SUITE; +#endif // SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT #if defined EMBER_TEST KeyEstablishEvent timeoutState = NO_KEY_ESTABLISHMENT_EVENT; @@ -250,9 +253,16 @@ static const char * terminateStatus[] = TERMINATE_STATUS_STRINGS; // Over the air message lengths for Initiate Key Establishment Request and Response // certificate + keyEstablishmentSuite + ephemeralDataGenerateTime + confirmKeyGenerateTime -# define INITIATE_KEY_ESTABLISHMENT_LENGTH_163K1 EMBER_CERTIFICATE_SIZE + 2 + 1 + 1 -# define INITIATE_KEY_ESTABLISHMENT_LENGTH_283K1 EMBER_CERTIFICATE_283K1_SIZE + 2 + 1 + 1 - +#define INITIATE_KEY_ESTABLISHMENT_LENGTH_163K1 EMBER_CERTIFICATE_SIZE + 2 + 1 + 1 +#define INITIATE_KEY_ESTABLISHMENT_LENGTH_283K1 EMBER_CERTIFICATE_283K1_SIZE + 2 + 1 + 1 +// The fixed length of the Key Establishment commands. +#define INITIATE_KEY_ESTABLISHMENT_REQUEST_COMMAND_MIN_LENGTH INITIATE_KEY_ESTABLISHMENT_LENGTH_163K1 +#define EPHEMERAL_DATA_REQUEST_COMMAND_MIN_LENGTH 22 +#define CONFIRM_KEY_DATA_REQUEST_COMMAND_MIN_LENGTH 16 + +#define INITIATE_KEY_ESTABLISHMENT_RESPONSE_COMMAND_MIN_LENGTH INITIATE_KEY_ESTABLISHMENT_LENGTH_163K1 +#define EPHEMERAL_DATA_RESPONSE_COMMAND_MIN_LENGTH 22 +#define CONFIRM_KEY_DATA_RESPONSE_COMMAND_MIN_LENGTH 16 //------------------------------------------------------------------------------ // Forward declarations static bool checkMalformed283k1Command(bool isCertificate); @@ -812,9 +822,11 @@ static void sendKeyEstablishMessage(KeyEstablishMessage message) *ptr++ = keyEstPartner.sequenceNumber; *ptr = message; +#ifdef SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT if (!emAfKeyEstablishmentTestHarnessMessageSendCallback(message)) { return; } +#endif // SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT if (keyEstPartner.isIntraPan) { EmberApsFrame apsFrame; @@ -1129,13 +1141,16 @@ static EmberStatus initiateKeyEstablishment(const EmberEUI64 eui64, // The Test Harness can skip the read attributes stage. This is useful // in running curve specific key establishment tests, irrespective of // which binaries are supported. - if (emUseTestHarnessSuite == EMBER_AF_INVALID_KEY_ESTABLISHMENT_SUITE) { - keyEstablishStateMachine(CHECK_SUPPORTED_CURVES, NULL, NULL); - } else { +#ifdef SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT + if (emUseTestHarnessSuite != EMBER_AF_INVALID_KEY_ESTABLISHMENT_SUITE) { lastEvent = CHECK_SUPPORTED_CURVES; validLastEvent = CHECK_SUPPORTED_CURVES; emAfKeyEstablishmentSelectCurve(emUseTestHarnessSuite); keyEstablishStateMachine(BEGIN_KEY_ESTABLISHMENT, NULL, NULL); + } else +#endif // SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT + { + keyEstablishStateMachine(CHECK_SUPPORTED_CURVES, NULL, NULL); } return ((lastEvent == validLastEvent) @@ -1250,7 +1265,9 @@ void sendNextKeyEstablishMessage(KeyEstablishMessage message, void emAfSkipCheckSupportedCurves(EmberAfCbkeKeyEstablishmentSuite suite) { +#ifdef SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT emUseTestHarnessSuite = suite; +#endif // SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT } void emAfSetAvailableCurves(EmberAfCbkeKeyEstablishmentSuite suite) @@ -1652,11 +1669,13 @@ void emAfPluginKeyEstablishmentGenerateCbkeKeysHandler(EmberStatus status, return; } +#ifdef SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT if (emAfKeyEstablishmentTestHarnessCbkeCallback(CBKE_OPERATION_GENERATE_KEYS, ephemeralPublicKey->contents, NULL)) { return; } +#endif //SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT (void) emberAfPushEndpointNetworkIndex(keyEstablishmentEndpoint); keyEstablishStateMachine(SEND_EPHEMERAL_DATA_MESSAGE, @@ -1680,11 +1699,13 @@ void emAfPluginKeyEstablishmentCalculateSmacsHandler(EmberStatus status, return; } +#ifdef SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT if (emAfKeyEstablishmentTestHarnessCbkeCallback(CBKE_OPERATION_GENERATE_SECRET, initiatorSmac->contents, responderSmac->contents)) { return; } +#endif // SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT (void) emberAfPushEndpointNetworkIndex(keyEstablishmentEndpoint); keyEstablishStateMachine(SEND_CONFIRM_KEY_MESSAGE, @@ -1705,11 +1726,13 @@ void emAfPluginKeyEstablishmentGenerateCbkeKeysHandler283k1(EmberStatus status, return; } +#ifdef SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT if (emAfKeyEstablishmentTestHarnessCbkeCallback(CBKE_OPERATION_GENERATE_KEYS_283K1, ephemeralPublicKey->contents, NULL)) { return; } +#endif // SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT (void) emberAfPushEndpointNetworkIndex(keyEstablishmentEndpoint); keyEstablishStateMachine(SEND_EPHEMERAL_DATA_MESSAGE, @@ -1731,11 +1754,13 @@ void emAfPluginKeyEstablishmentCalculateSmacsHandler283k1(EmberStatus status, return; } +#ifdef SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT if (emAfKeyEstablishmentTestHarnessCbkeCallback(CBKE_OPERATION_GENERATE_SECRET_283K1, initiatorSmac->contents, responderSmac->contents)) { return; } +#endif // SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT (void) emberAfPushEndpointNetworkIndex(keyEstablishmentEndpoint); keyEstablishStateMachine(SEND_CONFIRM_KEY_MESSAGE, @@ -1789,34 +1814,51 @@ uint32_t emberAfKeyEstablishmentClusterServerCommandParse(sl_service_opcode_t op switch (cmd->commandId) { case ZCL_INITIATE_KEY_ESTABLISHMENT_REQUEST_COMMAND_ID: { - sl_zcl_key_establishment_cluster_initiate_key_establishment_request_command_t cmd_data; - zclStatus = zcl_decode_key_establishment_cluster_initiate_key_establishment_request_command(cmd, &cmd_data); - - if (zclStatus == EMBER_ZCL_STATUS_SUCCESS) { - emberAfKeyEstablishmentClusterInitiateKeyEstablishmentRequestCallback(cmd_data.keyEstablishmentSuite, - cmd_data.ephemeralDataGenerateTime, - cmd_data.confirmKeyGenerateTime, - cmd_data.identity); + uint16_t payloadOffset = cmd->payloadStartIndex; + if (cmd->bufLen < payloadOffset + INITIATE_KEY_ESTABLISHMENT_REQUEST_COMMAND_MIN_LENGTH) { + zclStatus = EMBER_ZCL_STATUS_MALFORMED_COMMAND; + } else { + sl_zcl_key_establishment_cluster_initiate_key_establishment_request_command_t cmd_data; + zclStatus = zcl_decode_key_establishment_cluster_initiate_key_establishment_request_command(cmd, &cmd_data); + + if (zclStatus == EMBER_ZCL_STATUS_SUCCESS) { + emberAfKeyEstablishmentClusterInitiateKeyEstablishmentRequestCallback(cmd_data.keyEstablishmentSuite, + cmd_data.ephemeralDataGenerateTime, + cmd_data.confirmKeyGenerateTime, + cmd_data.identity); + } } break; } case ZCL_EPHEMERAL_DATA_REQUEST_COMMAND_ID: { - sl_zcl_key_establishment_cluster_ephemeral_data_request_command_t cmd_data; - zclStatus = zcl_decode_key_establishment_cluster_ephemeral_data_request_command(cmd, &cmd_data); + // The minimum length for this command is 16 + 6 bytes + uint16_t payloadOffset = cmd->payloadStartIndex; + if (cmd->bufLen < payloadOffset + EPHEMERAL_DATA_REQUEST_COMMAND_MIN_LENGTH) { + zclStatus = EMBER_ZCL_STATUS_MALFORMED_COMMAND; + } else { + sl_zcl_key_establishment_cluster_ephemeral_data_request_command_t cmd_data; + zclStatus = zcl_decode_key_establishment_cluster_ephemeral_data_request_command(cmd, &cmd_data); - if (zclStatus == EMBER_ZCL_STATUS_SUCCESS) { - emberAfKeyEstablishmentClusterEphemeralDataRequestCallback(cmd_data.ephemeralData); + if (zclStatus == EMBER_ZCL_STATUS_SUCCESS) { + emberAfKeyEstablishmentClusterEphemeralDataRequestCallback(cmd_data.ephemeralData); + } } break; } case ZCL_CONFIRM_KEY_DATA_REQUEST_COMMAND_ID: { - sl_zcl_key_establishment_cluster_confirm_key_data_request_command_t cmd_data; - zclStatus = zcl_decode_key_establishment_cluster_confirm_key_data_request_command(cmd, &cmd_data); + // The minimum length for this command is 16 bytes + uint16_t payloadOffset = cmd->payloadStartIndex; + if (cmd->bufLen < payloadOffset + CONFIRM_KEY_DATA_REQUEST_COMMAND_MIN_LENGTH) { + zclStatus = EMBER_ZCL_STATUS_MALFORMED_COMMAND; + } else { + sl_zcl_key_establishment_cluster_confirm_key_data_request_command_t cmd_data; + zclStatus = zcl_decode_key_establishment_cluster_confirm_key_data_request_command(cmd, &cmd_data); - if (zclStatus == EMBER_ZCL_STATUS_SUCCESS) { - emberAfKeyEstablishmentClusterConfirmKeyDataRequestCallback(cmd_data.secureMessageAuthenticationCode); + if (zclStatus == EMBER_ZCL_STATUS_SUCCESS) { + emberAfKeyEstablishmentClusterConfirmKeyDataRequestCallback(cmd_data.secureMessageAuthenticationCode); + } } break; } @@ -1866,34 +1908,49 @@ uint32_t emberAfKeyEstablishmentClusterClientCommandParse(sl_service_opcode_t op } case ZCL_INITIATE_KEY_ESTABLISHMENT_RESPONSE_COMMAND_ID: { - sl_zcl_key_establishment_cluster_initiate_key_establishment_response_command_t cmd_data; - zclStatus = zcl_decode_key_establishment_cluster_initiate_key_establishment_response_command(cmd, &cmd_data); - - if (zclStatus == EMBER_ZCL_STATUS_SUCCESS) { - emberAfKeyEstablishmentClusterInitiateKeyEstablishmentResponseCallback(cmd_data.requestedKeyEstablishmentSuite, - cmd_data.ephemeralDataGenerateTime, - cmd_data.confirmKeyGenerateTime, - cmd_data.identity); + uint16_t payloadOffset = cmd->payloadStartIndex; + if (cmd->bufLen < payloadOffset + INITIATE_KEY_ESTABLISHMENT_RESPONSE_COMMAND_MIN_LENGTH) { + zclStatus = EMBER_ZCL_STATUS_MALFORMED_COMMAND; + } else { + sl_zcl_key_establishment_cluster_initiate_key_establishment_response_command_t cmd_data; + zclStatus = zcl_decode_key_establishment_cluster_initiate_key_establishment_response_command(cmd, &cmd_data); + + if (zclStatus == EMBER_ZCL_STATUS_SUCCESS) { + emberAfKeyEstablishmentClusterInitiateKeyEstablishmentResponseCallback(cmd_data.requestedKeyEstablishmentSuite, + cmd_data.ephemeralDataGenerateTime, + cmd_data.confirmKeyGenerateTime, + cmd_data.identity); + } } break; } case ZCL_EPHEMERAL_DATA_RESPONSE_COMMAND_ID: { - sl_zcl_key_establishment_cluster_ephemeral_data_response_command_t cmd_data; - zclStatus = zcl_decode_key_establishment_cluster_ephemeral_data_response_command(cmd, &cmd_data); + uint16_t payloadOffset = cmd->payloadStartIndex; + if (cmd->bufLen < payloadOffset + EPHEMERAL_DATA_RESPONSE_COMMAND_MIN_LENGTH) { + zclStatus = EMBER_ZCL_STATUS_MALFORMED_COMMAND; + } else { + sl_zcl_key_establishment_cluster_ephemeral_data_response_command_t cmd_data; + zclStatus = zcl_decode_key_establishment_cluster_ephemeral_data_response_command(cmd, &cmd_data); - if (zclStatus == EMBER_ZCL_STATUS_SUCCESS) { - emberAfKeyEstablishmentClusterEphemeralDataResponseCallback(cmd_data.ephemeralData); + if (zclStatus == EMBER_ZCL_STATUS_SUCCESS) { + emberAfKeyEstablishmentClusterEphemeralDataResponseCallback(cmd_data.ephemeralData); + } } break; } case ZCL_CONFIRM_KEY_DATA_RESPONSE_COMMAND_ID: { - sl_zcl_key_establishment_cluster_confirm_key_data_response_command_t cmd_data; - zclStatus = zcl_decode_key_establishment_cluster_confirm_key_data_response_command(cmd, &cmd_data); + uint16_t payloadOffset = cmd->payloadStartIndex; + if (cmd->bufLen < payloadOffset + CONFIRM_KEY_DATA_RESPONSE_COMMAND_MIN_LENGTH) { + zclStatus = EMBER_ZCL_STATUS_MALFORMED_COMMAND; + } else { + sl_zcl_key_establishment_cluster_confirm_key_data_response_command_t cmd_data; + zclStatus = zcl_decode_key_establishment_cluster_confirm_key_data_response_command(cmd, &cmd_data); - if (zclStatus == EMBER_ZCL_STATUS_SUCCESS) { - emberAfKeyEstablishmentClusterConfirmKeyDataResponseCallback(cmd_data.secureMessageAuthenticationCode); + if (zclStatus == EMBER_ZCL_STATUS_SUCCESS) { + emberAfKeyEstablishmentClusterConfirmKeyDataResponseCallback(cmd_data.secureMessageAuthenticationCode); + } } break; } diff --git a/protocol/zigbee/app/framework/plugin/manufacturing-library-cli/manufacturing-library-cli-host.c b/protocol/zigbee/app/framework/plugin/manufacturing-library-cli/manufacturing-library-cli-host.c index c701cef91a..024aa2669f 100644 --- a/protocol/zigbee/app/framework/plugin/manufacturing-library-cli/manufacturing-library-cli-host.c +++ b/protocol/zigbee/app/framework/plugin/manufacturing-library-cli/manufacturing-library-cli-host.c @@ -96,7 +96,8 @@ bool emberAfMfglibEnabled(void) #ifndef EMBER_TEST halCommonGetToken(&enabled, TOKEN_MFG_LIB_ENABLED); #else - return false; + // no op + enabled = true; #endif (void) emberSerialPrintf(APP_SERIAL, diff --git a/protocol/zigbee/app/framework/plugin/meter-mirror/meter-mirror.c b/protocol/zigbee/app/framework/plugin/meter-mirror/meter-mirror.c index 7054e98ed4..831bcc5de5 100644 --- a/protocol/zigbee/app/framework/plugin/meter-mirror/meter-mirror.c +++ b/protocol/zigbee/app/framework/plugin/meter-mirror/meter-mirror.c @@ -22,6 +22,7 @@ #ifdef UC_BUILD #include "meter-mirror-config.h" #include "sl_component_catalog.h" +#include "zap-cluster-command-parser.h" #else // !UC_BUILD #ifdef EMBER_AF_PLUGIN_GBCS_COMPATIBILITY #define SL_CATALOG_ZIGBEE_GBCS_COMPATIBILITY_PRESENT @@ -265,6 +266,7 @@ uint16_t emberAfPluginMeterMirrorRequestMirror(EmberEUI64 requestingDeviceIeeeAd return endpoint; } +#ifndef UC_BUILD bool emberAfSimpleMeteringClusterConfigureMirrorCallback(uint32_t issuerEventId, uint32_t reportingInterval, uint8_t mirrorNotificationReporting, @@ -310,6 +312,7 @@ bool emberAfSimpleMeteringClusterConfigureMirrorCallback(uint32_t issuerEventId, emberAfSendImmediateDefaultResponse(status); return true; } +#endif // UC_BUILD uint16_t emberAfPluginSimpleMeteringClientRemoveMirrorCallback(EmberEUI64 requestingDeviceIeeeAddress) { @@ -543,3 +546,82 @@ static bool sendMirrorReportAttributeResponse(uint8_t endpoint, uint8_t index) emberAfSendResponse(); return true; } + +#ifdef UC_BUILD + +bool emberAfSimpleMeteringClusterConfigureMirrorCallback(EmberAfClusterCommand *cmd) +{ + sl_zcl_simple_metering_cluster_configure_mirror_command_t cmd_data; + + if (zcl_decode_simple_metering_cluster_configure_mirror_command(cmd, &cmd_data) + != EMBER_ZCL_STATUS_SUCCESS) { + return false; + } + + uint32_t issuerEventId = cmd_data.issuerEventId; + uint32_t reportingInterval = cmd_data.reportingInterval; + uint8_t mirrorNotificationReporting = cmd_data.mirrorNotificationReporting; + uint8_t notificationScheme = cmd_data.notificationScheme; + EmberAfStatus status = EMBER_ZCL_STATUS_SUCCESS; + uint8_t endpoint = emberAfCurrentEndpoint(); + EmberEUI64 sendersEui; + uint8_t index; + + emberAfSimpleMeteringClusterPrintln("ConfigureMirror on endpoint 0x%x", endpoint); + + if (EMBER_SUCCESS != emberLookupEui64ByNodeId(emberAfCurrentCommand()->source, sendersEui)) { + emberAfSimpleMeteringClusterPrintln("Error: Meter Mirror plugin cannot determine EUI64 for node ID 0x%2X", + emberAfCurrentCommand()->source); + status = EMBER_ZCL_STATUS_FAILURE; + goto kickout; + } + + index = findMirrorIndex(sendersEui); + if (index == INVALID_INDEX) { + emberAfSimpleMeteringClusterPrint("Error: Meter mirror plugin received unknown report from "); + emberAfPrintBigEndianEui64(sendersEui); + emberAfSimpleMeteringClusterPrintln(""); + status = EMBER_ZCL_STATUS_NOT_AUTHORIZED; + goto kickout; + } + + if (mirrorList[index].issuerEventId == 0 + || issuerEventId > mirrorList[index].issuerEventId) { + if (notificationScheme > 0x02) { + status = EMBER_ZCL_STATUS_INVALID_FIELD; + goto kickout; + } + + mirrorList[index].issuerEventId = issuerEventId; + mirrorList[index].reportingInterval = reportingInterval; + mirrorList[index].mirrorNotificationReporting = mirrorNotificationReporting; + mirrorList[index].notificationScheme = notificationScheme; + } + + kickout: + emberAfSendImmediateDefaultResponse(status); + return true; +} + +uint32_t emAfMeterMirrorSimpleMeteringClusterClientCommandParse(sl_service_opcode_t opcode, + sl_service_function_context_t *context) +{ + (void)opcode; + + EmberAfClusterCommand *cmd = (EmberAfClusterCommand *)context->data; + bool wasHandled = false; + + if (!cmd->mfgSpecific) { + switch (cmd->commandId) { + case ZCL_CONFIGURE_MIRROR_COMMAND_ID: + { + wasHandled = emberAfSimpleMeteringClusterConfigureMirrorCallback(cmd); + break; + } + } + } + return ((wasHandled) + ? EMBER_ZCL_STATUS_SUCCESS + : EMBER_ZCL_STATUS_UNSUP_COMMAND); +} +#endif // UC_BUILD diff --git a/protocol/zigbee/app/framework/plugin/meter-snapshot-server/meter-snapshot-server-cli.c b/protocol/zigbee/app/framework/plugin/meter-snapshot-server/meter-snapshot-server-cli.c index 071eb7f405..0b502e6ec8 100644 --- a/protocol/zigbee/app/framework/plugin/meter-snapshot-server/meter-snapshot-server-cli.c +++ b/protocol/zigbee/app/framework/plugin/meter-snapshot-server/meter-snapshot-server-cli.c @@ -41,7 +41,7 @@ void emAfMeterSnapshotServerCliPublish(sl_cli_command_arg_t *arguments) uint8_t dstEndpoint = sl_cli_get_argument_uint8(arguments, 2); uint32_t startTime = sl_cli_get_argument_uint32(arguments, 3); uint32_t endTime = sl_cli_get_argument_uint32(arguments, 4); - uint32_t offset = sl_cli_get_argument_uint32(arguments, 5); + uint8_t offset = sl_cli_get_argument_uint8(arguments, 5); uint32_t cause = sl_cli_get_argument_uint32(arguments, 6); uint8_t snapshotCriteria[13]; diff --git a/protocol/zigbee/app/framework/plugin/network-creator-security/config/network-creator-security-config.h b/protocol/zigbee/app/framework/plugin/network-creator-security/config/network-creator-security-config.h index 6297d321f0..f6827cbd26 100644 --- a/protocol/zigbee/app/framework/plugin/network-creator-security/config/network-creator-security-config.h +++ b/protocol/zigbee/app/framework/plugin/network-creator-security/config/network-creator-security-config.h @@ -23,11 +23,6 @@ // The time, in seconds, that the network will remain open. #define EMBER_AF_PLUGIN_NETWORK_CREATOR_SECURITY_NETWORK_OPEN_TIME_S 300 -// Trust Center Support -// Default: TRUE -// Set this option to true to include trust center security support in this plugin. If the option is set to false, then the application will only support creating distributed security networks. -#define EMBER_AF_PLUGIN_NETWORK_CREATOR_SECURITY_TRUST_CENTER_SUPPORT 1 - // Allow Home Automation Devices to remain on network (non-compliant) // Default: TRUE // Set this option to allow Home Automation devices to remain on the network after joining. diff --git a/protocol/zigbee/app/framework/plugin/network-creator-security/network-creator-security.c b/protocol/zigbee/app/framework/plugin/network-creator-security/network-creator-security.c index a9bb0679bc..608fafbd61 100644 --- a/protocol/zigbee/app/framework/plugin/network-creator-security/network-creator-security.c +++ b/protocol/zigbee/app/framework/plugin/network-creator-security/network-creator-security.c @@ -27,9 +27,6 @@ #ifdef UC_BUILD #include "network-creator-security-config.h" #include "sl_component_catalog.h" -#if (EMBER_AF_PLUGIN_NETWORK_CREATOR_SECURITY_TRUST_CENTER_SUPPORT == 1) -#define TRUST_CENTER_SUPPORT -#endif #if (EMBER_AF_PLUGIN_NETWORK_CREATOR_SECURITY_ALLOW_HA_DEVICES_TO_STAY == 1) #define ALLOW_HA_DEVICES_TO_STAY #endif @@ -40,9 +37,6 @@ #define ALLOW_TC_REJOIN_WITH_WELL_KNOWN_KEY #endif #else // !UC_BUILD -#ifdef EMBER_AF_PLUGIN_NETWORK_CREATOR_SECURITY_TRUST_CENTER_SUPPORT -#define TRUST_CENTER_SUPPORT -#endif #ifdef EMBER_AF_PLUGIN_NETWORK_CREATOR_SECURITY_ALLOW_HA_DEVICES_TO_STAY #define ALLOW_HA_DEVICES_TO_STAY #endif @@ -160,7 +154,7 @@ void emAfPluginNetworkCreatorSecurityStackStatusCallback(EmberStatus status) void emberAfPluginNetworkCreatorSecurityStackStatusCallback(EmberStatus status) #endif { -#ifdef TRUST_CENTER_SUPPORT +#ifdef EMBER_AF_HAS_COORDINATOR_NETWORK if (status == EMBER_NETWORK_UP && emberAfGetNodeId() == EMBER_TRUST_CENTER_NODE_ID) { EmberExtendedSecurityBitmask extended; @@ -179,13 +173,13 @@ void emberAfPluginNetworkCreatorSecurityStackStatusCallback(EmberStatus status) extended |= EMBER_NWK_LEAVE_REQUEST_NOT_ALLOWED; emberSetExtendedSecurityBitmask(extended); } -#endif /* TRUST_CENTER_SUPPORT */ +#endif /* EMBER_AF_HAS_COORDINATOR_NETWORK */ } // ----------------------------------------------------------------------------- // Stack Callbacks -#if (defined(TRUST_CENTER_SUPPORT) || defined(SL_CATALOG_ZIGBEE_TEST_HARNESS_Z3_PRESENT)) +#if (defined(EMBER_AF_HAS_COORDINATOR_NETWORK) || defined(SL_CATALOG_ZIGBEE_TEST_HARNESS_Z3_PRESENT)) static bool isWildcardEui64(EmberEUI64 eui64) { for (uint8_t i = 0; i < EUI64_SIZE; i++) { @@ -195,7 +189,7 @@ static bool isWildcardEui64(EmberEUI64 eui64) } return true; } -#endif // defined(TRUST_CENTER_SUPPORT) || defined(SL_CATALOG_ZIGBEE_TEST_HARNESS_Z3_PRESENT) +#endif // defined(EMBER_AF_HAS_COORDINATOR_NETWORK) || defined(SL_CATALOG_ZIGBEE_TEST_HARNESS_Z3_PRESENT) #if defined(SL_CATALOG_ZIGBEE_TEST_HARNESS_Z3_PRESENT) extern uint8_t emAfPluginTestHarnessZ3ServerMaskHigh; @@ -204,7 +198,7 @@ extern uint8_t emAfPluginTestHarnessZ3ServerMaskHigh; void emberAfPluginNetworkCreatorSecurityZigbeeKeyEstablishmentCallback(EmberEUI64 eui64, EmberKeyStatus keyStatus) { -#if (defined(TRUST_CENTER_SUPPORT) || defined(SL_CATALOG_ZIGBEE_TEST_HARNESS_Z3_PRESENT)) +#if (defined(EMBER_AF_HAS_COORDINATOR_NETWORK) || defined(SL_CATALOG_ZIGBEE_TEST_HARNESS_Z3_PRESENT)) // If we are notified that a joining node failed to verify their // TCLK properly, then we are going to kick them off the network, // as they pose a potential security hazard. @@ -234,7 +228,7 @@ void emberAfPluginNetworkCreatorSecurityZigbeeKeyEstablishmentCallback(EmberEUI6 destinationId, status); } -#endif // defined(TRUST_CENTER_SUPPORT) || defined(SL_CATALOG_ZIGBEE_TEST_HARNESS_Z3_PRESENT) +#endif // defined(EMBER_AF_HAS_COORDINATOR_NETWORK) || defined(SL_CATALOG_ZIGBEE_TEST_HARNESS_Z3_PRESENT) } // ----------------------------------------------------------------------------- @@ -263,7 +257,7 @@ EmberStatus emberAfPluginNetworkCreatorSecurityStart(bool centralizedNetwork) // Use distributed trust center mode. state.bitmask |= EMBER_DISTRIBUTED_TRUST_CENTER_MODE; } -#if (defined(TRUST_CENTER_SUPPORT) || defined(SL_CATALOG_ZIGBEE_TEST_HARNESS_Z3_PRESENT)) +#if (defined(EMBER_AF_HAS_COORDINATOR_NETWORK) || defined(SL_CATALOG_ZIGBEE_TEST_HARNESS_Z3_PRESENT)) else { // centralizedNetwork // Generate a random global link key. // This is the key the trust center will send to a joining node when it @@ -279,7 +273,13 @@ EmberStatus emberAfPluginNetworkCreatorSecurityStart(bool centralizedNetwork) // Tell the trust center to ignore leave requests. extended |= EMBER_NWK_LEAVE_REQUEST_NOT_ALLOWED; } -#endif // defined(TRUST_CENTER_SUPPORT) || defined(SL_CATALOG_ZIGBEE_TEST_HARNESS_Z3_PRESENT) +#else + else { // centralizedNetwork + // in case device doesn't support centralized network we should return EMBER_INVALID_CALL immediately + status = EMBER_INVALID_CALL; + goto kickout; + } +#endif // defined(EMBER_AF_HAS_COORDINATOR_NETWORK) || defined(SL_CATALOG_ZIGBEE_TEST_HARNESS_Z3_PRESENT) // Generate a random network key. status = emberAfGenerateRandomKey(&(state.networkKey)); @@ -324,13 +324,13 @@ EmberStatus emberAfPluginNetworkCreatorSecurityOpenNetwork(void) setTcRejoinsUsingWellKnownKeyAllowed(true); #endif - #if (defined(TRUST_CENTER_SUPPORT) || defined(SL_CATALOG_ZIGBEE_TEST_HARNESS_Z3_PRESENT)) + #if (defined(EMBER_AF_HAS_COORDINATOR_NETWORK) || defined(SL_CATALOG_ZIGBEE_TEST_HARNESS_Z3_PRESENT)) if (emberAfGetNodeId() == EMBER_TRUST_CENTER_NODE_ID) { EmberEUI64 wildcardEui64 = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, }; EmberKeyData centralizedKey = ZIGBEE_3_CENTRALIZED_SECURITY_LINK_KEY; status = emberAddTransientLinkKey(wildcardEui64, ¢ralizedKey); } - #endif // defined(TRUST_CENTER_SUPPORT) || defined(SL_CATALOG_ZIGBEE_TEST_HARNESS_Z3_PRESENT) + #endif // defined(EMBER_AF_HAS_COORDINATOR_NETWORK) || defined(SL_CATALOG_ZIGBEE_TEST_HARNESS_Z3_PRESENT) } if (status == EMBER_SUCCESS) { @@ -373,11 +373,11 @@ EmberStatus emberAfPluginNetworkCreatorSecurityOpenNetworkWithKeyPair(EmberEUI64 return EMBER_ERR_FATAL; } -#if (defined(TRUST_CENTER_SUPPORT) || defined(SL_CATALOG_ZIGBEE_TEST_HARNESS_Z3_PRESENT)) +#if (defined(EMBER_AF_HAS_COORDINATOR_NETWORK) || defined(SL_CATALOG_ZIGBEE_TEST_HARNESS_Z3_PRESENT)) if (emberAfGetNodeId() == EMBER_TRUST_CENTER_NODE_ID) { status = emberAddTransientLinkKey(eui64, &keyData); } -#endif // defined(TRUST_CENTER_SUPPORT) || defined(SL_CATALOG_ZIGBEE_TEST_HARNESS_Z3_PRESENT) +#endif // defined(EMBER_AF_HAS_COORDINATOR_NETWORK) || defined(SL_CATALOG_ZIGBEE_TEST_HARNESS_Z3_PRESENT) if (status == EMBER_SUCCESS) { openNetworkTimeRemainingS = NETWORK_OPEN_TIME_S; diff --git a/protocol/zigbee/app/framework/plugin/network-creator/network-creator.c b/protocol/zigbee/app/framework/plugin/network-creator/network-creator.c index c9d3c3f864..a5535bfd51 100644 --- a/protocol/zigbee/app/framework/plugin/network-creator/network-creator.c +++ b/protocol/zigbee/app/framework/plugin/network-creator/network-creator.c @@ -163,7 +163,7 @@ EmberStatus emberAfPluginNetworkCreatorNetworkForm(bool centralizedNetwork, status = emberAfPluginNetworkCreatorSecurityStart(centralizedNetwork); if (status == EMBER_SUCCESS) { - status = emberFormNetwork(&networkParameters); + status = emberAfFormNetwork(&networkParameters); emberAfCorePrintln("%p: Form. Channel: %d. Status: 0x%X", EMBER_AF_PLUGIN_NETWORK_CREATOR_PLUGIN_NAME, channel, @@ -229,7 +229,7 @@ static EmberStatus tryToFormNetwork(void) // Try to form the network. networkParameters.radioChannel = channel; - status = emberFormNetwork(&networkParameters); + status = emberAfFormNetwork(&networkParameters); emberAfCorePrintln("%p: Form. Channel: %d. Status: 0x%X", EMBER_AF_PLUGIN_NETWORK_CREATOR_PLUGIN_NAME, channel, diff --git a/protocol/zigbee/app/framework/plugin/ota-storage-posix-filesystem/ota-storage-linux-simulation.c b/protocol/zigbee/app/framework/plugin/ota-storage-posix-filesystem/ota-storage-linux-simulation.c index 8e1778b149..74cbf3999d 100644 --- a/protocol/zigbee/app/framework/plugin/ota-storage-posix-filesystem/ota-storage-linux-simulation.c +++ b/protocol/zigbee/app/framework/plugin/ota-storage-posix-filesystem/ota-storage-linux-simulation.c @@ -33,6 +33,7 @@ #define INVALID_DEVICE_ID 0xFFFF #define INVALID_FIRMWARE_VERSION 0xFFFFFFFFL #define INVALID_EUI64 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define INVALID_SLOT (uint32_t)-1 #define INVALID_OTA_IMAGE_ID \ { INVALID_MANUFACTURER_ID, \ @@ -124,3 +125,15 @@ EmberAfOtaImageId emberAfOtaStorageSearchCallback(uint16_t manufacturerId, { return emberInvalidImageId; } + +uint32_t emAfOtaStorageGetSlot(void) +{ + return INVALID_SLOT; +} + +uint32_t emberAfOtaStorageDriverMaxDownloadSizeCallback(void) +{ + // In theory we are limited by the local disk space, but for now + // assume there is no limit. + return 0xFFFFFFFFUL; +} diff --git a/protocol/zigbee/app/framework/plugin/reporting/reporting.c b/protocol/zigbee/app/framework/plugin/reporting/reporting.c index 16547a57a0..0d1c2687c8 100644 --- a/protocol/zigbee/app/framework/plugin/reporting/reporting.c +++ b/protocol/zigbee/app/framework/plugin/reporting/reporting.c @@ -46,7 +46,18 @@ static void retrySendReport(EmberOutgoingMessageType type, uint8_t *message, EmberStatus status); static uint32_t computeStringHash(uint8_t *data, uint8_t length); - +static EmberStatus readAttributeAndGetLastValue(const EmberAfPluginReportingEntry* const entry, + uint8_t entryIndex, + EmberAfAttributeType* pDataType, + uint16_t* pDataSize, + uint8_t* pReadData, + uint16_t readDataSize, + bool reportChange); +static void markReportTableChange(uint8_t *dataRef, + uint8_t dataSize, + EmberAfAttributeType dataType, + const EmberAfPluginReportingEntry* const entry, + uint8_t entryIndex); #ifdef UC_BUILD sl_zigbee_event_t emberAfPluginReportingTickEvent; #define tickEvent (&emberAfPluginReportingTickEvent) @@ -258,38 +269,11 @@ void emberAfPluginReportingTickEventHandler(SLXU_UC_EVENT) * MILLISECOND_TICKS_PER_SECOND))))) { continue; } - - status = emAfReadAttribute(entry.endpoint, - entry.clusterId, - entry.attributeId, - entry.mask, - entry.manufacturerCode, - (uint8_t *)&readData, - READ_DATA_SIZE, - &dataType); + status = readAttributeAndGetLastValue(&entry, i, &dataType, &dataSize, readData, READ_DATA_SIZE, false); if (status != EMBER_ZCL_STATUS_SUCCESS) { - emberAfReportingPrintln("ERR: reading cluster 0x%2x attribute 0x%2x: 0x%x", - entry.clusterId, - entry.attributeId, - status); - goto skipAttribute; - } - - if (emberAfIsLongStringAttributeType(dataType)) { - // LONG string types are rarely used and even more rarely (never?) - // reported; ignore and leave ensuing handling of other types unchanged. - emberAfReportingPrintln("ERR: reporting of LONG string attribute type not supported: cluster 0x%2x attribute 0x%2x", - entry.clusterId, - entry.attributeId); goto skipAttribute; } - // find size of current report - dataSize = emberAfAttributeValueSize(dataType, readData, sizeof(readData)); - if (dataSize == 0) { - goto skipAttribute; // defensive; read attribute above should have failed - } - reportSize = sizeof(entry.attributeId) + sizeof(dataType) + dataSize; // If we have already started a report for a different attribute or @@ -364,33 +348,6 @@ void emberAfPluginReportingTickEventHandler(SLXU_UC_EVENT) emberAfPutBlockInResp(readData, dataSize); #endif - // Store the current attribute value for comparison with future values - // to detect reportable changes. Use the actual attribute value for - // data types that are small enough to efficiently store; for string - // types, substitute a 32-bit hash of the string value. - uint32_t stringHash = 0; - uint8_t *copyData = readData; - uint8_t copySize = dataSize; - if (dataType == ZCL_OCTET_STRING_ATTRIBUTE_TYPE || dataType == ZCL_CHAR_STRING_ATTRIBUTE_TYPE) { - // dataSize was set above to count the string's length byte, in addition to string length. - // Compute hash on string value only. - stringHash = computeStringHash(readData + 1, dataSize - 1); - copyData = (uint8_t *)&stringHash; - copySize = sizeof(stringHash); - } - if (copySize <= sizeof(emAfPluginReportVolatileData[i].lastReportValue)) { - emAfPluginReportVolatileData[i].lastReportValue = 0; -#if (BIGENDIAN_CPU) - MEMMOVE(((uint8_t *)&emAfPluginReportVolatileData[i].lastReportValue - + sizeof(emAfPluginReportVolatileData[i].lastReportValue) - - copySize), - copyData, - copySize); -#else - MEMMOVE(&emAfPluginReportVolatileData[i].lastReportValue, copyData, copySize); -#endif - } - // Normally will arrive here at the conclusion of attribute processing. // Update the state used to decide if an attribute value is ready to // be reported. The shortest and longest intervals between reports for @@ -773,6 +730,140 @@ EmberStatus emAfPluginReportingRemoveEntry(uint16_t index) return status; } +// This function will check all entries in report table and update +// lastReportValue field with current value of attributes +void emAfPluginReportingGetLastValueAll(void) +{ + uint16_t i; + for (i = 0; i < reportTableActiveLength; i++) { + EmberAfPluginReportingEntry entry; + emAfPluginReportingGetEntry(i, &entry); + if (emberAfEndpointIsEnabled(entry.endpoint) + && entry.direction == EMBER_ZCL_REPORTING_DIRECTION_REPORTED) { + readAttributeAndGetLastValue(&entry, i, NULL, NULL, NULL, 0, true); + } + } + scheduleTick(); +} + +static void markReportTableChange(uint8_t *dataRef, + uint8_t dataSize, + EmberAfAttributeType dataType, + const EmberAfPluginReportingEntry* const entry, + uint8_t entryIndex) +{ + // If we are reporting this particular attribute, we only care whether + // the new value meets the reportable change criteria. If it does, we + // mark the entry as ready to report and reschedule the tick. Whether + // the tick will be scheduled for immediate or delayed execution depends + // on the minimum reporting interval. This is handled in the scheduler. + EmberAfDifferenceType difference + = emberAfGetDifference(dataRef, + emAfPluginReportVolatileData[entryIndex].lastReportValue, + dataSize); + uint8_t analogOrDiscrete = emberAfGetAttributeAnalogOrDiscreteType(dataType); + if ((analogOrDiscrete == EMBER_AF_DATA_TYPE_DISCRETE && difference != 0) + || (analogOrDiscrete == EMBER_AF_DATA_TYPE_ANALOG + && entry->data.reported.reportableChange <= difference)) { + emAfPluginReportVolatileData[entryIndex].reportableChange = true; + scheduleTick(); + } +} + +// This function will check specified entry in report table and update +// lastReportValue field with current value of attribute +static EmberStatus readAttributeAndGetLastValue(const EmberAfPluginReportingEntry* const entry, + uint8_t entryIndex, + EmberAfAttributeType* pDataType, + uint16_t* pDataSize, + uint8_t* pReadData, + uint16_t readDataSize, + bool reportChange) +{ + uint8_t readData[READ_DATA_SIZE]; + uint16_t dataSize; + EmberAfAttributeType dataType; + + EmberStatus status = emAfReadAttribute(entry->endpoint, + entry->clusterId, + entry->attributeId, + entry->mask, + entry->manufacturerCode, + readData, + READ_DATA_SIZE, + &dataType); + + if (status != EMBER_ZCL_STATUS_SUCCESS) { + emberAfReportingPrintln("ERR: reading cluster 0x%2x attribute 0x%2x: 0x%x", + entry->clusterId, + entry->attributeId, + status); + return status; + } + + if (emberAfIsLongStringAttributeType(dataType)) { + // LONG string types are rarely used and even more rarely (never?) + // reported; ignore and leave ensuing handling of other types unchanged. + emberAfReportingPrintln("ERR: reporting of LONG string attribute type not supported: cluster 0x%2x attribute 0x%2x", + entry->clusterId, + entry->attributeId); + return EMBER_ZCL_STATUS_INVALID_DATA_TYPE; + } + + // find size of current report + dataSize = emberAfAttributeValueSize(dataType, readData, READ_DATA_SIZE); + if (dataSize == 0 || (pReadData != NULL && dataSize > readDataSize)) { + return EMBER_ZCL_STATUS_FAILURE; // defensive; read attribute above should have failed + } + + // Store the current attribute value for comparison with future values + // to detect reportable changes. Use the actual attribute value for + // data types that are small enough to efficiently store; for string + // types, substitute a 32-bit hash of the string value. + uint32_t stringHash = 0; + uint8_t *copyData = readData; + uint8_t copySize = dataSize; + if (dataType == ZCL_OCTET_STRING_ATTRIBUTE_TYPE || dataType == ZCL_CHAR_STRING_ATTRIBUTE_TYPE) { + // dataSize was set above to count the string's length byte, in addition to string length. + // Compute hash on string value only. + stringHash = computeStringHash(readData + 1, dataSize - 1); + copyData = (uint8_t *)&stringHash; + copySize = sizeof(stringHash); + } + + // If need to report attribute change, calculate the difference and schedule to send reportAttributes + if (reportChange) { + markReportTableChange(readData, copySize, dataType, entry, entryIndex); + // The lastReportValue will be updated later in emberAfPluginReportingTickEventHandler + return EMBER_ZCL_STATUS_SUCCESS; + } + + if (copySize <= sizeof(emAfPluginReportVolatileData[entryIndex].lastReportValue)) { + emAfPluginReportVolatileData[entryIndex].lastReportValue = 0; +#if (BIGENDIAN_CPU) + MEMMOVE(((uint8_t *)&emAfPluginReportVolatileData[entryIndex].lastReportValue + + sizeof(emAfPluginReportVolatileData[entryIndex].lastReportValue) + - copySize), + copyData, + copySize); +#else + MEMMOVE(&emAfPluginReportVolatileData[entryIndex].lastReportValue, copyData, copySize); +#endif + } + + if (pDataType != NULL) { + *pDataType = dataType; + } + if (pDataSize != NULL) { + *pDataSize = dataSize; + } + if (pReadData != NULL) { + memcpy(pReadData, readData, dataSize); + } + + return EMBER_ZCL_STATUS_SUCCESS; +} + void emberAfReportingAttributeChangeCallback(uint8_t endpoint, EmberAfClusterId clusterId, EmberAfAttributeId attributeId, @@ -802,22 +893,7 @@ void emberAfReportingAttributeChangeCallback(uint8_t endpoint, dataRef = (uint8_t *)&stringHash; dataSize = sizeof(stringHash); } - // If we are reporting this particular attribute, we only care whether - // the new value meets the reportable change criteria. If it does, we - // mark the entry as ready to report and reschedule the tick. Whether - // the tick will be scheduled for immediate or delayed execution depends - // on the minimum reporting interval. This is handled in the scheduler. - EmberAfDifferenceType difference - = emberAfGetDifference(dataRef, - emAfPluginReportVolatileData[i].lastReportValue, - dataSize); - uint8_t analogOrDiscrete = emberAfGetAttributeAnalogOrDiscreteType(type); - if ((analogOrDiscrete == EMBER_AF_DATA_TYPE_DISCRETE && difference != 0) - || (analogOrDiscrete == EMBER_AF_DATA_TYPE_ANALOG - && entry.data.reported.reportableChange <= difference)) { - emAfPluginReportVolatileData[i].reportableChange = true; - scheduleTick(); - } + markReportTableChange(dataRef, dataSize, type, &entry, i); break; } } @@ -1051,9 +1127,11 @@ EmberAfStatus emberAfPluginReportingConfigureReportedAttribute(const EmberAfPlug if (index == reportTableActiveLength) { reportTableActiveLength++; } + // Always update the lastReportTimeMs and lastReportValue when the entry is updated or newly added emAfPluginReportVolatileData[index].lastReportTimeMs = halCommonGetInt32uMillisecondTick(); - emAfPluginReportVolatileData[index].lastReportValue = 0; - + if (readAttributeAndGetLastValue(&entry, index, NULL, NULL, NULL, 0, false) != EMBER_ZCL_STATUS_SUCCESS) { + emAfPluginReportVolatileData[index].lastReportValue = 0; + } emAfPluginReportingSetEntry(index, &entry); scheduleTick(); } diff --git a/protocol/zigbee/app/framework/plugin/reporting/reporting.h b/protocol/zigbee/app/framework/plugin/reporting/reporting.h index ae79d10395..2ff3cd1942 100644 --- a/protocol/zigbee/app/framework/plugin/reporting/reporting.h +++ b/protocol/zigbee/app/framework/plugin/reporting/reporting.h @@ -193,5 +193,5 @@ uint16_t emAfPluginReportingConditionallyAddReportingEntry(EmberAfPluginReportin uint16_t emAfPluginReportingNumEntries(void); uint16_t emAfPluginReportingAppendEntry(EmberAfPluginReportingEntry* newEntry); - +void emAfPluginReportingGetLastValueAll(void); #endif //REPORTING_H diff --git a/protocol/zigbee/app/framework/plugin/sleepy-message-queue/sleepy-message-queue.c b/protocol/zigbee/app/framework/plugin/sleepy-message-queue/sleepy-message-queue.c index c9743b8557..bb8ada68a6 100644 --- a/protocol/zigbee/app/framework/plugin/sleepy-message-queue/sleepy-message-queue.c +++ b/protocol/zigbee/app/framework/plugin/sleepy-message-queue/sleepy-message-queue.c @@ -62,7 +62,30 @@ enum { //------------------------------------------------------------------------------ -void emberAfPluginSleepyMessageQueueInitCallback() +#ifdef UC_BUILD +void emberAfPluginSleepyMessageQueueInitCallback(uint8_t init_level) +{ + switch (init_level) { + case SL_ZIGBEE_INIT_LEVEL_EVENT: + { + slxu_zigbee_event_init(&emberAfPluginSleepyMessageQueueTimeoutEvent, + emberAfPluginSleepyMessageQueueTimeoutEventHandler); + break; + } + case SL_ZIGBEE_INIT_LEVEL_LOCAL_DATA: + { + // Initialize sleepy buffer plugin. + uint8_t x; + for ( x = 0; x < SLEEPY_MSG_QUEUE_NUM_ENTRIES; x++ ) { + emSleepyMessageQueueInitEntry(x); + } + emberAfAppPrintln("Initialized Sleepy Message Queue"); + break; + } + } +} +#else // !UC_BUILD +void emberAfPluginSleepyMessageQueueInitCallback(void) { slxu_zigbee_event_init(msgTimeoutEvent, emberAfPluginSleepyMessageQueueTimeoutEventHandler); @@ -73,6 +96,7 @@ void emberAfPluginSleepyMessageQueueInitCallback() } emberAfAppPrintln("Initialized Sleepy Message Queue"); } +#endif // UC_BUILD static void emSleepyMessageQueueInitEntry(uint8_t x) { diff --git a/protocol/zigbee/app/framework/plugin/sleepy-message-queue/sleepy-message-queue.h b/protocol/zigbee/app/framework/plugin/sleepy-message-queue/sleepy-message-queue.h index bd6f23daeb..befae7cdb7 100644 --- a/protocol/zigbee/app/framework/plugin/sleepy-message-queue/sleepy-message-queue.h +++ b/protocol/zigbee/app/framework/plugin/sleepy-message-queue/sleepy-message-queue.h @@ -145,11 +145,22 @@ void emberAfPluginSleepyMessageQueueRemoveAllMessages(EmberEUI64 dstEui64); * @{ */ +#ifdef UC_BUILD +/** + * @brief Initialize the sleepy message queue. + * + * @param init_level Initialize event and local data + * - SL_ZIGBEE_INIT_LEVEL_EVENT (0x00) + * - SL_ZIGBEE_INIT_LEVEL_LOCAL_DATA (0x01) + **/ +void emberAfPluginSleepyMessageQueueInitCallback(uint8_t init_level); +#else // !UC_BUILD /** * @brief Initialize the sleepy message queue. * **/ void emberAfPluginSleepyMessageQueueInitCallback(void); +#endif // UC_BUILD /** @brief Message time out. * diff --git a/protocol/zigbee/app/framework/plugin/smart-energy-registration/smart-energy-registration.c b/protocol/zigbee/app/framework/plugin/smart-energy-registration/smart-energy-registration.c index 6a7bb4185a..83a74501a3 100644 --- a/protocol/zigbee/app/framework/plugin/smart-energy-registration/smart-energy-registration.c +++ b/protocol/zigbee/app/framework/plugin/smart-energy-registration/smart-energy-registration.c @@ -16,6 +16,16 @@ * ******************************************************************************/ +#ifdef UC_BUILD +#ifdef SL_COMPONENT_CATALOG_PRESENT +#include "sl_component_catalog.h" +#endif // SL_COMPONENT_CATALOG_PRESENT +#else // !UC_BUILD +#ifdef EMBER_AF_PLUGIN_TEST_HARNESS +#define SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT +#endif // EMBER_AF_PLUGIN_TEST_HARNESS +#endif // UC_BUILD + #include "app/framework/include/af.h" #include "app/framework/util/af-main.h" //emberAfIsFullSmartEnergySecurityPresent #include "app/util/zigbee-framework/zigbee-device-common.h" //emberBindRequest @@ -26,7 +36,9 @@ #endif //EZSP_HOST #include "smart-energy-registration.h" +#ifdef SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT #include "app/framework/plugin/test-harness/test-harness.h" +#endif // SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT #include "app/framework/plugin/esi-management/esi-management.h" @@ -249,9 +261,11 @@ EmberStatus emberAfRegistrationStartCallback(void) return EMBER_INVALID_CALL; } +#ifdef SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT if (!emAfTestHarnessAllowRegistration) { return EMBER_SECURITY_CONFIGURATION_INVALID; } +#endif // SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT // Registration is unnecessary for the trust center. For other nodes, wait // for the network broadcast traffic to die down and neighbor information to diff --git a/protocol/zigbee/app/framework/plugin/test-harness/config/test-harness-config.h b/protocol/zigbee/app/framework/plugin/test-harness/config/test-harness-config.h index b29e5c57e4..04864a2902 100644 --- a/protocol/zigbee/app/framework/plugin/test-harness/config/test-harness-config.h +++ b/protocol/zigbee/app/framework/plugin/test-harness/config/test-harness-config.h @@ -23,6 +23,13 @@ // This enables or disables whether Smart Energy registration automatically starts after joining or rebooting. Without this plugin the normal behavior is to start registration. #define EMBER_AF_PLUGIN_TEST_HARNESS_AUTO_REGISTRATION_START 1 +// Test configuration for trust center swap out test. +// Default: FALSE +// For testing purposes only, when set to 1, it suppresses, the normal call to emberNetworkInit() at reboot. +// This allows to call manual network initialization later and prevent the node from immediately coming back up on the network after reboot. +// This enables corresponding CLI command to initialize the network at later point in tests. +#define EMBER_AF_TC_SWAP_OUT_TEST 0 + // // <<< end of configuration section >>> diff --git a/protocol/zigbee/app/framework/plugin/trust-center-backup/trust-center-backup-cli-posix.c b/protocol/zigbee/app/framework/plugin/trust-center-backup/trust-center-backup-cli-posix.c index 8361eec52f..5043361710 100644 --- a/protocol/zigbee/app/framework/plugin/trust-center-backup/trust-center-backup-cli-posix.c +++ b/protocol/zigbee/app/framework/plugin/trust-center-backup/trust-center-backup-cli-posix.c @@ -97,7 +97,9 @@ static void getFilePathFromCommandLine(sl_cli_command_arg_t *arguments, uint8_t* void emAfTrustCenterBackupRestoreResetNodeCli(sl_cli_command_arg_t *arguments) { (void)arguments; +#if defined EZSP_HOST ezspResetNode(); +#endif } void emAfTrustCenterBackupWriteNcpTokenToZigbeedTokensCli(sl_cli_command_arg_t *arguments) @@ -141,5 +143,5 @@ static void getFilePathFromCommandLine(uint8_t* result) false); // leftpad? result[length] = '\0'; } -#endif -#endif // defined(EMBER_AF_PLUGIN_POSIX_FILE_BACKUP) +#endif // UC_BUILD +#endif // defined(POSIX_FILE_BACKUP_SUPPORT) diff --git a/protocol/zigbee/app/framework/plugin/trust-center-backup/trust-center-backup-posix.c b/protocol/zigbee/app/framework/plugin/trust-center-backup/trust-center-backup-posix.c index 4ca3e4eebd..b10014e703 100644 --- a/protocol/zigbee/app/framework/plugin/trust-center-backup/trust-center-backup-posix.c +++ b/protocol/zigbee/app/framework/plugin/trust-center-backup/trust-center-backup-posix.c @@ -30,6 +30,10 @@ #include #include +// For some reason gcc/armgcc 10 does not declare strnlen in string(s).h +// Hence, declare it as extern here. +extern size_t strnlen (const char *, size_t); + #ifdef UC_BUILD #include "trust-center-backup-config.h" #if (EMBER_AF_PLUGIN_TRUST_CENTER_BACKUP_POSIX_FILE_BACKUP_SUPPORT == 1) diff --git a/protocol/zigbee/app/framework/plugin/trust-center-backup/trust-center-backup.h b/protocol/zigbee/app/framework/plugin/trust-center-backup/trust-center-backup.h index 4cb6c755a3..a3c60ae380 100644 --- a/protocol/zigbee/app/framework/plugin/trust-center-backup/trust-center-backup.h +++ b/protocol/zigbee/app/framework/plugin/trust-center-backup/trust-center-backup.h @@ -110,6 +110,17 @@ EmberStatus emberAfTrustCenterBackupSaveTokensToFile(const char* filepath); */ EmberStatus emberAfTrustCenterBackupRestoreTokensFromFile(const char* filepath); +/** @brief Updates zigbeed tokens from a file that stores NCP tokens. + * + * @param filepath Ver.: always + * + * @return EmberStatus status code + * + * @note Available only for EMBER_AF_PLUGIN_TRUST_CENTER_BACKUP_POSIX_FILE_BACKUP_SUPPORT + * + */ +EmberStatus emberAfTrustCenterBackupWriteNcpTokenToZigbeedTokens(const char* filepath); + /** @} */ // end of name API /** @} */ // end of trust-center-backup #ifdef UC_BUILD diff --git a/protocol/zigbee/app/framework/scenarios/multiprotocol/DynamicMultiprotocolLight/DynamicMultiprotocolLight.slcp b/protocol/zigbee/app/framework/scenarios/multiprotocol/DynamicMultiprotocolLight/DynamicMultiprotocolLight.slcp index 1577e84b1c..89704a53dd 100644 --- a/protocol/zigbee/app/framework/scenarios/multiprotocol/DynamicMultiprotocolLight/DynamicMultiprotocolLight.slcp +++ b/protocol/zigbee/app/framework/scenarios/multiprotocol/DynamicMultiprotocolLight/DynamicMultiprotocolLight.slcp @@ -93,8 +93,14 @@ configuration: value: 4 - name: SL_HEAP_SIZE value: 16384 + - name: SL_STACK_SIZE + value: 1024 + condition: + - "freertos" - name: SL_STACK_SIZE value: 512 + condition: + - "micriumos_kernel" - name: LIB_MEM_CFG_HEAP_SIZE value: 0 - name: SL_CLI_HELP_DESCRIPTION_ENABLED diff --git a/protocol/zigbee/app/framework/scenarios/multiprotocol/DynamicMultiprotocolLight/DynamicMultiprotocolLightMinimal.slcp b/protocol/zigbee/app/framework/scenarios/multiprotocol/DynamicMultiprotocolLight/DynamicMultiprotocolLightMinimal.slcp index b4822f95de..28caaeccb7 100644 --- a/protocol/zigbee/app/framework/scenarios/multiprotocol/DynamicMultiprotocolLight/DynamicMultiprotocolLightMinimal.slcp +++ b/protocol/zigbee/app/framework/scenarios/multiprotocol/DynamicMultiprotocolLight/DynamicMultiprotocolLightMinimal.slcp @@ -85,8 +85,14 @@ configuration: value: 4 - name: SL_HEAP_SIZE value: 16384 + - name: SL_STACK_SIZE + value: 1024 + condition: + - "freertos" - name: SL_STACK_SIZE value: 512 + condition: + - "micriumos_kernel" - name: LIB_MEM_CFG_HEAP_SIZE value: 0 - name: SL_CLI_HELP_DESCRIPTION_ENABLED diff --git a/protocol/zigbee/app/framework/scenarios/multiprotocol/DynamicMultiprotocolLightSed/DynamicMultiprotocolLightSed.slcp b/protocol/zigbee/app/framework/scenarios/multiprotocol/DynamicMultiprotocolLightSed/DynamicMultiprotocolLightSed.slcp index 8289974b96..9dc77c645f 100644 --- a/protocol/zigbee/app/framework/scenarios/multiprotocol/DynamicMultiprotocolLightSed/DynamicMultiprotocolLightSed.slcp +++ b/protocol/zigbee/app/framework/scenarios/multiprotocol/DynamicMultiprotocolLightSed/DynamicMultiprotocolLightSed.slcp @@ -88,8 +88,14 @@ configuration: value: 4 - name: SL_HEAP_SIZE value: 16384 + - name: SL_STACK_SIZE + value: 1024 + condition: + - "freertos" - name: SL_STACK_SIZE value: 512 + condition: + - "micriumos_kernel" - name: LIB_MEM_CFG_HEAP_SIZE value: 0 - name: SL_CLI_HELP_DESCRIPTION_ENABLED diff --git a/protocol/zigbee/app/framework/scenarios/multiprotocol/DynamicMultiprotocolLightSed/DynamicMultiprotocolLightSedMinimal.slcp b/protocol/zigbee/app/framework/scenarios/multiprotocol/DynamicMultiprotocolLightSed/DynamicMultiprotocolLightSedMinimal.slcp index 8ed1f48231..7fa34d059b 100644 --- a/protocol/zigbee/app/framework/scenarios/multiprotocol/DynamicMultiprotocolLightSed/DynamicMultiprotocolLightSedMinimal.slcp +++ b/protocol/zigbee/app/framework/scenarios/multiprotocol/DynamicMultiprotocolLightSed/DynamicMultiprotocolLightSedMinimal.slcp @@ -80,8 +80,14 @@ configuration: value: 4 - name: SL_HEAP_SIZE value: 16384 + - name: SL_STACK_SIZE + value: 1024 + condition: + - "freertos" - name: SL_STACK_SIZE value: 512 + condition: + - "micriumos_kernel" - name: LIB_MEM_CFG_HEAP_SIZE value: 0 - name: SL_CLI_HELP_DESCRIPTION_ENABLED diff --git a/protocol/zigbee/app/framework/util/af-common.c b/protocol/zigbee/app/framework/util/af-common.c index fccc4a81c6..72eccd3cd1 100644 --- a/protocol/zigbee/app/framework/util/af-common.c +++ b/protocol/zigbee/app/framework/util/af-common.c @@ -47,6 +47,10 @@ #include "critical-message-queue.h" #endif +#ifdef SL_CATALOG_ZIGBEE_TEST_HARNESS_PRESENT + #include "test-harness-config.h" +#endif + #ifdef EZSP_HOST #define INVALID_MESSAGE_TAG 0xFFFF #define setStackProfile(stackProfile) \ @@ -704,18 +708,27 @@ EmberAfCbkeKeyEstablishmentSuite emberAfIsFullSmartEnergySecurityPresent(void) EmberStatus emberAfFormNetwork(EmberNetworkParameters *parameters) { EmberStatus status = EMBER_INVALID_CALL; -#ifdef EMBER_AF_HAS_COORDINATOR_NETWORK - if (emAfProIsCurrentNetwork() - && emAfCurrentZigbeeProNetwork->nodeType == EMBER_COORDINATOR) { - zaTrustCenterSecurityInit(true); // centralized network + EmberCurrentSecurityState securityState; + if (emAfProIsCurrentNetwork()) { emberAfCorePrintln("%ping on ch %d, panId 0x%2X", "Form", parameters->radioChannel, parameters->panId); emberAfCoreFlush(); - status = emberFormNetwork(parameters); + if (emAfCurrentZigbeeProNetwork->nodeType == EMBER_COORDINATOR) { + zaTrustCenterSecurityInit(true); // centralized network + } + // ignore return value for now since it always returns EMBER_SUCCESS + (void)emberGetCurrentSecurityState(&securityState); + if (emAfCurrentZigbeeProNetwork->nodeType == EMBER_COORDINATOR \ + || ((emAfCurrentZigbeeProNetwork->nodeType == EMBER_ROUTER) \ + && (securityState.bitmask & EMBER_DISTRIBUTED_TRUST_CENTER_MODE))) { + status = emberFormNetwork(parameters); + } else { + emberAfCorePrintln("Error: Device does not support %s network formation", + (securityState.bitmask & EMBER_DISTRIBUTED_TRUST_CENTER_MODE) ? "distributed" : "centralized"); + } } -#endif return status; } @@ -813,7 +826,7 @@ void emAfNetworkSecurityInit(void) // If possible, initialize each network. For ZigBee PRO networks, the node // type of the device must match the one used previously, but note that // coordinator-capable devices are allowed to initialize as routers. -#ifndef EMBER_AF_TC_SWAP_OUT_TEST +#if (EMBER_AF_TC_SWAP_OUT_TEST == 0) void emAfNetworkInit(SLXU_INIT_ARG) { SLXU_INIT_UNUSED_ARG; diff --git a/protocol/zigbee/app/framework/util/af-main.h b/protocol/zigbee/app/framework/util/af-main.h index 017c7df5cb..e013da371c 100644 --- a/protocol/zigbee/app/framework/util/af-main.h +++ b/protocol/zigbee/app/framework/util/af-main.h @@ -145,15 +145,6 @@ void emAfStackStatusHandler(EmberStatus status); void emAfNetworkSecurityInit(void); void emAfNetworkInit(SLXU_INIT_ARG); -// For testing purposes only, we suppress the normal call to emberNetworkInit() -// at reboot. This allows us to call it manually later and prevent the node -// from immediately coming back up on the network after reboot. -#ifdef EMBER_AF_TC_SWAP_OUT_TEST - #define EM_AF_NETWORK_INIT() -#else - #define EM_AF_NETWORK_INIT() emAfNetworkInit() -#endif - #define emberAfCopyBigEndianEui64Argument emberCopyBigEndianEui64Argument void emAfScheduleFindAndRejoinEvent(void); diff --git a/protocol/zigbee/app/framework/util/time-util.c b/protocol/zigbee/app/framework/util/time-util.c index 566b4645f1..5f3a1ba905 100644 --- a/protocol/zigbee/app/framework/util/time-util.c +++ b/protocol/zigbee/app/framework/util/time-util.c @@ -190,7 +190,7 @@ uint32_t emberAfEncodeDate(EmberAfDate* date) // from that value. void emberAfPrintTime(uint32_t utcTime) { -#ifdef EMBER_AF_PRINT_ENABLE +#if defined(EMBER_AF_PRINT_ENABLE) || defined(SL_CATALOG_ZIGBEE_DEBUG_PRINT_PRESENT) EmberAfTimeStruct time; emberAfFillTimeStructFromUtc(utcTime, &time); emberAfPrintln(emberAfPrintActiveArea, @@ -202,12 +202,12 @@ void emberAfPrintTime(uint32_t utcTime) time.minutes, time.seconds, utcTime); -#endif //EMBER_AF_PRINT_ENABLE +#endif //EMBER_AF_PRINT_ENABLE || SL_CATALOG_ZIGBEE_DEBUG_PRINT_PRESENT } void emberAfPrintTimeIsoFormat(uint32_t utcTime) { -#ifdef EMBER_AF_PRINT_ENABLE +#if defined(EMBER_AF_PRINT_ENABLE) || defined(SL_CATALOG_ZIGBEE_DEBUG_PRINT_PRESENT) EmberAfTimeStruct time; emberAfFillTimeStructFromUtc(utcTime, &time); emberAfPrint(emberAfPrintActiveArea, @@ -218,12 +218,12 @@ void emberAfPrintTimeIsoFormat(uint32_t utcTime) time.hours, time.minutes, time.seconds); -#endif //EMBER_AF_PRINT_ENABLE +#endif //EMBER_AF_PRINT_ENABLE || SL_CATALOG_ZIGBEE_DEBUG_PRINT_PRESENT } void emberAfPrintDate(const EmberAfDate * date) { -#ifdef EMBER_AF_PRINT_ENABLE +#if defined(EMBER_AF_PRINT_ENABLE) || defined(SL_CATALOG_ZIGBEE_DEBUG_PRINT_PRESENT) uint32_t zigbeeDate = ((((uint32_t)date->year) << 24) + (((uint32_t)date->month) << 16) + (((uint32_t)date->dayOfMonth) << 8) @@ -237,7 +237,7 @@ void emberAfPrintDate(const EmberAfDate * date) date->month, (date->dayOfMonth < 10 ? "0" : ""), date->dayOfMonth); -#endif //EMBER_AF_PRINT_ENABLE +#endif //EMBER_AF_PRINT_ENABLE || SL_CATALOG_ZIGBEE_DEBUG_PRINT_PRESENT } void emberAfPrintDateln(const EmberAfDate * date) diff --git a/protocol/zigbee/app/gpd/components/gpd-cb.c b/protocol/zigbee/app/gpd/components/gpd-cb.c index d0e96036cb..ae2e489bc4 100644 --- a/protocol/zigbee/app/gpd/components/gpd-cb.c +++ b/protocol/zigbee/app/gpd/components/gpd-cb.c @@ -107,11 +107,15 @@ SL_WEAK void emberGpdAfPluginSleepCallback(void) #if defined(EMBER_AF_PLUGIN_APPS_MAC_SEQ) && (EMBER_AF_PLUGIN_APPS_MAC_SEQ == EMBER_GPD_MAC_SEQ_RANDOM) SL_WEAK uint32_t emberGpdAfPluginGetRandomCallback(void) { - uint32_t randomValue; - #ifdef SL_CATALOG_PSA_CRYPTO_PRESENT + // randomValue is not initialised intentionally. + // The reason is, if the call returns 0 (i.e entropy is not supported), whatever randomness stack has that will be taken. + volatile uint8_t randomValue; +#ifdef SL_CATALOG_PSA_CRYPTO_PRESENT (void) psa_generate_random( (uint8_t *)(&randomValue), sizeof(randomValue)); - #endif //SL_CATALOG_PSA_CRYPTO_PRESENT - return randomValue; +#else + (void)emberGpdRailGetRadioEntropyWrapper((uint8_t*)(&randomValue), sizeof(randomValue)); +#endif //SL_CATALOG_PSA_CRYPTO_PRESENT + return (uint32_t)randomValue; } #endif diff --git a/protocol/zigbee/app/gpd/components/gpd-components-common.h b/protocol/zigbee/app/gpd/components/gpd-components-common.h index 55355e88bf..ae307cfaf6 100644 --- a/protocol/zigbee/app/gpd/components/gpd-components-common.h +++ b/protocol/zigbee/app/gpd/components/gpd-components-common.h @@ -335,6 +335,7 @@ void emberGpdRailWriteTxFifoWrapper(const uint8_t *dataPtr, uint16_t writeLength); void emberGpdRailStartRxWrapper(uint8_t channel); void emberGpdRailIdleWrapper(void); +uint16_t emberGpdRailGetRadioEntropyWrapper(uint8_t *dataPtr, uint16_t dataLength); void emberGpdRailProvideRailHandle(RAIL_Handle_t handle); // Security Function Prototypes diff --git a/protocol/zigbee/app/gpd/components/gpd-rail-wrapper.c b/protocol/zigbee/app/gpd/components/gpd-rail-wrapper.c index 353247a2cf..5c81aa9ce0 100644 --- a/protocol/zigbee/app/gpd/components/gpd-rail-wrapper.c +++ b/protocol/zigbee/app/gpd/components/gpd-rail-wrapper.c @@ -97,6 +97,11 @@ void emberGpdRailWriteTxFifoWrapper(const uint8_t *dataPtr, } } +uint16_t emberGpdRailGetRadioEntropyWrapper(uint8_t *dataPtr, uint16_t dataLength) +{ + return RAIL_GetRadioEntropy(railHandle, dataPtr, dataLength); +} + void emberGpdRadioInit(void) { // Set TX FIFO, and verify that the size is correct diff --git a/protocol/zigbee/app/gpd/sample-app/gpd-sensor/gpd-sensor.slcp b/protocol/zigbee/app/gpd/sample-app/gpd-sensor/gpd-sensor.slcp index 51d229dbca..9f802c58d8 100644 --- a/protocol/zigbee/app/gpd/sample-app/gpd-sensor/gpd-sensor.slcp +++ b/protocol/zigbee/app/gpd/sample-app/gpd-sensor/gpd-sensor.slcp @@ -24,7 +24,6 @@ component: - id: rail_util_init instance: - gpdrail -- id: psa_crypto #---------------- User Buttons ----------------------- - id: simple_button instance: diff --git a/protocol/zigbee/app/gpd/sample-app/gpd-switch/gpd-switch.slcp b/protocol/zigbee/app/gpd/sample-app/gpd-switch/gpd-switch.slcp index 269afe7ceb..4322929616 100644 --- a/protocol/zigbee/app/gpd/sample-app/gpd-switch/gpd-switch.slcp +++ b/protocol/zigbee/app/gpd/sample-app/gpd-switch/gpd-switch.slcp @@ -24,7 +24,6 @@ component: - id: rail_util_init instance: - gpdrail -- id: psa_crypto #---------------- User Buttons ----------------------- - id: simple_button instance: diff --git a/protocol/zigbee/app/ncp/sample-app/ncp-cmp/zigbee_ncp-ot_rcp-spi.slcp b/protocol/zigbee/app/ncp/sample-app/ncp-cmp/zigbee_ncp-ot_rcp-spi.slcp index 76635e2ac8..21eee9b0ab 100644 --- a/protocol/zigbee/app/ncp/sample-app/ncp-cmp/zigbee_ncp-ot_rcp-spi.slcp +++ b/protocol/zigbee/app/ncp/sample-app/ncp-cmp/zigbee_ncp-ot_rcp-spi.slcp @@ -100,8 +100,6 @@ configuration: value: 1 - name: OPENTHREAD_CONFIG_PLATFORM_KEY_REFERENCES_ENABLE value: 0 - - name: SL_CPC_SECURITY_ENABLED - value: 0 source: - path: "main.c" diff --git a/protocol/zigbee/app/util/ezsp/command-functions.h b/protocol/zigbee/app/util/ezsp/command-functions.h index 3c21e5824c..248ab3cd53 100644 --- a/protocol/zigbee/app/util/ezsp/command-functions.h +++ b/protocol/zigbee/app/util/ezsp/command-functions.h @@ -226,6 +226,9 @@ uint8_t ezspEcho( EzspStatus sendStatus = sendCommand(); if (sendStatus == EZSP_SUCCESS) { echoLength = fetchInt8u(); + if (echoLength > dataLength) { + return 0; + } fetchInt8uArray(echoLength, echo); return echoLength; } @@ -283,6 +286,46 @@ uint8_t ezspGetMfgToken( EzspStatus sendStatus = sendCommand(); if (sendStatus == EZSP_SUCCESS) { tokenDataLength = fetchInt8u(); + uint8_t expectedTokenDataLength = 0; + // the size of corresponding the EZSP Mfg token, + // please refer to app/util/ezsp/ezsp-enum.h + switch (tokenId) { + // 2 bytes + case EZSP_MFG_CUSTOM_VERSION: + case EZSP_MFG_MANUF_ID: + case EZSP_MFG_PHY_CONFIG: + case EZSP_MFG_CTUNE: + expectedTokenDataLength = 2; + break; + // 8 bytes + case EZSP_MFG_EZSP_STORAGE: + case EZSP_MFG_CUSTOM_EUI_64: + expectedTokenDataLength = 8; + break; + // 16 bytes + case EZSP_MFG_STRING: + case EZSP_MFG_BOARD_NAME: + case EZSP_MFG_BOOTLOAD_AES_KEY: + expectedTokenDataLength = 16; + break; + // 20 bytes + case EZSP_MFG_INSTALLATION_CODE: + expectedTokenDataLength = 20; + break; + // 40 bytes + case EZSP_MFG_ASH_CONFIG: + expectedTokenDataLength = 40; + break; + // 92 bytes + case EZSP_MFG_CBKE_DATA: + expectedTokenDataLength = 92; + break; + default: + break; + } + if (tokenDataLength != expectedTokenDataLength) { + return 255; + } fetchInt8uArray(tokenDataLength, tokenData); return tokenDataLength; } diff --git a/protocol/zigbee/app/util/ezsp/command-prototypes.h b/protocol/zigbee/app/util/ezsp/command-prototypes.h index ae879606c6..994e4eacab 100644 --- a/protocol/zigbee/app/util/ezsp/command-prototypes.h +++ b/protocol/zigbee/app/util/ezsp/command-prototypes.h @@ -16,13 +16,13 @@ //------------------------------------------------------------------------------ // The command allows the Host to specify the desired EZSP version and must be -// sent before any other command. This document describes EZSP version 8 and +// sent before any other command. This document describes EZSP version 9 and // stack type 2 (mesh). The response provides information about the firmware // running on the NCP. -// Return: The EZSP version the NCP is using (8). +// Return: The EZSP version the NCP is using (9). uint8_t ezspVersion( // The EZSP version the Host wishes to use. To successfully set the - // version and allow other commands, this must be 8. + // version and allow other commands, this must be 9. uint8_t desiredProtocolVersion, // Return: The type of stack running on the NCP (2). uint8_t *stackType, @@ -656,7 +656,7 @@ uint8_t ezspGetSourceRouteTableFilledSize(void); // Returns information about a source route table entry // Return: EMBER_SUCCESS if there is source route entry at -// index. EMBER_SOURCE_ROUTE_FAILURE if there is no +// index. EMBER_NOT_FOUND if there is no // source route at index. EmberStatus ezspGetSourceRouteTableEntry( // The index of the entry of interest in the @@ -2297,7 +2297,8 @@ void ezspMfglibRxHandler( // The length of the packetContents parameter in bytes. Will be greater // than 3 and less than 123. uint8_t packetLength, - // The received packet. The last two bytes are the 16-bit CRC. + // The received packet (last 2 bytes are not FCS / CRC and may be + // discarded) uint8_t *packetContents); //------------------------------------------------------------------------------ diff --git a/protocol/zigbee/app/util/ezsp/serial-interface-cpc.c b/protocol/zigbee/app/util/ezsp/serial-interface-cpc.c index d6efc6281d..2b22e7a7b9 100644 --- a/protocol/zigbee/app/util/ezsp/serial-interface-cpc.c +++ b/protocol/zigbee/app/util/ezsp/serial-interface-cpc.c @@ -35,8 +35,7 @@ #define ZIGBEE_CPC_TRANSMIT_WINDOW 1 -#define WAIT_FOR_RESPONSE_TIMEOUT_MS 50 -#define WAIT_FOR_RESPONSE_TIMEOUT_US (WAIT_FOR_RESPONSE_TIMEOUT_MS * 1000) +#define WAIT_FOR_RESPONSE_TIMEOUT_S 5 static uint8_t ezspFrameLength; uint8_t *ezspFrameLengthLocation = &ezspFrameLength; @@ -58,10 +57,28 @@ static uint8_t zigbee_cpc_rx_buffer[SL_CPC_READ_MINIMUM_SIZE]; #define test_print(...) #endif // CPC_TEST_CODE +static int max_restart_attempts = 3; +/****************************************************************************** + * Callback to register reset from other end. + *****************************************************************************/ static void reset_crash_callback(void) { - printf("Connection lost. Restart host process.\n"); - exit(-1); + int ret = 0; + int attempts = 0; + // Reset cpc communication if daemon signals + do { + //Try to restart CPC + ret = cpc_restart(&zigbee_cpc_handle); + //Mark how many times the restart was attempted + attempts++; + //Continue to try and restore CPC communication until we + //have exhausted the retries or restart was successful + } while ((ret != 0) && (attempts < max_restart_attempts)); + + if (ret < 0) { + perror("reset error"); + exit(EXIT_FAILURE); + } } EzspStatus ezspInit(void) @@ -137,8 +154,7 @@ WEAK_TEST EzspStatus serialResponseReceived(void) sizeof(waitingForResponse)); if (waitingForResponse) { - struct timeval timeout; - timeout.tv_usec = WAIT_FOR_RESPONSE_TIMEOUT_US; + cpc_timeval_t timeout = { WAIT_FOR_RESPONSE_TIMEOUT_S, 0 }; cpc_set_endpoint_option(zigbee_cpc_endpoint, CPC_OPTION_RX_TIMEOUT, &timeout, diff --git a/protocol/zigbee/app/zigbeed/zigbeed.slcp b/protocol/zigbee/app/zigbeed/zigbeed.slcp index 01c210003d..0d1b7f57b9 100644 --- a/protocol/zigbee/app/zigbeed/zigbeed.slcp +++ b/protocol/zigbee/app/zigbeed/zigbeed.slcp @@ -24,6 +24,7 @@ component: - id: "zigbee_xncp" - id: "toolchain_gcc" - id: "zigbee_stack_unix" + - id: "zigbee_mfglib" # not required by zigbeed, but could be enabled - id: "zigbee_r22_support" - id: "zigbee_token_interface" diff --git a/protocol/zigbee/build/binding-table-library-cortexm3-gcc-efr32mg12p-rail-ember_multi_network_stripped/binding-table-library.a b/protocol/zigbee/build/binding-table-library-cortexm3-gcc-efr32mg12p-rail-ember_multi_network_stripped/binding-table-library.a index 5840fac9f9..9f628fd61f 100644 --- a/protocol/zigbee/build/binding-table-library-cortexm3-gcc-efr32mg12p-rail-ember_multi_network_stripped/binding-table-library.a +++ b/protocol/zigbee/build/binding-table-library-cortexm3-gcc-efr32mg12p-rail-ember_multi_network_stripped/binding-table-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8901132c6a62b7f9f653dd79407286b4fc15a74675fb6ee209ecc3505074df97 +oid sha256:c46e31cb960d3ad06ce39b5ab1af8c843c5a092bf3bd2ad3eea621de165bdce2 size 10012 diff --git a/protocol/zigbee/build/binding-table-library-cortexm3-gcc-efr32mg12p-rail/binding-table-library.a b/protocol/zigbee/build/binding-table-library-cortexm3-gcc-efr32mg12p-rail/binding-table-library.a index b1e1fd6882..65da9dfc56 100644 --- a/protocol/zigbee/build/binding-table-library-cortexm3-gcc-efr32mg12p-rail/binding-table-library.a +++ b/protocol/zigbee/build/binding-table-library-cortexm3-gcc-efr32mg12p-rail/binding-table-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:dc52adf0f5b56d2ded70ada029b581c9b97d96f38a4eeb2fa7902eb196ba98e9 +oid sha256:8224a06a06d00f5b394bdfd45a5f1845f995e52d470ea3f03932c0d6fc7d04d6 size 10288 diff --git a/protocol/zigbee/build/binding-table-library-cortexm3-gcc-efr32mg13p-rail-ember_multi_network_stripped/binding-table-library.a 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a/protocol/zigbee/build/zll-library-cortexm3-iar-mgm24-rail-ember_multi_network_stripped/zll-library.a +++ b/protocol/zigbee/build/zll-library-cortexm3-iar-mgm24-rail-ember_multi_network_stripped/zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:32f7430d830ecf31038048d23d53f4535d956197fc1f048d01bbd8de54b911f8 -size 172504 +oid sha256:b2f3c364f79582750b73734ad18133b6f931909ef5028ac3c3ac28637eedabe0 +size 172500 diff --git a/protocol/zigbee/build/zll-library-cortexm3-iar-mgm24-rail-stack_protection/zll-library.a b/protocol/zigbee/build/zll-library-cortexm3-iar-mgm24-rail-stack_protection/zll-library.a index 1bdb950726..63c736e68b 100644 --- a/protocol/zigbee/build/zll-library-cortexm3-iar-mgm24-rail-stack_protection/zll-library.a +++ b/protocol/zigbee/build/zll-library-cortexm3-iar-mgm24-rail-stack_protection/zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1e4005bd75fb23186319f20e78e83dea6d8fef48566b514f0cd2507d2339d6ec -size 179714 +oid sha256:3357e186bf53dc4f8caa08a4393391fd0edb04f3a58a28f0aeb2021c734d43d7 +size 179768 diff --git a/protocol/zigbee/build/zll-library-cortexm3-iar-mgm24-rail/zll-library.a b/protocol/zigbee/build/zll-library-cortexm3-iar-mgm24-rail/zll-library.a index a9074222e0..a1207de17a 100644 --- a/protocol/zigbee/build/zll-library-cortexm3-iar-mgm24-rail/zll-library.a +++ b/protocol/zigbee/build/zll-library-cortexm3-iar-mgm24-rail/zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e0af48646626cece5fa6145b7960d9ab902bd3c2a814f9e06188b9f2bf131bbd -size 172554 +oid sha256:b8da8a22694e9749b367d915583d04ec4ae4727a8ac57d4671947fc2583c1ce8 +size 172544 diff --git a/protocol/zigbee/build/zll-library-unix-gcc-simulation-null-arm32v7-ember_multi_network_stripped/zll-library.a b/protocol/zigbee/build/zll-library-unix-gcc-simulation-null-arm32v7-ember_multi_network_stripped/zll-library.a index 1cba5687ef..dd0486536a 100644 --- a/protocol/zigbee/build/zll-library-unix-gcc-simulation-null-arm32v7-ember_multi_network_stripped/zll-library.a +++ b/protocol/zigbee/build/zll-library-unix-gcc-simulation-null-arm32v7-ember_multi_network_stripped/zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6e1a405f6714cb210806522eee865d00048a6da1c50b9d0c4bcc25de00954926 +oid sha256:6b30880737e1ea18c2d7f1e7a18363dc4250349818de801607ffaf0e579db27b size 209370 diff --git a/protocol/zigbee/build/zll-library-unix-gcc-simulation-null-arm64v8-ember_multi_network_stripped/zll-library.a b/protocol/zigbee/build/zll-library-unix-gcc-simulation-null-arm64v8-ember_multi_network_stripped/zll-library.a index 1d00387a11..8e5c8b15d4 100644 --- a/protocol/zigbee/build/zll-library-unix-gcc-simulation-null-arm64v8-ember_multi_network_stripped/zll-library.a +++ b/protocol/zigbee/build/zll-library-unix-gcc-simulation-null-arm64v8-ember_multi_network_stripped/zll-library.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c72fa73347e8f613b1c0f6087d9bc1550672ea1c24c280ed410de496b891977e -size 306374 +oid sha256:c15e2bb9ec7fe603b2a45df55efc604ed874698a079c108b8ede205052d21c5d +size 306366 diff --git a/protocol/zigbee/component/zigbee_app_framework_common.slcc b/protocol/zigbee/component/zigbee_app_framework_common.slcc index 9cca5059c8..60b1f78872 100644 --- a/protocol/zigbee/component/zigbee_app_framework_common.slcc +++ b/protocol/zigbee/component/zigbee_app_framework_common.slcc @@ -87,6 +87,8 @@ define: # for app builder while we make changes to make it work within UC. - name: UC_BUILD +# NOTE: Some cflags come in via platform/common/toolchain/toolchains.slct +# Example: -Wall, -Wextra. So there is no need to explicitly add them toolchain_settings: - option: gcc_compiler_option value: "-Wno-unused-parameter" @@ -94,6 +96,12 @@ toolchain_settings: value: "-Wno-missing-field-initializers" - option: gcc_compiler_option value: "-Wno-missing-braces" + # turn on warnings as errors only when compiling from source + - option: gcc_compiler_option + value: "-Werror" + condition: + - zigbee_pro_stack_common_source + # TODO: EMZIGBEE-6659 - option: gcc_compiler_option value: "-Wno-format" diff --git a/protocol/zigbee/component/zigbee_binding_table_library.slcc b/protocol/zigbee/component/zigbee_binding_table_library.slcc index 443c3817b7..583a30aa21 100644 --- a/protocol/zigbee/component/zigbee_binding_table_library.slcc +++ b/protocol/zigbee/component/zigbee_binding_table_library.slcc @@ -19,99 +19,6 @@ requires: - name: zigbee_binding_table library: - - path: protocol/zigbee/build/binding-table-library-cortexm3-iar-efr32mg1p-rail/binding-table-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/binding-table-library-cortexm3-iar-efr32mg1p-rail-stack_protection/binding-table-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/binding-table-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/binding-table-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/binding-table-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/binding-table-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/binding-table-library-cortexm3-iar-efr32mg1b-rail/binding-table-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/binding-table-library-cortexm3-iar-efr32mg1b-rail-stack_protection/binding-table-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/binding-table-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/binding-table-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/binding-table-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/binding-table-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/binding-table-library-cortexm3-iar-efr32mg1v-rail/binding-table-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/binding-table-library-cortexm3-iar-efr32mg1v-rail-stack_protection/binding-table-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/binding-table-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/binding-table-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/binding-table-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/binding-table-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - path: protocol/zigbee/build/binding-table-library-cortexm3-iar-efr32mg12p-rail/binding-table-library.a condition: - toolchain_iar @@ -174,19 +81,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/binding-table-library-cortexm3-iar-efr32mg14p-rail/binding-table-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/binding-table-library-cortexm3-iar-efr32mg14p-rail-stack_protection/binding-table-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/binding-table-library-cortexm3-iar-efr32mg21-rail/binding-table-library.a condition: - toolchain_iar @@ -466,54 +360,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/binding-table-library-cortexm3-gcc-efr32mg1p-rail/binding-table-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/binding-table-library-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/binding-table-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/binding-table-library-cortexm3-gcc-efr32mg1b-rail/binding-table-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/binding-table-library-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/binding-table-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/binding-table-library-cortexm3-gcc-efr32mg1v-rail/binding-table-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/binding-table-library-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/binding-table-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - path: protocol/zigbee/build/binding-table-library-cortexm3-gcc-efr32mg12p-rail/binding-table-library.a condition: - toolchain_gcc @@ -546,13 +392,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/binding-table-library-cortexm3-gcc-efr32mg14p-rail/binding-table-library.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/binding-table-library-cortexm3-gcc-efr32mg21-rail/binding-table-library.a condition: - toolchain_gcc @@ -697,111 +536,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/ncp-binding-library-cortexm3-iar-efr32mg1p-rail/ncp-binding-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-binding-library-cortexm3-iar-efr32mg1p-rail-stack_protection/ncp-binding-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-binding-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/ncp-binding-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-binding-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/ncp-binding-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - zigbee_ncp - - path: protocol/zigbee/build/ncp-binding-library-cortexm3-iar-efr32mg1b-rail/ncp-binding-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-binding-library-cortexm3-iar-efr32mg1b-rail-stack_protection/ncp-binding-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-binding-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/ncp-binding-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-binding-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/ncp-binding-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - zigbee_ncp - - path: protocol/zigbee/build/ncp-binding-library-cortexm3-iar-efr32mg1v-rail/ncp-binding-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-binding-library-cortexm3-iar-efr32mg1v-rail-stack_protection/ncp-binding-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-binding-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/ncp-binding-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-binding-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/ncp-binding-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - zigbee_ncp - path: protocol/zigbee/build/ncp-binding-library-cortexm3-iar-efr32mg12p-rail/ncp-binding-library.a condition: - toolchain_iar @@ -872,21 +606,6 @@ library: - zigbee_ncp unless: - zigbee_multi_network - - path: protocol/zigbee/build/ncp-binding-library-cortexm3-iar-efr32mg14p-rail/ncp-binding-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-binding-library-cortexm3-iar-efr32mg14p-rail-stack_protection/ncp-binding-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - path: protocol/zigbee/build/ncp-binding-library-cortexm3-iar-efr32mg21-rail/ncp-binding-library.a condition: - toolchain_iar @@ -1202,60 +921,6 @@ library: - zigbee_ncp unless: - zigbee_multi_network - - path: protocol/zigbee/build/ncp-binding-library-cortexm3-gcc-efr32mg1p-rail/ncp-binding-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-binding-library-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/ncp-binding-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-binding-library-cortexm3-gcc-efr32mg1b-rail/ncp-binding-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-binding-library-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/ncp-binding-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-binding-library-cortexm3-gcc-efr32mg1v-rail/ncp-binding-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-binding-library-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/ncp-binding-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - path: protocol/zigbee/build/ncp-binding-library-cortexm3-gcc-efr32mg12p-rail/ncp-binding-library.a condition: - toolchain_gcc @@ -1292,14 +957,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/ncp-binding-library-cortexm3-gcc-efr32mg14p-rail/ncp-binding-library.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - path: protocol/zigbee/build/ncp-binding-library-cortexm3-gcc-efr32mg21-rail/ncp-binding-library.a condition: - toolchain_gcc diff --git a/protocol/zigbee/component/zigbee_cbke_163k1_library.slcc b/protocol/zigbee/component/zigbee_cbke_163k1_library.slcc index ca2e2d3e82..db3e96daa9 100644 --- a/protocol/zigbee/component/zigbee_cbke_163k1_library.slcc +++ b/protocol/zigbee/component/zigbee_cbke_163k1_library.slcc @@ -19,99 +19,6 @@ requires: - name: zigbee_cbke_163k1 library: - - path: protocol/zigbee/build/cbke-163k1-library-cortexm3-iar-efr32mg1p-rail/cbke-163k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-163k1-library-cortexm3-iar-efr32mg1p-rail-stack_protection/cbke-163k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-163k1-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/cbke-163k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-163k1-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/cbke-163k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/cbke-163k1-library-cortexm3-iar-efr32mg1b-rail/cbke-163k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-163k1-library-cortexm3-iar-efr32mg1b-rail-stack_protection/cbke-163k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-163k1-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/cbke-163k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-163k1-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/cbke-163k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/cbke-163k1-library-cortexm3-iar-efr32mg1v-rail/cbke-163k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-163k1-library-cortexm3-iar-efr32mg1v-rail-stack_protection/cbke-163k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-163k1-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/cbke-163k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-163k1-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/cbke-163k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - path: protocol/zigbee/build/cbke-163k1-library-cortexm3-iar-efr32mg12p-rail/cbke-163k1-library.a condition: - toolchain_iar @@ -174,19 +81,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/cbke-163k1-library-cortexm3-iar-efr32mg14p-rail/cbke-163k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-163k1-library-cortexm3-iar-efr32mg14p-rail-stack_protection/cbke-163k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/cbke-163k1-library-cortexm3-iar-efr32mg21-rail/cbke-163k1-library.a condition: - toolchain_iar @@ -466,54 +360,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/cbke-163k1-library-cortexm3-gcc-efr32mg1p-rail/cbke-163k1-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-163k1-library-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/cbke-163k1-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-163k1-library-cortexm3-gcc-efr32mg1b-rail/cbke-163k1-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-163k1-library-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/cbke-163k1-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-163k1-library-cortexm3-gcc-efr32mg1v-rail/cbke-163k1-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-163k1-library-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/cbke-163k1-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - path: protocol/zigbee/build/cbke-163k1-library-cortexm3-gcc-efr32mg12p-rail/cbke-163k1-library.a condition: - toolchain_gcc @@ -546,13 +392,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/cbke-163k1-library-cortexm3-gcc-efr32mg14p-rail/cbke-163k1-library.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/cbke-163k1-library-cortexm3-gcc-efr32mg21-rail/cbke-163k1-library.a condition: - toolchain_gcc diff --git a/protocol/zigbee/component/zigbee_cbke_283k1_library.slcc b/protocol/zigbee/component/zigbee_cbke_283k1_library.slcc index feab4931cd..b33096a680 100644 --- a/protocol/zigbee/component/zigbee_cbke_283k1_library.slcc +++ b/protocol/zigbee/component/zigbee_cbke_283k1_library.slcc @@ -19,99 +19,6 @@ requires: - name: zigbee_cbke_283k1 library: - - path: protocol/zigbee/build/cbke-283k1-library-cortexm3-iar-efr32mg1p-rail/cbke-283k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-283k1-library-cortexm3-iar-efr32mg1p-rail-stack_protection/cbke-283k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-283k1-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/cbke-283k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-283k1-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/cbke-283k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/cbke-283k1-library-cortexm3-iar-efr32mg1b-rail/cbke-283k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-283k1-library-cortexm3-iar-efr32mg1b-rail-stack_protection/cbke-283k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-283k1-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/cbke-283k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-283k1-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/cbke-283k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/cbke-283k1-library-cortexm3-iar-efr32mg1v-rail/cbke-283k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-283k1-library-cortexm3-iar-efr32mg1v-rail-stack_protection/cbke-283k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-283k1-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/cbke-283k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-283k1-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/cbke-283k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - path: protocol/zigbee/build/cbke-283k1-library-cortexm3-iar-efr32mg12p-rail/cbke-283k1-library.a condition: - toolchain_iar @@ -174,19 +81,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/cbke-283k1-library-cortexm3-iar-efr32mg14p-rail/cbke-283k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-283k1-library-cortexm3-iar-efr32mg14p-rail-stack_protection/cbke-283k1-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/cbke-283k1-library-cortexm3-iar-efr32mg21-rail/cbke-283k1-library.a condition: - toolchain_iar @@ -466,54 +360,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/cbke-283k1-library-cortexm3-gcc-efr32mg1p-rail/cbke-283k1-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-283k1-library-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/cbke-283k1-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-283k1-library-cortexm3-gcc-efr32mg1b-rail/cbke-283k1-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-283k1-library-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/cbke-283k1-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-283k1-library-cortexm3-gcc-efr32mg1v-rail/cbke-283k1-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-283k1-library-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/cbke-283k1-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - path: protocol/zigbee/build/cbke-283k1-library-cortexm3-gcc-efr32mg12p-rail/cbke-283k1-library.a condition: - toolchain_gcc @@ -546,13 +392,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/cbke-283k1-library-cortexm3-gcc-efr32mg14p-rail/cbke-283k1-library.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/cbke-283k1-library-cortexm3-gcc-efr32mg21-rail/cbke-283k1-library.a condition: - toolchain_gcc diff --git a/protocol/zigbee/component/zigbee_cbke_core_library.slcc b/protocol/zigbee/component/zigbee_cbke_core_library.slcc index d50820f44b..a205b91e85 100644 --- a/protocol/zigbee/component/zigbee_cbke_core_library.slcc +++ b/protocol/zigbee/component/zigbee_cbke_core_library.slcc @@ -19,99 +19,6 @@ requires: - name: zigbee_cbke_core library: - - path: protocol/zigbee/build/cbke-library-core-cortexm3-iar-efr32mg1p-rail/cbke-library-core.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-core-cortexm3-iar-efr32mg1p-rail-stack_protection/cbke-library-core.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-core-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/cbke-library-core.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-core-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/cbke-library-core.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-core-cortexm3-iar-efr32mg1b-rail/cbke-library-core.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-core-cortexm3-iar-efr32mg1b-rail-stack_protection/cbke-library-core.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-core-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/cbke-library-core.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-core-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/cbke-library-core.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-core-cortexm3-iar-efr32mg1v-rail/cbke-library-core.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-core-cortexm3-iar-efr32mg1v-rail-stack_protection/cbke-library-core.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-core-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/cbke-library-core.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-core-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/cbke-library-core.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - path: protocol/zigbee/build/cbke-library-core-cortexm3-iar-efr32mg12p-rail/cbke-library-core.a condition: - toolchain_iar @@ -174,19 +81,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/cbke-library-core-cortexm3-iar-efr32mg14p-rail/cbke-library-core.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-core-cortexm3-iar-efr32mg14p-rail-stack_protection/cbke-library-core.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/cbke-library-core-cortexm3-iar-efr32mg21-rail/cbke-library-core.a condition: - toolchain_iar @@ -466,54 +360,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/cbke-library-core-cortexm3-gcc-efr32mg1p-rail/cbke-library-core.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-core-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/cbke-library-core.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-core-cortexm3-gcc-efr32mg1b-rail/cbke-library-core.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-core-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/cbke-library-core.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-core-cortexm3-gcc-efr32mg1v-rail/cbke-library-core.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-core-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/cbke-library-core.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - path: protocol/zigbee/build/cbke-library-core-cortexm3-gcc-efr32mg12p-rail/cbke-library-core.a condition: - toolchain_gcc @@ -546,13 +392,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-core-cortexm3-gcc-efr32mg14p-rail/cbke-library-core.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/cbke-library-core-cortexm3-gcc-efr32mg21-rail/cbke-library-core.a condition: - toolchain_gcc @@ -697,111 +536,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/ncp-cbke-library-cortexm3-iar-efr32mg1p-rail/ncp-cbke-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-cbke-library-cortexm3-iar-efr32mg1p-rail-stack_protection/ncp-cbke-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-cbke-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/ncp-cbke-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-cbke-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/ncp-cbke-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - zigbee_ncp - - path: protocol/zigbee/build/ncp-cbke-library-cortexm3-iar-efr32mg1b-rail/ncp-cbke-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-cbke-library-cortexm3-iar-efr32mg1b-rail-stack_protection/ncp-cbke-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-cbke-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/ncp-cbke-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-cbke-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/ncp-cbke-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - zigbee_ncp - - path: protocol/zigbee/build/ncp-cbke-library-cortexm3-iar-efr32mg1v-rail/ncp-cbke-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-cbke-library-cortexm3-iar-efr32mg1v-rail-stack_protection/ncp-cbke-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-cbke-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/ncp-cbke-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-cbke-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/ncp-cbke-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - zigbee_ncp - path: protocol/zigbee/build/ncp-cbke-library-cortexm3-iar-efr32mg12p-rail/ncp-cbke-library.a condition: - toolchain_iar @@ -832,21 +566,6 @@ library: - zigbee_phy_2_4 - stack_protection_iar - zigbee_ncp - - path: protocol/zigbee/build/ncp-cbke-library-cortexm3-iar-efr32mg14p-rail/ncp-cbke-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-cbke-library-cortexm3-iar-efr32mg14p-rail-stack_protection/ncp-cbke-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - path: protocol/zigbee/build/ncp-cbke-library-cortexm3-iar-efr32mg21-rail/ncp-cbke-library.a condition: - toolchain_iar @@ -982,60 +701,6 @@ library: - zigbee_phy_2_4 - stack_protection_iar - zigbee_ncp - - path: protocol/zigbee/build/ncp-cbke-library-cortexm3-gcc-efr32mg1p-rail/ncp-cbke-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-cbke-library-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/ncp-cbke-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-cbke-library-cortexm3-gcc-efr32mg1b-rail/ncp-cbke-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-cbke-library-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/ncp-cbke-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-cbke-library-cortexm3-gcc-efr32mg1v-rail/ncp-cbke-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-cbke-library-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/ncp-cbke-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - path: protocol/zigbee/build/ncp-cbke-library-cortexm3-gcc-efr32mg12p-rail/ncp-cbke-library.a condition: - toolchain_gcc @@ -1052,14 +717,6 @@ library: - zigbee_ncp unless: - stack_protection_iar - - path: protocol/zigbee/build/ncp-cbke-library-cortexm3-gcc-efr32mg14p-rail/ncp-cbke-library.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - path: protocol/zigbee/build/ncp-cbke-library-cortexm3-gcc-efr32mg21-rail/ncp-cbke-library.a condition: - toolchain_gcc diff --git a/protocol/zigbee/component/zigbee_cbke_dsa_sign_library.slcc b/protocol/zigbee/component/zigbee_cbke_dsa_sign_library.slcc index 7186b1db9a..6d351c559d 100644 --- a/protocol/zigbee/component/zigbee_cbke_dsa_sign_library.slcc +++ b/protocol/zigbee/component/zigbee_cbke_dsa_sign_library.slcc @@ -19,99 +19,6 @@ requires: - name: zigbee_cbke_dsa_sign library: - - path: protocol/zigbee/build/cbke-library-dsa-sign-cortexm3-iar-efr32mg1p-rail/cbke-library-dsa-sign.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-sign-cortexm3-iar-efr32mg1p-rail-stack_protection/cbke-library-dsa-sign.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-sign-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/cbke-library-dsa-sign.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-sign-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/cbke-library-dsa-sign.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-sign-cortexm3-iar-efr32mg1b-rail/cbke-library-dsa-sign.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-sign-cortexm3-iar-efr32mg1b-rail-stack_protection/cbke-library-dsa-sign.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-sign-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/cbke-library-dsa-sign.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-sign-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/cbke-library-dsa-sign.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-sign-cortexm3-iar-efr32mg1v-rail/cbke-library-dsa-sign.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-sign-cortexm3-iar-efr32mg1v-rail-stack_protection/cbke-library-dsa-sign.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-sign-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/cbke-library-dsa-sign.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-sign-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/cbke-library-dsa-sign.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - path: protocol/zigbee/build/cbke-library-dsa-sign-cortexm3-iar-efr32mg12p-rail/cbke-library-dsa-sign.a condition: - toolchain_iar @@ -174,19 +81,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/cbke-library-dsa-sign-cortexm3-iar-efr32mg14p-rail/cbke-library-dsa-sign.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-sign-cortexm3-iar-efr32mg14p-rail-stack_protection/cbke-library-dsa-sign.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/cbke-library-dsa-sign-cortexm3-iar-efr32mg21-rail/cbke-library-dsa-sign.a condition: - toolchain_iar @@ -466,54 +360,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/cbke-library-dsa-sign-cortexm3-gcc-efr32mg1p-rail/cbke-library-dsa-sign.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-sign-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/cbke-library-dsa-sign.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-sign-cortexm3-gcc-efr32mg1b-rail/cbke-library-dsa-sign.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-sign-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/cbke-library-dsa-sign.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-sign-cortexm3-gcc-efr32mg1v-rail/cbke-library-dsa-sign.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-sign-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/cbke-library-dsa-sign.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - path: protocol/zigbee/build/cbke-library-dsa-sign-cortexm3-gcc-efr32mg12p-rail/cbke-library-dsa-sign.a condition: - toolchain_gcc @@ -546,13 +392,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-sign-cortexm3-gcc-efr32mg14p-rail/cbke-library-dsa-sign.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/cbke-library-dsa-sign-cortexm3-gcc-efr32mg21-rail/cbke-library-dsa-sign.a condition: - toolchain_gcc diff --git a/protocol/zigbee/component/zigbee_cbke_dsa_verify_283k1_library.slcc b/protocol/zigbee/component/zigbee_cbke_dsa_verify_283k1_library.slcc index 827ebd685d..d3292ae5a4 100644 --- a/protocol/zigbee/component/zigbee_cbke_dsa_verify_283k1_library.slcc +++ b/protocol/zigbee/component/zigbee_cbke_dsa_verify_283k1_library.slcc @@ -19,99 +19,6 @@ requires: - name: zigbee_cbke_dsa_verify_283k1 library: - - path: protocol/zigbee/build/cbke-library-dsa-verify-283k1-cortexm3-iar-efr32mg1p-rail/cbke-library-dsa-verify-283k1.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-verify-283k1-cortexm3-iar-efr32mg1p-rail-stack_protection/cbke-library-dsa-verify-283k1.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-verify-283k1-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/cbke-library-dsa-verify-283k1.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-verify-283k1-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/cbke-library-dsa-verify-283k1.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-verify-283k1-cortexm3-iar-efr32mg1b-rail/cbke-library-dsa-verify-283k1.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-verify-283k1-cortexm3-iar-efr32mg1b-rail-stack_protection/cbke-library-dsa-verify-283k1.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-verify-283k1-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/cbke-library-dsa-verify-283k1.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-verify-283k1-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/cbke-library-dsa-verify-283k1.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-verify-283k1-cortexm3-iar-efr32mg1v-rail/cbke-library-dsa-verify-283k1.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-verify-283k1-cortexm3-iar-efr32mg1v-rail-stack_protection/cbke-library-dsa-verify-283k1.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-verify-283k1-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/cbke-library-dsa-verify-283k1.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-verify-283k1-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/cbke-library-dsa-verify-283k1.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - path: protocol/zigbee/build/cbke-library-dsa-verify-283k1-cortexm3-iar-efr32mg12p-rail/cbke-library-dsa-verify-283k1.a condition: - toolchain_iar @@ -174,19 +81,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/cbke-library-dsa-verify-283k1-cortexm3-iar-efr32mg14p-rail/cbke-library-dsa-verify-283k1.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-verify-283k1-cortexm3-iar-efr32mg14p-rail-stack_protection/cbke-library-dsa-verify-283k1.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/cbke-library-dsa-verify-283k1-cortexm3-iar-efr32mg21-rail/cbke-library-dsa-verify-283k1.a condition: - toolchain_iar @@ -466,54 +360,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/cbke-library-dsa-verify-283k1-cortexm3-gcc-efr32mg1p-rail/cbke-library-dsa-verify-283k1.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-verify-283k1-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/cbke-library-dsa-verify-283k1.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-verify-283k1-cortexm3-gcc-efr32mg1b-rail/cbke-library-dsa-verify-283k1.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-verify-283k1-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/cbke-library-dsa-verify-283k1.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-verify-283k1-cortexm3-gcc-efr32mg1v-rail/cbke-library-dsa-verify-283k1.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-verify-283k1-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/cbke-library-dsa-verify-283k1.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - path: protocol/zigbee/build/cbke-library-dsa-verify-283k1-cortexm3-gcc-efr32mg12p-rail/cbke-library-dsa-verify-283k1.a condition: - toolchain_gcc @@ -546,13 +392,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-verify-283k1-cortexm3-gcc-efr32mg14p-rail/cbke-library-dsa-verify-283k1.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/cbke-library-dsa-verify-283k1-cortexm3-gcc-efr32mg21-rail/cbke-library-dsa-verify-283k1.a condition: - toolchain_gcc diff --git a/protocol/zigbee/component/zigbee_cbke_dsa_verify_library.slcc b/protocol/zigbee/component/zigbee_cbke_dsa_verify_library.slcc index 06aaaed88c..3211c2dbfd 100644 --- a/protocol/zigbee/component/zigbee_cbke_dsa_verify_library.slcc +++ b/protocol/zigbee/component/zigbee_cbke_dsa_verify_library.slcc @@ -19,99 +19,6 @@ requires: - name: zigbee_cbke_dsa_verify library: - - path: protocol/zigbee/build/cbke-library-dsa-verify-cortexm3-iar-efr32mg1p-rail/cbke-library-dsa-verify.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-verify-cortexm3-iar-efr32mg1p-rail-stack_protection/cbke-library-dsa-verify.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-verify-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/cbke-library-dsa-verify.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-verify-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/cbke-library-dsa-verify.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-verify-cortexm3-iar-efr32mg1b-rail/cbke-library-dsa-verify.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-verify-cortexm3-iar-efr32mg1b-rail-stack_protection/cbke-library-dsa-verify.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-verify-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/cbke-library-dsa-verify.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-verify-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/cbke-library-dsa-verify.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-verify-cortexm3-iar-efr32mg1v-rail/cbke-library-dsa-verify.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-verify-cortexm3-iar-efr32mg1v-rail-stack_protection/cbke-library-dsa-verify.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-verify-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/cbke-library-dsa-verify.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-verify-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/cbke-library-dsa-verify.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - path: protocol/zigbee/build/cbke-library-dsa-verify-cortexm3-iar-efr32mg12p-rail/cbke-library-dsa-verify.a condition: - toolchain_iar @@ -174,19 +81,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/cbke-library-dsa-verify-cortexm3-iar-efr32mg14p-rail/cbke-library-dsa-verify.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-verify-cortexm3-iar-efr32mg14p-rail-stack_protection/cbke-library-dsa-verify.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/cbke-library-dsa-verify-cortexm3-iar-efr32mg21-rail/cbke-library-dsa-verify.a condition: - toolchain_iar @@ -466,54 +360,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/cbke-library-dsa-verify-cortexm3-gcc-efr32mg1p-rail/cbke-library-dsa-verify.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-verify-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/cbke-library-dsa-verify.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-verify-cortexm3-gcc-efr32mg1b-rail/cbke-library-dsa-verify.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-verify-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/cbke-library-dsa-verify.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-verify-cortexm3-gcc-efr32mg1v-rail/cbke-library-dsa-verify.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/cbke-library-dsa-verify-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/cbke-library-dsa-verify.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - path: protocol/zigbee/build/cbke-library-dsa-verify-cortexm3-gcc-efr32mg12p-rail/cbke-library-dsa-verify.a condition: - toolchain_gcc @@ -546,13 +392,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/cbke-library-dsa-verify-cortexm3-gcc-efr32mg14p-rail/cbke-library-dsa-verify.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/cbke-library-dsa-verify-cortexm3-gcc-efr32mg21-rail/cbke-library-dsa-verify.a condition: - toolchain_gcc diff --git a/protocol/zigbee/component/zigbee_debug_basic_library.slcc b/protocol/zigbee/component/zigbee_debug_basic_library.slcc index e20689f0c5..420e7507b3 100644 --- a/protocol/zigbee/component/zigbee_debug_basic_library.slcc +++ b/protocol/zigbee/component/zigbee_debug_basic_library.slcc @@ -19,99 +19,6 @@ requires: - name: zigbee_debug_basic library: - - path: protocol/zigbee/build/debug-basic-library-cortexm3-iar-efr32mg1p-rail/debug-basic-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/debug-basic-library-cortexm3-iar-efr32mg1p-rail-stack_protection/debug-basic-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/debug-basic-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/debug-basic-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/debug-basic-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/debug-basic-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/debug-basic-library-cortexm3-iar-efr32mg1b-rail/debug-basic-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/debug-basic-library-cortexm3-iar-efr32mg1b-rail-stack_protection/debug-basic-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/debug-basic-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/debug-basic-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/debug-basic-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/debug-basic-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/debug-basic-library-cortexm3-iar-efr32mg1v-rail/debug-basic-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/debug-basic-library-cortexm3-iar-efr32mg1v-rail-stack_protection/debug-basic-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/debug-basic-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/debug-basic-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/debug-basic-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/debug-basic-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - path: protocol/zigbee/build/debug-basic-library-cortexm3-iar-efr32mg12p-rail/debug-basic-library.a condition: - toolchain_iar @@ -138,19 +45,6 @@ library: - device_family_efr32mg13p - zigbee_phy_2_4 - stack_protection_iar - - path: protocol/zigbee/build/debug-basic-library-cortexm3-iar-efr32mg14p-rail/debug-basic-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/debug-basic-library-cortexm3-iar-efr32mg14p-rail-stack_protection/debug-basic-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/debug-basic-library-cortexm3-iar-efr32mg21-rail/debug-basic-library.a condition: - toolchain_iar @@ -268,54 +162,6 @@ library: - device_family_mgm24 - zigbee_phy_2_4 - stack_protection_iar - - path: protocol/zigbee/build/debug-basic-library-cortexm3-gcc-efr32mg1p-rail/debug-basic-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/debug-basic-library-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/debug-basic-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/debug-basic-library-cortexm3-gcc-efr32mg1b-rail/debug-basic-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/debug-basic-library-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/debug-basic-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/debug-basic-library-cortexm3-gcc-efr32mg1v-rail/debug-basic-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/debug-basic-library-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/debug-basic-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - path: protocol/zigbee/build/debug-basic-library-cortexm3-gcc-efr32mg12p-rail/debug-basic-library.a condition: - toolchain_gcc @@ -330,13 +176,6 @@ library: - zigbee_phy_2_4 unless: - stack_protection_iar - - path: protocol/zigbee/build/debug-basic-library-cortexm3-gcc-efr32mg14p-rail/debug-basic-library.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/debug-basic-library-cortexm3-gcc-efr32mg21-rail/debug-basic-library.a condition: - toolchain_gcc diff --git a/protocol/zigbee/component/zigbee_debug_extended_library.slcc b/protocol/zigbee/component/zigbee_debug_extended_library.slcc index 3e07a79014..705abe8173 100644 --- a/protocol/zigbee/component/zigbee_debug_extended_library.slcc +++ b/protocol/zigbee/component/zigbee_debug_extended_library.slcc @@ -19,99 +19,6 @@ requires: - name: zigbee_debug_extended library: - - path: protocol/zigbee/build/debug-extended-library-cortexm3-iar-efr32mg1p-rail/debug-extended-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/debug-extended-library-cortexm3-iar-efr32mg1p-rail-stack_protection/debug-extended-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/debug-extended-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/debug-extended-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/debug-extended-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/debug-extended-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/debug-extended-library-cortexm3-iar-efr32mg1b-rail/debug-extended-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/debug-extended-library-cortexm3-iar-efr32mg1b-rail-stack_protection/debug-extended-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/debug-extended-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/debug-extended-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/debug-extended-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/debug-extended-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/debug-extended-library-cortexm3-iar-efr32mg1v-rail/debug-extended-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/debug-extended-library-cortexm3-iar-efr32mg1v-rail-stack_protection/debug-extended-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/debug-extended-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/debug-extended-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/debug-extended-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/debug-extended-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - path: protocol/zigbee/build/debug-extended-library-cortexm3-iar-efr32mg12p-rail/debug-extended-library.a condition: - toolchain_iar @@ -138,19 +45,6 @@ library: - device_family_efr32mg13p - zigbee_phy_2_4 - stack_protection_iar - - path: protocol/zigbee/build/debug-extended-library-cortexm3-iar-efr32mg14p-rail/debug-extended-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/debug-extended-library-cortexm3-iar-efr32mg14p-rail-stack_protection/debug-extended-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/debug-extended-library-cortexm3-iar-efr32mg21-rail/debug-extended-library.a condition: - toolchain_iar @@ -268,54 +162,6 @@ library: - device_family_mgm24 - zigbee_phy_2_4 - stack_protection_iar - - path: protocol/zigbee/build/debug-extended-library-cortexm3-gcc-efr32mg1p-rail/debug-extended-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/debug-extended-library-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/debug-extended-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/debug-extended-library-cortexm3-gcc-efr32mg1b-rail/debug-extended-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/debug-extended-library-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/debug-extended-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/debug-extended-library-cortexm3-gcc-efr32mg1v-rail/debug-extended-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/debug-extended-library-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/debug-extended-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - path: protocol/zigbee/build/debug-extended-library-cortexm3-gcc-efr32mg12p-rail/debug-extended-library.a condition: - toolchain_gcc @@ -330,13 +176,6 @@ library: - zigbee_phy_2_4 unless: - stack_protection_iar - - path: protocol/zigbee/build/debug-extended-library-cortexm3-gcc-efr32mg14p-rail/debug-extended-library.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/debug-extended-library-cortexm3-gcc-efr32mg21-rail/debug-extended-library.a condition: - toolchain_gcc diff --git a/protocol/zigbee/component/zigbee_end_device_bind_library.slcc b/protocol/zigbee/component/zigbee_end_device_bind_library.slcc index 3a1ea3504f..5354bc47a8 100644 --- a/protocol/zigbee/component/zigbee_end_device_bind_library.slcc +++ b/protocol/zigbee/component/zigbee_end_device_bind_library.slcc @@ -19,99 +19,6 @@ requires: - name: zigbee_end_device_bind library: - - path: protocol/zigbee/build/end-device-bind-library-cortexm3-iar-efr32mg1p-rail/end-device-bind-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/end-device-bind-library-cortexm3-iar-efr32mg1p-rail-stack_protection/end-device-bind-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/end-device-bind-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/end-device-bind-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/end-device-bind-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/end-device-bind-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/end-device-bind-library-cortexm3-iar-efr32mg1b-rail/end-device-bind-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/end-device-bind-library-cortexm3-iar-efr32mg1b-rail-stack_protection/end-device-bind-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/end-device-bind-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/end-device-bind-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/end-device-bind-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/end-device-bind-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/end-device-bind-library-cortexm3-iar-efr32mg1v-rail/end-device-bind-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/end-device-bind-library-cortexm3-iar-efr32mg1v-rail-stack_protection/end-device-bind-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/end-device-bind-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/end-device-bind-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/end-device-bind-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/end-device-bind-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - path: protocol/zigbee/build/end-device-bind-library-cortexm3-iar-efr32mg12p-rail/end-device-bind-library.a condition: - toolchain_iar @@ -174,19 +81,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/end-device-bind-library-cortexm3-iar-efr32mg14p-rail/end-device-bind-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/end-device-bind-library-cortexm3-iar-efr32mg14p-rail-stack_protection/end-device-bind-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/end-device-bind-library-cortexm3-iar-efr32mg21-rail/end-device-bind-library.a condition: - toolchain_iar @@ -466,54 +360,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/end-device-bind-library-cortexm3-gcc-efr32mg1p-rail/end-device-bind-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/end-device-bind-library-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/end-device-bind-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/end-device-bind-library-cortexm3-gcc-efr32mg1b-rail/end-device-bind-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/end-device-bind-library-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/end-device-bind-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/end-device-bind-library-cortexm3-gcc-efr32mg1v-rail/end-device-bind-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/end-device-bind-library-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/end-device-bind-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - path: protocol/zigbee/build/end-device-bind-library-cortexm3-gcc-efr32mg12p-rail/end-device-bind-library.a condition: - toolchain_gcc @@ -546,13 +392,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/end-device-bind-library-cortexm3-gcc-efr32mg14p-rail/end-device-bind-library.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/end-device-bind-library-cortexm3-gcc-efr32mg21-rail/end-device-bind-library.a condition: - toolchain_gcc diff --git a/protocol/zigbee/component/zigbee_gp_library.slcc b/protocol/zigbee/component/zigbee_gp_library.slcc index 2689225b18..798dd964dd 100644 --- a/protocol/zigbee/component/zigbee_gp_library.slcc +++ b/protocol/zigbee/component/zigbee_gp_library.slcc @@ -19,45 +19,6 @@ requires: - name: zigbee_gp library: - - path: protocol/zigbee/build/gp-library-cortexm3-iar-efr32mg1p-rail/gp-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/gp-library-cortexm3-iar-efr32mg1p-rail-stack_protection/gp-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - - path: protocol/zigbee/build/gp-library-cortexm3-iar-efr32mg1b-rail/gp-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/gp-library-cortexm3-iar-efr32mg1b-rail-stack_protection/gp-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - - path: protocol/zigbee/build/gp-library-cortexm3-iar-efr32mg1v-rail/gp-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/gp-library-cortexm3-iar-efr32mg1v-rail-stack_protection/gp-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/gp-library-cortexm3-iar-efr32mg12p-rail/gp-library.a condition: - toolchain_iar @@ -120,19 +81,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/gp-library-cortexm3-iar-efr32mg14p-rail/gp-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/gp-library-cortexm3-iar-efr32mg14p-rail-stack_protection/gp-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/gp-library-cortexm3-iar-efr32mg21-rail/gp-library.a condition: - toolchain_iar @@ -412,27 +360,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/gp-library-cortexm3-gcc-efr32mg1p-rail/gp-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/gp-library-cortexm3-gcc-efr32mg1b-rail/gp-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/gp-library-cortexm3-gcc-efr32mg1v-rail/gp-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/gp-library-cortexm3-gcc-efr32mg12p-rail/gp-library.a condition: - toolchain_gcc @@ -465,13 +392,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/gp-library-cortexm3-gcc-efr32mg14p-rail/gp-library.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/gp-library-cortexm3-gcc-efr32mg21-rail/gp-library.a condition: - toolchain_gcc @@ -616,51 +536,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/ncp-gp-library-cortexm3-iar-efr32mg1p-rail/ncp-gp-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-gp-library-cortexm3-iar-efr32mg1p-rail-stack_protection/ncp-gp-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - - path: protocol/zigbee/build/ncp-gp-library-cortexm3-iar-efr32mg1b-rail/ncp-gp-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-gp-library-cortexm3-iar-efr32mg1b-rail-stack_protection/ncp-gp-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - - path: protocol/zigbee/build/ncp-gp-library-cortexm3-iar-efr32mg1v-rail/ncp-gp-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-gp-library-cortexm3-iar-efr32mg1v-rail-stack_protection/ncp-gp-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - path: protocol/zigbee/build/ncp-gp-library-cortexm3-iar-efr32mg12p-rail/ncp-gp-library.a condition: - toolchain_iar @@ -691,21 +566,6 @@ library: - zigbee_phy_2_4 - stack_protection_iar - zigbee_ncp - - path: protocol/zigbee/build/ncp-gp-library-cortexm3-iar-efr32mg14p-rail/ncp-gp-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-gp-library-cortexm3-iar-efr32mg14p-rail-stack_protection/ncp-gp-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - path: protocol/zigbee/build/ncp-gp-library-cortexm3-iar-efr32mg21-rail/ncp-gp-library.a condition: - toolchain_iar @@ -841,30 +701,6 @@ library: - zigbee_phy_2_4 - stack_protection_iar - zigbee_ncp - - path: protocol/zigbee/build/ncp-gp-library-cortexm3-gcc-efr32mg1p-rail/ncp-gp-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-gp-library-cortexm3-gcc-efr32mg1b-rail/ncp-gp-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-gp-library-cortexm3-gcc-efr32mg1v-rail/ncp-gp-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - path: protocol/zigbee/build/ncp-gp-library-cortexm3-gcc-efr32mg12p-rail/ncp-gp-library.a condition: - toolchain_gcc @@ -881,14 +717,6 @@ library: - zigbee_ncp unless: - stack_protection_iar - - path: protocol/zigbee/build/ncp-gp-library-cortexm3-gcc-efr32mg14p-rail/ncp-gp-library.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - path: protocol/zigbee/build/ncp-gp-library-cortexm3-gcc-efr32mg21-rail/ncp-gp-library.a condition: - toolchain_gcc diff --git a/protocol/zigbee/component/zigbee_install_code_library.slcc b/protocol/zigbee/component/zigbee_install_code_library.slcc index 2274e9d493..8a45edbdc9 100644 --- a/protocol/zigbee/component/zigbee_install_code_library.slcc +++ b/protocol/zigbee/component/zigbee_install_code_library.slcc @@ -19,99 +19,6 @@ requires: - name: zigbee_install_code library: - - path: protocol/zigbee/build/install-code-library-cortexm3-iar-efr32mg1p-rail/install-code-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/install-code-library-cortexm3-iar-efr32mg1p-rail-stack_protection/install-code-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/install-code-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/install-code-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/install-code-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/install-code-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/install-code-library-cortexm3-iar-efr32mg1b-rail/install-code-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/install-code-library-cortexm3-iar-efr32mg1b-rail-stack_protection/install-code-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/install-code-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/install-code-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/install-code-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/install-code-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/install-code-library-cortexm3-iar-efr32mg1v-rail/install-code-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/install-code-library-cortexm3-iar-efr32mg1v-rail-stack_protection/install-code-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/install-code-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/install-code-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/install-code-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/install-code-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - path: protocol/zigbee/build/install-code-library-cortexm3-iar-efr32mg12p-rail/install-code-library.a condition: - toolchain_iar @@ -174,19 +81,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/install-code-library-cortexm3-iar-efr32mg14p-rail/install-code-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/install-code-library-cortexm3-iar-efr32mg14p-rail-stack_protection/install-code-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/install-code-library-cortexm3-iar-efr32mg21-rail/install-code-library.a condition: - toolchain_iar @@ -466,54 +360,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/install-code-library-cortexm3-gcc-efr32mg1p-rail/install-code-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/install-code-library-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/install-code-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/install-code-library-cortexm3-gcc-efr32mg1b-rail/install-code-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/install-code-library-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/install-code-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/install-code-library-cortexm3-gcc-efr32mg1v-rail/install-code-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/install-code-library-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/install-code-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - path: protocol/zigbee/build/install-code-library-cortexm3-gcc-efr32mg12p-rail/install-code-library.a condition: - toolchain_gcc @@ -546,13 +392,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/install-code-library-cortexm3-gcc-efr32mg14p-rail/install-code-library.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/install-code-library-cortexm3-gcc-efr32mg21-rail/install-code-library.a condition: - toolchain_gcc diff --git a/protocol/zigbee/component/zigbee_mfglib_library.slcc b/protocol/zigbee/component/zigbee_mfglib_library.slcc index e2f5e47054..9e442101fc 100644 --- a/protocol/zigbee/component/zigbee_mfglib_library.slcc +++ b/protocol/zigbee/component/zigbee_mfglib_library.slcc @@ -19,99 +19,6 @@ requires: - name: zigbee_mfglib library: - - path: protocol/zigbee/build/mfglib-library-cortexm3-iar-efr32mg1p-rail/mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/mfglib-library-cortexm3-iar-efr32mg1p-rail-stack_protection/mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/mfglib-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/mfglib-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/mfglib-library-cortexm3-iar-efr32mg1b-rail/mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/mfglib-library-cortexm3-iar-efr32mg1b-rail-stack_protection/mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/mfglib-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/mfglib-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/mfglib-library-cortexm3-iar-efr32mg1v-rail/mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/mfglib-library-cortexm3-iar-efr32mg1v-rail-stack_protection/mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/mfglib-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/mfglib-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - path: protocol/zigbee/build/mfglib-library-cortexm3-iar-efr32mg12p-rail/mfglib-library.a condition: - toolchain_iar @@ -174,19 +81,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/mfglib-library-cortexm3-iar-efr32mg14p-rail/mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/mfglib-library-cortexm3-iar-efr32mg14p-rail-stack_protection/mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/mfglib-library-cortexm3-iar-efr32mg21-rail/mfglib-library.a condition: - toolchain_iar @@ -466,54 +360,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/mfglib-library-cortexm3-gcc-efr32mg1p-rail/mfglib-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/mfglib-library-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/mfglib-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/mfglib-library-cortexm3-gcc-efr32mg1b-rail/mfglib-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/mfglib-library-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/mfglib-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/mfglib-library-cortexm3-gcc-efr32mg1v-rail/mfglib-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/mfglib-library-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/mfglib-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - path: protocol/zigbee/build/mfglib-library-cortexm3-gcc-efr32mg12p-rail/mfglib-library.a condition: - toolchain_gcc @@ -546,13 +392,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/mfglib-library-cortexm3-gcc-efr32mg14p-rail/mfglib-library.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/mfglib-library-cortexm3-gcc-efr32mg21-rail/mfglib-library.a condition: - toolchain_gcc @@ -697,111 +536,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/ncp-mfglib-library-cortexm3-iar-efr32mg1p-rail/ncp-mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-mfglib-library-cortexm3-iar-efr32mg1p-rail-stack_protection/ncp-mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-mfglib-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/ncp-mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-mfglib-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/ncp-mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - zigbee_ncp - - path: protocol/zigbee/build/ncp-mfglib-library-cortexm3-iar-efr32mg1b-rail/ncp-mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-mfglib-library-cortexm3-iar-efr32mg1b-rail-stack_protection/ncp-mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-mfglib-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/ncp-mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-mfglib-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/ncp-mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - zigbee_ncp - - path: protocol/zigbee/build/ncp-mfglib-library-cortexm3-iar-efr32mg1v-rail/ncp-mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-mfglib-library-cortexm3-iar-efr32mg1v-rail-stack_protection/ncp-mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-mfglib-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/ncp-mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-mfglib-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/ncp-mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - zigbee_ncp - path: protocol/zigbee/build/ncp-mfglib-library-cortexm3-iar-efr32mg12p-rail/ncp-mfglib-library.a condition: - toolchain_iar @@ -872,21 +606,6 @@ library: - zigbee_ncp unless: - zigbee_multi_network - - path: protocol/zigbee/build/ncp-mfglib-library-cortexm3-iar-efr32mg14p-rail/ncp-mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-mfglib-library-cortexm3-iar-efr32mg14p-rail-stack_protection/ncp-mfglib-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - path: protocol/zigbee/build/ncp-mfglib-library-cortexm3-iar-efr32mg21-rail/ncp-mfglib-library.a condition: - toolchain_iar @@ -1202,60 +921,6 @@ library: - zigbee_ncp unless: - zigbee_multi_network - - path: protocol/zigbee/build/ncp-mfglib-library-cortexm3-gcc-efr32mg1p-rail/ncp-mfglib-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-mfglib-library-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/ncp-mfglib-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-mfglib-library-cortexm3-gcc-efr32mg1b-rail/ncp-mfglib-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-mfglib-library-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/ncp-mfglib-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-mfglib-library-cortexm3-gcc-efr32mg1v-rail/ncp-mfglib-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-mfglib-library-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/ncp-mfglib-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - path: protocol/zigbee/build/ncp-mfglib-library-cortexm3-gcc-efr32mg12p-rail/ncp-mfglib-library.a condition: - toolchain_gcc @@ -1292,14 +957,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/ncp-mfglib-library-cortexm3-gcc-efr32mg14p-rail/ncp-mfglib-library.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - path: protocol/zigbee/build/ncp-mfglib-library-cortexm3-gcc-efr32mg21-rail/ncp-mfglib-library.a condition: - toolchain_gcc @@ -1462,3 +1119,27 @@ library: unless: - zigbee_multi_network - stack_protection_iar + - path: protocol/zigbee/build/mfglib-library-unix-gcc-simulation-null-arm32v7-ember_multi_network_stripped/mfglib-library.a + condition: + - toolchain_gcc + - zigbee_stack_unix + - zigbee_ncp + - linux_arch_32 + - path: protocol/zigbee/build/mfglib-library-unix-gcc-simulation-null-arm64v8-ember_multi_network_stripped/mfglib-library.a + condition: + - toolchain_gcc + - zigbee_stack_unix + - zigbee_ncp + - linux_arch_64 + - path: protocol/zigbee/build/ncp-mfglib-library-unix-gcc-simulation-null-arm32v7-ember_multi_network_stripped/ncp-mfglib-library.a + condition: + - toolchain_gcc + - zigbee_stack_unix + - zigbee_ncp + - linux_arch_32 + - path: protocol/zigbee/build/ncp-mfglib-library-unix-gcc-simulation-null-arm64v8-ember_multi_network_stripped/ncp-mfglib-library.a + condition: + - toolchain_gcc + - zigbee_stack_unix + - zigbee_ncp + - linux_arch_64 diff --git a/protocol/zigbee/component/zigbee_ncp_cpc_library.slcc b/protocol/zigbee/component/zigbee_ncp_cpc_library.slcc index 2639a4388d..d6f565efbf 100644 --- a/protocol/zigbee/component/zigbee_ncp_cpc_library.slcc +++ b/protocol/zigbee/component/zigbee_ncp_cpc_library.slcc @@ -5,7 +5,7 @@ id: zigbee_ncp_cpc_library label: NCP CPC (Library) package: Zigbee category: Zigbee|Stack -quality: alpha +quality: production ui_hints: visibility: never @@ -19,99 +19,6 @@ requires: - name: zigbee_ncp_cpc library: - - path: protocol/zigbee/build/em260-cpc-library-cortexm3-iar-efr32mg1p-rail/em260-cpc-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-cpc-library-cortexm3-iar-efr32mg1p-rail-stack_protection/em260-cpc-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-cpc-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/em260-cpc-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/em260-cpc-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/em260-cpc-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/em260-cpc-library-cortexm3-iar-efr32mg1b-rail/em260-cpc-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-cpc-library-cortexm3-iar-efr32mg1b-rail-stack_protection/em260-cpc-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-cpc-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/em260-cpc-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/em260-cpc-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/em260-cpc-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/em260-cpc-library-cortexm3-iar-efr32mg1v-rail/em260-cpc-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-cpc-library-cortexm3-iar-efr32mg1v-rail-stack_protection/em260-cpc-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-cpc-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/em260-cpc-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/em260-cpc-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/em260-cpc-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - path: protocol/zigbee/build/em260-cpc-library-cortexm3-iar-efr32mg12p-rail/em260-cpc-library.a condition: - toolchain_iar @@ -174,19 +81,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/em260-cpc-library-cortexm3-iar-efr32mg14p-rail/em260-cpc-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/em260-cpc-library-cortexm3-iar-efr32mg14p-rail-stack_protection/em260-cpc-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/em260-cpc-library-cortexm3-iar-efr32mg21-rail/em260-cpc-library.a condition: - toolchain_iar @@ -466,54 +360,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/em260-cpc-library-cortexm3-gcc-efr32mg1p-rail/em260-cpc-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-cpc-library-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/em260-cpc-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/em260-cpc-library-cortexm3-gcc-efr32mg1b-rail/em260-cpc-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-cpc-library-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/em260-cpc-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/em260-cpc-library-cortexm3-gcc-efr32mg1v-rail/em260-cpc-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-cpc-library-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/em260-cpc-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - path: protocol/zigbee/build/em260-cpc-library-cortexm3-gcc-efr32mg12p-rail/em260-cpc-library.a condition: - toolchain_gcc @@ -546,13 +392,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/em260-cpc-library-cortexm3-gcc-efr32mg14p-rail/em260-cpc-library.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/em260-cpc-library-cortexm3-gcc-efr32mg21-rail/em260-cpc-library.a condition: - toolchain_gcc diff --git a/protocol/zigbee/component/zigbee_ncp_spi_library.slcc b/protocol/zigbee/component/zigbee_ncp_spi_library.slcc index 575d93a131..1a81d64952 100644 --- a/protocol/zigbee/component/zigbee_ncp_spi_library.slcc +++ b/protocol/zigbee/component/zigbee_ncp_spi_library.slcc @@ -19,99 +19,6 @@ requires: - name: zigbee_ncp_spi library: - - path: protocol/zigbee/build/em260-spi-util-library-cortexm3-iar-efr32mg1p-rail/em260-spi-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-spi-util-library-cortexm3-iar-efr32mg1p-rail-stack_protection/em260-spi-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-spi-util-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/em260-spi-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/em260-spi-util-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/em260-spi-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/em260-spi-util-library-cortexm3-iar-efr32mg1b-rail/em260-spi-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-spi-util-library-cortexm3-iar-efr32mg1b-rail-stack_protection/em260-spi-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-spi-util-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/em260-spi-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/em260-spi-util-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/em260-spi-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/em260-spi-util-library-cortexm3-iar-efr32mg1v-rail/em260-spi-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-spi-util-library-cortexm3-iar-efr32mg1v-rail-stack_protection/em260-spi-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-spi-util-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/em260-spi-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/em260-spi-util-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/em260-spi-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - path: protocol/zigbee/build/em260-spi-util-library-cortexm3-iar-efr32mg12p-rail/em260-spi-util-library.a condition: - toolchain_iar @@ -174,19 +81,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/em260-spi-util-library-cortexm3-iar-efr32mg14p-rail/em260-spi-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/em260-spi-util-library-cortexm3-iar-efr32mg14p-rail-stack_protection/em260-spi-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/em260-spi-util-library-cortexm3-iar-efr32mg21-rail/em260-spi-util-library.a condition: - toolchain_iar @@ -466,54 +360,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/em260-spi-util-library-cortexm3-gcc-efr32mg1p-rail/em260-spi-util-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-spi-util-library-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/em260-spi-util-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/em260-spi-util-library-cortexm3-gcc-efr32mg1b-rail/em260-spi-util-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-spi-util-library-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/em260-spi-util-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/em260-spi-util-library-cortexm3-gcc-efr32mg1v-rail/em260-spi-util-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-spi-util-library-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/em260-spi-util-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - path: protocol/zigbee/build/em260-spi-util-library-cortexm3-gcc-efr32mg12p-rail/em260-spi-util-library.a condition: - toolchain_gcc @@ -546,13 +392,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/em260-spi-util-library-cortexm3-gcc-efr32mg14p-rail/em260-spi-util-library.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/em260-spi-util-library-cortexm3-gcc-efr32mg21-rail/em260-spi-util-library.a condition: - toolchain_gcc diff --git a/protocol/zigbee/component/zigbee_ncp_uart_library.slcc b/protocol/zigbee/component/zigbee_ncp_uart_library.slcc index 41bc50ac33..d8c1391e16 100644 --- a/protocol/zigbee/component/zigbee_ncp_uart_library.slcc +++ b/protocol/zigbee/component/zigbee_ncp_uart_library.slcc @@ -19,99 +19,6 @@ requires: - name: zigbee_ncp_uart library: - - path: protocol/zigbee/build/em260-uart-util-library-cortexm3-iar-efr32mg1p-rail/em260-uart-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-uart-util-library-cortexm3-iar-efr32mg1p-rail-stack_protection/em260-uart-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-uart-util-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/em260-uart-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/em260-uart-util-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/em260-uart-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/em260-uart-util-library-cortexm3-iar-efr32mg1b-rail/em260-uart-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-uart-util-library-cortexm3-iar-efr32mg1b-rail-stack_protection/em260-uart-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-uart-util-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/em260-uart-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/em260-uart-util-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/em260-uart-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/em260-uart-util-library-cortexm3-iar-efr32mg1v-rail/em260-uart-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-uart-util-library-cortexm3-iar-efr32mg1v-rail-stack_protection/em260-uart-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-uart-util-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/em260-uart-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/em260-uart-util-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/em260-uart-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - path: protocol/zigbee/build/em260-uart-util-library-cortexm3-iar-efr32mg12p-rail/em260-uart-util-library.a condition: - toolchain_iar @@ -174,19 +81,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/em260-uart-util-library-cortexm3-iar-efr32mg14p-rail/em260-uart-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/em260-uart-util-library-cortexm3-iar-efr32mg14p-rail-stack_protection/em260-uart-util-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/em260-uart-util-library-cortexm3-iar-efr32mg21-rail/em260-uart-util-library.a condition: - toolchain_iar @@ -466,54 +360,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/em260-uart-util-library-cortexm3-gcc-efr32mg1p-rail/em260-uart-util-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-uart-util-library-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/em260-uart-util-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/em260-uart-util-library-cortexm3-gcc-efr32mg1b-rail/em260-uart-util-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-uart-util-library-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/em260-uart-util-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/em260-uart-util-library-cortexm3-gcc-efr32mg1v-rail/em260-uart-util-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-uart-util-library-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/em260-uart-util-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - path: protocol/zigbee/build/em260-uart-util-library-cortexm3-gcc-efr32mg12p-rail/em260-uart-util-library.a condition: - toolchain_gcc @@ -546,13 +392,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/em260-uart-util-library-cortexm3-gcc-efr32mg14p-rail/em260-uart-util-library.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/em260-uart-util-library-cortexm3-gcc-efr32mg21-rail/em260-uart-util-library.a condition: - toolchain_gcc diff --git a/protocol/zigbee/component/zigbee_packet_validate_library.slcc b/protocol/zigbee/component/zigbee_packet_validate_library.slcc index d62e03bbc3..01d9db7c2e 100644 --- a/protocol/zigbee/component/zigbee_packet_validate_library.slcc +++ b/protocol/zigbee/component/zigbee_packet_validate_library.slcc @@ -19,99 +19,6 @@ requires: - name: zigbee_packet_validate library: - - path: protocol/zigbee/build/packet-validate-library-cortexm3-iar-efr32mg1p-rail/packet-validate-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/packet-validate-library-cortexm3-iar-efr32mg1p-rail-stack_protection/packet-validate-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/packet-validate-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/packet-validate-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/packet-validate-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/packet-validate-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/packet-validate-library-cortexm3-iar-efr32mg1b-rail/packet-validate-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/packet-validate-library-cortexm3-iar-efr32mg1b-rail-stack_protection/packet-validate-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/packet-validate-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/packet-validate-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/packet-validate-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/packet-validate-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/packet-validate-library-cortexm3-iar-efr32mg1v-rail/packet-validate-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/packet-validate-library-cortexm3-iar-efr32mg1v-rail-stack_protection/packet-validate-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/packet-validate-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/packet-validate-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/packet-validate-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/packet-validate-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - path: protocol/zigbee/build/packet-validate-library-cortexm3-iar-efr32mg12p-rail/packet-validate-library.a condition: - toolchain_iar @@ -138,19 +45,6 @@ library: - device_family_efr32mg13p - zigbee_phy_2_4 - stack_protection_iar - - path: protocol/zigbee/build/packet-validate-library-cortexm3-iar-efr32mg14p-rail/packet-validate-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/packet-validate-library-cortexm3-iar-efr32mg14p-rail-stack_protection/packet-validate-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/packet-validate-library-cortexm3-iar-efr32mg21-rail/packet-validate-library.a condition: - toolchain_iar @@ -268,54 +162,6 @@ library: - device_family_mgm24 - zigbee_phy_2_4 - stack_protection_iar - - path: protocol/zigbee/build/packet-validate-library-cortexm3-gcc-efr32mg1p-rail/packet-validate-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/packet-validate-library-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/packet-validate-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/packet-validate-library-cortexm3-gcc-efr32mg1b-rail/packet-validate-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/packet-validate-library-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/packet-validate-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/packet-validate-library-cortexm3-gcc-efr32mg1v-rail/packet-validate-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/packet-validate-library-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/packet-validate-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - path: protocol/zigbee/build/packet-validate-library-cortexm3-gcc-efr32mg12p-rail/packet-validate-library.a condition: - toolchain_gcc @@ -330,13 +176,6 @@ library: - zigbee_phy_2_4 unless: - stack_protection_iar - - path: protocol/zigbee/build/packet-validate-library-cortexm3-gcc-efr32mg14p-rail/packet-validate-library.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/packet-validate-library-cortexm3-gcc-efr32mg21-rail/packet-validate-library.a condition: - toolchain_gcc diff --git a/protocol/zigbee/component/zigbee_pro_leaf_stack_library.slcc b/protocol/zigbee/component/zigbee_pro_leaf_stack_library.slcc index 6c43c44ea2..25d671a339 100644 --- a/protocol/zigbee/component/zigbee_pro_leaf_stack_library.slcc +++ b/protocol/zigbee/component/zigbee_pro_leaf_stack_library.slcc @@ -20,99 +20,6 @@ requires: - name: zigbee_pro_leaf_stack library: - - path: protocol/zigbee/build/zigbee-pro-leaf-stack-cortexm3-iar-efr32mg1p-rail/zigbee-pro-leaf-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/zigbee-pro-leaf-stack-cortexm3-iar-efr32mg1p-rail-stack_protection/zigbee-pro-leaf-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/zigbee-pro-leaf-stack-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/zigbee-pro-leaf-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-leaf-stack-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/zigbee-pro-leaf-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-leaf-stack-cortexm3-iar-efr32mg1b-rail/zigbee-pro-leaf-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/zigbee-pro-leaf-stack-cortexm3-iar-efr32mg1b-rail-stack_protection/zigbee-pro-leaf-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/zigbee-pro-leaf-stack-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/zigbee-pro-leaf-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-leaf-stack-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/zigbee-pro-leaf-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-leaf-stack-cortexm3-iar-efr32mg1v-rail/zigbee-pro-leaf-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/zigbee-pro-leaf-stack-cortexm3-iar-efr32mg1v-rail-stack_protection/zigbee-pro-leaf-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/zigbee-pro-leaf-stack-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/zigbee-pro-leaf-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-leaf-stack-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/zigbee-pro-leaf-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - path: protocol/zigbee/build/zigbee-pro-leaf-stack-cortexm3-iar-efr32mg12p-rail/zigbee-pro-leaf-stack.a condition: - toolchain_iar @@ -175,19 +82,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/zigbee-pro-leaf-stack-cortexm3-iar-efr32mg14p-rail/zigbee-pro-leaf-stack.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-leaf-stack-cortexm3-iar-efr32mg14p-rail-stack_protection/zigbee-pro-leaf-stack.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/zigbee-pro-leaf-stack-cortexm3-iar-efr32mg21-rail/zigbee-pro-leaf-stack.a condition: - toolchain_iar @@ -467,54 +361,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/zigbee-pro-leaf-stack-cortexm3-gcc-efr32mg1p-rail/zigbee-pro-leaf-stack.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/zigbee-pro-leaf-stack-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/zigbee-pro-leaf-stack.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-leaf-stack-cortexm3-gcc-efr32mg1b-rail/zigbee-pro-leaf-stack.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/zigbee-pro-leaf-stack-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/zigbee-pro-leaf-stack.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-leaf-stack-cortexm3-gcc-efr32mg1v-rail/zigbee-pro-leaf-stack.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/zigbee-pro-leaf-stack-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/zigbee-pro-leaf-stack.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - path: protocol/zigbee/build/zigbee-pro-leaf-stack-cortexm3-gcc-efr32mg12p-rail/zigbee-pro-leaf-stack.a condition: - toolchain_gcc @@ -547,13 +393,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-leaf-stack-cortexm3-gcc-efr32mg14p-rail/zigbee-pro-leaf-stack.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/zigbee-pro-leaf-stack-cortexm3-gcc-efr32mg21-rail/zigbee-pro-leaf-stack.a condition: - toolchain_gcc @@ -698,111 +537,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1p-rail/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1p-rail-stack_protection/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - zigbee_ncp - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1b-rail/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1b-rail-stack_protection/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - zigbee_ncp - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1v-rail/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1v-rail-stack_protection/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - zigbee_ncp - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg12p-rail/ncp-pro-library.a condition: - toolchain_iar @@ -873,21 +607,6 @@ library: - zigbee_ncp unless: - zigbee_multi_network - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg14p-rail/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg14p-rail-stack_protection/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg21-rail/ncp-pro-library.a condition: - toolchain_iar @@ -1203,60 +922,6 @@ library: - zigbee_ncp unless: - zigbee_multi_network - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg1p-rail/ncp-pro-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/ncp-pro-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg1b-rail/ncp-pro-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/ncp-pro-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg1v-rail/ncp-pro-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/ncp-pro-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg12p-rail/ncp-pro-library.a condition: - toolchain_gcc @@ -1293,14 +958,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg14p-rail/ncp-pro-library.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg21-rail/ncp-pro-library.a condition: - toolchain_gcc diff --git a/protocol/zigbee/component/zigbee_pro_stack_alt_mac_library.slcc b/protocol/zigbee/component/zigbee_pro_stack_alt_mac_library.slcc index f856332c49..5aa5dc48dd 100644 --- a/protocol/zigbee/component/zigbee_pro_stack_alt_mac_library.slcc +++ b/protocol/zigbee/component/zigbee_pro_stack_alt_mac_library.slcc @@ -20,45 +20,6 @@ requires: - name: zigbee_pro_stack_alt_mac library: - - path: protocol/zigbee/build/zigbee-pro-stack-alt-mac-cortexm3-iar-efr32mg1p-rail/zigbee-pro-stack-alt-mac.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-stack-alt-mac-cortexm3-iar-efr32mg1p-rail-stack_protection/zigbee-pro-stack-alt-mac.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-stack-alt-mac-cortexm3-iar-efr32mg1b-rail/zigbee-pro-stack-alt-mac.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-stack-alt-mac-cortexm3-iar-efr32mg1b-rail-stack_protection/zigbee-pro-stack-alt-mac.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-stack-alt-mac-cortexm3-iar-efr32mg1v-rail/zigbee-pro-stack-alt-mac.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-stack-alt-mac-cortexm3-iar-efr32mg1v-rail-stack_protection/zigbee-pro-stack-alt-mac.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/zigbee-pro-stack-alt-mac-cortexm3-iar-efr32mg12p-rail/zigbee-pro-stack-alt-mac.a condition: - toolchain_iar @@ -121,19 +82,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/zigbee-pro-stack-alt-mac-cortexm3-iar-efr32mg14p-rail/zigbee-pro-stack-alt-mac.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-stack-alt-mac-cortexm3-iar-efr32mg14p-rail-stack_protection/zigbee-pro-stack-alt-mac.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/zigbee-pro-stack-alt-mac-cortexm3-iar-efr32mg21-rail/zigbee-pro-stack-alt-mac.a condition: - toolchain_iar @@ -413,27 +361,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/zigbee-pro-stack-alt-mac-cortexm3-gcc-efr32mg1p-rail/zigbee-pro-stack-alt-mac.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-stack-alt-mac-cortexm3-gcc-efr32mg1b-rail/zigbee-pro-stack-alt-mac.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-stack-alt-mac-cortexm3-gcc-efr32mg1v-rail/zigbee-pro-stack-alt-mac.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/zigbee-pro-stack-alt-mac-cortexm3-gcc-efr32mg12p-rail/zigbee-pro-stack-alt-mac.a condition: - toolchain_gcc @@ -466,13 +393,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-stack-alt-mac-cortexm3-gcc-efr32mg14p-rail/zigbee-pro-stack-alt-mac.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/zigbee-pro-stack-alt-mac-cortexm3-gcc-efr32mg21-rail/zigbee-pro-stack-alt-mac.a condition: - toolchain_gcc @@ -617,111 +537,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1p-rail/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1p-rail-stack_protection/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - zigbee_ncp - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1b-rail/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1b-rail-stack_protection/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - zigbee_ncp - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1v-rail/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1v-rail-stack_protection/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - zigbee_ncp - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg12p-rail/ncp-pro-library.a condition: - toolchain_iar @@ -792,21 +607,6 @@ library: - zigbee_ncp unless: - zigbee_multi_network - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg14p-rail/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg14p-rail-stack_protection/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg21-rail/ncp-pro-library.a condition: - toolchain_iar @@ -1122,60 +922,6 @@ library: - zigbee_ncp unless: - zigbee_multi_network - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg1p-rail/ncp-pro-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/ncp-pro-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg1b-rail/ncp-pro-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/ncp-pro-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg1v-rail/ncp-pro-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/ncp-pro-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg12p-rail/ncp-pro-library.a condition: - toolchain_gcc @@ -1212,14 +958,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg14p-rail/ncp-pro-library.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg21-rail/ncp-pro-library.a condition: - toolchain_gcc diff --git a/protocol/zigbee/component/zigbee_pro_stack_library.slcc b/protocol/zigbee/component/zigbee_pro_stack_library.slcc index bc9f98ce7e..7beac7764e 100644 --- a/protocol/zigbee/component/zigbee_pro_stack_library.slcc +++ b/protocol/zigbee/component/zigbee_pro_stack_library.slcc @@ -20,162 +20,6 @@ requires: - name: zigbee_pro_stack library: - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-iar-efr32mg1p-rail/zigbee-pro-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - rail_mux - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-iar-efr32mg1p-rail-stack_protection/zigbee-pro-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - rail_mux - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/zigbee-pro-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - rail_mux - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/zigbee-pro-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-iar-efr32mg1p-rail-rail_mux/zigbee-pro-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - rail_mux - unless: - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-iar-efr32mg1p-rail-rail_mux-stack_protection/zigbee-pro-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - - rail_mux - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-iar-efr32mg1b-rail/zigbee-pro-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - rail_mux - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-iar-efr32mg1b-rail-stack_protection/zigbee-pro-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - rail_mux - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/zigbee-pro-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - rail_mux - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/zigbee-pro-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-iar-efr32mg1b-rail-rail_mux/zigbee-pro-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - rail_mux - unless: - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-iar-efr32mg1b-rail-rail_mux-stack_protection/zigbee-pro-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - - rail_mux - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-iar-efr32mg1v-rail/zigbee-pro-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - rail_mux - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-iar-efr32mg1v-rail-stack_protection/zigbee-pro-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - rail_mux - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/zigbee-pro-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - rail_mux - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/zigbee-pro-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-iar-efr32mg1v-rail-rail_mux/zigbee-pro-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - rail_mux - unless: - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-iar-efr32mg1v-rail-rail_mux-stack_protection/zigbee-pro-stack.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - - rail_mux - unless: - - zigbee_smart_energy_token_optimization - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-iar-efr32mg12p-rail/zigbee-pro-stack.a condition: - toolchain_iar @@ -294,37 +138,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-iar-efr32mg14p-rail/zigbee-pro-stack.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - rail_mux - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-iar-efr32mg14p-rail-stack_protection/zigbee-pro-stack.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - rail_mux - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-iar-efr32mg14p-rail-rail_mux/zigbee-pro-stack.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - rail_mux - unless: - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-iar-efr32mg14p-rail-rail_mux-stack_protection/zigbee-pro-stack.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - - rail_mux - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-iar-efr32mg21-rail/zigbee-pro-stack.a condition: - toolchain_iar @@ -856,87 +669,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-gcc-efr32mg1p-rail/zigbee-pro-stack.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - rail_mux - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/zigbee-pro-stack.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - rail_mux - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-gcc-efr32mg1p-rail-rail_mux/zigbee-pro-stack.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - rail_mux - unless: - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-gcc-efr32mg1b-rail/zigbee-pro-stack.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - rail_mux - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/zigbee-pro-stack.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - rail_mux - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-gcc-efr32mg1b-rail-rail_mux/zigbee-pro-stack.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - rail_mux - unless: - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-gcc-efr32mg1v-rail/zigbee-pro-stack.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - rail_mux - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/zigbee-pro-stack.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - rail_mux - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-gcc-efr32mg1v-rail-rail_mux/zigbee-pro-stack.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - rail_mux - unless: - - zigbee_smart_energy_token_optimization - - stack_protection_iar - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-gcc-efr32mg12p-rail/zigbee-pro-stack.a condition: - toolchain_gcc @@ -1007,22 +739,6 @@ library: - zigbee_multi_network - stack_protection_iar - rail_mux - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-gcc-efr32mg14p-rail/zigbee-pro-stack.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - rail_mux - - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-gcc-efr32mg14p-rail-rail_mux/zigbee-pro-stack.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - - rail_mux - unless: - - stack_protection_iar - path: protocol/zigbee/build/zigbee-pro-stack-cortexm3-gcc-efr32mg21-rail/zigbee-pro-stack.a condition: - toolchain_gcc @@ -1338,111 +1054,6 @@ library: - zigbee_multi_network - stack_protection_iar - rail_mux - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1p-rail/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1p-rail-stack_protection/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - zigbee_ncp - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1b-rail/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1b-rail-stack_protection/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - zigbee_ncp - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1v-rail/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1v-rail-stack_protection/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - zigbee_ncp - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg12p-rail/ncp-pro-library.a condition: - toolchain_iar @@ -1513,21 +1124,6 @@ library: - zigbee_ncp unless: - zigbee_multi_network - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg14p-rail/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg14p-rail-stack_protection/ncp-pro-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - path: protocol/zigbee/build/ncp-pro-library-cortexm3-iar-efr32mg21-rail/ncp-pro-library.a condition: - toolchain_iar @@ -1843,60 +1439,6 @@ library: - zigbee_ncp unless: - zigbee_multi_network - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg1p-rail/ncp-pro-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/ncp-pro-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg1b-rail/ncp-pro-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/ncp-pro-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg1v-rail/ncp-pro-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/ncp-pro-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg12p-rail/ncp-pro-library.a condition: - toolchain_gcc @@ -1933,14 +1475,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg14p-rail/ncp-pro-library.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - path: protocol/zigbee/build/ncp-pro-library-cortexm3-gcc-efr32mg21-rail/ncp-pro-library.a condition: - toolchain_gcc diff --git a/protocol/zigbee/component/zigbee_r22_support_library.slcc b/protocol/zigbee/component/zigbee_r22_support_library.slcc index 052d6d5860..fa17eb9a9b 100644 --- a/protocol/zigbee/component/zigbee_r22_support_library.slcc +++ b/protocol/zigbee/component/zigbee_r22_support_library.slcc @@ -19,99 +19,6 @@ requires: - name: zigbee_r22_support library: - - path: protocol/zigbee/build/zigbee-r22-support-library-cortexm3-iar-efr32mg1p-rail/zigbee-r22-support-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/zigbee-r22-support-library-cortexm3-iar-efr32mg1p-rail-stack_protection/zigbee-r22-support-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/zigbee-r22-support-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/zigbee-r22-support-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-r22-support-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/zigbee-r22-support-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-r22-support-library-cortexm3-iar-efr32mg1b-rail/zigbee-r22-support-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/zigbee-r22-support-library-cortexm3-iar-efr32mg1b-rail-stack_protection/zigbee-r22-support-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/zigbee-r22-support-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/zigbee-r22-support-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-r22-support-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/zigbee-r22-support-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-r22-support-library-cortexm3-iar-efr32mg1v-rail/zigbee-r22-support-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/zigbee-r22-support-library-cortexm3-iar-efr32mg1v-rail-stack_protection/zigbee-r22-support-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/zigbee-r22-support-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/zigbee-r22-support-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-r22-support-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/zigbee-r22-support-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - path: protocol/zigbee/build/zigbee-r22-support-library-cortexm3-iar-efr32mg12p-rail/zigbee-r22-support-library.a condition: - toolchain_iar @@ -174,19 +81,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/zigbee-r22-support-library-cortexm3-iar-efr32mg14p-rail/zigbee-r22-support-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-r22-support-library-cortexm3-iar-efr32mg14p-rail-stack_protection/zigbee-r22-support-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/zigbee-r22-support-library-cortexm3-iar-efr32mg21-rail/zigbee-r22-support-library.a condition: - toolchain_iar @@ -466,54 +360,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/zigbee-r22-support-library-cortexm3-gcc-efr32mg1p-rail/zigbee-r22-support-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/zigbee-r22-support-library-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/zigbee-r22-support-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-r22-support-library-cortexm3-gcc-efr32mg1b-rail/zigbee-r22-support-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/zigbee-r22-support-library-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/zigbee-r22-support-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/zigbee-r22-support-library-cortexm3-gcc-efr32mg1v-rail/zigbee-r22-support-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/zigbee-r22-support-library-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/zigbee-r22-support-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - path: protocol/zigbee/build/zigbee-r22-support-library-cortexm3-gcc-efr32mg12p-rail/zigbee-r22-support-library.a condition: - toolchain_gcc @@ -546,13 +392,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/zigbee-r22-support-library-cortexm3-gcc-efr32mg14p-rail/zigbee-r22-support-library.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/zigbee-r22-support-library-cortexm3-gcc-efr32mg21-rail/zigbee-r22-support-library.a condition: - toolchain_gcc diff --git a/protocol/zigbee/component/zigbee_security_link_keys_library.slcc b/protocol/zigbee/component/zigbee_security_link_keys_library.slcc index 15c5d43cef..eed351effe 100644 --- a/protocol/zigbee/component/zigbee_security_link_keys_library.slcc +++ b/protocol/zigbee/component/zigbee_security_link_keys_library.slcc @@ -19,99 +19,6 @@ requires: - name: zigbee_security_link_keys library: - - path: protocol/zigbee/build/security-library-link-keys-cortexm3-iar-efr32mg1p-rail/security-library-link-keys.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/security-library-link-keys-cortexm3-iar-efr32mg1p-rail-stack_protection/security-library-link-keys.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/security-library-link-keys-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/security-library-link-keys.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/security-library-link-keys-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/security-library-link-keys.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/security-library-link-keys-cortexm3-iar-efr32mg1b-rail/security-library-link-keys.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/security-library-link-keys-cortexm3-iar-efr32mg1b-rail-stack_protection/security-library-link-keys.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/security-library-link-keys-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/security-library-link-keys.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/security-library-link-keys-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/security-library-link-keys.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/security-library-link-keys-cortexm3-iar-efr32mg1v-rail/security-library-link-keys.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/security-library-link-keys-cortexm3-iar-efr32mg1v-rail-stack_protection/security-library-link-keys.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/security-library-link-keys-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/security-library-link-keys.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/security-library-link-keys-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/security-library-link-keys.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - path: protocol/zigbee/build/security-library-link-keys-cortexm3-iar-efr32mg12p-rail/security-library-link-keys.a condition: - toolchain_iar @@ -174,19 +81,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/security-library-link-keys-cortexm3-iar-efr32mg14p-rail/security-library-link-keys.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/security-library-link-keys-cortexm3-iar-efr32mg14p-rail-stack_protection/security-library-link-keys.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/security-library-link-keys-cortexm3-iar-efr32mg21-rail/security-library-link-keys.a condition: - toolchain_iar @@ -466,54 +360,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/security-library-link-keys-cortexm3-gcc-efr32mg1p-rail/security-library-link-keys.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/security-library-link-keys-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/security-library-link-keys.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/security-library-link-keys-cortexm3-gcc-efr32mg1b-rail/security-library-link-keys.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/security-library-link-keys-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/security-library-link-keys.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/security-library-link-keys-cortexm3-gcc-efr32mg1v-rail/security-library-link-keys.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/security-library-link-keys-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/security-library-link-keys.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - path: protocol/zigbee/build/security-library-link-keys-cortexm3-gcc-efr32mg12p-rail/security-library-link-keys.a condition: - toolchain_gcc @@ -546,13 +392,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/security-library-link-keys-cortexm3-gcc-efr32mg14p-rail/security-library-link-keys.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/security-library-link-keys-cortexm3-gcc-efr32mg21-rail/security-library-link-keys.a condition: - toolchain_gcc diff --git a/protocol/zigbee/component/zigbee_source_route_library.slcc b/protocol/zigbee/component/zigbee_source_route_library.slcc index 98495a705d..5079ae0eb0 100644 --- a/protocol/zigbee/component/zigbee_source_route_library.slcc +++ b/protocol/zigbee/component/zigbee_source_route_library.slcc @@ -19,99 +19,6 @@ requires: - name: zigbee_source_route library: - - path: protocol/zigbee/build/source-route-library-cortexm3-iar-efr32mg1p-rail/source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/source-route-library-cortexm3-iar-efr32mg1p-rail-stack_protection/source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/source-route-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/source-route-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/source-route-library-cortexm3-iar-efr32mg1b-rail/source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/source-route-library-cortexm3-iar-efr32mg1b-rail-stack_protection/source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/source-route-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/source-route-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/source-route-library-cortexm3-iar-efr32mg1v-rail/source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/source-route-library-cortexm3-iar-efr32mg1v-rail-stack_protection/source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/source-route-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/source-route-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - path: protocol/zigbee/build/source-route-library-cortexm3-iar-efr32mg12p-rail/source-route-library.a condition: - toolchain_iar @@ -174,19 +81,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/source-route-library-cortexm3-iar-efr32mg14p-rail/source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/source-route-library-cortexm3-iar-efr32mg14p-rail-stack_protection/source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/source-route-library-cortexm3-iar-efr32mg21-rail/source-route-library.a condition: - toolchain_iar @@ -466,54 +360,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/source-route-library-cortexm3-gcc-efr32mg1p-rail/source-route-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/source-route-library-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/source-route-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/source-route-library-cortexm3-gcc-efr32mg1b-rail/source-route-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/source-route-library-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/source-route-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/source-route-library-cortexm3-gcc-efr32mg1v-rail/source-route-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/source-route-library-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/source-route-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - path: protocol/zigbee/build/source-route-library-cortexm3-gcc-efr32mg12p-rail/source-route-library.a condition: - toolchain_gcc @@ -546,13 +392,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/source-route-library-cortexm3-gcc-efr32mg14p-rail/source-route-library.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/source-route-library-cortexm3-gcc-efr32mg21-rail/source-route-library.a condition: - toolchain_gcc @@ -697,111 +536,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/ncp-source-route-library-cortexm3-iar-efr32mg1p-rail/ncp-source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-source-route-library-cortexm3-iar-efr32mg1p-rail-stack_protection/ncp-source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-source-route-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/ncp-source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-source-route-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/ncp-source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - zigbee_ncp - - path: protocol/zigbee/build/ncp-source-route-library-cortexm3-iar-efr32mg1b-rail/ncp-source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-source-route-library-cortexm3-iar-efr32mg1b-rail-stack_protection/ncp-source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-source-route-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/ncp-source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-source-route-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/ncp-source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - zigbee_ncp - - path: protocol/zigbee/build/ncp-source-route-library-cortexm3-iar-efr32mg1v-rail/ncp-source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-source-route-library-cortexm3-iar-efr32mg1v-rail-stack_protection/ncp-source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-source-route-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/ncp-source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-source-route-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/ncp-source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - zigbee_ncp - path: protocol/zigbee/build/ncp-source-route-library-cortexm3-iar-efr32mg12p-rail/ncp-source-route-library.a condition: - toolchain_iar @@ -832,21 +566,6 @@ library: - zigbee_phy_2_4 - stack_protection_iar - zigbee_ncp - - path: protocol/zigbee/build/ncp-source-route-library-cortexm3-iar-efr32mg14p-rail/ncp-source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-source-route-library-cortexm3-iar-efr32mg14p-rail-stack_protection/ncp-source-route-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - path: protocol/zigbee/build/ncp-source-route-library-cortexm3-iar-efr32mg21-rail/ncp-source-route-library.a condition: - toolchain_iar @@ -982,60 +701,6 @@ library: - zigbee_phy_2_4 - stack_protection_iar - zigbee_ncp - - path: protocol/zigbee/build/ncp-source-route-library-cortexm3-gcc-efr32mg1p-rail/ncp-source-route-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-source-route-library-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/ncp-source-route-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-source-route-library-cortexm3-gcc-efr32mg1b-rail/ncp-source-route-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-source-route-library-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/ncp-source-route-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-source-route-library-cortexm3-gcc-efr32mg1v-rail/ncp-source-route-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/ncp-source-route-library-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/ncp-source-route-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - zigbee_ncp - unless: - - stack_protection_iar - path: protocol/zigbee/build/ncp-source-route-library-cortexm3-gcc-efr32mg12p-rail/ncp-source-route-library.a condition: - toolchain_gcc @@ -1052,14 +717,6 @@ library: - zigbee_ncp unless: - stack_protection_iar - - path: protocol/zigbee/build/ncp-source-route-library-cortexm3-gcc-efr32mg14p-rail/ncp-source-route-library.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - path: protocol/zigbee/build/ncp-source-route-library-cortexm3-gcc-efr32mg21-rail/ncp-source-route-library.a condition: - toolchain_gcc diff --git a/protocol/zigbee/component/zigbee_stack_unix.slcc b/protocol/zigbee/component/zigbee_stack_unix.slcc index b23ddf6400..c0c208216c 100644 --- a/protocol/zigbee/component/zigbee_stack_unix.slcc +++ b/protocol/zigbee/component/zigbee_stack_unix.slcc @@ -243,11 +243,6 @@ toolchain_settings: template_contribution: - name: component_catalog value: zigbee_stack_unix - - name: event_handler - value: - event: stack_process_action - include: "serial_adapter.h" - handler: sli_serial_adapter_tick_callback documentation: docset: zigbee diff --git a/protocol/zigbee/component/zigbee_xncp_library.slcc b/protocol/zigbee/component/zigbee_xncp_library.slcc index b184661193..728885ffe1 100644 --- a/protocol/zigbee/component/zigbee_xncp_library.slcc +++ b/protocol/zigbee/component/zigbee_xncp_library.slcc @@ -19,99 +19,6 @@ requires: - name: zigbee_xncp library: - - path: protocol/zigbee/build/em260-xncp-library-cortexm3-iar-efr32mg1p-rail/em260-xncp-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-xncp-library-cortexm3-iar-efr32mg1p-rail-stack_protection/em260-xncp-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-xncp-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens/em260-xncp-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/em260-xncp-library-cortexm3-iar-efr32mg1p-rail-smart_energy_stack_tokens-stack_protection/em260-xncp-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/em260-xncp-library-cortexm3-iar-efr32mg1b-rail/em260-xncp-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-xncp-library-cortexm3-iar-efr32mg1b-rail-stack_protection/em260-xncp-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-xncp-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens/em260-xncp-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/em260-xncp-library-cortexm3-iar-efr32mg1b-rail-smart_energy_stack_tokens-stack_protection/em260-xncp-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - - path: protocol/zigbee/build/em260-xncp-library-cortexm3-iar-efr32mg1v-rail/em260-xncp-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-xncp-library-cortexm3-iar-efr32mg1v-rail-stack_protection/em260-xncp-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - unless: - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-xncp-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens/em260-xncp-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/em260-xncp-library-cortexm3-iar-efr32mg1v-rail-smart_energy_stack_tokens-stack_protection/em260-xncp-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - - stack_protection_iar - path: protocol/zigbee/build/em260-xncp-library-cortexm3-iar-efr32mg12p-rail/em260-xncp-library.a condition: - toolchain_iar @@ -138,19 +45,6 @@ library: - device_family_efr32mg13p - zigbee_phy_2_4 - stack_protection_iar - - path: protocol/zigbee/build/em260-xncp-library-cortexm3-iar-efr32mg14p-rail/em260-xncp-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/em260-xncp-library-cortexm3-iar-efr32mg14p-rail-stack_protection/em260-xncp-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/em260-xncp-library-cortexm3-iar-efr32mg21-rail/em260-xncp-library.a condition: - toolchain_iar @@ -268,54 +162,6 @@ library: - device_family_mgm24 - zigbee_phy_2_4 - stack_protection_iar - - path: protocol/zigbee/build/em260-xncp-library-cortexm3-gcc-efr32mg1p-rail/em260-xncp-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-xncp-library-cortexm3-gcc-efr32mg1p-rail-smart_energy_stack_tokens/em260-xncp-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/em260-xncp-library-cortexm3-gcc-efr32mg1b-rail/em260-xncp-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-xncp-library-cortexm3-gcc-efr32mg1b-rail-smart_energy_stack_tokens/em260-xncp-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - - path: protocol/zigbee/build/em260-xncp-library-cortexm3-gcc-efr32mg1v-rail/em260-xncp-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - zigbee_smart_energy_token_optimization - - path: protocol/zigbee/build/em260-xncp-library-cortexm3-gcc-efr32mg1v-rail-smart_energy_stack_tokens/em260-xncp-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_smart_energy_token_optimization - unless: - - stack_protection_iar - path: protocol/zigbee/build/em260-xncp-library-cortexm3-gcc-efr32mg12p-rail/em260-xncp-library.a condition: - toolchain_gcc @@ -330,13 +176,6 @@ library: - zigbee_phy_2_4 unless: - stack_protection_iar - - path: protocol/zigbee/build/em260-xncp-library-cortexm3-gcc-efr32mg14p-rail/em260-xncp-library.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/em260-xncp-library-cortexm3-gcc-efr32mg21-rail/em260-xncp-library.a condition: - toolchain_gcc diff --git a/protocol/zigbee/component/zigbee_zll_library.slcc b/protocol/zigbee/component/zigbee_zll_library.slcc index 49bf136f6e..a76658af97 100644 --- a/protocol/zigbee/component/zigbee_zll_library.slcc +++ b/protocol/zigbee/component/zigbee_zll_library.slcc @@ -19,45 +19,6 @@ requires: - name: zigbee_zll library: - - path: protocol/zigbee/build/zll-library-cortexm3-iar-efr32mg1p-rail/zll-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/zll-library-cortexm3-iar-efr32mg1p-rail-stack_protection/zll-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - - path: protocol/zigbee/build/zll-library-cortexm3-iar-efr32mg1b-rail/zll-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/zll-library-cortexm3-iar-efr32mg1b-rail-stack_protection/zll-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - - path: protocol/zigbee/build/zll-library-cortexm3-iar-efr32mg1v-rail/zll-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/zll-library-cortexm3-iar-efr32mg1v-rail-stack_protection/zll-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/zll-library-cortexm3-iar-efr32mg12p-rail/zll-library.a condition: - toolchain_iar @@ -120,19 +81,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/zll-library-cortexm3-iar-efr32mg14p-rail/zll-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/zll-library-cortexm3-iar-efr32mg14p-rail-stack_protection/zll-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - path: protocol/zigbee/build/zll-library-cortexm3-iar-efr32mg21-rail/zll-library.a condition: - toolchain_iar @@ -412,27 +360,6 @@ library: - stack_protection_iar unless: - zigbee_multi_network - - path: protocol/zigbee/build/zll-library-cortexm3-gcc-efr32mg1p-rail/zll-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/zll-library-cortexm3-gcc-efr32mg1b-rail/zll-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - unless: - - stack_protection_iar - - path: protocol/zigbee/build/zll-library-cortexm3-gcc-efr32mg1v-rail/zll-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/zll-library-cortexm3-gcc-efr32mg12p-rail/zll-library.a condition: - toolchain_gcc @@ -465,13 +392,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/zll-library-cortexm3-gcc-efr32mg14p-rail/zll-library.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - unless: - - stack_protection_iar - path: protocol/zigbee/build/zll-library-cortexm3-gcc-efr32mg21-rail/zll-library.a condition: - toolchain_gcc @@ -616,51 +536,6 @@ library: unless: - zigbee_multi_network - stack_protection_iar - - path: protocol/zigbee/build/ncp-zll-library-cortexm3-iar-efr32mg1p-rail/ncp-zll-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-zll-library-cortexm3-iar-efr32mg1p-rail-stack_protection/ncp-zll-library.a - condition: - - toolchain_iar - - device_family_efr32mg1p - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - - path: protocol/zigbee/build/ncp-zll-library-cortexm3-iar-efr32mg1b-rail/ncp-zll-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-zll-library-cortexm3-iar-efr32mg1b-rail-stack_protection/ncp-zll-library.a - condition: - - toolchain_iar - - device_family_efr32mg1b - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - - path: protocol/zigbee/build/ncp-zll-library-cortexm3-iar-efr32mg1v-rail/ncp-zll-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-zll-library-cortexm3-iar-efr32mg1v-rail-stack_protection/ncp-zll-library.a - condition: - - toolchain_iar - - device_family_efr32mg1v - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - path: protocol/zigbee/build/ncp-zll-library-cortexm3-iar-efr32mg12p-rail/ncp-zll-library.a condition: - toolchain_iar @@ -691,21 +566,6 @@ library: - zigbee_phy_2_4 - stack_protection_iar - zigbee_ncp - - path: protocol/zigbee/build/ncp-zll-library-cortexm3-iar-efr32mg14p-rail/ncp-zll-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-zll-library-cortexm3-iar-efr32mg14p-rail-stack_protection/ncp-zll-library.a - condition: - - toolchain_iar - - device_family_efr32mg14p - - zigbee_phy_2_4 - - stack_protection_iar - - zigbee_ncp - path: protocol/zigbee/build/ncp-zll-library-cortexm3-iar-efr32mg21-rail/ncp-zll-library.a condition: - toolchain_iar @@ -841,30 +701,6 @@ library: - zigbee_phy_2_4 - stack_protection_iar - zigbee_ncp - - path: protocol/zigbee/build/ncp-zll-library-cortexm3-gcc-efr32mg1p-rail/ncp-zll-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-zll-library-cortexm3-gcc-efr32mg1b-rail/ncp-zll-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1b - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - - path: protocol/zigbee/build/ncp-zll-library-cortexm3-gcc-efr32mg1v-rail/ncp-zll-library.a - condition: - - toolchain_gcc - - device_family_efr32mg1v - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - path: protocol/zigbee/build/ncp-zll-library-cortexm3-gcc-efr32mg12p-rail/ncp-zll-library.a condition: - toolchain_gcc @@ -881,14 +717,6 @@ library: - zigbee_ncp unless: - stack_protection_iar - - path: protocol/zigbee/build/ncp-zll-library-cortexm3-gcc-efr32mg14p-rail/ncp-zll-library.a - condition: - - toolchain_gcc - - device_family_efr32mg14p - - zigbee_phy_2_4 - - zigbee_ncp - unless: - - stack_protection_iar - path: protocol/zigbee/build/ncp-zll-library-cortexm3-gcc-efr32mg21-rail/ncp-zll-library.a condition: - toolchain_gcc diff --git a/protocol/zigbee/docs/release-highlights.txt b/protocol/zigbee/docs/release-highlights.txt index 586963c0d6..caf82534bb 100644 --- a/protocol/zigbee/docs/release-highlights.txt +++ b/protocol/zigbee/docs/release-highlights.txt @@ -1,10 +1,4 @@ -Zigbee EmberZNet SDK 7.1.0.0 -- 2.4GHz Zigbee Smart Energy support for xG24 -- 802.15.4 Signal Identifier and MAC CCA Mode 2 and 3 support for xG24 -- Zigbee Green Power Gateway Backup -- Updated GCC and IAR Compiler Version -- Alpha Concurrent Multiprotocol Zigbee in NCP mode and Open-Thread in RCP mode -- Alpha Dynamic Multiprotocol Blue-tooth and multi-PAN 802.15.4 in RCP mode - +Zigbee EmberZNet SDK 7.1.1.0 +- Targeted quality improvements and bug fixes. diff --git a/protocol/zigbee/documentation/slEmberZNet_docContent.xml b/protocol/zigbee/documentation/slEmberZNet_docContent.xml index 9575ff5b88..cd4005b46a 100644 --- a/protocol/zigbee/documentation/slEmberZNet_docContent.xml +++ b/protocol/zigbee/documentation/slEmberZNet_docContent.xml @@ -1,488 +1,495 @@ - - + + + Describes the impact of Wi-Fi on Zigbee and Thread, and methods to improve coexistence. First, methods to improve coexistence without direct interaction between Zigbee/Thread and Wi-Fi radios are described. Second, Silicon Labs's Packet Traffic Arbitration (PTA) support to coordinate 2.5 GHz RF traffic for co-located Zigbee/Thread and Wi-Fi radios is described (for the EFR32MG only). - + - Describes the impact of Wi-Fi on Zigbee and Thread, and methods to improve coexistence. First, methods to improve coexistence without direct interaction between Zigbee/Thread and Wi-Fi radios are described. Second, Silicon Labs's Packet Traffic Arbitration (PTA) support to coordinate 2.5 GHz RF traffic for co-located Zigbee/Thread and Wi-Fi radios is described (for the EFR32MG only). - + + Includes detailed information on using the Silicon Labs Gecko Bootloader with EmberZNet. It supplements the general Gecko Bootloader implementation information provided in UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher. - + - Includes detailed information on using the Silicon Labs Gecko Bootloader with EmberZNet. It supplements the general Gecko Bootloader implementation information provided in UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher. - + + Explains how to use Simplicity Commander to check, write, verify, and erase installation codes on Silicon Labs Wireless Gecko (EFR32) devices. - + - Explains how to use Simplicity Commander to check, write, verify, and erase installation codes on Silicon Labs Wireless Gecko (EFR32) devices. - + + Includes guidelines for certifying Zigbee 3.0 devices, instructions on setting up and using the Zigbee test harness and Zigbee test tool, and troubleshooting tips. - + - Includes guidelines for certifying Zigbee 3.0 devices, instructions on setting up and using the Zigbee test harness and Zigbee test tool, and troubleshooting tips. - + + Contains three complete PICS documents for Z3ColorControlLight, Z3Gateway and Z3SmartOutlet reference designs, along with XML files for Z3ColorControlLight clusters. - + - Contains three complete PICS documents for Z3ColorControlLight, Z3Gateway and Z3SmartOutlet reference designs, along with XML files for Z3ColorControlLight clusters. - + + Describes the Secure EZSP protocol and how to configure the hardware and required software to construct a secure EZSP Host-to-NCP interface. - + - Describes the Secure EZSP protocol and how to configure the hardware and required software to construct a secure EZSP Host-to-NCP interface. - + + Explains how NVM3 can be used as non-volatile data storage in various protocol implementations. - + - Explains how NVM3 can be used as non-volatile data storage in various protocol implementations. - + + Details methods for testing Zigbee mesh network performance; results are intended to provide guidance on design practices and principles as well as expected field performance results. - + - Details methods for testing Zigbee mesh network performance; results are intended to provide guidance on design practices and principles as well as expected field performance results. - + + Reviews the Zigbee, Thread, and Bluetooth mesh networks to evaluate their differences in performance and behavior. - + - Reviews the Zigbee, Thread, and Bluetooth mesh networks to evaluate their differences in performance and behavior. - + + Describes tokens and shows how to use them for non-volatile data storage in EmberZNet PRO and Silicon Labs Flex applications. - + - Describes tokens and shows how to use them for non-volatile data storage in EmberZNet PRO and Silicon Labs Flex applications. - + + Describes how to use the manufacturing library and its associated plugins in Simplicity Studio to perform RF tests during the manufacturing phase. - + - Describes how to use the manufacturing library and its associated plugins in Simplicity Studio to perform RF tests during the manufacturing phase. - + + Describes how to lock and unlock the debug access of EFR32 Gecko Series 2 devices. Many aspects of the debug access, including the secure debug unlock are described. The Debug Challenge Interface (DCI) and Secure Engine (SE) Mailbox Interface for locking and unlocking debug access are also included. - + - Describes how to lock and unlock the debug access of EFR32 Gecko Series 2 devices. Many aspects of the debug access, including the secure debug unlock are described. The Debug Challenge Interface (DCI) and Secure Engine (SE) Mailbox Interface for locking and unlocking debug access are also included. - + + Contains detailed information on configuring and using the Secure Boot with hardware Root of Trust and Secure Loader on Series 2 devices, including how to provision the signing key. This is a companion document to UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher. - + - Contains detailed information on configuring and using the Secure Boot with hardware Root of Trust and Secure Loader on Series 2 devices, including how to provision the signing key. This is a companion document to UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher. - + + Details on programming, provisioning, and configuring Series 2 devices in production environments. Covers Secure Engine Subsystem of Series 2 devices, which runs easily upgradeable Secure Engine (SE) or Virtual Secure Engine (VSE) firmware. - + - Details on programming, provisioning, and configuring Series 2 devices in production environments. Covers Secure Engine Subsystem of Series 2 devices, which runs easily upgradeable Secure Engine (SE) or Virtual Secure Engine (VSE) firmware. - + + Introduces some basic security concepts, including network layer security, trust centers, and application support layer security features. It then discusses the types of standard security protocols available in EmberZNet PRO. Coding requirements for implementing security are reviewed in summary. Finally, information on implementing Zigbee Smart Energy security is provided. - + - Introduces some basic security concepts, including network layer security, trust centers, and application support layer security features. It then discusses the types of standard security protocols available in EmberZNet PRO. Coding requirements for implementing security are reviewed in summary. Finally, information on implementing Zigbee Smart Energy security is provided. - + + How to program, provision, and configure the anti-tamper module on EFR32 Series 2 devices with Secure Vault. - + - How to program, provision, and configure the anti-tamper module on EFR32 Series 2 devices with Secure Vault. - + + How to authenticate an EFR32 Series 2 device with Secure Vault, using secure device certificates and signatures. - + - How to authenticate an EFR32 Series 2 device with Secure Vault, using secure device certificates and signatures. - + + How to securely "wrap" keys in EFR32 Series 2 devices with Secure Vault, so they can be stored in non-volatile storage. - + - How to securely "wrap" keys in EFR32 Series 2 devices with Secure Vault, so they can be stored in non-volatile storage. - + + Summarizes the differences between Zigbee EmberZNet 7.x in GSDK 4.x and earlier AppBuilder-based versions. - + - Summarizes the differences between Zigbee EmberZNet 7.x in GSDK 4.x and earlier AppBuilder-based versions. - + + Describes how to provision and configure Series 2 devices through the DCI and SWD. - + - Describes how to provision and configure Series 2 devices through the DCI and SWD. - + + Describes how to integrate crypto functionality into applications using PSA Crypto compared to Mbed TLS. - + - Describes how to integrate crypto functionality into applications using PSA Crypto compared to Mbed TLS. - + + Provides instructions for configuring various aspects of a component-based NCP application using Zigbee EmberZNet SDK 7.0 and higher with the tools included in Simplicity Studio 5. - + - Provides instructions for configuring various aspects of a component-based NCP application using Zigbee EmberZNet SDK 7.0 and higher with the tools included in Simplicity Studio 5. - + + Describes how to configure peripherals running firmware produced with Zigbee 7.0 and higher using Simplicity Studio's Pin Tool and Project Configurator. - + - Describes how to configure peripherals running firmware produced with Zigbee 7.0 and higher using Simplicity Studio's Pin Tool and Project Configurator. - + + Provides details on developing Dynamic Multiprotocol applications using Bluetooth and Zigbee EmberZNet SDK 7.0 and higher. - + - Provides details on developing Dynamic Multiprotocol applications using Bluetooth and Zigbee EmberZNet SDK 7.0 and higher. - + + Describes how to use Project Configurator to configure both receive and transmit Antenna Diversity in Zigbee EmberZNet applications. - + - Describes how to use Project Configurator to configure both receive and transmit Antenna Diversity in Zigbee EmberZNet applications. - + + Describes how to use the Zigbee Cluster Configurator, an advanced configuration tool within Simplicity Studio that allows developers to manage the Zigbee endpoints, clusters and commands implemented by their device. - + - Describes how to use the Zigbee Cluster Configurator, an advanced configuration tool within Simplicity Studio that allows developers to manage the Zigbee endpoints, clusters and commands implemented by their device. - + + Describes how to run any combination of Zigbee EmberZNet, OpenThread, and Bluetooth networking stacks on a Linux host processor, interfacing with a single EFR32 radio co-processor (RCP) with multiprotocol and multi-PAN support, as well as how to run the Zigbee stack on the EFR32 as a network co-processor (NCP) alongside the OpenThread RCP. - + + + + + Describes how to perform a Zigbee over-the-air (OTA) bootloading session between a ZCL OTA Upgrade cluster client device and server device. The instructions are for EFR32MG12 development kits. Users can also refer to this procedure when setting up or testing Zigbee OTA bootload cluster download in their own development environments with their own hardware. + + + - Describes how to run any combination of Zigbee EmberZNet, OpenThread, and Bluetooth networking stacks on a Linux host processor, interfacing with a single EFR32 Radio Coprocessor (RCP) with multiprotocol and multi-PAN support. - + + Summarizes the results of simultaneous Thread and Zigbee throughput performance testing for the concurrent multiprotocol / multi-PAN RCP, running both OpenThread and Zigbee on the host processor. - + - Summarizes the performance test effort and results for some testing scenarios of the CPCd interface using multi-PAN for both OpenThread and Zigbee protocols. - + + Describes how to use the backup and restore feature in a Z3GatewayGPCombo scenario application. - + + + + + Zigbee EmberZNet 7.0 and higher no longer supports compiling host applications in MinGW for Windows. This document offers an alternative solution by using a Docker container to run the NCP Host Application. + + + - Describes how to use the backup and restore feature in a Z3GatewayGPCombo scenario application. - + + Details the different options for integrating RF testing and characterization into standard test flows for the EFR32. - + - Details the different options for integrating RF testing and characterization into standard test flows for the EFR32. - + + Describes procedures for initial tests of a host connected to a Zigbee processor using EZSP-UART. It assumes that you have already read UG101, the UART Gateway Protocol Reference Guide. You should have a basic understanding of the UART Gateway protocol, as well as the signals needed by the UART interface. - + - Describes procedures for initial tests of a host connected to a Zigbee processor using EZSP-UART. It assumes that you have already read UG101, the UART Gateway Protocol Reference Guide. You should have a basic understanding of the UART Gateway protocol, as well as the signals needed by the UART interface. - + + Provides an overview of the use of install codes and certificates in a Smart Energy network. Describes the components of a Smart Energy certificate and the differences between test certificates and production certificates. Explains how to use Silicon Labs utilities to program, verify and erase install codes and certificates. - + - Provides an overview of the use of install codes and certificates in a Smart Energy network. Describes the components of a Smart Energy certificate and the differences between test certificates and production certificates. Explains how to use Silicon Labs utilities to program, verify and erase install codes and certificates. - + + Details the EZSP-SPI Protocol used by a host microcontroller to communicate with an Ember network co-processor (NCP) running the EmberZNet PRO stack. It includes recommended procedures for developing and testing a driver for the EZSP-SPI Protocol on a new host microcontroller. - + - Details the EZSP-SPI Protocol used by a host microcontroller to communicate with an Ember network co-processor (NCP) running the EmberZNet PRO stack. It includes recommended procedures for developing and testing a driver for the EZSP-SPI Protocol on a new host microcontroller. - + + Describes how to set up a device with the security resources required to support Smart Energy (SE) security, which is based on certificate-based key establishment (CBKE) using Elliptic-Curve Cryptography (ECC). You should be familiar the Zigbee Smart Energy Profile specification. - + - Describes how to set up a device with the security resources required to support Smart Energy (SE) security, which is based on certificate-based key establishment (CBKE) using Elliptic-Curve Cryptography (ECC). You should be familiar the Zigbee Smart Energy Profile specification. - + + Provides instructions for creating Zigbee Over-the-air (OTA) bootloader files with Image Builder, which takes an existing file (or multiple files) and wraps them in the file format as declared in the Zigbee specification. - + - Provides instructions for creating Zigbee Over-the-air (OTA) bootloader files with Image Builder, which takes an existing file (or multiple files) and wraps them in the file format as declared in the Zigbee specification. - + + Provides a high-level description of the different options for integrating RF testing and characterization into your standard test flows. It is intended for customers who are moving from the early prototype development stage to the manufacturing production environment and need assistance with manufacturing test. - + - Provides a high-level description of the different options for integrating RF testing and characterization into your standard test flows. It is intended for customers who are moving from the early prototype development stage to the manufacturing production environment and need assistance with manufacturing test. - - - - - + Describes the multi-network stack feature that allows a single-radio chip to be concurrently part of more than one distinct network. Some limitations and restrictions are enforced by the multi-network stack and should be taken into account during the design of a multi-network application. These limitations are mostly related to the role the node assumes on the networks and are discussed here in detail. - - - + - Describes how to perform a Zigbee over-the-air (OTA) bootload cluster download between a client and server device. The instructions are for Smart Energy 1.x devices using Ember EM35x development kits. Users can also refer to this procedure when setting up or testing Zigbee OTA bootload cluster download in their own development environments with their own hardware. - + + Describes how to initialize a piece of custom hardware (a 'device') based on the EFR32MG and EFR32FG families so that it interfaces correctly with a network stack. The same procedures can be used to restore devices whose settings have been corrupted or erased. - + - Describes how to initialize a piece of custom hardware (a 'device') based on the EFR32MG and EFR32FG families so that it interfaces correctly with a network stack. The same procedures can be used to restore devices whose settings have been corrupted or erased. - + + Provides an overview and hyperlinks to all packaged documentation. - + - Provides an overview and hyperlinks to all packaged documentation. - + + Provides basic information on configuring, building, and installing applications for the EFR32MG family of SoCs using the Zigbee EmberZNet Software Development Kit (SDK) v7.0 and higher with Simplicity Studio 5. - + - Provides basic information on configuring, building, and installing applications for the EFR32MG family of SoCs using the Zigbee EmberZNet Software Development Kit (SDK) v7.0 and higher with Simplicity Studio 5. - + + Lists SoC Platform APIs used to interface to the EmberZNet PRO stack, HAL, and status of the application-controlled network. These APIs concern network management, device and stack management, messaging, fragmentation, serial communication, token access, peripheral access, bootload utilities, and others. They are independent of the Application Framework and therefore can be used to develop applications that do not rely on the Zigbee Cluster Library. - + - Lists SoC Platform APIs used to interface to the EmberZNet PRO stack, HAL, and status of the application-controlled network. These APIs concern network management, device and stack management, messaging, fragmentation, serial communication, token access, peripheral access, bootload utilities, and others. They are independent of the Application Framework and therefore can be used to develop applications that do not rely on the Zigbee Cluster Library. - + + Describes Zigbee Application Framework APIs, the CLI interface, and callbacks. - + - Describes Zigbee Application Framework APIs, the CLI interface, and callbacks. - + + A companion to the EmberZNet API references, for developers whose applications require functionality not available through Project Configurator and the application framework, or who prefer working with an API. Includes an introduction to the stack API, a discussion of advanced design issues to consider when developing an application using the API, and provides an example application. - + - A companion to the EmberZNet API references, for developers whose applications require functionality not available through Project Configurator and the application framework, or who prefer working with an API. Includes an introduction to the stack API, a discussion of advanced design issues to consider when developing an application using the API, and provides an example application. - + + The Zigbee Application Framework is a body of embedded C code that can be configured by project configuration tools to implement any Zigbee Cluster Library (ZCL) application. This guide covers the structure and usage of the Zigbee Application Framework in SDK 7.0 and higher. - + - The Zigbee Application Framework is a body of embedded C code that can be configured by project configuration tools to implement any Zigbee Cluster Library (ZCL) application. This guide covers the structure and usage of the Zigbee Application Framework in SDK 7.0 and higher. - + + Gecko Bootloader v2.x, introduced in GSDK 4.0, contains a number of changes compared to Gecko Bootloader v1.x. This document describes the differences between the versions, including how to configure the new Gecko Bootloader in Simplicity Studio 5. - + - Gecko Bootloader v2.x, introduced in GSDK 4.0, contains a number of changes compared to Gecko Bootloader v1.x. This document describes the differences between the versions, including how to configure the new Gecko Bootloader in Simplicity Studio 5. - + + A detailed overview of all the changes, additions, and fixes in the Gecko Platform components. The Gecko Platform consists of: EMLIB, EMDRV, RAIL Library, NVM3, and the mbedTLS Plugin. - + - A detailed overview of all the changes, additions, and fixes in the Gecko Platform components. The Gecko Platform consists of: EMLIB, EMDRV, RAIL Library, NVM3, and the mbedTLS Plugin. - + + Lists compatibility requirements and sources for all software components in the development environment. Discusses the latest changes to the Zigbee 7.x stack (and associated utilities) including added/deleted/deprecated features/API, and lists bugs that have been fixed since the last release and any pending ones. - + - Lists compatibility requirements and sources for all software components in the development environment. Discusses the latest changes to the Zigbee 7.x stack (and associated utilities) including added/deleted/deprecated features/API, and lists bugs that have been fixed since the last release and any pending ones. - + + Describes the EmberZNet Serial Protocol (EZSP), used by a host application processor to interact with the EmberZNet PRO stack running on an NCP over either a SPI or a UART interface. Describes the frame formats for different EZSP-bound stack activities such as network management, messaging, bootloading, and token access. - + - Describes the EmberZNet Serial Protocol (EZSP), used by a host application processor to interact with the EmberZNet PRO stack running on an NCP over either a SPI or a UART interface. Describes the frame formats for different EZSP-bound stack activities such as network management, messaging, bootloading, and token access. - + + Describes the protocol used by EZSP-UART to reliably carry commands and responses between a host processor and a network co-processor. The topics discussed include a brief overview of Ember-designed ASH (Asynchronus Serial Host) protocol, general ASH frame format, different ASH frames, and their operation. - + - Describes the protocol used by EZSP-UART to reliably carry commands and responses between a host processor and a network co-processor. The topics discussed include a brief overview of Ember-designed ASH (Asynchronus Serial Host) protocol, general ASH frame format, different ASH frames, and their operation. - + + Introduces some fundamental concepts of wireless networking. These concepts are referred to in other Fundamentals documents. If you are new to wireless networking, read this document first. - + - Introduces some fundamental concepts of wireless networking. These concepts are referred to in other Fundamentals documents. If you are new to wireless networking, read this document first. - + + Describes the key features and characteristics of a Zigbee solution. It also includes a section on Zigbee 3.0. - + - Describes the key features and characteristics of a Zigbee solution. It also includes a section on Zigbee 3.0. - + + Discusses the major decisions that must be made about which wireless protocol you should use, as well as additional decisions to be made if you are designing a Zigbee solution. - + - Discusses the major decisions that must be made about which wireless protocol you should use, as well as additional decisions to be made if you are designing a Zigbee solution. - + + Introduces the security concepts that must be considered when implementing an Internet of Things (IoT) system. Using the ioXt Alliance's eight security principles as a structure, it clearly delineates the solutions Silicon Labs provides to support endpoint security and what you must do outside of the Silicon Labs framework. - + - Introduces the security concepts that must be considered when implementing an Internet of Things (IoT) system. Using the ioXt Alliance's eight security principles as a structure, it clearly delineates the solutions Silicon Labs provides to support endpoint security and what you must do outside of the Silicon Labs framework. - + + Introduces bootloading for Silicon Labs networking devices. Discusses the Gecko Bootloader and describes the file formats used by each. - + - Introduces bootloading for Silicon Labs networking devices. Discusses the Gecko Bootloader and describes the file formats used by each. - + + Introduces non-volatile data storage using flash and the three different storage implementations offered for Silicon Labs microcontrollers and SoCs: Simulated EEPROM, PS Store, and NVM3. - + - Introduces non-volatile data storage using flash and the three different storage implementations offered for Silicon Labs microcontrollers and SoCs: Simulated EEPROM, PS Store, and NVM3. - + + Compares the ZLL stack and network with the EmberZNet PRO stack and network, with notes about considerations when implementing a ZLL solution. Includes a basic description of ZLL configuration and commissioning, and notes about the interoperability of ZLL and non-ZLL devices. - + - Compares the ZLL stack and network with the EmberZNet PRO stack and network, with notes about considerations when implementing a ZLL solution. Includes a basic description of ZLL configuration and commissioning, and notes about the interoperability of ZLL and non-ZLL devices. - + + Describes the main features and functions of Zigbee Green Power (ZGP) and a basic ZGP network, including its device types and commissioning process, and how EmberZNet supports the ZGP device types. - + - Describes the main features and functions of Zigbee Green Power (ZGP) and a basic ZGP network, including its device types and commissioning process, and how EmberZNet supports the ZGP device types. - + + Describes the four multiprotocol modes, discusses considerations when selecting protocols for multiprotocol implementations, and reviews the Radio Scheduler, a required component of a dynamic multiprotocol solution. - + - Describes the four multiprotocol modes, discusses considerations when selecting protocols for multiprotocol implementations, and reviews the Radio Scheduler, a required component of a dynamic multiprotocol solution. - + + Describes methods to improve the coexistence of 2.4 GHz IEEE 802.11b/g/n Wi-Fi and other 2.4 GHz radios such as Bluetooth, Bluetooth Mesh, Bluetooth Low Energy, and IEEE 802.15.4-based radios such as Zigbee and OpenThread - + - Describes methods to improve the coexistence of 2.4 GHz IEEE 802.11b/g/n Wi-Fi and other 2.4 GHz radios such as Bluetooth, Bluetooth Mesh, Bluetooth Low Energy, and IEEE 802.15.4-based radios such as Zigbee and OpenThread - + + Describes strategies for testing and debugging applications, including: hardware and application considerations, initial development testing, and lab testing. For additional information about later stages of programming and testing see application notes AN700.1: Manufacturing Test Guidelines and AN718: Manufacturing Test Overview. - + - Describes strategies for testing and debugging applications, including: hardware and application considerations, initial development testing, and lab testing. For additional information about later stages of programming and testing see application notes AN700.1: Manufacturing Test Guidelines and AN718: Manufacturing Test Overview. - + + Describes how and when to use Simplicity Commander's Command-Line Interface with EFR32 parts. - + - Describes how and when to use Simplicity Commander's Command-Line Interface with EFR32 parts. - + + Describes how to implement a dynamic multiprotocol solution. - + - Describes how to implement a dynamic multiprotocol solution. - + + Introduces Silicon Labs Green Power components within the EmberZNet PRO stack and explains how to enable your network for Green Power. - + - Introduces Silicon Labs Green Power components within the EmberZNet PRO stack and explains how to enable your network for Green Power. - + + Describes the high-level implementation of the Silicon Labs Gecko Bootloader for EFR32 SoCs and NCPs, and provides information on how to get started using the Gecko Bootloader with Silicon Labs wireless protocol stacks in GSDK 4.0 and higher. - + - Describes the high-level implementation of the Silicon Labs Gecko Bootloader for EFR32 SoCs and NCPs, and provides information on how to get started using the Gecko Bootloader with Silicon Labs wireless protocol stacks in GSDK 4.0 and higher. diff --git a/protocol/zigbee/esf.properties b/protocol/zigbee/esf.properties index 76a3a565b9..3a975ca8be 100644 --- a/protocol/zigbee/esf.properties +++ b/protocol/zigbee/esf.properties @@ -3,18 +3,18 @@ # # This files lists Studio SDK properties pertaining to the ZigBee stack. # -# The version=7.1.0.0 +# The version=7.1.1.0 # release branch, or it should be set to 0.0.0 otherwise. This is the # version that Studio displays for the loaded stack. # id=com.silabs.sdk.stack.znet -version=7.1.0.0 +version=7.1.1.0 label=EmberZNet SDK description=Silicon Labs EmberZNet SDK -prop.subLabel=EmberZNet\\ 7.1.0.0 +prop.subLabel=EmberZNet\\ 7.1.1.0 -prop.partCompatibility=.*host.* .*efr32mg(1|12|13|14)p.* .*efr32mg2[1247].* .*mgm(1|12|13|21|22|24).* .*rm21.* +prop.partCompatibility=.*host.* .*efr32mg(12|13)p.* .*efr32mg2[1247].* .*mgm(12|13|21|22|24).* .*rm21.* prop.file.appDirectory=app/gpd app/ncp prop.file.appConfiguratorDirectory=tool/appbuilder diff --git a/protocol/zigbee/stack/config/config.h b/protocol/zigbee/stack/config/config.h index ae5314cbf5..1a45aaa7ea 100644 --- a/protocol/zigbee/stack/config/config.h +++ b/protocol/zigbee/stack/config/config.h @@ -33,7 +33,7 @@ // The 4 digit version: A.B.C.D #define EMBER_MAJOR_VERSION 7 #define EMBER_MINOR_VERSION 1 -#define EMBER_PATCH_VERSION 0 +#define EMBER_PATCH_VERSION 1 #define EMBER_SPECIAL_VERSION 0 // 2 bytes diff --git a/protocol/zigbee/tool/image-builder/image-builder-linux b/protocol/zigbee/tool/image-builder/image-builder-linux index 369ad3f35d..e797ed6099 100644 Binary files a/protocol/zigbee/tool/image-builder/image-builder-linux and b/protocol/zigbee/tool/image-builder/image-builder-linux differ diff --git a/protocol/zigbee/tool/image-builder/image-builder-windows.exe b/protocol/zigbee/tool/image-builder/image-builder-windows.exe index ff60be80f4..4e0cf65df8 100644 --- a/protocol/zigbee/tool/image-builder/image-builder-windows.exe +++ b/protocol/zigbee/tool/image-builder/image-builder-windows.exe @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:760964f672a99e35bef4f2d01c216632ed4525079b39d6946678123888752039 +oid sha256:36e93341bfec2df99b3e84ae8df58916442f7c08ce8dad78e21797eb0b74198a size 3024294 diff --git a/protocol/zigbee/zigbee_alpha_templates.xml b/protocol/zigbee/zigbee_alpha_templates.xml index fe230f1410..95acdbb044 100644 --- a/protocol/zigbee/zigbee_alpha_templates.xml +++ b/protocol/zigbee/zigbee_alpha_templates.xml @@ -8,7 +8,7 @@ - + @@ -21,9 +21,9 @@ - - - + + + @@ -36,9 +36,9 @@ - - - + + + diff --git a/protocol/zigbee/zigbee_production_demos.xml b/protocol/zigbee/zigbee_production_demos.xml index 502840160d..db579386ff 100644 --- a/protocol/zigbee/zigbee_production_demos.xml +++ b/protocol/zigbee/zigbee_production_demos.xml @@ -1,616 +1,593 @@ - - - - - - - This network coprocessor (NCP) application supports communication with a host application over a SPI interface. This NCP application can be built as configured, or optionally can be augmented with customized extensions for initialization, main loop processing, event definition/handling, and messaging with the host. + + + + + + + - - - - - - - This network coprocessor (NCP) application supports communication with a host application over a SPI interface. This NCP application can be built as configured, or optionally can be augmented with customized extensions for initialization, main loop processing, event definition/handling, and messaging with the host. + + + + + + + - - - - - - - This network coprocessor (NCP) application supports communication with a host application over a SPI interface. This NCP application can be built as configured, or optionally can be augmented with customized extensions for initialization, main loop processing, event definition/handling, and messaging with the host. + + + + + + + - - - - - - - This network coprocessor (NCP) application supports communication with a host application over a SPI interface. This NCP application can be built as configured, or optionally can be augmented with customized extensions for initialization, main loop processing, event definition/handling, and messaging with the host. + + + + + + + - - - - - - - - This network coprocessor (NCP) application supports communication with a host application over a SPI interface. This NCP application can be built as configured, or optionally can be augmented with customized extensions for initialization, main loop processing, event definition/handling, and messaging with the host. - - - - - - - - - - This network coprocessor (NCP) application supports communication with a host application over a SPI interface. This NCP application can be built as configured, or optionally can be augmented with customized extensions for initialization, main loop processing, event definition/handling, and messaging with the host. + + + + + + + - - - - - - - This network coprocessor (NCP) application supports communication with a host application over a SPI interface. This NCP application can be built as configured, or optionally can be augmented with customized extensions for initialization, main loop processing, event definition/handling, and messaging with the host. + + + + + + + - - - - - - - This network coprocessor (NCP) application supports communication with a host application over a SPI interface. This NCP application can be built as configured, or optionally can be augmented with customized extensions for initialization, main loop processing, event definition/handling, and messaging with the host. + + + + + + + - - - - - - - This network coprocessor (NCP) application supports communication with a host application over a UART interface with hardware flow control. This NCP application can be built as configured, or optionally can be augmented with customized extensions for initialization, main loop processing, event definition/handling, and messaging with the host. Steps to create a ECC enabled application for Smart Energy Profile application: 1) Download the side package 'EmberZnet-Smart-Energy.zip' 2) Extract the side package over installed SDK. 3) Enable 'CBKE 163k1' and/or 'CBKE 283k1' components depending on the use case. 4) Build the application. + + + + + + + - - - - - - - This network coprocessor (NCP) application supports communication with a host application over a UART interface with hardware flow control. This NCP application can be built as configured, or optionally can be augmented with customized extensions for initialization, main loop processing, event definition/handling, and messaging with the host. Steps to create a ECC enabled application for Smart Energy Profile application: 1) Download the side package 'EmberZnet-Smart-Energy.zip' 2) Extract the side package over installed SDK. 3) Enable 'CBKE 163k1' and/or 'CBKE 283k1' components depending on the use case. 4) Build the application. + + + + + + + - - - - - - - This network coprocessor (NCP) application supports communication with a host application over a UART interface with hardware flow control. This NCP application can be built as configured, or optionally can be augmented with customized extensions for initialization, main loop processing, event definition/handling, and messaging with the host. Steps to create a ECC enabled application for Smart Energy Profile application: 1) Download the side package 'EmberZnet-Smart-Energy.zip' 2) Extract the side package over installed SDK. 3) Enable 'CBKE 163k1' and/or 'CBKE 283k1' components depending on the use case. 4) Build the application. + + + + + + + - - - - - - - This network coprocessor (NCP) application supports communication with a host application over a UART interface with hardware flow control. This NCP application can be built as configured, or optionally can be augmented with customized extensions for initialization, main loop processing, event definition/handling, and messaging with the host. Steps to create a ECC enabled application for Smart Energy Profile application: 1) Download the side package 'EmberZnet-Smart-Energy.zip' 2) Extract the side package over installed SDK. 3) Enable 'CBKE 163k1' and/or 'CBKE 283k1' components depending on the use case. 4) Build the application. + + + + + + + - - - - - - - - This network coprocessor (NCP) application supports communication with a host application over a UART interface with hardware flow control. This NCP application can be built as configured, or optionally can be augmented with customized extensions for initialization, main loop processing, event definition/handling, and messaging with the host. -Steps to create a ECC enabled application for Smart Energy Profile application: 1) Download the side package 'EmberZnet-Smart-Energy.zip' 2) Extract the side package over installed SDK. 3) Enable 'CBKE 163k1' and/or 'CBKE 283k1' components depending on the use case. 4) Build the application. - - - - - - - - - - This network coprocessor (NCP) application supports communication with a host application over a UART interface with hardware flow control. This NCP application can be built as configured, or optionally can be augmented with customized extensions for initialization, main loop processing, event definition/handling, and messaging with the host. Steps to create a ECC enabled application for Smart Energy Profile application: 1) Download the side package 'EmberZnet-Smart-Energy.zip' 2) Extract the side package over installed SDK. 3) Enable 'CBKE 163k1' and/or 'CBKE 283k1' components depending on the use case. 4) Build the application. + + + + + + + - - - - - - - This network coprocessor (NCP) application supports communication with a host application over a UART interface with hardware flow control. This NCP application can be built as configured, or optionally can be augmented with customized extensions for initialization, main loop processing, event definition/handling, and messaging with the host. Steps to create a ECC enabled application for Smart Energy Profile application: 1) Download the side package 'EmberZnet-Smart-Energy.zip' 2) Extract the side package over installed SDK. 3) Enable 'CBKE 163k1' and/or 'CBKE 283k1' components depending on the use case. 4) Build the application. + + + + + + + - - - - - - - This network coprocessor (NCP) application supports communication with a host application over a UART interface with hardware flow control. This NCP application can be built as configured, or optionally can be augmented with customized extensions for initialization, main loop processing, event definition/handling, and messaging with the host. Steps to create a ECC enabled application for Smart Energy Profile application: 1) Download the side package 'EmberZnet-Smart-Energy.zip' 2) Extract the side package over installed SDK. 3) Enable 'CBKE 163k1' and/or 'CBKE 283k1' components depending on the use case. 4) Build the application. + + + + + + + - - - - - - - This is a sample application demonstrating a light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LED or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LED or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LED or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LED or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LED or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LED or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LED or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LED or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LED or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LED or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LED or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LED or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LED or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LED or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a sleepy light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LEDs or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a sleepy light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LEDs or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a sleepy light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LEDs or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a sleepy light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LEDs or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a sleepy light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LEDs or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a sleepy light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LEDs or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a sleepy light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LEDs or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a sleepy light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LEDs or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a sleepy light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LEDs or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a sleepy light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LEDs or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a sleepy light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LEDs or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a sleepy light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LEDs or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a sleepy light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LEDs or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a sleepy light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. This application does not use LCD, LEDs or buttons. + + + + + + + - - - - - - - This is a sample application demonstrating a sleepy light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. + + + + + + + - - - - - - - This is a sample application demonstrating a sleepy light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. + + + + + + + - - - - - - - This is a sample application demonstrating a light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. + + + + + + + - - - - - - - This is a sample application demonstrating a light application using dynamic multiprotocol (Zigbee + Bluetooth LE) and NVM3 for persistent storage. + + + + + + + - - - - - - - This is a Zigbee 3.0 light application using NVM3 as the persistent storage. + + + + + + + - - - - - - - This is a Zigbee 3.0 light application using NVM3 as the persistent storage. + + + + + + + - - - - - - - This is a Zigbee 3.0 light application using NVM3 as the persistent storage. + + + + + + + - - - - - - - Zigbee 3.0 Switch with Voice + + + + + + + - - - - - - - This is a Zigbee 3.0 switch application using NVM3 as the persistent storage. + + + + + + + - - - - - - - This is a Zigbee 3.0 switch application using NVM3 as the persistent storage. + + + + + + + - - - - - - - This is a Zigbee 3.0 switch application using NVM3 as the persistent storage. + + + + + + + diff --git a/protocol/zigbee/zigbee_production_templates.xml b/protocol/zigbee/zigbee_production_templates.xml index f269497d42..2fa3f062d7 100644 --- a/protocol/zigbee/zigbee_production_templates.xml +++ b/protocol/zigbee/zigbee_production_templates.xml @@ -8,7 +8,7 @@ - + @@ -21,9 +21,9 @@ - - - + + + @@ -37,8 +37,8 @@ - - + + @@ -51,9 +51,9 @@ - - - + + + @@ -67,8 +67,8 @@ - - + + @@ -83,7 +83,7 @@ - + @@ -98,7 +98,7 @@ - + @@ -113,7 +113,7 @@ - + @@ -126,9 +126,9 @@ - - - + + + @@ -141,9 +141,9 @@ - - - + + + @@ -156,9 +156,9 @@ - - - + + + @@ -173,7 +173,7 @@ - + @@ -186,9 +186,9 @@ - - - + + + @@ -203,7 +203,7 @@ - + @@ -216,9 +216,9 @@ - - - + + + @@ -231,9 +231,9 @@ - - - + + + @@ -246,9 +246,9 @@ - - - + + + @@ -261,9 +261,9 @@ - - - + + + @@ -276,9 +276,9 @@ - - - + + + @@ -291,9 +291,9 @@ - - - + + + @@ -306,9 +306,9 @@ - - - + + + @@ -321,9 +321,9 @@ - - - + + + @@ -336,9 +336,9 @@ - - - + + + @@ -353,7 +353,7 @@ - + diff --git a/util/plugin/plugin-common/demo-ui/demo-ui.h b/util/plugin/plugin-common/demo-ui/demo-ui.h index d355e94d5d..60f3cd3640 100644 --- a/util/plugin/plugin-common/demo-ui/demo-ui.h +++ b/util/plugin/plugin-common/demo-ui/demo-ui.h @@ -17,6 +17,10 @@ #ifndef DEMO_UI_H #define DEMO_UI_H +#ifdef __cplusplus +extern "C" { +#endif + /**************************************************************************//** * DEMO UI uses the underlying DMD interface and the GLIB and exposes several * wrapper functions to application. These functions are used to display @@ -171,4 +175,7 @@ void demoUIClearMainScreen(uint8_t* name, bool showPROT1, bool showPROT2); *****************************************************************************/ void demoUIDisplayChan(uint8_t channel); +#ifdef __cplusplus +} +#endif #endif //DEMO_UI_H diff --git a/util/silicon_labs/aox/lib/gcc/release/libaox_static_darwin_x86_64.a b/util/silicon_labs/aox/lib/gcc/release/libaox_static_darwin_x86_64.a index ef2c4026c5..6eedf63866 100644 --- a/util/silicon_labs/aox/lib/gcc/release/libaox_static_darwin_x86_64.a +++ b/util/silicon_labs/aox/lib/gcc/release/libaox_static_darwin_x86_64.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2a4f9d3c6e5fff72abeda24fa0f2256eeb9ad9dc6c750052121ac8a96a7722a0 +oid sha256:7feedd830925fa368a095bc9264d834e505e672fe7c4a8013e7715fe75f370c4 size 4775896 diff --git a/util/silicon_labs/aox/lib/gcc/release/libaox_static_linux_aarch64.a b/util/silicon_labs/aox/lib/gcc/release/libaox_static_linux_aarch64.a index 6d833422ee..5984b41fe6 100644 --- a/util/silicon_labs/aox/lib/gcc/release/libaox_static_linux_aarch64.a +++ b/util/silicon_labs/aox/lib/gcc/release/libaox_static_linux_aarch64.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8ccc838550facf5839569ed0cf257da9785c67cf6442b25e36446f831bcbffee +oid sha256:a11e53554ac4f1028094ca4122896762a1a95d8883707d7a3781db99a51a1222 size 4935702 diff --git a/util/silicon_labs/aox/lib/gcc/release/libaox_static_linux_armv7l.a b/util/silicon_labs/aox/lib/gcc/release/libaox_static_linux_armv7l.a index ccc1d199b0..2b8f2b4880 100644 --- a/util/silicon_labs/aox/lib/gcc/release/libaox_static_linux_armv7l.a +++ b/util/silicon_labs/aox/lib/gcc/release/libaox_static_linux_armv7l.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0c56fae10f9136c1a4b591124722eff03b79047d8e2b7b8580e0f3dd9c919e47 +oid sha256:c06da414452876db3976ac553b45edf795a1ef2be760b6f38e433e99f8b46d6b size 4878520 diff --git a/util/silicon_labs/aox/lib/gcc/release/libaox_static_linux_x86_64.a b/util/silicon_labs/aox/lib/gcc/release/libaox_static_linux_x86_64.a index ecf69af59a..264c6d18b1 100644 --- a/util/silicon_labs/aox/lib/gcc/release/libaox_static_linux_x86_64.a +++ b/util/silicon_labs/aox/lib/gcc/release/libaox_static_linux_x86_64.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f14a660de50fbba9575cee31ad88c83867f2d8b0e0502433f8e0f54e65656d52 +oid sha256:26da234884bba13ac81c1f7e6dd15cda712faaa146dab18cf19daaa11648d1dd size 4850772 diff --git a/util/silicon_labs/aox/lib/gcc/release/libaox_static_windows_x86_64.a b/util/silicon_labs/aox/lib/gcc/release/libaox_static_windows_x86_64.a index 7cdfaaa168..ff546d8fff 100644 --- a/util/silicon_labs/aox/lib/gcc/release/libaox_static_windows_x86_64.a +++ b/util/silicon_labs/aox/lib/gcc/release/libaox_static_windows_x86_64.a @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e490e9e8df4f9f2c38b49c174bae82913a9372d78a9ebdc7be8e739ed07e577a +oid sha256:c908060fd64cbb573c9471f625e7552fcf710393626bdbe848890d79951185db size 4825912 diff --git a/util/third_party/crypto/component/tz_common.slcc b/util/third_party/crypto/component/tz_common.slcc index d36c16db4e..0c1cd50e94 100644 --- a/util/third_party/crypto/component/tz_common.slcc +++ b/util/third_party/crypto/component/tz_common.slcc @@ -11,9 +11,11 @@ component_root_path: util/third_party/crypto provides: - name: tz_common +requires: + - name: tz_util + include: - path: sl_component/sl_trustzone/inc/common file_list: - path: sli_tz_iovec.h - - path: sli_tz_util.h - path: sli_tz_s_interface.h diff --git a/util/third_party/crypto/component/tz_secure_nvm3_s.slcc b/util/third_party/crypto/component/tz_secure_nvm3_s.slcc index 4d23e27335..48f97f9133 100644 --- a/util/third_party/crypto/component/tz_secure_nvm3_s.slcc +++ b/util/third_party/crypto/component/tz_secure_nvm3_s.slcc @@ -13,11 +13,5 @@ provides: requires: - name: trustzone_secure - - name: nvm3_lib - name: nvm3_default - - name: nvm_system -define: - # Not used, however, needed in order to avoid IAR linker error. - - name: NVM3_BASE - value: 0 \ No newline at end of file diff --git a/util/third_party/crypto/component/tz_service_syscfg.slcc b/util/third_party/crypto/component/tz_service_syscfg.slcc index 28a861ce1f..549b36b9ba 100644 --- a/util/third_party/crypto/component/tz_service_syscfg.slcc +++ b/util/third_party/crypto/component/tz_service_syscfg.slcc @@ -20,5 +20,6 @@ source: condition: [trustzone_secure] requires: + - name: tz_util - name: emlib_syscfg condition: [trustzone_secure] \ No newline at end of file diff --git a/util/third_party/crypto/component/tz_util.slcc b/util/third_party/crypto/component/tz_util.slcc new file mode 100644 index 0000000000..61c4d19444 --- /dev/null +++ b/util/third_party/crypto/component/tz_util.slcc @@ -0,0 +1,17 @@ +id: tz_util +package: platform +category: Platform|Security|TrustZone +description: >- + This component provides includes utility files for TZ Secure and NonSecure applications. +ui_hints: + visibility: never +quality: beta +component_root_path: util/third_party/crypto + +provides: + - name: tz_util + +include: + - path: sl_component/sl_trustzone/inc/common + file_list: + - path: sli_tz_util.h diff --git a/util/third_party/crypto/sl_component/se_manager/inc/sl_se_manager_attestation.h b/util/third_party/crypto/sl_component/se_manager/inc/sl_se_manager_attestation.h index e811f74480..b62cc39f53 100644 --- a/util/third_party/crypto/sl_component/se_manager/inc/sl_se_manager_attestation.h +++ b/util/third_party/crypto/sl_component/se_manager/inc/sl_se_manager_attestation.h @@ -32,7 +32,9 @@ #include "em_device.h" -#if defined(SEMAILBOX_PRESENT) || defined(DOXYGEN) +#if (defined(SEMAILBOX_PRESENT) \ + && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) \ + || defined(DOXYGEN) /// @addtogroup sl_se_manager /// @{ @@ -61,8 +63,6 @@ extern "C" { #endif -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) || defined(DOXYGEN) - // ----------------------------------------------------------------------------- // Defines @@ -198,8 +198,6 @@ sl_status_t sl_se_attestation_get_config_token_size(sl_se_command_context_t *cmd size_t challenge_size, size_t *token_size); -#endif // (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - #ifdef __cplusplus } #endif @@ -207,6 +205,6 @@ sl_status_t sl_se_attestation_get_config_token_size(sl_se_command_context_t *cmd /// @} (end addtogroup sl_se_manager_attestation) /// @} (end addtogroup sl_se_manager) -#endif // defined(SEMAILBOX_PRESENT) +#endif // SEMAILBOX_PRESENT && VAULT #endif // SL_SE_MANAGER_ATTESTATION_H diff --git a/util/third_party/crypto/sl_component/se_manager/inc/sl_se_manager_cipher.h b/util/third_party/crypto/sl_component/se_manager/inc/sl_se_manager_cipher.h index d5a7bac99d..ff46843282 100644 --- a/util/third_party/crypto/sl_component/se_manager/inc/sl_se_manager_cipher.h +++ b/util/third_party/crypto/sl_component/se_manager/inc/sl_se_manager_cipher.h @@ -395,7 +395,6 @@ sl_status_t sl_se_ccm_auth_decrypt(sl_se_command_context_t *cmd_ctx, * @return * Status code, @ref sl_status.h. ******************************************************************************/ -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) sl_status_t sl_se_ccm_multipart_starts(sl_se_ccm_multipart_context_t *ccm_ctx, sl_se_command_context_t *cmd_ctx, const sl_se_key_descriptor_t *key, @@ -406,7 +405,6 @@ sl_status_t sl_se_ccm_multipart_starts(sl_se_ccm_multipart_context_t *ccm_ctx, const uint8_t *add, size_t add_len, size_t tag_len); -#endif /***************************************************************************//** * @brief @@ -440,7 +438,7 @@ sl_status_t sl_se_ccm_multipart_starts(sl_se_ccm_multipart_context_t *ccm_ctx, * @return * Status code, @ref sl_status.h. ******************************************************************************/ -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) + sl_status_t sl_se_ccm_multipart_update(sl_se_ccm_multipart_context_t *ccm_ctx, sl_se_command_context_t *cmd_ctx, const sl_se_key_descriptor_t *key, @@ -448,7 +446,6 @@ sl_status_t sl_se_ccm_multipart_update(sl_se_ccm_multipart_context_t *ccm_ctx, const uint8_t *input, uint8_t *output, size_t *output_length); -#endif /***************************************************************************//** * @brief @@ -486,7 +483,6 @@ sl_status_t sl_se_ccm_multipart_update(sl_se_ccm_multipart_context_t *ccm_ctx, * Returns SL_SE_INVALID_SIGNATURE if authentication step fails. * Status code, @ref sl_status.h. ******************************************************************************/ -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) sl_status_t sl_se_ccm_multipart_finish(sl_se_ccm_multipart_context_t *ccm_ctx, sl_se_command_context_t *cmd_ctx, const sl_se_key_descriptor_t *key, @@ -495,7 +491,6 @@ sl_status_t sl_se_ccm_multipart_finish(sl_se_ccm_multipart_context_t *ccm_ctx, uint8_t *output, uint8_t output_size, uint8_t *output_length); -#endif /***************************************************************************//** * @brief diff --git a/util/third_party/crypto/sl_component/se_manager/inc/sl_se_manager_types.h b/util/third_party/crypto/sl_component/se_manager/inc/sl_se_manager_types.h index 0eed247097..fcb0c48d4e 100644 --- a/util/third_party/crypto/sl_component/se_manager/inc/sl_se_manager_types.h +++ b/util/third_party/crypto/sl_component/se_manager/inc/sl_se_manager_types.h @@ -346,18 +346,24 @@ typedef struct { /// CCM streaming context. typedef struct { - uint32_t message_length; ///< Current length of the encrypted/decrypted data + uint32_t processed_message_length;///< Current length of the encrypted/decrypted data uint32_t total_message_length; ///< Total length of data to be encrypted/decrypted uint8_t iv[13]; ///< Nonce (MAX size is 13 bytes) - uint8_t se_ctx[32]; ///< SE encryption state uint32_t tag_len; ///< Tag length sl_se_cipher_operation_t mode;///< CCM mode (decrypt or encrypt) + #if (_SILICON_LABS_32B_SERIES_2_CONFIG == 1) + uint8_t nonce_counter[16]; ///< Counter to keep CTR state + uint8_t iv_len; ///< Nonce length + uint8_t cbc_mac_state[16]; ///< State of authenication/MAC + uint8_t final_data[16]; ///< Input data saved for finish operation + #else + uint8_t se_ctx[32]; ///< SE encryption state union { uint8_t tagbuf[16]; ///< Tag uint8_t final_data[16]; ///< Input data saved for finish operation } mode_specific_buffer; + #endif uint8_t final_data_length; ///< Length of data saved - bool last_update_operation; ///< Last operation / update } sl_se_ccm_multipart_context_t; /// GCM streaming context. Deprecated. diff --git a/util/third_party/crypto/sl_component/se_manager/src/sl_se_manager_cipher.c b/util/third_party/crypto/sl_component/se_manager/src/sl_se_manager_cipher.c index 49f9007039..c9b26faa1a 100644 --- a/util/third_party/crypto/sl_component/se_manager/src/sl_se_manager_cipher.c +++ b/util/third_party/crypto/sl_component/se_manager/src/sl_se_manager_cipher.c @@ -37,6 +37,8 @@ #include "sl_assert.h" #include +#define BUFSIZE 16 + /// @addtogroup sl_se_manager /// @{ @@ -556,6 +558,360 @@ sl_status_t sl_se_ccm_auth_decrypt(sl_se_command_context_t *cmd_ctx, } } +#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 1) +sl_status_t sl_se_ccm_multipart_starts(sl_se_ccm_multipart_context_t *ccm_ctx, + sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_cipher_operation_t mode, + uint32_t total_message_length, + const uint8_t *iv, + size_t iv_len, + const uint8_t *aad, + size_t aad_len, + size_t tag_len) +{ + sl_status_t status = SL_STATUS_OK; + uint8_t q; + uint8_t b[BUFSIZE] = { 0 }; + uint8_t tag_out[BUFSIZE] = { 0 }; + uint8_t cbc_mac_state[BUFSIZE] = { 0 }; + uint8_t nonce_counter[BUFSIZE] = { 0 }; + uint32_t len_left; + + //Check input parameters + if (ccm_ctx == NULL || cmd_ctx == NULL || key == NULL || iv == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + if (aad_len > 0 && aad == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (tag_len == 2 || tag_len > 16 || tag_len % 2 != 0) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (iv_len < 7 || iv_len > 13) { + return SL_STATUS_INVALID_PARAMETER; + } + + // q is the the octet length of Q which again is a bit string representation of + // the octet length of the payload. + q = 16 - 1 - (uint8_t) iv_len; + + // The parameter q determines the maximum length of the payload: by definition, p<2^(8*q), + // where p is payload. + if ((q < sizeof(total_message_length)) && (total_message_length >= (1UL << (q * 8)))) { + return SL_STATUS_INVALID_PARAMETER; + } + memset(ccm_ctx, 0, sizeof(sl_se_ccm_multipart_context_t)); + + // Format first input block B_O according to the formatting function: + + // 0 .. 0 flags + // 1 .. iv_len nonce (aka iv) + // iv_len+1 .. 15 length + // + // With flags as (bits): + // 7 0 + // 6 add present? + // 5 .. 3 (t - 2) / 2 + // 2 .. 0 q - 1 + + b[0] = 0; + b[0] |= (aad_len > 0) << 6; + b[0] |= ((tag_len - 2) / 2) << 3; + b[0] |= q - 1; + + memcpy(b + 1, iv, iv_len); + + len_left = total_message_length; + for (uint32_t i = 0; i < q; i++, len_left >>= 8) { + b[15 - i] = (unsigned char)(len_left & 0xFF); + } + + ccm_ctx->mode = mode; + ccm_ctx->processed_message_length = 0; + ccm_ctx->total_message_length = total_message_length; + ccm_ctx->tag_len = tag_len; + ccm_ctx->mode = mode; + ccm_ctx->iv_len = iv_len; + memcpy(ccm_ctx->iv, iv, iv_len); + + status = sl_se_aes_crypt_cbc(cmd_ctx, + key, + SL_SE_ENCRYPT, + BUFSIZE, + cbc_mac_state, + b, + tag_out); + + if (status != SL_STATUS_OK) { + return status; + } + + // If there is additional data, update using CBC. Must be done + // blockwise to achieve the same behaviour as CBC-MAC. + if (aad_len > 0) { + uint8_t use_len; + len_left = aad_len; + memset(b, 0, sizeof(b)); + // First block. + b[0] = (unsigned char)((aad_len >> 8) & 0xFF); + b[1] = (unsigned char)((aad_len) & 0xFF); + use_len = len_left < BUFSIZE - 2 ? len_left : 16 - 2; + memcpy(b + 2, aad, use_len); + len_left -= use_len; + aad += use_len; + + status = sl_se_aes_crypt_cbc(cmd_ctx, + key, + SL_SE_ENCRYPT, + BUFSIZE, + cbc_mac_state, + b, + tag_out); + if (status != SL_STATUS_OK) { + return status; + } + + while (len_left) { + use_len = len_left > 16 ? 16 : len_left; + + memset(b, 0, sizeof(b)); + memcpy(b, aad, use_len); + status = sl_se_aes_crypt_cbc(cmd_ctx, + key, + SL_SE_ENCRYPT, + BUFSIZE, + cbc_mac_state, + b, + tag_out); + + if (status != SL_STATUS_OK) { + return status; + } + len_left -= use_len; + aad += use_len; + } + } + + memcpy(ccm_ctx->cbc_mac_state, cbc_mac_state, sizeof(cbc_mac_state)); + + // Prepare nonce counter for encryption/decryption operation. + nonce_counter[0] = q - 1; + memcpy(nonce_counter + 1, iv, iv_len); + memset(nonce_counter + 1 + iv_len, 0, q); + nonce_counter[15] = 1; + + memcpy(ccm_ctx->nonce_counter, nonce_counter, sizeof(ccm_ctx->nonce_counter)); + + return SL_STATUS_OK; +} + +sl_status_t sl_se_ccm_multipart_update(sl_se_ccm_multipart_context_t *ccm_ctx, + sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + size_t length, + const uint8_t *input, + uint8_t *output, + size_t *output_length) +{ + sl_status_t status = SL_STATUS_OK; + *output_length = 0; + + uint8_t out_buf[BUFSIZE] = { 0 }; + uint8_t empty[BUFSIZE] = { 0 }; + uint8_t b[BUFSIZE] = { 0 }; + + size_t len_left; + + // Check input parameters. + if (ccm_ctx == NULL || cmd_ctx == NULL || key == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (length == 0) { + return SL_STATUS_OK; + } + + // Check variable overflow + if (ccm_ctx->processed_message_length > 0xFFFFFFFF - length) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (ccm_ctx->processed_message_length + length > ccm_ctx->total_message_length) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (length > 0 && (input == NULL || output == NULL)) { + return SL_STATUS_INVALID_PARAMETER; + } + + if ((uint32_t)output + length > RAM_MEM_END) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Support partial overlap. + if ((output > input) && (output < (input + length))) { + memmove(output, input, length); + input = output; + } + + if (length + ccm_ctx->final_data_length < BUFSIZE && length < BUFSIZE && ccm_ctx->processed_message_length + length != ccm_ctx->total_message_length ) { + if (ccm_ctx->final_data_length > BUFSIZE) { + // Context is not valid. + return SL_STATUS_INVALID_PARAMETER; + } + memcpy(ccm_ctx->final_data + ccm_ctx->final_data_length, input, length); + ccm_ctx->final_data_length += length; + *output_length = 0; + return SL_STATUS_OK; + } + + len_left = length + ccm_ctx->final_data_length; + + // Authenticate and {en,de}crypt the message. + + // The only difference between encryption and decryption is + // the respective order of authentication and {en,de}cryption. + while (len_left > 0 ) { + uint8_t use_len = len_left > BUFSIZE ? BUFSIZE : len_left; + + memset(b, 0, sizeof(b)); + + // Process data stored in context first. + if (ccm_ctx->final_data_length > 0) { + if (ccm_ctx->final_data_length > BUFSIZE) { + // Context is not valid. + return SL_STATUS_INVALID_PARAMETER; + } + memcpy(b, ccm_ctx->final_data, ccm_ctx->final_data_length); + memcpy(b + ccm_ctx->final_data_length, input, BUFSIZE - ccm_ctx->final_data_length); + input += BUFSIZE - ccm_ctx->final_data_length; + ccm_ctx->final_data_length = 0; + } else { + memcpy(b, input, use_len); + input += use_len; + } + if (ccm_ctx->mode == SL_SE_ENCRYPT) { + // Authenticate input. + status = sl_se_aes_crypt_cbc(cmd_ctx, + key, + SL_SE_ENCRYPT, + BUFSIZE, + ccm_ctx->cbc_mac_state, + b, + out_buf); + + if (status != SL_STATUS_OK) { + return status; + } + } + // Encrypt/decrypt data with CTR. + status = sl_se_aes_crypt_ctr(cmd_ctx, + key, + use_len, + NULL, + ccm_ctx->nonce_counter, + empty, + b, + output); + + if (ccm_ctx->mode == SL_SE_DECRYPT) { + // Authenticate output. + memset(b, 0, sizeof(b)); + memcpy(b, output, use_len); + status = sl_se_aes_crypt_cbc(cmd_ctx, + key, + SL_SE_ENCRYPT, + BUFSIZE, + ccm_ctx->cbc_mac_state, + b, + out_buf); + + if (status != SL_STATUS_OK) { + return status; + } + } + ccm_ctx->processed_message_length += use_len; + *output_length += use_len; + len_left -= use_len; + output += use_len; + + if (len_left < BUFSIZE && ((ccm_ctx->processed_message_length + len_left) != ccm_ctx->total_message_length)) { + memcpy(ccm_ctx->final_data, input, len_left); + ccm_ctx->final_data_length = len_left; + break; + } + } + + if (status != SL_STATUS_OK) { + return status; + } + + return SL_STATUS_OK; +} + +sl_status_t sl_se_ccm_multipart_finish(sl_se_ccm_multipart_context_t *ccm_ctx, + sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + uint8_t *tag, + uint8_t tag_size, + uint8_t *output, + uint8_t output_size, + uint8_t *output_length) +{ + (void)output; + uint8_t q; + uint8_t ctr[BUFSIZE] = { 0 }; + uint8_t out_tag[BUFSIZE] = { 0 }; + //Check input parameters + if (ccm_ctx == NULL || cmd_ctx == NULL || key == NULL || tag == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (tag_size < ccm_ctx->tag_len || output_size < ccm_ctx->final_data_length) { + return SL_STATUS_INVALID_PARAMETER; + } + + sl_status_t status = SL_STATUS_OK; + + // Reset CTR counter. + q = 16 - 1 - (unsigned char) ccm_ctx->iv_len; + + ctr[0] = q - 1; + memcpy(ctr + 1, ccm_ctx->iv, ccm_ctx->iv_len); + + // Encrypt the tag with CTR. + uint8_t empty[BUFSIZE] = { 0 }; + status = sl_se_aes_crypt_ctr(cmd_ctx, + key, + ccm_ctx->tag_len, + NULL, + ctr, + empty, + ccm_ctx->cbc_mac_state, + out_tag); + + if (status != SL_STATUS_OK) { + memset(out_tag, 0, sizeof(out_tag)); + return status; + } + + if (ccm_ctx->mode == SL_SE_DECRYPT) { + if (memcmp_time_cst(tag, out_tag, ccm_ctx->tag_len) != 0) { + memset(tag, 0, ccm_ctx->tag_len); + return SL_STATUS_INVALID_SIGNATURE; + } + } else { + memcpy(tag, out_tag, ccm_ctx->tag_len); + } + + *output_length = 0; + return SL_STATUS_OK; +} +#endif// _SILICON_LABS_32B_SERIES_2_CONFIG == 1 + #if (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) /***************************************************************************//** * Prepare a CCM streaming command context object to be used in subsequent @@ -574,7 +930,7 @@ sl_status_t sl_se_ccm_multipart_starts(sl_se_ccm_multipart_context_t *ccm_ctx, { sl_status_t status = SL_STATUS_OK; - unsigned char q; + uint8_t q; //Check input parameters if (ccm_ctx == NULL || cmd_ctx == NULL || key == NULL || iv == NULL) { @@ -600,10 +956,9 @@ sl_status_t sl_se_ccm_multipart_starts(sl_se_ccm_multipart_context_t *ccm_ctx, memset(ccm_ctx, 0, sizeof(sl_se_ccm_multipart_context_t)); ccm_ctx->mode = mode; - ccm_ctx->message_length = 0; + ccm_ctx->processed_message_length = 0; ccm_ctx->total_message_length = total_message_length; ccm_ctx->tag_len = tag_len; - ccm_ctx->last_update_operation = false; memcpy(ccm_ctx->iv, iv, iv_len); SE_Command_t *se_cmd = &cmd_ctx->command; @@ -700,56 +1055,124 @@ sl_status_t sl_se_ccm_multipart_update(sl_se_ccm_multipart_context_t *ccm_ctx, } if (length == 0) { - ccm_ctx->last_update_operation = true; return SL_STATUS_OK; } - if ((ccm_ctx->message_length) + length > ccm_ctx->total_message_length) { + if (ccm_ctx->processed_message_length + length > ccm_ctx->total_message_length) { return SL_STATUS_INVALID_PARAMETER; } - if (length > 0 && (input == NULL || output == NULL)) { + // Check variable overflow + if (ccm_ctx->processed_message_length > 0xFFFFFFFF - length) { return SL_STATUS_INVALID_PARAMETER; } - if ((uint32_t)output + length > RAM_MEM_END) { + if (length > 0 && (input == NULL || output == NULL)) { return SL_STATUS_INVALID_PARAMETER; } - if (ccm_ctx->last_update_operation == true) { - // We've already closed the input stream, no way back. + if ((uint32_t)output + length > RAM_MEM_END) { return SL_STATUS_INVALID_PARAMETER; } SE_Command_t *se_cmd = &cmd_ctx->command; + *output_length = 0; // Approach: // Encrypt or decrypt regularly with context store. The crypto DMA must have input data in the 'END' operation, thus, // some data must be saved in the context. - ccm_ctx->message_length += length; - if ((length % 16 != 0) && (ccm_ctx->message_length != ccm_ctx->total_message_length)) { - return SL_STATUS_INVALID_PARAMETER; + if ((ccm_ctx->final_data_length + length) < 16 && length < 16) { + if (ccm_ctx->final_data_length > 16) { + // Context is not valid. + return SL_STATUS_INVALID_PARAMETER; + } + + memcpy(ccm_ctx->mode_specific_buffer.final_data + ccm_ctx->final_data_length, input, length); + ccm_ctx->final_data_length += length; + return SL_STATUS_OK; } - if ((ccm_ctx->message_length == ccm_ctx->total_message_length)) { - // Indicate that this is our last operation - ccm_ctx->last_update_operation = true; - //The update operation must have a multiple of 16 as input, so what is left up to or equal 16 bytes will be stored. - if (length <= 16) { - //go directly to finish - memcpy(ccm_ctx->mode_specific_buffer.final_data, input, length); - ccm_ctx->final_data_length = length; + // If there is data in final_data, this must be processed first + if (ccm_ctx->final_data_length) { + if (ccm_ctx->final_data_length > 16) { + // Context is not valid. + return SL_STATUS_INVALID_PARAMETER; + } + + // Fill up the remainder of the buffer. + memcpy(ccm_ctx->mode_specific_buffer.final_data + ccm_ctx->final_data_length, input, 16 - ccm_ctx->final_data_length); + + if (ccm_ctx->processed_message_length + 16 == ccm_ctx->total_message_length ) { + // The finish operation must have some data or the SE fails. + ccm_ctx->final_data_length = 16; + return SL_STATUS_OK; + } + + SE_DataTransfer_t iv_ctx_in = SE_DATATRANSFER_DEFAULT(ccm_ctx->se_ctx, sizeof(ccm_ctx->se_ctx)); + + SE_DataTransfer_t data_in = + SE_DATATRANSFER_DEFAULT(ccm_ctx->mode_specific_buffer.final_data, 16); + SE_DataTransfer_t data_out = + SE_DATATRANSFER_DEFAULT(output, 16); + + SE_DataTransfer_t ctx_out = SE_DATATRANSFER_DEFAULT(ccm_ctx->se_ctx, sizeof(ccm_ctx->se_ctx)); + + sli_se_command_init(cmd_ctx, + ((ccm_ctx->mode == SL_SE_DECRYPT) + ? SLI_SE_COMMAND_AES_CCM_DECRYPT : SLI_SE_COMMAND_AES_CCM_ENCRYPT) + | SLI_SE_COMMAND_OPTION_CONTEXT_ADD); + + sli_add_key_parameters(cmd_ctx, key, status); + + SE_addParameter(se_cmd, 16); + + sli_add_key_metadata(cmd_ctx, key, status); + sli_add_key_input(cmd_ctx, key, status); + + SE_addDataInput(se_cmd, &iv_ctx_in); + SE_addDataInput(se_cmd, &data_in); + + SE_addDataOutput(se_cmd, &data_out); + SE_addDataOutput(se_cmd, &ctx_out); + + status = sli_se_execute_and_wait(cmd_ctx); + if (status != SL_STATUS_OK) { + memset(output, 0, length); + memset(ccm_ctx->se_ctx, 0, sizeof(ccm_ctx->se_ctx)); *output_length = 0; + return status; + } + ccm_ctx->processed_message_length += 16; + output += 16; + length -= (16 - ccm_ctx->final_data_length); + input += (16 - ccm_ctx->final_data_length); + ccm_ctx->final_data_length = 0; + *output_length += 16; + } + + if (length < 16) { + memcpy(ccm_ctx->mode_specific_buffer.final_data, input, length); + ccm_ctx->final_data_length += length; + return SL_STATUS_OK; + } + + // Run only multiples of 16 and store residue data in context + if (length % 16 != 0) { + uint8_t residue_data_length = length % 16; + memcpy(ccm_ctx->mode_specific_buffer.final_data, input + (length - residue_data_length), residue_data_length); + length -= residue_data_length; + ccm_ctx->final_data_length = residue_data_length; + } + + if ((ccm_ctx->total_message_length == ccm_ctx->processed_message_length + length) && !ccm_ctx->final_data_length) { + // The finish operation must have some data or the SE fails. + memcpy(ccm_ctx->mode_specific_buffer.final_data, input + (length - 16), 16); + ccm_ctx->final_data_length = 16; + length -= 16; + if (!length) { return SL_STATUS_OK; - } else if (length % 16 > 0) { - memcpy(ccm_ctx->mode_specific_buffer.final_data, input + (length - length % 16), length % 16); - ccm_ctx->final_data_length = length % 16; - } else { - memcpy(ccm_ctx->mode_specific_buffer.final_data, input + (length - 16), 16); - ccm_ctx->final_data_length = 16; } - length -= ccm_ctx->final_data_length; } SE_DataTransfer_t iv_ctx_in = SE_DATATRANSFER_DEFAULT(ccm_ctx->se_ctx, sizeof(ccm_ctx->se_ctx)); @@ -786,7 +1209,8 @@ sl_status_t sl_se_ccm_multipart_update(sl_se_ccm_multipart_context_t *ccm_ctx, return status; } - *output_length = length; + *output_length += length; + ccm_ctx->processed_message_length += length; return status; } @@ -2227,6 +2651,15 @@ sl_status_t sl_se_gcm_multipart_update(sl_se_gcm_multipart_context_t *gcm_ctx, // Case final_data_length + length > 16: Add data to fill up the gcm_ctx->final_data-buffer, run update // on the gcm_ctx->final_data-buffer and finally run update as explained above on the rest of the data. + // Our drivers only support full or no overlap between input and output + // buffers. So in the case of partial overlap, copy the input buffer into + // the output buffer and process it in place as if the buffers fully + // overlapped. + if ((output > input) && (output < (input + length))) { + memmove(output, input, length); + input = output; + } + // Check for data in final_data_length. if (gcm_ctx->final_data_length && gcm_ctx->final_data_length != 16) { if ((gcm_ctx->final_data_length + length) < 16) { diff --git a/util/third_party/crypto/sl_component/se_manager/src/sl_se_manager_util.c b/util/third_party/crypto/sl_component/se_manager/src/sl_se_manager_util.c index 4177bb41da..143ccdee80 100644 --- a/util/third_party/crypto/sl_component/se_manager/src/sl_se_manager_util.c +++ b/util/third_party/crypto/sl_component/se_manager/src/sl_se_manager_util.c @@ -556,15 +556,29 @@ sl_status_t sl_se_init_otp(sl_se_command_context_t *cmd_ctx, uint8_t reset_threshold; } otp_tamper_settings; + // Check for reserved sources + if ((otp_init->tamper_levels[SL_SE_TAMPER_SIGNAL_RESERVED_1] != SL_SE_TAMPER_LEVEL_IGNORE) + || (otp_init->tamper_levels[SL_SE_TAMPER_SIGNAL_RESERVED_2] != SL_SE_TAMPER_LEVEL_IGNORE) + || (otp_init->tamper_levels[SL_SE_TAMPER_SIGNAL_RESERVED_3] != SL_SE_TAMPER_LEVEL_IGNORE) + || (otp_init->tamper_levels[SL_SE_TAMPER_SIGNAL_RESERVED_4] != SL_SE_TAMPER_LEVEL_IGNORE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Combine tamper levels, two per byte for (size_t i = 0; i < SL_SE_TAMPER_SIGNAL_NUM_SIGNALS; i += 2) { // Check for reserved levels - EFM_ASSERT((otp_init->tamper_levels[i] != 3) - && (otp_init->tamper_levels[i] != 5) - && (otp_init->tamper_levels[i] != 6)); - EFM_ASSERT((otp_init->tamper_levels[i + 1] != 3) - && (otp_init->tamper_levels[i + 1] != 5) - && (otp_init->tamper_levels[i + 1] != 6)); + for (size_t offset = 0; offset < 2; ++offset) { + switch (otp_init->tamper_levels[i + offset]) { + case SL_SE_TAMPER_LEVEL_IGNORE: + case SL_SE_TAMPER_LEVEL_INTERRUPT: + case SL_SE_TAMPER_LEVEL_FILTER: + case SL_SE_TAMPER_LEVEL_RESET: + case SL_SE_TAMPER_LEVEL_PERMANENTLY_ERASE_OTP: + break; + default: + return SL_STATUS_INVALID_PARAMETER; + } + } otp_tamper_settings.levels[i / 2] = (otp_init->tamper_levels[i] & 0x7) | ((otp_init->tamper_levels[i + 1] & 0x7) << 4); diff --git a/util/third_party/crypto/sl_component/sl_mbedtls_support/config/config-device-acceleration.h b/util/third_party/crypto/sl_component/sl_mbedtls_support/config/config-device-acceleration.h index 6d3fbbc045..fbe5f13694 100644 --- a/util/third_party/crypto/sl_component/sl_mbedtls_support/config/config-device-acceleration.h +++ b/util/third_party/crypto/sl_component/sl_mbedtls_support/config/config-device-acceleration.h @@ -54,6 +54,10 @@ #include "em_se.h" #endif +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + /** * @name SECTION: Silicon Labs Acceleration settings * @@ -498,9 +502,11 @@ && (defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) \ || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) \ || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) ) +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) #undef MBEDTLS_ENTROPY_RAIL_PRESENT #define MBEDTLS_ENTROPY_RAIL_PRESENT #endif +#endif /* Default ECC configuration for Silicon Labs devices: */ diff --git a/util/third_party/crypto/sl_component/sl_mbedtls_support/src/sl_entropy_hardware.c b/util/third_party/crypto/sl_component/sl_mbedtls_support/src/sl_entropy_hardware.c index 569b28d8f5..d8a5f035c2 100644 --- a/util/third_party/crypto/sl_component/sl_mbedtls_support/src/sl_entropy_hardware.c +++ b/util/third_party/crypto/sl_component/sl_mbedtls_support/src/sl_entropy_hardware.c @@ -100,8 +100,7 @@ static int rail_get_random(unsigned char *output, } #endif // radio fallback -#if defined(MBEDTLS_ENTROPY_ADC_C) \ - && !defined(MBEDTLS_ENTROPY_RAIL_PRESENT) \ +#if defined(MBEDTLS_ENTROPY_ADC_C) \ && (!defined(SLI_ENTROPY_HAVE_TRNG) || defined(SLI_ENTROPY_REQUIRE_FALLBACK)) #if !defined(MBEDTLS_ENTROPY_ADC_INSTANCE) #define MBEDTLS_ENTROPY_ADC_INSTANCE 0 @@ -129,6 +128,33 @@ static int adc_get_random(unsigned char *output, } #endif // ADC fallback +#if (defined(MBEDTLS_ENTROPY_RAIL_PRESENT) || defined(MBEDTLS_ENTROPY_ADC_C)) \ + && (!defined(SLI_ENTROPY_HAVE_TRNG) || defined(SLI_ENTROPY_REQUIRE_FALLBACK)) +static int rail_adc_entropy(unsigned char *output, + size_t len, + size_t *olen) +{ + (void) output; + (void) len; + (void) olen; + + *olen = 0; + int ret = MBEDTLS_ERR_ENTROPY_SOURCE_FAILED; + #if defined(MBEDTLS_ENTROPY_RAIL_PRESENT) + ret = rail_get_random(output, len, olen); + if (*olen > 0 && ret == 0) { + // Return if we actually gathered something + // Otherwise, fallback to the ADC source if it is available. + return ret; + } + #endif // MBEDTLS_ENTROPY_RAIL_PRESENT + #if defined(MBEDTLS_ENTROPY_ADC_C) + ret = adc_get_random(output, len, olen); + #endif // MBEDTLS_ENTROPY_ADC_C + return ret; +} +#endif // RAIL and ADC entropy + // ------------------------------------- // Global function definitions @@ -146,24 +172,12 @@ int mbedtls_hardware_poll(void *data, if ((rev.major == 1) && (rev.minor < 3)) { // On affected revisions, fall back to radio (prefered) or ADC entropy - #if defined(MBEDTLS_ENTROPY_RAIL_PRESENT) - return rail_get_random(output, len, olen); - #elif defined(MBEDTLS_ENTROPY_ADC_C) - return adc_get_random(output, len, olen); - #else - return MBEDTLS_ERR_ENTROPY_SOURCE_FAILED; - #endif + return rail_adc_entropy(output, len, olen); } #elif defined(SLI_ENTROPY_REQUIRE_FALLBACK) // Other devices for which this symbol is defined have TRNG erratas requiring // fallback to other sources for all revisions. - #if defined(MBEDTLS_ENTROPY_RAIL_PRESENT) - return rail_get_random(output, len, olen); - #elif defined(MBEDTLS_ENTROPY_ADC_C) - return adc_get_random(output, len, olen); - #else - return MBEDTLS_ERR_ENTROPY_SOURCE_FAILED; - #endif + return rail_adc_entropy(output, len, olen); #endif #if !defined(SLI_ENTROPY_REQUIRE_FALLBACK) \ @@ -178,13 +192,9 @@ int mbedtls_hardware_poll(void *data, } else { return MBEDTLS_ERR_ENTROPY_SOURCE_FAILED; } - #elif defined(MBEDTLS_ENTROPY_RAIL_PRESENT) - return rail_get_random(output, len, olen); - #elif defined(MBEDTLS_ENTROPY_ADC_C) - return adc_get_random(output, len, olen); - #else - return MBEDTLS_ERR_ENTROPY_SOURCE_FAILED; - #endif + #else // SLI_ENTROPY_HAVE_TRNG + return rail_adc_entropy(output, len, olen); + #endif // SLI_ENTROPY_HAVE_TRNG #endif } diff --git a/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_crypto_transparent_driver_aead.c b/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_crypto_transparent_driver_aead.c index 754eb81ad1..b2215c2c94 100644 --- a/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_crypto_transparent_driver_aead.c +++ b/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_crypto_transparent_driver_aead.c @@ -2135,77 +2135,82 @@ psa_status_t sli_crypto_transparent_aead_update(sli_crypto_transparent_aead_oper return PSA_SUCCESS; } -#if defined(PSA_WANT_ALG_GCM) - if (PSA_ALG_AEAD_WITH_SHORTENED_TAG(operation->alg, 0) == PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0)) { - // Deal with input that are not a multiple of 16. - if ((operation->unprocessed_length + input_length) < 16 && input_length < 16) { - if (operation->unprocessed_length > 16) { - // Context is not valid. - return PSA_ERROR_INVALID_ARGUMENT; - } + // Deal with input that are not a multiple of 16. + if ((operation->unprocessed_length + input_length) < 16 && input_length < 16) { + if (operation->unprocessed_length > 16) { + // Context is not valid. + return PSA_ERROR_INVALID_ARGUMENT; + } - // Fill context buffer and end operation. - memcpy(operation->unprocessed_block + operation->unprocessed_length, input, input_length); - operation->unprocessed_length += input_length; - *output_length = 0; + // Fill context buffer and end operation. + memcpy(operation->unprocessed_block + operation->unprocessed_length, input, input_length); + operation->unprocessed_length += input_length; + *output_length = 0; - return PSA_SUCCESS; - } + return PSA_SUCCESS; } -#endif if (operation->processed_len == 0 && operation->add_len == 0) { // Multipart operation not initialized. crypto_aead_start(operation); } -#if defined(PSA_WANT_ALG_GCM) uint8_t input_offset = 0; uint8_t output_offset = 0; - if (PSA_ALG_AEAD_WITH_SHORTENED_TAG(operation->alg, 0) == PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0)) { - if (operation->unprocessed_length != 0) { - if (operation->unprocessed_length > 16) { - // Context is not valid. - return PSA_ERROR_INVALID_ARGUMENT; - } + if (operation->unprocessed_length != 0) { + if (operation->unprocessed_length > 16) { + // Context is not valid. + return PSA_ERROR_INVALID_ARGUMENT; + } - // If there is data stored in the context it must be processed first. - input_offset = 16 - operation->unprocessed_length; + // If there is data stored in the context it must be processed first. + input_offset = 16 - operation->unprocessed_length; - memcpy(operation->unprocessed_block + operation->unprocessed_length, input, input_offset); + memcpy(operation->unprocessed_block + operation->unprocessed_length, input, input_offset); +#if defined(PSA_WANT_ALG_GCM) + if (PSA_ALG_AEAD_WITH_SHORTENED_TAG(operation->alg, 0) == PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0)) { sli_gcm_update(operation, NULL, sizeof(operation->unprocessed_block), operation->unprocessed_block, output); + } +#endif +#if defined(PSA_WANT_ALG_CCM) + if (PSA_ALG_AEAD_WITH_SHORTENED_TAG(operation->alg, 0) == PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0)) { + sli_ccm_update(operation, + NULL, + sizeof(operation->unprocessed_block), + operation->unprocessed_block, + output); + } +#endif - input_length -= input_offset; - output_offset += 16; - input += input_offset; - output += output_offset; + input_length -= input_offset; + output_offset += 16; + input += input_offset; + output += output_offset; - sli_psa_zeroize(operation->unprocessed_block, sizeof(operation->unprocessed_block)); - operation->unprocessed_length = 0; + sli_psa_zeroize(operation->unprocessed_block, sizeof(operation->unprocessed_block)); + operation->unprocessed_length = 0; - if (input_length < 16) { - // Fill context buffer and end operation. - memcpy(operation->unprocessed_block, input, input_length); - operation->unprocessed_length = input_length; - *output_length = output_offset; + if (input_length < 16) { + // Fill context buffer and end operation. + memcpy(operation->unprocessed_block, input, input_length); + operation->unprocessed_length = input_length; + *output_length = output_offset; - return PSA_SUCCESS; - } + return PSA_SUCCESS; } - // Store data that is not a multiple of 16 in context. - uint8_t res_data_length = input_length % 16; - memcpy(operation->unprocessed_block, input + (input_length - res_data_length), - res_data_length); - operation->unprocessed_length = res_data_length; - input_length -= res_data_length; } -#endif // PSA_WANT_ALG_GCM + // Store data that is not a multiple of 16 in context. + uint8_t res_data_length = input_length % 16; + memcpy(operation->unprocessed_block, input + (input_length - res_data_length), + res_data_length); + operation->unprocessed_length = res_data_length; + input_length -= res_data_length; // Our drivers only support full or no overlap between input and output // buffers. So in the case of partial overlap, copy the input buffer into @@ -2239,7 +2244,7 @@ psa_status_t sli_crypto_transparent_aead_update(sli_crypto_transparent_aead_oper input, output); - *output_length = input_length; + *output_length = input_length + output_offset; break; } #endif @@ -2302,29 +2307,23 @@ psa_status_t sli_crypto_transparent_aead_finish(sli_crypto_transparent_aead_oper crypto_aead_start(operation); } -#if defined(PSA_WANT_ALG_GCM) - if (PSA_ALG_AEAD_WITH_SHORTENED_TAG(operation->alg, 0) == PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0)) { - if (operation->unprocessed_length) { - // Any unprocessed data in context must be processed first. - if (ciphertext_size < operation->unprocessed_length) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - sli_gcm_update(operation, - NULL, - operation->unprocessed_length, - operation->unprocessed_block, - ciphertext); - - *ciphertext_length = operation->unprocessed_length; - } - } -#endif - switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(operation->alg, 0)) { #if defined(PSA_WANT_ALG_GCM) case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): { + if (operation->unprocessed_length) { + // Any unprocessed data in context must be processed first. + if (ciphertext_size < operation->unprocessed_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + sli_gcm_update(operation, + NULL, + operation->unprocessed_length, + operation->unprocessed_block, + ciphertext); + + *ciphertext_length = operation->unprocessed_length; + } sli_gcm_finish(operation, NULL, tag, @@ -2336,6 +2335,19 @@ psa_status_t sli_crypto_transparent_aead_finish(sli_crypto_transparent_aead_oper #if defined(PSA_WANT_ALG_CCM) case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): { + if (operation->unprocessed_length) { + // Any unprocessed data in context must be processed first. + if (ciphertext_size < operation->unprocessed_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + sli_ccm_update(operation, + NULL, + operation->unprocessed_length, + operation->unprocessed_block, + ciphertext); + + *ciphertext_length = operation->unprocessed_length; + } sli_ccm_finish(operation, NULL, tag, diff --git a/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_aead.c b/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_aead.c index ba4fbbe124..380db10715 100644 --- a/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_aead.c +++ b/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_aead.c @@ -1197,12 +1197,17 @@ psa_status_t sli_cryptoacc_transparent_aead_update(sli_cryptoacc_transparent_aea return PSA_ERROR_BAD_STATE; } - if (input_length == 0) { - return PSA_SUCCESS; + // Check variable overflow + if (operation->processed_len > 0xFFFFFFFF - input_length) { + return PSA_ERROR_INVALID_ARGUMENT; } *output_length = 0; + if (input_length == 0) { + return PSA_SUCCESS; + } + psa_algorithm_t alg = operation->alg; psa_status_t return_status = PSA_ERROR_CORRUPTION_DETECTED; @@ -1219,24 +1224,24 @@ psa_status_t sli_cryptoacc_transparent_aead_update(sli_cryptoacc_transparent_aea block_t nonce_block = NULL_blk; block_t aad_block = NULL_blk; -#if defined(PSA_WANT_ALG_GCM) - if (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0) == PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0)) { - // The extra logic is to support non-blocksize input data for gcm. - - // Store data in context if there is space in the data buffer. - if ((input_length + operation->final_data_length) < 16 && input_length < 16) { - if (operation->final_data_length > 16) { - //Invalid context. - return PSA_ERROR_INVALID_ARGUMENT; - } + // The extra logic is to support non-blocksize input data. - memcpy(operation->final_data + operation->final_data_length, input, input_length); - operation->final_data_length += input_length; - return PSA_SUCCESS; + // Store data in context if there is space in the data buffer. + if ((input_length + operation->final_data_length) < 16 && input_length < 16) { + if (operation->final_data_length > 16) { + // Invalid context. + return PSA_ERROR_INVALID_ARGUMENT; } + + memcpy(operation->final_data + operation->final_data_length, input, input_length); + operation->final_data_length += input_length; + return PSA_SUCCESS; } + uint8_t input_offset = 0; - uint8_t output_offset = 0; + +#if defined(PSA_WANT_ALG_CCM) + uint32_t tag_length = PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg); #endif if (operation->ad_len == 0 && operation->processed_len == 0) { @@ -1244,29 +1249,37 @@ psa_status_t sli_cryptoacc_transparent_aead_update(sli_cryptoacc_transparent_aea nonce_block = block_t_convert(operation->ctx.preinit.nonce, operation->ctx.preinit.nonce_length); } - #if defined(PSA_WANT_ALG_GCM) + if (operation->final_data_length) { + if (operation->final_data_length > 16) { + // Invalid context. + return PSA_ERROR_INVALID_ARGUMENT; + } - if (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0) == PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0)) { - if (operation->final_data_length) { - if (operation->final_data_length > 16) { - //Invalid context. - return PSA_ERROR_INVALID_ARGUMENT; - } + // If there is data stored in context: fill final_data buffer and process it first. + input_offset = 16 - operation->final_data_length; + memcpy(operation->final_data + operation->final_data_length, input, input_offset); - // If there is data stored in context: fill final_data buffer and process it first. - input_offset = 16 - operation->final_data_length; - memcpy(operation->final_data + operation->final_data_length, input, input_offset); +#if defined(PSA_WANT_ALG_CCM) + if (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0) == PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0)) { + if (operation->processed_len + 16 == operation->total_length) { + operation->final_data_length = 16; + return PSA_SUCCESS; + } + } +#endif - block_t input_block_final = block_t_convert(operation->final_data, 16); - block_t output_block_final = block_t_convert(output, 16); + block_t input_block_final = block_t_convert(operation->final_data, 16); + block_t output_block_final = block_t_convert(output, 16); - return_status = cryptoacc_management_acquire(); - if (return_status != PSA_SUCCESS) { - return return_status; - } + return_status = cryptoacc_management_acquire(); + if (return_status != PSA_SUCCESS) { + return return_status; + } + #if defined(PSA_WANT_ALG_GCM) + if (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0) == PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0)) { if (operation->ad_len == 0 && operation->processed_len == 0) { - //Not initialized. + // Not initialized. if (operation->direction == SLI_AES_ENC) { sx_ret = sx_aes_gcm_encrypt_init(&key, &input_block_final, @@ -1297,35 +1310,75 @@ psa_status_t sli_cryptoacc_transparent_aead_update(sli_cryptoacc_transparent_aea &ctx_out_block); } } + } + #endif //PSA_WANT_ALG_GCM - // Release ownership. - return_status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS || return_status != PSA_SUCCESS ) { - return PSA_ERROR_HARDWARE_FAILURE; + #if defined(PSA_WANT_ALG_CCM) + if (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0) == PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0)) { + if (operation->ad_len == 0 && operation->processed_len == 0) { + // Not initialized. + if (operation->direction == SLI_AES_ENC) { + sx_ret = sx_aes_ccm_encrypt_init(&key, + &input_block_final, + &output_block_final, + &nonce_block, + &ctx_out_block, + &aad_block, + tag_length, + operation->total_length); + } else { + sx_ret = sx_aes_ccm_decrypt_init(&key, + &input_block_final, + &output_block_final, + &nonce_block, + &ctx_out_block, + &aad_block, + tag_length, + operation->total_length); + } + } else { + if (operation->direction == SLI_AES_ENC) { + sx_ret = sx_aes_ccm_encrypt_update(&key, + &input_block_final, + &output_block_final, + &ctx_in_block, + &ctx_out_block); + } else { + sx_ret = sx_aes_ccm_decrypt_update(&key, + &input_block_final, + &output_block_final, + &ctx_in_block, + &ctx_out_block); + } } - - operation->final_data_length = 0; - input_length -= input_offset; - operation->processed_len += 16; - output_offset += 16; - *output_length += 16; } + #endif //PSA_WANT_ALG_CCM - // If data is less than 16: store data in context. - if (input_length < 16) { - memcpy(operation->final_data, input + input_offset, input_length); - operation->final_data_length = input_length; - return PSA_SUCCESS; + // Release ownership. + return_status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS || return_status != PSA_SUCCESS ) { + return PSA_ERROR_HARDWARE_FAILURE; } - // Store data that is not a multiple of 16 in context. - uint8_t res_data_length = input_length % 16; - memcpy(operation->final_data, input + input_offset + (input_length - res_data_length), res_data_length); - operation->final_data_length = res_data_length; - input_length -= res_data_length; - input_block = block_t_convert(input + input_offset, input_length); - output_block = block_t_convert(output + output_offset, input_length); + + operation->final_data_length = 0; + input_length -= input_offset; + operation->processed_len += 16; + output += 16; + *output_length += 16; } - #endif + + // Store data in context if there is space in the data buffer. + if (input_length < 16 && !operation->final_data_length && input_length < 16) { + memcpy(operation->final_data, input + input_offset, input_length); + operation->final_data_length = input_length; + return PSA_SUCCESS; + } + + // Store data that is not a multiple of 16 in context. + uint8_t res_data_length = input_length % 16; + memcpy(operation->final_data, input + input_offset + (input_length - res_data_length), res_data_length); + operation->final_data_length = res_data_length; + input_length -= res_data_length; // Get ownership. return_status = cryptoacc_management_acquire(); @@ -1336,29 +1389,22 @@ psa_status_t sli_cryptoacc_transparent_aead_update(sli_cryptoacc_transparent_aea switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { #if defined(PSA_WANT_ALG_CCM) case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): - // CCM multipart finish will hardfault without input data, so we must always save up to 16 bytes. - // Check for last operation. + // CCM multipart finish will hardfault without input data, so we must always save + // some data for the final operation. if ((operation->processed_len + input_length) == operation->total_length) { - if (input_length <= 16) { - memcpy(operation->final_data, input, input_length); - operation->final_data_length = input_length; + memcpy(operation->final_data, input + (input_length - 16), 16); + operation->final_data_length = 16; + input_length -= operation->final_data_length; + if (!input_length) { return PSA_SUCCESS; - } else if (input_length % 16 > 0) { - memcpy(operation->final_data, input + (input_length - input_length % 16), input_length % 16); - operation->final_data_length = input_length % 16; - } else { - memcpy(operation->final_data, input + (input_length - 16), 16); - operation->final_data_length = 16; } - input_length -= operation->final_data_length; } - input_block = block_t_convert(input, input_length); + + input_block = block_t_convert(input + input_offset, input_length); output_block = block_t_convert(output, input_length); if (operation->ad_len == 0 && operation->processed_len == 0) { - uint32_t tag_length = PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg); - - //Not initialized. + // Not initialized. if (operation->direction == SLI_AES_ENC) { sx_ret = sx_aes_ccm_encrypt_init(&key, &input_block, @@ -1394,11 +1440,15 @@ psa_status_t sli_cryptoacc_transparent_aead_update(sli_cryptoacc_transparent_aea } } break; - #endif//PSA_WANT_ALG_CCM + #endif //PSA_WANT_ALG_CCM #if defined(PSA_WANT_ALG_GCM) case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + + input_block = block_t_convert(input + input_offset, input_length); + output_block = block_t_convert(output, input_length); + if (operation->ad_len == 0 && operation->processed_len == 0) { - //Not initialized. + // Not initialized. if (operation->direction == SLI_AES_ENC) { sx_ret = sx_aes_gcm_encrypt_init(&key, &input_block, @@ -1430,7 +1480,7 @@ psa_status_t sli_cryptoacc_transparent_aead_update(sli_cryptoacc_transparent_aea } } break; - #endif//PSA_WANT_ALG_GCM + #endif //PSA_WANT_ALG_GCM default: return PSA_ERROR_NOT_SUPPORTED; } @@ -1470,7 +1520,7 @@ psa_status_t sli_cryptoacc_transparent_aead_finish(sli_cryptoacc_transparent_aea } if (ciphertext_size < operation->final_data_length) { - return PSA_ERROR_INVALID_ARGUMENT; + return PSA_ERROR_BUFFER_TOO_SMALL; } uint32_t tag_len = PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg); @@ -1519,7 +1569,7 @@ psa_status_t sli_cryptoacc_transparent_aead_finish(sli_cryptoacc_transparent_aea *ciphertext_length = 0; break; } - #endif//PSA_WANT_ALG_CCM + #endif //PSA_WANT_ALG_CCM #if defined(PSA_WANT_ALG_GCM) case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): { @@ -1534,11 +1584,11 @@ psa_status_t sli_cryptoacc_transparent_aead_finish(sli_cryptoacc_transparent_aea *ciphertext_length = operation->final_data_length; break; } - #endif//PSA_WANT_ALG_GCM + #endif //PSA_WANT_ALG_GCM default: return PSA_ERROR_NOT_SUPPORTED; } - //Release ownership. + // Release ownership. status = cryptoacc_management_release(); if (sx_ret != CRYPTOLIB_SUCCESS || status != PSA_SUCCESS ) { *ciphertext_length = 0; @@ -1586,7 +1636,7 @@ psa_status_t sli_cryptoacc_transparent_aead_finish(sli_cryptoacc_transparent_aea &tag_block); break; } - #endif//PSA_WANT_ALG_CCM + #endif //PSA_WANT_ALG_CCM #if defined(PSA_WANT_ALG_GCM) case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): { @@ -1599,7 +1649,7 @@ psa_status_t sli_cryptoacc_transparent_aead_finish(sli_cryptoacc_transparent_aea &len_a_c); break; } - #endif//PSA_WANT_ALG_GCM + #endif //PSA_WANT_ALG_GCM default: return PSA_ERROR_NOT_SUPPORTED; } diff --git a/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_se_driver_aead.c b/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_se_driver_aead.c index a8f9922d7f..babd5fc654 100644 --- a/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_se_driver_aead.c +++ b/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_se_driver_aead.c @@ -885,7 +885,7 @@ psa_status_t sli_se_driver_aead_encrypt_decrypt_setup(sli_se_driver_aead_operati size_t key_storage_buffer_size, size_t key_storage_overhead) { -#if (defined(PSA_WANT_ALG_CCM) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 2)) \ +#if defined(PSA_WANT_ALG_CCM) \ || defined(PSA_WANT_ALG_GCM) if (operation == NULL @@ -921,7 +921,7 @@ psa_status_t sli_se_driver_aead_encrypt_decrypt_setup(sli_se_driver_aead_operati operation->alg = alg; break; #endif -#if (defined(PSA_WANT_ALG_CCM) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 2)) +#if defined(PSA_WANT_ALG_CCM) case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): operation->alg = alg; break; @@ -988,8 +988,8 @@ psa_status_t sli_se_driver_aead_set_nonce(sli_se_driver_aead_operation_t *operat const uint8_t *nonce, size_t nonce_size) { -#if (defined(PSA_WANT_ALG_CCM) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 2)) \ - || defined(PSA_WANT_ALG_GCM) \ +#if defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_GCM) \ if (operation == NULL || nonce == NULL) { @@ -1034,7 +1034,7 @@ psa_status_t sli_se_driver_aead_set_lengths(sli_se_driver_aead_operation_t *oper size_t ad_length, size_t plaintext_length) { -#if (defined(PSA_WANT_ALG_CCM) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 2)) \ +#if (defined(PSA_WANT_ALG_CCM)) \ || defined(PSA_WANT_ALG_GCM) if (operation == NULL) { @@ -1044,7 +1044,6 @@ psa_status_t sli_se_driver_aead_set_lengths(sli_se_driver_aead_operation_t *oper // To pass current PSA Crypto test suite, tag length encoded in the // algorithm needs to be checked at this point. switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(operation->alg, 0)) { -#if defined(PSA_WANT_ALG_CCM) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): if ((PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg) % 2 != 0) || PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg) < 4 @@ -1052,7 +1051,6 @@ psa_status_t sli_se_driver_aead_set_lengths(sli_se_driver_aead_operation_t *oper return PSA_ERROR_INVALID_ARGUMENT; } break; -#endif #if defined(PSA_WANT_ALG_GCM) case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): if (PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg) < 4 @@ -1083,7 +1081,7 @@ psa_status_t sli_se_driver_aead_set_lengths(sli_se_driver_aead_operation_t *oper #endif // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM } -#if (defined(PSA_WANT_ALG_CCM) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 2)) \ +#if defined(PSA_WANT_ALG_CCM) \ || defined(PSA_WANT_ALG_GCM) static psa_status_t aead_start(sli_se_driver_aead_operation_t *operation, @@ -1092,7 +1090,7 @@ static psa_status_t aead_start(sli_se_driver_aead_operation_t *operation, { // Ephemeral contexts #if defined(PSA_WANT_ALG_GCM) \ - || (defined(PSA_WANT_ALG_CCM) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 2)) + || defined(PSA_WANT_ALG_CCM) sli_se_driver_aead_preinit_t preinit = operation->ctx.preinit; #endif @@ -1103,7 +1101,7 @@ static psa_status_t aead_start(sli_se_driver_aead_operation_t *operation, return PSA_ERROR_HARDWARE_FAILURE; } -#if defined(PSA_WANT_ALG_CCM) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) +#if defined(PSA_WANT_ALG_CCM) uint8_t tag_length = PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg); #endif//PSA_WANT_ALG_CCM @@ -1127,7 +1125,7 @@ static psa_status_t aead_start(sli_se_driver_aead_operation_t *operation, operation->ad_len += input_length; return PSA_SUCCESS; #endif//PSA_WANT_ALG_GCM -#if defined(PSA_WANT_ALG_CCM) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) +#if defined(PSA_WANT_ALG_CCM) case PSA_ALG_CCM: status = sl_se_ccm_multipart_starts(&operation->ctx.ccm, &cmd_ctx, @@ -1159,7 +1157,7 @@ psa_status_t sli_se_driver_aead_update_ad(sli_se_driver_aead_operation_t *operat const uint8_t *input, size_t input_length) { -#if (defined(PSA_WANT_ALG_CCM) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 2)) \ +#if defined(PSA_WANT_ALG_CCM) \ || defined(PSA_WANT_ALG_GCM) if (operation == NULL @@ -1203,7 +1201,7 @@ psa_status_t sli_se_driver_aead_update(sli_se_driver_aead_operation_t *operation size_t output_size, size_t *output_length) { -#if (defined(PSA_WANT_ALG_CCM) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 2)) \ +#if defined(PSA_WANT_ALG_CCM) \ || defined(PSA_WANT_ALG_GCM) (void)key_buffer; @@ -1267,7 +1265,7 @@ psa_status_t sli_se_driver_aead_update(sli_se_driver_aead_operation_t *operation break; } #endif // PSA_WANT_ALG_GCM -#if defined(PSA_WANT_ALG_CCM) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) +#if defined(PSA_WANT_ALG_CCM) case PSA_ALG_CCM: { status = sl_se_ccm_multipart_update(&operation->ctx.ccm, @@ -1316,7 +1314,7 @@ psa_status_t sli_se_driver_aead_finish(sli_se_driver_aead_operation_t *operation size_t tag_size, size_t *tag_length) { -#if (defined(PSA_WANT_ALG_CCM) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 2)) \ +#if (defined(PSA_WANT_ALG_CCM)) \ || defined(PSA_WANT_ALG_GCM) (void)ciphertext; @@ -1389,7 +1387,7 @@ psa_status_t sli_se_driver_aead_finish(sli_se_driver_aead_operation_t *operation psa_status = PSA_SUCCESS; break; #endif // PSA_WANT_ALG_GCM -#if defined(PSA_WANT_ALG_CCM) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) +#if defined(PSA_WANT_ALG_CCM) case PSA_ALG_CCM: if (operation->ctx.ccm.mode != SL_SE_ENCRYPT) { psa_status = PSA_ERROR_INVALID_ARGUMENT; @@ -1452,7 +1450,7 @@ psa_status_t sli_se_driver_aead_verify(sli_se_driver_aead_operation_t *operation const uint8_t *tag, size_t tag_length) { -#if (defined(PSA_WANT_ALG_CCM) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 2)) \ +#if defined(PSA_WANT_ALG_CCM) \ || defined(PSA_WANT_ALG_GCM) (void)plaintext; @@ -1519,7 +1517,7 @@ psa_status_t sli_se_driver_aead_verify(sli_se_driver_aead_operation_t *operation psa_status = PSA_SUCCESS; break; #endif // PSA_WANT_ALG_GCM -#if defined(PSA_WANT_ALG_CCM) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) +#if defined(PSA_WANT_ALG_CCM) case PSA_ALG_CCM: { uint32_t tag_len = PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg); diff --git a/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_se_transparent_driver_mac.c b/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_se_transparent_driver_mac.c index 8e7ce1ce3f..b058822085 100644 --- a/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_se_transparent_driver_mac.c +++ b/util/third_party/crypto/sl_component/sl_psa_driver/src/sli_se_transparent_driver_mac.c @@ -437,8 +437,19 @@ psa_status_t sli_se_transparent_mac_sign_finish( + (sizeof(operation->hmac.opad) / 2)]; size_t olen = 0; psa_algorithm_t hash_alg = PSA_ALG_HMAC_GET_HASH(operation->hmac.alg); + + #if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_SE) + if (hash_alg == PSA_ALG_SHA_384 || hash_alg == PSA_ALG_SHA_512) { + // Could only reach here if the programmer has made some errors. Take the + // safe approach of checking just in case, in order to avoid certain + // buffer overflows. + return PSA_ERROR_BAD_STATE; + } + size_t blocklen = 64; + #else // (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_SE) size_t blocklen = (hash_alg == PSA_ALG_SHA_384 || hash_alg == PSA_ALG_SHA_512) ? 128 : 64; + #endif // (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_SE) // Construct outer hash input from opad and hash result memcpy(buffer, operation->hmac.opad, blocklen); diff --git a/util/third_party/crypto/sl_component/sl_trustzone/tz_secure_key_library_s_app/tz_secure_key_library_s.slcp b/util/third_party/crypto/sl_component/sl_trustzone/tz_secure_key_library_s_app/tz_secure_key_library_s.slcp index db5ce7c360..4daa89d870 100644 --- a/util/third_party/crypto/sl_component/sl_trustzone/tz_secure_key_library_s_app/tz_secure_key_library_s.slcp +++ b/util/third_party/crypto/sl_component/sl_trustzone/tz_secure_key_library_s_app/tz_secure_key_library_s.slcp @@ -80,6 +80,8 @@ toolchain_settings: value: -Xlinker --cmse-implib - option: gcc_linker_option value: -Xlinker --out-implib=skl_secure_lib.o + - option: iar_linker_option + value: --import_cmse_lib_out=$PROJ_DIR$\skl_secure_lib.o tag: - "companion:user-trustzone-non-secure-app.slcp" diff --git a/util/third_party/crypto/trusted-firmware-m/interface/include/psa/error.h b/util/third_party/crypto/trusted-firmware-m/interface/include/psa/error.h index e8903f0445..2e49ee219c 100644 --- a/util/third_party/crypto/trusted-firmware-m/interface/include/psa/error.h +++ b/util/third_party/crypto/trusted-firmware-m/interface/include/psa/error.h @@ -23,7 +23,7 @@ extern "C" { * is also defined in an external header, so prevent its multiple * definition. */ -#ifndef PSA_SUCCESS +#if !defined(PSA_SUCCESS) && !defined(PSA_CRYPTO_TYPES_H) typedef int32_t psa_status_t; #endif diff --git a/util/third_party/crypto/trusted-firmware-m/interface/include/psa/storage_common.h b/util/third_party/crypto/trusted-firmware-m/interface/include/psa/storage_common.h index 3f901c5bf9..3a8f05679c 100644 --- a/util/third_party/crypto/trusted-firmware-m/interface/include/psa/storage_common.h +++ b/util/third_party/crypto/trusted-firmware-m/interface/include/psa/storage_common.h @@ -32,7 +32,10 @@ typedef uint64_t psa_storage_uid_t; /* A container for metadata associated with a specific uid */ struct psa_storage_info_t { +#if !defined(TFM_CONFIG_SL_SECURE_LIBRARY) + // The PSA crypto implementation used internally doesn't have this member. size_t capacity; +#endif size_t size; psa_storage_create_flags_t flags; }; diff --git a/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/crypto_aead.c b/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/crypto_aead.c index c67111da81..f6373ea2d2 100644 --- a/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/crypto_aead.c +++ b/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/crypto_aead.c @@ -143,9 +143,10 @@ psa_status_t tfm_crypto_aead_encrypt_setup(psa_invec in_vec[], if (status != PSA_SUCCESS) { #if defined(TFM_CONFIG_SL_SECURE_LIBRARY) if (status == PSA_ERROR_BAD_STATE) { - *handle_out = handle; + /* Invalidate the handle and abort the operation since the setup functon + never gets called to perform the proper abort operation */ /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + (void)tfm_crypto_operation_release(handle_out, true); } #endif return status; @@ -161,7 +162,7 @@ psa_status_t tfm_crypto_aead_encrypt_setup(psa_invec in_vec[], exit: /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + (void)tfm_crypto_operation_release(handle_out, true); return status; #endif /* TFM_CRYPTO_AEAD_MODULE_DISABLED */ } @@ -197,9 +198,10 @@ psa_status_t tfm_crypto_aead_decrypt_setup(psa_invec in_vec[], if (status != PSA_SUCCESS) { #if defined(TFM_CONFIG_SL_SECURE_LIBRARY) if (status == PSA_ERROR_BAD_STATE) { - *handle_out = handle; + /* Invalidate the handle and abort the operation since the setup functon + never gets called to perform the proper abort operation */ /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + (void)tfm_crypto_operation_release(handle_out, true); } #endif return status; @@ -215,7 +217,7 @@ psa_status_t tfm_crypto_aead_decrypt_setup(psa_invec in_vec[], exit: /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + (void)tfm_crypto_operation_release(handle_out, true); return status; #endif /* TFM_CRYPTO_AEAD_MODULE_DISABLED */ } @@ -258,11 +260,13 @@ psa_status_t tfm_crypto_aead_abort(psa_invec in_vec[], if (status != PSA_SUCCESS) { /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + (void)tfm_crypto_operation_release(handle_out, true); return status; } - return tfm_crypto_operation_release(handle_out); + /* The abort() function is called by the underlying crypto function + so just invalidate the operation */ + return tfm_crypto_operation_release(handle_out, false); #endif /* TFM_CRYPTO_AEAD_MODULE_DISABLED */ } @@ -304,27 +308,15 @@ psa_status_t tfm_crypto_aead_finish(psa_invec in_vec[], handle, (void **)&operation); if (status != PSA_SUCCESS) { -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if (status == PSA_ERROR_BAD_STATE) { - *handle_out = handle; - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); - } -#endif return status; } status = psa_aead_finish(operation, ciphertext, ciphertext_size, &out_vec[1].len, tag, tag_size, &out_vec[2].len); - -#if !defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if (status == PSA_SUCCESS) -#endif - { - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); - } + /* The abort() function is called by the underlying crypto function + so just indicate that the operation is invalid. */ + (void)tfm_crypto_operation_release(handle_out, false); return status; #endif /* TFM_CRYPTO_AEAD_MODULE_DISABLED */ @@ -363,25 +355,17 @@ psa_status_t tfm_crypto_aead_generate_nonce(psa_invec in_vec[], handle, (void **)&operation); if (status != PSA_SUCCESS) { -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if (status == PSA_ERROR_BAD_STATE) { - *handle_out = handle; - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); - } -#endif return status; } *handle_out = handle; status = psa_aead_generate_nonce(operation, nonce, nonce_size, &out_vec[1].len); -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if (status == PSA_ERROR_BAD_STATE) { - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + if (status != PSA_SUCCESS) { + /* If the operation failed, the abort() function is called by the underlying crypto function + so just indicate that the operation is invalid. */ + (void)tfm_crypto_operation_release(handle_out, false); } -#endif return status; #endif /* TFM_CRYPTO_AEAD_MODULE_DISABLED */ } @@ -418,23 +402,15 @@ psa_status_t tfm_crypto_aead_set_nonce(psa_invec in_vec[], handle, (void **)&operation); if (status != PSA_SUCCESS) { -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if (status == PSA_ERROR_BAD_STATE) { - *handle_out = handle; - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); - } -#endif return status; } status = psa_aead_set_nonce(operation, nonce, nonce_length); -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if (status == PSA_ERROR_BAD_STATE) { - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + if (status != PSA_SUCCESS) { + /* If the operation failed, the abort() function is called by the underlying crypto function + so just indicate that the operation is invalid. */ + (void)tfm_crypto_operation_release(handle_out, false); } -#endif return status; #endif /* TFM_CRYPTO_AEAD_MODULE_DISABLED */ } @@ -471,23 +447,15 @@ psa_status_t tfm_crypto_aead_set_lengths(psa_invec in_vec[], handle, (void **)&operation); if (status != PSA_SUCCESS) { -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if (status == PSA_ERROR_BAD_STATE) { - *handle_out = handle; - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); - } -#endif return status; } status = psa_aead_set_lengths(operation, *ad_length, *plaintext_length); -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if (status == PSA_ERROR_BAD_STATE) { - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + if (status != PSA_SUCCESS) { + /* If the operation failed, the abort() function is called by the underlying crypto function + so just indicate that the operation is invalid. */ + (void)tfm_crypto_operation_release(handle_out, false); } -#endif return status; #endif /* TFM_CRYPTO_AEAD_MODULE_DISABLED */ } @@ -530,28 +498,18 @@ psa_status_t tfm_crypto_aead_update(psa_invec in_vec[], handle, (void **)&operation); if (status != PSA_SUCCESS) { -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if (status == PSA_ERROR_BAD_STATE) { - *handle_out = handle; - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); - } -#endif return status; } -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) status = psa_aead_update(operation, input, input_length, - output, output_size, &out_vec[1].len); - if (status == PSA_ERROR_BAD_STATE) { - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + output, output_size, &out_vec[1].len); + if (status != PSA_SUCCESS) { + /* If the operation failed, the abort() function is called by the underlying crypto function + so just indicate that the operation is invalid. */ + (void)tfm_crypto_operation_release(handle_out, false); } + return status; -#else - return psa_aead_update(operation, input, input_length, - output, output_size, &out_vec[1].len); -#endif #endif /* TFM_CRYPTO_AEAD_MODULE_DISABLED */ } @@ -587,23 +545,16 @@ psa_status_t tfm_crypto_aead_update_ad(psa_invec in_vec[], handle, (void **)&operation); if (status != PSA_SUCCESS) { -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if (status == PSA_ERROR_BAD_STATE) { - *handle_out = handle; - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); - } -#endif return status; } status = psa_aead_update_ad(operation, input, input_length); -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if (status == PSA_ERROR_BAD_STATE) { - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + if (status != PSA_SUCCESS) { + /* If the operation failed, the abort() function is called by the underlying crypto function + so just indicate that the operation is invalid. */ + (void)tfm_crypto_operation_release(handle_out, false); } -#endif + return status; #endif /* TFM_CRYPTO_AEAD_MODULE_DISABLED */ } @@ -646,29 +597,18 @@ psa_status_t tfm_crypto_aead_verify(psa_invec in_vec[], handle, (void **)&operation); if (status != PSA_SUCCESS) { -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if (status == PSA_ERROR_BAD_STATE) { - *handle_out = handle; - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); - } -#endif return status; } -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) status = psa_aead_verify(operation, plaintext, plaintext_size, &out_vec[1].len, tag, tag_length); - if (status == PSA_ERROR_BAD_STATE) { - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); - } - return status; -#else - return psa_aead_update(operation, input, input_length, - output, output_size, &out_vec[1].len); -#endif + + /* The abort() function is called by the underlying crypto function + so just indicate that the operation is invalid. */ + (void)tfm_crypto_operation_release(handle_out, false); + + return status; #endif /* TFM_CRYPTO_AEAD_MODULE_DISABLED */ } /*!@}*/ diff --git a/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/crypto_alloc.c b/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/crypto_alloc.c index 2c0bc946f5..35f7047073 100644 --- a/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/crypto_alloc.c +++ b/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/crypto_alloc.c @@ -154,7 +154,7 @@ psa_status_t tfm_crypto_operation_alloc(enum tfm_crypto_operation_type type, return PSA_ERROR_NOT_PERMITTED; } -psa_status_t tfm_crypto_operation_release(uint32_t *handle) +psa_status_t tfm_crypto_operation_release(uint32_t *handle, bool clean_backend_context) { uint32_t h_val = *handle; int32_t partition_id = 0; @@ -169,8 +169,9 @@ psa_status_t tfm_crypto_operation_release(uint32_t *handle) (h_val <= TFM_CRYPTO_CONC_OPER_NUM) && (operation[h_val - 1].in_use == TFM_CRYPTO_IN_USE) && (operation[h_val - 1].owner == partition_id)) { - - memset_operation_context(h_val - 1); + if (clean_backend_context) { + memset_operation_context(h_val - 1); + } operation[h_val - 1].in_use = TFM_CRYPTO_NOT_IN_USE; operation[h_val - 1].type = TFM_CRYPTO_OPERATION_NONE; operation[h_val - 1].owner = 0; diff --git a/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/crypto_cipher.c b/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/crypto_cipher.c index 0b2653e329..63c36399a0 100644 --- a/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/crypto_cipher.c +++ b/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/crypto_cipher.c @@ -53,28 +53,19 @@ psa_status_t tfm_crypto_cipher_generate_iv(psa_invec in_vec[], handle, (void **)&operation); if (status != PSA_SUCCESS) { -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if (status == PSA_ERROR_BAD_STATE) { - *handle_out = handle; - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); - } -#endif return status; } *handle_out = handle; -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) status = psa_cipher_generate_iv(operation, iv, iv_size, &out_vec[1].len); - if (status == PSA_ERROR_BAD_STATE) { - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + if (status != PSA_SUCCESS) { + /* If the operation failed, the abort() function is called by the underlying crypto function + so just indicate that the operation is invalid. */ + (void)tfm_crypto_operation_release(handle_out, false); } + return status; -#else - return psa_cipher_generate_iv(operation, iv, iv_size, &out_vec[1].len); -#endif #endif /* TFM_CRYPTO_CIPHER_MODULE_DISABLED */ } @@ -110,26 +101,17 @@ psa_status_t tfm_crypto_cipher_set_iv(psa_invec in_vec[], handle, (void **)&operation); if (status != PSA_SUCCESS) { -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if (status == PSA_ERROR_BAD_STATE) { - *handle_out = handle; - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); - } -#endif return status; } -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) status = psa_cipher_set_iv(operation, iv, iv_length); - if (status == PSA_ERROR_BAD_STATE) { - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + if (status != PSA_SUCCESS) { + /* If the operation failed, the abort() function is called by the underlying crypto function + so just indicate that the operation is invalid. */ + (void)tfm_crypto_operation_release(handle_out, false); } + return status; -#else - return psa_cipher_set_iv(operation, iv, iv_length); -#endif #endif /* TFM_CRYPTO_CIPHER_MODULE_DISABLED */ } @@ -165,9 +147,10 @@ psa_status_t tfm_crypto_cipher_encrypt_setup(psa_invec in_vec[], if (status != PSA_SUCCESS) { #if defined(TFM_CONFIG_SL_SECURE_LIBRARY) if (status == PSA_ERROR_BAD_STATE) { - *handle_out = handle; + /* Invalidate the handle and abort the operation since the setup functon + never gets called to perform the proper abort operation */ /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + (void)tfm_crypto_operation_release(handle_out, true); } #endif return status; @@ -188,7 +171,7 @@ psa_status_t tfm_crypto_cipher_encrypt_setup(psa_invec in_vec[], exit: /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + (void)tfm_crypto_operation_release(handle_out, true); return status; #endif /* TFM_CRYPTO_CIPHER_MODULE_DISABLED */ } @@ -225,9 +208,10 @@ psa_status_t tfm_crypto_cipher_decrypt_setup(psa_invec in_vec[], if (status != PSA_SUCCESS) { #if defined(TFM_CONFIG_SL_SECURE_LIBRARY) if (status == PSA_ERROR_BAD_STATE) { - *handle_out = handle; + /* Invalidate the handle and abort the operation since the setup functon + never gets called to perform the proper abort operation */ /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + (void)tfm_crypto_operation_release(handle_out, true); } #endif return status; @@ -248,7 +232,7 @@ psa_status_t tfm_crypto_cipher_decrypt_setup(psa_invec in_vec[], exit: /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + (void)tfm_crypto_operation_release(handle_out, true); return status; #endif /* TFM_CRYPTO_CIPHER_MODULE_DISABLED */ } @@ -291,28 +275,18 @@ psa_status_t tfm_crypto_cipher_update(psa_invec in_vec[], handle, (void **)&operation); if (status != PSA_SUCCESS) { -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if (status == PSA_ERROR_BAD_STATE) { - *handle_out = handle; - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); - } -#endif return status; } -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) status = psa_cipher_update(operation, input, input_length, output, output_size, &out_vec[1].len); - if (status == PSA_ERROR_BAD_STATE) { - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + if (status != PSA_SUCCESS) { + /* If the operation failed, the abort() function is called by the underlying crypto function + so just indicate that the operation is invalid. */ + (void)tfm_crypto_operation_release(handle_out, false); } + return status; -#else - return psa_cipher_update(operation, input, input_length, - output, output_size, &out_vec[1].len); -#endif #endif /* TFM_CRYPTO_CIPHER_MODULE_DISABLED */ } @@ -351,24 +325,13 @@ psa_status_t tfm_crypto_cipher_finish(psa_invec in_vec[], handle, (void **)&operation); if (status != PSA_SUCCESS) { -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if (status == PSA_ERROR_BAD_STATE) { - *handle_out = handle; - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); - } -#endif return status; } status = psa_cipher_finish(operation, output, output_size, &out_vec[1].len); -#if !defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if (status == PSA_SUCCESS) -#endif - { - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); - } + /* The abort() function is called by the underlying crypto function + so just indicate that the operation is invalid. */ + (void)tfm_crypto_operation_release(handle_out, false); return status; #endif /* TFM_CRYPTO_CIPHER_MODULE_DISABLED */ @@ -412,11 +375,13 @@ psa_status_t tfm_crypto_cipher_abort(psa_invec in_vec[], if (status != PSA_SUCCESS) { /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + (void)tfm_crypto_operation_release(handle_out, true); return status; } - return tfm_crypto_operation_release(handle_out); + /* The abort() function is called by the underlying crypto function + so just invalidate the operation */ + return tfm_crypto_operation_release(handle_out, false); #endif /* TFM_CRYPTO_CIPHER_MODULE_DISABLED */ } diff --git a/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/crypto_hash.c b/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/crypto_hash.c index 10c5ae0c39..96d76674ec 100644 --- a/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/crypto_hash.c +++ b/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/crypto_hash.c @@ -53,9 +53,10 @@ psa_status_t tfm_crypto_hash_setup(psa_invec in_vec[], if (status != PSA_SUCCESS) { #if defined(TFM_CONFIG_SL_SECURE_LIBRARY) if (status == PSA_ERROR_BAD_STATE) { - *handle_out = handle; + /* Invalidate the handle and abort the operation since the PSA Hash + setup functon never gets called to perform the proper abort operation */ /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + (void)tfm_crypto_operation_release(handle_out, true); } #endif return status; @@ -65,8 +66,9 @@ psa_status_t tfm_crypto_hash_setup(psa_invec in_vec[], status = psa_hash_setup(operation, alg); if (status != PSA_SUCCESS) { - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + /* If the operation failed, the abort() function is called by the underlying crypto function + so just indicate that the operation is invalid. */ + (void)tfm_crypto_operation_release(handle_out, false); } return status; @@ -105,17 +107,17 @@ psa_status_t tfm_crypto_hash_update(psa_invec in_vec[], handle, (void **)&operation); if (status != PSA_SUCCESS) { -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if (status == PSA_ERROR_BAD_STATE) { - *handle_out = handle; - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); - } -#endif return status; } - return psa_hash_update(operation, input, input_length); + status = psa_hash_update(operation, input, input_length); + if (status != PSA_SUCCESS) { + /* If the operation failed, the abort() function is called by the underlying crypto function + so just indicate that the operation is invalid. */ + (void)tfm_crypto_operation_release(handle_out, false); + } + + return status; #endif /* TFM_CRYPTO_HASH_MODULE_DISABLED */ } @@ -154,22 +156,13 @@ psa_status_t tfm_crypto_hash_finish(psa_invec in_vec[], handle, (void **)&operation); if (status != PSA_SUCCESS) { -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if (status == PSA_ERROR_BAD_STATE) { - *handle_out = handle; - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); - } -#endif return status; } status = psa_hash_finish(operation, hash, hash_size, &out_vec[1].len); - if (status == PSA_SUCCESS) { - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); - } - + /* The abort() function is called by the underlying crypto function + so just indicate that the operation is invalid. */ + (void)tfm_crypto_operation_release(handle_out, false); return status; #endif /* TFM_CRYPTO_HASH_MODULE_DISABLED */ } @@ -210,12 +203,14 @@ psa_status_t tfm_crypto_hash_verify(psa_invec in_vec[], } status = psa_hash_verify(operation, hash, hash_length); -#if !defined(TFM_CONFIG_SL_SECURE_LIBRARY) if (status == PSA_SUCCESS) -#endif { /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + (void)tfm_crypto_operation_release(handle_out, true); + } else { + /* If the operation failed, the abort() function is called by the underlying crypto function + so just indicate that the operation is invalid. */ + (void)tfm_crypto_operation_release(handle_out, false); } return status; @@ -259,11 +254,13 @@ psa_status_t tfm_crypto_hash_abort(psa_invec in_vec[], status = psa_hash_abort(operation); if (status != PSA_SUCCESS) { /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + (void)tfm_crypto_operation_release(handle_out, true); return status; } - return tfm_crypto_operation_release(handle_out); + /* The abort() function is called by the underlying crypto function + so just invalidate the operation */ + return tfm_crypto_operation_release(handle_out, false); #endif /* TFM_CRYPTO_HASH_MODULE_DISABLED */ } @@ -303,10 +300,23 @@ psa_status_t tfm_crypto_hash_clone(psa_invec in_vec[], target_handle, (void **)&target_operation); if (status != PSA_SUCCESS) { +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + if (status == PSA_ERROR_BAD_STATE) { + /* Invalidate the handle and abort the operation since the PSA Hash + clone functon never gets called to perform the proper abort operation */ + /* Release the operation context, ignore if the operation fails. */ + (void)tfm_crypto_operation_release(target_handle, true); + } +#endif return status; } - return psa_hash_clone(source_operation, target_operation); + status = psa_hash_clone(source_operation, target_operation); + if (status != PSA_SUCCESS) { + /* Release the operation context, ignore if the operation fails. */ + (void)tfm_crypto_operation_release(target_handle, false); + } + return status; #endif /* TFM_CRYPTO_HASH_MODULE_DISABLED */ } diff --git a/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/crypto_key_derivation.c b/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/crypto_key_derivation.c index ef4987f407..6e0d9e89c4 100644 --- a/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/crypto_key_derivation.c +++ b/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/crypto_key_derivation.c @@ -188,7 +188,7 @@ psa_status_t tfm_crypto_key_derivation_setup(psa_invec in_vec[], } if (status != PSA_SUCCESS) { /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + (void)tfm_crypto_operation_release(handle_out, true); return status; } @@ -504,13 +504,11 @@ psa_status_t tfm_crypto_key_derivation_abort(psa_invec in_vec[], } if (status != PSA_SUCCESS) { /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + (void)tfm_crypto_operation_release(handle_out, true); return status; } - status = tfm_crypto_operation_release(handle_out); - - return status; + return tfm_crypto_operation_release(handle_out, false); #endif /* TFM_CRYPTO_KEY_DERIVATION_MODULE_DISABLED */ } diff --git a/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/crypto_mac.c b/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/crypto_mac.c index 720059077c..4414d14fec 100644 --- a/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/crypto_mac.c +++ b/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/crypto_mac.c @@ -55,9 +55,10 @@ psa_status_t tfm_crypto_mac_sign_setup(psa_invec in_vec[], if (status != PSA_SUCCESS) { #if defined(TFM_CONFIG_SL_SECURE_LIBRARY) if (status == PSA_ERROR_BAD_STATE) { - *handle_out = handle; + /* Invalidate the handle and abort the operation since the PSA Sign Mac + setup functon never gets called to perform the proper abort operation */ /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + (void)tfm_crypto_operation_release(handle_out, true); } #endif return status; @@ -79,7 +80,7 @@ psa_status_t tfm_crypto_mac_sign_setup(psa_invec in_vec[], exit: /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + (void)tfm_crypto_operation_release(handle_out, true); return status; #endif /* TFM_CRYPTO_MAC_MODULE_DISABLED */ } @@ -119,9 +120,10 @@ psa_status_t tfm_crypto_mac_verify_setup(psa_invec in_vec[], if (status != PSA_SUCCESS) { #if defined(TFM_CONFIG_SL_SECURE_LIBRARY) if (status == PSA_ERROR_BAD_STATE) { - *handle_out = handle; + /* Invalidate the handle and abort the operation since the PSA Verify Mac + setup functon never gets called to perform the proper abort operation */ /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + (void)tfm_crypto_operation_release(handle_out, true); } #endif return status; @@ -143,7 +145,7 @@ psa_status_t tfm_crypto_mac_verify_setup(psa_invec in_vec[], exit: /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + (void)tfm_crypto_operation_release(handle_out, true); return status; #endif /* TFM_CRYPTO_MAC_MODULE_DISABLED */ } @@ -180,17 +182,17 @@ psa_status_t tfm_crypto_mac_update(psa_invec in_vec[], handle, (void **)&operation); if (status != PSA_SUCCESS) { -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if (status == PSA_ERROR_BAD_STATE) { - *handle_out = handle; - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); - } -#endif return status; } - return psa_mac_update(operation, input, input_length); + status = psa_mac_update(operation, input, input_length); + if (status != PSA_SUCCESS) { + /* If the operation failed, the abort() function is called by the underlying crypto function + so just indicate that the operation is invalid. */ + (void)tfm_crypto_operation_release(handle_out, false); + } + + return status; #endif /* TFM_CRYPTO_MAC_MODULE_DISABLED */ } @@ -229,29 +231,13 @@ psa_status_t tfm_crypto_mac_sign_finish(psa_invec in_vec[], handle, (void **)&operation); if (status != PSA_SUCCESS) { -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if (status == PSA_ERROR_BAD_STATE) { - *handle_out = handle; - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); - } -#endif return status; } status = psa_mac_sign_finish(operation, mac, mac_size, &out_vec[1].len); -#if !defined(TFM_CONFIG_SL_SECURE_LIBRARY) - /* Expected by sign_message_fail() in test_suite_psa_crypto.function: - * The value of *signature_length is unspecified on error, but - * whatever it is, it should be less than signature_size, so that - * if the caller tries to read *signature_length bytes without - * checking the error code then they don't overflow a buffer. */ - if (status == PSA_SUCCESS) -#endif - { - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); - } + /* The abort() function is called by the underlying crypto function + so just indicate that the operation is invalid. */ + (void)tfm_crypto_operation_release(handle_out, false); return status; #endif /* TFM_CRYPTO_MAC_MODULE_DISABLED */ @@ -289,24 +275,13 @@ psa_status_t tfm_crypto_mac_verify_finish(psa_invec in_vec[], handle, (void **)&operation); if (status != PSA_SUCCESS) { -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if (status == PSA_ERROR_BAD_STATE) { - *handle_out = handle; - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); - } -#endif return status; } status = psa_mac_verify_finish(operation, mac, mac_length); -#if !defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if (status == PSA_SUCCESS) -#endif - { - /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); - } + /* The abort() function is called by the underlying crypto function + so just indicate that the operation is invalid. */ + (void)tfm_crypto_operation_release(handle_out, false); return status; #endif /* TFM_CRYPTO_MAC_MODULE_DISABLED */ @@ -347,14 +322,15 @@ psa_status_t tfm_crypto_mac_abort(psa_invec in_vec[], } status = psa_mac_abort(operation); - if (status != PSA_SUCCESS) { /* Release the operation context, ignore if the operation fails. */ - (void)tfm_crypto_operation_release(handle_out); + (void)tfm_crypto_operation_release(handle_out, true); return status; } - return tfm_crypto_operation_release(handle_out); + /* The abort() function is called by the underlying crypto function + so just invalidate the operation */ + return tfm_crypto_operation_release(handle_out, false); #endif /* TFM_CRYPTO_MAC_MODULE_DISABLED */ } @@ -404,7 +380,7 @@ psa_status_t tfm_crypto_mac_verify(psa_invec in_vec[], #else // No output. (void)out_vec; - + psa_status_t status = PSA_SUCCESS; CRYPTO_IN_OUT_LEN_VALIDATE(in_len, 1, 3, out_len, 0, 0); diff --git a/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/tfm_crypto_api.h b/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/tfm_crypto_api.h index a7c31040e4..8d312e2350 100644 --- a/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/tfm_crypto_api.h +++ b/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/crypto/tfm_crypto_api.h @@ -112,10 +112,11 @@ psa_status_t tfm_crypto_operation_alloc(enum tfm_crypto_operation_type type, * \brief Release an operation context in the backend * * \param[in] handle Pointer to the handle of the context to release + * \param[in] clean_backend_context Clean the backend operation context * * \return Return values as described in \ref psa_status_t */ -psa_status_t tfm_crypto_operation_release(uint32_t *handle); +psa_status_t tfm_crypto_operation_release(uint32_t *handle, bool clean_backend_context); /** * \brief Look up an operation context in the backend for the corresponding * frontend operation diff --git a/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/nvm3/nvm3.c b/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/nvm3/nvm3.c index c25838c9cc..8b12a85800 100644 --- a/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/nvm3/nvm3.c +++ b/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/nvm3/nvm3.c @@ -47,6 +47,9 @@ #endif #endif // defined(TFM_CONFIG_SL_SECURE_LIBRARY) +nvm3_Handle_t nvm3_defaultHandleData; +nvm3_Handle_t *nvm3_defaultHandle = &nvm3_defaultHandleData; + psa_status_t tfm_nvm3_init(void) { // This init function is required by TFM and not used otherwise. @@ -92,7 +95,7 @@ psa_status_t tfm_nvm3_deinit_default(psa_invec in_vec[], Ecode_t *nvm3_status = out_vec[0].base; - *nvm3_status = nvm3_deinitDefault(); + *nvm3_status = nvm3_close(nvm3_defaultHandle); return PSA_SUCCESS; } diff --git a/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/nvm3/tfm_nvm3_include.h b/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/nvm3/tfm_nvm3_include.h index 0ca224287e..eebcc3454d 100644 --- a/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/nvm3/tfm_nvm3_include.h +++ b/util/third_party/crypto/trusted-firmware-m/secure_fw/partitions/nvm3/tfm_nvm3_include.h @@ -47,7 +47,6 @@ #include "nvm3_spe.h" #endif -#include "nvm3_default_config.h" -#include "nvm3_default.h" +#include "nvm3.h" #endif /* __TFM_NVM3_INCLUDE_H__ */ diff --git a/util/third_party/openthread/.github/workflows/build.yml b/util/third_party/openthread/.github/workflows/build.yml index fe08b5f396..b4a3ff49e9 100644 --- a/util/third_party/openthread/.github/workflows/build.yml +++ b/util/third_party/openthread/.github/workflows/build.yml @@ -216,7 +216,7 @@ jobs: strategy: fail-fast: false matrix: - clang_ver: ["6.0", "7", "8", "9"] + clang_ver: ["6.0", "7", "8", "9", "10", "11", "12", "13"] env: CC: clang-${{ matrix.clang_ver }} CXX: clang++-${{ matrix.clang_ver }} @@ -226,7 +226,14 @@ jobs: submodules: true - name: Bootstrap run: | - sudo rm /etc/apt/sources.list.d/* && sudo apt-get update + sudo rm /etc/apt/sources.list.d/* + wget -O - https://apt.llvm.org/llvm-snapshot.gpg.key | sudo apt-key add - + echo 'deb http://apt.llvm.org/focal/ llvm-toolchain-focal main + deb-src http://apt.llvm.org/focal/ llvm-toolchain-focal main + # 13 + deb http://apt.llvm.org/focal/ llvm-toolchain-focal-13 main + deb-src http://apt.llvm.org/focal/ llvm-toolchain-focal-13 main' | sudo tee -a /etc/apt/sources.list + sudo apt-get update sudo apt-get --no-install-recommends install -y clang-${{ matrix.clang_ver }} clang++-${{ matrix.clang_ver }} ninja-build libreadline-dev libncurses-dev - name: Build run: | @@ -239,7 +246,7 @@ jobs: strategy: fail-fast: false matrix: - clang_ver: ["6.0", "7", "8", "9"] + clang_ver: ["6.0", "7", "8", "9", "10", "11", "12", "13"] env: CC: clang-${{ matrix.clang_ver }} CXX: clang++-${{ matrix.clang_ver }} @@ -253,6 +260,12 @@ jobs: - name: Bootstrap run: | sudo dpkg --add-architecture i386 + wget -O - https://apt.llvm.org/llvm-snapshot.gpg.key | sudo apt-key add - + echo 'deb http://apt.llvm.org/focal/ llvm-toolchain-focal main + deb-src http://apt.llvm.org/focal/ llvm-toolchain-focal main + # 13 + deb http://apt.llvm.org/focal/ llvm-toolchain-focal-13 main + deb-src http://apt.llvm.org/focal/ llvm-toolchain-focal-13 main' | sudo tee -a /etc/apt/sources.list sudo apt-get update sudo apt-get --no-install-recommends install -y clang-${{ matrix.clang_ver }} clang++-${{ matrix.clang_ver }} ninja-build sudo apt-get --no-install-recommends install -y g++-multilib libreadline-dev:i386 libncurses-dev:i386 diff --git a/util/third_party/openthread/.github/workflows/otbr.yml b/util/third_party/openthread/.github/workflows/otbr.yml index 159c84d593..368dc72df3 100644 --- a/util/third_party/openthread/.github/workflows/otbr.yml +++ b/util/third_party/openthread/.github/workflows/otbr.yml @@ -46,7 +46,7 @@ jobs: REFERENCE_DEVICE: 1 VIRTUAL_TIME: 0 PACKET_VERIFICATION: 1 - THREAD_VERSION: 1.2 + THREAD_VERSION: 1.3 INTER_OP: 1 COVERAGE: 1 MULTIPLY: 1 @@ -83,12 +83,12 @@ jobs: sudo -E ./script/test cert_suite ./tests/scripts/thread-cert/backbone/*.py || (sudo chmod a+r *.log *.json *.pcap && false) - uses: actions/upload-artifact@v2 with: - name: cov-thread-1-2-backbone-docker + name: cov-thread-1-3-backbone-docker path: /tmp/coverage/ - uses: actions/upload-artifact@v2 if: ${{ failure() }} with: - name: thread-1-2-backbone-results + name: thread-1-3-backbone-results path: | *.pcap *.json @@ -100,7 +100,7 @@ jobs: ./script/test generate_coverage gcc - uses: actions/upload-artifact@v2 with: - name: cov-thread-1-2-backbone + name: cov-thread-1-3-backbone path: tmp/coverage.info thread-border-router: @@ -144,7 +144,7 @@ jobs: REFERENCE_DEVICE: 1 VIRTUAL_TIME: 0 PACKET_VERIFICATION: ${{ matrix.packet_verification }} - THREAD_VERSION: 1.2 + THREAD_VERSION: 1.3 INTER_OP: 1 COVERAGE: 1 MULTIPLY: 1 diff --git a/util/third_party/openthread/.github/workflows/otci.yml b/util/third_party/openthread/.github/workflows/otci.yml index 5023d7c167..a1e3a9b99d 100644 --- a/util/third_party/openthread/.github/workflows/otci.yml +++ b/util/third_party/openthread/.github/workflows/otci.yml @@ -61,7 +61,7 @@ jobs: - name: Build run: | ./bootstrap - make -f examples/Makefile-simulation THREAD_VERSION=1.2 DUA=1 MLR=1 BACKBONE_ROUTER=1 CSL_RECEIVER=1 + make -f examples/Makefile-simulation THREAD_VERSION=1.3 DUA=1 MLR=1 BACKBONE_ROUTER=1 CSL_RECEIVER=1 - name: Install OTCI Python Library run: | (cd tools/otci && python3 setup.py install --user) diff --git a/util/third_party/openthread/.github/workflows/simulation-1.2.yml b/util/third_party/openthread/.github/workflows/simulation-1.2.yml index 7b7a949c9b..26166466d9 100644 --- a/util/third_party/openthread/.github/workflows/simulation-1.2.yml +++ b/util/third_party/openthread/.github/workflows/simulation-1.2.yml @@ -26,7 +26,7 @@ # POSSIBILITY OF SUCH DAMAGE. # -name: Simulation 1.2 +name: Simulation 1.3 on: [push, pull_request] @@ -40,15 +40,15 @@ jobs: GITHUB_TOKEN: "${{ secrets.GITHUB_TOKEN }}" if: "github.ref != 'refs/heads/main'" - thread-1-2: - name: thread-1-2-${{ matrix.compiler.c }}-${{ matrix.arch }} + thread-1-3: + name: thread-1-3-${{ matrix.compiler.c }}-${{ matrix.arch }} runs-on: ubuntu-20.04 env: CFLAGS: -${{ matrix.arch }} CXXFLAGS: -${{ matrix.arch }} LDFLAGS: -${{ matrix.arch }} COVERAGE: 1 - THREAD_VERSION: 1.2 + THREAD_VERSION: 1.3 VIRTUAL_TIME: 1 INTER_OP: 1 CC: ${{ matrix.compiler.c }} @@ -87,12 +87,12 @@ jobs: - uses: actions/upload-artifact@v2 if: ${{ failure() }} with: - name: thread-1-2-${{ matrix.compiler.c }}-${{ matrix.arch }}-pcaps + name: thread-1-3-${{ matrix.compiler.c }}-${{ matrix.arch }}-pcaps path: "*.pcap" - uses: actions/upload-artifact@v2 if: ${{ failure() && env.CRASHED == '1' }} with: - name: core-packet-verification-thread-1-2 + name: core-packet-verification-thread-1-3 path: | ./ot-core-dump/* - name: Generate Coverage @@ -100,7 +100,7 @@ jobs: ./script/test generate_coverage "${{ matrix.compiler.gcov }}" - uses: actions/upload-artifact@v2 with: - name: cov-thread-1-2-${{ matrix.compiler.c }}-${{ matrix.arch }} + name: cov-thread-1-3-${{ matrix.compiler.c }}-${{ matrix.arch }} path: tmp/coverage.info packet-verification-low-power: @@ -110,7 +110,7 @@ jobs: VIRTUAL_TIME: 1 COVERAGE: 1 PACKET_VERIFICATION: 1 - THREAD_VERSION: 1.2 + THREAD_VERSION: 1.3 MAC_FILTER: 1 INTER_OP: 1 INTER_OP_BBR: 0 @@ -164,13 +164,13 @@ jobs: name: cov-packet-verification-low-power path: tmp/coverage.info - packet-verification-1-1-on-1-2: + packet-verification-1-1-on-1-3: runs-on: ubuntu-20.04 env: REFERENCE_DEVICE: 1 VIRTUAL_TIME: 1 PACKET_VERIFICATION: 1 - THREAD_VERSION: 1.2 + THREAD_VERSION: 1.3 MULTIPLY: 3 steps: - uses: actions/checkout@v2 @@ -193,7 +193,7 @@ jobs: - uses: actions/upload-artifact@v2 if: ${{ failure() }} with: - name: packet-verification-1.1-on-1.2-pcaps + name: packet-verification-1.1-on-1.3-pcaps path: | *.pcap *.json @@ -202,14 +202,14 @@ jobs: ./script/test generate_coverage gcc - uses: actions/upload-artifact@v2 with: - name: cov-packet-verification-1-1-on-1-2 + name: cov-packet-verification-1-1-on-1-3 path: tmp/coverage.info expects: runs-on: ubuntu-20.04 env: COVERAGE: 1 - THREAD_VERSION: 1.2 + THREAD_VERSION: 1.3 VIRTUAL_TIME: 0 steps: - uses: actions/checkout@v2 @@ -232,7 +232,7 @@ jobs: - uses: actions/upload-artifact@v2 if: ${{ failure() && env.CRASHED == '1' }} with: - name: core-expect-1-2 + name: core-expect-1-3 path: | ./ot-core-dump/* - name: Generate Coverage @@ -243,13 +243,13 @@ jobs: name: cov-expects path: tmp/coverage.info - thread-1-2-posix: + thread-1-3-posix: runs-on: ubuntu-20.04 env: COVERAGE: 1 PYTHONUNBUFFERED: 1 READLINE: readline - THREAD_VERSION: 1.2 + THREAD_VERSION: 1.3 OT_NODE_TYPE: rcp USE_MTD: 1 VIRTUAL_TIME: 1 @@ -285,12 +285,12 @@ jobs: - uses: actions/upload-artifact@v2 if: ${{ failure() }} with: - name: thread-1-2-posix-pcaps + name: thread-1-3-posix-pcaps path: "*.pcap" - uses: actions/upload-artifact@v2 if: ${{ failure() && env.CRASHED == '1' }} with: - name: core-thread-1-2-posix + name: core-thread-1-3-posix path: | ./ot-core-dump/* - name: Generate Coverage @@ -298,16 +298,16 @@ jobs: ./script/test generate_coverage gcc - uses: actions/upload-artifact@v2 with: - name: cov-thread-1-2-posix + name: cov-thread-1-3-posix path: tmp/coverage.info upload-coverage: needs: - - thread-1-2 + - thread-1-3 - packet-verification-low-power - - packet-verification-1-1-on-1-2 + - packet-verification-1-1-on-1-3 - expects - - thread-1-2-posix + - thread-1-3-posix runs-on: ubuntu-20.04 steps: - uses: actions/checkout@v2 diff --git a/util/third_party/openthread/Android.mk b/util/third_party/openthread/Android.mk index 2e06a206c4..e2e424994f 100644 --- a/util/third_party/openthread/Android.mk +++ b/util/third_party/openthread/Android.mk @@ -222,7 +222,6 @@ LOCAL_SRC_FILES := \ src/core/backbone_router/multicast_listeners_table.cpp \ src/core/backbone_router/ndproxy_table.cpp \ src/core/border_router/infra_if.cpp \ - src/core/border_router/router_advertisement.cpp \ src/core/border_router/routing_manager.cpp \ src/core/coap/coap.cpp \ src/core/coap/coap_message.cpp \ @@ -305,6 +304,7 @@ LOCAL_SRC_FILES := \ src/core/net/ip6_filter.cpp \ src/core/net/ip6_headers.cpp \ src/core/net/ip6_mpl.cpp \ + src/core/net/nd6.cpp \ src/core/net/nd_agent.cpp \ src/core/net/netif.cpp \ src/core/net/sntp_client.cpp \ diff --git a/util/third_party/openthread/etc/cmake/options.cmake b/util/third_party/openthread/etc/cmake/options.cmake index d5594465bc..3881b89ed0 100644 --- a/util/third_party/openthread/etc/cmake/options.cmake +++ b/util/third_party/openthread/etc/cmake/options.cmake @@ -369,6 +369,11 @@ if (OT_TREL) target_compile_definitions(ot-config INTERFACE "OPENTHREAD_CONFIG_RADIO_LINK_TREL_ENABLE=1") endif() +option(OT_TX_BEACON_PAYLOAD "enable Thread beacon payload in outgoing beacons") +if (OT_TX_BEACON_PAYLOAD) + target_compile_definitions(ot-config INTERFACE "OPENTHREAD_CONFIG_MAC_OUTGOING_BEACON_PAYLOAD_ENABLE=1") +endif() + option(OT_UDP_FORWARD "enable UDP forward support") if(OT_UDP_FORWARD) target_compile_definitions(ot-config INTERFACE "OPENTHREAD_CONFIG_UDP_FORWARD_ENABLE=1") diff --git a/util/third_party/openthread/examples/apps/cli/radio.cmake b/util/third_party/openthread/examples/apps/cli/radio.cmake index dc3e4e9811..4302adca54 100644 --- a/util/third_party/openthread/examples/apps/cli/radio.cmake +++ b/util/third_party/openthread/examples/apps/cli/radio.cmake @@ -37,13 +37,17 @@ if(NOT DEFINED OT_PLATFORM_LIB_RCP) set(OT_PLATFORM_LIB_RCP ${OT_PLATFORM_LIB}) endif() +if(NOT DEFINED OT_MBEDTLS_RCP) + set(OT_MBEDTLS_RCP ${OT_MBEDTLS}) +endif() + target_link_libraries(ot-cli-radio PRIVATE openthread-cli-radio ${OT_PLATFORM_LIB_RCP} openthread-radio-cli ${OT_PLATFORM_LIB_RCP} openthread-cli-radio - ${OT_MBEDTLS} + ${OT_MBEDTLS_RCP} ot-config ) diff --git a/util/third_party/openthread/examples/platforms/utils/soft_source_match_table.c b/util/third_party/openthread/examples/platforms/utils/soft_source_match_table.c index 6d9f80c553..f19acbab71 100644 --- a/util/third_party/openthread/examples/platforms/utils/soft_source_match_table.c +++ b/util/third_party/openthread/examples/platforms/utils/soft_source_match_table.c @@ -413,3 +413,20 @@ void otPlatRadioClearSrcMatchExtEntries(otInstance *aInstance) printExtEntryTable(iid); } #endif // RADIO_CONFIG_SRC_MATCH_EXT_ENTRY_NUM + + +uint8_t utilsSoftSrcMatchFindIidFromPanId(otPanId panId) +{ + uint8_t iid = 0xFF; + + for(uint8_t index = 0; index < RADIO_CONFIG_SRC_MATCH_PANID_NUM; index++) + { + if(sPanId[index] == panId) + { + iid = index + 1; + break; + } + } + + return iid; +} diff --git a/util/third_party/openthread/examples/platforms/utils/soft_source_match_table.h b/util/third_party/openthread/examples/platforms/utils/soft_source_match_table.h index b97c0f17f9..9eb3a05712 100644 --- a/util/third_party/openthread/examples/platforms/utils/soft_source_match_table.h +++ b/util/third_party/openthread/examples/platforms/utils/soft_source_match_table.h @@ -73,6 +73,8 @@ int16_t utilsSoftSrcMatchShortFindEntry(uint8_t iid, uint16_t aShortAddress); int16_t utilsSoftSrcMatchExtFindEntry(uint8_t iid, const otExtAddress *aExtAddress); #endif // RADIO_CONFIG_SRC_MATCH_EXT_ENTRY_NUM +uint8_t utilsSoftSrcMatchFindIidFromPanId(otPanId panId); + #ifdef __cplusplus } // extern "C" #endif diff --git a/util/third_party/openthread/include/openthread/border_agent.h b/util/third_party/openthread/include/openthread/border_agent.h index 0b267a867e..83babfa142 100644 --- a/util/third_party/openthread/include/openthread/border_agent.h +++ b/util/third_party/openthread/include/openthread/border_agent.h @@ -63,17 +63,17 @@ typedef enum otBorderAgentState } otBorderAgentState; /** - * This function gets the state of Thread Border Agent role. + * Gets the #otBorderAgentState of the Thread Border Agent role. * * @param[in] aInstance A pointer to an OpenThread instance. * - * @returns State of the Border Agent. + * @returns The current #otBorderAgentState of the Border Agent. * */ otBorderAgentState otBorderAgentGetState(otInstance *aInstance); /** - * This function gets the UDP port of Thread Border Agent service. + * Gets the UDP port of the Thread Border Agent service. * * @param[in] aInstance A pointer to an OpenThread instance. * diff --git a/util/third_party/openthread/include/openthread/border_router.h b/util/third_party/openthread/include/openthread/border_router.h index b09ab205ae..3b5aad862c 100644 --- a/util/third_party/openthread/include/openthread/border_router.h +++ b/util/third_party/openthread/include/openthread/border_router.h @@ -73,7 +73,7 @@ extern "C" { otError otBorderRoutingInit(otInstance *aInstance, uint32_t aInfraIfIndex, bool aInfraIfIsRunning); /** - * This method enables/disables the Border Routing Manager. + * Enables or disables the Border Routing Manager. * * @note The Border Routing Manager is disabled by default. * @@ -87,10 +87,36 @@ otError otBorderRoutingInit(otInstance *aInstance, uint32_t aInfraIfIndex, bool otError otBorderRoutingSetEnabled(otInstance *aInstance, bool aEnabled); /** - * This method returns the off-mesh-routable (OMR) prefix. + * This function gets the preference used when advertising Route Info Options (e.g., for discovered OMR prefixes) in + * Router Advertisement messages sent over the infrastructure link. * - * The randomly generated 64-bit prefix will be published - * in the Thread network if there isn't already an OMR prefix. + * @param[in] aInstance A pointer to an OpenThread instance. + * + * @returns The OMR prefix advertisement preference. + * + */ +otRoutePreference otBorderRoutingGetRouteInfoOptionPreference(otInstance *aInstance); + +/** + * This function sets the preference to use when advertising Route Info Options (e.g., for discovered OMR prefixes) in + * Router Advertisement messages sent over the infrastructure link. + * + * By default BR will use 'medium' preference level but this function allows the default value to be changed. As an + * example, it can be set to 'low' preference in the case where device is a temporary BR (a mobile BR or a + * battery-powered BR) to indicate that other BRs (if any) should be preferred over this BR on the infrastructure link. + * + * @param[in] aInstance A pointer to an OpenThread instance. + * @param[in] aPreference The route preference to use. + * + */ +void otBorderRoutingSetRouteInfoOptionPreference(otInstance *aInstance, otRoutePreference aPreference); + +/** + * Gets the Off-Mesh-Routable (OMR) Prefix, for example `fdfc:1ff5:1512:5622::/64`. + * + * An OMR Prefix is a randomly generated 64-bit prefix that's published in the + * Thread network if there isn't already an OMR prefix. This prefix can be reached + * from the local Wi-Fi or Ethernet network. * * @param[in] aInstance A pointer to an OpenThread instance. * @param[out] aPrefix A pointer to where the prefix will be output to. @@ -102,11 +128,10 @@ otError otBorderRoutingSetEnabled(otInstance *aInstance, bool aEnabled); otError otBorderRoutingGetOmrPrefix(otInstance *aInstance, otIp6Prefix *aPrefix); /** - * This method returns the on-link prefix for the adjacent infrastructure link. + * Gets the On-Link Prefix for the adjacent infrastructure link, for example `fd41:2650:a6f5:0::/64`. * - * The randomly generated 64-bit prefix will be advertised - * on the infrastructure link if there isn't already a usable - * on-link prefix being advertised on the link. + * An On-Link Prefix is a randomly generated 64-bit prefix that's advertised on the infrastructure + * link if there isn't already a usable on-link prefix being advertised on the link. * * @param[in] aInstance A pointer to an OpenThread instance. * @param[out] aPrefix A pointer to where the prefix will be output to. @@ -118,12 +143,11 @@ otError otBorderRoutingGetOmrPrefix(otInstance *aInstance, otIp6Prefix *aPrefix) otError otBorderRoutingGetOnLinkPrefix(otInstance *aInstance, otIp6Prefix *aPrefix); /** - * This function returns the local NAT64 prefix. + * Gets the local NAT64 Prefix of the Border Router. * - * This prefix might not be advertised in the Thread network. + * NAT64 Prefix might not be advertised in the Thread network. * - * This function is only available when `OPENTHREAD_CONFIG_BORDER_ROUTING_NAT64_ENABLE` - * is enabled. + * `OPENTHREAD_CONFIG_BORDER_ROUTING_NAT64_ENABLE` must be enabled. * * @param[in] aInstance A pointer to an OpenThread instance. * @param[out] aPrefix A pointer to where the prefix will be output to. diff --git a/util/third_party/openthread/include/openthread/coprocessor_rpc.h b/util/third_party/openthread/include/openthread/coprocessor_rpc.h index 5322719e89..9dc5ca7397 100644 --- a/util/third_party/openthread/include/openthread/coprocessor_rpc.h +++ b/util/third_party/openthread/include/openthread/coprocessor_rpc.h @@ -184,6 +184,8 @@ void otCRPCProcessHelp(void *aContext, uint8_t aArgsLength, char *aArgs[]); */ void otCRPCSetUserCommands(const otCliCommand *aUserCommands, uint8_t aLength, void *aContext); +char * otCRPCGetStaticOutputBuffer(void); +size_t otCRPCGetStaticOutputBufferSize(void); /** * @} * diff --git a/util/third_party/openthread/include/openthread/dataset.h b/util/third_party/openthread/include/openthread/dataset.h index a92f3a78c3..63e1e26adc 100644 --- a/util/third_party/openthread/include/openthread/dataset.h +++ b/util/third_party/openthread/include/openthread/dataset.h @@ -213,6 +213,17 @@ typedef struct otOperationalDatasetComponents bool mIsChannelMaskPresent : 1; ///< TRUE if Channel Mask is present, FALSE otherwise. } otOperationalDatasetComponents; +/** + * This structure represents a Thread Dataset timestamp component. + * + */ +typedef struct otTimestamp +{ + uint64_t mSeconds; + uint16_t mTicks; + bool mAuthoritative; +} otTimestamp; + /** * This structure represents an Active or Pending Operational Dataset. * @@ -221,8 +232,8 @@ typedef struct otOperationalDatasetComponents */ typedef struct otOperationalDataset { - uint64_t mActiveTimestamp; ///< Active Timestamp - uint64_t mPendingTimestamp; ///< Pending Timestamp + otTimestamp mActiveTimestamp; ///< Active Timestamp + otTimestamp mPendingTimestamp; ///< Pending Timestamp otNetworkKey mNetworkKey; ///< Network Key otNetworkName mNetworkName; ///< Network Name otExtendedPanId mExtendedPanId; ///< Extended PAN ID diff --git a/util/third_party/openthread/include/openthread/instance.h b/util/third_party/openthread/include/openthread/instance.h index ae935f154a..0b55850782 100644 --- a/util/third_party/openthread/include/openthread/instance.h +++ b/util/third_party/openthread/include/openthread/instance.h @@ -53,7 +53,7 @@ extern "C" { * @note This number versions both OpenThread platform and user APIs. * */ -#define OPENTHREAD_API_VERSION (216) +#define OPENTHREAD_API_VERSION (223) /** * @addtogroup api-instance diff --git a/util/third_party/openthread/include/openthread/ip6.h b/util/third_party/openthread/include/openthread/ip6.h index 00f20b098c..f624b426ee 100644 --- a/util/third_party/openthread/include/openthread/ip6.h +++ b/util/third_party/openthread/include/openthread/ip6.h @@ -781,6 +781,8 @@ typedef void (*otIp6RegisterMulticastListenersCallback)(void * aCon const otIp6Address *aFailedAddresses, uint8_t aFailedAddressNum); +#define OT_IP6_MAX_MLR_ADDRESSES 15 ///< Max number of IPv6 addresses supported by Multicast Listener Registration. + /** * This function registers Multicast Listeners to Primary Backbone Router. * diff --git a/util/third_party/openthread/include/openthread/joiner.h b/util/third_party/openthread/include/openthread/joiner.h index 8453c3ac7a..a1873f74cb 100644 --- a/util/third_party/openthread/include/openthread/joiner.h +++ b/util/third_party/openthread/include/openthread/joiner.h @@ -94,7 +94,7 @@ typedef struct otJoinerDiscerner typedef void (*otJoinerCallback)(otError aError, void *aContext); /** - * This function enables the Thread Joiner role. + * Enables the Thread Joiner role. * * @param[in] aInstance A pointer to an OpenThread instance. * @param[in] aPskd A pointer to the PSKd. @@ -123,7 +123,7 @@ otError otJoinerStart(otInstance * aInstance, void * aContext); /** - * This function disables the Thread Joiner role. + * Disables the Thread Joiner role. * * @param[in] aInstance A pointer to an OpenThread instance. * @@ -131,7 +131,7 @@ otError otJoinerStart(otInstance * aInstance, void otJoinerStop(otInstance *aInstance); /** - * This function returns the Joiner State. + * Gets the Joiner State. * * @param[in] aInstance A pointer to an OpenThread instance. * @@ -146,12 +146,12 @@ void otJoinerStop(otInstance *aInstance); otJoinerState otJoinerGetState(otInstance *aInstance); /** - * This function gets the Joiner ID. + * Gets the Joiner ID. * * If a Joiner Discerner is not set, Joiner ID is the first 64 bits of the result of computing SHA-256 over * factory-assigned IEEE EUI-64. Otherwise the Joiner ID is calculated from the Joiner Discerner value. * - * The Joiner ID is also used as the device's IEEE 802.15.4 Extended Address during commissioning process. + * The Joiner ID is also used as the device's IEEE 802.15.4 Extended Address during the commissioning process. * * @param[in] aInstance A pointer to the OpenThread instance. * @@ -161,13 +161,11 @@ otJoinerState otJoinerGetState(otInstance *aInstance); const otExtAddress *otJoinerGetId(otInstance *aInstance); /** - * This function sets the Joiner Discerner. + * Sets the Joiner Discerner. * - * The Joiner Discerner is used to calculate the Joiner ID used during commissioning/joining process. - * - * By default (when a discerner is not provided or set to NULL), Joiner ID is derived as first 64 bits of the result - * of computing SHA-256 over factory-assigned IEEE EUI-64. Note that this is the main behavior expected by Thread - * specification. + * The Joiner Discerner is used to calculate the Joiner ID during the Thread Commissioning process. For more + * information, refer to #otJoinerGetId. + * @note The Joiner Discerner takes the place of the Joiner EUI-64 during the joiner session of Thread Commissioning. * * @param[in] aInstance A pointer to the OpenThread instance. * @param[in] aDiscerner A pointer to a Joiner Discerner. If NULL clears any previously set discerner. @@ -180,7 +178,7 @@ const otExtAddress *otJoinerGetId(otInstance *aInstance); otError otJoinerSetDiscerner(otInstance *aInstance, otJoinerDiscerner *aDiscerner); /** - * This function gets the Joiner Discerner. + * Gets the Joiner Discerner. For more information, refer to #otJoinerSetDiscerner. * * @param[in] aInstance A pointer to the OpenThread instance. * diff --git a/util/third_party/openthread/include/openthread/netdata_publisher.h b/util/third_party/openthread/include/openthread/netdata_publisher.h index fa44686be8..2c38e15137 100644 --- a/util/third_party/openthread/include/openthread/netdata_publisher.h +++ b/util/third_party/openthread/include/openthread/netdata_publisher.h @@ -175,10 +175,10 @@ void otNetDataSetDnsSrpServicePublisherCallback(otInstance * void * aContext); /** - * This function unpublishes any previously added "DNS/SRP (Anycast or Unicast) Service" entry from the Thread Network + * Unpublishes any previously added DNS/SRP (Anycast or Unicast) Service entry from the Thread Network * Data. * - * This function requires the feature `OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE` to be enabled. + * `OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE` must be enabled. * * @param[in] aInstance A pointer to an OpenThread instance. * @@ -192,12 +192,18 @@ void otNetDataUnpublishDnsSrpService(otInstance *aInstance); * * Only stable entries can be published (i.e.,`aConfig.mStable` MUST be TRUE). * + * A subsequent call to this method will replace a previous request for the same prefix. In particular, if the new call + * only changes the flags (e.g., preference level) and the prefix is already added in the Network Data, the change to + * flags is immediately reflected in the Network Data. This ensures that existing entries in the Network Data are not + * abruptly removed. Note that a change in the preference level can potentially later cause the entry to be removed + * from the Network Data after determining there are other nodes that are publishing the same prefix with the same or + * higher preference. + * * @param[in] aInstance A pointer to an OpenThread instance. * @param[in] aConfig The on-mesh prefix config to publish (MUST NOT be NULL). * * @retval OT_ERROR_NONE The on-mesh prefix is published successfully. * @retval OT_ERROR_INVALID_ARGS The @p aConfig is not valid (bad prefix, invalid flag combinations, or not stable). - * @retval OT_ERROR_ALREADY An entry with the same prefix is already in the published list. * @retval OT_ERROR_NO_BUFS Could not allocate an entry for the new request. Publisher supports a limited number * of entries (shared between on-mesh prefix and external route) determined by config * `OPENTHREAD_CONFIG_NETDATA_PUBLISHER_MAX_PREFIX_ENTRIES`. @@ -213,12 +219,18 @@ otError otNetDataPublishOnMeshPrefix(otInstance *aInstance, const otBorderRouter * * Only stable entries can be published (i.e.,`aConfig.mStable` MUST be TRUE). * + * A subsequent call to this method will replace a previous request for the same prefix. In particular, if the new call + * only changes the flags (e.g., preference level) and the prefix is already added in the Network Data, the change to + * flags is immediately reflected in the Network Data. This ensures that existing entries in the Network Data are not + * abruptly removed. Note that a change in the preference level can potentially later cause the entry to be removed + * from the Network Data after determining there are other nodes that are publishing the same prefix with the same or + * higher preference. + * * @param[in] aInstance A pointer to an OpenThread instance. * @param[in] aConfig The external route config to publish (MUST NOT be NULL). * * @retval OT_ERROR_NONE The external route is published successfully. * @retval OT_ERROR_INVALID_ARGS The @p aConfig is not valid (bad prefix, invalid flag combinations, or not stable). - * @retval OT_ERROR_ALREADY An entry with the same prefix is already in the published list. * @retval OT_ERROR_NO_BUFS Could not allocate an entry for the new request. Publisher supports a limited number * of entries (shared between on-mesh prefix and external route) determined by config * `OPENTHREAD_CONFIG_NETDATA_PUBLISHER_MAX_PREFIX_ENTRIES`. @@ -258,9 +270,9 @@ void otNetDataSetPrefixPublisherCallback(otInstance * aInsta void * aContext); /** - * This function unpublishes a previously published prefix (on-mesh or external route). + * Unpublishes a previously published On-Mesh or External Route Prefix. * - * This function requires the feature `OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE` to be enabled. + * `OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE` must be enabled. * * @param[in] aInstance A pointer to an OpenThread instance. * @param[in] aPrefix The prefix to unpublish (MUST NOT be NULL). diff --git a/util/third_party/openthread/include/openthread/platform/radio.h b/util/third_party/openthread/include/openthread/platform/radio.h index 8ccad64d26..c08e5b99c2 100644 --- a/util/third_party/openthread/include/openthread/platform/radio.h +++ b/util/third_party/openthread/include/openthread/platform/radio.h @@ -444,7 +444,7 @@ const char *otPlatRadioGetVersionString(otInstance *aInstance); int8_t otPlatRadioGetReceiveSensitivity(otInstance *aInstance); /** - * Get the factory-assigned IEEE EUI-64 for this interface. + * Gets the factory-assigned IEEE EUI-64 for this interface. * * @param[in] aInstance The OpenThread instance structure. * @param[out] aIeeeEui64 A pointer to the factory-assigned IEEE EUI-64. @@ -1143,6 +1143,33 @@ otError otPlatRadioConfigureEnhAckProbing(otInstance * aInstance, otShortAddress aShortAddress, const otExtAddress *aExtAddress); + +#if OPENTHREAD_CONFIG_DIAG_ENABLE + +/** + * Enable transmitting stream random character mode. + * + */ +otError otPlatDiagTxStreamRandom(void); + +/** + * Enable transmitting stream unmodulated tone mode. + * + */ +otError otPlatDiagTxStreamTone(void); + +/** + * Disable transmitting stream mode. + * + */ +otError otPlatDiagTxStreamStop(void); + +otError otPlatDiagTxStreamAddrMatch(uint8_t enable); +otError otPlatDiagTxStreamAutoAck(uint8_t autoAckEnabled); + +#endif // #if OPENTHREAD_CONFIG_DIAG_ENABLE + + /** * @} * diff --git a/util/third_party/openthread/include/openthread/srp_client.h b/util/third_party/openthread/include/openthread/srp_client.h index 1dc0c9e3e1..bb291d414d 100644 --- a/util/third_party/openthread/include/openthread/srp_client.h +++ b/util/third_party/openthread/include/openthread/srp_client.h @@ -75,8 +75,9 @@ typedef enum typedef struct otSrpClientHostInfo { const char * mName; ///< Host name (label) string (NULL if not yet set). - const otIp6Address * mAddresses; ///< Pointer to an array of host IPv6 addresses (NULL if not yet set). + const otIp6Address * mAddresses; ///< Array of host IPv6 addresses (NULL if not set or auto address is enabled). uint8_t mNumAddresses; ///< Number of IPv6 addresses in `mAddresses` array. + bool mAutoAddress; ///< Indicates whether auto address mode is enabled or not. otSrpClientItemState mState; ///< Host info state. } otSrpClientHostInfo; @@ -428,6 +429,27 @@ const otSrpClientHostInfo *otSrpClientGetHostInfo(otInstance *aInstance); */ otError otSrpClientSetHostName(otInstance *aInstance, const char *aName); +/** + * This function enables auto host address mode. + * + * When enabled host IPv6 addresses are automatically set by SRP client using all the unicast addresses on Thread netif + * excluding all link-local and mesh-local addresses. If there is no valid address, then Mesh Local EID address is + * added. The SRP client will automatically re-register when/if addresses on Thread netif are updated (new addresses + * are added or existing addresses are removed). + * + * The auto host address mode can be enabled before start or during operation of SRP client except when the host info + * is being removed (client is busy handling a remove request from an call to `otSrpClientRemoveHostAndServices()` and + * host info still being in either `STATE_TO_REMOVE` or `STATE_REMOVING` states). + * + * After auto host address mode is enabled, it can be disabled by a call to `otSrpClientSetHostAddresses()` which + * then explicitly sets the host addresses. + * + * @retval OT_ERROR_NONE Successfully enabled auto host address mode. + * @retval OT_ERROR_INVALID_STATE Host is being removed and therefore cannot enable auto host address mode. + * + */ +otError otSrpClientEnableAutoHostAddress(otInstance *aInstance); + /** * This function sets/updates the list of host IPv6 address. * @@ -442,6 +464,9 @@ otError otSrpClientSetHostName(otInstance *aInstance, const char *aName); * After a successful call to this function, `otSrpClientCallback` will be called to report the status of the address * registration with SRP server. * + * Calling this function disables auto host address mode if it was previously enabled from a successful call to + * `otSrpClientEnableAutoHostAddress()`. + * * @param[in] aInstance A pointer to the OpenThread instance. * @param[in] aIp6Addresses A pointer to the an array containing the host IPv6 addresses. * @param[in] aNumAddresses The number of addresses in the @p aIp6Addresses array. diff --git a/util/third_party/openthread/include/openthread/thread.h b/util/third_party/openthread/include/openthread/thread.h index fe829003cb..04cb747f11 100644 --- a/util/third_party/openthread/include/openthread/thread.h +++ b/util/third_party/openthread/include/openthread/thread.h @@ -194,11 +194,22 @@ typedef struct otThreadParentResponseInfo bool mIsAttached; ///< Is the node receiving parent response attached } otThreadParentResponseInfo; +/** + * This callback informs the application that the detaching process has finished. + * + * @param[in] aContext A pointer to application-specific context. + * + */ +typedef void (*otDetachGracefullyCallback)(void *aContext); + /** * This function starts Thread protocol operation. * * The interface must be up when calling this function. * + * Calling this function with @p aEnabled set to FALSE stops any ongoing processes of detaching started by + * otThreadDetachGracefully(). Its callback will be called. + * * @param[in] aInstance A pointer to an OpenThread instance. * @param[in] aEnabled TRUE if Thread is enabled, FALSE otherwise. * @@ -1009,6 +1020,21 @@ otError otThreadSendProactiveBackboneNotification(otInstance * aIns otIp6InterfaceIdentifier *aMlIid, uint32_t aTimeSinceLastTransaction); +/** + * This function notifies other nodes in the network (if any) and then stops Thread protocol operation. + * + * It sends an Address Release if it's a router, or sets its child timeout to 0 if it's a child. + * + * @param[in] aInstance A pointer to an OpenThread instance. + * @param[in] aCallback A pointer to a function that is called upon finishing detaching. + * @param[in] aContext A pointer to callback application-specific context. + * + * @retval OT_ERROR_NONE Successfully started detaching. + * @retval OT_ERROR_BUSY Detaching is already in progress. + * + */ +otError otThreadDetachGracefully(otInstance *aInstance, otDetachGracefullyCallback aCallback, void *aContext); + /** * @} * diff --git a/util/third_party/openthread/script/check-arm-build-autotools b/util/third_party/openthread/script/check-arm-build-autotools index 4390ff8dae..e994c20252 100644 --- a/util/third_party/openthread/script/check-arm-build-autotools +++ b/util/third_party/openthread/script/check-arm-build-autotools @@ -43,7 +43,7 @@ build_cc2538() "DNS_CLIENT=1" "JOINER=1" "SLAAC=1" - # cc2538 does not have enough resources to support Thread 1.2 + # cc2538 does not have enough resources to support Thread 1.3 "THREAD_VERSION=1.1" ) diff --git a/util/third_party/openthread/script/check-arm-build-cmake b/util/third_party/openthread/script/check-arm-build-cmake index d8210ab1fd..3ee62b06e6 100644 --- a/util/third_party/openthread/script/check-arm-build-cmake +++ b/util/third_party/openthread/script/check-arm-build-cmake @@ -51,7 +51,7 @@ reset_source() build_cc2538() { local options=( - # cc2538 does not have enough resources to support Thread 1.2 + # cc2538 does not have enough resources to support Thread 1.3 "-DOT_THREAD_VERSION=1.1" ) diff --git a/util/third_party/openthread/script/check-gn-build b/util/third_party/openthread/script/check-gn-build index 2a02c3ffe1..68b17a7b75 100644 --- a/util/third_party/openthread/script/check-gn-build +++ b/util/third_party/openthread/script/check-gn-build @@ -43,10 +43,10 @@ main() ninja -C gn-out test -f gn-out/obj/src/core/libopenthread-ftd.a - # Check GN build for OT1.2 + # Check GN build for OT1.3 rm gn-out -r || true mkdir gn-out - echo 'openthread_config_thread_version = "1.2"' >gn-out/args.gn + echo 'openthread_config_thread_version = "1.3"' >gn-out/args.gn gn gen --check gn-out gn args gn-out --list ninja -C gn-out diff --git a/util/third_party/openthread/script/check-ncp-rcp-migrate b/util/third_party/openthread/script/check-ncp-rcp-migrate index 1001ccc429..ce38eb527b 100644 --- a/util/third_party/openthread/script/check-ncp-rcp-migrate +++ b/util/third_party/openthread/script/check-ncp-rcp-migrate @@ -83,7 +83,7 @@ send "ifconfig up\r\n" expect "Done" send "thread start\r\n" expect "Done" -sleep 5 +sleep 10 send "state\r\n" expect "leader" expect "Done" diff --git a/util/third_party/openthread/script/check-posix-pty b/util/third_party/openthread/script/check-posix-pty index 4aad5649f1..716d154d43 100644 --- a/util/third_party/openthread/script/check-posix-pty +++ b/util/third_party/openthread/script/check-posix-pty @@ -182,7 +182,7 @@ send "ifconfig up\r\n" expect "Done" send "thread start\r\n" expect "Done" -sleep 5 +sleep 10 send "state\r\n" expect "leader" expect "Done" @@ -207,7 +207,7 @@ EOF sleep 5 # wait until the node becomes leader - timeout_run 5 wait_for_leader + timeout_run 10 wait_for_leader # wait coap service start sleep 5 diff --git a/util/third_party/openthread/script/check-simulation-build-autotools b/util/third_party/openthread/script/check-simulation-build-autotools index 086f2688c8..528419d475 100644 --- a/util/third_party/openthread/script/check-simulation-build-autotools +++ b/util/third_party/openthread/script/check-simulation-build-autotools @@ -93,7 +93,7 @@ build_all_features() "-DOPENTHREAD_CONFIG_MAC_OUTGOING_BEACON_PAYLOAD_ENABLE=1" ) - local options_1_2=( + local options_1_3=( "-DOPENTHREAD_CONFIG_BACKBONE_ROUTER_ENABLE=1" "-DOPENTHREAD_CONFIG_MAC_CSL_RECEIVER_ENABLE=1" "-DOPENTHREAD_CONFIG_DUA_ENABLE=1" @@ -101,24 +101,24 @@ build_all_features() ) # Build Thread 1.1 with full features and no log - export CPPFLAGS="${options[*]} -DOPENTHREAD_CONFIG_LOG_OUTPUT=OT_LOG_OUTPUT_NONE" + export CPPFLAGS="${options[*]}" reset_source - make -f examples/Makefile-simulation THREAD_VERSION=1.1 + make -f examples/Makefile-simulation THREAD_VERSION=1.1 LOG_OUTPUT=NONE # Build Thread 1.1 with full features and full logs export CPPFLAGS="${options[*]}" reset_source make -f examples/Makefile-simulation THREAD_VERSION=1.1 FULL_LOGS=1 - # Build Thread 1.2 with full features and logs - export CPPFLAGS="${options[*]} ${options_1_2[*]} -DOPENTHREAD_CONFIG_LOG_OUTPUT=OT_LOG_OUTPUT_NONE" + # Build Thread 1.3 with full features and logs + export CPPFLAGS="${options[*]} ${options_1_3[*]}" reset_source - make -f examples/Makefile-simulation THREAD_VERSION=1.2 + make -f examples/Makefile-simulation THREAD_VERSION=1.3 LOG_OUTPUT=NONE - # Build Thread 1.2 with full features and full logs - export CPPFLAGS="${options[*]} ${options_1_2[*]}" + # Build Thread 1.3 with full features and full logs + export CPPFLAGS="${options[*]} ${options_1_3[*]}" reset_source - make -f examples/Makefile-simulation THREAD_VERSION=1.2 FULL_LOGS=1 + make -f examples/Makefile-simulation THREAD_VERSION=1.3 FULL_LOGS=1 # Build Thread 1.1 with ASSERT disabled export CPPFLAGS="${options[*]} -DOPENTHREAD_CONFIG_ASSERT_ENABLE=0" diff --git a/util/third_party/openthread/script/check-simulation-build-cmake b/util/third_party/openthread/script/check-simulation-build-cmake index e9a3b4549b..f296ab1ec8 100644 --- a/util/third_party/openthread/script/check-simulation-build-cmake +++ b/util/third_party/openthread/script/check-simulation-build-cmake @@ -53,7 +53,7 @@ build_all_features() -DOT_FTD=OFF \ -DOT_MTD=OFF - # Thread 1.2 options + # Thread 1.3 options local options=( "-DOT_BACKBONE_ROUTER=ON" "-DOT_BORDER_ROUTING=ON" @@ -61,18 +61,18 @@ build_all_features() "-DOT_MLR=ON" "-DOT_OTNS=ON" "-DOT_SIMULATION_VIRTUAL_TIME=ON" - "-DOT_THREAD_VERSION=1.2" + "-DOT_THREAD_VERSION=1.3" ) - # Build Thread 1.2 with full features + # Build Thread 1.3 with full features reset_source "$(dirname "$0")"/cmake-build simulation "${options[@]}" -DOT_DUA=ON - # Build Thread 1.2 Backbone Router without DUA ND Proxying + # Build Thread 1.3 Backbone Router without DUA ND Proxying reset_source "$(dirname "$0")"/cmake-build simulation "${options[@]}" -DOT_BACKBONE_ROUTER_DUA_NDPROXYING=OFF - # Build Thread 1.2 Backbone Router without Multicast Routing + # Build Thread 1.3 Backbone Router without Multicast Routing reset_source "$(dirname "$0")"/cmake-build simulation "${options[@]}" -DOT_BACKBONE_ROUTER_MULTICAST_ROUTING=OFF @@ -82,11 +82,11 @@ build_all_features() -DOT_THREAD_VERSION=1.1 \ -DOT_VENDOR_EXTENSION=../../src/core/common/extension_example.cpp - # Build Thread 1.2 with no additional features + # Build Thread 1.3 with no additional features reset_source - "$(dirname "$0")"/cmake-build simulation -DOT_THREAD_VERSION=1.2 + "$(dirname "$0")"/cmake-build simulation -DOT_THREAD_VERSION=1.3 - # Build Thread 1.2 with full features and OT_ASSERT=OFF + # Build Thread 1.3 with full features and OT_ASSERT=OFF reset_source "$(dirname "$0")"/cmake-build simulation "${options[@]}" -DOT_DUA=ON -DOT_ASSERT=OFF diff --git a/util/third_party/openthread/script/check-size b/util/third_party/openthread/script/check-size index 2163d05765..e81c0bfafa 100644 --- a/util/third_party/openthread/script/check-size +++ b/util/third_party/openthread/script/check-size @@ -151,9 +151,9 @@ size_nrf52840_version() local thread_version=$1 - if [[ ${thread_version} == "1.2" ]]; then + if [[ ${thread_version} != "1.1" ]]; then options+=( - "-DOT_THREAD_VERSION=1.2" + "-DOT_THREAD_VERSION=1.3" "-DOT_BACKBONE_ROUTER=ON" "-DOT_DUA=ON" "-DOT_MLR=ON" @@ -243,7 +243,7 @@ size_nrf52840() "${reporter}" init OpenThread size_nrf52840_version 1.1 - size_nrf52840_version 1.2 + size_nrf52840_version 1.3 "${reporter}" post } diff --git a/util/third_party/openthread/script/make-pretty b/util/third_party/openthread/script/make-pretty index 70984de7c0..22201c3f1a 100644 --- a/util/third_party/openthread/script/make-pretty +++ b/util/third_party/openthread/script/make-pretty @@ -121,7 +121,7 @@ readonly OT_CLANG_TIDY_BUILD_OPTS=( '-DOT_SNTP_CLIENT=ON' '-DOT_SRP_CLIENT=ON' '-DOT_SRP_SERVER=ON' - '-DOT_THREAD_VERSION=1.2' + '-DOT_THREAD_VERSION=1.3' '-DOT_TREL=ON' '-DOT_COVERAGE=ON' '-DOT_LOG_LEVEL_DYNAMIC=ON' @@ -177,7 +177,7 @@ do_clang_tidy_fix() (mkdir -p ./build/cmake-tidy \ && cd ./build/cmake-tidy \ - && THREAD_VERSION=1.2 cmake "${OT_CLANG_TIDY_BUILD_OPTS[@]}" ../.. \ + && THREAD_VERSION=1.3 cmake "${OT_CLANG_TIDY_BUILD_OPTS[@]}" ../.. \ && ../../script/clang-tidy -header-filter='.*' -checks="${OT_CLANG_TIDY_CHECKS}" -j"$OT_BUILD_JOBS" "${OT_CLANG_TIDY_FIX_DIRS[@]}" -fix) } @@ -190,7 +190,7 @@ do_clang_tidy_check() ( mkdir -p ./build/cmake-tidy \ && cd ./build/cmake-tidy \ - && THREAD_VERSION=1.2 cmake "${OT_CLANG_TIDY_BUILD_OPTS[@]}" ../.. \ + && THREAD_VERSION=1.3 cmake "${OT_CLANG_TIDY_BUILD_OPTS[@]}" ../.. \ && ../../script/clang-tidy -header-filter='.*' -checks="${OT_CLANG_TIDY_CHECKS}" -j"$OT_BUILD_JOBS" "${OT_CLANG_TIDY_FIX_DIRS[@]}" \ | grep -v -E "third_party" >output.txt if grep -q "warning: \|error: " output.txt; then diff --git a/util/third_party/openthread/script/test b/util/third_party/openthread/script/test index 2c5226145c..631013ad29 100644 --- a/util/third_party/openthread/script/test +++ b/util/third_party/openthread/script/test @@ -42,7 +42,7 @@ readonly OT_COLOR_NONE='\033[0m' readonly OT_NODE_TYPE="${OT_NODE_TYPE:-cli}" readonly OT_NATIVE_IP="${OT_NATIVE_IP:-0}" -readonly THREAD_VERSION="${THREAD_VERSION:-1.2}" +readonly THREAD_VERSION="${THREAD_VERSION:-1.3}" readonly INTER_OP="${INTER_OP:-0}" readonly VERBOSE="${VERBOSE:-0}" readonly BORDER_ROUTING="${BORDER_ROUTING:-1}" @@ -81,7 +81,7 @@ build_simulation() options+=("-DOT_FULL_LOGS=ON") fi - if [[ ${version} == "1.2" ]]; then + if [[ ${version} != "1.1" ]]; then options+=("-DOT_DUA=ON") options+=("-DOT_MLR=ON") fi @@ -90,7 +90,7 @@ build_simulation() options+=("-DOT_SIMULATION_VIRTUAL_TIME=ON") fi - if [[ ${version} == "1.2" ]]; then + if [[ ${version} != "1.1" ]]; then options+=("-DOT_CSL_RECEIVER=ON") options+=("-DOT_LINK_METRICS_INITIATOR=ON") options+=("-DOT_LINK_METRICS_SUBJECT=ON") @@ -106,7 +106,7 @@ build_simulation() OT_CMAKE_NINJA_TARGET=ot-rcp OT_CMAKE_BUILD_DIR="${OT_BUILDDIR}/openthread-simulation-${version}" "${OT_SRCDIR}"/script/cmake-build simulation "${options[@]}" "-DOT_SIMULATION_VIRTUAL_TIME_UART=ON" fi - if [[ ${version} == "1.2" && ${INTER_OP_BBR} == 1 ]]; then + if [[ ${version} != "1.1" && ${INTER_OP_BBR} == 1 ]]; then options+=("-DOT_BACKBONE_ROUTER=ON") @@ -124,7 +124,7 @@ build_posix() local version="$1" local options=("-DOT_MESSAGE_USE_HEAP=ON" "-DOT_THREAD_VERSION=${version}" "-DBUILD_TESTING=ON") - if [[ ${version} == "1.2" ]]; then + if [[ ${version} != "1.1" ]]; then options+=("-DOT_DUA=ON") options+=("-DOT_MLR=ON") fi @@ -147,7 +147,7 @@ build_posix() OT_CMAKE_BUILD_DIR="${OT_BUILDDIR}/openthread-posix-${version}" "${OT_SRCDIR}"/script/cmake-build posix "${options[@]}" - if [[ ${version} == "1.2" && ${INTER_OP_BBR} == 1 ]]; then + if [[ ${version} != "1.1" && ${INTER_OP_BBR} == 1 ]]; then options+=("-DOT_BACKBONE_ROUTER=ON") @@ -170,7 +170,7 @@ do_build() { build_for_one_version "${THREAD_VERSION}" - if [[ ${THREAD_VERSION} == "1.2" && ${INTER_OP} == "1" ]]; then + if [[ ${THREAD_VERSION} != "1.1" && ${INTER_OP} == "1" ]]; then build_for_one_version 1.1 fi } @@ -201,8 +201,8 @@ do_unit() { do_unit_version "${THREAD_VERSION}" - if [[ ${THREAD_VERSION} == "1.2" && ${INTER_OP_BBR} == 1 ]]; then - do_unit_version "1.2-bbr" + if [[ ${THREAD_VERSION} != "1.1" && ${INTER_OP_BBR} == 1 ]]; then + do_unit_version "1.3-bbr" fi } @@ -220,8 +220,8 @@ do_cert() ;; esac - if [[ ${THREAD_VERSION} == "1.2" ]]; then - export top_builddir_1_2_bbr="${OT_BUILDDIR}/openthread-simulation-1.2-bbr" + if [[ ${THREAD_VERSION} != "1.1" ]]; then + export top_builddir_1_3_bbr="${OT_BUILDDIR}/openthread-simulation-1.3-bbr" if [[ ${INTER_OP} == "1" ]]; then export top_builddir_1_1="${OT_BUILDDIR}/openthread-simulation-1.1" fi @@ -238,8 +238,8 @@ do_cert_suite() { export top_builddir="${OT_BUILDDIR}/openthread-simulation-${THREAD_VERSION}" - if [[ ${THREAD_VERSION} == "1.2" ]]; then - export top_builddir_1_2_bbr="${OT_BUILDDIR}/openthread-simulation-1.2-bbr" + if [[ ${THREAD_VERSION} != "1.1" ]]; then + export top_builddir_1_3_bbr="${OT_BUILDDIR}/openthread-simulation-1.3-bbr" if [[ ${INTER_OP} == "1" ]]; then export top_builddir_1_1="${OT_BUILDDIR}/openthread-simulation-1.1" fi @@ -386,7 +386,7 @@ do_expect() test_patterns=(-name 'tun-*.exp') else test_patterns=(-name 'posix-*.exp' -o -name 'cli-*.exp') - if [[ ${THREAD_VERSION} == "1.2" ]]; then + if [[ ${THREAD_VERSION} != "1.1" ]]; then test_patterns+=(-o -name 'v1_2-*.exp') fi fi @@ -421,9 +421,9 @@ ENVIRONMENTS: VERBOSE 1 to build or test verbosely. The default is 0. VIRTUAL_TIME 1 for virtual time, otherwise real time. The default value is 0 when running expect tests, otherwise default value is 1. - THREAD_VERSION 1.1 for Thread 1.1 stack, 1.2 for Thread 1.2 stack. The default is 1.2. - INTER_OP 1 to build 1.1 together. Only works when THREAD_VERSION is 1.2. The default is 0. - INTER_OP_BBR 1 to build bbr version together. Only works when THREAD_VERSION is 1.2. The default is 1. + THREAD_VERSION 1.1 for Thread 1.1 stack, 1.3 for Thread 1.3 stack. The default is 1.3. + INTER_OP 1 to build 1.1 together. Only works when THREAD_VERSION is 1.3. The default is 0. + INTER_OP_BBR 1 to build bbr version together. Only works when THREAD_VERSION is 1.3. The default is 1. COMMANDS: clean Clean built files to prepare for new build. @@ -455,7 +455,7 @@ EXAMPLES: THREAD_VERSION=1.1 VIRTUAL_TIME=0 $0 clean build cert tests/scripts/thread-cert/Cert_5_1_01_RouterAttach.py THREAD_VERSION=1.1 VIRTUAL_TIME=0 $0 cert tests/scripts/thread-cert/Cert_5_1_02_ChildAddressTimeout.py - # Test Thread 1.2 with real time, use 'INTER_OP=1' when the case needs both versions. + # Test Thread 1.3 with real time, use 'INTER_OP=1' when the case needs both versions. VIRTUAL_TIME=0 $0 clean build cert tests/scripts/thread-cert/v1_2_test_enhanced_keep_alive.py INTER_OP=1 VIRTUAL_TIME=0 $0 clean build cert tests/scripts/thread-cert/v1_2_router_5_1_1.py INTER_OP=1 VIRTUAL_TIME=0 $0 clean build cert_suite tests/scripts/thread-cert/v1_2_* @@ -559,10 +559,10 @@ envsetup() export RADIO_DEVICE="${OT_BUILDDIR}/openthread-simulation-${THREAD_VERSION}/examples/apps/ncp/ot-rcp" export OT_CLI_PATH="${OT_BUILDDIR}/openthread-posix-${THREAD_VERSION}/src/posix/ot-cli" - if [[ ${THREAD_VERSION} == "1.2" ]]; then + if [[ ${THREAD_VERSION} != "1.1" ]]; then export RADIO_DEVICE_1_1="${OT_BUILDDIR}/openthread-simulation-1.1/examples/apps/ncp/ot-rcp" export OT_CLI_PATH_1_1="${OT_BUILDDIR}/openthread-posix-1.1/src/posix/ot-cli" - export OT_CLI_PATH_1_2_BBR="${OT_BUILDDIR}/openthread-posix-1.2-bbr/src/posix/ot-cli" + export OT_CLI_PATH_BBR="${OT_BUILDDIR}/openthread-posix-1.3-bbr/src/posix/ot-cli" fi fi @@ -606,7 +606,7 @@ main() fi [[ ${VIRTUAL_TIME} == 1 ]] && echo "Using virtual time" || echo "Using real time" - [[ ${THREAD_VERSION} == "1.2" ]] && echo "Using Thread 1.2 stack" || echo "Using Thread 1.1 stack" + [[ ${THREAD_VERSION} != "1.1" ]] && echo "Using Thread 1.3 stack" || echo "Using Thread 1.1 stack" while [[ $# != 0 ]]; do case "$1" in diff --git a/util/third_party/openthread/src/cli/README.md b/util/third_party/openthread/src/cli/README.md index 1dd92e45ac..c088da4749 100644 --- a/util/third_party/openthread/src/cli/README.md +++ b/util/third_party/openthread/src/cli/README.md @@ -62,7 +62,6 @@ Done - [leaderdata](#leaderdata) - [leaderweight](#leaderweight) - [linkmetrics](#linkmetrics-mgmt-ipaddr-enhanced-ack-clear) -- [linkquality](#linkquality-extaddr) - [locate](#locate) - [log](#log-filename-filename) - [mac](#mac-retries-direct) @@ -395,6 +394,25 @@ fd14:1078:b3d5:b0b0:0:0::/96 Done ``` +### br rioprf + +Get the preference used when advertising Route Info Options (e.g., for discovered OMR prefixes) in emitted Router Advertisement message. + +```bash +> br rioprf +med +Done +``` + +### br rioprf \ + +Set the preference (which may be 'high', 'med', or 'low') to use when advertising Route Info Options (e.g., for discovered OMR prefixes) in emitted Router Advertisement message. + +```bash +> br rioprf low +Done +``` + ### bufferinfo Show the current message buffer information. @@ -1627,25 +1645,6 @@ Done - RSSI: -18 (dBm) (Exponential Moving Average) ``` -### linkquality \ - -Get the link quality on the link to a given extended address. - -```bash -> linkquality 36c1dd7a4f5201ff -3 -Done -``` - -### linkquality \ \ - -Set the link quality on the link to a given extended address. - -```bash -> linkquality 36c1dd7a4f5201ff 3 -Done -``` - ### locate Gets the current state (`In Progress` or `Idle`) of anycast locator. diff --git a/util/third_party/openthread/src/cli/README_DATASET.md b/util/third_party/openthread/src/cli/README_DATASET.md index 1043bbaa00..87cd4d21c0 100644 --- a/util/third_party/openthread/src/cli/README_DATASET.md +++ b/util/third_party/openthread/src/cli/README_DATASET.md @@ -196,7 +196,7 @@ Done Usage: `dataset activetimestamp [timestamp]` -Get active timestamp. +Get active timestamp seconds. ```bash > dataset activetimestamp @@ -204,7 +204,7 @@ Get active timestamp. Done ``` -Set active timestamp. +Set active timestamp seconds. ```bash > dataset activetimestamp 123456789 @@ -457,7 +457,7 @@ Done Usage: `dataset pendingtimestamp [timestamp]` -Get pending timestamp. +Get pending timestamp seconds. ```bash > dataset pendingtimestamp @@ -465,7 +465,7 @@ Get pending timestamp. Done ``` -Set pending timestamp. +Set pending timestamp seconds. ```bash > dataset pendingtimestamp 123456789 diff --git a/util/third_party/openthread/src/cli/README_SRP_CLIENT.md b/util/third_party/openthread/src/cli/README_SRP_CLIENT.md index ab5dcdb772..ae48fbf1e4 100644 --- a/util/third_party/openthread/src/cli/README_SRP_CLIENT.md +++ b/util/third_party/openthread/src/cli/README_SRP_CLIENT.md @@ -139,6 +139,14 @@ name:"dev4312", state:Registered, addrs:[fd00:0:0:0:0:0:0:1234, fd00:0:0:0:0:0:0 Done ``` +When auto host address mode is enabled. + +```bash +srp client host +name:"dev1234", state:Registered, addrs:auto +Done +``` + ### host name Usage: `srp client host name [name]` @@ -160,9 +168,17 @@ Done ### host address -Usage : `srp client host address [
...]` +Usage : `srp client host address [auto |
...]` + +Indicate auto address mode is enabled. + +```bash +> srp client host address +auto +Done +``` -Get the list of host addresses. +Get the list of host addresses (when auto host address is not enabled). ```bash > srp client host address @@ -171,7 +187,14 @@ fd00:0:0:0:0:0:0:beef Done ``` -Set the list of host addresses (can be set while client is running to update the host addresses) +Enable auto host address mode. When enabled client will automatically use all Thread netif unicast addresses excluding all link-local and mesh-local addresses. If there is no valid address, then Mesh Local EID address is added. SRP client will automatically re-register if/when addresses on Thread netif get changed (e.g., new address is added or existing address is removed). + +```bash +> srp client host address auto +Done +``` + +Explicitly set the list of host addresses (can be set while client is running to update the host addresses), also disabled auto host address mode. ```bash > srp client host address fd00::cafe diff --git a/util/third_party/openthread/src/cli/cli.cpp b/util/third_party/openthread/src/cli/cli.cpp index f5bc298303..f6b06e32b8 100644 --- a/util/third_party/openthread/src/cli/cli.cpp +++ b/util/third_party/openthread/src/cli/cli.cpp @@ -410,6 +410,55 @@ otError Interpreter::ParsePingInterval(const Arg &aArg, uint32_t &aInterval) #endif // OPENTHREAD_CONFIG_PING_SENDER_ENABLE +otError Interpreter::ParsePreference(const Arg &aArg, otRoutePreference &aPreference) +{ + otError error = OT_ERROR_NONE; + + if (aArg == "high") + { + aPreference = OT_ROUTE_PREFERENCE_HIGH; + } + else if (aArg == "med") + { + aPreference = OT_ROUTE_PREFERENCE_MED; + } + else if (aArg == "low") + { + aPreference = OT_ROUTE_PREFERENCE_LOW; + } + else + { + error = OT_ERROR_INVALID_ARGS; + } + + return error; +} + +const char *Interpreter::PreferenceToString(signed int aPreference) +{ + const char *str = ""; + + switch (aPreference) + { + case OT_ROUTE_PREFERENCE_LOW: + str = "low"; + break; + + case OT_ROUTE_PREFERENCE_MED: + str = "med"; + break; + + case OT_ROUTE_PREFERENCE_HIGH: + str = "high"; + break; + + default: + break; + } + + return str; +} + #if OPENTHREAD_CONFIG_HISTORY_TRACKER_ENABLE template <> otError Interpreter::Process(Arg aArgs[]) { @@ -422,10 +471,30 @@ template <> otError Interpreter::Process(Arg aArgs[]) { otError error = OT_ERROR_NONE; + /** + * @cli ba port + * @code + * ba port + * 49153 + * Done + * @endcode + * @par api_copy + * #otBorderAgentGetUdpPort + */ if (aArgs[0] == "port") { OutputLine("%hu", otBorderAgentGetUdpPort(GetInstancePtr())); } + /** + * @cli ba state + * @code + * ba state + * Started + * Done + * @endcode + * @par api_copy + * #otBorderAgentGetState + */ else if (aArgs[0] == "state") { static const char *const kStateStrings[] = { @@ -455,10 +524,33 @@ template <> otError Interpreter::Process(Arg aArgs[]) otError error = OT_ERROR_NONE; bool enable; + /** + * @cli br (enable,disable) + * @code + * br enable + * Done + * @endcode + * @code + * br disable + * Done + * @endcode + * @par api_copy + * #otBorderRoutingSetEnabled + */ if (ParseEnableOrDisable(aArgs[0], enable) == OT_ERROR_NONE) { SuccessOrExit(error = otBorderRoutingSetEnabled(GetInstancePtr(), enable)); } + /** + * @cli br omrprefix + * @code + * br omrprefix + * fdfc:1ff5:1512:5622::/64 + * Done + * @endcode + * @par api_copy + * #otBorderRoutingGetOmrPrefix + */ else if (aArgs[0] == "omrprefix") { otIp6Prefix omrPrefix; @@ -466,6 +558,16 @@ template <> otError Interpreter::Process(Arg aArgs[]) SuccessOrExit(error = otBorderRoutingGetOmrPrefix(GetInstancePtr(), &omrPrefix)); OutputIp6PrefixLine(omrPrefix); } + /** + * @cli br onlinkprefix + * @code + * br onlinkprefix + * fd41:2650:a6f5:0::/64 + * Done + * @endcode + * @par api_copy + * #otBorderRoutingGetOnLinkPrefix + */ else if (aArgs[0] == "onlinkprefix") { otIp6Prefix onLinkPrefix; @@ -474,6 +576,16 @@ template <> otError Interpreter::Process(Arg aArgs[]) OutputIp6PrefixLine(onLinkPrefix); } #if OPENTHREAD_CONFIG_BORDER_ROUTING_NAT64_ENABLE + /** + * @cli br nat64prefix + * @code + * br nat64prefix + * fd14:1078:b3d5:b0b0:0:0::/96 + * Done + * @endcode + * @par api_copy + * #otBorderRoutingGetNat64Prefix + */ else if (aArgs[0] == "nat64prefix") { otIp6Prefix nat64Prefix; @@ -482,6 +594,40 @@ template <> otError Interpreter::Process(Arg aArgs[]) OutputIp6PrefixLine(nat64Prefix); } #endif // OPENTHREAD_CONFIG_BORDER_ROUTING_NAT64_ENABLE + /** + * @cli br rioprf [high\med\low] + * + * @code + * br rioprf + * med + * Done + * @endcode + * + * @cparam br rioprf [@ca{high}|@ca{med}|@ca{low}] + * + * @code + * br rioprf low + * Done + * @endcode + * + * @par api_copy + * #otBorderRoutingSetRouteInfoOptionPreference + * + */ + else if ((aArgs[0] == "rioprf")) + { + if (aArgs[1].IsEmpty()) + { + OutputLine("%s", PreferenceToString(otBorderRoutingGetRouteInfoOptionPreference(GetInstancePtr()))); + } + else + { + otRoutePreference preference; + + SuccessOrExit(error = ParsePreference(aArgs[1], preference)); + otBorderRoutingSetRouteInfoOptionPreference(GetInstancePtr(), preference); + } + } else { error = OT_ERROR_INVALID_COMMAND; @@ -1462,6 +1608,25 @@ template <> otError Interpreter::Process(Arg aArgs[]) } #endif +template <> otError Interpreter::Process(Arg aArgs[]) +{ + otError error = OT_ERROR_NONE; + + if (aArgs[0] == "async") + { + SuccessOrExit(error = otThreadDetachGracefully(GetInstancePtr(), nullptr, nullptr)); + } + else + { + SuccessOrExit(error = + otThreadDetachGracefully(GetInstancePtr(), &Interpreter::HandleDetachGracefullyResult, this)); + error = OT_ERROR_PENDING; + } + +exit: + return error; +} + template <> otError Interpreter::Process(Arg aArgs[]) { otError error = OT_ERROR_NONE; @@ -1810,6 +1975,16 @@ template <> otError Interpreter::Process(Arg aArgs[]) } #endif +/** + * @cli eui64 + * @code + * eui64 + * 0615aae900124b00 + * Done + * @endcode + * @par api_copy + * #otPlatRadioGetIeeeEui64 + */ template <> otError Interpreter::Process(Arg aArgs[]) { OT_UNUSED_VARIABLE(aArgs); @@ -2681,7 +2856,7 @@ template <> otError Interpreter::Process(Arg aArgs[]) if (aArgs[0] == "reg") { - otIp6Address addresses[kIp6AddressesNumMax]; + otIp6Address addresses[OT_IP6_MAX_MLR_ADDRESSES]; uint32_t timeout; bool hasTimeout = false; uint8_t numAddresses = 0; @@ -3468,17 +3643,11 @@ otError Interpreter::ParsePrefix(Arg aArgs[], otBorderRouterConfig &aConfig) for (; !aArgs->IsEmpty(); aArgs++) { - if (*aArgs == "high") - { - aConfig.mPreference = OT_ROUTE_PREFERENCE_HIGH; - } - else if (*aArgs == "med") - { - aConfig.mPreference = OT_ROUTE_PREFERENCE_MED; - } - else if (*aArgs == "low") + otRoutePreference preference; + + if (ParsePreference(*aArgs, preference) == OT_ERROR_NONE) { - aConfig.mPreference = OT_ROUTE_PREFERENCE_LOW; + aConfig.mPreference = preference; } else { @@ -3538,6 +3707,23 @@ template <> otError Interpreter::Process(Arg aArgs[]) { otError error = OT_ERROR_NONE; + /** + * @cli prefix + * @code + * prefix + * 2001:dead:beef:cafe::/64 paros med + * - fd00:7d03:7d03:7d03::/64 prosD med + * Done + * @endcode + * @par + * Get the prefix list in the local Network Data. + * @note For the Thread 1.2 border router with backbone capability, the local Domain Prefix + * is listed as well and includes the `D` flag. If backbone functionality is disabled, a dash + * `-` is printed before the local Domain Prefix. + * @par + * For more information about #otBorderRouterConfig flags, refer to @overview. + * @sa otBorderRouterGetNextOnMeshPrefix + */ if (aArgs[0].IsEmpty()) { otNetworkDataIterator iterator = OT_NETWORK_DATA_ITERATOR_INIT; @@ -3557,6 +3743,22 @@ template <> otError Interpreter::Process(Arg aArgs[]) } #endif } + /** + * @cli prefix add + * @code + * prefix add 2001:dead:beef:cafe::/64 paros med + * Done + * @endcode + * @code + * prefix add fd00:7d03:7d03:7d03::/64 prosD low + * Done + * @endcode + * @cparam prefix add @ca{prefix} [@ca{padcrosnD}] [@ca{high}|@ca{med}|@ca{low}] + * OT CLI uses mapped arguments to configure #otBorderRouterConfig values. @moreinfo{the @overview}. + * @par + * Adds a valid prefix to the Network Data. + * @sa otBorderRouterAddOnMeshPrefix + */ else if (aArgs[0] == "add") { otBorderRouterConfig config; @@ -3564,6 +3766,15 @@ template <> otError Interpreter::Process(Arg aArgs[]) SuccessOrExit(error = ParsePrefix(aArgs + 1, config)); error = otBorderRouterAddOnMeshPrefix(GetInstancePtr(), &config); } + /** + * @cli prefix remove + * @code + * prefix remove 2001:dead:beef:cafe::/64 + * Done + * @endcode + * @par api_copy + * #otBorderRouterRemoveOnMeshPrefix + */ else if (aArgs[0] == "remove") { otIp6Prefix prefix; @@ -3571,6 +3782,16 @@ template <> otError Interpreter::Process(Arg aArgs[]) SuccessOrExit(error = aArgs[1].ParseAsIp6Prefix(prefix)); error = otBorderRouterRemoveOnMeshPrefix(GetInstancePtr(), &prefix); } + /** + * @cli prefix meshlocal + * @code + * prefix meshlocal + * fdde:ad00:beef:0::/64 + * Done + * @endcode + * @par + * Get the mesh local prefix. + */ else if (aArgs[0] == "meshlocal") { if (aArgs[1].IsEmpty()) @@ -3697,6 +3918,8 @@ otError Interpreter::ParseRoute(Arg aArgs[], otExternalRouteConfig &aConfig) for (; !aArgs->IsEmpty(); aArgs++) { + otRoutePreference preference; + if (*aArgs == "s") { aConfig.mStable = true; @@ -3705,17 +3928,9 @@ otError Interpreter::ParseRoute(Arg aArgs[], otExternalRouteConfig &aConfig) { aConfig.mNat64 = true; } - else if (*aArgs == "high") - { - aConfig.mPreference = OT_ROUTE_PREFERENCE_HIGH; - } - else if (*aArgs == "med") + else if (ParsePreference(*aArgs, preference) == OT_ERROR_NONE) { - aConfig.mPreference = OT_ROUTE_PREFERENCE_MED; - } - else if (*aArgs == "low") - { - aConfig.mPreference = OT_ROUTE_PREFERENCE_LOW; + aConfig.mPreference = preference; } else { @@ -4594,6 +4809,7 @@ template <> otError Interpreter::Process(Arg aArgs[]) #if OPENTHREAD_CONFIG_COPROCESSOR_RPC_ENABLE otError Interpreter::ProcessCRPC(Arg aArgs[]) { + // This is a host-side function otError error = OT_ERROR_INVALID_COMMAND; char *args[kMaxArgs]; @@ -4933,6 +5149,17 @@ void Interpreter::OutputChildTableEntry(uint8_t aIndentSize, const otNetworkDiag } #endif // OPENTHREAD_FTD || OPENTHREAD_CONFIG_TMF_NETWORK_DIAG_MTD_ENABLE +void Interpreter::HandleDetachGracefullyResult(void *aContext) +{ + static_cast(aContext)->HandleDetachGracefullyResult(); +} + +void Interpreter::HandleDetachGracefullyResult(void) +{ + OutputLine("Finished detaching"); + OutputResult(OT_ERROR_NONE); +} + void Interpreter::HandleDiscoveryRequest(const otThreadDiscoveryRequestInfo &aInfo) { OutputFormat("~ Discovery Request from "); @@ -5047,6 +5274,7 @@ otError Interpreter::ProcessCommand(Arg aArgs[]) #if OPENTHREAD_FTD CmdEntry("delaytimermin"), #endif + CmdEntry("detach"), #endif // OPENTHREAD_FTD || OPENTHREAD_MTD #if OPENTHREAD_CONFIG_DIAG_ENABLE CmdEntry("diag"), diff --git a/util/third_party/openthread/src/cli/cli.hpp b/util/third_party/openthread/src/cli/cli.hpp index 82437adedf..b3bfe89364 100644 --- a/util/third_party/openthread/src/cli/cli.hpp +++ b/util/third_party/openthread/src/cli/cli.hpp @@ -47,6 +47,7 @@ #include #include #include +#include #include #include #if OPENTHREAD_CONFIG_TCP_ENABLE && OPENTHREAD_CONFIG_CLI_TCP_ENABLE @@ -219,6 +220,29 @@ class Interpreter : public Output */ static const char *AddressOriginToString(uint8_t aOrigin); + /** + * This static method parses a given argument string as a route preference comparing it against "high", "med", or + * "low". + * + * @param[in] aArg The argument string to parse. + * @param[out] aPreference Reference to a `otRoutePreference` to return the parsed preference. + * + * @retval OT_ERROR_NONE Successfully parsed @p aArg and updated @p aPreference. + * @retval OT_ERROR_INVALID_ARG @p aArg is not a valid preference string "high", "med", or "low". + * + */ + static otError ParsePreference(const Arg &aArg, otRoutePreference &aPreference); + + /** + * This static method converts a route preference value to human-readable string. + * + * @param[in] aPreference The preference value to convert (`OT_ROUTE_PREFERENCE_*` values). + * + * @returns A string representation @p aPreference. + * + */ + static const char *PreferenceToString(signed int aPreference); + protected: static Interpreter *sInterpreter; @@ -462,6 +486,9 @@ class Interpreter : public Output const char *LinkMetricsStatusToStr(uint8_t aStatus); #endif // OPENTHREAD_CONFIG_MLE_LINK_METRICS_INITIATOR_ENABLE + static void HandleDetachGracefullyResult(void *aContext); + void HandleDetachGracefullyResult(void); + static void HandleDiscoveryRequest(const otThreadDiscoveryRequestInfo *aInfo, void *aContext) { static_cast(aContext)->HandleDiscoveryRequest(*aInfo); diff --git a/util/third_party/openthread/src/cli/cli_dataset.cpp b/util/third_party/openthread/src/cli/cli_dataset.cpp index efade0586a..573436aea6 100644 --- a/util/third_party/openthread/src/cli/cli_dataset.cpp +++ b/util/third_party/openthread/src/cli/cli_dataset.cpp @@ -51,12 +51,12 @@ otError Dataset::Print(otOperationalDataset &aDataset) { if (aDataset.mComponents.mIsPendingTimestampPresent) { - OutputLine("Pending Timestamp: %lu", aDataset.mPendingTimestamp); + OutputLine("Pending Timestamp: %lu", aDataset.mPendingTimestamp.mSeconds); } if (aDataset.mComponents.mIsActiveTimestampPresent) { - OutputLine("Active Timestamp: %lu", aDataset.mActiveTimestamp); + OutputLine("Active Timestamp: %lu", aDataset.mActiveTimestamp.mSeconds); } if (aDataset.mComponents.mIsChannelPresent) @@ -205,12 +205,14 @@ template <> otError Dataset::Process(Arg aArgs[]) { if (sDataset.mComponents.mIsActiveTimestampPresent) { - OutputLine("%lu", sDataset.mActiveTimestamp); + OutputLine("%lu", sDataset.mActiveTimestamp.mSeconds); } } else { - SuccessOrExit(error = aArgs[0].ParseAsUint64(sDataset.mActiveTimestamp)); + SuccessOrExit(error = aArgs[0].ParseAsUint64(sDataset.mActiveTimestamp.mSeconds)); + sDataset.mActiveTimestamp.mTicks = 0; + sDataset.mActiveTimestamp.mAuthoritative = false; sDataset.mComponents.mIsActiveTimestampPresent = true; } @@ -423,12 +425,14 @@ template <> otError Dataset::Process(Arg aArgs[]) { if (sDataset.mComponents.mIsPendingTimestampPresent) { - OutputLine("%lu", sDataset.mPendingTimestamp); + OutputLine("%lu", sDataset.mPendingTimestamp.mSeconds); } } else { - SuccessOrExit(error = aArgs[0].ParseAsUint64(sDataset.mPendingTimestamp)); + SuccessOrExit(error = aArgs[0].ParseAsUint64(sDataset.mPendingTimestamp.mSeconds)); + sDataset.mPendingTimestamp.mTicks = 0; + sDataset.mPendingTimestamp.mAuthoritative = false; sDataset.mComponents.mIsPendingTimestampPresent = true; } @@ -450,14 +454,18 @@ template <> otError Dataset::Process(Arg aArgs[]) if (*arg == "activetimestamp") { arg++; + SuccessOrExit(error = arg->ParseAsUint64(dataset.mActiveTimestamp.mSeconds)); + dataset.mActiveTimestamp.mTicks = 0; + dataset.mActiveTimestamp.mAuthoritative = false; dataset.mComponents.mIsActiveTimestampPresent = true; - SuccessOrExit(error = arg->ParseAsUint64(dataset.mActiveTimestamp)); } else if (*arg == "pendingtimestamp") { arg++; + SuccessOrExit(error = arg->ParseAsUint64(dataset.mPendingTimestamp.mSeconds)); + dataset.mPendingTimestamp.mTicks = 0; + dataset.mPendingTimestamp.mAuthoritative = false; dataset.mComponents.mIsPendingTimestampPresent = true; - SuccessOrExit(error = arg->ParseAsUint64(dataset.mPendingTimestamp)); } else if (*arg == "networkkey") { diff --git a/util/third_party/openthread/src/cli/cli_history.cpp b/util/third_party/openthread/src/cli/cli_history.cpp index 5f6095cc7d..d3c25a3e16 100644 --- a/util/third_party/openthread/src/cli/cli_history.cpp +++ b/util/third_party/openthread/src/cli/cli_history.cpp @@ -112,7 +112,9 @@ template <> otError History::Process(Arg aArgs[]) if (!isList) { - sprintf(&addressString[strlen(addressString)], "/%d", info->mPrefixLength); + size_t len = strlen(addressString); + + snprintf(&addressString[len], sizeof(addressString) - len, "/%d", info->mPrefixLength); OutputLine("| %20s | %-7s | %-43s | %-6s | %3d | %c | %c | %c |", ageString, Stringify(info->mEvent, kSimpleEventStrings), addressString, @@ -600,7 +602,7 @@ template <> otError History::Process(Arg aArgs[]) OutputLine(isList ? "%s -> event:%s prefix:%s flags:%s pref:%s rloc16:0x%04x" : "| %20s | %-7s | %-43s | %-9s | %-4s | 0x%04x |", ageString, Stringify(info->mEvent, kSimpleEventStrings), prefixString, flagsString, - NetworkData::PreferenceToString(info->mPrefix.mPreference), info->mPrefix.mRloc16); + Interpreter::PreferenceToString(info->mPrefix.mPreference), info->mPrefix.mRloc16); } exit: @@ -650,7 +652,7 @@ template <> otError History::Process(Arg aArgs[]) OutputLine(isList ? "%s -> event:%s route:%s flags:%s pref:%s rloc16:0x%04x" : "| %20s | %-7s | %-43s | %-9s | %-4s | 0x%04x |", ageString, Stringify(info->mEvent, kSimpleEventStrings), prefixString, flagsString, - NetworkData::PreferenceToString(info->mRoute.mPreference), info->mRoute.mRloc16); + Interpreter::PreferenceToString(info->mRoute.mPreference), info->mRoute.mRloc16); } exit: diff --git a/util/third_party/openthread/src/cli/cli_joiner.cpp b/util/third_party/openthread/src/cli/cli_joiner.cpp index c4509fe6ef..82d0d3765c 100644 --- a/util/third_party/openthread/src/cli/cli_joiner.cpp +++ b/util/third_party/openthread/src/cli/cli_joiner.cpp @@ -46,6 +46,16 @@ template <> otError Joiner::Process(Arg aArgs[]) { otError error = OT_ERROR_INVALID_ARGS; + /** + * @cli joiner discerner + * @code + * joiner discerner + * 0xabc/12 + * Done + * @endcode + * @par api_copy + * #otJoinerGetDiscerner + */ if (aArgs[0].IsEmpty()) { const otJoinerDiscerner *discerner = otJoinerGetDiscerner(GetInstancePtr()); @@ -61,10 +71,31 @@ template <> otError Joiner::Process(Arg aArgs[]) memset(&discerner, 0, sizeof(discerner)); + /** + * @cli joiner discerner clear + * @code + * joiner discerner clear + * Done + * @endcode + * @par + * Clear the %Joiner discerner. + */ if (aArgs[0] == "clear") { error = otJoinerSetDiscerner(GetInstancePtr(), nullptr); } + /** + * @cli joiner discerner (set) + * @code + * joiner discerner 0xabc/12 + * Done + * @endcode + * @cparam joiner discerner @ca{discerner} + * * Use `{number}/{length}` to set the `discerner`. + * * `joiner discerner clear` sets `aDiscerner` to `nullptr`. + * @par api_copy + * #otJoinerSetDiscerner + */ else { VerifyOrExit(aArgs[1].IsEmpty()); @@ -77,6 +108,16 @@ template <> otError Joiner::Process(Arg aArgs[]) return error; } +/** + * @cli joiner id + * @code + * joiner id + * d65e64fa83f81cf7 + * Done + * @endcode + * @par api_copy + * #otJoinerGetId + */ template <> otError Joiner::Process(Arg aArgs[]) { OT_UNUSED_VARIABLE(aArgs); @@ -86,6 +127,20 @@ template <> otError Joiner::Process(Arg aArgs[]) return OT_ERROR_NONE; } +/** + * @cli joiner start + * @code + * joiner start J01NM3 + * Done + * @endcode + * @cparam joiner start @ca{joining-device-credential} [@ca{provisioning-url}] + * * `joining-device-credential`: %Joiner Passphrase. Must be a string of all uppercase alphanumeric + * characters (0-9 and A-Y, excluding I, O, Q, and Z for readability), with a length between 6 and + * 32 characters. + * * `provisioning-url`: Provisioning URL for the %Joiner (optional). + * @par api_copy + * #otJoinerStart + */ template <> otError Joiner::Process(Arg aArgs[]) { otError error; @@ -105,6 +160,15 @@ template <> otError Joiner::Process(Arg aArgs[]) return error; } +/** + * @cli joiner stop + * @code + * joiner stop + * Done + * @endcode + * @par api_copy + * #otJoinerStop + */ template <> otError Joiner::Process(Arg aArgs[]) { OT_UNUSED_VARIABLE(aArgs); @@ -114,6 +178,24 @@ template <> otError Joiner::Process(Arg aArgs[]) return OT_ERROR_NONE; } +/** + * @cli joiner state + * @code + * joiner state + * Idle + * Done + * @endcode + * @par api_copy + * #otJoinerGetState + * @par + * Returns one of the following states: + * * `Idle` + * * `Discover` + * * `Connecting` + * * `Connected` + * * `Entrust` + * * `Joined` + */ template <> otError Joiner::Process(Arg aArgs[]) { OT_UNUSED_VARIABLE(aArgs); @@ -141,6 +223,20 @@ otError Joiner::Process(Arg aArgs[]) otError error = OT_ERROR_INVALID_COMMAND; const Command *command; + /** + * @cli joiner help + * @code + * joiner help + * help + * id + * start + * state + * stop + * Done + * @endcode + * @par + * Print the `joiner` help menu. + */ if (aArgs[0].IsEmpty() || (aArgs[0] == "help")) { OutputCommandTable(kCommands); diff --git a/util/third_party/openthread/src/cli/cli_network_data.cpp b/util/third_party/openthread/src/cli/cli_network_data.cpp index ee02b1bbcd..1c3de9071d 100644 --- a/util/third_party/openthread/src/cli/cli_network_data.cpp +++ b/util/third_party/openthread/src/cli/cli_network_data.cpp @@ -108,7 +108,7 @@ void NetworkData::OutputPrefix(const otBorderRouterConfig &aConfig) OutputFormat(" %s", flagsString); } - OutputLine(" %s %04x", PreferenceToString(aConfig.mPreference), aConfig.mRloc16); + OutputLine(" %s %04x", Interpreter::PreferenceToString(aConfig.mPreference), aConfig.mRloc16); } void NetworkData::RouteFlagsToString(const otExternalRouteConfig &aConfig, FlagsString &aString) @@ -141,32 +141,7 @@ void NetworkData::OutputRoute(const otExternalRouteConfig &aConfig) OutputFormat(" %s", flagsString); } - OutputLine(" %s %04x", PreferenceToString(aConfig.mPreference), aConfig.mRloc16); -} - -const char *NetworkData::PreferenceToString(signed int aPreference) -{ - const char *str = ""; - - switch (aPreference) - { - case OT_ROUTE_PREFERENCE_LOW: - str = "low"; - break; - - case OT_ROUTE_PREFERENCE_MED: - str = "med"; - break; - - case OT_ROUTE_PREFERENCE_HIGH: - str = "high"; - break; - - default: - break; - } - - return str; + OutputLine(" %s %04x", Interpreter::PreferenceToString(aConfig.mPreference), aConfig.mRloc16); } void NetworkData::OutputService(const otServiceConfig &aConfig) @@ -192,6 +167,24 @@ template <> otError NetworkData::Process(Arg aArgs[]) #if OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE if (aArgs[0] == "dnssrp") { + /** + * @cli netdata publish dnssrp anycast + * @code + * netdata publish dnssrp anycast 1 + * Done + * @endcode + * @cparam netdata publish dnssrp anycast @ca{seq-num} + * @par + * Publishes a DNS/SRP Service Anycast Address with a sequence number. Any current + * DNS/SRP Service entry being published from a previous `publish dnssrp{anycast|unicast}` + * command is removed and replaced with the new arguments. + * @par + * `OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE` must be enabled. + * @csa{netdata publish dnssrp unicast (addr,port)} + * @csa{netdata publish dnssrp unicast (mle)} + * @sa otNetDataPublishDnsSrpServiceAnycast + * @endcli + */ if (aArgs[1] == "anycast") { uint8_t sequenceNumber; @@ -206,6 +199,26 @@ template <> otError NetworkData::Process(Arg aArgs[]) otIp6Address address; uint16_t port; + /** + * @cli netdata publish dnssrp unicast (mle) + * @code + * netdata publish dnssrp unicast 50152 + * Done + * @endcode + * @cparam netdata publish dnssrp unicast @ca{port} + * @par + * Publishes the device's Mesh-Local EID with a port number. MLE and port information is + * included in the Server TLV data. To use a different Unicast address, use the + * `netdata publish dnssrp unicast (addr,port)` command. + * @par + * Any current DNS/SRP Service entry being published from a previous + * `publish dnssrp{anycast|unicast}` command is removed and replaced with the new arguments. + * @par + * `OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE` must be enabled. + * @csa{netdata publish dnssrp unicast (addr,port)} + * @csa{netdata publish dnssrp anycast} + * @sa otNetDataPublishDnsSrpServiceUnicastMeshLocalEid + */ if (aArgs[3].IsEmpty()) { SuccessOrExit(error = aArgs[2].ParseAsUint16(port)); @@ -213,6 +226,24 @@ template <> otError NetworkData::Process(Arg aArgs[]) ExitNow(); } + /** + * @cli netdata publish dnssrp unicast (addr,port) + * @code + * netdata publish dnssrp unicast fd00::1234 51525 + * Done + * @endcode + * @cparam netdata publish dnssrp unicast @ca{address} @ca{port} + * @par + * Publishes a DNS/SRP Service Unicast Address with an address and port number. The address + * and port information is included in Service TLV data. Any current DNS/SRP Service entry being + * published from a previous `publish dnssrp{anycast|unicast}` command is removed and replaced + * with the new arguments. + * @par + * `OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE` must be enabled. + * @csa{netdata publish dnssrp unicast (mle)} + * @csa{netdata publish dnssrp anycast} + * @sa otNetDataPublishDnsSrpServiceUnicast + */ SuccessOrExit(error = aArgs[2].ParseAsIp6Address(address)); SuccessOrExit(error = aArgs[3].ParseAsUint16(port)); otNetDataPublishDnsSrpServiceUnicast(GetInstancePtr(), &address, port); @@ -222,6 +253,18 @@ template <> otError NetworkData::Process(Arg aArgs[]) #endif // OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE #if OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE + /** + * @cli netdata publish prefix + * @code + * netdata publish prefix fd00:1234:5678::/64 paos med + * Done + * @endcode + * @cparam netdata publish prefix @ca{prefix} [@ca{padcrosnD}] [@ca{high}|@ca{med}|@ca{low}] + * OT CLI uses mapped arguments to configure #otBorderRouterConfig values. @moreinfo{the @overview}. + * @par + * Publish an on-mesh prefix entry. @moreinfo{@netdata}. + * @sa otNetDataPublishOnMeshPrefix + */ if (aArgs[0] == "prefix") { otBorderRouterConfig config; @@ -231,6 +274,18 @@ template <> otError NetworkData::Process(Arg aArgs[]) ExitNow(); } + /** + * @cli netdata publish route + * @code + * netdata publish route fd00:1234:5678::/64 s high + * Done + * @endcode + * @cparam publish route @ca{prefix} [@ca{sn}] [@ca{high}|@ca{med}|@ca{low}] + * OT CLI uses mapped arguments to configure #otExternalRouteConfig values. @moreinfo{the @overview}. + * @par + * Publish an external route entry. @moreinfo{@netdata}. + * @sa otNetDataPublishExternalRoute + */ if (aArgs[0] == "route") { otExternalRouteConfig config; @@ -251,6 +306,15 @@ template <> otError NetworkData::Process(Arg aArgs[]) { otError error = OT_ERROR_NONE; +/** + * @cli netdata unpublish dnssrp + * @code + * netdata unpublish dnssrp + * Done + * @endcode + * @par api_copy + * #otNetDataUnpublishDnsSrpService + */ #if OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE if (aArgs[0] == "dnssrp") { @@ -259,6 +323,18 @@ template <> otError NetworkData::Process(Arg aArgs[]) } #endif +/** + * @cli netdata unpublish (prefix) + * @code + * netdata unpublish fd00:1234:5678::/64 + * Done + * @endcode + * @cparam netdata unpublish @ca{prefix} + * @par api_copy + * #otNetDataUnpublishPrefix + * @par + * @moreinfo{@netdata}. + */ #if OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE { otIp6Prefix prefix; @@ -279,6 +355,22 @@ template <> otError NetworkData::Process(Arg aArgs[]) #endif // OPENTHREAD_CONFIG_NETDATA_PUBLISHER_ENABLE #if OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE || OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE +/** + * @cli netdata register + * @code + * netdata register + * Done + * @endcode + * @par + * Register configured prefixes, routes, and services with the Leader. + * @par + * OT CLI checks for `OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE`. If OTBR is enabled, it + * registers local Network Data with the Leader. Otherwise, it calls the CLI function `otServerRegister`. + * @moreinfo{@netdata}. + * @csa{prefix add} + * @sa otBorderRouterRegister + * @sa otServerAddService + */ template <> otError NetworkData::Process(Arg aArgs[]) { OT_UNUSED_VARIABLE(aArgs); @@ -314,10 +406,38 @@ template <> otError NetworkData::Process(Arg aArgs[]) SuccessOrExit(error); + /** + * @cli netdata steeringdata check (discerner) + * @code + * netdata steeringdata check 0xabc/12 + * Done + * @endcode + * @code + * netdata steeringdata check 0xdef/12 + * Error 23: NotFound + * @endcode + * @cparam netdata steeringdata check @ca{discerner} + * * `discerner`: The %Joiner discerner in format `{number}/{length}`. + * @par api_copy + * #otNetDataSteeringDataCheckJoinerWithDiscerner + * @csa{joiner discerner} + */ if (discerner.mLength) { error = otNetDataSteeringDataCheckJoinerWithDiscerner(GetInstancePtr(), &discerner); } + /** + * @cli netdata steeringdata check (eui64) + * @code + * netdata steeringdata check d45e64fa83f81cf7 + * Done + * @endcode + * @cparam netdata steeringdata check @ca{eui64} + * * `eui64`: The IEEE EUI-64 of the %Joiner. + * @par api_copy + * #otNetDataSteeringDataCheckJoiner + * @csa{eui64} + */ else { error = otNetDataSteeringDataCheckJoiner(GetInstancePtr(), &addr); @@ -452,6 +572,36 @@ otError NetworkData::OutputBinary(bool aLocal) return error; } +/** + * @cli netdata show + * @code + * netdata show + * Prefixes: + * fd00:dead:beef:cafe::/64 paros med dc00 + * Routes: + * fd49:7770:7fc5:0::/64 s med 4000 + * Services: + * 44970 5d c000 s 4000 + * 44970 01 9a04b000000e10 s 4000 + * Done + * @endcode + * @code + * netdata show -x + * 08040b02174703140040fd00deadbeefcafe0504dc00330007021140 + * Done + * @endcode + * @cparam netdata show [@ca{-x}] + * * The optional `-x` argument gets Network Data as hex-encoded TLVs. + * @par + * `netdata show` from OT CLI gets full Network Data received from the Leader. This command uses several + * API functions to combine prefixes, routes, and services, including #otNetDataGetNextOnMeshPrefix, + * #otNetDataGetNextRoute, and #otNetDataGetNextService. + * @par + * @moreinfo{@netdata}. + * @csa{br omrprefix} + * @csa{br onlinkprefix} + * @sa otBorderRouterGetNetData + */ template <> otError NetworkData::Process(Arg aArgs[]) { otError error = OT_ERROR_INVALID_ARGS; @@ -460,6 +610,27 @@ template <> otError NetworkData::Process(Arg aArgs[]) for (uint8_t i = 0; !aArgs[i].IsEmpty(); i++) { + /** + * @cli netdata show local + * @code + * netdata show local + * Prefixes: + * fd00:dead:beef:cafe::/64 paros med dc00 + * Routes: + * Services: + * Done + * @endcode + * @code + * netdata show local -x + * 08040b02174703140040fd00deadbeefcafe0504dc00330007021140 + * Done + * @endcode + * @cparam netdata show local [@ca{-x}] + * * The optional `-x` argument gets local Network Data as hex-encoded TLVs. + * @par + * Print local Network Data to sync with the Leader. + * @csa{netdata show} + */ if (aArgs[i] == "local") { local = true; @@ -518,6 +689,22 @@ otError NetworkData::Process(Arg aArgs[]) otError error = OT_ERROR_INVALID_COMMAND; const Command *command; + /** + * @cli netdata help + * @code + * netdata help + * help + * publish + * register + * show + * steeringdata + * unpublish + * Done + * @endcode + * @par + * Gets a list of `netdata` CLI commands. + * @sa @netdata + */ if (aArgs[0].IsEmpty() || (aArgs[0] == "help")) { OutputCommandTable(kCommands); diff --git a/util/third_party/openthread/src/cli/cli_network_data.hpp b/util/third_party/openthread/src/cli/cli_network_data.hpp index 0fb2098df5..d46ba9ecda 100644 --- a/util/third_party/openthread/src/cli/cli_network_data.hpp +++ b/util/third_party/openthread/src/cli/cli_network_data.hpp @@ -125,16 +125,6 @@ class NetworkData : private OutputWrapper */ static void RouteFlagsToString(const otExternalRouteConfig &aConfig, FlagsString &aString); - /** - * This static method converts a route preference value to human-readable string. - * - * @param[in] aPreference The preference value to convert (`OT_ROUTE_PREFERENCE_*` values). - * - * @returns A string representation @p aPreference. - * - */ - static const char *PreferenceToString(signed int aPreference); - private: using Command = CommandEntry; diff --git a/util/third_party/openthread/src/cli/cli_srp_client.cpp b/util/third_party/openthread/src/cli/cli_srp_client.cpp index 4d81cd9010..0732ac2e4c 100644 --- a/util/third_party/openthread/src/cli/cli_srp_client.cpp +++ b/util/third_party/openthread/src/cli/cli_srp_client.cpp @@ -160,10 +160,21 @@ template <> otError SrpClient::Process(Arg aArgs[]) { const otSrpClientHostInfo *hostInfo = otSrpClientGetHostInfo(GetInstancePtr()); - for (uint8_t index = 0; index < hostInfo->mNumAddresses; index++) + if (hostInfo->mAutoAddress) { - OutputIp6AddressLine(hostInfo->mAddresses[index]); + OutputLine("auto"); } + else + { + for (uint8_t index = 0; index < hostInfo->mNumAddresses; index++) + { + OutputIp6AddressLine(hostInfo->mAddresses[index]); + } + } + } + else if (aArgs[1] == "auto") + { + error = otSrpClientEnableAutoHostAddress(GetInstancePtr()); } else { @@ -447,19 +458,28 @@ void SrpClient::OutputHostInfo(uint8_t aIndentSize, const otSrpClientHostInfo &a OutputFormat("(null)"); } - OutputFormat(", state:%s, addrs:[", otSrpClientItemStateToString(aHostInfo.mState)); + OutputFormat(", state:%s, addrs:", otSrpClientItemStateToString(aHostInfo.mState)); - for (uint8_t index = 0; index < aHostInfo.mNumAddresses; index++) + if (aHostInfo.mAutoAddress) + { + OutputLine("auto"); + } + else { - if (index > 0) + OutputFormat("["); + + for (uint8_t index = 0; index < aHostInfo.mNumAddresses; index++) { - OutputFormat(", "); + if (index > 0) + { + OutputFormat(", "); + } + + OutputIp6Address(aHostInfo.mAddresses[index]); } - OutputIp6Address(aHostInfo.mAddresses[index]); + OutputLine("]"); } - - OutputLine("]"); } void SrpClient::OutputServiceList(uint8_t aIndentSize, const otSrpClientService *aServices) diff --git a/util/third_party/openthread/src/cli/radio.cmake b/util/third_party/openthread/src/cli/radio.cmake index 9b69a9e6b4..3e7354aa69 100644 --- a/util/third_party/openthread/src/cli/radio.cmake +++ b/util/third_party/openthread/src/cli/radio.cmake @@ -46,10 +46,14 @@ target_sources(openthread-cli-radio cli_output.cpp ) +if(NOT DEFINED OT_MBEDTLS_RCP) + set(OT_MBEDTLS_RCP ${OT_MBEDTLS}) +endif() + target_link_libraries(openthread-cli-radio PUBLIC openthread-radio PRIVATE - ${OT_MBEDTLS} + ${OT_MBEDTLS_RCP} ot-config ) diff --git a/util/third_party/openthread/src/core/BUILD.gn b/util/third_party/openthread/src/core/BUILD.gn index ff85b9941d..2a566d33fe 100644 --- a/util/third_party/openthread/src/core/BUILD.gn +++ b/util/third_party/openthread/src/core/BUILD.gn @@ -37,6 +37,8 @@ if (openthread_enable_core_config_args) { defines += [ "OPENTHREAD_CONFIG_THREAD_VERSION=OT_THREAD_VERSION_1_1" ] } else if (openthread_config_thread_version == "1.2") { defines += [ "OPENTHREAD_CONFIG_THREAD_VERSION=OT_THREAD_VERSION_1_2" ] + } else if (openthread_config_thread_version == "1.3") { + defines += [ "OPENTHREAD_CONFIG_THREAD_VERSION=OT_THREAD_VERSION_1_3" ] } else if (openthread_config_thread_version != "") { assert(false, "Unrecognized Thread version: ${openthread_config_thread_version}") @@ -370,8 +372,6 @@ openthread_core_files = [ "backbone_router/ndproxy_table.hpp", "border_router/infra_if.cpp", "border_router/infra_if.hpp", - "border_router/router_advertisement.cpp", - "border_router/router_advertisement.hpp", "border_router/routing_manager.cpp", "border_router/routing_manager.hpp", "coap/coap.cpp", @@ -565,6 +565,8 @@ openthread_core_files = [ "net/ip6_mpl.cpp", "net/ip6_mpl.hpp", "net/ip6_types.hpp", + "net/nd6.cpp", + "net/nd6.hpp", "net/nd_agent.cpp", "net/nd_agent.hpp", "net/netif.cpp", diff --git a/util/third_party/openthread/src/core/CMakeLists.txt b/util/third_party/openthread/src/core/CMakeLists.txt index 493d29546c..28c4344598 100644 --- a/util/third_party/openthread/src/core/CMakeLists.txt +++ b/util/third_party/openthread/src/core/CMakeLists.txt @@ -88,7 +88,6 @@ set(COMMON_SOURCES backbone_router/multicast_listeners_table.cpp backbone_router/ndproxy_table.cpp border_router/infra_if.cpp - border_router/router_advertisement.cpp border_router/routing_manager.cpp coap/coap.cpp coap/coap_message.cpp @@ -171,6 +170,7 @@ set(COMMON_SOURCES net/ip6_filter.cpp net/ip6_headers.cpp net/ip6_mpl.cpp + net/nd6.cpp net/nd_agent.cpp net/netif.cpp net/sntp_client.cpp diff --git a/util/third_party/openthread/src/core/Makefile.am b/util/third_party/openthread/src/core/Makefile.am index e226132762..5c754eefbe 100644 --- a/util/third_party/openthread/src/core/Makefile.am +++ b/util/third_party/openthread/src/core/Makefile.am @@ -178,7 +178,6 @@ SOURCES_COMMON = \ backbone_router/multicast_listeners_table.cpp \ backbone_router/ndproxy_table.cpp \ border_router/infra_if.cpp \ - border_router/router_advertisement.cpp \ border_router/routing_manager.cpp \ coap/coap.cpp \ coap/coap_message.cpp \ @@ -261,6 +260,7 @@ SOURCES_COMMON = \ net/ip6_filter.cpp \ net/ip6_headers.cpp \ net/ip6_mpl.cpp \ + net/nd6.cpp \ net/nd_agent.cpp \ net/netif.cpp \ net/sntp_client.cpp \ @@ -420,7 +420,6 @@ HEADERS_COMMON = \ backbone_router/multicast_listeners_table.hpp \ backbone_router/ndproxy_table.hpp \ border_router/infra_if.hpp \ - border_router/router_advertisement.hpp \ border_router/routing_manager.hpp \ coap/coap.hpp \ coap/coap_message.hpp \ @@ -570,6 +569,7 @@ HEADERS_COMMON = \ net/ip6_headers.hpp \ net/ip6_mpl.hpp \ net/ip6_types.hpp \ + net/nd6.hpp \ net/nd_agent.hpp \ net/netif.hpp \ net/sntp_client.hpp \ diff --git a/util/third_party/openthread/src/core/api/border_router_api.cpp b/util/third_party/openthread/src/core/api/border_router_api.cpp index d90893192e..621551655a 100644 --- a/util/third_party/openthread/src/core/api/border_router_api.cpp +++ b/util/third_party/openthread/src/core/api/border_router_api.cpp @@ -54,6 +54,18 @@ otError otBorderRoutingSetEnabled(otInstance *aInstance, bool aEnabled) return AsCoreType(aInstance).Get().SetEnabled(aEnabled); } +otRoutePreference otBorderRoutingGetRouteInfoOptionPreference(otInstance *aInstance) +{ + return static_cast( + AsCoreType(aInstance).Get().GetRouteInfoOptionPreference()); +} + +void otBorderRoutingSetRouteInfoOptionPreference(otInstance *aInstance, otRoutePreference aPreference) +{ + AsCoreType(aInstance).Get().SetRouteInfoOptionPreference( + static_cast(aPreference)); +} + otError otBorderRoutingGetOmrPrefix(otInstance *aInstance, otIp6Prefix *aPrefix) { return AsCoreType(aInstance).Get().GetOmrPrefix(AsCoreType(aPrefix)); diff --git a/util/third_party/openthread/src/core/api/coprocessor_rpc_api.cpp b/util/third_party/openthread/src/core/api/coprocessor_rpc_api.cpp index eaeb2501cb..ca3cae9b0b 100644 --- a/util/third_party/openthread/src/core/api/coprocessor_rpc_api.cpp +++ b/util/third_party/openthread/src/core/api/coprocessor_rpc_api.cpp @@ -125,6 +125,16 @@ extern "C" void otCRPCSetUserCommands(const otCliCommand *aUserCommands, uint8_t { RPC::GetRPC().SetUserCommands(aUserCommands, aLength, aContext); } + +extern "C" char* otCRPCGetStaticOutputBuffer(void) +{ + return RPC::GetRPC().GetStaticOutputBuffer(); +} + +extern "C" size_t otCRPCGetStaticOutputBufferSize(void) +{ + return RPC::GetRPC().GetStaticOutputBufferSize(); +} #endif #endif // OPENTHREAD_CONFIG_COPROCESSOR_RPC_ENABLE diff --git a/util/third_party/openthread/src/core/api/srp_client_api.cpp b/util/third_party/openthread/src/core/api/srp_client_api.cpp index a0c16e3d95..3ec356f343 100644 --- a/util/third_party/openthread/src/core/api/srp_client_api.cpp +++ b/util/third_party/openthread/src/core/api/srp_client_api.cpp @@ -124,6 +124,11 @@ otError otSrpClientSetHostName(otInstance *aInstance, const char *aName) return AsCoreType(aInstance).Get().SetHostName(aName); } +otError otSrpClientEnableAutoHostAddress(otInstance *aInstance) +{ + return AsCoreType(aInstance).Get().EnableAutoHostAddress(); +} + otError otSrpClientSetHostAddresses(otInstance *aInstance, const otIp6Address *aIp6Addresses, uint8_t aNumAddresses) { return AsCoreType(aInstance).Get().SetHostAddresses(AsCoreTypePtr(aIp6Addresses), aNumAddresses); diff --git a/util/third_party/openthread/src/core/api/thread_api.cpp b/util/third_party/openthread/src/core/api/thread_api.cpp index ca38757e87..bec8c0633e 100644 --- a/util/third_party/openthread/src/core/api/thread_api.cpp +++ b/util/third_party/openthread/src/core/api/thread_api.cpp @@ -497,4 +497,9 @@ bool otThreadIsAnycastLocateInProgress(otInstance *aInstance) } #endif +otError otThreadDetachGracefully(otInstance *aInstance, otDetachGracefullyCallback aCallback, void *aContext) +{ + return AsCoreType(aInstance).Get().DetachGracefully(aCallback, aContext); +} + #endif // OPENTHREAD_FTD || OPENTHREAD_MTD diff --git a/util/third_party/openthread/src/core/backbone_router/bbr_manager.cpp b/util/third_party/openthread/src/core/backbone_router/bbr_manager.cpp index 850245d4b9..2de2f6f824 100644 --- a/util/third_party/openthread/src/core/backbone_router/bbr_manager.cpp +++ b/util/third_party/openthread/src/core/backbone_router/bbr_manager.cpp @@ -165,7 +165,7 @@ void Manager::HandleMulticastListenerRegistration(const Coap::Message &aMessage, uint16_t addressesOffset, addressesLength; Ip6::Address address; - Ip6::Address addresses[kIp6AddressesNumMax]; + Ip6::Address addresses[Ip6AddressesTlv::kMaxAddresses]; uint8_t failedAddressNum = 0; uint8_t successAddressNum = 0; TimeMilli expireTime; @@ -207,7 +207,7 @@ void Manager::HandleMulticastListenerRegistration(const Coap::Message &aMessage, kErrorNone, error = kErrorParse); VerifyOrExit(addressesLength % sizeof(Ip6::Address) == 0, status = ThreadStatusTlv::kMlrGeneralFailure); - VerifyOrExit(addressesLength / sizeof(Ip6::Address) <= kIp6AddressesNumMax, + VerifyOrExit(addressesLength / sizeof(Ip6::Address) <= Ip6AddressesTlv::kMaxAddresses, status = ThreadStatusTlv::kMlrGeneralFailure); if (!processTimeoutTlv) @@ -244,7 +244,7 @@ void Manager::HandleMulticastListenerRegistration(const Coap::Message &aMessage, mMulticastListenersTable.Remove(address); // Put successfully de-registered addresses at the end of `addresses`. - addresses[kIp6AddressesNumMax - (++successAddressNum)] = address; + addresses[Ip6AddressesTlv::kMaxAddresses - (++successAddressNum)] = address; } else { @@ -278,7 +278,7 @@ void Manager::HandleMulticastListenerRegistration(const Coap::Message &aMessage, else { // Put successfully registered addresses at the end of `addresses`. - addresses[kIp6AddressesNumMax - (++successAddressNum)] = address; + addresses[Ip6AddressesTlv::kMaxAddresses - (++successAddressNum)] = address; } } } @@ -291,7 +291,7 @@ void Manager::HandleMulticastListenerRegistration(const Coap::Message &aMessage, if (successAddressNum > 0) { - SendBackboneMulticastListenerRegistration(&addresses[kIp6AddressesNumMax - successAddressNum], + SendBackboneMulticastListenerRegistration(&addresses[Ip6AddressesTlv::kMaxAddresses - successAddressNum], successAddressNum, timeout); } } @@ -341,7 +341,7 @@ void Manager::SendBackboneMulticastListenerRegistration(const Ip6::Address *aAdd Ip6AddressesTlv addressesTlv; BackboneTmfAgent &backboneTmf = Get(); - OT_ASSERT(aAddressNum >= kIp6AddressesNumMin && aAddressNum <= kIp6AddressesNumMax); + OT_ASSERT(aAddressNum >= Ip6AddressesTlv::kMinAddresses && aAddressNum <= Ip6AddressesTlv::kMaxAddresses); message = backboneTmf.NewNonConfirmablePostMessage(UriPath::kBackboneMlr); VerifyOrExit(message != nullptr, error = kErrorNoBufs); diff --git a/util/third_party/openthread/src/core/border_router/router_advertisement.cpp b/util/third_party/openthread/src/core/border_router/router_advertisement.cpp deleted file mode 100644 index c1c3c1d148..0000000000 --- a/util/third_party/openthread/src/core/border_router/router_advertisement.cpp +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright (c) 2020, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file - * This file includes implementations for ICMPv6 Router Advertisement. - * - */ - -#include "border_router/router_advertisement.hpp" - -#if OPENTHREAD_CONFIG_BORDER_ROUTING_ENABLE - -#include "common/as_core_type.hpp" -#include "common/code_utils.hpp" - -namespace ot { -namespace BorderRouter { -namespace RouterAdv { - -const Option *Option::GetNextOption(const Option *aCurOption, const uint8_t *aBuffer, uint16_t aBufferLength) -{ - const uint8_t *nextOption = nullptr; - const uint8_t *bufferEnd = aBuffer + aBufferLength; - - VerifyOrExit(aBuffer != nullptr, nextOption = nullptr); - - if (aCurOption == nullptr) - { - nextOption = aBuffer; - } - else - { - nextOption = reinterpret_cast(aCurOption) + aCurOption->GetSize(); - } - - VerifyOrExit(nextOption + sizeof(Option) <= bufferEnd, nextOption = nullptr); - VerifyOrExit(reinterpret_cast(nextOption)->GetSize() > 0, nextOption = nullptr); - VerifyOrExit(nextOption + reinterpret_cast(nextOption)->GetSize() <= bufferEnd, - nextOption = nullptr); - -exit: - return reinterpret_cast(nextOption); -} - -//---------------------------------------------------------------------------------------------------------------------- -// PrefixInfoOption - -void PrefixInfoOption::Init(void) -{ - Clear(); - SetType(Type::kPrefixInfo); - SetSize(sizeof(PrefixInfoOption)); - - OT_UNUSED_VARIABLE(mReserved2); -} - -void PrefixInfoOption::SetPrefix(const Ip6::Prefix &aPrefix) -{ - mPrefixLength = aPrefix.mLength; - mPrefix = AsCoreType(&aPrefix.mPrefix); -} - -void PrefixInfoOption::GetPrefix(Ip6::Prefix &aPrefix) const -{ - aPrefix.Set(mPrefix.GetBytes(), mPrefixLength); -} - -bool PrefixInfoOption::IsValid(void) const -{ - return (GetSize() >= sizeof(*this)) && (mPrefixLength <= Ip6::Prefix::kMaxLength) && - (GetPreferredLifetime() <= GetValidLifetime()); -} - -//---------------------------------------------------------------------------------------------------------------------- -// RouteInfoOption - -void RouteInfoOption::Init(void) -{ - Clear(); - SetType(Type::kRouteInfo); -} - -void RouteInfoOption::SetPreference(RoutePreference aPreference) -{ - mResvdPrf &= ~kPreferenceMask; - mResvdPrf |= (NetworkData::RoutePreferenceToValue(aPreference) << kPreferenceOffset) & kPreferenceMask; -} - -RoutePreference RouteInfoOption::GetPreference(void) const -{ - return NetworkData::RoutePreferenceFromValue((mResvdPrf & kPreferenceMask) >> kPreferenceOffset); -} - -void RouteInfoOption::SetPrefix(const Ip6::Prefix &aPrefix) -{ - SetLength(OptionLengthForPrefix(aPrefix.mLength)); - mPrefixLength = aPrefix.mLength; - memcpy(GetPrefixBytes(), aPrefix.GetBytes(), aPrefix.GetBytesSize()); -} - -void RouteInfoOption::GetPrefix(Ip6::Prefix &aPrefix) const -{ - aPrefix.Set(GetPrefixBytes(), mPrefixLength); -} - -bool RouteInfoOption::IsValid(void) const -{ - return (GetSize() >= kMinSize) && (mPrefixLength <= Ip6::Prefix::kMaxLength) && - (GetLength() >= OptionLengthForPrefix(mPrefixLength)) && - NetworkData::IsRoutePreferenceValid(GetPreference()); -} - -uint8_t RouteInfoOption::OptionLengthForPrefix(uint8_t aPrefixLength) -{ - static constexpr uint8_t kMaxPrefixLenForOptionLen1 = 0; - static constexpr uint8_t kMaxPrefixLenForOptionLen2 = 64; - - uint8_t length; - - // The Option Length can be 1, 2, or 3 depending on the prefix - // length - // - // - 1 when prefix len is zero. - // - 2 when prefix len is less then or equal to 64. - // - 3 otherwise. - - if (aPrefixLength == kMaxPrefixLenForOptionLen1) - { - length = 1; - } - else if (aPrefixLength <= kMaxPrefixLenForOptionLen2) - { - length = 2; - } - else - { - length = 3; - } - - return length; -} - -//---------------------------------------------------------------------------------------------------------------------- -// RouterAdvMessage - -void RouterAdvMessage::SetToDefault(void) -{ - OT_UNUSED_VARIABLE(mCode); - OT_UNUSED_VARIABLE(mCurHopLimit); - OT_UNUSED_VARIABLE(mReachableTime); - OT_UNUSED_VARIABLE(mRetransTimer); - - Clear(); - mType = Ip6::Icmp::Header::kTypeRouterAdvert; -} - -RoutePreference RouterAdvMessage::GetDefaultRouterPreference(void) const -{ - return NetworkData::RoutePreferenceFromValue((mFlags & kPreferenceMask) >> kPreferenceOffset); -} - -void RouterAdvMessage::SetDefaultRouterPreference(RoutePreference aPreference) -{ - mFlags &= ~kPreferenceMask; - mFlags |= (NetworkData::RoutePreferenceToValue(aPreference) << kPreferenceOffset) & kPreferenceMask; -} - -//---------------------------------------------------------------------------------------------------------------------- -// RouterAdvMessage - -RouterSolicitMessage::RouterSolicitMessage(void) -{ - mHeader.Clear(); - mHeader.SetType(Ip6::Icmp::Header::kTypeRouterSolicit); -} - -} // namespace RouterAdv -} // namespace BorderRouter -} // namespace ot - -#endif // OPENTHREAD_CONFIG_BORDER_ROUTING_ENABLE diff --git a/util/third_party/openthread/src/core/border_router/router_advertisement.hpp b/util/third_party/openthread/src/core/border_router/router_advertisement.hpp deleted file mode 100644 index c98f440722..0000000000 --- a/util/third_party/openthread/src/core/border_router/router_advertisement.hpp +++ /dev/null @@ -1,575 +0,0 @@ -/* - * Copyright (c) 2020, The OpenThread Authors. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file - * This file includes definitions for IPv6 Router Advertisement. - * - * See RFC 4861: Neighbor Discovery for IP version 6 (https://tools.ietf.org/html/rfc4861). - * - */ - -#ifndef ROUTER_ADVERTISEMENT_HPP_ -#define ROUTER_ADVERTISEMENT_HPP_ - -#include "openthread-core-config.h" - -#if OPENTHREAD_CONFIG_BORDER_ROUTING_ENABLE - -#include - -#include -#include - -#include "common/const_cast.hpp" -#include "common/encoding.hpp" -#include "common/equatable.hpp" -#include "net/icmp6.hpp" -#include "net/ip6.hpp" -#include "thread/network_data_types.hpp" - -using ot::Encoding::BigEndian::HostSwap16; -using ot::Encoding::BigEndian::HostSwap32; - -namespace ot { -namespace BorderRouter { -namespace RouterAdv { - -typedef NetworkData::RoutePreference RoutePreference; ///< Route Preference - -/** - * This class represents the variable length options in Neighbor Discovery messages. - * - * @sa PrefixInfoOption - * @sa RouteInfoOption - * - */ -OT_TOOL_PACKED_BEGIN -class Option -{ -public: - enum class Type : uint8_t - { - kPrefixInfo = 3, ///< Prefix Information Option. - kRouteInfo = 24, ///< Route Information Option. - }; - - static constexpr uint16_t kLengthUnit = 8; ///< The unit of length in octets. - - /** - * This method gets the option type. - * - * @returns The option type. - * - */ - Type GetType(void) const { return mType; } - - /** - * This method sets the option type. - * - * @param[in] aType The option type. - * - * - */ - void SetType(Type aType) { mType = aType; } - - /** - * This method sets the length based on a given total option size in bytes. - * - * Th option must end on a 64-bit boundary, so the length is derived as `(aSize + 7) / 8 * 8`. - * - * @param[in] aSize The size of option in bytes. - * - */ - void SetSize(uint16_t aSize) { mLength = static_cast((aSize + kLengthUnit - 1) / kLengthUnit); } - - /** - * This method returns the size of the option in bytes. - * - * @returns The size of the option in bytes. - * - */ - uint16_t GetSize(void) const { return mLength * kLengthUnit; } - - /** - * This method sets the length of the option (in unit of 8 bytes). - * - * @param[in] aLength The length of the option in unit of 8 bytes. - * - */ - void SetLength(uint8_t aLength) { mLength = aLength; } - - /** - * This method returns the length of the option (in unit of 8 bytes). - * - * @returns The length of the option in unit of 8 bytes. - * - */ - uint16_t GetLength(void) const { return mLength; } - - /** - * This helper method returns a pointer to the next valid option in the buffer. - * - * @param[in] aCurOption The current option. Use `nullptr` to get the first option. - * @param[in] aBuffer The buffer within which the options are held. - * @param[in] aBufferLength The length of the buffer. - * - * @returns A pointer to the next option if there are a valid one. Otherwise, `nullptr`. - * - */ - static const Option *GetNextOption(const Option *aCurOption, const uint8_t *aBuffer, uint16_t aBufferLength); - - /** - * This method indicates whether or not this option is valid. - * - * @retval TRUE The option is valid. - * @retval FALSE The option is not valid. - * - */ - bool IsValid(void) const { return mLength > 0; } - -private: - Type mType; // Type of the option. - uint8_t mLength; // Length of the option in unit of 8 octets, including the `mType` and `mLength` fields. -} OT_TOOL_PACKED_END; - -/** - * This class represents the Prefix Information Option. - * - * See section 4.6.2 of RFC 4861 for definition of this option [https://tools.ietf.org/html/rfc4861#section-4.6.2] - * - */ -OT_TOOL_PACKED_BEGIN -class PrefixInfoOption : public Option, private Clearable -{ -public: - static constexpr Type kType = Type::kPrefixInfo; ///< Prefix Information Option Type. - - /** - * This method initializes the Prefix Info option with proper type and length and sets all other fields to zero. - * - */ - void Init(void); - - /** - * This method indicates whether or not the on-link flag is set. - * - * @retval TRUE The on-link flag is set. - * @retval FALSE The on-link flag is not set. - * - */ - bool IsOnLinkFlagSet(void) const { return (mFlags & kOnLinkFlagMask) != 0; } - - /** - * This method sets the on-link (L) flag. - * - */ - void SetOnLinkFlag(void) { mFlags |= kOnLinkFlagMask; } - - /** - * This method clears the on-link (L) flag. - * - */ - void ClearOnLinkFlag(void) { mFlags &= ~kOnLinkFlagMask; } - - /** - * This method indicates whether or not the autonomous address-configuration (A) flag is set. - * - * @retval TRUE The auto address-config flag is set. - * @retval FALSE The auto address-config flag is not set. - * - */ - bool IsAutoAddrConfigFlagSet(void) const { return (mFlags & kAutoConfigFlagMask) != 0; } - - /** - * This method sets the autonomous address-configuration (A) flag. - * - */ - void SetAutoAddrConfigFlag(void) { mFlags |= kAutoConfigFlagMask; } - - /** - * This method clears the autonomous address-configuration (A) flag. - * - */ - void ClearAutoAddrConfigFlag(void) { mFlags &= ~kAutoConfigFlagMask; } - - /** - * This method sets the valid lifetime of the prefix in seconds. - * - * @param[in] aValidLifetime The valid lifetime in seconds. - * - */ - void SetValidLifetime(uint32_t aValidLifetime) { mValidLifetime = HostSwap32(aValidLifetime); } - - /** - * THis method gets the valid lifetime of the prefix in seconds. - * - * @returns The valid lifetime in seconds. - * - */ - uint32_t GetValidLifetime(void) const { return HostSwap32(mValidLifetime); } - - /** - * This method sets the preferred lifetime of the prefix in seconds. - * - * @param[in] aPreferredLifetime The preferred lifetime in seconds. - * - */ - void SetPreferredLifetime(uint32_t aPreferredLifetime) { mPreferredLifetime = HostSwap32(aPreferredLifetime); } - - /** - * THis method returns the preferred lifetime of the prefix in seconds. - * - * @returns The preferred lifetime in seconds. - * - */ - uint32_t GetPreferredLifetime(void) const { return HostSwap32(mPreferredLifetime); } - - /** - * This method sets the prefix. - * - * @param[in] aPrefix The prefix contained in this option. - * - */ - void SetPrefix(const Ip6::Prefix &aPrefix); - - /** - * This method gets the prefix in this option. - * - * @param[out] aPrefix Reference to an `Ip6::Prefix` to return the prefix. - * - */ - void GetPrefix(Ip6::Prefix &aPrefix) const; - - /** - * This method indicates whether or not the option is valid. - * - * @retval TRUE The option is valid - * @retval FALSE The option is not valid. - * - */ - bool IsValid(void) const; - - PrefixInfoOption(void) = delete; - -private: - // Prefix Information Option - // - // 0 1 2 3 - // 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 - // +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - // | Type | Length | Prefix Length |L|A| Reserved1 | - // +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - // | Valid Lifetime | - // +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - // | Preferred Lifetime | - // +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - // | Reserved2 | - // +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - // | | - // + + - // | | - // + Prefix + - // | | - // + + - // | | - // +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - - static constexpr uint8_t kAutoConfigFlagMask = 0x40; // Autonomous address-configuration flag. - static constexpr uint8_t kOnLinkFlagMask = 0x80; // On-link flag. - - uint8_t mPrefixLength; // The prefix length in bits. - uint8_t mFlags; // The flags field. - uint32_t mValidLifetime; // The valid lifetime of the prefix. - uint32_t mPreferredLifetime; // The preferred lifetime of the prefix. - uint32_t mReserved2; // The reserved field. - Ip6::Address mPrefix; // The prefix. -} OT_TOOL_PACKED_END; - -static_assert(sizeof(PrefixInfoOption) == 32, "invalid PrefixInfoOption structure"); - -/** - * This class represents the Route Information Option. - * - * See section 2.3 of RFC 4191 for definition of this option. [https://tools.ietf.org/html/rfc4191#section-2.3] - * - */ -OT_TOOL_PACKED_BEGIN -class RouteInfoOption : public Option, private Clearable -{ -public: - static constexpr uint16_t kMinSize = kLengthUnit; ///< Minimum size (in bytes) of a Route Info Option - static constexpr Type kType = Type::kRouteInfo; ///< Route Information Option Type. - - /** - * This method initializes the option setting the type and clearing (setting to zero) all other fields. - * - */ - void Init(void); - - /** - * This method sets the route preference. - * - * @param[in] aPreference The route preference. - * - */ - void SetPreference(RoutePreference aPreference); - - /** - * This method gets the route preference. - * - * @returns The route preference. - * - */ - RoutePreference GetPreference(void) const; - - /** - * This method sets the lifetime of the route in seconds. - * - * @param[in] aLifetime The lifetime of the route in seconds. - * - */ - void SetRouteLifetime(uint32_t aLifetime) { mRouteLifetime = HostSwap32(aLifetime); } - - /** - * This method gets Route Lifetime in seconds. - * - * @returns The Route Lifetime in seconds. - * - */ - uint32_t GetRouteLifetime(void) const { return HostSwap32(mRouteLifetime); } - - /** - * This method sets the prefix and adjusts the option length based on the prefix length. - * - * @param[in] aPrefix The prefix contained in this option. - * - */ - void SetPrefix(const Ip6::Prefix &aPrefix); - - /** - * This method gets the prefix in this option. - * - * @param[out] aPrefix Reference to an `Ip6::Prefix` to return the prefix. - * - */ - void GetPrefix(Ip6::Prefix &aPrefix) const; - - /** - * This method tells whether this option is valid. - * - * @returns A boolean indicates whether this option is valid. - * - */ - bool IsValid(void) const; - - /** - * This static method calculates the minimum option length for a given prefix length. - * - * The option length (which is in unit of 8 octets) can be 1, 2, or 3 depending on the prefix length. It can be 1 - * for a zero prefix length, 2 if the prefix length is not greater than 64, and 3 otherwise. - * - * @param[in] aPrefixLength The prefix length (in bits). - * - * @returns The option length (in unit of 8 octet) for @p aPrefixLength. - * - */ - static uint8_t OptionLengthForPrefix(uint8_t aPrefixLength); - - /** - * This static method calculates the minimum option size (in bytes) for a given prefix length. - * - * @param[in] aPrefixLength The prefix length (in bits). - * - * @returns The option size (in bytes) for @p aPrefixLength. - * - */ - static uint16_t OptionSizeForPrefix(uint8_t aPrefixLength) - { - return kLengthUnit * OptionLengthForPrefix(aPrefixLength); - } - - RouteInfoOption(void) = delete; - -private: - // Route Information Option - // - // 0 1 2 3 - // 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 - // +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - // | Type | Length | Prefix Length |Resvd|Prf|Resvd| - // +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - // | Route Lifetime | - // +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - // | Prefix (Variable Length) | - // . . - // . . - // +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - - static constexpr uint8_t kPreferenceOffset = 3; - static constexpr uint8_t kPreferenceMask = 3 << kPreferenceOffset; - - uint8_t * GetPrefixBytes(void) { return AsNonConst(AsConst(this)->GetPrefixBytes()); } - const uint8_t *GetPrefixBytes(void) const { return reinterpret_cast(this) + sizeof(*this); } - - uint8_t mPrefixLength; // The prefix length in bits. - uint8_t mResvdPrf; // The preference. - uint32_t mRouteLifetime; // The lifetime in seconds. - // Followed by prefix bytes (variable length). - -} OT_TOOL_PACKED_END; - -static_assert(sizeof(RouteInfoOption) == 8, "invalid RouteInfoOption structure"); - -/** - * This class implements the Router Advertisement message header. - * - * See section 2.2 of RFC 4191 [https://datatracker.ietf.org/doc/html/rfc4191] - * - */ -OT_TOOL_PACKED_BEGIN -class RouterAdvMessage : public Equatable, private Clearable -{ -public: - /** - * This constructor initializes the Router Advertisement message with - * zero router lifetime, reachable time and retransmission timer. - * - */ - RouterAdvMessage(void) { SetToDefault(); } - - /** - * This method sets the RA message to default values. - * - */ - void SetToDefault(void); - - /** - * This method sets the checksum value. - * - * @param[in] aChecksum The checksum value. - * - */ - void SetChecksum(uint16_t aChecksum) { mChecksum = HostSwap16(aChecksum); } - - /** - * This method sets the Router Lifetime in seconds. - * - * @param[in] aRouterLifetime The router lifetime in seconds. - * - */ - void SetRouterLifetime(uint16_t aRouterLifetime) { mRouterLifetime = HostSwap16(aRouterLifetime); } - - /** - * This method gets the Router Lifetime (in seconds). - * - * Router Lifetime set to zero indicates that the sender is not a default router. - * - * @returns The router lifetime in seconds. - * - */ - uint16_t GetRouterLifetime(void) const { return HostSwap16(mRouterLifetime); } - - /** - * This method sets the default router preference. - * - * @param[in] aPreference The router preference. - * - */ - void SetDefaultRouterPreference(RoutePreference aPreference); - - /** - * This method gets the default router preference. - * - * @returns The router preference. - * - */ - RoutePreference GetDefaultRouterPreference(void) const; - -private: - // Router Advertisement Message - // - // 0 1 2 3 - // 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 - // +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - // | Type | Code | Checksum | - // +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - // | Cur Hop Limit |M|O|H|Prf|Resvd| Router Lifetime | - // +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - // | Reachable Time | - // +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - // | Retrans Timer | - // +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - // | Options ... - // +-+-+-+-+-+-+-+-+-+-+-+- - - static constexpr uint8_t kPreferenceOffset = 3; - static constexpr uint8_t kPreferenceMask = 3 << kPreferenceOffset; - - uint8_t mType; - uint8_t mCode; - uint16_t mChecksum; - uint8_t mCurHopLimit; - uint8_t mFlags; - uint16_t mRouterLifetime; - uint32_t mReachableTime; - uint32_t mRetransTimer; -} OT_TOOL_PACKED_END; - -static_assert(sizeof(RouterAdvMessage) == 16, "invalid RouterAdvMessage structure"); - -/** - * This class implements the Router Solicitation message. - * - * See section 4.1 of RFC 4861 for definition of this message. - * https://tools.ietf.org/html/rfc4861#section-4.1 - * - */ -OT_TOOL_PACKED_BEGIN -class RouterSolicitMessage -{ -public: - /** - * This constructor initializes the Router Solicitation message. - * - */ - RouterSolicitMessage(void); - -private: - Ip6::Icmp::Header mHeader; // The common ICMPv6 header. -} OT_TOOL_PACKED_END; - -static_assert(sizeof(RouterSolicitMessage) == 8, "invalid RouterSolicitMessage structure"); - -} // namespace RouterAdv -} // namespace BorderRouter -} // namespace ot - -#endif // OPENTHREAD_CONFIG_BORDER_ROUTING_ENABLE - -#endif // ROUTER_ADVERTISEMENT_HPP_ diff --git a/util/third_party/openthread/src/core/border_router/routing_manager.cpp b/util/third_party/openthread/src/core/border_router/routing_manager.cpp index 1ea7059f6b..3645f33078 100644 --- a/util/third_party/openthread/src/core/border_router/routing_manager.cpp +++ b/util/third_party/openthread/src/core/border_router/routing_manager.cpp @@ -64,12 +64,14 @@ RoutingManager::RoutingManager(Instance &aInstance) , mIsRunning(false) , mIsEnabled(false) , mInfraIf(aInstance) + , mLocalOmrPrefix(aInstance) + , mRouteInfoOptionPreference(NetworkData::kRoutePreferenceMedium) , mIsAdvertisingLocalOnLinkPrefix(false) , mOnLinkPrefixDeprecateTimer(aInstance, HandleOnLinkPrefixDeprecateTimer) , mIsAdvertisingLocalNat64Prefix(false) + , mDiscoveredPrefixTable(aInstance) , mTimeRouterAdvMessageLastUpdate(TimerMilli::GetNow()) , mLearntRouterAdvMessageFromHost(false) - , mDiscoveredPrefixInvalidTimer(aInstance, HandleDiscoveredPrefixInvalidTimer) , mDiscoveredPrefixStaleTimer(aInstance, HandleDiscoveredPrefixStaleTimer) , mRouterAdvertisementCount(0) , mLastRouterAdvertisementSendTime(TimerMilli::GetNow() - kMinDelayBetweenRtrAdvs) @@ -77,9 +79,9 @@ RoutingManager::RoutingManager(Instance &aInstance) , mRouterSolicitCount(0) , mRoutingPolicyTimer(aInstance, HandleRoutingPolicyTimer) { - mBrUlaPrefix.Clear(); + mFavoredDiscoveredOnLinkPrefix.Clear(); - mLocalOmrPrefix.Clear(); + mBrUlaPrefix.Clear(); mLocalOnLinkPrefix.Clear(); @@ -93,7 +95,7 @@ Error RoutingManager::Init(uint32_t aInfraIfIndex, bool aInfraIfIsRunning) SuccessOrExit(error = mInfraIf.Init(aInfraIfIndex)); SuccessOrExit(error = LoadOrGenerateRandomBrUlaPrefix()); - GenerateOmrPrefix(); + mLocalOmrPrefix.GenerateFrom(mBrUlaPrefix); #if OPENTHREAD_CONFIG_BORDER_ROUTING_NAT64_ENABLE GenerateNat64Prefix(); #endif @@ -125,12 +127,25 @@ Error RoutingManager::SetEnabled(bool aEnabled) return error; } +void RoutingManager::SetRouteInfoOptionPreference(RoutePreference aPreference) +{ + VerifyOrExit(mRouteInfoOptionPreference != aPreference); + + mRouteInfoOptionPreference = aPreference; + + VerifyOrExit(mIsRunning); + StartRoutingPolicyEvaluationJitter(kRoutingPolicyEvaluationJitter); + +exit: + return; +} + Error RoutingManager::GetOmrPrefix(Ip6::Prefix &aPrefix) { Error error = kErrorNone; VerifyOrExit(IsInitialized(), error = kErrorInvalidState); - aPrefix = mLocalOmrPrefix; + aPrefix = mLocalOmrPrefix.GetPrefix(); exit: return error; @@ -193,15 +208,6 @@ Error RoutingManager::LoadOrGenerateRandomBrUlaPrefix(void) return error; } -void RoutingManager::GenerateOmrPrefix(void) -{ - mLocalOmrPrefix = mBrUlaPrefix; - mLocalOmrPrefix.SetSubnetId(kOmrPrefixSubnetId); - mLocalOmrPrefix.SetLength(kOmrPrefixLength); - - LogInfo("Generated OMR prefix: %s", mLocalOmrPrefix.ToString().AsCString()); -} - #if OPENTHREAD_CONFIG_BORDER_ROUTING_NAT64_ENABLE void RoutingManager::GenerateNat64Prefix(void) { @@ -247,6 +253,7 @@ void RoutingManager::Start(void) LogInfo("Border Routing manager started"); mIsRunning = true; + UpdateDiscoveredPrefixTableOnNetDataChange(); StartRouterSolicitationDelay(); } } @@ -255,7 +262,9 @@ void RoutingManager::Stop(void) { VerifyOrExit(mIsRunning); - UnpublishLocalOmrPrefix(); + mLocalOmrPrefix.RemoveFromNetData(); + + mFavoredDiscoveredOnLinkPrefix.Clear(); if (mIsAdvertisingLocalOnLinkPrefix) { @@ -279,9 +288,7 @@ void RoutingManager::Stop(void) mAdvertisedOmrPrefixes.Clear(); mOnLinkPrefixDeprecateTimer.Stop(); - InvalidateAllDiscoveredPrefixes(); - mDiscoveredPrefixes.Clear(); - mDiscoveredPrefixInvalidTimer.Stop(); + mDiscoveredPrefixTable.RemoveAllEntries(); mDiscoveredPrefixStaleTimer.Stop(); mRouterAdvertisementCount = 0; @@ -334,8 +341,7 @@ void RoutingManager::HandleNotifierEvents(Events aEvents) if (mIsRunning && aEvents.Contains(kEventThreadNetdataChanged)) { - // Invalidate discovered prefixes because OMR Prefixes in Network Data may change. - InvalidateDiscoveredPrefixes(); + UpdateDiscoveredPrefixTableOnNetDataChange(); StartRoutingPolicyEvaluationJitter(kRoutingPolicyEvaluationJitter); } @@ -361,149 +367,142 @@ void RoutingManager::HandleNotifierEvents(Events aEvents) return; } +void RoutingManager::UpdateDiscoveredPrefixTableOnNetDataChange(void) +{ + NetworkData::Iterator iterator = NetworkData::kIteratorInit; + NetworkData::OnMeshPrefixConfig prefixConfig; + bool foundDefRouteOmrPrefix = false; + + // Remove all OMR prefixes in Network Data from the + // discovered prefix table. Also check if we have + // an OMR prefix with default route flag. + + while (Get().GetNextOnMeshPrefix(iterator, prefixConfig) == kErrorNone) + { + if (!IsValidOmrPrefix(prefixConfig)) + { + continue; + } + + mDiscoveredPrefixTable.RemoveRoutePrefix(prefixConfig.GetPrefix(), + DiscoveredPrefixTable::kUnpublishFromNetData); + + if (prefixConfig.mDefaultRoute) + { + foundDefRouteOmrPrefix = true; + } + } + + // If we find an OMR prefix with default route flag, it indicates + // that this prefix can be used with default route (routable beyond + // infra link). + // + // `DiscoveredPrefixTable` will always track which routers provide + // default route when processing received RA messages, but only + // if we see an OMR prefix with default route flag, we allow it + // to publish the discovered default route (as ::/0 external + // route) in Network Data. + + mDiscoveredPrefixTable.SetAllowDefaultRouteInNetData(foundDefRouteOmrPrefix); +} + void RoutingManager::EvaluateOmrPrefix(OmrPrefixArray &aNewOmrPrefixes) { NetworkData::Iterator iterator = NetworkData::kIteratorInit; NetworkData::OnMeshPrefixConfig onMeshPrefixConfig; - Ip6::Prefix * electedOmrPrefix = nullptr; - signed int electedOmrPrefixPreference = 0; - Ip6::Prefix * publishedLocalOmrPrefix = nullptr; + OmrPrefix * favoredOmrEntry = nullptr; + OmrPrefix * localOmrEntry = nullptr; OT_ASSERT(mIsRunning); while (Get().GetNextOnMeshPrefix(iterator, onMeshPrefixConfig) == kErrorNone) { - const Ip6::Prefix &prefix = onMeshPrefixConfig.GetPrefix(); + OmrPrefix *entry; if (!IsValidOmrPrefix(onMeshPrefixConfig)) { continue; } - if (aNewOmrPrefixes.Contains(prefix)) + entry = aNewOmrPrefixes.FindMatching(onMeshPrefixConfig.GetPrefix()); + + if (entry != nullptr) { - // Ignore duplicate prefixes. - continue; - } + // Update the entry if we find the same prefix with higher + // preference in network data + + if (onMeshPrefixConfig.GetPreference() <= entry->GetPreference()) + { + continue; + } - if (aNewOmrPrefixes.PushBack(prefix) != kErrorNone) + entry->SetPreference(onMeshPrefixConfig.GetPreference()); + } + else { - LogWarn("EvaluateOmrPrefix: Too many OMR prefixes, ignoring prefix %s", prefix.ToString().AsCString()); - continue; + entry = aNewOmrPrefixes.PushBack(); + + if (entry == nullptr) + { + LogWarn("EvaluateOmrPrefix: Too many OMR prefixes, ignoring prefix %s", + onMeshPrefixConfig.GetPrefix().ToString().AsCString()); + continue; + } + + entry->InitFrom(onMeshPrefixConfig); } if (onMeshPrefixConfig.mPreferred) { - if (electedOmrPrefix == nullptr || onMeshPrefixConfig.mPreference > electedOmrPrefixPreference || - (onMeshPrefixConfig.mPreference == electedOmrPrefixPreference && prefix < *electedOmrPrefix)) + if ((favoredOmrEntry == nullptr) || (entry->IsFavoredOver(*favoredOmrEntry))) { - electedOmrPrefix = aNewOmrPrefixes.Back(); - electedOmrPrefixPreference = onMeshPrefixConfig.mPreference; + favoredOmrEntry = entry; } } - if (prefix == mLocalOmrPrefix) + if (entry->GetPrefix() == mLocalOmrPrefix.GetPrefix()) { - publishedLocalOmrPrefix = aNewOmrPrefixes.Back(); + localOmrEntry = entry; } } // Decide if we need to add or remove our local OMR prefix. - if (electedOmrPrefix == nullptr) + if (favoredOmrEntry == nullptr) { - LogInfo("EvaluateOmrPrefix: No preferred OMR prefixes found in Thread network"); - - if (PublishLocalOmrPrefix() == kErrorNone) - { - IgnoreError(aNewOmrPrefixes.PushBack(mLocalOmrPrefix)); - } + LogInfo("EvaluateOmrPrefix: No preferred OMR prefix found in Thread network"); // The `aNewOmrPrefixes` remains empty if we fail to publish // the local OMR prefix. - } - else - { - if (*electedOmrPrefix == mLocalOmrPrefix) - { - IgnoreError(PublishLocalOmrPrefix()); - } - else if (IsOmrPrefixAddedToLocalNetworkData()) - { - LogInfo("EvaluateOmrPrefix: There is already a preferred OMR prefix %s (pref=%d) in the Thread network", - electedOmrPrefix->ToString().AsCString(), electedOmrPrefixPreference); + SuccessOrExit(mLocalOmrPrefix.AddToNetData()); - UnpublishLocalOmrPrefix(); + if (localOmrEntry == nullptr) + { + localOmrEntry = aNewOmrPrefixes.PushBack(); + VerifyOrExit(localOmrEntry != nullptr); - // Remove the local OMR prefix from the list by overwriting it - // with the last element and then popping it from the list. - if (publishedLocalOmrPrefix != nullptr) - { - *publishedLocalOmrPrefix = *aNewOmrPrefixes.Back(); - aNewOmrPrefixes.PopBack(); - } + localOmrEntry->Init(mLocalOmrPrefix.GetPrefix(), NetworkData::kRoutePreferenceLow); } } -} - -Error RoutingManager::PublishLocalOmrPrefix(void) -{ - Error error = kErrorNone; - NetworkData::OnMeshPrefixConfig omrPrefixConfig; - - OT_ASSERT(mIsRunning); - - VerifyOrExit(!IsOmrPrefixAddedToLocalNetworkData()); - - omrPrefixConfig.Clear(); - omrPrefixConfig.mPrefix = mLocalOmrPrefix; - omrPrefixConfig.mStable = true; - omrPrefixConfig.mSlaac = true; - omrPrefixConfig.mPreferred = true; - omrPrefixConfig.mOnMesh = true; - omrPrefixConfig.mDefaultRoute = false; - omrPrefixConfig.mPreference = NetworkData::kRoutePreferenceMedium; - - error = Get().AddOnMeshPrefix(omrPrefixConfig); - if (error != kErrorNone) + else if (favoredOmrEntry == localOmrEntry) { - LogWarn("Failed to publish local OMR prefix %s in Thread network: %s", mLocalOmrPrefix.ToString().AsCString(), - ErrorToString(error)); + IgnoreError(mLocalOmrPrefix.AddToNetData()); } - else + else if (mLocalOmrPrefix.IsAddedInNetData()) { - Get().HandleServerDataUpdated(); - LogInfo("Publishing local OMR prefix %s in Thread network", mLocalOmrPrefix.ToString().AsCString()); - } - -exit: - return error; -} - -void RoutingManager::UnpublishLocalOmrPrefix(void) -{ - Error error = kErrorNone; - - VerifyOrExit(mIsRunning); - - VerifyOrExit(IsOmrPrefixAddedToLocalNetworkData()); + LogInfo("EvaluateOmrPrefix: There is already a preferred OMR prefix %s in the Thread network", + favoredOmrEntry->ToString().AsCString()); - SuccessOrExit(error = Get().RemoveOnMeshPrefix(mLocalOmrPrefix)); - - Get().HandleServerDataUpdated(); - LogInfo("Unpublishing local OMR prefix %s from Thread network", mLocalOmrPrefix.ToString().AsCString()); + mLocalOmrPrefix.RemoveFromNetData(); -exit: - if (error != kErrorNone && error != kErrorNotFound) - { - LogWarn("Failed to unpublish local OMR prefix %s from Thread network: %s", - mLocalOmrPrefix.ToString().AsCString(), ErrorToString(error)); + if (localOmrEntry != nullptr) + { + aNewOmrPrefixes.Remove(*localOmrEntry); + } } -} -bool RoutingManager::IsOmrPrefixAddedToLocalNetworkData(void) const -{ - return Get().ContainsOnMeshPrefix(mLocalOmrPrefix); +exit: + return; } Error RoutingManager::PublishExternalRoute(const Ip6::Prefix &aPrefix, RoutePreference aRoutePreference, bool aNat64) @@ -526,21 +525,13 @@ Error RoutingManager::PublishExternalRoute(const Ip6::Prefix &aPrefix, RoutePref LogWarn("Failed to publish external route %s: %s", aPrefix.ToString().AsCString(), ErrorToString(error)); } - return (error == kErrorAlready) ? kErrorNone : error; + return error; } void RoutingManager::UnpublishExternalRoute(const Ip6::Prefix &aPrefix) { - Error error = kErrorNone; - VerifyOrExit(mIsRunning); - - error = Get().UnpublishPrefix(aPrefix); - - if (error != kErrorNone) - { - LogWarn("Failed to unpublish route %s: %s", aPrefix.ToString().AsCString(), ErrorToString(error)); - } + IgnoreError(Get().UnpublishPrefix(aPrefix)); exit: return; @@ -548,67 +539,51 @@ void RoutingManager::UnpublishExternalRoute(const Ip6::Prefix &aPrefix) void RoutingManager::EvaluateOnLinkPrefix(void) { - const Ip6::Prefix *smallestOnLinkPrefix = nullptr; - - // We don't evaluate on-link prefix if we are doing Router Solicitation. VerifyOrExit(!IsRouterSolicitationInProgress()); - for (const ExternalPrefix &prefix : mDiscoveredPrefixes) - { - if (!prefix.IsOnLinkPrefix() || prefix.IsDeprecated()) - { - continue; - } - - if (smallestOnLinkPrefix == nullptr || (prefix.GetPrefix() < *smallestOnLinkPrefix)) - { - smallestOnLinkPrefix = &prefix.GetPrefix(); - } - } + mDiscoveredPrefixTable.FindFavoredOnLinkPrefix(mFavoredDiscoveredOnLinkPrefix); - // We start advertising our local on-link prefix if there is no existing one. - if (smallestOnLinkPrefix == nullptr) + if (mFavoredDiscoveredOnLinkPrefix.GetLength() == 0) { - if (!mIsAdvertisingLocalOnLinkPrefix && - (PublishExternalRoute(mLocalOnLinkPrefix, NetworkData::kRoutePreferenceMedium) == kErrorNone)) - { - mIsAdvertisingLocalOnLinkPrefix = true; - LogInfo("Start advertising on-link prefix %s on %s", mLocalOnLinkPrefix.ToString().AsCString(), - mInfraIf.ToString().AsCString()); - - // We go through `mDiscoveredPrefixes` list to check if the - // local on-link prefix was previously discovered and - // included in the list and if so we remove it from list. - // - // Note that `UpdateDiscoveredOnLinkPrefix()` will also - // check and not add local on-link prefix in the discovered - // prefix list while we are advertising the local on-link - // prefix. - - for (ExternalPrefix &prefix : mDiscoveredPrefixes) - { - if (prefix.IsOnLinkPrefix() && mLocalOnLinkPrefix == prefix.GetPrefix()) - { - // To remove the prefix from the list, we copy the - // popped last entry into `prefix` entry. - prefix = *mDiscoveredPrefixes.PopBack(); - break; - } - } - } + // We need to advertise our local on-link prefix since there is + // no discovered on-link prefix. mOnLinkPrefixDeprecateTimer.Stop(); + VerifyOrExit(!mIsAdvertisingLocalOnLinkPrefix); + + SuccessOrExit(PublishExternalRoute(mLocalOnLinkPrefix, NetworkData::kRoutePreferenceMedium)); + + mIsAdvertisingLocalOnLinkPrefix = true; + LogInfo("Start advertising on-link prefix %s on %s", mLocalOnLinkPrefix.ToString().AsCString(), + mInfraIf.ToString().AsCString()); + + // We remove the local on-link prefix from discovered prefix + // table, in case it was previously discovered and included in + // the table (now as a deprecating entry). We remove it with + // `kKeepInNetData` flag to ensure that the prefix is not + // unpublished from network data. + // + // Note that `ShouldProcessPrefixInfoOption()` will also check + // not allow the local on-link prefix to be added in the prefix + // table while we are advertising it. + + mDiscoveredPrefixTable.RemoveOnLinkPrefix(mLocalOnLinkPrefix, DiscoveredPrefixTable::kKeepInNetData); } - // When an application-specific on-link prefix is received and it is bigger than the - // advertised prefix, we will not remove the advertised prefix. In this case, there - // will be two on-link prefixes on the infra link. But all BRs will still converge to - // the same smallest on-link prefix and the application-specific prefix is not used. - else if (mIsAdvertisingLocalOnLinkPrefix) + else { - if (!(mLocalOnLinkPrefix < *smallestOnLinkPrefix)) + VerifyOrExit(mIsAdvertisingLocalOnLinkPrefix); + + // When an application-specific on-link prefix is received and + // it is larger than the local prefix, we will not remove the + // advertised local prefix. In this case, there will be two + // on-link prefixes on the infra link. But all BRs will still + // converge to the same smallest/favored on-link prefix and the + // application-specific prefix is not used. + + if (!(mLocalOnLinkPrefix < mFavoredDiscoveredOnLinkPrefix)) { - LogInfo("EvaluateOnLinkPrefix: There is already smaller on-link prefix %s on %s", - smallestOnLinkPrefix->ToString().AsCString(), mInfraIf.ToString().AsCString()); + LogInfo("EvaluateOnLinkPrefix: There is already favored on-link prefix %s on %s", + mFavoredDiscoveredOnLinkPrefix.ToString().AsCString(), mInfraIf.ToString().AsCString()); DeprecateOnLinkPrefix(); } } @@ -624,22 +599,11 @@ void RoutingManager::HandleOnLinkPrefixDeprecateTimer(Timer &aTimer) void RoutingManager::HandleOnLinkPrefixDeprecateTimer(void) { - bool discoveredLocalOnLinkPrefix = false; - OT_ASSERT(!mIsAdvertisingLocalOnLinkPrefix); LogInfo("Local on-link prefix %s expired", mLocalOnLinkPrefix.ToString().AsCString()); - for (const ExternalPrefix &prefix : mDiscoveredPrefixes) - { - if (prefix.IsOnLinkPrefix() && prefix.GetPrefix() == mLocalOnLinkPrefix) - { - discoveredLocalOnLinkPrefix = true; - break; - } - } - - if (!discoveredLocalOnLinkPrefix) + if (!mDiscoveredPrefixTable.ContainsOnLinkPrefix(mLocalOnLinkPrefix)) { UnpublishExternalRoute(mLocalOnLinkPrefix); } @@ -803,9 +767,9 @@ bool RoutingManager::IsRouterSolicitationInProgress(void) const Error RoutingManager::SendRouterSolicitation(void) { - Ip6::Address destAddress; - RouterAdv::RouterSolicitMessage routerSolicit; - InfraIf::Icmp6Packet packet; + Ip6::Address destAddress; + Ip6::Nd::RouterSolicitMessage routerSolicit; + InfraIf::Icmp6Packet packet; OT_ASSERT(IsInitialized()); @@ -815,126 +779,76 @@ Error RoutingManager::SendRouterSolicitation(void) return mInfraIf.Send(packet, destAddress); } -// This method sends Router Advertisement messages to advertise on-link prefix and route for OMR prefix. -// @param[in] aNewOmrPrefixes An array of the new OMR prefixes to be advertised. -// Empty array means we should stop advertising OMR prefixes. void RoutingManager::SendRouterAdvertisement(const OmrPrefixArray &aNewOmrPrefixes) { - uint8_t buffer[kMaxRouterAdvMessageLength]; - uint16_t bufferLength = 0; - - static_assert(sizeof(mRouterAdvMessage) <= sizeof(buffer), "RA buffer too small"); - memcpy(buffer, &mRouterAdvMessage, sizeof(mRouterAdvMessage)); - bufferLength += sizeof(mRouterAdvMessage); - - if (mIsAdvertisingLocalOnLinkPrefix) - { - RouterAdv::PrefixInfoOption *pio; - - OT_ASSERT(bufferLength + sizeof(RouterAdv::PrefixInfoOption) <= sizeof(buffer)); - - pio = reinterpret_cast(buffer + bufferLength); - - pio->Init(); - pio->SetOnLinkFlag(); - pio->SetAutoAddrConfigFlag(); - pio->SetValidLifetime(kDefaultOnLinkPrefixLifetime); - pio->SetPreferredLifetime(kDefaultOnLinkPrefixLifetime); - pio->SetPrefix(mLocalOnLinkPrefix); + uint8_t buffer[kMaxRouterAdvMessageLength]; + Ip6::Nd::RouterAdvertMessage raMsg(mRouterAdvertHeader, buffer); - bufferLength += pio->GetSize(); + // Append PIO for local on-link prefix. Ensure it is either being + // advertised or deprecated. - LogInfo("Send on-link prefix %s in PIO (preferred lifetime = %u seconds, valid lifetime = %u seconds)", - mLocalOnLinkPrefix.ToString().AsCString(), pio->GetPreferredLifetime(), pio->GetValidLifetime()); - - mTimeAdvertisedOnLinkPrefix = TimerMilli::GetNow(); - } - else if (mOnLinkPrefixDeprecateTimer.IsRunning()) + if (mIsAdvertisingLocalOnLinkPrefix || mOnLinkPrefixDeprecateTimer.IsRunning()) { - RouterAdv::PrefixInfoOption *pio; - - OT_ASSERT(bufferLength + sizeof(RouterAdv::PrefixInfoOption) <= sizeof(buffer)); - - pio = reinterpret_cast(buffer + bufferLength); + uint32_t validLifetime = kDefaultOnLinkPrefixLifetime; + uint32_t preferredLifetime = kDefaultOnLinkPrefixLifetime; - pio->Init(); - pio->SetOnLinkFlag(); - pio->SetAutoAddrConfigFlag(); - pio->SetValidLifetime(TimeMilli::MsecToSec(mOnLinkPrefixDeprecateTimer.GetFireTime() - TimerMilli::GetNow())); + if (mOnLinkPrefixDeprecateTimer.IsRunning()) + { + validLifetime = TimeMilli::MsecToSec(mOnLinkPrefixDeprecateTimer.GetFireTime() - TimerMilli::GetNow()); + preferredLifetime = 0; + } - // Set zero preferred lifetime to immediately deprecate the advertised on-link prefix. - pio->SetPreferredLifetime(0); - pio->SetPrefix(mLocalOnLinkPrefix); + SuccessOrAssert(raMsg.AppendPrefixInfoOption(mLocalOnLinkPrefix, validLifetime, preferredLifetime)); - bufferLength += pio->GetSize(); + if (mIsAdvertisingLocalOnLinkPrefix) + { + mTimeAdvertisedOnLinkPrefix = TimerMilli::GetNow(); + } - LogInfo("Send on-link prefix %s in PIO (preferred lifetime = %u seconds, valid lifetime = %u seconds)", - mLocalOnLinkPrefix.ToString().AsCString(), pio->GetPreferredLifetime(), pio->GetValidLifetime()); + LogInfo("RouterAdvert: Added PIO for %s (valid=%u, preferred=%u)", mLocalOnLinkPrefix.ToString().AsCString(), + validLifetime, preferredLifetime); } - // Invalidate the advertised OMR prefixes if they are no longer in the new OMR prefix array. + // Invalidate previously advertised OMR prefixes if they are no + // longer in the new OMR prefix array. - for (const Ip6::Prefix &advertisedOmrPrefix : mAdvertisedOmrPrefixes) + for (const OmrPrefix &omrPrefix : mAdvertisedOmrPrefixes) { - if (!aNewOmrPrefixes.Contains(advertisedOmrPrefix)) + if (!aNewOmrPrefixes.ContainsMatching(omrPrefix.GetPrefix())) { - RouterAdv::RouteInfoOption *rio; - - OT_ASSERT(bufferLength + RouterAdv::RouteInfoOption::OptionSizeForPrefix(advertisedOmrPrefix.GetLength()) <= - sizeof(buffer)); - - rio = reinterpret_cast(buffer + bufferLength); - - // Set zero route lifetime to immediately invalidate the advertised OMR prefix. - rio->Init(); - rio->SetRouteLifetime(0); - rio->SetPrefix(advertisedOmrPrefix); + SuccessOrAssert( + raMsg.AppendRouteInfoOption(omrPrefix.GetPrefix(), /* aRouteLifetime */ 0, mRouteInfoOptionPreference)); - bufferLength += rio->GetSize(); - - LogInfo("Stop advertising OMR prefix %s on %s", advertisedOmrPrefix.ToString().AsCString(), - mInfraIf.ToString().AsCString()); + LogInfo("RouterAdvert: Added RIO for %s (lifetime=0)", omrPrefix.GetPrefix().ToString().AsCString()); } } - for (const Ip6::Prefix &newOmrPrefix : aNewOmrPrefixes) + for (const OmrPrefix &omrPrefix : aNewOmrPrefixes) { - RouterAdv::RouteInfoOption *rio; - - OT_ASSERT(bufferLength + RouterAdv::RouteInfoOption::OptionSizeForPrefix(newOmrPrefix.GetLength()) <= - sizeof(buffer)); - - rio = reinterpret_cast(buffer + bufferLength); - - rio->Init(); - rio->SetRouteLifetime(kDefaultOmrPrefixLifetime); - rio->SetPrefix(newOmrPrefix); + SuccessOrAssert( + raMsg.AppendRouteInfoOption(omrPrefix.GetPrefix(), kDefaultOmrPrefixLifetime, mRouteInfoOptionPreference)); - bufferLength += rio->GetSize(); - - LogInfo("Send OMR prefix %s in RIO (valid lifetime = %u seconds)", newOmrPrefix.ToString().AsCString(), + LogInfo("RouterAdvert: Added RIO for %s (lifetime=%u)", omrPrefix.GetPrefix().ToString().AsCString(), kDefaultOmrPrefixLifetime); } - // Send the message only when there are options. - if (bufferLength > sizeof(mRouterAdvMessage)) + if (raMsg.ContainsAnyOptions()) { - Error error; - Ip6::Address destAddress; - InfraIf::Icmp6Packet packet; + Error error; + Ip6::Address destAddress; ++mRouterAdvertisementCount; - packet.Init(buffer, bufferLength); destAddress.SetToLinkLocalAllNodesMulticast(); - error = mInfraIf.Send(packet, destAddress); + error = mInfraIf.Send(raMsg.GetAsPacket(), destAddress); if (error == kErrorNone) { mLastRouterAdvertisementSendTime = TimerMilli::GetNow(); LogInfo("Sent Router Advertisement on %s", mInfraIf.ToString().AsCString()); - DumpDebg("[BR-CERT] direction=send | type=RA |", buffer, bufferLength); + DumpDebg("[BR-CERT] direction=send | type=RA |", raMsg.GetAsPacket().GetBytes(), + raMsg.GetAsPacket().GetLength()); } else { @@ -944,6 +858,68 @@ void RoutingManager::SendRouterAdvertisement(const OmrPrefixArray &aNewOmrPrefix } } +bool RoutingManager::IsReceivdRouterAdvertFromManager(const Ip6::Nd::RouterAdvertMessage &aRaMessage) const +{ + // Determines whether or not a received RA message was prepared by + // by `RoutingManager` itself. + + bool isFromManager = false; + uint16_t rioCount = 0; + Ip6::Prefix prefix; + + VerifyOrExit(aRaMessage.ContainsAnyOptions()); + + for (const Ip6::Nd::Option &option : aRaMessage) + { + switch (option.GetType()) + { + case Ip6::Nd::Option::kTypePrefixInfo: + { + // PIO should match `mLocalOnLinkPrefix`. + + const Ip6::Nd::PrefixInfoOption &pio = static_cast(option); + + VerifyOrExit(pio.IsValid()); + pio.GetPrefix(prefix); + + VerifyOrExit(prefix == mLocalOnLinkPrefix); + break; + } + + case Ip6::Nd::Option::kTypeRouteInfo: + { + // RIO (with non-zero lifetime) should match entries from + // `mAdvertisedOmrPrefixes`. We keep track of the number + // of matched RIOs and check after the loop ends that all + // entries were seen. + + const Ip6::Nd::RouteInfoOption &rio = static_cast(option); + + VerifyOrExit(rio.IsValid()); + rio.GetPrefix(prefix); + + if (rio.GetRouteLifetime() != 0) + { + VerifyOrExit(mAdvertisedOmrPrefixes.ContainsMatching(prefix)); + rioCount++; + } + + break; + } + + default: + ExitNow(); + } + } + + VerifyOrExit(rioCount == mAdvertisedOmrPrefixes.GetLength()); + + isFromManager = true; + +exit: + return isFromManager; +} + bool RoutingManager::IsValidBrUlaPrefix(const Ip6::Prefix &aBrUlaPrefix) { return aBrUlaPrefix.mLength == kBrUlaPrefixLength && aBrUlaPrefix.mPrefix.mFields.m8[0] == 0xfd; @@ -962,7 +938,7 @@ bool RoutingManager::IsValidOmrPrefix(const Ip6::Prefix &aOmrPrefix) (aOmrPrefix.mLength >= 3 && (aOmrPrefix.GetBytes()[0] & 0xE0) == 0x20); } -bool RoutingManager::IsValidOnLinkPrefix(const RouterAdv::PrefixInfoOption &aPio) +bool RoutingManager::IsValidOnLinkPrefix(const Ip6::Nd::PrefixInfoOption &aPio) { Ip6::Prefix prefix; @@ -973,7 +949,8 @@ bool RoutingManager::IsValidOnLinkPrefix(const RouterAdv::PrefixInfoOption &aPio bool RoutingManager::IsValidOnLinkPrefix(const Ip6::Prefix &aOnLinkPrefix) { - return !aOnLinkPrefix.IsLinkLocal() && !aOnLinkPrefix.IsMulticast(); + return aOnLinkPrefix.IsValid() && (aOnLinkPrefix.GetLength() > 0) && !aOnLinkPrefix.IsLinkLocal() && + !aOnLinkPrefix.IsMulticast(); } void RoutingManager::HandleRouterSolicitTimer(Timer &aTimer) @@ -1016,37 +993,20 @@ void RoutingManager::HandleRouterSolicitTimer(void) } else { - // Invalidate/deprecate all OMR/on-link prefixes that are not refreshed during Router Solicitation. - for (ExternalPrefix &prefix : mDiscoveredPrefixes) - { - if (prefix.GetLastUpdateTime() <= mTimeRouterSolicitStart) - { - if (prefix.IsOnLinkPrefix()) - { - prefix.ClearPreferredLifetime(); - } - else - { - prefix.ClearValidLifetime(); - } - } - } - - InvalidateDiscoveredPrefixes(); + // Remove route prefixes and deprecate on-link prefixes that + // are not refreshed during Router Solicitation. + mDiscoveredPrefixTable.RemoveOrDeprecateOldEntries(mTimeRouterSolicitStart); // Invalidate the learned RA message if it is not refreshed during Router Solicitation. if (mTimeRouterAdvMessageLastUpdate <= mTimeRouterSolicitStart) { - UpdateRouterAdvMessage(/* aRouterAdvMessage */ nullptr); + UpdateRouterAdvertHeader(/* aRouterAdvertMessage */ nullptr); } mRouterSolicitCount = 0; // Re-evaluate our routing policy and send Router Advertisement if necessary. StartRoutingPolicyEvaluationDelay(/* aDelayJitter */ 0); - - // Reset prefix stale timer because `mDiscoveredPrefixes` may change. - ResetDiscoveredPrefixStaleTimer(); } } @@ -1061,16 +1021,6 @@ void RoutingManager::HandleDiscoveredPrefixStaleTimer(void) StartRouterSolicitationDelay(); } -void RoutingManager::HandleDiscoveredPrefixInvalidTimer(Timer &aTimer) -{ - aTimer.Get().HandleDiscoveredPrefixInvalidTimer(); -} - -void RoutingManager::HandleDiscoveredPrefixInvalidTimer(void) -{ - InvalidateDiscoveredPrefixes(); -} - void RoutingManager::HandleRoutingPolicyTimer(Timer &aTimer) { aTimer.Get().EvaluateRoutingPolicy(); @@ -1090,159 +1040,79 @@ void RoutingManager::HandleRouterSolicit(const InfraIf::Icmp6Packet &aPacket, co void RoutingManager::HandleRouterAdvertisement(const InfraIf::Icmp6Packet &aPacket, const Ip6::Address &aSrcAddress) { - OT_ASSERT(mIsRunning); - OT_UNUSED_VARIABLE(aSrcAddress); + Ip6::Nd::RouterAdvertMessage routerAdvMessage(aPacket); - using RouterAdv::Option; - using RouterAdv::PrefixInfoOption; - using RouterAdv::RouteInfoOption; - using RouterAdv::RouterAdvMessage; - - bool needReevaluate = false; - const uint8_t * optionsBegin; - uint16_t optionsLength; - const Option * option; - const RouterAdvMessage *routerAdvMessage; + OT_ASSERT(mIsRunning); - VerifyOrExit(aPacket.GetLength() >= sizeof(RouterAdvMessage)); + VerifyOrExit(routerAdvMessage.IsValid()); LogInfo("Received Router Advertisement from %s on %s", aSrcAddress.ToString().AsCString(), mInfraIf.ToString().AsCString()); DumpDebg("[BR-CERT] direction=recv | type=RA |", aPacket.GetBytes(), aPacket.GetLength()); - routerAdvMessage = reinterpret_cast(aPacket.GetBytes()); - optionsBegin = aPacket.GetBytes() + sizeof(RouterAdvMessage); - optionsLength = aPacket.GetLength() - sizeof(RouterAdvMessage); - - option = nullptr; - while ((option = Option::GetNextOption(option, optionsBegin, optionsLength)) != nullptr) - { - switch (option->GetType()) - { - case Option::Type::kPrefixInfo: - { - const PrefixInfoOption *pio = static_cast(option); - - if (pio->IsValid()) - { - needReevaluate |= UpdateDiscoveredOnLinkPrefix(*pio); - } - } - break; - - case Option::Type::kRouteInfo: - { - const RouteInfoOption *rio = static_cast(option); - - if (rio->IsValid()) - { - UpdateDiscoveredOmrPrefix(*rio); - } - } - break; - - default: - break; - } - } + mDiscoveredPrefixTable.ProcessRouterAdvertMessage(routerAdvMessage, aSrcAddress); // Remember the header and parameters of RA messages which are // initiated from the infra interface. if (mInfraIf.HasAddress(aSrcAddress)) { - needReevaluate |= UpdateRouterAdvMessage(routerAdvMessage); - } - - if (needReevaluate) - { - StartRoutingPolicyEvaluationJitter(kRoutingPolicyEvaluationJitter); + UpdateRouterAdvertHeader(&routerAdvMessage); } exit: return; } -// Adds or deprecates a discovered on-link prefix (new external routes may be added -// to the Thread network). Returns a boolean which indicates whether we need to do -// routing policy evaluation. -bool RoutingManager::UpdateDiscoveredOnLinkPrefix(const RouterAdv::PrefixInfoOption &aPio) +bool RoutingManager::ShouldProcessPrefixInfoOption(const Ip6::Nd::PrefixInfoOption &aPio, const Ip6::Prefix &aPrefix) { - Ip6::Prefix prefix; - bool needReevaluate = false; - ExternalPrefix onLinkPrefix; - ExternalPrefix *existingPrefix = nullptr; + // Indicate whether to process or skip a given prefix + // from a PIO (from received RA message). - aPio.GetPrefix(prefix); + bool shouldProcess = false; + + VerifyOrExit(mIsRunning); if (!IsValidOnLinkPrefix(aPio)) { - LogInfo("Ignore invalid on-link prefix in PIO: %s", prefix.ToString().AsCString()); + LogInfo("Ignore invalid on-link prefix in PIO: %s", aPrefix.ToString().AsCString()); ExitNow(); } - VerifyOrExit(!mIsAdvertisingLocalOnLinkPrefix || prefix != mLocalOnLinkPrefix); - - LogInfo("Discovered on-link prefix (%s, %u seconds) from %s", prefix.ToString().AsCString(), - aPio.GetValidLifetime(), mInfraIf.ToString().AsCString()); - - onLinkPrefix.InitFrom(aPio); - - existingPrefix = mDiscoveredPrefixes.Find(onLinkPrefix); - - if (existingPrefix == nullptr) - { - if (onLinkPrefix.GetValidLifetime() == 0) - { - ExitNow(); - } - - if (!mDiscoveredPrefixes.IsFull()) - { - SuccessOrExit(PublishExternalRoute(prefix, NetworkData::kRoutePreferenceMedium)); - existingPrefix = mDiscoveredPrefixes.PushBack(); - *existingPrefix = onLinkPrefix; - needReevaluate = true; - } - else - { - LogWarn("Discovered too many prefixes, ignore new on-link prefix %s", prefix.ToString().AsCString()); - ExitNow(); - } - } - else + if (mIsAdvertisingLocalOnLinkPrefix) { - // The on-link prefix routing policy may be affected when a - // discovered on-link prefix becomes deprecated or preferred. - needReevaluate = (onLinkPrefix.IsDeprecated() != existingPrefix->IsDeprecated()); - - existingPrefix->AdoptValidAndPreferredLiftimesFrom(onLinkPrefix); + VerifyOrExit(aPrefix != mLocalOnLinkPrefix); } - mDiscoveredPrefixInvalidTimer.FireAtIfEarlier(existingPrefix->GetExpireTime()); - ResetDiscoveredPrefixStaleTimer(); + shouldProcess = true; exit: - return needReevaluate; + return shouldProcess; } -// Adds or removes a discovered OMR prefix (external route will be added to or removed -// from the Thread network). -void RoutingManager::UpdateDiscoveredOmrPrefix(const RouterAdv::RouteInfoOption &aRio) +bool RoutingManager::ShouldProcessRouteInfoOption(const Ip6::Nd::RouteInfoOption &aRio, const Ip6::Prefix &aPrefix) { - Ip6::Prefix prefix; - ExternalPrefix omrPrefix; - ExternalPrefix *existingPrefix = nullptr; + // Indicate whether to process or skip a given prefix + // from a RIO (from received RA message). - aRio.GetPrefix(prefix); + OT_UNUSED_VARIABLE(aRio); + + bool shouldProcess = false; + + VerifyOrExit(mIsRunning); + + if (aPrefix.GetLength() == 0) + { + // Always process default route ::/0 prefix. + ExitNow(shouldProcess = true); + } - if (!IsValidOmrPrefix(prefix)) + if (!IsValidOmrPrefix(aPrefix)) { - LogInfo("Ignore invalid OMR prefix in RIO: %s", prefix.ToString().AsCString()); + LogInfo("Ignore RIO prefix %s since not a valid OMR prefix", aPrefix.ToString().AsCString()); ExitNow(); } - // Ignore own OMR prefix. - VerifyOrExit(mLocalOmrPrefix != prefix); + VerifyOrExit(mLocalOmrPrefix.GetPrefix() != aPrefix); // Ignore OMR prefixes advertised by ourselves or in current Thread Network Data. // The `mAdvertisedOmrPrefixes` and the OMR prefix set in Network Data should eventually @@ -1254,269 +1124,762 @@ void RoutingManager::UpdateDiscoveredOmrPrefix(const RouterAdv::RouteInfoOption // messages are usually faster than Thread Network Data propagation). // They are the reasons why we need both the checks. - VerifyOrExit(!mAdvertisedOmrPrefixes.Contains(prefix)); - VerifyOrExit(!NetworkDataContainsOmrPrefix(prefix)); + VerifyOrExit(!mAdvertisedOmrPrefixes.ContainsMatching(aPrefix)); + VerifyOrExit(!Get().NetworkDataContainsOmrPrefix(aPrefix)); - LogInfo("Discovered OMR prefix (%s, %u seconds) from %s", prefix.ToString().AsCString(), aRio.GetRouteLifetime(), - mInfraIf.ToString().AsCString()); + shouldProcess = true; - omrPrefix.InitFrom(aRio); +exit: + return shouldProcess; +} - existingPrefix = mDiscoveredPrefixes.Find(omrPrefix); +void RoutingManager::HandleDiscoveredPrefixTableChanged(void) +{ + // This is a callback from `mDiscoveredPrefixTable` indicating that + // there has been a change in the table. If the favored on-link + // prefix has changed, we trigger a re-evaluation of the routing + // policy. + + Ip6::Prefix newFavoredPrefix; + + VerifyOrExit(mIsRunning); + + ResetDiscoveredPrefixStaleTimer(); + + mDiscoveredPrefixTable.FindFavoredOnLinkPrefix(newFavoredPrefix); + + if (newFavoredPrefix != mFavoredDiscoveredOnLinkPrefix) + { + StartRoutingPolicyEvaluationJitter(kRoutingPolicyEvaluationJitter); + } + +exit: + return; +} + +bool RoutingManager::NetworkDataContainsOmrPrefix(const Ip6::Prefix &aPrefix) const +{ + NetworkData::Iterator iterator = NetworkData::kIteratorInit; + NetworkData::OnMeshPrefixConfig onMeshPrefixConfig; + bool contain = false; - if (omrPrefix.GetValidLifetime() == 0) + while (Get().GetNextOnMeshPrefix(iterator, onMeshPrefixConfig) == OT_ERROR_NONE) { - if (existingPrefix != nullptr) + if (IsValidOmrPrefix(onMeshPrefixConfig) && onMeshPrefixConfig.GetPrefix() == aPrefix) { - existingPrefix->ClearValidLifetime(); - InvalidateDiscoveredPrefixes(); + contain = true; + break; } + } - ExitNow(); + return contain; +} + +void RoutingManager::UpdateRouterAdvertHeader(const Ip6::Nd::RouterAdvertMessage *aRouterAdvertMessage) +{ + // Updates the `mRouterAdvertHeader` from the given RA message. + + Ip6::Nd::RouterAdvertMessage::Header oldHeader; + + if (aRouterAdvertMessage != nullptr) + { + // We skip and do not update RA header if the received RA message + // was not prepared and sent by `RoutingManager` itself. + + VerifyOrExit(!IsReceivdRouterAdvertFromManager(*aRouterAdvertMessage)); + } + + oldHeader = mRouterAdvertHeader; + mTimeRouterAdvMessageLastUpdate = TimerMilli::GetNow(); + + if (aRouterAdvertMessage == nullptr || aRouterAdvertMessage->GetHeader().GetRouterLifetime() == 0) + { + mRouterAdvertHeader.SetToDefault(); + mLearntRouterAdvMessageFromHost = false; + } + else + { + // The checksum is set to zero in `mRouterAdvertHeader` + // which indicates to platform that it needs to do the + // calculation and update it. + + mRouterAdvertHeader = aRouterAdvertMessage->GetHeader(); + mRouterAdvertHeader.SetChecksum(0); + mLearntRouterAdvMessageFromHost = true; + } + + ResetDiscoveredPrefixStaleTimer(); + + if (mRouterAdvertHeader != oldHeader) + { + // If there was a change to the header, start timer to + // reevaluate routing policy and send RA message with new + // header. + + StartRoutingPolicyEvaluationJitter(kRoutingPolicyEvaluationJitter); + } + +exit: + return; +} + +void RoutingManager::ResetDiscoveredPrefixStaleTimer(void) +{ + TimeMilli now = TimerMilli::GetNow(); + TimeMilli nextStaleTime; + + OT_ASSERT(mIsRunning); + + // The stale timer triggers sending RS to check the state of + // discovered prefixes and host RA messages. + + nextStaleTime = mDiscoveredPrefixTable.CalculateNextStaleTime(now); + + // Check for stale Router Advertisement Message if learnt from Host. + if (mLearntRouterAdvMessageFromHost) + { + TimeMilli raStaleTime = OT_MAX(now, mTimeRouterAdvMessageLastUpdate + Time::SecToMsec(kRtrAdvStaleTime)); + + nextStaleTime = OT_MIN(nextStaleTime, raStaleTime); } - if (existingPrefix == nullptr) + if (nextStaleTime == now.GetDistantFuture()) { - if (!mDiscoveredPrefixes.IsFull()) + if (mDiscoveredPrefixStaleTimer.IsRunning()) { - SuccessOrExit(PublishExternalRoute(prefix, omrPrefix.GetRoutePreference())); - existingPrefix = mDiscoveredPrefixes.PushBack(); + LogDebg("Prefix stale timer stopped"); } - else + + mDiscoveredPrefixStaleTimer.Stop(); + } + else + { + mDiscoveredPrefixStaleTimer.FireAt(nextStaleTime); + LogDebg("Prefix stale timer scheduled in %lu ms", nextStaleTime - now); + } +} + +//--------------------------------------------------------------------------------------------------------------------- +// DiscoveredPrefixTable + +RoutingManager::DiscoveredPrefixTable::DiscoveredPrefixTable(Instance &aInstance) + : InstanceLocator(aInstance) + , mTimer(aInstance, HandleTimer) + , mSignalTask(aInstance, HandleSignalTask) + , mAllowDefaultRouteInNetData(false) +{ +} + +void RoutingManager::DiscoveredPrefixTable::ProcessRouterAdvertMessage(const Ip6::Nd::RouterAdvertMessage &aRaMessage, + const Ip6::Address & aSrcAddress) +{ + // Process a received RA message and update the prefix table. + + Router *router = mRouters.FindMatching(aSrcAddress); + + if (router == nullptr) + { + router = mRouters.PushBack(); + + if (router == nullptr) { - LogWarn("Discovered too many prefixes, ignore new prefix %s", prefix.ToString().AsCString()); + LogWarn("Received RA from too many routers, ignore RA from %s", aSrcAddress.ToString().AsCString()); ExitNow(); } + + router->mAddress = aSrcAddress; + router->mEntries.Clear(); } - *existingPrefix = omrPrefix; + // RA message can indicate router provides default route in the RA + // message header and can also include an RIO for `::/0`. When + // processing an RA message, the preference and lifetime values + // in a `::/0` RIO override the preference and lifetime values in + // the RA header (per RFC 4191 section 3.1). - mDiscoveredPrefixInvalidTimer.FireAtIfEarlier(existingPrefix->GetExpireTime()); - ResetDiscoveredPrefixStaleTimer(); + ProcessDefaultRoute(aRaMessage.GetHeader(), *router); + + for (const Ip6::Nd::Option &option : aRaMessage) + { + switch (option.GetType()) + { + case Ip6::Nd::Option::kTypePrefixInfo: + ProcessPrefixInfoOption(static_cast(option), *router); + break; + + case Ip6::Nd::Option::kTypeRouteInfo: + ProcessRouteInfoOption(static_cast(option), *router); + break; + + default: + break; + } + } + + RemoveRoutersWithNoEntries(); exit: return; } -void RoutingManager::InvalidateDiscoveredPrefixes(void) +void RoutingManager::DiscoveredPrefixTable::ProcessDefaultRoute(const Ip6::Nd::RouterAdvertMessage::Header &aRaHeader, + Router & aRouter) { - TimeMilli now = TimerMilli::GetNow(); - TimeMilli nextExpireTime = now.GetDistantFuture(); - bool containsOnLinkPrefix = false; + Entry * entry; + Ip6::Prefix prefix; - mDiscoveredPrefixInvalidTimer.Stop(); + prefix.Clear(); + entry = aRouter.mEntries.FindMatching(Entry::Matcher(prefix, Entry::kTypeRoute)); - for (ExternalPrefixArray::IndexType index = 0; index < mDiscoveredPrefixes.GetLength();) + if (entry == nullptr) { - ExternalPrefix &prefix = mDiscoveredPrefixes[index]; + VerifyOrExit(aRaHeader.GetRouterLifetime() != 0); - // We invalidate expired prefixes, or local OMR prefixes - // (either in `mAdvertisedOmrPrefixes` or in Thread Network - // Data). + entry = AllocateEntry(); - if ((prefix.GetExpireTime() <= now) || - (!prefix.IsOnLinkPrefix() && - (mAdvertisedOmrPrefixes.Contains(prefix.GetPrefix()) || NetworkDataContainsOmrPrefix(prefix.GetPrefix())))) + if (entry == nullptr) { - UnpublishExternalRoute(prefix.GetPrefix()); + LogWarn("Discovered too many prefixes, ignore default route from RA header"); + ExitNow(); + } - // Remove the prefix from the array by replacing it with - // last entry in the array (we copy the popped last entry - // into `prefix` entry at current `index`). Also in this - // case, the `index` is not incremented. + entry->InitFrom(aRaHeader); + aRouter.mEntries.Push(*entry); + } + else + { + entry->InitFrom(aRaHeader); + } - prefix = *mDiscoveredPrefixes.PopBack(); - } - else - { - nextExpireTime = OT_MIN(nextExpireTime, prefix.GetExpireTime()); - containsOnLinkPrefix |= prefix.IsOnLinkPrefix(); + UpdateNetworkDataOnChangeTo(*entry); + mTimer.FireAtIfEarlier(entry->GetExpireTime()); + SignalTableChanged(); + +exit: + return; +} - index++; +void RoutingManager::DiscoveredPrefixTable::ProcessPrefixInfoOption(const Ip6::Nd::PrefixInfoOption &aPio, + Router & aRouter) +{ + Ip6::Prefix prefix; + Entry * entry; + + VerifyOrExit(aPio.IsValid()); + aPio.GetPrefix(prefix); + + VerifyOrExit(Get().ShouldProcessPrefixInfoOption(aPio, prefix)); + + LogInfo("Processing PIO (%s, %u seconds)", prefix.ToString().AsCString(), aPio.GetValidLifetime()); + + entry = aRouter.mEntries.FindMatching(Entry::Matcher(prefix, Entry::kTypeOnLink)); + + if (entry == nullptr) + { + VerifyOrExit(aPio.GetValidLifetime() != 0); + + entry = AllocateEntry(); + + if (entry == nullptr) + { + LogWarn("Discovered too many prefixes, ignore on-link prefix %s", prefix.ToString().AsCString()); + ExitNow(); } + + entry->InitFrom(aPio); + aRouter.mEntries.Push(*entry); } + else + { + Entry newEntry; - if (nextExpireTime != now.GetDistantFuture()) + newEntry.InitFrom(aPio); + entry->AdoptValidAndPreferredLiftimesFrom(newEntry); + } + + UpdateNetworkDataOnChangeTo(*entry); + mTimer.FireAtIfEarlier(entry->GetExpireTime()); + SignalTableChanged(); + +exit: + return; +} + +void RoutingManager::DiscoveredPrefixTable::ProcessRouteInfoOption(const Ip6::Nd::RouteInfoOption &aRio, + Router & aRouter) +{ + Ip6::Prefix prefix; + Entry * entry; + + VerifyOrExit(aRio.IsValid()); + aRio.GetPrefix(prefix); + + VerifyOrExit(Get().ShouldProcessRouteInfoOption(aRio, prefix)); + + LogInfo("Processing RIO (%s, %u seconds)", prefix.ToString().AsCString(), aRio.GetRouteLifetime()); + + entry = aRouter.mEntries.FindMatching(Entry::Matcher(prefix, Entry::kTypeRoute)); + + if (entry == nullptr) + { + VerifyOrExit(aRio.GetRouteLifetime() != 0); + + entry = AllocateEntry(); + + if (entry == nullptr) + { + LogWarn("Discovered too many prefixes, ignore route prefix %s", prefix.ToString().AsCString()); + ExitNow(); + } + + entry->InitFrom(aRio); + aRouter.mEntries.Push(*entry); + } + else { - mDiscoveredPrefixInvalidTimer.FireAt(nextExpireTime); + entry->InitFrom(aRio); } - if (!containsOnLinkPrefix && !mIsAdvertisingLocalOnLinkPrefix) + UpdateNetworkDataOnChangeTo(*entry); + mTimer.FireAtIfEarlier(entry->GetExpireTime()); + SignalTableChanged(); + +exit: + return; +} + +void RoutingManager::DiscoveredPrefixTable::SetAllowDefaultRouteInNetData(bool aAllow) +{ + Entry * favoredEntry; + Ip6::Prefix prefix; + + VerifyOrExit(aAllow != mAllowDefaultRouteInNetData); + + LogInfo("Allow default route in netdata: %s -> %s", ToYesNo(mAllowDefaultRouteInNetData), ToYesNo(aAllow)); + + mAllowDefaultRouteInNetData = aAllow; + + prefix.Clear(); + favoredEntry = FindFavoredEntryToPublish(prefix); + VerifyOrExit(favoredEntry != nullptr); + + if (mAllowDefaultRouteInNetData) { - // There are no valid on-link prefixes on infra link now, start - // Router Solicitation to discover more on-link prefixes or - // time out to advertise the local on-link prefix. - StartRouterSolicitationDelay(); + PublishEntry(*favoredEntry); } + else + { + UnpublishEntry(*favoredEntry); + } + +exit: + return; } -void RoutingManager::InvalidateAllDiscoveredPrefixes(void) +void RoutingManager::DiscoveredPrefixTable::FindFavoredOnLinkPrefix(Ip6::Prefix &aPrefix) const { - for (ExternalPrefix &prefix : mDiscoveredPrefixes) + // Find the smallest preferred on-link prefix entry in the table + // and return it in `aPrefix`. If there is none, `aPrefix` is + // cleared (prefix length is set to zero). + + aPrefix.Clear(); + + for (const Router &router : mRouters) { - prefix.ClearValidLifetime(); + for (const Entry &entry : router.mEntries) + { + if (!entry.IsOnLinkPrefix() || entry.IsDeprecated()) + { + continue; + } + + if ((aPrefix.GetLength() == 0) || (entry.GetPrefix() < aPrefix)) + { + aPrefix = entry.GetPrefix(); + } + } } +} - InvalidateDiscoveredPrefixes(); +bool RoutingManager::DiscoveredPrefixTable::ContainsOnLinkPrefix(const Ip6::Prefix &aPrefix) const +{ + return ContainsPrefix(Entry::Matcher(aPrefix, Entry::kTypeOnLink)); +} - OT_ASSERT(mDiscoveredPrefixes.IsEmpty()); +bool RoutingManager::DiscoveredPrefixTable::ContainsRoutePrefix(const Ip6::Prefix &aPrefix) const +{ + return ContainsPrefix(Entry::Matcher(aPrefix, Entry::kTypeRoute)); } -bool RoutingManager::NetworkDataContainsOmrPrefix(const Ip6::Prefix &aPrefix) const +bool RoutingManager::DiscoveredPrefixTable::ContainsPrefix(const Entry::Matcher &aMatcher) const { - NetworkData::Iterator iterator = NetworkData::kIteratorInit; - NetworkData::OnMeshPrefixConfig onMeshPrefixConfig; - bool contain = false; + bool contains = false; - while (Get().GetNextOnMeshPrefix(iterator, onMeshPrefixConfig) == OT_ERROR_NONE) + for (const Router &router : mRouters) { - if (IsValidOmrPrefix(onMeshPrefixConfig) && onMeshPrefixConfig.GetPrefix() == aPrefix) + if (router.mEntries.ContainsMatching(aMatcher)) { - contain = true; + contains = true; break; } } - return contain; + return contains; } -// Update the `mRouterAdvMessage` with given Router Advertisement message. -// Returns a boolean which indicates whether there are changes of `mRouterAdvMessage`. -bool RoutingManager::UpdateRouterAdvMessage(const RouterAdv::RouterAdvMessage *aRouterAdvMessage) +void RoutingManager::DiscoveredPrefixTable::RemoveOnLinkPrefix(const Ip6::Prefix &aPrefix, NetDataMode aNetDataMode) { - RouterAdv::RouterAdvMessage oldRouterAdvMessage; + RemovePrefix(Entry::Matcher(aPrefix, Entry::kTypeOnLink), aNetDataMode); +} - oldRouterAdvMessage = mRouterAdvMessage; +void RoutingManager::DiscoveredPrefixTable::RemoveRoutePrefix(const Ip6::Prefix &aPrefix, NetDataMode aNetDataMode) +{ + RemovePrefix(Entry::Matcher(aPrefix, Entry::kTypeRoute), aNetDataMode); +} - mTimeRouterAdvMessageLastUpdate = TimerMilli::GetNow(); +void RoutingManager::DiscoveredPrefixTable::RemovePrefix(const Entry::Matcher &aMatcher, NetDataMode aNetDataMode) +{ + // Removes all entries matching a given prefix from the table. + // `aNetDataMode` specifies behavior when a match is found and + // removed. It indicates whether or not to unpublish it from + // Network Data. + + LinkedList removedEntries; - if (aRouterAdvMessage == nullptr || aRouterAdvMessage->GetRouterLifetime() == 0) + for (Router &router : mRouters) { - mRouterAdvMessage.SetToDefault(); - mLearntRouterAdvMessageFromHost = false; + router.mEntries.RemoveAllMatching(aMatcher, removedEntries); } - else - { - // The checksum is set to zero in `mRouterAdvMessage` - // which indicates to platform that it needs to do the - // calculation and update it. - mRouterAdvMessage = *aRouterAdvMessage; - mRouterAdvMessage.SetChecksum(0); - mLearntRouterAdvMessageFromHost = true; + VerifyOrExit(!removedEntries.IsEmpty()); + + if (aNetDataMode == kUnpublishFromNetData) + { + UnpublishEntry(*removedEntries.GetHead()); } - ResetDiscoveredPrefixStaleTimer(); + FreeEntries(removedEntries); + RemoveRoutersWithNoEntries(); - return (mRouterAdvMessage != oldRouterAdvMessage); + SignalTableChanged(); + +exit: + return; } -void RoutingManager::ResetDiscoveredPrefixStaleTimer(void) +void RoutingManager::DiscoveredPrefixTable::RemoveAllEntries(void) { - TimeMilli now = TimerMilli::GetNow(); - TimeMilli nextStaleTime = now.GetDistantFuture(); - TimeMilli maxOnlinkPrefixStaleTime = now; - bool requireCheckStaleOnlinkPrefix = false; + // Remove all entries from the table and unpublish them + // from Network Data. - OT_ASSERT(mIsRunning); + for (Router &router : mRouters) + { + Entry *entry; - // The stale timer triggers sending RS to check the state of On-Link/OMR prefixes and host RA messages. - // The rules for calculating the next stale time: - // 1. If BR learns RA header from Host daemons, it should send RS when the RA header is stale. - // 2. If BR discovered any on-link prefix, it should send RS when all on-link prefixes are stale. - // 3. If BR discovered any OMR prefix, it should send RS when the first OMR prefix is stale. + while ((entry = router.mEntries.Pop()) != nullptr) + { + UnpublishEntry(*entry); + FreeEntry(*entry); + SignalTableChanged(); + } + } - // Check for stale Router Advertisement Message if learnt from Host. - if (mLearntRouterAdvMessageFromHost) + RemoveRoutersWithNoEntries(); + mTimer.Stop(); +} + +void RoutingManager::DiscoveredPrefixTable::RemoveOrDeprecateOldEntries(TimeMilli aTimeThreshold) +{ + // Remove route prefix entries and deprecate on-link entries in + // the table that are old (not updated since `aTimeThreshold`). + + for (Router &router : mRouters) { - TimeMilli routerAdvMessageStaleTime = mTimeRouterAdvMessageLastUpdate + Time::SecToMsec(kRtrAdvStaleTime); + for (Entry &entry : router.mEntries) + { + if (entry.GetLastUpdateTime() <= aTimeThreshold) + { + if (entry.IsOnLinkPrefix()) + { + entry.ClearPreferredLifetime(); + } + else + { + entry.ClearValidLifetime(); + } - nextStaleTime = OT_MIN(nextStaleTime, routerAdvMessageStaleTime); + SignalTableChanged(); + } + } + } + + RemoveExpiredEntries(); +} + +TimeMilli RoutingManager::DiscoveredPrefixTable::CalculateNextStaleTime(TimeMilli aNow) const +{ + TimeMilli onLinkStaleTime = aNow; + TimeMilli routeStaleTime = aNow.GetDistantFuture(); + bool foundOnLink = false; + + // For on-link prefixes, we consider stale time as when all on-link + // prefixes become stale (the latest stale time) but for route + // prefixes we consider the earliest stale time. + + for (const Router &router : mRouters) + { + for (const Entry &entry : router.mEntries) + { + TimeMilli entryStaleTime = OT_MAX(aNow, entry.GetStaleTime()); + + if (entry.IsOnLinkPrefix() && !entry.IsDeprecated()) + { + onLinkStaleTime = OT_MAX(onLinkStaleTime, entryStaleTime); + foundOnLink = true; + } + + if (!entry.IsOnLinkPrefix()) + { + routeStaleTime = OT_MIN(routeStaleTime, entryStaleTime); + } + } } - for (ExternalPrefix &externalPrefix : mDiscoveredPrefixes) + return foundOnLink ? OT_MIN(onLinkStaleTime, routeStaleTime) : routeStaleTime; +} + +void RoutingManager::DiscoveredPrefixTable::RemoveRoutersWithNoEntries(void) +{ + mRouters.RemoveAllMatching(Router::kContainsNoEntries); +} + +void RoutingManager::DiscoveredPrefixTable::FreeEntries(LinkedList &aEntries) +{ + // Frees all entries in the given list `aEntries` (put them back + // in the entry pool). + + Entry *entry; + + while ((entry = aEntries.Pop()) != nullptr) { - TimeMilli prefixStaleTime = externalPrefix.GetStaleTime(); + FreeEntry(*entry); + } +} + +RoutingManager::DiscoveredPrefixTable::Entry *RoutingManager::DiscoveredPrefixTable::FindFavoredEntryToPublish( + const Ip6::Prefix &aPrefix) +{ + // Finds the favored entry matching a given `aPrefix` in the table + // to publish in the Network Data. We can have multiple entries + // in the table matching the same `aPrefix` from different + // routers and potentially with different preference values. We + // select the one with the highest preference as the favored + // entry to publish. - if (externalPrefix.IsOnLinkPrefix()) + Entry *favoredEntry = nullptr; + + for (Router &router : mRouters) + { + for (Entry &entry : router.mEntries) { - if (!externalPrefix.IsDeprecated()) + if (entry.GetPrefix() != aPrefix) { - // Check for least recent stale On-Link Prefixes if BR is not advertising local On-Link Prefix. - maxOnlinkPrefixStaleTime = OT_MAX(maxOnlinkPrefixStaleTime, prefixStaleTime); - requireCheckStaleOnlinkPrefix = true; + continue; + } + + if ((favoredEntry == nullptr) || (entry.GetPreference() > favoredEntry->GetPreference())) + { + favoredEntry = &entry; } } + } + + return favoredEntry; +} + +void RoutingManager::DiscoveredPrefixTable::UpdateNetworkDataOnChangeTo(Entry &aEntry) +{ + // Updates Network Data when there is a change to `aEntry` which + // can be a newly added entry or an existing entry that is + // modified due to processing of a received RA message. + + Entry *favoredEntry; + + if (aEntry.GetPrefix().GetLength() == 0) + { + // If the change is to default route ::/0 prefix, make sure we + // are allowed to publish default route in Network Data. + + VerifyOrExit(mAllowDefaultRouteInNetData); + } + + favoredEntry = FindFavoredEntryToPublish(aEntry.GetPrefix()); + + OT_ASSERT(favoredEntry != nullptr); + PublishEntry(*favoredEntry); + +exit: + return; +} + +void RoutingManager::DiscoveredPrefixTable::PublishEntry(const Entry &aEntry) +{ + IgnoreError(Get().PublishExternalRoute(aEntry.GetPrefix(), aEntry.GetPreference())); +} + +void RoutingManager::DiscoveredPrefixTable::UnpublishEntry(const Entry &aEntry) +{ + Get().UnpublishExternalRoute(aEntry.GetPrefix()); +} + +void RoutingManager::DiscoveredPrefixTable::HandleTimer(Timer &aTimer) +{ + aTimer.Get().mDiscoveredPrefixTable.HandleTimer(); +} + +void RoutingManager::DiscoveredPrefixTable::HandleTimer(void) +{ + RemoveExpiredEntries(); +} + +void RoutingManager::DiscoveredPrefixTable::RemoveExpiredEntries(void) +{ + TimeMilli now = TimerMilli::GetNow(); + TimeMilli nextExpireTime = now.GetDistantFuture(); + LinkedList expiredEntries; + + for (Router &router : mRouters) + { + router.mEntries.RemoveAllMatching(Entry::ExpirationChecker(now), expiredEntries); + } + + RemoveRoutersWithNoEntries(); + + // Determine if we need to publish/unpublish any prefixes in + // the Network Data. + + for (const Entry &expiredEntry : expiredEntries) + { + Entry *favoredEntry = FindFavoredEntryToPublish(expiredEntry.GetPrefix()); + + if (favoredEntry == nullptr) + { + UnpublishEntry(expiredEntry); + } else { - // Check for most recent stale OMR Prefixes - nextStaleTime = OT_MIN(nextStaleTime, prefixStaleTime); + PublishEntry(*favoredEntry); } } - if (requireCheckStaleOnlinkPrefix) + if (!expiredEntries.IsEmpty()) { - nextStaleTime = OT_MIN(nextStaleTime, maxOnlinkPrefixStaleTime); + SignalTableChanged(); } - if (nextStaleTime == now.GetDistantFuture()) + FreeEntries(expiredEntries); + + // Determine the next expire time and schedule timer. + + for (const Router &router : mRouters) { - if (mDiscoveredPrefixStaleTimer.IsRunning()) + for (const Entry &entry : router.mEntries) { - LogDebg("Prefix stale timer stopped"); + nextExpireTime = OT_MIN(nextExpireTime, entry.GetExpireTime()); } - mDiscoveredPrefixStaleTimer.Stop(); } - else + + if (nextExpireTime != now.GetDistantFuture()) { - mDiscoveredPrefixStaleTimer.FireAt(nextStaleTime); - LogDebg("Prefix stale timer scheduled in %lu ms", nextStaleTime - now); + mTimer.FireAt(nextExpireTime); } } +void RoutingManager::DiscoveredPrefixTable::SignalTableChanged(void) +{ + mSignalTask.Post(); +} + +void RoutingManager::DiscoveredPrefixTable::HandleSignalTask(Tasklet &aTasklet) +{ + aTasklet.Get().HandleDiscoveredPrefixTableChanged(); +} + //--------------------------------------------------------------------------------------------------------------------- -// ExtneralPrefix +// DiscoveredPrefixTable::Entry + +void RoutingManager::DiscoveredPrefixTable::Entry::InitFrom(const Ip6::Nd::RouterAdvertMessage::Header &aRaHeader) +{ + Clear(); + mType = kTypeRoute; + mValidLifetime = aRaHeader.GetRouterLifetime(); + mShared.mRoutePreference = aRaHeader.GetDefaultRouterPreference(); + mLastUpdateTime = TimerMilli::GetNow(); +} -void RoutingManager::ExternalPrefix::InitFrom(const RouterAdv::PrefixInfoOption &aPio) +void RoutingManager::DiscoveredPrefixTable::Entry::InitFrom(const Ip6::Nd::PrefixInfoOption &aPio) { Clear(); aPio.GetPrefix(mPrefix); - mIsOnLinkPrefix = true; - mValidLifetime = aPio.GetValidLifetime(); - mPreferredLifetime = aPio.GetPreferredLifetime(); - mLastUpdateTime = TimerMilli::GetNow(); + mType = kTypeOnLink; + mValidLifetime = aPio.GetValidLifetime(); + mShared.mPreferredLifetime = aPio.GetPreferredLifetime(); + mLastUpdateTime = TimerMilli::GetNow(); } -void RoutingManager::ExternalPrefix::InitFrom(const RouterAdv::RouteInfoOption &aRio) +void RoutingManager::DiscoveredPrefixTable::Entry::InitFrom(const Ip6::Nd::RouteInfoOption &aRio) { Clear(); aRio.GetPrefix(mPrefix); - mIsOnLinkPrefix = false; - mValidLifetime = aRio.GetRouteLifetime(); - mRoutePreference = aRio.GetPreference(); - mLastUpdateTime = TimerMilli::GetNow(); + mType = kTypeRoute; + mValidLifetime = aRio.GetRouteLifetime(); + mShared.mRoutePreference = aRio.GetPreference(); + mLastUpdateTime = TimerMilli::GetNow(); +} + +bool RoutingManager::DiscoveredPrefixTable::Entry::operator==(const Entry &aOther) const +{ + return (mType == aOther.mType) && (mPrefix == aOther.mPrefix); +} + +bool RoutingManager::DiscoveredPrefixTable::Entry::Matches(const Matcher &aMatcher) const +{ + return (mType == aMatcher.mType) && (mPrefix == aMatcher.mPrefix); +} + +bool RoutingManager::DiscoveredPrefixTable::Entry::Matches(const ExpirationChecker &aCheker) const +{ + return GetExpireTime() <= aCheker.mNow; } -bool RoutingManager::ExternalPrefix::operator==(const ExternalPrefix &aPrefix) const +TimeMilli RoutingManager::DiscoveredPrefixTable::Entry::GetExpireTime(void) const { - return mIsOnLinkPrefix == aPrefix.mIsOnLinkPrefix && (mPrefix == aPrefix.mPrefix); + return mLastUpdateTime + CalculateExpireDelay(mValidLifetime); } -TimeMilli RoutingManager::ExternalPrefix::GetStaleTime(void) const +TimeMilli RoutingManager::DiscoveredPrefixTable::Entry::GetStaleTime(void) const { - uint32_t delay = OT_MIN(kRtrAdvStaleTime, mIsOnLinkPrefix ? mPreferredLifetime : mValidLifetime); + uint32_t delay = OT_MIN(kRtrAdvStaleTime, IsOnLinkPrefix() ? GetPreferredLifetime() : mValidLifetime); return mLastUpdateTime + TimeMilli::SecToMsec(delay); } -bool RoutingManager::ExternalPrefix::IsDeprecated(void) const +bool RoutingManager::DiscoveredPrefixTable::Entry::IsDeprecated(void) const { - OT_ASSERT(mIsOnLinkPrefix); + OT_ASSERT(IsOnLinkPrefix()); - return mLastUpdateTime + TimeMilli::SecToMsec(mPreferredLifetime) <= TimerMilli::GetNow(); + return mLastUpdateTime + TimeMilli::SecToMsec(GetPreferredLifetime()) <= TimerMilli::GetNow(); } -void RoutingManager::ExternalPrefix::AdoptValidAndPreferredLiftimesFrom(const ExternalPrefix &aPrefix) +RoutingManager::RoutePreference RoutingManager::DiscoveredPrefixTable::Entry::GetPreference(void) const +{ + // Returns the preference level to use when we publish + // the prefix entry in Network Data. + + return IsOnLinkPrefix() ? NetworkData::kRoutePreferenceMedium : GetRoutePreference(); +} + +void RoutingManager::DiscoveredPrefixTable::Entry::AdoptValidAndPreferredLiftimesFrom(const Entry &aEntry) { constexpr uint32_t kTwoHoursInSeconds = 2 * 3600; @@ -1531,20 +1894,20 @@ void RoutingManager::ExternalPrefix::AdoptValidAndPreferredLiftimesFrom(const Ex // 3. Otherwise, reset the valid lifetime of the corresponding // address to 2 hours. - if (aPrefix.mValidLifetime > kTwoHoursInSeconds || aPrefix.GetExpireTime() > GetExpireTime()) + if (aEntry.mValidLifetime > kTwoHoursInSeconds || aEntry.GetExpireTime() > GetExpireTime()) { - mValidLifetime = aPrefix.mValidLifetime; + mValidLifetime = aEntry.mValidLifetime; } else if (GetExpireTime() > TimerMilli::GetNow() + TimeMilli::SecToMsec(kTwoHoursInSeconds)) { mValidLifetime = kTwoHoursInSeconds; } - mPreferredLifetime = aPrefix.GetPreferredLifetime(); - mLastUpdateTime = aPrefix.GetLastUpdateTime(); + mShared.mPreferredLifetime = aEntry.GetPreferredLifetime(); + mLastUpdateTime = aEntry.GetLastUpdateTime(); } -uint32_t RoutingManager::ExternalPrefix::GetPrefixExpireDelay(uint32_t aValidLifetime) +uint32_t RoutingManager::DiscoveredPrefixTable::Entry::CalculateExpireDelay(uint32_t aValidLifetime) { uint32_t delay; @@ -1560,6 +1923,126 @@ uint32_t RoutingManager::ExternalPrefix::GetPrefixExpireDelay(uint32_t aValidLif return delay; } +//--------------------------------------------------------------------------------------------------------------------- +// OmrPrefix + +void RoutingManager::OmrPrefix::Init(const Ip6::Prefix &aPrefix, RoutePreference aPreference) +{ + mPrefix = aPrefix; + mPreference = aPreference; +} + +void RoutingManager::OmrPrefix::InitFrom(NetworkData::OnMeshPrefixConfig &aOnMeshPrefixConfig) +{ + Init(aOnMeshPrefixConfig.GetPrefix(), aOnMeshPrefixConfig.GetPreference()); +} + +bool RoutingManager::OmrPrefix::IsFavoredOver(const OmrPrefix &aOther) const +{ + // This method determines whether this OMR prefix is favored + // over `aOther` prefix. A prefix with higher preference is + // favored. If the preference is the same, then the smaller + // prefix (in the sense defined by `Ip6::Prefix`) is favored. + + return (mPreference > aOther.mPreference) || ((mPreference == aOther.mPreference) && (mPrefix < aOther.mPrefix)); +} + +RoutingManager::OmrPrefix::InfoString RoutingManager::OmrPrefix::ToString(void) const +{ + InfoString string; + + string.Append("%s (prf:", mPrefix.ToString().AsCString()); + + switch (mPreference) + { + case NetworkData::kRoutePreferenceHigh: + string.Append("high)"); + break; + case NetworkData::kRoutePreferenceMedium: + string.Append("med)"); + break; + case NetworkData::kRoutePreferenceLow: + string.Append("low)"); + break; + } + + return string; +} + +//--------------------------------------------------------------------------------------------------------------------- +// LocalOmrPrefix + +RoutingManager::LocalOmrPrefix::LocalOmrPrefix(Instance &aInstance) + : InstanceLocator(aInstance) + , mIsAddedInNetData(false) +{ +} + +void RoutingManager::LocalOmrPrefix::GenerateFrom(const Ip6::Prefix &aBrUlaPrefix) +{ + mPrefix = aBrUlaPrefix; + mPrefix.SetSubnetId(kOmrPrefixSubnetId); + mPrefix.SetLength(kOmrPrefixLength); + + LogInfo("Generated OMR prefix: %s", mPrefix.ToString().AsCString()); +} + +Error RoutingManager::LocalOmrPrefix::AddToNetData(void) +{ + Error error = kErrorNone; + NetworkData::OnMeshPrefixConfig config; + + VerifyOrExit(!mIsAddedInNetData); + + config.Clear(); + config.mPrefix = mPrefix; + config.mStable = true; + config.mSlaac = true; + config.mPreferred = true; + config.mOnMesh = true; + config.mDefaultRoute = false; + config.mPreference = NetworkData::kRoutePreferenceLow; + + error = Get().AddOnMeshPrefix(config); + + if (error != kErrorNone) + { + LogWarn("Failed to add local OMR prefix %s in Thread Network Data: %s", mPrefix.ToString().AsCString(), + ErrorToString(error)); + ExitNow(); + } + + mIsAddedInNetData = true; + Get().HandleServerDataUpdated(); + LogInfo("Added local OMR prefix %s in Thread Network Data", mPrefix.ToString().AsCString()); + +exit: + return error; +} + +void RoutingManager::LocalOmrPrefix::RemoveFromNetData(void) +{ + Error error = kErrorNone; + + VerifyOrExit(mIsAddedInNetData); + + error = Get().RemoveOnMeshPrefix(mPrefix); + + if (error != kErrorNone) + { + LogWarn("Failed to remove local OMR prefix %s from Thread Network Data: %s", mPrefix.ToString().AsCString(), + ErrorToString(error)); + ExitNow(); + } + + mIsAddedInNetData = false; + Get().HandleServerDataUpdated(); + LogInfo("Removed local OMR prefix %s from Thread Network Data", mPrefix.ToString().AsCString()); + +exit: + return; +} + } // namespace BorderRouter } // namespace ot diff --git a/util/third_party/openthread/src/core/border_router/routing_manager.hpp b/util/third_party/openthread/src/core/border_router/routing_manager.hpp index b4b5014603..a8f9dbb633 100644 --- a/util/third_party/openthread/src/core/border_router/routing_manager.hpp +++ b/util/third_party/openthread/src/core/border_router/routing_manager.hpp @@ -50,13 +50,16 @@ #include #include "border_router/infra_if.hpp" -#include "border_router/router_advertisement.hpp" #include "common/array.hpp" #include "common/error.hpp" +#include "common/linked_list.hpp" #include "common/locator.hpp" #include "common/notifier.hpp" +#include "common/pool.hpp" +#include "common/string.hpp" #include "common/timer.hpp" #include "net/ip6.hpp" +#include "net/nd6.hpp" #include "thread/network_data.hpp" namespace ot { @@ -76,6 +79,8 @@ class RoutingManager : public InstanceLocator friend class ot::Instance; public: + typedef NetworkData::RoutePreference RoutePreference; ///< Route preference (high, medium, low). + /** * This constructor initializes the routing manager. * @@ -110,6 +115,29 @@ class RoutingManager : public InstanceLocator */ Error SetEnabled(bool aEnabled); + /** + * This method gets the preference used when advertising Route Info Options (e.g., for discovered OMR prefixes) in + * Router Advertisement messages sent over the infrastructure link. + * + * @returns The Route Info Option preference. + * + */ + RoutePreference GetRouteInfoOptionPreference(void) const { return mRouteInfoOptionPreference; } + + /** + * This method sets the preference to use when advertising Route Info Options (e.g., for discovered OMR prefixes) + * in Router Advertisement messages sent over the infrastructure link. + * + * By default BR will use 'medium' preference level but this method allows the default value to be changed. As an + * example, it can be set to 'low' preference in the case where device is a temporary BR (a mobile BR or a + * battery-powered BR) to indicate that other BRs (if any) should be preferred over this BR on the infrastructure + * link. + * + * @param[in] aPreference The route preference to use. + * + */ + void SetRouteInfoOptionPreference(RoutePreference aPreference); + /** * This method returns the off-mesh-routable (OMR) prefix. * @@ -192,16 +220,11 @@ class RoutingManager : public InstanceLocator static bool IsValidOmrPrefix(const Ip6::Prefix &aOmrPrefix); private: - typedef NetworkData::RoutePreference RoutePreference; - static constexpr uint16_t kMaxRouterAdvMessageLength = 256; // The maximum RA message length we can handle. // The maximum number of the OMR prefixes to advertise. static constexpr uint8_t kMaxOmrPrefixNum = OPENTHREAD_CONFIG_IP6_SLAAC_NUM_ADDRESSES; - // The maximum number of prefixes to discover on the infra link. - static constexpr uint8_t kMaxDiscoveredPrefixNum = OPENTHREAD_CONFIG_BORDER_ROUTING_MAX_DISCOVERED_PREFIXES; - static constexpr uint8_t kOmrPrefixLength = OT_IP6_PREFIX_BITSIZE; // The length of an OMR prefix. In bits. static constexpr uint8_t kOnLinkPrefixLength = OT_IP6_PREFIX_BITSIZE; // The length of an On-link prefix. In bits. static constexpr uint8_t kBrUlaPrefixLength = 48; // The length of a BR ULA prefix. In bits. @@ -243,43 +266,205 @@ class RoutingManager : public InstanceLocator static_assert(kRtrAdvStaleTime >= 1800 && kRtrAdvStaleTime <= kDefaultOnLinkPrefixLifetime, "invalid RA STALE time"); - // A prefix discovered from Router Advert msg from infra netif - class ExternalPrefix : private Clearable, public Unequatable + class DiscoveredPrefixTable : public InstanceLocator { + // This class maintains the discovered on-link and route prefixes + // from the received RA messages by processing PIO and RIO options + // from the message. It takes care of processing the RA message but + // delegates the decision whether to include or exclude a prefix to + // `RoutingManager` by calling its `ShouldProcessPrefixInfoOption()` + // and `ShouldProcessRouteInfoOption()` methods. + // + // It manages the lifetime of the discovered entries and publishes + // and unpublishes the prefixes in the Network Data (as external + // route) as they are added or removed. + // + // When there is any change in the table (an entry is added, removed, + // or modified), it signals the change to `RoutingManager` by calling + // `HandleDiscoveredPrefixTableChanged()` callback. A `Tasklet` is + // used for signalling which ensures that if there are multiple + // changes within the same flow of execution, the callback is + // invoked after all the changes are processed. + public: - void InitFrom(const RouterAdv::PrefixInfoOption &aPio); - void InitFrom(const RouterAdv::RouteInfoOption &aRio); - bool IsOnLinkPrefix(void) const { return mIsOnLinkPrefix; } - const Ip6::Prefix &GetPrefix(void) const { return mPrefix; } - const TimeMilli & GetLastUpdateTime(void) const { return mLastUpdateTime; } - uint32_t GetValidLifetime(void) const { return mValidLifetime; } - void ClearValidLifetime(void) { mValidLifetime = 0; } - TimeMilli GetExpireTime(void) const { return mLastUpdateTime + GetPrefixExpireDelay(mValidLifetime); } - TimeMilli GetStaleTime(void) const; - bool operator==(const ExternalPrefix &aPrefix) const; - - // Methods to use when `IsOnLinkPrefix()` - uint32_t GetPreferredLifetime(void) const { return mPreferredLifetime; } - void ClearPreferredLifetime(void) { mPreferredLifetime = 0; } - bool IsDeprecated(void) const; - void AdoptValidAndPreferredLiftimesFrom(const ExternalPrefix &Prefix); - - // Method to use when `!IsOnlinkPrefix()` - RoutePreference GetRoutePreference(void) const { return mRoutePreference; } + enum NetDataMode : uint8_t // Used in `Remove{}` methods + { + kUnpublishFromNetData, // Unpublish the entry from Network Data if previously published. + kKeepInNetData, // Keep entry in Network Data if previously published. + }; + + explicit DiscoveredPrefixTable(Instance &aInstance); + + void ProcessRouterAdvertMessage(const Ip6::Nd::RouterAdvertMessage &aRaMessage, + const Ip6::Address & aSrcAddress); + + void SetAllowDefaultRouteInNetData(bool aAllow); + + void FindFavoredOnLinkPrefix(Ip6::Prefix &aPrefix) const; + bool ContainsOnLinkPrefix(const Ip6::Prefix &aPrefix) const; + void RemoveOnLinkPrefix(const Ip6::Prefix &aPrefix, NetDataMode aNetDataMode); + + bool ContainsRoutePrefix(const Ip6::Prefix &aPrefix) const; + void RemoveRoutePrefix(const Ip6::Prefix &aPrefix, NetDataMode aNetDataMode); + + void RemoveAllEntries(void); + void RemoveOrDeprecateOldEntries(TimeMilli aTimeThreshold); + + TimeMilli CalculateNextStaleTime(TimeMilli aNow) const; private: - static uint32_t GetPrefixExpireDelay(uint32_t aValidLifetime); + static constexpr uint16_t kMaxRouters = OPENTHREAD_CONFIG_BORDER_ROUTING_MAX_DISCOVERED_ROUTERS; + static constexpr uint16_t kMaxEntries = OPENTHREAD_CONFIG_BORDER_ROUTING_MAX_DISCOVERED_PREFIXES; + + class Entry : public LinkedListEntry, public Unequatable, private Clearable + { + friend class LinkedListEntry; + + public: + enum Type : uint8_t + { + kTypeOnLink, + kTypeRoute, + }; + + struct Matcher + { + Matcher(const Ip6::Prefix &aPrefix, Type aType) + : mPrefix(aPrefix) + , mType(aType) + { + } + + const Ip6::Prefix &mPrefix; + bool mType; + }; + + struct ExpirationChecker + { + explicit ExpirationChecker(TimeMilli aNow) + : mNow(aNow) + { + } + + TimeMilli mNow; + }; + + void InitFrom(const Ip6::Nd::RouterAdvertMessage::Header &aRaHeader); + void InitFrom(const Ip6::Nd::PrefixInfoOption &aPio); + void InitFrom(const Ip6::Nd::RouteInfoOption &aRio); + Type GetType(void) const { return mType; } + bool IsOnLinkPrefix(void) const { return (mType == kTypeOnLink); } + const Ip6::Prefix &GetPrefix(void) const { return mPrefix; } + const TimeMilli & GetLastUpdateTime(void) const { return mLastUpdateTime; } + uint32_t GetValidLifetime(void) const { return mValidLifetime; } + void ClearValidLifetime(void) { mValidLifetime = 0; } + TimeMilli GetExpireTime(void) const; + TimeMilli GetStaleTime(void) const; + RoutePreference GetPreference(void) const; + bool operator==(const Entry &aOther) const; + bool Matches(const Matcher &aMatcher) const; + bool Matches(const ExpirationChecker &aCheker) const; + + // Methods to use when `IsOnLinkPrefix()` + uint32_t GetPreferredLifetime(void) const { return mShared.mPreferredLifetime; } + void ClearPreferredLifetime(void) { mShared.mPreferredLifetime = 0; } + bool IsDeprecated(void) const; + void AdoptValidAndPreferredLiftimesFrom(const Entry &aEntry); + + // Method to use when `!IsOnlinkPrefix()` + RoutePreference GetRoutePreference(void) const { return mShared.mRoutePreference; } + + private: + static uint32_t CalculateExpireDelay(uint32_t aValidLifetime); + + Entry * mNext; + Ip6::Prefix mPrefix; + Type mType; + TimeMilli mLastUpdateTime; + uint32_t mValidLifetime; + union + { + uint32_t mPreferredLifetime; // Applicable when prefix is on-link. + RoutePreference mRoutePreference; // Applicable when prefix is not on-link + } mShared; + }; + + struct Router + { + enum EmptyChecker : uint8_t + { + kContainsNoEntries + }; + + bool Matches(const Ip6::Address &aAddress) const { return aAddress == mAddress; } + bool Matches(EmptyChecker) const { return mEntries.IsEmpty(); } + + Ip6::Address mAddress; + LinkedList mEntries; + }; + + void ProcessDefaultRoute(const Ip6::Nd::RouterAdvertMessage::Header &aRaHeader, Router &aRouter); + void ProcessPrefixInfoOption(const Ip6::Nd::PrefixInfoOption &aPio, Router &aRouter); + void ProcessRouteInfoOption(const Ip6::Nd::RouteInfoOption &aRio, Router &aRouter); + bool ContainsPrefix(const Entry::Matcher &aMatcher) const; + void RemovePrefix(const Entry::Matcher &aMatcher, NetDataMode aNetDataMode); + void RemoveRoutersWithNoEntries(void); + Entry * AllocateEntry(void) { return mEntryPool.Allocate(); } + void FreeEntry(Entry &aEntry) { mEntryPool.Free(aEntry); } + void FreeEntries(LinkedList &aEntries); + void UpdateNetworkDataOnChangeTo(Entry &aEntry); + Entry * FindFavoredEntryToPublish(const Ip6::Prefix &aPrefix); + void PublishEntry(const Entry &aEntry); + void UnpublishEntry(const Entry &aEntry); + static void HandleTimer(Timer &aTimer); + void HandleTimer(void); + void RemoveExpiredEntries(void); + void SignalTableChanged(void); + static void HandleSignalTask(Tasklet &aTasklet); + + Array mRouters; + Pool mEntryPool; + TimerMilli mTimer; + Tasklet mSignalTask; + bool mAllowDefaultRouteInNetData; + }; + + class OmrPrefix // An OMR Prefix + { + public: + static constexpr uint16_t kInfoStringSize = 60; + typedef String InfoString; + void Init(const Ip6::Prefix &aPrefix, RoutePreference aPreference); + void InitFrom(NetworkData::OnMeshPrefixConfig &aOnMeshPrefixConfig); + const Ip6::Prefix &GetPrefix(void) const { return mPrefix; } + RoutePreference GetPreference(void) const { return mPreference; } + void SetPreference(RoutePreference aPreference) { mPreference = aPreference; } + bool Matches(const Ip6::Prefix &aPrefix) const { return mPrefix == aPrefix; } + bool IsFavoredOver(const OmrPrefix &aOther) const; + InfoString ToString(void) const; + + private: Ip6::Prefix mPrefix; - TimeMilli mLastUpdateTime; - uint32_t mValidLifetime; - uint32_t mPreferredLifetime; // Applicable when prefix is on-link. - RoutePreference mRoutePreference; // Applicable when prefix is not on-link - bool mIsOnLinkPrefix; + RoutePreference mPreference; }; - typedef Array OmrPrefixArray; - typedef Array ExternalPrefixArray; + typedef Array OmrPrefixArray; + + class LocalOmrPrefix : InstanceLocator + { + public: + explicit LocalOmrPrefix(Instance &aInstance); + void GenerateFrom(const Ip6::Prefix &aBrUlaPrefix); + const Ip6::Prefix &GetPrefix(void) const { return mPrefix; } + Error AddToNetData(void); + void RemoveFromNetData(void); + bool IsAddedInNetData(void) const { return mIsAddedInNetData; } + + private: + Ip6::Prefix mPrefix; + bool mIsAddedInNetData; + }; void EvaluateState(void); void Start(void); @@ -288,7 +473,6 @@ class RoutingManager : public InstanceLocator bool IsInitialized(void) const { return mInfraIf.IsInitialized(); } bool IsEnabled(void) const { return mIsEnabled; } Error LoadOrGenerateRandomBrUlaPrefix(void); - void GenerateOmrPrefix(void); void GenerateOnLinkPrefix(void); void EvaluateOnLinkPrefix(void); @@ -302,9 +486,6 @@ class RoutingManager : public InstanceLocator void StartRoutingPolicyEvaluationJitter(uint32_t aJitterMilli); void StartRoutingPolicyEvaluationDelay(uint32_t aDelayMilli); void EvaluateOmrPrefix(OmrPrefixArray &aNewOmrPrefixes); - Error PublishLocalOmrPrefix(void); - void UnpublishLocalOmrPrefix(void); - bool IsOmrPrefixAddedToLocalNetworkData(void) const; Error PublishExternalRoute(const Ip6::Prefix &aPrefix, RoutePreference aRoutePreference, bool aNat64 = false); void UnpublishExternalRoute(const Ip6::Prefix &aPrefix); void StartRouterSolicitationDelay(void); @@ -325,16 +506,17 @@ class RoutingManager : public InstanceLocator void DeprecateOnLinkPrefix(void); void HandleRouterSolicit(const InfraIf::Icmp6Packet &aPacket, const Ip6::Address &aSrcAddress); void HandleRouterAdvertisement(const InfraIf::Icmp6Packet &aPacket, const Ip6::Address &aSrcAddress); - bool UpdateDiscoveredOnLinkPrefix(const RouterAdv::PrefixInfoOption &aPio); - void UpdateDiscoveredOmrPrefix(const RouterAdv::RouteInfoOption &aRio); - void InvalidateDiscoveredPrefixes(void); - void InvalidateAllDiscoveredPrefixes(void); + bool ShouldProcessPrefixInfoOption(const Ip6::Nd::PrefixInfoOption &aPio, const Ip6::Prefix &aPrefix); + bool ShouldProcessRouteInfoOption(const Ip6::Nd::RouteInfoOption &aRio, const Ip6::Prefix &aPrefix); + void UpdateDiscoveredPrefixTableOnNetDataChange(void); + void HandleDiscoveredPrefixTableChanged(void); bool NetworkDataContainsOmrPrefix(const Ip6::Prefix &aPrefix) const; - bool UpdateRouterAdvMessage(const RouterAdv::RouterAdvMessage *aRouterAdvMessage); + void UpdateRouterAdvertHeader(const Ip6::Nd::RouterAdvertMessage *aRouterAdvertMessage); + bool IsReceivdRouterAdvertFromManager(const Ip6::Nd::RouterAdvertMessage &aRaMessage) const; void ResetDiscoveredPrefixStaleTimer(void); static bool IsValidBrUlaPrefix(const Ip6::Prefix &aBrUlaPrefix); - static bool IsValidOnLinkPrefix(const RouterAdv::PrefixInfoOption &aPio); + static bool IsValidOnLinkPrefix(const Ip6::Nd::PrefixInfoOption &aPio); static bool IsValidOnLinkPrefix(const Ip6::Prefix &aOnLinkPrefix); // Indicates whether the Routing Manager is running (started). @@ -350,8 +532,7 @@ class RoutingManager : public InstanceLocator // randomly generated if none is found in persistent storage. Ip6::Prefix mBrUlaPrefix; - // The OMR prefix allocated from the /48 BR ULA prefix. - Ip6::Prefix mLocalOmrPrefix; + LocalOmrPrefix mLocalOmrPrefix; // The advertised OMR prefixes. For a stable Thread network without // manually configured OMR prefixes, there should be a single OMR @@ -361,6 +542,12 @@ class RoutingManager : public InstanceLocator // advertised on infra link. OmrPrefixArray mAdvertisedOmrPrefixes; + RoutePreference mRouteInfoOptionPreference; + + // The currently favored (smallest) discovered on-link prefix. + // Prefix length of zero indicates there is none. + Ip6::Prefix mFavoredDiscoveredOnLinkPrefix; + // The on-link prefix loaded from local persistent storage or // randomly generated if non is found in persistent storage. Ip6::Prefix mLocalOnLinkPrefix; @@ -378,20 +565,15 @@ class RoutingManager : public InstanceLocator // True if the local NAT64 prefix is advertised in Thread network. bool mIsAdvertisingLocalNat64Prefix; - // The array of prefixes discovered on the infra link. Those - // prefixes consist of on-link prefix(es) and OMR prefixes - // advertised by BRs in another Thread Network which is connected to - // the same infra link. - ExternalPrefixArray mDiscoveredPrefixes; + DiscoveredPrefixTable mDiscoveredPrefixTable; // The RA header and parameters for the infra interface. // This value is initialized with `RouterAdvMessage::SetToDefault` // and updated with RA messages initiated from infra interface. - RouterAdv::RouterAdvMessage mRouterAdvMessage; - TimeMilli mTimeRouterAdvMessageLastUpdate; - bool mLearntRouterAdvMessageFromHost; + Ip6::Nd::RouterAdvertMessage::Header mRouterAdvertHeader; + TimeMilli mTimeRouterAdvMessageLastUpdate; + bool mLearntRouterAdvMessageFromHost; - TimerMilli mDiscoveredPrefixInvalidTimer; TimerMilli mDiscoveredPrefixStaleTimer; uint32_t mRouterAdvertisementCount; diff --git a/util/third_party/openthread/src/core/common/array.hpp b/util/third_party/openthread/src/core/common/array.hpp index ded006f939..2afb4fda5d 100644 --- a/util/third_party/openthread/src/core/common/array.hpp +++ b/util/third_party/openthread/src/core/common/array.hpp @@ -310,6 +310,27 @@ class Array */ IndexType IndexOf(const Type &aElement) const { return static_cast(&aElement - &mElements[0]); } + /** + * This method removes an element from the array. + * + * The @p aElement MUST be from the array, otherwise the behavior of this method is undefined. + * + * To remove @p aElement, it is replaced by the last element in array, so the order of items in the array can + * change after a call to this method. + * + * The method uses assignment `=` operator on `Type` to copy the last element in place of @p aElement. + * + */ + void Remove(Type &aElement) + { + Type *lastElement = PopBack(); + + if (lastElement != &aElement) + { + aElement = *lastElement; + } + } + /** * This method finds the first match of a given entry in the array. * @@ -430,6 +451,68 @@ class Array return FindMatching(aIndicator) != nullptr; } + /** + * This template method removes the first element in the array matching a given indicator. + * + * This method behaves similar to `Remove()`, i.e., the matched element (if found) is replaced with the last element + * in the array (using `=` operator on `Type`). So the order of items in the array can change after a call to this + * method. + * + * The template type `Indicator` specifies the type of @p aIndicator object which is used to match against elements + * in the array. To check that an element matches the given indicator, the `Matches()` method is invoked on each + * `Type` element in the array. The `Matches()` method should be provided by `Type` class accordingly: + * + * bool Type::Matches(const Indicator &aIndicator) const + * + * @param[in] aIndicator An indicator to match with elements in the array. + * + */ + template void RemoveMatching(const Indicator &aIndicator) + { + Type *entry = FindMatching(aIndicator); + + if (entry != nullptr) + { + Remove(*entry); + } + } + + /** + * This template method removes all elements in the array matching a given indicator. + * + * This method behaves similar to `Remove()`, i.e., a matched element is replaced with the last element in the + * array (using `=` operator on `Type`). So the order of items in the array can change after a call to this method. + * + * The template type `Indicator` specifies the type of @p aIndicator object which is used to match against elements + * in the array. To check that an element matches the given indicator, the `Matches()` method is invoked on each + * `Type` element in the array. The `Matches()` method should be provided by `Type` class accordingly: + * + * bool Type::Matches(const Indicator &aIndicator) const + * + * @param[in] aIndicator An indicator to match with elements in the array. + * + */ + template void RemoveAllMatching(const Indicator &aIndicator) + { + for (IndexType index = 0; index < GetLength();) + { + Type &entry = mElements[index]; + + if (entry.Matches(aIndicator)) + { + Remove(entry); + + // When the entry is removed from the array it is + // replaced with the last element. In this case, we do + // not increment `index`. + } + else + { + index++; + } + } + } + /** * This method overloads assignment `=` operator to copy elements from another array into the array. * diff --git a/util/third_party/openthread/src/core/common/instance.cpp b/util/third_party/openthread/src/core/common/instance.cpp index 0ab3d5048e..3b88891600 100644 --- a/util/third_party/openthread/src/core/common/instance.cpp +++ b/util/third_party/openthread/src/core/common/instance.cpp @@ -78,6 +78,121 @@ Instance::Instance(void) , mMessagePool(*this) , mIp6(*this) , mThreadNetif(*this) + , mTmfAgent(*this) +#if OPENTHREAD_CONFIG_DHCP6_CLIENT_ENABLE + , mDhcp6Client(*this) +#endif +#if OPENTHREAD_CONFIG_DHCP6_SERVER_ENABLE + , mDhcp6Server(*this) +#endif +#if OPENTHREAD_CONFIG_NEIGHBOR_DISCOVERY_AGENT_ENABLE + , mNeighborDiscoveryAgent(*this) +#endif +#if OPENTHREAD_CONFIG_IP6_SLAAC_ENABLE + , mSlaac(*this) +#endif +#if OPENTHREAD_CONFIG_DNS_CLIENT_ENABLE + , mDnsClient(*this) +#endif +#if OPENTHREAD_CONFIG_SRP_CLIENT_ENABLE + , mSrpClient(*this) +#endif +#if OPENTHREAD_CONFIG_SRP_CLIENT_BUFFERS_ENABLE + , mSrpClientBuffers(*this) +#endif +#if OPENTHREAD_CONFIG_DNSSD_SERVER_ENABLE + , mDnssdServer(*this) +#endif +#if OPENTHREAD_CONFIG_DNS_DSO_ENABLE + , mDnsDso(*this) +#endif +#if OPENTHREAD_CONFIG_SNTP_CLIENT_ENABLE + , mSntpClient(*this) +#endif + , mActiveDataset(*this) + , mPendingDataset(*this) + , mExtendedPanIdManager(*this) + , mNetworkNameManager(*this) + , mIp6Filter(*this) + , mKeyManager(*this) + , mLowpan(*this) + , mMac(*this) + , mMeshForwarder(*this) + , mMleRouter(*this) + , mDiscoverScanner(*this) + , mAddressResolver(*this) +#if OPENTHREAD_CONFIG_MULTI_RADIO + , mRadioSelector(*this) +#endif +#if OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE || OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE + , mNetworkDataLocal(*this) +#endif + , mNetworkDataLeader(*this) +#if OPENTHREAD_FTD || OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE || OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE + , mNetworkDataNotifier(*this) +#endif +#if OPENTHREAD_CONFIG_NETDATA_PUBLISHER_ENABLE + , mNetworkDataPublisher(*this) +#endif + , mNetworkDataServiceManager(*this) +#if OPENTHREAD_FTD || OPENTHREAD_CONFIG_TMF_NETWORK_DIAG_MTD_ENABLE + , mNetworkDiagnostic(*this) +#endif +#if OPENTHREAD_CONFIG_BORDER_AGENT_ENABLE + , mBorderAgent(*this) +#endif +#if OPENTHREAD_CONFIG_COMMISSIONER_ENABLE && OPENTHREAD_FTD + , mCommissioner(*this) +#endif +#if OPENTHREAD_CONFIG_DTLS_ENABLE + , mCoapSecure(*this) +#endif +#if OPENTHREAD_CONFIG_JOINER_ENABLE + , mJoiner(*this) +#endif +#if OPENTHREAD_CONFIG_JAM_DETECTION_ENABLE + , mJamDetector(*this) +#endif +#if OPENTHREAD_FTD + , mJoinerRouter(*this) + , mLeader(*this) +#endif +#if (OPENTHREAD_CONFIG_THREAD_VERSION >= OT_THREAD_VERSION_1_2) + , mBackboneRouterLeader(*this) +#endif +#if OPENTHREAD_FTD && OPENTHREAD_CONFIG_BACKBONE_ROUTER_ENABLE + , mBackboneRouterLocal(*this) + , mBackboneRouterManager(*this) +#endif +#if OPENTHREAD_CONFIG_MLR_ENABLE || (OPENTHREAD_FTD && OPENTHREAD_CONFIG_TMF_PROXY_MLR_ENABLE) + , mMlrManager(*this) +#endif + +#if OPENTHREAD_CONFIG_DUA_ENABLE || (OPENTHREAD_FTD && OPENTHREAD_CONFIG_TMF_PROXY_DUA_ENABLE) + , mDuaManager(*this) +#endif +#if OPENTHREAD_CONFIG_SRP_SERVER_ENABLE + , mSrpServer(*this) +#endif + +#if OPENTHREAD_CONFIG_CHILD_SUPERVISION_ENABLE +#if OPENTHREAD_FTD + , mChildSupervisor(*this) +#endif + , mSupervisionListener(*this) +#endif + , mAnnounceBegin(*this) + , mPanIdQuery(*this) + , mEnergyScan(*this) +#if OPENTHREAD_CONFIG_TMF_ANYCAST_LOCATOR_ENABLE + , mAnycastLocator(*this) +#endif +#if OPENTHREAD_CONFIG_TIME_SYNC_ENABLE + , mTimeSync(*this) +#endif +#if OPENTHREAD_CONFIG_MLE_LINK_METRICS_INITIATOR_ENABLE || OPENTHREAD_CONFIG_MLE_LINK_METRICS_SUBJECT_ENABLE + , mLinkMetrics(*this) +#endif #if OPENTHREAD_CONFIG_COAP_API_ENABLE , mApplicationCoap(*this) #endif diff --git a/util/third_party/openthread/src/core/common/instance.hpp b/util/third_party/openthread/src/core/common/instance.hpp index ddb1477da4..d5800a5459 100644 --- a/util/third_party/openthread/src/core/common/instance.hpp +++ b/util/third_party/openthread/src/core/common/instance.hpp @@ -63,28 +63,72 @@ #include "utils/otns.hpp" #if OPENTHREAD_FTD || OPENTHREAD_MTD +#include "backbone_router/backbone_tmf.hpp" #include "backbone_router/bbr_leader.hpp" #include "backbone_router/bbr_local.hpp" +#include "backbone_router/bbr_manager.hpp" #include "border_router/routing_manager.hpp" +#include "coap/coap_secure.hpp" #include "common/code_utils.hpp" #include "common/notifier.hpp" #include "common/settings.hpp" #include "crypto/mbedtls.hpp" +#include "mac/mac.hpp" #include "meshcop/border_agent.hpp" +#include "meshcop/commissioner.hpp" +#include "meshcop/dataset_manager.hpp" #include "meshcop/dataset_updater.hpp" #include "meshcop/extended_panid.hpp" +#include "meshcop/joiner.hpp" +#include "meshcop/joiner_router.hpp" +#include "meshcop/meshcop_leader.hpp" #include "meshcop/network_name.hpp" +#include "net/dhcp6.hpp" +#include "net/dhcp6_client.hpp" +#include "net/dhcp6_server.hpp" +#include "net/dns_client.hpp" +#include "net/dns_dso.hpp" +#include "net/dnssd_server.hpp" #include "net/ip6.hpp" +#include "net/ip6_filter.hpp" +#include "net/nd_agent.hpp" +#include "net/netif.hpp" +#include "net/sntp_client.hpp" +#include "net/srp_client.hpp" +#include "net/srp_server.hpp" +#include "thread/address_resolver.hpp" +#include "thread/announce_begin_server.hpp" #include "thread/announce_sender.hpp" +#include "thread/anycast_locator.hpp" +#include "thread/discover_scanner.hpp" +#include "thread/dua_manager.hpp" +#include "thread/energy_scan_server.hpp" +#include "thread/key_manager.hpp" #include "thread/link_metrics.hpp" #include "thread/link_quality.hpp" +#include "thread/mesh_forwarder.hpp" +#include "thread/mle.hpp" +#include "thread/mle_router.hpp" +#include "thread/mlr_manager.hpp" +#include "thread/network_data_local.hpp" +#include "thread/network_data_notifier.hpp" +#include "thread/network_data_publisher.hpp" +#include "thread/network_data_service.hpp" +#include "thread/network_diagnostic.hpp" +#include "thread/panid_query_server.hpp" +#include "thread/radio_selector.hpp" #include "thread/thread_netif.hpp" +#include "thread/time_sync_service.hpp" #include "thread/tmf.hpp" #include "utils/channel_manager.hpp" #include "utils/channel_monitor.hpp" +#include "utils/child_supervision.hpp" #include "utils/heap.hpp" #include "utils/history_tracker.hpp" +#include "utils/jam_detector.hpp" #include "utils/ping_sender.hpp" +#include "utils/slaac_address.hpp" +#include "utils/srp_client_buffers.hpp" #endif // OPENTHREAD_FTD || OPENTHREAD_MTD /** @@ -348,6 +392,7 @@ class Instance : public otInstance, private NonCopyable // (particularly, SubMac and Mac) to allow them to use its methods // from their constructor. Radio mRadio; + #if OPENTHREAD_CONFIG_UPTIME_ENABLE Uptime mUptime; #endif @@ -364,6 +409,153 @@ class Instance : public otInstance, private NonCopyable Ip6::Ip6 mIp6; ThreadNetif mThreadNetif; + Tmf::Agent mTmfAgent; + +#if OPENTHREAD_CONFIG_DHCP6_CLIENT_ENABLE + Dhcp6::Client mDhcp6Client; +#endif + +#if OPENTHREAD_CONFIG_DHCP6_SERVER_ENABLE + Dhcp6::Server mDhcp6Server; +#endif + +#if OPENTHREAD_CONFIG_NEIGHBOR_DISCOVERY_AGENT_ENABLE + NeighborDiscovery::Agent mNeighborDiscoveryAgent; +#endif + +#if OPENTHREAD_CONFIG_IP6_SLAAC_ENABLE + Utils::Slaac mSlaac; +#endif + +#if OPENTHREAD_CONFIG_DNS_CLIENT_ENABLE + Dns::Client mDnsClient; +#endif + +#if OPENTHREAD_CONFIG_SRP_CLIENT_ENABLE + Srp::Client mSrpClient; +#endif + +#if OPENTHREAD_CONFIG_SRP_CLIENT_BUFFERS_ENABLE + Utils::SrpClientBuffers mSrpClientBuffers; +#endif + +#if OPENTHREAD_CONFIG_DNSSD_SERVER_ENABLE + Dns::ServiceDiscovery::Server mDnssdServer; +#endif + +#if OPENTHREAD_CONFIG_DNS_DSO_ENABLE + Dns::Dso mDnsDso; +#endif + +#if OPENTHREAD_CONFIG_SNTP_CLIENT_ENABLE + Sntp::Client mSntpClient; +#endif + + MeshCoP::ActiveDatasetManager mActiveDataset; + MeshCoP::PendingDatasetManager mPendingDataset; + MeshCoP::ExtendedPanIdManager mExtendedPanIdManager; + MeshCoP::NetworkNameManager mNetworkNameManager; + Ip6::Filter mIp6Filter; + KeyManager mKeyManager; + Lowpan::Lowpan mLowpan; + Mac::Mac mMac; + MeshForwarder mMeshForwarder; + Mle::MleRouter mMleRouter; + Mle::DiscoverScanner mDiscoverScanner; + AddressResolver mAddressResolver; + +#if OPENTHREAD_CONFIG_MULTI_RADIO + RadioSelector mRadioSelector; +#endif + +#if OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE || OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE + NetworkData::Local mNetworkDataLocal; +#endif + + NetworkData::Leader mNetworkDataLeader; + +#if OPENTHREAD_FTD || OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE || OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE + NetworkData::Notifier mNetworkDataNotifier; +#endif + +#if OPENTHREAD_CONFIG_NETDATA_PUBLISHER_ENABLE + NetworkData::Publisher mNetworkDataPublisher; +#endif + + NetworkData::Service::Manager mNetworkDataServiceManager; + +#if OPENTHREAD_FTD || OPENTHREAD_CONFIG_TMF_NETWORK_DIAG_MTD_ENABLE + NetworkDiagnostic::NetworkDiagnostic mNetworkDiagnostic; +#endif + +#if OPENTHREAD_CONFIG_BORDER_AGENT_ENABLE + MeshCoP::BorderAgent mBorderAgent; +#endif + +#if OPENTHREAD_CONFIG_COMMISSIONER_ENABLE && OPENTHREAD_FTD + MeshCoP::Commissioner mCommissioner; +#endif + +#if OPENTHREAD_CONFIG_DTLS_ENABLE + Coap::CoapSecure mCoapSecure; +#endif + +#if OPENTHREAD_CONFIG_JOINER_ENABLE + MeshCoP::Joiner mJoiner; +#endif + +#if OPENTHREAD_CONFIG_JAM_DETECTION_ENABLE + Utils::JamDetector mJamDetector; +#endif + +#if OPENTHREAD_FTD + MeshCoP::JoinerRouter mJoinerRouter; + MeshCoP::Leader mLeader; +#endif + +#if (OPENTHREAD_CONFIG_THREAD_VERSION >= OT_THREAD_VERSION_1_2) + BackboneRouter::Leader mBackboneRouterLeader; +#endif + +#if OPENTHREAD_FTD && OPENTHREAD_CONFIG_BACKBONE_ROUTER_ENABLE + BackboneRouter::Local mBackboneRouterLocal; + BackboneRouter::Manager mBackboneRouterManager; +#endif + +#if OPENTHREAD_CONFIG_MLR_ENABLE || (OPENTHREAD_FTD && OPENTHREAD_CONFIG_TMF_PROXY_MLR_ENABLE) + MlrManager mMlrManager; +#endif + +#if OPENTHREAD_CONFIG_DUA_ENABLE || (OPENTHREAD_FTD && OPENTHREAD_CONFIG_TMF_PROXY_DUA_ENABLE) + DuaManager mDuaManager; +#endif + +#if OPENTHREAD_CONFIG_SRP_SERVER_ENABLE + Srp::Server mSrpServer; +#endif + +#if OPENTHREAD_CONFIG_CHILD_SUPERVISION_ENABLE +#if OPENTHREAD_FTD + Utils::ChildSupervisor mChildSupervisor; +#endif + Utils::SupervisionListener mSupervisionListener; +#endif + + AnnounceBeginServer mAnnounceBegin; + PanIdQueryServer mPanIdQuery; + EnergyScanServer mEnergyScan; + +#if OPENTHREAD_CONFIG_TMF_ANYCAST_LOCATOR_ENABLE + AnycastLocator mAnycastLocator; +#endif + +#if OPENTHREAD_CONFIG_TIME_SYNC_ENABLE + TimeSync mTimeSync; +#endif + +#if OPENTHREAD_CONFIG_MLE_LINK_METRICS_INITIATOR_ENABLE || OPENTHREAD_CONFIG_MLE_LINK_METRICS_SUBJECT_ENABLE + LinkMetrics::LinkMetrics mLinkMetrics; +#endif #if OPENTHREAD_CONFIG_COAP_API_ENABLE Coap::Coap mApplicationCoap; @@ -406,22 +598,27 @@ class Instance : public otInstance, private NonCopyable #endif #endif // OPENTHREAD_MTD || OPENTHREAD_FTD + #if OPENTHREAD_RADIO || OPENTHREAD_CONFIG_LINK_RAW_ENABLE Mac::LinkRaw mLinkRaw; -#endif // OPENTHREAD_RADIO || OPENTHREAD_CONFIG_LINK_RAW_ENABLE +#endif #if OPENTHREAD_CONFIG_LOG_LEVEL_DYNAMIC_ENABLE static LogLevel sLogLevel; #endif + #if OPENTHREAD_ENABLE_VENDOR_EXTENSION Extension::ExtensionBase &mExtension; #endif + #if OPENTHREAD_CONFIG_COPROCESSOR_RPC_ENABLE Coprocessor::RPC mCRPC; #endif + #if OPENTHREAD_CONFIG_DIAG_ENABLE FactoryDiags::Diags mDiags; #endif + bool mIsInitialized; #if OPENTHREAD_CONFIG_REFERENCE_DEVICE_ENABLE && (OPENTHREAD_FTD || OPENTHREAD_MTD) @@ -479,45 +676,45 @@ template <> inline SettingsDriver &Instance::Get(void) template <> inline MeshForwarder &Instance::Get(void) { - return mThreadNetif.mMeshForwarder; + return mMeshForwarder; } #if OPENTHREAD_CONFIG_MULTI_RADIO template <> inline RadioSelector &Instance::Get(void) { - return mThreadNetif.mRadioSelector; + return mRadioSelector; } #endif template <> inline Mle::Mle &Instance::Get(void) { - return mThreadNetif.mMleRouter; + return mMleRouter; } template <> inline Mle::MleRouter &Instance::Get(void) { - return mThreadNetif.mMleRouter; + return mMleRouter; } template <> inline Mle::DiscoverScanner &Instance::Get(void) { - return mThreadNetif.mDiscoverScanner; + return mDiscoverScanner; } template <> inline NeighborTable &Instance::Get(void) { - return mThreadNetif.mMleRouter.mNeighborTable; + return mMleRouter.mNeighborTable; } #if OPENTHREAD_FTD template <> inline ChildTable &Instance::Get(void) { - return mThreadNetif.mMleRouter.mChildTable; + return mMleRouter.mChildTable; } template <> inline RouterTable &Instance::Get(void) { - return mThreadNetif.mMleRouter.mRouterTable; + return mMleRouter.mRouterTable; } #endif @@ -538,144 +735,144 @@ template <> inline Ip6::Ip6 &Instance::Get(void) template <> inline Mac::Mac &Instance::Get(void) { - return mThreadNetif.mMac; + return mMac; } template <> inline Mac::SubMac &Instance::Get(void) { - return mThreadNetif.mMac.mLinks.mSubMac; + return mMac.mLinks.mSubMac; } #if OPENTHREAD_CONFIG_RADIO_LINK_TREL_ENABLE template <> inline Trel::Link &Instance::Get(void) { - return mThreadNetif.mMac.mLinks.mTrel; + return mMac.mLinks.mTrel; } template <> inline Trel::Interface &Instance::Get(void) { - return mThreadNetif.mMac.mLinks.mTrel.mInterface; + return mMac.mLinks.mTrel.mInterface; } #endif #if OPENTHREAD_CONFIG_MAC_FILTER_ENABLE template <> inline Mac::Filter &Instance::Get(void) { - return mThreadNetif.mMac.mFilter; + return mMac.mFilter; } #endif template <> inline Lowpan::Lowpan &Instance::Get(void) { - return mThreadNetif.mLowpan; + return mLowpan; } template <> inline KeyManager &Instance::Get(void) { - return mThreadNetif.mKeyManager; + return mKeyManager; } template <> inline Ip6::Filter &Instance::Get(void) { - return mThreadNetif.mIp6Filter; + return mIp6Filter; +} + +template <> inline AddressResolver &Instance::Get(void) +{ + return mAddressResolver; } #if OPENTHREAD_FTD template <> inline IndirectSender &Instance::Get(void) { - return mThreadNetif.mMeshForwarder.mIndirectSender; + return mMeshForwarder.mIndirectSender; } template <> inline SourceMatchController &Instance::Get(void) { - return mThreadNetif.mMeshForwarder.mIndirectSender.mSourceMatchController; + return mMeshForwarder.mIndirectSender.mSourceMatchController; } template <> inline DataPollHandler &Instance::Get(void) { - return mThreadNetif.mMeshForwarder.mIndirectSender.mDataPollHandler; + return mMeshForwarder.mIndirectSender.mDataPollHandler; } #if OPENTHREAD_CONFIG_MAC_CSL_TRANSMITTER_ENABLE template <> inline CslTxScheduler &Instance::Get(void) { - return mThreadNetif.mMeshForwarder.mIndirectSender.mCslTxScheduler; + return mMeshForwarder.mIndirectSender.mCslTxScheduler; } #endif -template <> inline AddressResolver &Instance::Get(void) -{ - return mThreadNetif.mAddressResolver; -} - template <> inline MeshCoP::Leader &Instance::Get(void) { - return mThreadNetif.mLeader; + return mLeader; } template <> inline MeshCoP::JoinerRouter &Instance::Get(void) { - return mThreadNetif.mJoinerRouter; + return mJoinerRouter; } #endif // OPENTHREAD_FTD template <> inline AnnounceBeginServer &Instance::Get(void) { - return mThreadNetif.mAnnounceBegin; + return mAnnounceBegin; } template <> inline DataPollSender &Instance::Get(void) { - return mThreadNetif.mMeshForwarder.mDataPollSender; + return mMeshForwarder.mDataPollSender; } template <> inline EnergyScanServer &Instance::Get(void) { - return mThreadNetif.mEnergyScan; + return mEnergyScan; } template <> inline PanIdQueryServer &Instance::Get(void) { - return mThreadNetif.mPanIdQuery; + return mPanIdQuery; } #if OPENTHREAD_CONFIG_TMF_ANYCAST_LOCATOR_ENABLE template <> inline AnycastLocator &Instance::Get(void) { - return mThreadNetif.mAnycastLocator; + return mAnycastLocator; } #endif #if OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE || OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE template <> inline NetworkData::Local &Instance::Get(void) { - return mThreadNetif.mNetworkDataLocal; + return mNetworkDataLocal; } #endif template <> inline NetworkData::Leader &Instance::Get(void) { - return mThreadNetif.mNetworkDataLeader; + return mNetworkDataLeader; } #if OPENTHREAD_FTD || OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE || OPENTHREAD_CONFIG_TMF_NETDATA_SERVICE_ENABLE template <> inline NetworkData::Notifier &Instance::Get(void) { - return mThreadNetif.mNetworkDataNotifier; + return mNetworkDataNotifier; } #endif #if OPENTHREAD_CONFIG_NETDATA_PUBLISHER_ENABLE template <> inline NetworkData::Publisher &Instance::Get(void) { - return mThreadNetif.mNetworkDataPublisher; + return mNetworkDataPublisher; } #endif template <> inline NetworkData::Service::Manager &Instance::Get(void) { - return mThreadNetif.mNetworkDataServiceManager; + return mNetworkDataServiceManager; } #if OPENTHREAD_CONFIG_TCP_ENABLE @@ -702,138 +899,138 @@ template <> inline Ip6::Mpl &Instance::Get(void) template <> inline Tmf::Agent &Instance::Get(void) { - return mThreadNetif.mTmfAgent; + return mTmfAgent; } #if OPENTHREAD_CONFIG_DTLS_ENABLE template <> inline Coap::CoapSecure &Instance::Get(void) { - return mThreadNetif.mCoapSecure; + return mCoapSecure; } #endif template <> inline MeshCoP::ExtendedPanIdManager &Instance::Get(void) { - return mThreadNetif.mExtendedPanIdManager; + return mExtendedPanIdManager; } template <> inline MeshCoP::NetworkNameManager &Instance::Get(void) { - return mThreadNetif.mNetworkNameManager; + return mNetworkNameManager; } template <> inline MeshCoP::ActiveDatasetManager &Instance::Get(void) { - return mThreadNetif.mActiveDataset; + return mActiveDataset; } template <> inline MeshCoP::PendingDatasetManager &Instance::Get(void) { - return mThreadNetif.mPendingDataset; + return mPendingDataset; } #if OPENTHREAD_CONFIG_TIME_SYNC_ENABLE template <> inline TimeSync &Instance::Get(void) { - return mThreadNetif.mTimeSync; + return mTimeSync; } #endif #if OPENTHREAD_CONFIG_COMMISSIONER_ENABLE && OPENTHREAD_FTD template <> inline MeshCoP::Commissioner &Instance::Get(void) { - return mThreadNetif.mCommissioner; + return mCommissioner; } #endif #if OPENTHREAD_CONFIG_JOINER_ENABLE template <> inline MeshCoP::Joiner &Instance::Get(void) { - return mThreadNetif.mJoiner; + return mJoiner; } #endif #if OPENTHREAD_CONFIG_DNS_CLIENT_ENABLE template <> inline Dns::Client &Instance::Get(void) { - return mThreadNetif.mDnsClient; + return mDnsClient; } #endif #if OPENTHREAD_CONFIG_SRP_CLIENT_ENABLE template <> inline Srp::Client &Instance::Get(void) { - return mThreadNetif.mSrpClient; + return mSrpClient; } #endif #if OPENTHREAD_CONFIG_SRP_CLIENT_BUFFERS_ENABLE template <> inline Utils::SrpClientBuffers &Instance::Get(void) { - return mThreadNetif.mSrpClientBuffers; + return mSrpClientBuffers; } #endif #if OPENTHREAD_CONFIG_DNSSD_SERVER_ENABLE template <> inline Dns::ServiceDiscovery::Server &Instance::Get(void) { - return mThreadNetif.mDnssdServer; + return mDnssdServer; } #endif #if OPENTHREAD_CONFIG_DNS_DSO_ENABLE template <> inline Dns::Dso &Instance::Get(void) { - return mThreadNetif.mDnsDso; + return mDnsDso; } #endif #if OPENTHREAD_FTD || OPENTHREAD_CONFIG_TMF_NETWORK_DIAG_MTD_ENABLE template <> inline NetworkDiagnostic::NetworkDiagnostic &Instance::Get(void) { - return mThreadNetif.mNetworkDiagnostic; + return mNetworkDiagnostic; } #endif #if OPENTHREAD_CONFIG_DHCP6_CLIENT_ENABLE template <> inline Dhcp6::Client &Instance::Get(void) { - return mThreadNetif.mDhcp6Client; + return mDhcp6Client; } #endif #if OPENTHREAD_CONFIG_DHCP6_SERVER_ENABLE template <> inline Dhcp6::Server &Instance::Get(void) { - return mThreadNetif.mDhcp6Server; + return mDhcp6Server; } #endif #if OPENTHREAD_CONFIG_NEIGHBOR_DISCOVERY_AGENT_ENABLE template <> inline NeighborDiscovery::Agent &Instance::Get(void) { - return mThreadNetif.mNeighborDiscoveryAgent; + return mNeighborDiscoveryAgent; } #endif #if OPENTHREAD_CONFIG_IP6_SLAAC_ENABLE template <> inline Utils::Slaac &Instance::Get(void) { - return mThreadNetif.mSlaac; + return mSlaac; } #endif #if OPENTHREAD_CONFIG_JAM_DETECTION_ENABLE template <> inline Utils::JamDetector &Instance::Get(void) { - return mThreadNetif.mJamDetector; + return mJamDetector; } #endif #if OPENTHREAD_CONFIG_SNTP_CLIENT_ENABLE template <> inline Sntp::Client &Instance::Get(void) { - return mThreadNetif.mSntpClient; + return mSntpClient; } #endif @@ -841,12 +1038,12 @@ template <> inline Sntp::Client &Instance::Get(void) #if OPENTHREAD_FTD template <> inline Utils::ChildSupervisor &Instance::Get(void) { - return mThreadNetif.mChildSupervisor; + return mChildSupervisor; } #endif template <> inline Utils::SupervisionListener &Instance::Get(void) { - return mThreadNetif.mSupervisionListener; + return mSupervisionListener; } #endif @@ -888,7 +1085,7 @@ template <> inline MeshCoP::DatasetUpdater &Instance::Get(void) #if OPENTHREAD_CONFIG_BORDER_AGENT_ENABLE template <> inline MeshCoP::BorderAgent &Instance::Get(void) { - return mThreadNetif.mBorderAgent; + return mBorderAgent; } #endif @@ -908,57 +1105,57 @@ template <> inline MessagePool &Instance::Get(void) template <> inline BackboneRouter::Leader &Instance::Get(void) { - return mThreadNetif.mBackboneRouterLeader; + return mBackboneRouterLeader; } #if OPENTHREAD_FTD && OPENTHREAD_CONFIG_BACKBONE_ROUTER_ENABLE template <> inline BackboneRouter::Local &Instance::Get(void) { - return mThreadNetif.mBackboneRouterLocal; + return mBackboneRouterLocal; } template <> inline BackboneRouter::Manager &Instance::Get(void) { - return mThreadNetif.mBackboneRouterManager; + return mBackboneRouterManager; } #if OPENTHREAD_CONFIG_BACKBONE_ROUTER_MULTICAST_ROUTING_ENABLE template <> inline BackboneRouter::MulticastListenersTable &Instance::Get(void) { - return mThreadNetif.mBackboneRouterManager.GetMulticastListenersTable(); + return mBackboneRouterManager.GetMulticastListenersTable(); } #endif #if OPENTHREAD_CONFIG_BACKBONE_ROUTER_DUA_NDPROXYING_ENABLE template <> inline BackboneRouter::NdProxyTable &Instance::Get(void) { - return mThreadNetif.mBackboneRouterManager.GetNdProxyTable(); + return mBackboneRouterManager.GetNdProxyTable(); } #endif template <> inline BackboneRouter::BackboneTmfAgent &Instance::Get(void) { - return mThreadNetif.mBackboneRouterManager.GetBackboneTmfAgent(); + return mBackboneRouterManager.GetBackboneTmfAgent(); } #endif #if OPENTHREAD_CONFIG_MLR_ENABLE || (OPENTHREAD_FTD && OPENTHREAD_CONFIG_TMF_PROXY_MLR_ENABLE) template <> inline MlrManager &Instance::Get(void) { - return mThreadNetif.mMlrManager; + return mMlrManager; } #endif #if OPENTHREAD_CONFIG_DUA_ENABLE || (OPENTHREAD_FTD && OPENTHREAD_CONFIG_TMF_PROXY_DUA_ENABLE) template <> inline DuaManager &Instance::Get(void) { - return mThreadNetif.mDuaManager; + return mDuaManager; } #endif #if OPENTHREAD_CONFIG_MLE_LINK_METRICS_INITIATOR_ENABLE || OPENTHREAD_CONFIG_MLE_LINK_METRICS_SUBJECT_ENABLE template <> inline LinkMetrics::LinkMetrics &Instance::Get(void) { - return mThreadNetif.mLinkMetrics; + return mLinkMetrics; } #endif @@ -986,7 +1183,7 @@ template <> inline BorderRouter::InfraIf &Instance::Get(void) #if OPENTHREAD_CONFIG_SRP_SERVER_ENABLE template <> inline Srp::Server &Instance::Get(void) { - return mThreadNetif.mSrpServer; + return mSrpServer; } #endif diff --git a/util/third_party/openthread/src/core/common/owning_list.hpp b/util/third_party/openthread/src/core/common/owning_list.hpp index be57ab9fb4..3b73fe6ebf 100644 --- a/util/third_party/openthread/src/core/common/owning_list.hpp +++ b/util/third_party/openthread/src/core/common/owning_list.hpp @@ -89,7 +89,7 @@ template class OwningList : public LinkedList * * @note This method does not change the popped entry itself, i.e., the popped entry next pointer stays as before. * - * @returns An `OwnerPtr` to the entry that was popped (set to null if list of empty). + * @returns An `OwnedPtr` to the entry that was popped (set to null if list of empty). * */ OwnedPtr Pop(void) { return OwnedPtr(LinkedList::Pop()); } @@ -102,7 +102,7 @@ template class OwningList : public LinkedList * @param[in] aPrevEntry A pointer to a previous entry. If it is not `nullptr` the entry after this will be popped, * otherwise (if it is `nullptr`) the entry at the head of the list is popped. * - * @returns An `OwnerPtr` to the entry that was popped (set to null if there is no entry to pop). + * @returns An `OwnedPtr` to the entry that was popped (set to null if there is no entry to pop). * */ OwnedPtr PopAfter(Type *aPrevEntry) { return OwnedPtr(LinkedList::PopAfter(aPrevEntry)); } @@ -121,7 +121,7 @@ template class OwningList : public LinkedList * * @param[in] aIndicator An entry indicator to match against entries in the list. * - * @returns An `OwnerPtr` to the entry that was removed (set to null if there is no matching entry to remove). + * @returns An `OwnedPtr` to the entry that was removed (set to null if there is no matching entry to remove). * */ template OwnedPtr RemoveMatching(const Indicator &aIndicator) diff --git a/util/third_party/openthread/src/core/common/time_ticker.cpp b/util/third_party/openthread/src/core/common/time_ticker.cpp index c770275e54..2bfb130a13 100644 --- a/util/third_party/openthread/src/core/common/time_ticker.cpp +++ b/util/third_party/openthread/src/core/common/time_ticker.cpp @@ -94,6 +94,13 @@ void TimeTicker::HandleTimer(void) Get().HandleTimeTick(); } +#if OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE && OPENTHREAD_CONFIG_BORDER_ROUTER_REQUEST_ROUTER_ROLE + if (mReceivers & Mask(kNetworkDataNotifier)) + { + Get().HandleTimeTick(); + } +#endif + #if OPENTHREAD_CONFIG_CHILD_SUPERVISION_ENABLE if (mReceivers & Mask(kChildSupervisor)) { diff --git a/util/third_party/openthread/src/core/common/time_ticker.hpp b/util/third_party/openthread/src/core/common/time_ticker.hpp index 78860c4d63..a89f3e36e2 100644 --- a/util/third_party/openthread/src/core/common/time_ticker.hpp +++ b/util/third_party/openthread/src/core/common/time_ticker.hpp @@ -71,6 +71,7 @@ class TimeTicker : public InstanceLocator, private NonCopyable kIp6FragmentReassembler, ///< `Ip6::Ip6` (handling of fragmented messages) kDuaManager, ///< `DuaManager` kMlrManager, ///< `MlrManager` + kNetworkDataNotifier, ///< `NetworkData::Notifier` kNumReceivers, ///< Number of receivers. }; diff --git a/util/third_party/openthread/src/core/config/border_router.h b/util/third_party/openthread/src/core/config/border_router.h index f3959d50d5..b917a02846 100644 --- a/util/third_party/openthread/src/core/config/border_router.h +++ b/util/third_party/openthread/src/core/config/border_router.h @@ -55,6 +55,32 @@ #define OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE 0 #endif +/** + * @def OPENTHREAD_CONFIG_BORDER_ROUTER_REQUEST_ROUTER_ROLE + * + * Define to 1 to enable mechanism on a Border Router which provides IP connectivity to request router role upgrade. + * + * This config is applicable on an `OPENTHREAD_FTD` build and when `OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE` is also + * enabled. + * + * A Border Router is considered to provide external IP connectivity if at least one of the below conditions hold: + * + * - It has added at least one external route entry. + * - It has added at least one prefix entry with default-route and on-mesh flags set. + * - It has added at least one domain prefix (domain and on-mesh flags set). + * + * A Border Router which provides IP connectivity and is acting as a REED is eligible to request a router role upgrade + * by sending an "Address Solicit" request to leader with status reason `BorderRouterRequest`. This reason is used when + * the number of active routers in the Thread mesh is above the threshold, and only if the number of existing eligible + * BRs (determined from the Thread Network Data) that are acting as router is less than two. This mechanism allows up + * to two eligible Border Routers to request router role upgrade when the number of routers is already above the + * threshold. + * + */ +#ifndef OPENTHREAD_CONFIG_BORDER_ROUTER_REQUEST_ROUTER_ROLE +#define OPENTHREAD_CONFIG_BORDER_ROUTER_REQUEST_ROUTER_ROLE 1 +#endif + /** * @def OPENTHREAD_CONFIG_BORDER_ROUTING_ENABLE * @@ -65,6 +91,16 @@ #define OPENTHREAD_CONFIG_BORDER_ROUTING_ENABLE 0 #endif +/** + * @def OPENTHREAD_CONFIG_BORDER_ROUTING_MAX_DISCOVERED_ROUTERS + * + * Specifies maximum number of routers (on infra link) to track by routing manager. + * + */ +#ifndef OPENTHREAD_CONFIG_BORDER_ROUTING_MAX_DISCOVERED_ROUTERS +#define OPENTHREAD_CONFIG_BORDER_ROUTING_MAX_DISCOVERED_ROUTERS 16 +#endif + /** * @def OPENTHREAD_CONFIG_BORDER_ROUTING_MAX_DISCOVERED_PREFIXES * @@ -72,7 +108,7 @@ * */ #ifndef OPENTHREAD_CONFIG_BORDER_ROUTING_MAX_DISCOVERED_PREFIXES -#define OPENTHREAD_CONFIG_BORDER_ROUTING_MAX_DISCOVERED_PREFIXES 8 +#define OPENTHREAD_CONFIG_BORDER_ROUTING_MAX_DISCOVERED_PREFIXES 64 #endif /** diff --git a/util/third_party/openthread/src/core/config/misc.h b/util/third_party/openthread/src/core/config/misc.h index 3508cf5a24..07186e9d7e 100644 --- a/util/third_party/openthread/src/core/config/misc.h +++ b/util/third_party/openthread/src/core/config/misc.h @@ -431,6 +431,68 @@ #define OPENTHREAD_CONFIG_NUM_FRAGMENT_PRIORITY_ENTRIES 8 #endif +/** + * @def OPENTHREAD_CONFIG_DELAY_AWARE_QUEUE_MANAGEMENT_ENABLE + * + * Define to 1 to enable delay-aware queue management for the send queue. + * + * When enabled device will monitor time-in-queue of messages in the direct tx queue and if the wait time is lager than + * specified thresholds it may update ECN flag (if message indicates it is ECN-capable) or drop the message. + * + */ +#ifndef OPENTHREAD_CONFIG_DELAY_AWARE_QUEUE_MANAGEMENT_ENABLE +#define OPENTHREAD_CONFIG_DELAY_AWARE_QUEUE_MANAGEMENT_ENABLE \ + (OPENTHREAD_CONFIG_THREAD_VERSION >= OT_THREAD_VERSION_1_3) +#endif + +/** + * @OPENTHREAD_CONFIG_DELAY_AWARE_QUEUE_MANAGEMENT_MARK_ECN_INTERVAL + * + * Specifies the time-in-queue threshold interval in milliseconds to mark ECN on a message if it is ECN-capable or + * drop the message if not ECN-capable. + * + */ +#ifndef OPENTHREAD_CONFIG_DELAY_AWARE_QUEUE_MANAGEMENT_MARK_ECN_INTERVAL +#define OPENTHREAD_CONFIG_DELAY_AWARE_QUEUE_MANAGEMENT_MARK_ECN_INTERVAL 500 +#endif + +/** + * @OPENTHREAD_CONFIG_DELAY_AWARE_QUEUE_MANAGEMENT_DROP_MSG_INTERVAL + * + * Specifies the time-in-queue threshold interval in milliseconds to drop a message. + * + */ +#ifndef OPENTHREAD_CONFIG_DELAY_AWARE_QUEUE_MANAGEMENT_DROP_MSG_INTERVAL +#define OPENTHREAD_CONFIG_DELAY_AWARE_QUEUE_MANAGEMENT_DROP_MSG_INTERVAL 1000 +#endif + +/** + * OPENTHREAD_CONFIG_DELAY_AWARE_QUEUE_MANAGEMENT_FRAG_TAG_RETAIN_TIME + * + * Specifies the max retain time in seconds of a mesh header fragmentation tag entry in the list. + * + * The entry in list is used to track whether an earlier fragment of same message was dropped by the router and if so + * the next fragments are also dropped. The entry is removed once last fragment is processed or after the retain time + * specified by this config parameter expires. + * + */ +#ifndef OPENTHREAD_CONFIG_DELAY_AWARE_QUEUE_MANAGEMENT_FRAG_TAG_RETAIN_TIME +#define OPENTHREAD_CONFIG_DELAY_AWARE_QUEUE_MANAGEMENT_FRAG_TAG_RETAIN_TIME (4 * 60) // 4 minutes +#endif + +/** + * OPENTHREAD_CONFIG_DELAY_AWARE_QUEUE_MANAGEMENT_FRAG_TAG_ENTRY_LIST_SIZE + * + * Specifies the number of mesh header fragmentation tag entries in the list for delay-aware queue management. + * + * The list is used to track whether an earlier fragment of same message was dropped by the router and if so the next + * fragments are also dropped. + * + */ +#ifndef OPENTHREAD_CONFIG_DELAY_AWARE_QUEUE_MANAGEMENT_FRAG_TAG_ENTRY_LIST_SIZE +#define OPENTHREAD_CONFIG_DELAY_AWARE_QUEUE_MANAGEMENT_FRAG_TAG_ENTRY_LIST_SIZE 16 +#endif + /** * @def OPENTHREAD_CONFIG_PLATFORM_RADIO_PROPRIETARY_SUPPORT * diff --git a/util/third_party/openthread/src/core/coprocessor/rpc.cpp b/util/third_party/openthread/src/core/coprocessor/rpc.cpp index fda11a85e7..8d4d79a776 100644 --- a/util/third_party/openthread/src/core/coprocessor/rpc.cpp +++ b/util/third_party/openthread/src/core/coprocessor/rpc.cpp @@ -86,6 +86,9 @@ using ot::Encoding::BigEndian::HostSwap16; const RPC::Command RPC::sCommands[] = { {"help-crpc", otCRPCProcessHelp}, }; + +char RPC::mStaticOutputBuffer[RPC::kMaxStaticOutputBufferSize]; + #else RPC::Arg RPC::mCachedCommands[RPC::kMaxCommands]; @@ -145,15 +148,16 @@ void RPC::Initialize(Instance &aInstance) void RPC::ProcessLine(const char *aString, char *aOutput, size_t aOutputMaxLen) { Error error = kErrorNone; - char buffer[kMaxCommandBuffer]; + char temp_command_buffer[kMaxCommandLineBufferSize]; char * args[kMaxArgs]; uint8_t argCount = 0; - VerifyOrExit(StringLength(aString, kMaxCommandBuffer) < kMaxCommandBuffer, error = kErrorNoBufs); + VerifyOrExit(StringLength(aString, kMaxCommandLineBufferSize) < kMaxCommandLineBufferSize, error = kErrorNoBufs); - strcpy(buffer, aString); + strcpy(temp_command_buffer, aString); argCount = kMaxArgs; - error = ParseCmd(buffer, argCount, args); + // Parse the argCount and arguments + error = ParseCmd(temp_command_buffer, argCount, args); exit: @@ -327,6 +331,14 @@ int RPC::OutputFormatV(const char *aFormat, va_list aArguments) if (rval > 0) { mOutputBufferCount += static_cast(rval); + + // NOTE: vsnprintf returns "the number of bytes that would have been written if the buffer had enough space" + // It does NOT return the actual number of bytes written. + // + // Because of this, we need to set mOutputBufferCount to a maximum value of mOutputBufferMaxLen + if (mOutputBufferCount > mOutputBufferMaxLen) { + mOutputBufferCount = mOutputBufferMaxLen; + } } exit: return rval; diff --git a/util/third_party/openthread/src/core/coprocessor/rpc.hpp b/util/third_party/openthread/src/core/coprocessor/rpc.hpp index 3b1f595176..77c36115cb 100644 --- a/util/third_party/openthread/src/core/coprocessor/rpc.hpp +++ b/util/third_party/openthread/src/core/coprocessor/rpc.hpp @@ -288,13 +288,24 @@ class RPC : public InstanceLocator, private NonCopyable void ProcessHelp(void *aContext, uint8_t aArgsLength, char *aArgs[]); + char * GetStaticOutputBuffer(void) + { + return mStaticOutputBuffer; + } + + size_t GetStaticOutputBufferSize(void) + { + return sizeof(mStaticOutputBuffer); + } + #endif enum { - kMaxCommands = OPENTHREAD_CONFIG_COPROCESSOR_RPC_COMMANDS_MAX, - kMaxArgs = OPENTHREAD_CONFIG_COPROCESSOR_RPC_CMD_LINE_ARGS_MAX, - kMaxCommandBuffer = OPENTHREAD_CONFIG_COPROCESSOR_RPC_OUTPUT_BUFFER_SIZE, - kCommandCacheBufferLength = OPENTHREAD_CONFIG_COPROCESSOR_RPC_COMMAND_CACHE_BUFFER_SIZE, + kMaxCommands = OPENTHREAD_CONFIG_COPROCESSOR_RPC_COMMANDS_MAX, + kMaxCommandLineBufferSize = OPENTHREAD_CONFIG_COPROCESSOR_RPC_CMD_LINE_BUFFER_SIZE, + kMaxArgs = OPENTHREAD_CONFIG_COPROCESSOR_RPC_CMD_LINE_ARGS_MAX, + kMaxStaticOutputBufferSize = OPENTHREAD_CONFIG_COPROCESSOR_RPC_OUTPUT_BUFFER_SIZE, + kCommandCacheBufferLength = OPENTHREAD_CONFIG_COPROCESSOR_RPC_COMMAND_CACHE_BUFFER_SIZE, }; protected: @@ -327,6 +338,7 @@ class RPC : public InstanceLocator, private NonCopyable void * mUserCommandsContext; otError mUserCommandsError; uint8_t mUserCommandsLength; + static char mStaticOutputBuffer[kMaxStaticOutputBufferSize]; #else static Arg mCachedCommands[kMaxCommands]; static char mCachedCommandsBuffer[kCommandCacheBufferLength]; diff --git a/util/third_party/openthread/src/core/diags/factory_diags.cpp b/util/third_party/openthread/src/core/diags/factory_diags.cpp index 6410421f76..d0abf6d0f2 100644 --- a/util/third_party/openthread/src/core/diags/factory_diags.cpp +++ b/util/third_party/openthread/src/core/diags/factory_diags.cpp @@ -71,7 +71,7 @@ namespace FactoryDiags { const struct Diags::Command Diags::sCommands[] = { {"channel", &Diags::ProcessChannel}, {"echo", &Diags::ProcessEcho}, {"power", &Diags::ProcessPower}, - {"start", &Diags::ProcessStart}, {"stop", &Diags::ProcessStop}, + {"start", &Diags::ProcessStart}, {"stop", &Diags::ProcessStop}, {"stream", &Diags::ProcessStream}, }; Diags::Diags(Instance &aInstance) @@ -79,6 +79,44 @@ Diags::Diags(Instance &aInstance) { } +Error Diags::ProcessStream(uint8_t aArgsLength, char *aArgs[], char *aOutput, size_t aOutputMaxLen) +{ + Error error = kErrorNone; + + VerifyOrExit(aArgsLength > 0, error = kErrorInvalidArgs); + + if (strcmp(aArgs[0], "stop") == 0) + { + otPlatDiagTxStreamStop(); + } + else if (strcmp(aArgs[0], "tone") == 0) + { + otPlatDiagTxStreamTone(); + } + else if (strcmp(aArgs[0], "random") == 0) + { + otPlatDiagTxStreamRandom(); + } + else if (strcmp(aArgs[0], "addrMatch") == 0) + { + long value; + SuccessOrExit(ParseLong(aArgs[1], value)); + + otPlatDiagTxStreamAddrMatch(static_cast(value)); + } + else if (strcmp(aArgs[0], "autoAck") == 0) + { + long value; + SuccessOrExit(ParseLong(aArgs[1], value)); + + otPlatDiagTxStreamAutoAck(static_cast(value)); + } + +exit: + AppendErrorResult(error, aOutput, aOutputMaxLen); + return error; +} + Error Diags::ProcessChannel(uint8_t aArgsLength, char *aArgs[], char *aOutput, size_t aOutputMaxLen) { Error error = kErrorNone; @@ -183,7 +221,7 @@ extern "C" void otPlatDiagAlarmFired(otInstance *aInstance) const struct Diags::Command Diags::sCommands[] = { {"channel", &Diags::ProcessChannel}, {"power", &Diags::ProcessPower}, {"radio", &Diags::ProcessRadio}, {"repeat", &Diags::ProcessRepeat}, {"send", &Diags::ProcessSend}, {"start", &Diags::ProcessStart}, - {"stats", &Diags::ProcessStats}, {"stop", &Diags::ProcessStop}, + {"stats", &Diags::ProcessStats}, {"stop", &Diags::ProcessStop}, {"stream", &Diags::ProcessStream}, }; Diags::Diags(Instance &aInstance) @@ -200,6 +238,52 @@ Diags::Diags(Instance &aInstance) mStats.Clear(); } + +Error Diags::ProcessStream(uint8_t aArgsLength, char *aArgs[], char *aOutput, size_t aOutputMaxLen) +{ + Error error = kErrorNone; + + VerifyOrExit(otPlatDiagModeGet(), error = kErrorInvalidState); + VerifyOrExit(aArgsLength > 0, error = kErrorInvalidArgs); + + SuccessOrExit(error = Get().Sleep()); + + if (strcmp(aArgs[0], "stop") == 0) + { + SuccessOrExit(error = Get().TxStreamStop()); + snprintf(aOutput, aOutputMaxLen, "stop stream transmission\r\nstatus 0x%02x\r\n", error); + } + else if (strcmp(aArgs[0], "tone") == 0) + { + SuccessOrExit(error = Get().TxStreamTone()); + snprintf(aOutput, aOutputMaxLen, "start transmitting unmodulated tone\r\nstatus 0x%02x\r\n", error); + } + else if (strcmp(aArgs[0], "random") == 0) + { + SuccessOrExit(error = Get().TxStreamRandom()); + snprintf(aOutput, aOutputMaxLen, "start transmitting random characters stream\r\nstatus 0x%02x\r\n", error); + } + else if (strcmp(aArgs[0], "addrMatch") == 0) + { + long value; + SuccessOrExit(ParseLong(aArgs[1], value)); + SuccessOrExit(error = Get().TxStreamAddrMatch(static_cast(value))); + snprintf(aOutput, aOutputMaxLen, "Toggle stream AddrMatch\r\nstatus 0x%02x\r\n", error); + } + else if (strcmp(aArgs[0], "autoAck") == 0) + { + long value; + SuccessOrExit(ParseLong(aArgs[1], value)); + SuccessOrExit(error = Get().TxStreamAutoAck(static_cast(value))); + snprintf(aOutput, aOutputMaxLen, "Toggle stream AutoAck\r\nstatus 0x%02x\r\n", error); + } + +exit: + AppendErrorResult(error, aOutput, aOutputMaxLen); + return error; +} + + Error Diags::ProcessChannel(uint8_t aArgsLength, char *aArgs[], char *aOutput, size_t aOutputMaxLen) { Error error = kErrorNone; diff --git a/util/third_party/openthread/src/core/diags/factory_diags.hpp b/util/third_party/openthread/src/core/diags/factory_diags.hpp index 26ccd9e838..78e2ba1a9d 100644 --- a/util/third_party/openthread/src/core/diags/factory_diags.hpp +++ b/util/third_party/openthread/src/core/diags/factory_diags.hpp @@ -154,6 +154,7 @@ class Diags : public InstanceLocator, private NonCopyable #if OPENTHREAD_RADIO && !OPENTHREAD_RADIO_CLI Error ProcessEcho(uint8_t aArgsLength, char *aArgs[], char *aOutput, size_t aOutputMaxLen); #endif + Error ProcessStream(uint8_t aArgsLength, char *aArgs[], char *aOutput, size_t aOutputMaxLen); void TransmitPacket(void); diff --git a/util/third_party/openthread/src/core/mac/mac.cpp b/util/third_party/openthread/src/core/mac/mac.cpp index 6c99c573ce..dbe3c974a2 100644 --- a/util/third_party/openthread/src/core/mac/mac.cpp +++ b/util/third_party/openthread/src/core/mac/mac.cpp @@ -92,6 +92,10 @@ Mac::Mac(Instance &aInstance) #if OPENTHREAD_CONFIG_MAC_CSL_TRANSMITTER_ENABLE , mCslTxFireTime(TimeMilli::kMaxDuration) #endif +#if OPENTHREAD_CONFIG_MAC_CSL_RECEIVER_ENABLE + , mCslChannel(0) + , mCslPeriod(0) +#endif #endif , mActiveScanHandler(nullptr) // Initialize `mActiveScanHandler` and `mEnergyScanHandler` union , mScanHandlerContext(nullptr) @@ -413,6 +417,10 @@ Error Mac::SetPanChannel(uint8_t aChannel) mRadioChannel = mPanChannel; +#if OPENTHREAD_CONFIG_MAC_CSL_RECEIVER_ENABLE + UpdateCsl(); +#endif + UpdateIdleMode(); exit: @@ -553,7 +561,7 @@ void Mac::UpdateIdleMode(void) #if OPENTHREAD_CONFIG_MAC_CSL_RECEIVER_ENABLE if (IsCslEnabled()) { - mLinks.CslSample(mRadioChannel); + mLinks.CslSample(); ExitNow(); } #endif @@ -2257,52 +2265,57 @@ uint8_t Mac::GetTimeIeOffset(const Frame &aFrame) #endif #if OPENTHREAD_CONFIG_MAC_CSL_RECEIVER_ENABLE -void Mac::SetCslChannel(uint8_t aChannel) +void Mac::UpdateCsl(void) { - VerifyOrExit(GetCslChannel() != aChannel); + uint16_t period; + uint8_t channel; + + VerifyOrExit(IsCslSupported()); - mLinks.GetSubMac().SetCslChannel(aChannel); - mLinks.GetSubMac().SetCslChannelSpecified(aChannel != 0); + period = Get().IsRxOnWhenIdle() ? 0 : GetCslPeriod(); + channel = GetCslChannel() ? GetCslChannel() : mRadioChannel; - if (IsCslEnabled()) + if (mLinks.UpdateCsl(period, channel, Get().GetParent().GetRloc16(), + &Get().GetParent().GetExtAddress())) { - Get().ScheduleChildUpdateRequest(); + Get().RecalculatePollPeriod(); + if (period) + { + Get().ScheduleChildUpdateRequest(); + } + UpdateIdleMode(); } + exit: return; } -void Mac::SetCslPeriod(uint16_t aPeriod) +void Mac::SetCslChannel(uint8_t aChannel) { - mLinks.GetSubMac().SetCslPeriod(aPeriod); - - Get().RecalculatePollPeriod(); - - if ((GetCslPeriod() == 0) || IsCslEnabled()) - { - IgnoreError(Get().EnableCsl(GetCslPeriod(), Get().GetParent().GetRloc16(), - &Get().GetParent().GetExtAddress())); - } - - if (IsCslEnabled()) - { - Get().ScheduleChildUpdateRequest(); - } + mCslChannel = aChannel; + UpdateCsl(); +} - UpdateIdleMode(); +void Mac::SetCslPeriod(uint16_t aPeriod) +{ + mCslPeriod = aPeriod; + UpdateCsl(); } bool Mac::IsCslEnabled(void) const { - return !GetRxOnWhenIdle() && IsCslCapable(); + return !Get().IsRxOnWhenIdle() && IsCslCapable(); } bool Mac::IsCslCapable(void) const { - return (GetCslPeriod() > 0) && Get().IsChild() && - Get().GetParent().IsEnhancedKeepAliveSupported(); + return (GetCslPeriod() > 0) && IsCslSupported(); } +bool Mac::IsCslSupported(void) const +{ + return Get().IsChild() && Get().GetParent().IsEnhancedKeepAliveSupported(); +} #endif // OPENTHREAD_CONFIG_MAC_CSL_RECEIVER_ENABLE #if OPENTHREAD_FTD && OPENTHREAD_CONFIG_MAC_CSL_TRANSMITTER_ENABLE diff --git a/util/third_party/openthread/src/core/mac/mac.hpp b/util/third_party/openthread/src/core/mac/mac.hpp index 940a458bca..babdbbf351 100644 --- a/util/third_party/openthread/src/core/mac/mac.hpp +++ b/util/third_party/openthread/src/core/mac/mac.hpp @@ -583,7 +583,7 @@ class Mac : public InstanceLocator, private NonCopyable * @returns CSL channel. * */ - uint8_t GetCslChannel(void) const { return mLinks.GetSubMac().GetCslChannel(); } + uint8_t GetCslChannel(void) const { return mCslChannel; } /** * This method sets the CSL channel. @@ -594,12 +594,10 @@ class Mac : public InstanceLocator, private NonCopyable void SetCslChannel(uint8_t aChannel); /** - * This method indicates if CSL channel has been explicitly specified by the upper layer. - * - * @returns If CSL channel has been specified. + * This method centralizes CSL state switching conditions evaluating, configuring SubMac accordingly. * */ - bool IsCslChannelSpecified(void) const { return mLinks.GetSubMac().IsCslChannelSpecified(); } + void UpdateCsl(void); /** * This method gets the CSL period. @@ -607,7 +605,7 @@ class Mac : public InstanceLocator, private NonCopyable * @returns CSL period in units of 10 symbols. * */ - uint16_t GetCslPeriod(void) const { return mLinks.GetSubMac().GetCslPeriod(); } + uint16_t GetCslPeriod(void) const { return mCslPeriod; } /** * This method sets the CSL period. @@ -635,6 +633,15 @@ class Mac : public InstanceLocator, private NonCopyable */ bool IsCslCapable(void) const; + /** + * This method indicates whether the device is connected to a parent which supports CSL. + * + * @retval TRUE If parent supports CSL. + * @retval FALSE If parent does not support CSL. + * + */ + bool IsCslSupported(void) const; + /** * This method returns CSL parent clock accuracy, in ± ppm. * @@ -820,6 +827,11 @@ class Mac : public InstanceLocator, private NonCopyable #if OPENTHREAD_CONFIG_MAC_CSL_TRANSMITTER_ENABLE TimeMilli mCslTxFireTime; #endif +#endif +#if OPENTHREAD_CONFIG_MAC_CSL_RECEIVER_ENABLE + // When Mac::mCslChannel is 0, it indicates that CSL channel has not been specified by the upper layer. + uint8_t mCslChannel; + uint16_t mCslPeriod; #endif union diff --git a/util/third_party/openthread/src/core/mac/mac_links.hpp b/util/third_party/openthread/src/core/mac/mac_links.hpp index 85aa0e54be..99406f7ad8 100644 --- a/util/third_party/openthread/src/core/mac/mac_links.hpp +++ b/util/third_party/openthread/src/core/mac/mac_links.hpp @@ -457,18 +457,42 @@ class Links : public InstanceLocator #if OPENTHREAD_CONFIG_MAC_CSL_RECEIVER_ENABLE /** - * This method transitions all radios link to CSL sample state. + * This method configures CSL parameters in all radios. * - * CSL sample state is only applicable and used for 15.4 radio link. Other link are transitioned to sleep state. + * @param[in] aPeriod The CSL period. + * @param[in] aChannel The CSL channel. + * @param[in] aShortAddr The short source address of CSL receiver's peer. + * @param[in] aExtAddr The extended source address of CSL receiver's peer. + * + * @retval TRUE if CSL Period or CSL Channel changed. + * @retval FALSE if CSL Period and CSL Channel did not change. + * + */ + bool UpdateCsl(uint16_t aPeriod, uint8_t aChannel, otShortAddress aShortAddr, const otExtAddress *aExtAddr) + { + bool retval = false; + + OT_UNUSED_VARIABLE(aPeriod); + OT_UNUSED_VARIABLE(aChannel); + OT_UNUSED_VARIABLE(aShortAddr); + OT_UNUSED_VARIABLE(aExtAddr); +#if OPENTHREAD_CONFIG_RADIO_LINK_IEEE_802_15_4_ENABLE + retval = mSubMac.UpdateCsl(aPeriod, aChannel, aShortAddr, aExtAddr); +#endif + return retval; + } + + /** + * This method transitions all radios link to CSL sample state, given that a non-zero CSL period is configured. + * + * CSL sample state is only applicable and used for 15.4 radio link. Other link are transitioned to sleep state + * when CSL period is non-zero. * - * @param[in] aPanChannel The current phy channel used by the device. This param will only take effect when CSL - * channel hasn't been explicitly specified. */ - void CslSample(uint8_t aPanChannel) + void CslSample(void) { - OT_UNUSED_VARIABLE(aPanChannel); #if OPENTHREAD_CONFIG_RADIO_LINK_IEEE_802_15_4_ENABLE - IgnoreError(mSubMac.CslSample(aPanChannel)); + mSubMac.CslSample(); #endif #if OPENTHREAD_CONFIG_RADIO_LINK_TREL_ENABLE mTrel.Sleep(); diff --git a/util/third_party/openthread/src/core/mac/sub_mac.cpp b/util/third_party/openthread/src/core/mac/sub_mac.cpp index eb7c064db7..01243de7a9 100644 --- a/util/third_party/openthread/src/core/mac/sub_mac.cpp +++ b/util/third_party/openthread/src/core/mac/sub_mac.cpp @@ -95,12 +95,11 @@ void SubMac::Init(void) mTimer.Stop(); #if OPENTHREAD_CONFIG_MAC_CSL_RECEIVER_ENABLE - mCslPeriod = 0; - mCslChannel = 0; - mIsCslChannelSpecified = false; - mCslSampleTime = TimeMicro{0}; - mCslLastSync = TimeMicro{0}; - mCslState = kCslIdle; + mCslPeriod = 0; + mCslChannel = 0; + mIsCslSampling = false; + mCslSampleTime = TimeMicro{0}; + mCslLastSync = TimeMicro{0}; mCslTimer.Stop(); #endif } @@ -201,6 +200,10 @@ Error SubMac::Disable(void) { Error error; +#if OPENTHREAD_CONFIG_MAC_CSL_RECEIVER_ENABLE + mCslTimer.Stop(); +#endif + mTimer.Stop(); SuccessOrExit(error = Get().Sleep()); SuccessOrExit(error = Get().Disable()); @@ -254,43 +257,26 @@ Error SubMac::Receive(uint8_t aChannel) } #if OPENTHREAD_CONFIG_MAC_CSL_RECEIVER_ENABLE -Error SubMac::CslSample(uint8_t aPanChannel) +void SubMac::CslSample(void) { - Error error = kErrorNone; - - if (!IsCslChannelSpecified()) - { - mCslChannel = aPanChannel; - } - #if OPENTHREAD_CONFIG_MAC_FILTER_ENABLE - VerifyOrExit(!mRadioFilterEnabled, error = Get().Sleep()); + VerifyOrExit(!mRadioFilterEnabled, IgnoreError(Get().Sleep())); #endif - switch (mCslState) + SetState(kStateCslSample); + + if (mIsCslSampling && !RadioSupportsReceiveTiming()) { - case kCslSample: - error = Get().Receive(mCslChannel); - break; - case kCslSleep: -#if !OPENTHREAD_CONFIG_MAC_CSL_DEBUG_ENABLE - error = Get().Sleep(); // Don't actually sleep for debugging -#endif - break; - case kCslIdle: - ExitNow(error = kErrorInvalidState); - default: - OT_ASSERT(false); + IgnoreError(Get().Receive(mCslChannel)); + ExitNow(); } - SetState(kStateCslSample); +#if !OPENTHREAD_CONFIG_MAC_CSL_DEBUG_ENABLE + IgnoreError(Get().Sleep()); // Don't actually sleep for debugging +#endif exit: - if (error != kErrorNone) - { - LogWarn("CslSample() failed, error: %s", ErrorToString(error)); - } - return error; + return; } #endif // OPENTHREAD_CONFIG_MAC_CSL_RECEIVER_ENABLE @@ -318,7 +304,7 @@ void SubMac::HandleReceiveDone(RxFrame *aFrame, Error aError) #if OPENTHREAD_CONFIG_MAC_CSL_DEBUG_ENABLE // Split the log into two lines for RTT to output LogDebg("Received frame in state (SubMac %s, CSL %s), timestamp %u", StateToString(mState), - CslStateToString(mCslState), static_cast(aFrame->mInfo.mRxInfo.mTimestamp)); + mIsCslSampling ? "CslSample" : "CslSleep", static_cast(aFrame->mInfo.mRxInfo.mTimestamp)); LogDebg("Target sample start time %u, time drift %d", mCslSampleTime.GetValue(), static_cast(aFrame->mInfo.mRxInfo.mTimestamp) - mCslSampleTime.GetValue()); #endif @@ -1055,63 +1041,35 @@ const char *SubMac::StateToString(State aState) return kStateStrings[aState]; } -#if OPENTHREAD_CONFIG_MAC_CSL_RECEIVER_ENABLE -const char *SubMac::CslStateToString(CslState aCslState) -{ - static const char *const kCslStateStrings[] = { - "CslIdle", // (0) kCslIdle - "CslSample", // (1) kCslSample - "CslSleep", // (2) kCslSleep - }; - - static_assert(kCslIdle == 0, "kCslIdle value is incorrect"); - static_assert(kCslSample == 1, "kCslSample value is incorrect"); - static_assert(kCslSleep == 2, "kCslSleep value is incorrect"); - - return kCslStateStrings[aCslState]; -} -#endif - // LCOV_EXCL_STOP //--------------------------------------------------------------------------------------------------------------------- // CSL Receiver methods #if OPENTHREAD_CONFIG_MAC_CSL_RECEIVER_ENABLE -void SubMac::SetCslChannel(uint8_t aChannel) +bool SubMac::UpdateCsl(uint16_t aPeriod, uint8_t aChannel, otShortAddress aShortAddr, const otExtAddress *aExtAddr) { - mCslChannel = aChannel; -} + bool diffPeriod = aPeriod != mCslPeriod; + bool diffChannel = aChannel != mCslChannel; + bool retval = diffPeriod || diffChannel; -void SubMac::SetCslPeriod(uint16_t aPeriod) -{ - VerifyOrExit(mCslPeriod != aPeriod); + VerifyOrExit(retval); + mCslChannel = aChannel; + VerifyOrExit(diffPeriod); mCslPeriod = aPeriod; + IgnoreError(Get().EnableCsl(aPeriod, aShortAddr, aExtAddr)); mCslTimer.Stop(); - if (mCslPeriod > 0) { mCslSampleTime = TimeMicro(static_cast(otPlatRadioGetNow(&GetInstance()))); - mCslState = kCslSleep; + mIsCslSampling = false; HandleCslTimer(); } - else - { - mCslState = kCslIdle; - - if (mState == kStateCslSample) - { - IgnoreError(Get().Sleep()); - SetState(kStateSleep); - } - } - - LogDebg("CSL Period: %u", mCslPeriod); exit: - return; + return retval; } void SubMac::HandleCslTimer(Timer &aTimer) @@ -1135,11 +1093,9 @@ void SubMac::HandleCslTimer(void) GetCslWindowEdges(timeAhead, timeAfter); - switch (mCslState) + if (mIsCslSampling) { - case kCslSample: - mCslState = kCslSleep; - + mIsCslSampling = false; mCslTimer.FireAt(mCslSampleTime - timeAhead); if (mState == kStateCslSample) { @@ -1148,9 +1104,9 @@ void SubMac::HandleCslTimer(void) #endif LogDebg("CSL sleep %u", mCslTimer.GetNow().GetValue()); } - break; - - case kCslSleep: + } + else + { if (RadioSupportsReceiveTiming()) { mCslSampleTime += periodUs; @@ -1160,33 +1116,22 @@ void SubMac::HandleCslTimer(void) else { mCslTimer.FireAt(mCslSampleTime + timeAfter); - mCslState = kCslSample; + mIsCslSampling = true; mCslSampleTime += periodUs; } Get().UpdateCslSampleTime(mCslSampleTime.GetValue()); - if (RadioSupportsReceiveTiming()) + if (RadioSupportsReceiveTiming() && (mState != kStateDisabled)) { - if (mState != kStateDisabled && mCslChannel) - { - IgnoreError(Get().ReceiveAt(mCslChannel, mCslSampleTime.GetValue() - periodUs - timeAhead, - timeAhead + timeAfter)); - } + IgnoreError(Get().ReceiveAt(mCslChannel, mCslSampleTime.GetValue() - periodUs - timeAhead, + timeAhead + timeAfter)); } else if (mState == kStateCslSample) { IgnoreError(Get().Receive(mCslChannel)); LogDebg("CSL sample %u, duration %u", mCslTimer.GetNow().GetValue(), timeAhead + timeAfter); } - break; - - case kCslIdle: - break; - - default: - OT_ASSERT(false); - break; } } diff --git a/util/third_party/openthread/src/core/mac/sub_mac.hpp b/util/third_party/openthread/src/core/mac/sub_mac.hpp index 0a59857543..f7d5e5e1a0 100644 --- a/util/third_party/openthread/src/core/mac/sub_mac.hpp +++ b/util/third_party/openthread/src/core/mac/sub_mac.hpp @@ -398,69 +398,27 @@ class SubMac : public InstanceLocator, private NonCopyable int8_t GetNoiseFloor(void); #if OPENTHREAD_CONFIG_MAC_CSL_RECEIVER_ENABLE - - /** - * This method lets `SubMac` start CSL sample. - * - * `SubMac` would switch the radio state between `Receive` and `Sleep` according the CSL timer. When CslSample is - * started, `mState` will become `kStateCslSample`. But it could be doing `Sleep` or `Receive` at this moment - * (depending on `mCslState`). - * - * @param[in] aPanChannel The current phy channel used by the device. This param will only take effect when CSL - * channel hasn't been explicitly specified. - * - * @retval kErrorNone Successfully entered CSL operation (sleep or receive according to CSL timer). - * @retval kErrorBusy The radio was transmitting. - * @retval kErrorInvalidState The radio was disabled. - * - */ - Error CslSample(uint8_t aPanChannel); - - /** - * This method gets the CSL channel. - * - * @returns CSL channel. - * - */ - uint8_t GetCslChannel(void) const { return mCslChannel; } - - /** - * This method sets the CSL channel. - * - * @param[in] aChannel The CSL channel. `0` to set CSL Channel unspecified. - * - */ - void SetCslChannel(uint8_t aChannel); - - /** - * This method indicates if CSL channel has been explicitly specified by the upper layer. - * - * @returns If CSL channel has been specified. - * - */ - bool IsCslChannelSpecified(void) const { return mIsCslChannelSpecified; } - /** - * This method sets the flag representing if CSL channel has been specified. + * This method configures CSL parameters in 'SubMac'. * - */ - void SetCslChannelSpecified(bool aIsSpecified) { mIsCslChannelSpecified = aIsSpecified; } - - /** - * This method gets the CSL period. + * @param[in] aPeriod The CSL period. + * @param[in] aChannel The CSL channel. + * @param[in] aShortAddr The short source address of CSL receiver's peer. + * @param[in] aExtAddr The extended source address of CSL receiver's peer. * - * @returns CSL period. + * @retval TRUE if CSL Period or CSL Channel changed. + * @retval FALSE if CSL Period and CSL Channel did not change. * */ - uint16_t GetCslPeriod(void) const { return mCslPeriod; } + bool UpdateCsl(uint16_t aPeriod, uint8_t aChannel, otShortAddress aShortAddr, const otExtAddress *aExtAddr); /** - * This method sets the CSL period. + * This method lets `SubMac` start CSL sample mode given a configured non-zero CSL period. * - * @param[in] aPeriod The CSL period in 10 symbols. + * `SubMac` would switch the radio state between `Receive` and `Sleep` according the CSL timer. * */ - void SetCslPeriod(uint16_t aPeriod); + void CslSample(void); /** * This method returns CSL parent clock accuracy, in ± ppm. @@ -626,12 +584,6 @@ class SubMac : public InstanceLocator, private NonCopyable // CSL receivers would wake up `kCslReceiveTimeAhead` earlier // than expected sample window. The value is in usec. static constexpr uint32_t kCslReceiveTimeAhead = OPENTHREAD_CONFIG_CSL_RECEIVE_TIME_AHEAD; - - enum CslState : uint8_t{ - kCslIdle, // CSL receiver is not started. - kCslSample, // Sampling CSL channel. - kCslSleep, // Radio in sleep. - }; #endif /** @@ -677,9 +629,6 @@ class SubMac : public InstanceLocator, private NonCopyable void SetState(State aState); static const char *StateToString(State aState); -#if OPENTHREAD_CONFIG_MAC_CSL_RECEIVER_ENABLE - static const char *CslStateToString(CslState aCslState); -#endif otRadioCaps mRadioCaps; State mState; @@ -712,14 +661,14 @@ class SubMac : public InstanceLocator, private NonCopyable #endif #if OPENTHREAD_CONFIG_MAC_CSL_RECEIVER_ENABLE - uint16_t mCslPeriod; // The CSL sample period, in units of 10 symbols (160 microseconds). - uint8_t mCslChannel : 7; // The CSL sample channel (only when `mIsCslChannelSpecified` is `true`). - uint8_t mIsCslChannelSpecified : 1; // Whether the CSL channel was explicitly set - TimeMicro mCslSampleTime; // The CSL sample time of the current period. - TimeMicro mCslLastSync; // The timestamp of the last successful CSL synchronization. - uint8_t mCslParentAccuracy; // Drift of timer used for scheduling CSL tx by the parent, in ± ppm. - uint8_t mCslParentUncert; // Uncertainty of the scheduling CSL of tx by the parent, in ±10 us units. - CslState mCslState; + uint16_t mCslPeriod; // The CSL sample period, in units of 10 symbols (160 microseconds). + uint8_t mCslChannel : 7; // The CSL sample channel. + bool mIsCslSampling : 1; // Indicates that the radio is receiving in CSL state for platforms not supporting delayed + // reception. + TimeMicro mCslSampleTime; // The CSL sample time of the current period. + TimeMicro mCslLastSync; // The timestamp of the last successful CSL synchronization. + uint8_t mCslParentAccuracy; // Drift of timer used for scheduling CSL tx by the parent, in ± ppm. + uint8_t mCslParentUncert; // Uncertainty of the scheduling CSL of tx by the parent, in ±10 us units. TimerMicro mCslTimer; #endif }; diff --git a/util/third_party/openthread/src/core/meshcop/dataset.cpp b/util/third_party/openthread/src/core/meshcop/dataset.cpp index 74d9a09190..0478085945 100644 --- a/util/third_party/openthread/src/core/meshcop/dataset.cpp +++ b/util/third_party/openthread/src/core/meshcop/dataset.cpp @@ -43,6 +43,7 @@ #include "common/log.hpp" #include "mac/mac_types.hpp" #include "meshcop/meshcop_tlvs.hpp" +#include "meshcop/timestamp.hpp" #include "thread/mle_tlvs.hpp" namespace ot { @@ -69,10 +70,12 @@ Error Dataset::Info::GenerateRandom(Instance &aInstance) Clear(); - mActiveTimestamp = 1; - mChannel = preferredChannels.ChooseRandomChannel(); - mChannelMask = supportedChannels.GetMask(); - mPanId = Mac::GenerateRandomPanId(); + mActiveTimestamp.mSeconds = 1; + mActiveTimestamp.mTicks = 0; + mActiveTimestamp.mAuthoritative = false; + mChannel = preferredChannels.ChooseRandomChannel(); + mChannelMask = supportedChannels.GetMask(); + mPanId = Mac::GenerateRandomPanId(); AsCoreType(&mSecurityPolicy).SetToDefault(); SuccessOrExit(error = AsCoreType(&mNetworkKey).GenerateRandom()); @@ -193,7 +196,7 @@ void Dataset::ConvertTo(Info &aDatasetInfo) const switch (cur->GetType()) { case Tlv::kActiveTimestamp: - aDatasetInfo.SetActiveTimestamp(As(cur)->GetTimestamp().GetSeconds()); + aDatasetInfo.SetActiveTimestamp(As(cur)->GetTimestamp()); break; case Tlv::kChannel: @@ -237,7 +240,7 @@ void Dataset::ConvertTo(Info &aDatasetInfo) const break; case Tlv::kPendingTimestamp: - aDatasetInfo.SetPendingTimestamp(As(cur)->GetTimestamp().GetSeconds()); + aDatasetInfo.SetPendingTimestamp(As(cur)->GetTimestamp()); break; case Tlv::kPskc: @@ -286,20 +289,18 @@ Error Dataset::SetFrom(const Info &aDatasetInfo) if (aDatasetInfo.IsActiveTimestampPresent()) { - Timestamp timestamp; + Timestamp activeTimestamp; - timestamp.Clear(); - timestamp.SetSeconds(aDatasetInfo.GetActiveTimestamp()); - IgnoreError(SetTlv(Tlv::kActiveTimestamp, timestamp)); + aDatasetInfo.GetActiveTimestamp(activeTimestamp); + IgnoreError(SetTlv(Tlv::kActiveTimestamp, activeTimestamp)); } if (aDatasetInfo.IsPendingTimestampPresent()) { - Timestamp timestamp; + Timestamp pendingTimestamp; - timestamp.Clear(); - timestamp.SetSeconds(aDatasetInfo.GetPendingTimestamp()); - IgnoreError(SetTlv(Tlv::kPendingTimestamp, timestamp)); + aDatasetInfo.GetPendingTimestamp(pendingTimestamp); + IgnoreError(SetTlv(Tlv::kPendingTimestamp, pendingTimestamp)); } if (aDatasetInfo.IsDelayPresent()) diff --git a/util/third_party/openthread/src/core/meshcop/dataset.hpp b/util/third_party/openthread/src/core/meshcop/dataset.hpp index 4e200d6cf7..3809513736 100644 --- a/util/third_party/openthread/src/core/meshcop/dataset.hpp +++ b/util/third_party/openthread/src/core/meshcop/dataset.hpp @@ -203,7 +203,7 @@ class Dataset * @returns The Active Timestamp in the Dataset. * */ - uint64_t GetActiveTimestamp(void) const { return mActiveTimestamp; } + void GetActiveTimestamp(Timestamp &aTimestamp) const { aTimestamp.SetFromTimestamp(mActiveTimestamp); } /** * This method sets the Active Timestamp in the Dataset. @@ -211,9 +211,9 @@ class Dataset * @param[in] aTimestamp A Timestamp value. * */ - void SetActiveTimestamp(uint64_t aTimestamp) + void SetActiveTimestamp(const Timestamp &aTimestamp) { - mActiveTimestamp = aTimestamp; + aTimestamp.ConvertTo(mActiveTimestamp); mComponents.mIsActiveTimestampPresent = true; } @@ -234,7 +234,7 @@ class Dataset * @returns The Pending Timestamp in the Dataset. * */ - uint64_t GetPendingTimestamp(void) const { return mPendingTimestamp; } + void GetPendingTimestamp(Timestamp &aTimestamp) const { aTimestamp.SetFromTimestamp(mPendingTimestamp); } /** * This method sets the Pending Timestamp in the Dataset. @@ -242,9 +242,9 @@ class Dataset * @param[in] aTimestamp A Timestamp value. * */ - void SetPendingTimestamp(uint64_t aTimestamp) + void SetPendingTimestamp(const Timestamp &aTimestamp) { - mPendingTimestamp = aTimestamp; + aTimestamp.ConvertTo(mPendingTimestamp); mComponents.mIsPendingTimestampPresent = true; } diff --git a/util/third_party/openthread/src/core/meshcop/dataset_updater.cpp b/util/third_party/openthread/src/core/meshcop/dataset_updater.cpp index 00782b227e..36d63d7f90 100644 --- a/util/third_party/openthread/src/core/meshcop/dataset_updater.cpp +++ b/util/third_party/openthread/src/core/meshcop/dataset_updater.cpp @@ -41,6 +41,7 @@ #include "common/locator_getters.hpp" #include "common/log.hpp" #include "common/random.hpp" +#include "meshcop/timestamp.hpp" namespace ot { namespace MeshCoP { @@ -193,9 +194,17 @@ void DatasetUpdater::HandleNotifierEvents(Events aEvents) { Finish(kErrorNone); } - else if (requestedDataset.GetActiveTimestamp() <= dataset.GetActiveTimestamp()) + else { - Finish(kErrorAlready); + Timestamp requestedDatasetTimestamp; + Timestamp activeDatasetTimestamp; + + requestedDataset.GetActiveTimestamp(requestedDatasetTimestamp); + dataset.GetActiveTimestamp(activeDatasetTimestamp); + if (Timestamp::Compare(requestedDatasetTimestamp, activeDatasetTimestamp) <= 0) + { + Finish(kErrorAlready); + } } } diff --git a/util/third_party/openthread/src/core/meshcop/timestamp.cpp b/util/third_party/openthread/src/core/meshcop/timestamp.cpp index 5d8f59bf68..08ed36b94c 100644 --- a/util/third_party/openthread/src/core/meshcop/timestamp.cpp +++ b/util/third_party/openthread/src/core/meshcop/timestamp.cpp @@ -38,13 +38,23 @@ namespace ot { namespace MeshCoP { +void Timestamp::ConvertTo(otTimestamp &aTimestamp) const +{ + aTimestamp.mSeconds = GetSeconds(); + aTimestamp.mTicks = GetTicks(); + aTimestamp.mAuthoritative = GetAuthoritative(); +} + +void Timestamp::SetFromTimestamp(const otTimestamp &aTimestamp) +{ + SetSeconds(aTimestamp.mSeconds); + SetTicks(aTimestamp.mTicks); + SetAuthoritative(aTimestamp.mAuthoritative); +} + int Timestamp::Compare(const Timestamp *aFirst, const Timestamp *aSecond) { - int rval; - uint64_t firstSeconds; - uint64_t secondSeconds; - uint16_t firstTicks; - uint16_t secondTicks; + int rval; if (aFirst == nullptr) { @@ -62,22 +72,46 @@ int Timestamp::Compare(const Timestamp *aFirst, const Timestamp *aSecond) // Both are non-null. - firstSeconds = aFirst->GetSeconds(); - secondSeconds = aSecond->GetSeconds(); + rval = Compare(*aFirst, *aSecond); + +exit: + return rval; +} + +int Timestamp::Compare(const Timestamp &aFirst, const Timestamp &aSecond) +{ + int rval; + uint64_t firstSeconds; + uint64_t secondSeconds; + uint16_t firstTicks; + uint16_t secondTicks; + bool firstAuthoritative; + bool secondAuthoritative; + + firstSeconds = aFirst.GetSeconds(); + secondSeconds = aSecond.GetSeconds(); if (firstSeconds != secondSeconds) { ExitNow(rval = (firstSeconds > secondSeconds) ? 1 : -1); } - firstTicks = aFirst->GetTicks(); - secondTicks = aSecond->GetTicks(); + firstTicks = aFirst.GetTicks(); + secondTicks = aSecond.GetTicks(); if (firstTicks != secondTicks) { ExitNow(rval = (firstTicks > secondTicks) ? 1 : -1); } + firstAuthoritative = aFirst.GetAuthoritative(); + secondAuthoritative = aSecond.GetAuthoritative(); + + if (firstAuthoritative != secondAuthoritative) + { + ExitNow(rval = firstAuthoritative ? 1 : -1); + } + rval = 0; exit: diff --git a/util/third_party/openthread/src/core/meshcop/timestamp.hpp b/util/third_party/openthread/src/core/meshcop/timestamp.hpp index ea3b115830..1eace251d5 100644 --- a/util/third_party/openthread/src/core/meshcop/timestamp.hpp +++ b/util/third_party/openthread/src/core/meshcop/timestamp.hpp @@ -39,6 +39,7 @@ #include +#include #include #include "common/clearable.hpp" @@ -59,6 +60,18 @@ OT_TOOL_PACKED_BEGIN class Timestamp : public Clearable { public: + /** + * This method converts the timestamp to `otTimestamp`. + * + */ + void ConvertTo(otTimestamp &aTimestamp) const; + + /** + * This method sets the timestamp from `otTimestamp`. + * + */ + void SetFromTimestamp(const otTimestamp &aTimestamp); + /** * This method returns the Seconds value. * @@ -127,6 +140,15 @@ class Timestamp : public Clearable */ void AdvanceRandomTicks(void); + /** + * This method indicates whether the timestamp indicates an MLE Orphan Announce message. + * + * @retval TRUE The timestamp indicates an Orphan Announce message. + * @retval FALSE If the timestamp does not indicate an Orphan Announce message. + * + */ + bool IsOrphanTimestamp(void) const { return GetSeconds() == 0 && GetTicks() == 0 && GetAuthoritative(); } + /** * This static method compares two timestamps. * @@ -143,6 +165,19 @@ class Timestamp : public Clearable */ static int Compare(const Timestamp *aFirst, const Timestamp *aSecond); + /** + * This static method compares two timestamps. + * + * @param[in] aFirst A reference to the first timestamp to compare. + * @param[in] aSecond A reference to the second timestamp to compare. + * + * @retval -1 if @p aFirst is less than @p aSecond (`aFirst < aSecond`). + * @retval 0 if @p aFirst is equal to @p aSecond (`aFirst == aSecond`). + * @retval 1 if @p aFirst is greater than @p aSecond (`aFirst > aSecond`). + * + */ + static int Compare(const Timestamp &aFirst, const Timestamp &aSecond); + private: static constexpr uint8_t kTicksOffset = 1; static constexpr uint16_t kTicksMask = 0x7fff << kTicksOffset; diff --git a/util/third_party/openthread/src/core/net/dns_dso.cpp b/util/third_party/openthread/src/core/net/dns_dso.cpp index 27222baf55..a18b459380 100644 --- a/util/third_party/openthread/src/core/net/dns_dso.cpp +++ b/util/third_party/openthread/src/core/net/dns_dso.cpp @@ -1409,20 +1409,7 @@ Error Dso::Connection::PendingRequests::Add(MessageId aMessageId, Tlv::Type aPri void Dso::Connection::PendingRequests::Remove(MessageId aMessageId) { - Entry *entry = mRequests.FindMatching(aMessageId); - Entry *lastEntry; - - VerifyOrExit(entry != nullptr); - - // Remove last entry from the `mRequests` array, if it is not the - // `entry` we want to remove, replace `entry` with `lastEntry. - - lastEntry = mRequests.PopBack(); - VerifyOrExit(lastEntry != entry); - *entry = *lastEntry; - -exit: - return; + mRequests.RemoveMatching(aMessageId); } bool Dso::Connection::PendingRequests::HasAnyTimedOut(TimeMilli aNow) const diff --git a/util/third_party/openthread/src/core/net/ip6.cpp b/util/third_party/openthread/src/core/net/ip6.cpp index b510fb12cf..7fda32910f 100644 --- a/util/third_party/openthread/src/core/net/ip6.cpp +++ b/util/third_party/openthread/src/core/net/ip6.cpp @@ -1495,5 +1495,181 @@ const char *Ip6::EcnToString(Ecn aEcn) // LCOV_EXCL_STOP +//--------------------------------------------------------------------------------------------------------------------- +// Headers + +Error Headers::ParseFrom(const Message &aMessage) +{ + Error error = kErrorParse; + + Clear(); + + SuccessOrExit(mIp6Header.ParseFrom(aMessage)); + + switch (mIp6Header.GetNextHeader()) + { + case kProtoUdp: + SuccessOrExit(aMessage.Read(sizeof(Header), mHeader.mUdp)); + break; + case kProtoTcp: + SuccessOrExit(aMessage.Read(sizeof(Header), mHeader.mTcp)); + break; + case kProtoIcmp6: + SuccessOrExit(aMessage.Read(sizeof(Header), mHeader.mIcmp)); + break; + default: + break; + } + + error = kErrorNone; + +exit: + return error; +} + +Error Headers::DecompressFrom(const Message & aMessage, + uint16_t aOffset, + const Mac::Address &aMacSource, + const Mac::Address &aMacDest) +{ + static constexpr uint16_t kReadLength = Lowpan::FragmentHeader::kSubsequentFragmentHeaderSize + sizeof(Headers); + + uint8_t frameBuffer[kReadLength]; + uint16_t frameLength; + + frameLength = aMessage.ReadBytes(aOffset, frameBuffer, sizeof(frameBuffer)); + + return DecompressFrom(frameBuffer, frameLength, aMacSource, aMacDest, aMessage.GetInstance()); +} + +Error Headers::DecompressFrom(const uint8_t * aFrame, + uint16_t aFrameLength, + const Mac::Address &aMacSource, + const Mac::Address &aMacDest, + Instance & aInstance) +{ + Error error = kErrorNone; + Lowpan::FragmentHeader fragmentHeader; + uint16_t fragmentHeaderLength; + int headerLength; + bool nextHeaderCompressed; + + if (fragmentHeader.ParseFrom(aFrame, aFrameLength, fragmentHeaderLength) == kErrorNone) + { + // Only the first fragment header is followed by a LOWPAN_IPHC header + VerifyOrExit(fragmentHeader.GetDatagramOffset() == 0, error = kErrorNotFound); + aFrame += fragmentHeaderLength; + aFrameLength -= fragmentHeaderLength; + } + + VerifyOrExit(aFrameLength >= 1 && Lowpan::Lowpan::IsLowpanHc(aFrame), error = kErrorNotFound); + headerLength = aInstance.Get().DecompressBaseHeader(mIp6Header, nextHeaderCompressed, aMacSource, + aMacDest, aFrame, aFrameLength); + + VerifyOrExit(headerLength > 0, error = kErrorParse); + + aFrame += headerLength; + aFrameLength -= headerLength; + + switch (mIp6Header.GetNextHeader()) + { + case kProtoUdp: + if (nextHeaderCompressed) + { + headerLength = aInstance.Get().DecompressUdpHeader(mHeader.mUdp, aFrame, aFrameLength); + VerifyOrExit(headerLength >= 0, error = kErrorParse); + } + else + { + VerifyOrExit(aFrameLength >= sizeof(Udp::Header), error = kErrorParse); + mHeader.mUdp = *reinterpret_cast(aFrame); + } + break; + + case kProtoTcp: + VerifyOrExit(aFrameLength >= sizeof(Tcp::Header), error = kErrorParse); + mHeader.mTcp = *reinterpret_cast(aFrame); + break; + + case kProtoIcmp6: + VerifyOrExit(aFrameLength >= sizeof(Icmp::Header), error = kErrorParse); + mHeader.mIcmp = *reinterpret_cast(aFrame); + break; + + default: + break; + } + +exit: + return error; +} + +uint16_t Headers::GetSourcePort(void) const +{ + uint16_t port = 0; + + switch (GetIpProto()) + { + case kProtoUdp: + port = mHeader.mUdp.GetSourcePort(); + break; + + case kProtoTcp: + port = mHeader.mTcp.GetSourcePort(); + break; + + default: + break; + } + + return port; +} + +uint16_t Headers::GetDestinationPort(void) const +{ + uint16_t port = 0; + + switch (GetIpProto()) + { + case kProtoUdp: + port = mHeader.mUdp.GetDestinationPort(); + break; + + case kProtoTcp: + port = mHeader.mTcp.GetDestinationPort(); + break; + + default: + break; + } + + return port; +} + +uint16_t Headers::GetChecksum(void) const +{ + uint16_t checksum = 0; + + switch (GetIpProto()) + { + case kProtoUdp: + checksum = mHeader.mUdp.GetChecksum(); + break; + + case kProtoTcp: + checksum = mHeader.mTcp.GetChecksum(); + break; + + case kProtoIcmp6: + checksum = mHeader.mIcmp.GetChecksum(); + break; + + default: + break; + } + + return checksum; +} + } // namespace Ip6 } // namespace ot diff --git a/util/third_party/openthread/src/core/net/ip6.hpp b/util/third_party/openthread/src/core/net/ip6.hpp index 0855e13270..3fb9678d9e 100644 --- a/util/third_party/openthread/src/core/net/ip6.hpp +++ b/util/third_party/openthread/src/core/net/ip6.hpp @@ -377,6 +377,193 @@ class Ip6 : public InstanceLocator, private NonCopyable #endif }; +/** + * This class represents parsed IPv6 header along with UDP/TCP/ICMP6 headers from a received message/frame. + * + */ +class Headers : private Clearable +{ +public: + /** + * This method parses the IPv6 and UDP/TCP/ICMP6 headers from a given message. + * + * @param[in] aMessage The message to parse the headers from. + * + * @retval kErrorNone The headers are parsed successfully. + * @retval kErrorParse Failed to parse the headers. + * + */ + Error ParseFrom(const Message &aMessage); + + /** + * This method decompresses lowpan frame and parses the IPv6 and UDP/TCP/ICMP6 headers. + * + * @param[in] aMessage The message from which to read the lowpan frame. + * @param[in] aOffset The offset in @p aMessage to start reading the frame. + * @param[in] aMacSource The MAC source address. + * @param[in] aMacDest The MAC destination address. + * + * @retval kErrorNone Successfully decompressed and parsed IPv6 and UDP/TCP/ICMP6 headers. + * @retval kErrorNotFound Lowpan frame is a next fragment and does not contain IPv6 headers. + * @retval kErrorParse Failed to parse the headers. + * + */ + Error DecompressFrom(const Message & aMessage, + uint16_t aOffset, + const Mac::Address &aMacSource, + const Mac::Address &aMacDest); + + /** + * This method decompresses lowpan frame and parses the IPv6 and UDP/TCP/ICMP6 headers. + * + * @param[in] aFrame Buffer containig the lowpan frame. + * @param[in] aFrameLength Number of bytes in @p aFrame. + * @param[in] aMacSource The MAC source address. + * @param[in] aMacDest The MAC destination address. + * @param[in] aInstance The OpenThread instance. + * + * @retval kErrorNone Successfully decompressed and parsed IPv6 and UDP/TCP/ICMP6 headers. + * @retval kErrorNotFound Lowpan frame is a next fragment and does not contain IPv6 headers. + * @retval kErrorParse Failed to parse the headers. + * + */ + Error DecompressFrom(const uint8_t * aFrame, + uint16_t aFrameLength, + const Mac::Address &aMacSource, + const Mac::Address &aMacDest, + Instance & aInstance); + + /** + * This method returns the IPv6 header. + * + * @returns The IPv6 header. + * + */ + const Header &GetIp6Header(void) const { return mIp6Header; } + + /** + * This method returns the IP protocol number from IPv6 Next Header field. + * + * @returns The IP protocol number. + * + */ + uint8_t GetIpProto(void) const { return mIp6Header.GetNextHeader(); } + + /** + * This method returns the 2-bit Explicit Congestion Notification (ECN) from Traffic Class field from IPv6 header. + * + * @returns The ECN value. + * + */ + Ecn GetEcn(void) const { return mIp6Header.GetEcn(); } + + /** + * This method indicates if the protocol number from IPv6 header is UDP. + * + * @retval TRUE If the protocol number in IPv6 header is UDP. + * @retval FALSE If the protocol number in IPv6 header is not UDP. + * + */ + bool IsUdp(void) const { return GetIpProto() == kProtoUdp; } + + /** + * This method indicates if the protocol number from IPv6 header is TCP. + * + * @retval TRUE If the protocol number in IPv6 header is TCP. + * @retval FALSE If the protocol number in IPv6 header is not TCP. + * + */ + bool IsTcp(void) const { return GetIpProto() == kProtoTcp; } + + /** + * This method indicates if the protocol number from IPv6 header is ICMPv6. + * + * @retval TRUE If the protocol number in IPv6 header is ICMPv6. + * @retval FALSE If the protocol number in IPv6 header is not ICMPv6. + * + */ + bool IsIcmp6(void) const { return GetIpProto() == kProtoIcmp6; } + + /** + * This method returns the source IPv6 address from IPv6 header. + * + * @returns The source IPv6 address. + * + */ + const Address &GetSourceAddress(void) const { return mIp6Header.GetSource(); } + + /** + * This method returns the destination IPv6 address from IPv6 header. + * + * @returns The destination IPv6 address. + * + */ + const Address &GetDestinationAddress(void) const { return mIp6Header.GetDestination(); } + + /** + * This method returns the UDP header. + * + * This method MUST be used when `IsUdp() == true`. Otherwise its behavior is undefined + * + * @returns The UDP header. + * + */ + const Udp::Header &GetUdpHeader(void) const { return mHeader.mUdp; } + + /** + * This method returns the TCP header. + * + * This method MUST be used when `IsTcp() == true`. Otherwise its behavior is undefined + * + * @returns The TCP header. + * + */ + const Tcp::Header &GetTcpHeader(void) const { return mHeader.mTcp; } + + /** + * This method returns the ICMPv6 header. + * + * This method MUST be used when `IsIcmp6() == true`. Otherwise its behavior is undefined + * + * @returns The ICMPv6 header. + * + */ + const Icmp::Header &GetIcmpHeader(void) const { return mHeader.mIcmp; } + + /** + * This method returns the source port number if header is UDP or TCP, or zero otherwise + * + * @returns The source port number under UDP / TCP or zero. + * + */ + uint16_t GetSourcePort(void) const; + + /** + * This method returns the destination port number if header is UDP or TCP, or zero otherwise. + * + * @returns The destination port number under UDP / TCP or zero. + * + */ + uint16_t GetDestinationPort(void) const; + + /** + * This method returns the checksum values from corresponding UDP, TCP, or ICMPv6 header. + * + * @returns The checksum value. + * + */ + uint16_t GetChecksum(void) const; + +private: + Header mIp6Header; + union + { + Udp::Header mUdp; + Tcp::Header mTcp; + Icmp::Header mIcmp; + } mHeader; +}; + /** * @} * diff --git a/util/third_party/openthread/src/core/net/ip6_address.cpp b/util/third_party/openthread/src/core/net/ip6_address.cpp index 11dcf9393f..5708146a09 100644 --- a/util/third_party/openthread/src/core/net/ip6_address.cpp +++ b/util/third_party/openthread/src/core/net/ip6_address.cpp @@ -77,13 +77,17 @@ bool Prefix::IsEqual(const uint8_t *aPrefixBytes, uint8_t aPrefixLength) const bool Prefix::operator<(const Prefix &aOther) const { bool isSmaller; + uint8_t minLength; uint8_t matchedLength; - VerifyOrExit(GetLength() == aOther.GetLength(), isSmaller = GetLength() < aOther.GetLength()); + minLength = OT_MIN(GetLength(), aOther.GetLength()); + matchedLength = MatchLength(GetBytes(), aOther.GetBytes(), SizeForLength(minLength)); - matchedLength = MatchLength(GetBytes(), aOther.GetBytes(), GetBytesSize()); - - VerifyOrExit(matchedLength < GetLength(), isSmaller = false); + if (matchedLength >= minLength) + { + isSmaller = (GetLength() < aOther.GetLength()); + ExitNow(); + } isSmaller = GetBytes()[matchedLength / CHAR_BIT] < aOther.GetBytes()[matchedLength / CHAR_BIT]; diff --git a/util/third_party/openthread/src/core/net/ip6_address.hpp b/util/third_party/openthread/src/core/net/ip6_address.hpp index c7bf081c0a..3c55f21901 100644 --- a/util/third_party/openthread/src/core/net/ip6_address.hpp +++ b/util/third_party/openthread/src/core/net/ip6_address.hpp @@ -266,8 +266,10 @@ class Prefix : public otIp6Prefix, public Clearable, public Unequatable< /** * This method overloads operator `<` to compare two prefixes. * - * A prefix with shorter length is considered smaller than the one with longer length. If the prefix lengths are - * equal, then the prefix bytes are compared directly. + * If the two prefixes have the same length N, then the bytes are compared directly (as two big-endian N-bit + * numbers). If the two prefix have different lengths, the shorter prefix is padded by `0` bit up to the longer + * prefix length N before the bytes are compared (as big-endian N-bit numbers). If all bytes are equal, the prefix + * with shorter length is considered smaller. * * @param[in] aOther The other prefix to compare against. * diff --git a/util/third_party/openthread/src/core/net/ip6_filter.cpp b/util/third_party/openthread/src/core/net/ip6_filter.cpp index 86a3e54205..0104fac814 100644 --- a/util/third_party/openthread/src/core/net/ip6_filter.cpp +++ b/util/third_party/openthread/src/core/net/ip6_filter.cpp @@ -50,19 +50,11 @@ namespace Ip6 { RegisterLogModule("Ip6Filter"); -Filter::Filter(Instance &aInstance) - : InstanceLocator(aInstance) -{ - memset(mUnsecurePorts, 0, sizeof(mUnsecurePorts)); -} - bool Filter::Accept(Message &aMessage) const { - bool rval = false; - Header ip6; - Udp::Header udp; - Tcp::Header tcp; - uint16_t dstport; + bool rval = false; + Headers headers; + uint16_t dstPort; // Allow all received IPv6 datagrams with link security enabled if (aMessage.IsLinkSecurityEnabled()) @@ -70,11 +62,11 @@ bool Filter::Accept(Message &aMessage) const ExitNow(rval = true); } - // Read IPv6 header - SuccessOrExit(aMessage.Read(0, ip6)); + SuccessOrExit(headers.ParseFrom(aMessage)); // Allow only link-local unicast or multicast - VerifyOrExit(ip6.GetDestination().IsLinkLocal() || ip6.GetDestination().IsLinkLocalMulticast()); + VerifyOrExit(headers.GetDestinationAddress().IsLinkLocal() || + headers.GetDestinationAddress().IsLinkLocalMulticast()); // Allow all link-local IPv6 datagrams when Thread is not enabled if (Get().GetRole() == Mle::kRoleDisabled) @@ -82,16 +74,13 @@ bool Filter::Accept(Message &aMessage) const ExitNow(rval = true); } - switch (ip6.GetNextHeader()) + dstPort = headers.GetDestinationPort(); + + switch (headers.GetIpProto()) { case kProtoUdp: - // Read the UDP header and get the dst port - SuccessOrExit(aMessage.Read(sizeof(ip6), udp)); - - dstport = udp.GetDestinationPort(); - // Allow MLE traffic - if (dstport == Mle::kUdpPort) + if (dstPort == Mle::kUdpPort) { ExitNow(rval = true); } @@ -99,7 +88,7 @@ bool Filter::Accept(Message &aMessage) const #if OPENTHREAD_CONFIG_BORDER_AGENT_ENABLE // Allow native commissioner traffic if (Get().GetSecurityPolicy().mNativeCommissioningEnabled && - dstport == Get().GetUdpPort()) + dstPort == Get().GetUdpPort()) { ExitNow(rval = true); } @@ -107,11 +96,6 @@ bool Filter::Accept(Message &aMessage) const break; case kProtoTcp: - // Read the TCP header and get the dst port - SuccessOrExit(aMessage.Read(sizeof(ip6), tcp)); - - dstport = tcp.GetDestinationPort(); - break; default: @@ -120,111 +104,37 @@ bool Filter::Accept(Message &aMessage) const } // Check against allowed unsecure port list - for (uint16_t unsecurePort : mUnsecurePorts) - { - if (unsecurePort != 0 && unsecurePort == dstport) - { - ExitNow(rval = true); - } - } + rval = mUnsecurePorts.Contains(dstPort); exit: return rval; } -Error Filter::AddUnsecurePort(uint16_t aPort) +Error Filter::UpdateUnsecurePorts(Action aAction, uint16_t aPort) { - Error error = kErrorNone; + Error error = kErrorNone; + uint16_t *entry; VerifyOrExit(aPort != 0, error = kErrorInvalidArgs); - for (uint16_t unsecurePort : mUnsecurePorts) - { - if (unsecurePort == aPort) - { - ExitNow(); - } - } + entry = mUnsecurePorts.Find(aPort); - for (uint16_t &unsecurePort : mUnsecurePorts) + if (aAction == kAdd) { - if (unsecurePort == 0) - { - unsecurePort = aPort; - LogInfo("Added unsecure port %d", aPort); - ExitNow(); - } + VerifyOrExit(entry == nullptr); + SuccessOrExit(error = mUnsecurePorts.PushBack(aPort)); } - - ExitNow(error = kErrorNoBufs); - -exit: - return error; -} - -Error Filter::RemoveUnsecurePort(uint16_t aPort) -{ - Error error = kErrorNone; - - VerifyOrExit(aPort != 0, error = kErrorInvalidArgs); - - for (int i = 0; i < kMaxUnsecurePorts; i++) + else { - if (mUnsecurePorts[i] == aPort) - { - // Shift all of the ports higher than this - // port down. - for (; i < kMaxUnsecurePorts - 1; i++) - { - mUnsecurePorts[i] = mUnsecurePorts[i + 1]; - } - - // Clear the last port entry. - mUnsecurePorts[i] = 0; - LogInfo("Removed unsecure port %d", aPort); - ExitNow(); - } + VerifyOrExit(entry != nullptr, error = kErrorNotFound); + mUnsecurePorts.Remove(*entry); } - ExitNow(error = kErrorNotFound); + LogInfo("%s unsecure port %d", (aAction == kAdd) ? "Added" : "Removed", aPort); exit: return error; } -bool Filter::IsUnsecurePort(uint16_t aPort) -{ - bool found = false; - - for (uint16_t unsecurePort : mUnsecurePorts) - { - if (unsecurePort == aPort) - { - found = true; - break; - } - } - return found; -} - -void Filter::RemoveAllUnsecurePorts(void) -{ - memset(mUnsecurePorts, 0, sizeof(mUnsecurePorts)); -} - -const uint16_t *Filter::GetUnsecurePorts(uint8_t &aNumEntries) const -{ - // Count the number of unsecure ports. - for (aNumEntries = 0; aNumEntries < kMaxUnsecurePorts; aNumEntries++) - { - if (mUnsecurePorts[aNumEntries] == 0) - { - break; - } - } - - return mUnsecurePorts; -} - } // namespace Ip6 } // namespace ot diff --git a/util/third_party/openthread/src/core/net/ip6_filter.hpp b/util/third_party/openthread/src/core/net/ip6_filter.hpp index 86bdc4cf36..664aa0ed1e 100644 --- a/util/third_party/openthread/src/core/net/ip6_filter.hpp +++ b/util/third_party/openthread/src/core/net/ip6_filter.hpp @@ -36,6 +36,7 @@ #include "openthread-core-config.h" +#include "common/array.hpp" #include "common/locator.hpp" #include "common/message.hpp" #include "common/non_copyable.hpp" @@ -66,7 +67,10 @@ class Filter : public InstanceLocator, private NonCopyable * @param[in] aInstance A reference to the OpenThread instance. * */ - explicit Filter(Instance &aInstance); + explicit Filter(Instance &aInstance) + : InstanceLocator(aInstance) + { + } /** * This method indicates whether or not the IPv6 datagram passes the filter. @@ -89,7 +93,7 @@ class Filter : public InstanceLocator, private NonCopyable * @retval kErrorNoBufs The unsecure port list is full. * */ - Error AddUnsecurePort(uint16_t aPort); + Error AddUnsecurePort(uint16_t aPort) { return UpdateUnsecurePorts(kAdd, aPort); } /** * This method removes a port from the allowed unsecure port list. @@ -101,7 +105,7 @@ class Filter : public InstanceLocator, private NonCopyable * @retval kErrorNotFound The port was not found in the unsecure port list. * */ - Error RemoveUnsecurePort(uint16_t aPort); + Error RemoveUnsecurePort(uint16_t aPort) { return UpdateUnsecurePorts(kRemove, aPort); } /** * This method checks whether a port is in the unsecure port list. @@ -111,13 +115,13 @@ class Filter : public InstanceLocator, private NonCopyable * @returns Whether the given port is in the unsecure port list. * */ - bool IsUnsecurePort(uint16_t aPort); + bool IsUnsecurePort(uint16_t aPort) { return mUnsecurePorts.Contains(aPort); } /** * This method removes all ports from the allowed unsecure port list. * */ - void RemoveAllUnsecurePorts(void); + void RemoveAllUnsecurePorts(void) { mUnsecurePorts.Clear(); } /** * This method returns a pointer to the unsecure port list. @@ -129,12 +133,25 @@ class Filter : public InstanceLocator, private NonCopyable * @returns A pointer to the unsecure port list. * */ - const uint16_t *GetUnsecurePorts(uint8_t &aNumEntries) const; + const uint16_t *GetUnsecurePorts(uint8_t &aNumEntries) const + { + aNumEntries = mUnsecurePorts.GetLength(); + + return &mUnsecurePorts[0]; + } private: static constexpr uint16_t kMaxUnsecurePorts = 2; - uint16_t mUnsecurePorts[kMaxUnsecurePorts]; + enum Action : uint8_t + { + kAdd, + kRemove, + }; + + Error UpdateUnsecurePorts(Action aAction, uint16_t aPort); + + Array mUnsecurePorts; }; } // namespace Ip6 diff --git a/util/third_party/openthread/src/core/net/nd6.cpp b/util/third_party/openthread/src/core/net/nd6.cpp new file mode 100644 index 0000000000..5b57e1be9b --- /dev/null +++ b/util/third_party/openthread/src/core/net/nd6.cpp @@ -0,0 +1,282 @@ +/* + * Copyright (c) 2020, The OpenThread Authors. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file + * This file includes implementations for IPv6 Neighbor Discovery (ND6). + * + */ + +#include "nd6.hpp" + +#include "common/as_core_type.hpp" +#include "common/code_utils.hpp" + +namespace ot { +namespace Ip6 { +namespace Nd { + +//---------------------------------------------------------------------------------------------------------------------- +// Option::Iterator + +Option::Iterator::Iterator(void) + : mOption(nullptr) + , mEnd(nullptr) +{ + // An empty iterator (used to indicate `end()` of list). +} + +Option::Iterator::Iterator(const void *aStart, const void *aEnd) + : mOption(nullptr) + , mEnd(reinterpret_cast(aEnd)) +{ + // Note that `Validate()` uses `mEnd` so can only be called after + // `mEnd` is set. + + mOption = Validate(reinterpret_cast(aStart)); +} + +const Option *Option::Iterator::Next(const Option *aOption) +{ + return reinterpret_cast(reinterpret_cast(aOption) + aOption->GetSize()); +} + +void Option::Iterator::Advance(void) +{ + mOption = (mOption != nullptr) ? Validate(Next(mOption)) : nullptr; +} + +const Option *Option::Iterator::Validate(const Option *aOption) const +{ + // Check if `aOption` is well-formed and fits in the range + // up to `mEnd`. Returns `aOption` if it is valid, `nullptr` + // otherwise. + + return ((aOption != nullptr) && ((aOption + 1) <= mEnd) && aOption->IsValid() && (Next(aOption) <= mEnd)) ? aOption + : nullptr; +} + +//---------------------------------------------------------------------------------------------------------------------- +// PrefixInfoOption + +void PrefixInfoOption::Init(void) +{ + Clear(); + SetType(kTypePrefixInfo); + SetSize(sizeof(PrefixInfoOption)); + + OT_UNUSED_VARIABLE(mReserved2); +} + +void PrefixInfoOption::SetPrefix(const Prefix &aPrefix) +{ + mPrefixLength = aPrefix.mLength; + mPrefix = AsCoreType(&aPrefix.mPrefix); +} + +void PrefixInfoOption::GetPrefix(Prefix &aPrefix) const +{ + aPrefix.Set(mPrefix.GetBytes(), mPrefixLength); +} + +bool PrefixInfoOption::IsValid(void) const +{ + return (GetSize() >= sizeof(*this)) && (mPrefixLength <= Prefix::kMaxLength) && + (GetPreferredLifetime() <= GetValidLifetime()); +} + +//---------------------------------------------------------------------------------------------------------------------- +// RouteInfoOption + +void RouteInfoOption::Init(void) +{ + Clear(); + SetType(kTypeRouteInfo); +} + +void RouteInfoOption::SetPreference(RoutePreference aPreference) +{ + mResvdPrf &= ~kPreferenceMask; + mResvdPrf |= (NetworkData::RoutePreferenceToValue(aPreference) << kPreferenceOffset) & kPreferenceMask; +} + +RoutePreference RouteInfoOption::GetPreference(void) const +{ + return NetworkData::RoutePreferenceFromValue((mResvdPrf & kPreferenceMask) >> kPreferenceOffset); +} + +void RouteInfoOption::SetPrefix(const Prefix &aPrefix) +{ + SetLength(OptionLengthForPrefix(aPrefix.mLength)); + mPrefixLength = aPrefix.mLength; + memcpy(GetPrefixBytes(), aPrefix.GetBytes(), aPrefix.GetBytesSize()); +} + +void RouteInfoOption::GetPrefix(Prefix &aPrefix) const +{ + aPrefix.Set(GetPrefixBytes(), mPrefixLength); +} + +bool RouteInfoOption::IsValid(void) const +{ + return (GetSize() >= kMinSize) && (mPrefixLength <= Prefix::kMaxLength) && + (GetLength() >= OptionLengthForPrefix(mPrefixLength)) && + NetworkData::IsRoutePreferenceValid(GetPreference()); +} + +uint8_t RouteInfoOption::OptionLengthForPrefix(uint8_t aPrefixLength) +{ + static constexpr uint8_t kMaxPrefixLenForOptionLen1 = 0; + static constexpr uint8_t kMaxPrefixLenForOptionLen2 = 64; + + uint8_t length; + + // The Option Length can be 1, 2, or 3 depending on the prefix + // length + // + // - 1 when prefix len is zero. + // - 2 when prefix len is less then or equal to 64. + // - 3 otherwise. + + if (aPrefixLength == kMaxPrefixLenForOptionLen1) + { + length = 1; + } + else if (aPrefixLength <= kMaxPrefixLenForOptionLen2) + { + length = 2; + } + else + { + length = 3; + } + + return length; +} + +//---------------------------------------------------------------------------------------------------------------------- +// RouterAdverMessage::Header + +void RouterAdvertMessage::Header::SetToDefault(void) +{ + OT_UNUSED_VARIABLE(mCode); + OT_UNUSED_VARIABLE(mCurHopLimit); + OT_UNUSED_VARIABLE(mReachableTime); + OT_UNUSED_VARIABLE(mRetransTimer); + + Clear(); + mType = Icmp::Header::kTypeRouterAdvert; +} + +RoutePreference RouterAdvertMessage::Header::GetDefaultRouterPreference(void) const +{ + return NetworkData::RoutePreferenceFromValue((mFlags & kPreferenceMask) >> kPreferenceOffset); +} + +void RouterAdvertMessage::Header::SetDefaultRouterPreference(RoutePreference aPreference) +{ + mFlags &= ~kPreferenceMask; + mFlags |= (NetworkData::RoutePreferenceToValue(aPreference) << kPreferenceOffset) & kPreferenceMask; +} + +//---------------------------------------------------------------------------------------------------------------------- +// RouterAdverMessage + +Option *RouterAdvertMessage::AppendOption(uint16_t aOptionSize) +{ + // This method appends an option with a given size to the RA + // message by reserving space in the data buffer if there is + // room. On success returns pointer to the option, on failure + // returns `nullptr`. The returned option needs to be + // initialized and populated by the caller. + + Option * option = nullptr; + uint32_t newLength = mData.GetLength(); + + newLength += aOptionSize; + VerifyOrExit(newLength <= mMaxLength); + + option = reinterpret_cast